[PATCH v3 0/2] arm: dts: nxp: imx: add Draeger M48 CPU board

[PATCH v3 0/2] arm: dts: nxp: imx: add Draeger M48 CPU board

[Petko Manolov]

Adds the device trees for “Dräger M48 on NXP i.MX6 (Q|DL) and Intel/Altera
SoCFPGA Cyclone V” board variant.  It has both (the SoC and FPGA) on the
same carrier and they are cross-monitoring each other.  The SoCFPGA boots
independently off qspi flash.

This is the imx6 devicetree part.  There are two bindings as well as device
trees, since M48 is using two parts: imx6q and imx6dl.

new in v3:

  - used LLM to cleanup most of the errors and warnings;

  - proper use of dt-schema this time around;

new in v2:

  - add the tag from Conor Dooley <conor.dooley@microchip.com>;

  - it should be clarified that "draeger" vendor prefix is added in
    my previous Draeger M48 patch series;

Petko Manolov (2):
  dt-bindings: arm: fsl: add Draeger M48 dual-cpu board
  arm: dts: nxp: imx: Add devicetree files for M48

 .../devicetree/bindings/arm/fsl.yaml          |   2 +
 arch/arm/boot/dts/nxp/imx/Makefile            |   2 +
 .../boot/dts/nxp/imx/imx6dl-draeger-m48.dts   |  16 ++
 .../boot/dts/nxp/imx/imx6q-draeger-m48.dts    |  16 ++
 .../boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi | 213 ++++++++++++++++++
 5 files changed, 249 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi

-- 
2.47.3

[PATCH v3 1/2] dt-bindings: arm: fsl: add Draeger M48 dual-cpu board

[Petko Manolov]

M48 is a heterogeneous board made by Draeger that is based on two
independent cpus, that are monitoring each other.  One of them is
imx6, the other is Altera SoCFPGA Cyclone 5.  The latter is booting
independently off qspi.

The imx6 parts that are used in M48 are imx6q and imx6dl, hence the
two bindings.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 Documentation/devicetree/bindings/arm/fsl.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 656f2596e1d5..8f3a04228780 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -260,6 +260,7 @@ properties:
               - boundary,imx6q-nitrogen6x
               - compulab,cm-fx6           # CompuLab CM-FX6
               - dmo,imx6q-edmqmx6         # Data Modul eDM-QMX6 Board
+              - draeger,imx6q-m48         # Draeger imx6q variant of M48
               - ds,imx6q-sbc              # Da Sheng COM-9XX Modules
               - embest,imx6q-marsboard    # Embest MarS Board i.MX6Dual
               - emtrion,emcon-mx6         # emCON-MX6D or emCON-MX6Q SoM
@@ -458,6 +459,7 @@ properties:
               - boundary,imx6dl-nit6xlite     # Boundary Devices Nitrogen6 Lite
               - boundary,imx6dl-nitrogen6x    # Boundary Devices Nitrogen6x
               - bticino,imx6dl-mamoj      # BTicino i.MX6DL Mamoj
+              - draeger,imx6dl-m48        # Draeger imx6dl variant of M48
               - eckelmann,imx6dl-ci4x10
               - emtrion,emcon-mx6         # emCON-MX6S or emCON-MX6DL SoM
               - emtrion,emcon-mx6-avari   # emCON-MX6S or emCON-MX6DL SoM on Avari Base
-- 
2.47.3

Re: [PATCH v3 1/2] dt-bindings: arm: fsl: add Draeger M48 dual-cpu board

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] dt-bindings: arm: fsl: undocumented draeger vendor prefix
--

commit 795e5eabed6a73f1faa10f56606455efcbd039b8
Author: Petko Manolov <petko.manolov@konsulko.com>

dt-bindings: arm: fsl: add Draeger M48 dual-cpu board

This commit adds devicetree binding compatible strings for the imx6q and
imx6dl variants of the Draeger M48 board to
Documentation/devicetree/bindings/arm/fsl.yaml.

> diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> index 656f2596e1d53..8f3a04228780a 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> @@ -260,6 +260,7 @@ properties:
>                - boundary,imx6q-nitrogen6x
>                - compulab,cm-fx6           # CompuLab CM-FX6
>                - dmo,imx6q-edmqmx6         # Data Modul eDM-QMX6 Board
> +              - draeger,imx6q-m48         # Draeger imx6q variant of M48
>                - ds,imx6q-sbc              # Da Sheng COM-9XX Modules
>                - embest,imx6q-marsboard    # Embest MarS Board i.MX6Dual
>                - emtrion,emcon-mx6         # emCON-MX6D or emCON-MX6Q SoM
> @@ -458,6 +459,7 @@ properties:
>                - boundary,imx6dl-nit6xlite     # Boundary Devices Nitrogen6 Lite
>                - boundary,imx6dl-nitrogen6x    # Boundary Devices Nitrogen6x
>                - bticino,imx6dl-mamoj      # BTicino i.MX6DL Mamoj
> +              - draeger,imx6dl-m48        # Draeger imx6dl variant of M48
>                - eckelmann,imx6dl-ci4x10
>                - emtrion,emcon-mx6         # emCON-MX6S or emCON-MX6DL SoM
>                - emtrion,emcon-mx6-avari   # emCON-MX6S or emCON-MX6DL SoM on Avari Base

[Severity: Low]
Should the draeger vendor prefix also be documented under patternProperties
in Documentation/devicetree/bindings/vendor-prefixes.yaml?

Currently, Documentation/devicetree/bindings/vendor-prefixes.yaml has no
entry for draeger between dptel and dragino:

  "^dptel,.*":
    description: Guangdong Dapu Telecom Co., Ltd.
  "^dragino,.*":
    description: Dragino Technology Co., Limited

Without an entry in vendor-prefixes.yaml, process() in scripts/checkpatch.pl
reports an undocumented vendor prefix warning when device tree files (such
as arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts and
arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts) or driver match tables
reference draeger,imx6q-m48 or draeger,imx6dl-m48, and any draeger,*
vendor-specific properties will fail schema validation.

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261021092140.4142493-1-petko.manolov@konsulko.com?part=1

Re: [PATCH v3 1/2] dt-bindings: arm: fsl: add Draeger M48 dual-cpu board

[Frank Li]

On Wed, Oct 21, 2026 at 09:32:12AM +0000, sashiko-bot@kernel.org wrote:
> Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
> - [Low] dt-bindings: arm: fsl: undocumented draeger vendor prefix
> --
>
> commit 795e5eabed6a73f1faa10f56606455efcbd039b8
> Author: Petko Manolov <petko.manolov@konsulko.com>
>
> dt-bindings: arm: fsl: add Draeger M48 dual-cpu board
>
> This commit adds devicetree binding compatible strings for the imx6q and
> imx6dl variants of the Draeger M48 board to
> Documentation/devicetree/bindings/arm/fsl.yaml.
>
> > diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
> > index 656f2596e1d53..8f3a04228780a 100644
> > --- a/Documentation/devicetree/bindings/arm/fsl.yaml
> > +++ b/Documentation/devicetree/bindings/arm/fsl.yaml
> > @@ -260,6 +260,7 @@ properties:
> >                - boundary,imx6q-nitrogen6x
> >                - compulab,cm-fx6           # CompuLab CM-FX6
> >                - dmo,imx6q-edmqmx6         # Data Modul eDM-QMX6 Board
> > +              - draeger,imx6q-m48         # Draeger imx6q variant of M48
> >                - ds,imx6q-sbc              # Da Sheng COM-9XX Modules
> >                - embest,imx6q-marsboard    # Embest MarS Board i.MX6Dual
> >                - emtrion,emcon-mx6         # emCON-MX6D or emCON-MX6Q SoM
> > @@ -458,6 +459,7 @@ properties:
> >                - boundary,imx6dl-nit6xlite     # Boundary Devices Nitrogen6 Lite
> >                - boundary,imx6dl-nitrogen6x    # Boundary Devices Nitrogen6x
> >                - bticino,imx6dl-mamoj      # BTicino i.MX6DL Mamoj
> > +              - draeger,imx6dl-m48        # Draeger imx6dl variant of M48
> >                - eckelmann,imx6dl-ci4x10
> >                - emtrion,emcon-mx6         # emCON-MX6S or emCON-MX6DL SoM
> >                - emtrion,emcon-mx6-avari   # emCON-MX6S or emCON-MX6DL SoM on Avari Base
>
> [Severity: Low]
> Should the draeger vendor prefix also be documented under patternProperties
> in Documentation/devicetree/bindings/vendor-prefixes.yaml?

This need be fixed

Frank
>
> Currently, Documentation/devicetree/bindings/vendor-prefixes.yaml has no
> entry for draeger between dptel and dragino:
>
>   "^dptel,.*":
>     description: Guangdong Dapu Telecom Co., Ltd.
>   "^dragino,.*":
>     description: Dragino Technology Co., Limited
>
> Without an entry in vendor-prefixes.yaml, process() in scripts/checkpatch.pl
> reports an undocumented vendor prefix warning when device tree files (such
> as arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts and
> arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts) or driver match tables
> reference draeger,imx6q-m48 or draeger,imx6dl-m48, and any draeger,*
> vendor-specific properties will fail schema validation.
>
> --
> Sashiko AI review · https://sashiko.dev/#/patchset/20261021092140.4142493-1-petko.manolov@konsulko.com?part=1

[PATCH v3 2/2] arm: dts: nxp: imx: Add devicetree files for M48

[Petko Manolov]

M48 is a heterogeneous board made by Draeger that is based on two
independent cpus, that are monitoring each other.  One of them is
imx6, the other is Altera SoCFPGA Cyclone 5.  The latter is booting
independently off qspi.

Add the DT for the two variants of M48 that are based on imx6q and
imx6dl.

Signed-off-by: Petko Manolov <petko.manolov@konsulko.com>
---
 arch/arm/boot/dts/nxp/imx/Makefile            |   2 +
 .../boot/dts/nxp/imx/imx6dl-draeger-m48.dts   |  16 ++
 .../boot/dts/nxp/imx/imx6q-draeger-m48.dts    |  16 ++
 .../boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi | 213 ++++++++++++++++++
 4 files changed, 247 insertions(+)
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
 create mode 100644 arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi

diff --git a/arch/arm/boot/dts/nxp/imx/Makefile b/arch/arm/boot/dts/nxp/imx/Makefile
index 1a2539fa19b4..cdd252fd5109 100644
--- a/arch/arm/boot/dts/nxp/imx/Makefile
+++ b/arch/arm/boot/dts/nxp/imx/Makefile
@@ -104,6 +104,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6dl-dfi-fs700-m60.dtb \
 	imx6dl-dhcom-pdk2.dtb \
 	imx6dl-dhcom-picoitx.dtb \
+	imx6dl-draeger-m48.dtb \
 	imx6dl-eckelmann-ci4x10.dtb \
 	imx6dl-emcon-avari.dtb \
 	imx6dl-gw51xx.dtb \
@@ -219,6 +220,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
 	imx6q-display5-tianma-tm070-1280x768.dtb \
 	imx6q-dmo-edmqmx6.dtb \
 	imx6q-dms-ba16.dtb \
+	imx6q-draeger-m48.dtb \
 	imx6q-ds.dtb \
 	imx6q-emcon-avari.dtb \
 	imx6q-evi.dtb \
diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
new file mode 100644
index 000000000000..b0bc9a67f5b3
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ *
+ * Device Tree file for Draeger M48 Board
+ */
+
+/dts-v1/;
+
+#include "imx6dl.dtsi"
+#include "imx6qdl-draeger-m48.dtsi"
+
+/ {
+	model = "Draeger M48 i.MX6 DualLite";
+	compatible = "draeger,imx6dl-m48", "fsl,imx6dl";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts b/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
new file mode 100644
index 000000000000..ff9c337e93fb
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ *
+ * Device Tree file for Draeger M48 Board
+ */
+
+/dts-v1/;
+
+#include "imx6q.dtsi"
+#include "imx6qdl-draeger-m48.dtsi"
+
+/ {
+	model = "Draeger M48 i.MX6 Quad";
+	compatible = "draeger,imx6q-m48", "fsl,imx6q";
+};
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi
new file mode 100644
index 000000000000..19207d45764c
--- /dev/null
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2020 Draeger and Licensors, info@draeger.com
+ * Based on work by Russell King
+ *
+ * Device Tree file for Draeger M48 Board
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	aliases {
+		mmc0 = &usdhc3;
+	};
+
+	chosen {
+		stdout-path = &uart1;
+	};
+
+	/* Will be filled by the bootloader */
+	memory@10000000 {
+		device_type = "memory";
+		reg = <0x10000000 0x80000000>;
+	};
+};
+
+&fec {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_enet>;
+	phy-mode = "rgmii-id";
+	phy-handle = <&ethphy>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy: ethernet-phy@0 {
+			reg = <0>;
+			rxc-skew-ps = <1380>;
+			rxd0-skew-ps = <0>;
+			rxd1-skew-ps = <0>;
+			rxd2-skew-ps = <0>;
+			rxd3-skew-ps = <0>;
+			rxdv-skew-ps = <0>;
+			txc-skew-ps = <1860>;
+			txd0-skew-ps = <0>;
+			txd1-skew-ps = <0>;
+			txd2-skew-ps = <0>;
+			txd3-skew-ps = <0>;
+			txen-skew-ps = <0>;
+		};
+	};
+};
+
+&hdmi {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hdmi>;
+	status = "okay";
+};
+
+&i2c2 {
+	clock-frequency = <100000>;
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c2>;
+	pinctrl-1 = <&pinctrl_i2c2_gpio>;
+	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+
+	eeprom_mac: eeprom@50 {
+		compatible = "atmel,24c08";
+		reg = <0x50>;
+		pagesize = <16>;
+	};
+};
+
+&i2c3 {
+	pinctrl-names = "default", "gpio";
+	pinctrl-0 = <&pinctrl_i2c3>;
+	pinctrl-1 = <&pinctrl_i2c3_gpio>;
+	scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
+	status = "okay";
+};
+
+&ldb {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lvds>;
+	fsl,dual-channel;
+	status = "okay";
+
+	lvds-channel@0 {
+		fsl,data-mapping = "spwg";
+		fsl,data-width = <24>;
+		status = "okay";
+
+		display-timings {
+			native-mode = <&timing0>;
+
+			/* LVDS split mode */
+			timing0: timing-1920x1080 {
+				clock-frequency = <71190000>;	/* pixclk / 2 */
+				hactive = <1920>;
+				vactive = <1080>;
+				hback-porch = <60>;		/* left * 2 */
+				hfront-porch = <60>;		/* right * 2 */
+				vback-porch = <30>;
+				vfront-porch = <3>;
+				hsync-len = <60>;		/* hsync * 2 */
+				vsync-len = <17>;
+			};
+		};
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart1>;
+	status = "okay";
+};
+
+&usdhc3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usdhc3>;
+	bus-width = <4>;
+	non-removable;
+	status = "okay";
+};
+
+&iomuxc {
+	pinctrl_enet: enetgrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL1__ENET_MDIO		0x1b0b0
+			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
+			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x13018
+			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b018
+			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b018
+			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b018
+			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b018
+			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x13018
+			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
+			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x13030
+			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
+			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
+			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
+			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
+			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x13030
+		>;
+	};
+
+	pinctrl_hdmi: hdmigrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA	0x1b0b0
+			MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL	0x1b0b0
+		>;
+	};
+
+	pinctrl_i2c2: i2c2grp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b820
+			MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b820
+		>;
+	};
+
+	pinctrl_i2c2_gpio: i2c2gpiogrp {
+		fsl,pins = <
+			MX6QDL_PAD_KEY_COL3__GPIO4_IO12		0x1b820
+			MX6QDL_PAD_KEY_ROW3__GPIO4_IO13		0x1b820
+		>;
+	};
+
+	pinctrl_i2c3: i2c3grp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b820
+			MX6QDL_PAD_EIM_D18__I2C3_SDA		0x4001b820
+		>;
+	};
+
+	pinctrl_i2c3_gpio: i2c3gpiogrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_D17__GPIO3_IO17		0x1b820
+			MX6QDL_PAD_EIM_D18__GPIO3_IO18		0x1b820
+		>;
+	};
+
+	pinctrl_lvds: lvdsgrp {
+		fsl,pins = <
+			MX6QDL_PAD_EIM_A22__GPIO2_IO16		0x1b010	/* DISPLAY_EN */
+			MX6QDL_PAD_EIM_A20__GPIO2_IO18		0x1b010	/* BACKLIGHT_EN */
+			MX6QDL_PAD_EIM_A18__GPIO2_IO20		0x1b010	/* DISP0_CONTRAST */
+		>;
+	};
+
+	pinctrl_uart1: uart1grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b010
+			MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b010
+		>;
+	};
+
+	pinctrl_usdhc3: usdhc3grp {
+		fsl,pins = <
+			MX6QDL_PAD_SD3_CMD__SD3_CMD		0x1b060
+			MX6QDL_PAD_SD3_CLK__SD3_CLK		0x1b060
+			MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x1b060
+			MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x1b060
+			MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x1b060
+			MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x1b060
+			MX6QDL_PAD_NANDF_CS1__SD3_VSELECT	0x1b060
+		>;
+	};
+};
-- 
2.47.3

Re: [PATCH v3 2/2] arm: dts: nxp: imx: Add devicetree files for M48

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:
- [Medium] ARM: dts: imx6qdl-draeger-m48: missing GPIO_OPEN_DRAIN on I2C recovery GPIOs
- [Medium] ARM: dts: imx6qdl-draeger-m48: halved LVDS pixel clock in split mode
- [Medium] ARM: dts: imx6: missing ODE and SION bits on HDMI DDC pins in draeger-m48
- [Low] ARM: dts: imx6qdl-draeger-m48: undocumented draeger vendor prefix
--

commit 1f358a609d69dc3047258ea0965effc8740f95c7
Author: Petko Manolov <petko.manolov@konsulko.com>

arm: dts: nxp: imx: Add devicetree files for M48

This commit adds devicetree files for the i.MX6 DualLite and i.MX6 Quad
variants of the Draeger M48 board.

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts b/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
> new file mode 100644
> index 0000000000000..b0bc9a67f5b34
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts
> @@ -0,0 +1,16 @@
[ ... ]
> +/ {
> +	model = "Draeger M48 i.MX6 DualLite";
> +	compatible = "draeger,imx6dl-m48", "fsl,imx6dl";
> +};
> diff --git a/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts b/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
> new file mode 100644
> index 0000000000000..ff9c337e93fbf
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts
> @@ -0,0 +1,16 @@
[ ... ]
> +/ {
> +	model = "Draeger M48 i.MX6 Quad";
> +	compatible = "draeger,imx6q-m48", "fsl,imx6q";
> +};

[Severity: Low]
The root compatible properties in
arch/arm/boot/dts/nxp/imx/imx6dl-draeger-m48.dts and
arch/arm/boot/dts/nxp/imx/imx6q-draeger-m48.dts introduce the "draeger"
vendor prefix, but Documentation/devicetree/bindings/vendor-prefixes.yaml
only contains entries for "^dptel,.*" and "^dragino,.*" in patternProperties:

  "^dptel,.*":
    description: Guangdong Dapu Telecom Co., Ltd.
  "^dragino,.*":
    description: Dragino Technology Co., Limited

Should the "draeger" vendor prefix be documented in
Documentation/devicetree/bindings/vendor-prefixes.yaml so that checkpatch.pl
and schema validation do not warn about an undocumented compatible string
vendor?

> diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi
> new file mode 100644
> index 0000000000000..19207d45764c0
> --- /dev/null
> +++ b/arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi
> @@ -0,0 +1,213 @@
[ ... ]
> +&hdmi {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_hdmi>;
> +	status = "okay";
> +};
> +
> +&i2c2 {
> +	clock-frequency = <100000>;
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c2>;
> +	pinctrl-1 = <&pinctrl_i2c2_gpio>;
> +	scl-gpios = <&gpio4 12 GPIO_ACTIVE_HIGH>;
> +	sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +
> +	eeprom_mac: eeprom@50 {
> +		compatible = "atmel,24c08";
> +		reg = <0x50>;
> +		pagesize = <16>;
> +	};
> +};
> +
> +&i2c3 {
> +	pinctrl-names = "default", "gpio";
> +	pinctrl-0 = <&pinctrl_i2c3>;
> +	pinctrl-1 = <&pinctrl_i2c3_gpio>;
> +	scl-gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>;
> +	sda-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
> +	status = "okay";
> +};

[Severity: Medium]
During adapter registration for &i2c2 and &i2c3,
i2c_init_recovery() -> i2c_gpio_init_generic_recovery() in
drivers/i2c/i2c-core-base.c requests scl-gpios with
GPIOD_OUT_HIGH_OPEN_DRAIN and sda-gpios with GPIOD_IN.

When GPIO_OPEN_DRAIN is not set on scl-gpios in the devicetree,
gpiod_configure_flags() in drivers/gpio/gpiolib.c logs a runtime warning:

	if (lflags & GPIO_OPEN_DRAIN)
		set_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags);
	else if (dflags & GPIOD_FLAGS_BIT_OPEN_DRAIN) {
		set_bit(GPIOD_FLAG_OPEN_DRAIN, &desc->flags);
		gpiod_warn(desc,
			   "enforced open drain please flag it properly in DT/ACPI DSDT/board file\n");
	}

In addition, because sda-gpios is requested with GPIOD_IN,
i2c_init_recovery() in drivers/i2c/i2c-core-base.c checks whether the line is
single-ended before enabling sda driving for bus recovery:

		if (bri->sda_gpiod) {
			bri->get_sda = get_sda_gpio_value;
			if (gpiod_get_direction(bri->sda_gpiod) == GPIO_LINE_DIRECTION_OUT ||
			    gpiod_is_single_ended(bri->sda_gpiod))
				bri->set_sda = set_sda_gpio_value;
		}

Without GPIO_OPEN_DRAIN on sda-gpios, gpiod_is_single_ended(bri->sda_gpiod)
returns false and bri->set_sda remains NULL, preventing recovery from driving
sda to generate a stop condition. Also, pinctrl_i2c2_gpio and
pinctrl_i2c3_gpio below use pad config 0x1b820 without the sion bit
(0x40000000), unlike pinctrl_i2c2 and pinctrl_i2c3 (0x4001b820).

Should scl-gpios and sda-gpios in &i2c2 and &i2c3 be flagged with
(GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), and should pinctrl_i2c2_gpio and
pinctrl_i2c3_gpio also set 0x4001b820?

> +
> +&ldb {
> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pinctrl_lvds>;
> +	fsl,dual-channel;
> +	status = "okay";
> +
> +	lvds-channel@0 {
> +		fsl,data-mapping = "spwg";
> +		fsl,data-width = <24>;
> +		status = "okay";
> +
> +		display-timings {
> +			native-mode = <&timing0>;
> +
> +			/* LVDS split mode */
> +			timing0: timing-1920x1080 {
> +				clock-frequency = <71190000>;	/* pixclk / 2 */
> +				hactive = <1920>;
> +				vactive = <1080>;
> +				hback-porch = <60>;		/* left * 2 */
> +				hfront-porch = <60>;		/* right * 2 */
> +				vback-porch = <30>;
> +				vfront-porch = <3>;
> +				hsync-len = <60>;		/* hsync * 2 */
> +				vsync-len = <17>;
> +			};

[Severity: Medium]
In timing0 under &ldb, the horizontal parameters specify the full two-channel
line totals (1920 + 60 + 60 + 60 = 2100 pixels per line, 1130 lines per
frame), which require a 142.38 MHz pixel clock for 60 Hz, while
clock-frequency is pre-divided by 2 to 71190000.

When fsl,dual-channel is enabled, imx_ldb_encoder_atomic_mode_set() in
drivers/gpu/drm/imx/ipuv3/imx-ldb.c treats mode->clock as the full combined
display interface pixel clock (di_clk = mode->clock * 1000) and already
halves the per-channel serial clock multiplier:

	if (dual) {
		serial_clk = 3500UL * mode->clock;
		imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
		imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
	} else {
		serial_clk = 7000UL * mode->clock;
		imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
				  di_clk);
	}

Meanwhile, ipu_di_sync_config_noninterlaced() in
drivers/gpu/ipu-v3/ipu-di.c clocks all 2100 horizontal pixels per line at
di_clk.

Will pre-dividing clock-frequency to 71190000 here cause the display
interface and lvds channels to run at half the intended clock rate (30 Hz
instead of 60 Hz), and should clock-frequency be <142380000> instead?

> +		};
> +	};
> +};
[ ... ]
> +&iomuxc {
[ ... ]
> +	pinctrl_hdmi: hdmigrp {
> +		fsl,pins = <
> +			MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA	0x1b0b0
> +			MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL	0x1b0b0
> +		>;
> +	};

[Severity: Medium]
The &hdmi node in arch/arm/boot/dts/nxp/imx/imx6qdl-draeger-m48.dtsi does not
specify an external ddc-i2c-bus phandle, so dw_hdmi_probe() in
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c uses the internal DesignWare ddc
i2c master on the pads configured by pinctrl_hdmi.

Here MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA and
MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL are configured with 0x1b0b0, which omits
both open drain enable (0x800) and software input on (0x40000000). Other
i.MX6 boards using the internal hdmi ddc controller (such as
imx6qdl-apalis.dtsi and imx6qdl-colibri.dtsi in pinctrl_hdmi_ddc) configure
these pads with 0x4001b8b1.

Without open drain and software input on enabled on these pads, can hdmi edid
reads over the internal ddc i2c bus fail?

[ ... ]

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20261021092140.4142493-1-petko.manolov@konsulko.com?part=2