Re: [PATCH 2/3] dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit

[Frank Li <Frank.li@oss.nxp.com>]

On Wed, Nov 04, 2026 at 11:09:31AM +0000, Sheetal wrote:
>
> Tegra264 uses the same ADMA FIFO size for every ADMAIF request. The
> driver currently obtains this by setting sreq_index_offset to zero,
> which makes every valid request select a FIFO size of 2.
>
> Add a SoC data field for the uniform FIFO size and set it to 2 for
> Tegra264. Retain the request-index-based FIFO selection for earlier
> SoCs. This preserves existing FIFO programming and allows devices
> with a different uniform FIFO size to specify it in their SoC data.
>
> Signed-off-by: Sheetal <sheetal@nvidia.com>
> ---
...
>
>         ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
>
> @@ -1018,7 +1030,7 @@ static const struct tegra_adma_chip_data tegra264_chip_data = {
>         .ch_reg_size            = 0x100,
>         .nr_channels            = 64,
>         .ch_fifo_size_mask      = 0x7f,
> -       .sreq_index_offset      = 0,

Don't mix this change into this patch? if you want to remove reduntant
init 0, use seperate patch for it.

Frank

> +       .ch_fifo_size           = 2,
>         .max_page               = 10,
>         .set_global_pg_config   = tegra264_adma_global_page_config,
>  };
> --
> 2.43.0
>