From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney@redhat.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Taniya Das <taniya.das@oss.qualcomm.com>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
krishna.chundru@oss.qualcomm.com
Subject: Re: [PATCH v4 2/7] clk: qcom: Add generic clkref_en support
Date: Tue, 9 Jun 2026 14:57:52 +0200 [thread overview]
Message-ID: <b0479824-0c6d-498d-bdc8-63f678a6f2ee@oss.qualcomm.com> (raw)
In-Reply-To: <20260527-tcsr_qref_0527-v4-2-ded83866c9d9@oss.qualcomm.com>
On 5/28/26 4:29 AM, Qiang Yu wrote:
> Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
> a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
> register controls whether refclk is gated through to the PHY side.
>
> These clkref controls are different from typical GCC branch clocks:
> - only a single enable bit is present, without branch-style config bits
> - regulators must be voted before enable and unvoted after disable
>
> Model this as a dedicated clk_ref clock type with custom clk_ops instead
> of reusing struct clk_branch semantics.
>
> Also provide a common registration/probe API so the same clkref model
> can be reused regardless of where clkref_en registers are placed, e.g.
> TCSR on glymur and TLMM on SM8750.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---
[...]
> +static int qcom_clk_ref_enable(struct clk_hw *hw)
> +{
> + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
> + int ret;
> +
> + ret = regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK,
> + QCOM_CLK_REF_EN_MASK);
regmap_set_bits()
> + if (ret)
> + return ret;
> +
> + udelay(10);
> +
> + return 0;
> +}
> +
> +static void qcom_clk_ref_disable(struct clk_hw *hw)
> +{
> + struct qcom_clk_ref *rclk = to_qcom_clk_ref(hw);
> +
> + regmap_update_bits(rclk->regmap, rclk->desc.offset, QCOM_CLK_REF_EN_MASK, 0);
regmap_clear_bits()
[...]
> +static int qcom_clk_ref_register(struct device *dev, struct regmap *regmap,
> + struct qcom_clk_ref *clk_refs,
> + const struct qcom_clk_ref_desc *descs,
> + size_t num_clk_refs)
> +{
> + const struct qcom_clk_ref_desc *desc;
> + struct qcom_clk_ref *clk_ref;
> + size_t clk_idx;
> + unsigned int i;
> + int ret;
> +
> + for (clk_idx = 0; clk_idx < num_clk_refs; clk_idx++) {
> + clk_ref = &clk_refs[clk_idx];
> + desc = &descs[clk_idx];
> +
> + if (!desc->name)
> + continue;
// this allows "holes" in dt-bindings for $reasons
if (!desc)
continue;
// this makes sure the programmer did not omit something important
// while not taking the entire system down
if (WARN_ON(!desc->name)
continue;
Konrad
next prev parent reply other threads:[~2026-06-09 12:57 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-28 2:29 [PATCH v4 0/7] clk: qcom: Add common clkref support and migrate Glymur and Mahua Qiang Yu
2026-05-28 2:29 ` [PATCH v4 1/7] dt-bindings: clock: qcom,sm8550-tcsr: Add QREF/REFGEN supply properties for glymur and mahua Qiang Yu
2026-05-28 7:57 ` Krzysztof Kozlowski
2026-05-28 12:28 ` Qiang Yu
2026-05-28 12:34 ` Krzysztof Kozlowski
2026-05-29 7:05 ` Qiang Yu
2026-05-28 2:29 ` [PATCH v4 2/7] clk: qcom: Add generic clkref_en support Qiang Yu
2026-05-28 3:03 ` Jie Gan
2026-05-28 13:06 ` Qiang Yu
2026-05-28 13:46 ` Jie Gan
2026-05-28 15:01 ` Dmitry Baryshkov
2026-05-29 6:43 ` Qiang Yu
2026-05-29 6:45 ` Qiang Yu
2026-05-28 3:05 ` sashiko-bot
2026-06-01 9:02 ` Qiang Yu
2026-06-09 12:38 ` Konrad Dybcio
2026-06-15 8:34 ` Qiang Yu
2026-06-09 12:57 ` Konrad Dybcio [this message]
2026-06-15 8:40 ` Qiang Yu
2026-05-28 2:29 ` [PATCH v4 3/7] clk: qcom: tcsrcc-glymur: Migrate tcsr_pcie_N_clkref_en to clk_ref common helper Qiang Yu
2026-05-28 3:40 ` sashiko-bot
2026-06-09 13:02 ` Konrad Dybcio
2026-06-15 8:46 ` Qiang Yu
2026-05-28 2:29 ` [PATCH v4 4/7] clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support Qiang Yu
2026-05-28 2:29 ` [PATCH v4 5/7] arm64: dts: qcom: glymur: Add QREF regulator supplies to TCSR Qiang Yu
2026-05-28 4:06 ` sashiko-bot
2026-05-28 2:29 ` [PATCH v4 6/7] arm64: dts: qcom: mahua: " Qiang Yu
2026-05-28 2:29 ` [PATCH v4 7/7] arm64: dts: qcom: mahua: Switch pcie5_phy ref clock to RPMH_CXO_CLK Qiang Yu
2026-06-09 13:06 ` Konrad Dybcio
2026-06-09 13:55 ` Krzysztof Kozlowski
2026-06-09 14:07 ` Konrad Dybcio
2026-06-15 8:51 ` Qiang Yu
2026-06-17 12:11 ` Konrad Dybcio
2026-06-18 2:34 ` Qiang Yu
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