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From: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Rob Clark <robin.clark@oss.qualcomm.com>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Sean Paul <sean@poorly.run>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Krishna Manikandan <quic_mkrishn@quicinc.com>,
	Abel Vesa <abelvesa@kernel.org>,
	Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>,
	linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 2/3] drm/msm/mdss: Enable INT2_GDSC alongside CORE_GDSC
Date: Thu, 13 Aug 2026 15:45:13 +0800	[thread overview]
Message-ID: <b360c4a0-72ec-4121-b16d-b7aa94e1a1f1@oss.qualcomm.com> (raw)
In-Reply-To: <nwz6ail4qwkmsejow6757nxkutojc2q76tw7lt6oj3h4pncp5f@w6xkgj3bnlmh>



On 7/22/2026 2:40 AM, Dmitry Baryshkov wrote:
> On Mon, Jul 20, 2026 at 04:43:54PM +0800, Yongxing Mou wrote:
>> Kaanapali (SM8750) and Glymur use two display power domains.
>> CORE_GDSC powers the main display hardware while INT2_GDSC powers
>> a subset of SSPP blocks (VIG2/VIG3/DMA5/DMA6).
>>
>> The MDSS driver currently relies on the default runtime PM handling
>> and does not enable the secondary INT2_GDSC. As a result, display
>> pipes backed by INT2_GDSC remain inaccessible.
>>
>> Attach and manage both power domains explicitly and enable them
>> during MDSS runtime PM activation.
>>
>> Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
>> ---
>>   drivers/gpu/drm/msm/msm_mdss.c | 53 +++++++++++++++++++++++++++++++++++++++++-
>>   1 file changed, 52 insertions(+), 1 deletion(-)
> 
> Why is it being handled in the MDSS rather than DPU?
> 
Will move it next patchset.
>> @@ -421,6 +451,27 @@ static struct msm_mdss *msm_mdss_init(struct platform_device *pdev, bool is_mdp5
>>   	irq_set_chained_handler_and_data(irq, msm_mdss_irq,
>>   					 msm_mdss);
>>   
>> +	/*
>> +	 * When two power domains are listed in DT, the core framework does not
>> +	 * auto-attach either of them.  Attach and manage both explicitly so
>> +	 * that INT2_GDSC (needed for VIG2/VIG3) is enabled alongside the main
>> +	 * CORE_GDSC.  Single-domain platforms are unaffected.
>> +	 */
>> +	if (of_count_phandle_with_args(pdev->dev.of_node, "power-domains",
>> +				       "#power-domain-cells") > 1) {
>> +		static const char * const mdss_pd_names[] = { "core", "int2" };
>> +		static const struct dev_pm_domain_attach_data pd_data = {
>> +			.pd_names = mdss_pd_names,
>> +			.num_pd_names = ARRAY_SIZE(mdss_pd_names),
>> +			.pd_flags = PD_FLAG_NO_DEV_LINK,
> 
> Can't you use DL_FLAG_PM_RUNTIME here?
> 
Got it.Will ust it next patch.
>> +		};
>> +
>> +		ret = devm_pm_domain_attach_list(&pdev->dev, &pd_data,
>> +						 &msm_mdss->pd_list);
>> +		if (ret < 0)
>> +			return ERR_PTR(ret);
>> +	}
>> +
>>   	pm_runtime_enable(&pdev->dev);
>>   
>>   	return msm_mdss;
>>
>> -- 
>> 2.43.0
>>
> 


  reply	other threads:[~2026-08-13  7:45 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-20  8:43 [PATCH 0/3] drm/msm: Enable dual MDSS power domains Yongxing Mou
2026-07-20  8:43 ` [PATCH 1/3] dt-bindings: display: msm: Allow two " Yongxing Mou
2026-07-20  8:49   ` Konrad Dybcio
2026-08-13  7:44     ` Yongxing Mou
2026-08-17 14:12       ` Konrad Dybcio
2026-08-18  3:32         ` Dmitry Baryshkov
2026-08-17 14:13       ` Konrad Dybcio
2026-08-17 14:14         ` Konrad Dybcio
2026-08-19  3:27           ` Yongxing Mou
2026-08-25  6:28           ` Yongxing Mou
2026-08-25  8:30             ` Konrad Dybcio
2026-08-26  2:53               ` Yongxing Mou
2026-08-26 13:19                 ` Konrad Dybcio
2026-08-19  3:23         ` Yongxing Mou
2026-08-18  3:31       ` Dmitry Baryshkov
2026-08-19  5:50         ` Yongxing Mou
2026-07-20  8:54   ` sashiko-bot
2026-07-21 18:18   ` Dmitry Baryshkov
2026-08-13  7:45     ` Yongxing Mou
2026-07-21 18:20   ` Dmitry Baryshkov
2026-08-13  8:06     ` Yongxing Mou
2026-07-24  9:36   ` Krzysztof Kozlowski
2026-08-13  7:45     ` Yongxing Mou
2026-08-18  3:29       ` Dmitry Baryshkov
2026-07-20  8:43 ` [PATCH 2/3] drm/msm/mdss: Enable INT2_GDSC alongside CORE_GDSC Yongxing Mou
2026-07-20  8:58   ` sashiko-bot
2026-07-21 18:40   ` Dmitry Baryshkov
2026-08-13  7:45     ` Yongxing Mou [this message]
2026-07-20  8:43 ` [PATCH 3/3] arm64: dts: qcom: Add INT2_GDSC to MDSS on Kaanapali and Glymur Yongxing Mou
2026-07-20  9:05   ` sashiko-bot

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