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From: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
To: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Rob Clark <robin.clark@oss.qualcomm.com>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Sean Paul <sean@poorly.run>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
	Maxime Ripard <mripard@kernel.org>,
	Thomas Zimmermann <tzimmermann@suse.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Krishna Manikandan <quic_mkrishn@quicinc.com>,
	Abel Vesa <abelvesa@kernel.org>,
	Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
	freedreno@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 1/3] dt-bindings: display: msm: Allow two MDSS power domains
Date: Thu, 13 Aug 2026 15:44:53 +0800	[thread overview]
Message-ID: <ccab8aae-d980-423a-b39e-3ce2a7c82542@oss.qualcomm.com> (raw)
In-Reply-To: <b36691d3-e996-4fc0-8955-25beeeecc385@oss.qualcomm.com>



On 7/20/2026 4:49 PM, Konrad Dybcio wrote:
> On 7/20/26 10:43 AM, Yongxing Mou wrote:
>> Kaanapali (SM8750) and Glymur use two display power domains.
>> CORE_GDSC powers the main display hardware while INT2_GDSC
>> powers a subset of SSPP blocks.
> 
> Can they operate independently? Does INT2_GDSC need to be
> powered on after CORE_GDSC?
> 
On Kaanapali, my understanding is that CORE_GDSC and INT2_GDSC should 
generally track the same state, except that INT2_GDSC may be powered 
down when SSPP1 (VIG2/VIG3/DMA5) is unused.
    - CORE off, INT2 off
     - CORE on,  INT2 off
     - CORE on,  INT2 on
> If so, perhaps changing the clock driver to make CORE a parent
> of INT2 could be the simpler solution
> 
> Konrad
That would still need DT and binding changes -- DPU has to reference 
INT2_GDSC directly to gate it independently, so it can't be hidden in 
the clock driver. The two GDSCs have independent GDSCR registers with no 
HW-enforced sequencing, so they appear to be peers rather than parent/child.

  reply	other threads:[~2026-08-13  7:45 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-20  8:43 [PATCH 0/3] drm/msm: Enable dual MDSS power domains Yongxing Mou
2026-07-20  8:43 ` [PATCH 1/3] dt-bindings: display: msm: Allow two " Yongxing Mou
2026-07-20  8:49   ` Konrad Dybcio
2026-08-13  7:44     ` Yongxing Mou [this message]
2026-07-20  8:54   ` sashiko-bot
2026-07-21 18:18   ` Dmitry Baryshkov
2026-08-13  7:45     ` Yongxing Mou
2026-07-21 18:20   ` Dmitry Baryshkov
2026-08-13  8:06     ` Yongxing Mou
2026-07-24  9:36   ` Krzysztof Kozlowski
2026-08-13  7:45     ` Yongxing Mou
2026-07-20  8:43 ` [PATCH 2/3] drm/msm/mdss: Enable INT2_GDSC alongside CORE_GDSC Yongxing Mou
2026-07-20  8:58   ` sashiko-bot
2026-07-21 18:40   ` Dmitry Baryshkov
2026-08-13  7:45     ` Yongxing Mou
2026-07-20  8:43 ` [PATCH 3/3] arm64: dts: qcom: Add INT2_GDSC to MDSS on Kaanapali and Glymur Yongxing Mou
2026-07-20  9:05   ` sashiko-bot

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