From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Neil Armstrong <neil.armstrong@linaro.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties
Date: Tue, 21 Apr 2026 12:42:48 +0200 [thread overview]
Message-ID: <b8bd10c2-bdcd-47e2-8fe0-92177906c477@oss.qualcomm.com> (raw)
In-Reply-To: <20260420-topic-sm8650-upstream-cpu-props-v2-2-689e07d8ab8c@linaro.org>
On 4/20/26 9:26 PM, Neil Armstrong wrote:
> Add the L1 cache size and its line size (cache-size and
> cache-line-size) with the corresponding L1-I cache and L1-D cache.
>
> L1 cache is unified, but clidr_el1 register (get_cache_type) tells that
> L1 cache is separated (CACHE_TYPE_SEPARATE), add i-cache-line-size and
> d-cache-line-size and cache-line-size of L3 cache is specified.
>
> All cache line sizes were confirmed by checking ccsidr_el1.
>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
next prev parent reply other threads:[~2026-04-21 10:42 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-04-20 19:26 [PATCH v2 0/3] arm64: qcom: sm8650: misc enhancements Neil Armstrong
2026-04-20 19:26 ` [PATCH v2 1/3] arm64: dts: qcom: sm8650: update the cpus capacity-dmips-mhz Neil Armstrong
2026-04-20 19:26 ` [PATCH v2 2/3] arm64: dts: qcom: sm8650: add CPU cache size properties Neil Armstrong
2026-04-21 10:42 ` Konrad Dybcio [this message]
2026-04-20 19:26 ` [PATCH v2 3/3] arm64: dts: qcom: sm8650: fix soundwire ports properties Neil Armstrong
2026-04-22 11:04 ` Konrad Dybcio
2026-04-22 11:22 ` Krzysztof Kozlowski
2026-04-22 14:09 ` Neil Armstrong
2026-04-22 14:35 ` Krzysztof Kozlowski
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