From: Jan Kiszka <jan.kiszka@siemens.com>
To: Nishanth Menon <nm@ti.com>, Judith Mendez <jm@ti.com>
Cc: devicetree@vger.kernel.org, Vignesh Raghavendra <vigneshr@ti.com>,
linux-kernel@vger.kernel.org, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>
Subject: Re: [PATCH v2 0/6] Add and fix ESM nodes
Date: Thu, 15 Aug 2024 16:19:03 +0200 [thread overview]
Message-ID: <bac9837c-6dea-4ca1-9bda-9a4985403ed2@siemens.com> (raw)
In-Reply-To: <20240815122928.4i2yob5aj5ssqhzw@reply>
On 15.08.24 14:29, Nishanth Menon wrote:
> On 08:59-20240814, Judith Mendez wrote:
>> Hi Jan,
>>
>> On 8/13/24 11:04 PM, Jan Kiszka wrote:
>>> On 14.08.24 01:03, Judith Mendez wrote:
>>>> The following patch adds ESM nodes and fixes ESM source
>>>> interrupts for Sitara K3 platforms. Currently watchdog cannot
>>>> reset the CPU because of misconfiguration or missing ESM node
>>>> in DT.
>>>>
>>>> ESM node was added for am62ax and am65x. For am62px ESM source
>>>> interrupts are fixed. Comments were also added for clarity on what
>>>> source interrupts are routed to ESM based on device TRM.
>>>>
>>>> ESM nodes like MCU ESM for am65x are added for device completion,
>>>> currently, some ESM0 events are not routed to MCU ESM, so watchdog
>>>> cannot reset the CPU using the current implementation.
>>>
>>> Yes, that's why there is https://github.com/siemens/k3-rti-wdt and
>>> probably similar bits in other R5 firmware. I was always told that is
>>> the only way to reset the /system/ (CPU alone would not help). That
>>> information is still correct?
>>
>> If you look at 9.4.14 MCU_ESM0 Interrupt Map, ESM0_ESM_INT_CFG_LVL_0,
>> ESM0_ESM_INT_HI_LVL_0, and ESM0_ESM_INT_LOW_LVL_0 are not routed to
>> MCU_ESM0. So the current implementation to route events from ESM0 to
>> MCU_ESM0 to reset the CPU will not work for AM65x, this is the
>> implementation on other K3 Sitara platforms and how watchdog can reset
>> the cpu.
>>
>> I did find MAIN_ESM_ERROR_INT which should be SOC_SAFETY_ERRORn, look
>> at Figure 12-3690. Perhaps the ESMs could be configured to use
>> SOC_SAFETY_ERRORn instead, not sure.
>>
>> The above should apply to both SR1 and SR2 devices according to the TRM.
>
> Thanks for clarifying - you should add that in the commit message.
>
So the short answer to my question is "yes".
Jan
--
Siemens AG, Technology
Linux Expert Center
next prev parent reply other threads:[~2024-08-15 14:19 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-13 23:03 [PATCH v2 0/6] Add and fix ESM nodes Judith Mendez
2024-08-13 23:03 ` [PATCH v2 1/6] arm64: dts: ti: k3-am62a: Add " Judith Mendez
2024-08-13 23:03 ` [PATCH v2 2/6] arm64: dts: ti: k3-am62p: Fix ESM interrupt sources Judith Mendez
2024-08-13 23:03 ` [PATCH v2 3/6] arm64: dts: ti: k3-am62p: Remove 'reserved' status for ESM Judith Mendez
2024-08-13 23:03 ` [PATCH v2 4/6] arm64: dts: ti: k3-am62: Add comments to ESM nodes Judith Mendez
2024-08-13 23:03 ` [PATCH v2 5/6] arm64: dts: ti: k3-am64: Add more ESM interrupt sources Judith Mendez
2024-08-13 23:03 ` [PATCH v2 6/6] arm64: dts: ti: k3-am65: Add ESM nodes Judith Mendez
2024-08-14 14:05 ` Judith Mendez
2024-08-15 12:32 ` Nishanth Menon
2024-08-15 14:20 ` Jan Kiszka
2024-08-14 4:04 ` [PATCH v2 0/6] Add and fix " Jan Kiszka
2024-08-14 13:59 ` Judith Mendez
2024-08-15 12:29 ` Nishanth Menon
2024-08-15 14:19 ` Jan Kiszka [this message]
2024-08-15 14:27 ` Judith Mendez
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