Re: [PATCH v3 2/5] arm64: dts: qcom: Add Kalambo SoC

[Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>]

On 7/29/2026 7:39 PM, Konrad Dybcio wrote:
> On 7/27/26 2:51 PM, Gopikrishna Garmidi wrote:
>> Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
>> with CPU cluster 0 removed, leaving it with just cluster 1 (cpu6-cpu11).
>>
>> The surviving cluster is re-added to the cpu-map as cluster0, since the
>> kernel stops scanning at the first missing clusterN index. cpu6-cpu11
>> are reassigned to SCMI performance domain 0, as domain 1 is no longer
>> present.
>>
>> Kalambo uses PDP1 whose tx shmem (lpri1) sits at offset 0x200 within
>> imem, vs 0x180 on Glymur (PDP0). This pushes the tx region end to
>> 0x380, requiring an imem size override. The rx shmem (lpri0) stays at
>> offset 0x0. The PDP mailbox addresses are overridden to match the
>> Kalambo SCP firmware.
>>
>> Add labels to the cpus and cpu-map nodes in Glymur to allow derived
>> SoCs to delete and redefine the cpu-map entirely.
>>
>> Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
>> Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
>> ---
> 
> I now noticed you'll also need to override the PDC ranges. I sent
> a fixup for glymur/mahua (the map is common for the two), but kalambo
> is different.
> 

Hi konrad,

Thanks. Kalambo only differs in one spot: pins 109/110 are unconnected,
so <108 619 22> splits into:

	<108 619 1>,
	<111 622 19>,

Everything else matches the Glymur values. Will add in v3.

Thanks,
Gopikrishna