[PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Marek Vasut]

Add a DT overlay to bind the WaveShare 2-Channel Isolated CAN FD
Expansion HAT on the Retronix R-Car V4H Sparrow Hawk board.

Current device link is at https://www.waveshare.com/2-ch-can-fd-hat.htm

Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Geert Uytterhoeven <geert+renesas@glider.be>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-renesas-soc@vger.kernel.org
---
 arch/arm64/boot/dts/renesas/Makefile          |   3 +
 .../r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso   | 130 ++++++++++++++++++
 2 files changed, 133 insertions(+)
 create mode 100644 arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso

diff --git a/arch/arm64/boot/dts/renesas/Makefile b/arch/arm64/boot/dts/renesas/Makefile
index 8bf155badd111..69c1405a6fd01 100644
--- a/arch/arm64/boot/dts/renesas/Makefile
+++ b/arch/arm64/boot/dts/renesas/Makefile
@@ -124,6 +124,9 @@ dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-5in.dtb
 dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
 r8a779g3-sparrow-hawk-rpi-display-2-7in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-rpi-display-2-7in.dtbo
 dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-rpi-display-2-7in.dtb
+dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-2ch-canfd.dtbo
+r8a779g3-sparrow-hawk-ws-2ch-canfd-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-ws-2ch-canfd.dtbo
+dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-2ch-canfd.dtb
 dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtbo
 r8a779g3-sparrow-hawk-ws-display-13in-dtbs := r8a779g3-sparrow-hawk.dtb r8a779g3-sparrow-hawk-ws-display-13in.dtbo
 dtb-$(CONFIG_ARCH_R8A779G0) += r8a779g3-sparrow-hawk-ws-display-13in.dtb
diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso
new file mode 100644
index 0000000000000..de72680efa7c6
--- /dev/null
+++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso
@@ -0,0 +1,130 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Device Tree Overlay for the Waveshare 2-Channel Isolated CAN FD HAT
+ * on connector CN7 on R-Car V4H ES3.0 Sparrow Hawk board
+ *
+ * Copyright (C) 2026 Marek Vasut <marek.vasut+renesas@mailbox.org>
+ *
+ * Example usage:
+ * - Connect HAT signals to Sparrow Hawk board CAN BUS connector CONN2:
+ *   HAT CAN_0 H -- CONN2 pin 6
+ *   HAT CAN_0 L -- CONN2 pin 2
+ *   HAT CAN_1 H -- CONN2 pin 5
+ *   HAT CAN_1 L -- CONN2 pin 1
+ *
+ * - Determine which interface is which:
+ *   $ ip -d link show
+ *   2: can0: <NOARP,ECHO> ...
+ *      ...
+ *        clock 40000000 ... e6660000.can <------ Native Renesas CANFD
+ *   3: can1: <NOARP,ECHO> ...
+ *      ...
+ *   4: can2: <NOARP,ECHO> ...
+ *      ...
+ *        clock 40000000 ... spi1.0 <------------ SPI CANFD on this HAT
+ *   5: can3: <NOARP,ECHO> ...
+ *      ...
+ *
+ * - Bring connected interfaces up:
+ *   # CAN_0 link
+ *   $ ip link set can0 up type can bitrate 125000 dbitrate 250000 fd on
+ *   $ ip link set can3 up type can bitrate 125000 dbitrate 250000 fd on
+ *
+ *   # CAN_1 link
+ *   $ ip link set can1 up type can bitrate 125000 dbitrate 250000 fd on
+ *   $ ip link set can2 up type can bitrate 125000 dbitrate 250000 fd on
+ *
+ * - Perform CAN test, run each of the pair commands in separate terminals:
+ *   # CAN_0 link
+ *   $ canfdtest -v can0
+ *   $ canfdtest -g -v can3
+ *
+ *   # CAN_1 link
+ *   $ canfdtest -v can1
+ *   $ canfdtest -g -v can2
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+&{/} {
+	/* Fixed clock dedicated to SPI CAN on 2-CH CAN FD HAT */
+	clk_can0: clk-ws-2ch-canfd0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+
+	clk_can1: clk-ws-2ch-canfd1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <40000000>;
+	};
+
+	/*
+	 * SPI_1 is operated as GPIO SPI, because MSIOF5 can not be
+	 * muxed on the pins allocated for SPI_1 on this CANFD HAT.
+	 */
+	spi-ws-2ch-canfd {	/* SPI_1 */
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "spi-gpio";
+		sck-gpios = <&gpio0 10 0>;		/* CN7 pin 40 */
+		miso-gpios = <&gpio0 9 0>;		/* CN7 pin 35 */
+		mosi-gpios = <&gpio0 12 0>;		/* CN7 pin 38 */
+		cs-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;	/* CN7 pin 12 */
+		num-chipselects = <1>;
+
+		can@0 {
+			compatible = "microchip,mcp2518fd";
+			clocks = <&clk_can1>;
+			/* CN7 pin 18 */
+			interrupts-extended = <&gpio1 25 IRQ_TYPE_EDGE_FALLING>;
+			reg = <0>;
+			spi-max-frequency = <20000000>;
+		};
+	};
+};
+
+&msiof0 {	/* SPI_0 */
+	#address-cells = <1>;
+	#size-cells = <0>;
+	pinctrl-0 = <&msiof0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+
+	/*
+	 * Native MSIOF chipselect does not work with MCP2518FD
+	 * because MCP251xFD driver needs to keep the chipselect
+	 * line asserted between transfers. This requirement is
+	 * fulfilled only by using GPIO chipselect.
+	 */
+	cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+
+	can@0 {
+		compatible = "microchip,mcp2518fd";
+		clocks = <&clk_can0>;
+		interrupts-extended = <&gpio1 26 IRQ_TYPE_EDGE_FALLING>;
+		reg = <0>;
+		spi-max-frequency = <20000000>;
+	};
+};
+
+&pfc {
+	msiof0_pins: spi-ws-2ch-canfd0 {	/* SPI_0 */
+		groups = "msiof0_clk", "msiof0_txd", "msiof0_rxd";
+		function = "msiof0";
+	};
+};
+
+/*
+ * PWM1 uses PWM1_B pin configuration for pin GP2_13. This conflicts
+ * with SPI_1 CE_1 signal which is also on pin GP2_13. Disable PWM1
+ * in case this hat is in use.
+ */
+&pwm1 {
+	status = "disabled";
+};
-- 
2.53.0

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] Potential CAN controller freeze due to edge-triggered interrupt configuration for active-low level-sensitive INT pin.
- [Low] Devicetree schema violation with non-standard node names for clock and SPI nodes.
--

--- Patch [1]: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT ---
commit b5cd8b12c94510c91e67da4257339818760852d2
Author: Marek Vasut <marek.vasut+renesas@mailbox.org>

arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

Add a DT overlay to bind the WaveShare 2-Channel Isolated CAN FD Expansion
HAT on the Retronix R-Car V4H Sparrow Hawk board.

> diff --git a/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso
> new file mode 100644
> index 0000000000000..de72680efa7c6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso
[ ... ]
> +&{/} {
> +	/* Fixed clock dedicated to SPI CAN on 2-CH CAN FD HAT */
> +	clk_can0: clk-ws-2ch-canfd0 {

[Severity: Low]
Does this node name violate the fixed-clock devicetree bindings schema?
The schema typically mandates node names matching the pattern clock-* to pass
dtbs_check validation.

> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <40000000>;
> +	};
> +
> +	clk_can1: clk-ws-2ch-canfd1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <40000000>;
> +	};
> +
> +	/*
> +	 * SPI_1 is operated as GPIO SPI, because MSIOF5 can not be
> +	 * muxed on the pins allocated for SPI_1 on this CANFD HAT.
> +	 */
> +	spi-ws-2ch-canfd {	/* SPI_1 */

[Severity: Low]
Is this non-generic node name likely to trigger devicetree validation
warnings? Standard devicetree practices recommend using the generic spi node
name rather than spi-ws-2ch-canfd.

> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		compatible = "spi-gpio";
> +		sck-gpios = <&gpio0 10 0>;		/* CN7 pin 40 */
> +		miso-gpios = <&gpio0 9 0>;		/* CN7 pin 35 */
> +		mosi-gpios = <&gpio0 12 0>;		/* CN7 pin 38 */
> +		cs-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>;	/* CN7 pin 12 */
> +		num-chipselects = <1>;
> +
> +		can@0 {
> +			compatible = "microchip,mcp2518fd";
> +			clocks = <&clk_can1>;
> +			/* CN7 pin 18 */
> +			interrupts-extended = <&gpio1 25 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Can configuring this interrupt as IRQ_TYPE_EDGE_FALLING cause the CAN
controller to freeze?

The MCP2518FD INT pin is active-low and level-sensitive. If a new interrupt
condition occurs while the INT pin is already asserted low, a new falling
edge might not be generated, causing the new interrupt to be permanently
missed. Should this use IRQ_TYPE_LEVEL_LOW instead?

> +			reg = <0>;
> +			spi-max-frequency = <20000000>;
> +		};
> +	};
> +};
> +
> +&msiof0 {	/* SPI_0 */
> +	#address-cells = <1>;
> +	#size-cells = <0>;
> +	pinctrl-0 = <&msiof0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +
> +	/*
> +	 * Native MSIOF chipselect does not work with MCP2518FD
> +	 * because MCP251xFD driver needs to keep the chipselect
> +	 * line asserted between transfers. This requirement is
> +	 * fulfilled only by using GPIO chipselect.
> +	 */
> +	cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> +
> +	can@0 {
> +		compatible = "microchip,mcp2518fd";
> +		clocks = <&clk_can0>;
> +		interrupts-extended = <&gpio1 26 IRQ_TYPE_EDGE_FALLING>;

[Severity: High]
Similarly, can this edge-triggered configuration for the native MSIOF CAN
controller lead to missed interrupts if the active-low level-sensitive INT
pin is already asserted when a new interrupt arrives?

> +		reg = <0>;
> +		spi-max-frequency = <20000000>;
> +	};
> +};

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/20260808025724.131943-1-marek.vasut+renesas@mailbox.org?part=1

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Geert Uytterhoeven]

Hi Marek,

On Sat, 8 Aug 2026 at 04:57, Marek Vasut
<marek.vasut+renesas@mailbox.org> wrote:
> Add a DT overlay to bind the WaveShare 2-Channel Isolated CAN FD
> Expansion HAT on the Retronix R-Car V4H Sparrow Hawk board.
>
> Current device link is at https://www.waveshare.com/2-ch-can-fd-hat.htm
>
> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>

Thanks for your patch!

> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk-ws-2ch-canfd.dtso

> +&{/} {
> +       /* Fixed clock dedicated to SPI CAN on 2-CH CAN FD HAT */
> +       clk_can0: clk-ws-2ch-canfd0 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <40000000>;
> +       };
> +
> +       clk_can1: clk-ws-2ch-canfd1 {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <40000000>;
> +       };
> +
> +       /*
> +        * SPI_1 is operated as GPIO SPI, because MSIOF5 can not be
> +        * muxed on the pins allocated for SPI_1 on this CANFD HAT.
> +        */
> +       spi-ws-2ch-canfd {      /* SPI_1 */
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               compatible = "spi-gpio";

Please list the "compatible" property first (everywhere).

> +               sck-gpios = <&gpio0 10 0>;              /* CN7 pin 40 */
> +               miso-gpios = <&gpio0 9 0>;              /* CN7 pin 35 */
> +               mosi-gpios = <&gpio0 12 0>;             /* CN7 pin 38 */
> +               cs-gpios = <&gpio2 13 GPIO_ACTIVE_LOW>; /* CN7 pin 12 */
> +               num-chipselects = <1>;
> +
> +               can@0 {
> +                       compatible = "microchip,mcp2518fd";
> +                       clocks = <&clk_can1>;
> +                       /* CN7 pin 18 */
> +                       interrupts-extended = <&gpio1 25 IRQ_TYPE_EDGE_FALLING>;

Datasheet says active low, so IRQ_TYPE_LEVEL_LOW.

> +                       reg = <0>;

Please list the "reg" property second (everywhere).

> +                       spi-max-frequency = <20000000>;
> +               };
> +       };
> +};
> +
> +&msiof0 {      /* SPI_0 */
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       pinctrl-0 = <&msiof0_pins>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +
> +       /*
> +        * Native MSIOF chipselect does not work with MCP2518FD
> +        * because MCP251xFD driver needs to keep the chipselect
> +        * line asserted between transfers. This requirement is
> +        * fulfilled only by using GPIO chipselect.
> +        */
> +       cs-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
> +
> +       can@0 {
> +               compatible = "microchip,mcp2518fd";
> +               clocks = <&clk_can0>;

Please insert a comment "/* CN7 pin 22 */".

> +               interrupts-extended = <&gpio1 26 IRQ_TYPE_EDGE_FALLING>;

IRQ_TYPE_LEVEL_LOW.

> +               reg = <0>;
> +               spi-max-frequency = <20000000>;
> +       };
> +};
> +
> +&pfc {
> +       msiof0_pins: spi-ws-2ch-canfd0 {        /* SPI_0 */

Node name should be "msiof0".

> +               groups = "msiof0_clk", "msiof0_txd", "msiof0_rxd";
> +               function = "msiof0";
> +       };
> +};
> +
> +/*
> + * PWM1 uses PWM1_B pin configuration for pin GP2_13. This conflicts
> + * with SPI_1 CE_1 signal which is also on pin GP2_13. Disable PWM1
> + * in case this hat is in use.
> + */
> +&pwm1 {
> +       status = "disabled";
> +};

Please move this node disabling pwm1 to the top, for compatibility
with dynamic DT overlays.

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Marek Vasut]

On 9/8/26 2:02 PM, Geert Uytterhoeven wrote:

Hello Geert,

>> +&pfc {
>> +       msiof0_pins: spi-ws-2ch-canfd0 {        /* SPI_0 */
> 
> Node name should be "msiof0".

Do we also have to fix up 
arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts this:

"
  755         msiof1_pins: sound {
                           ^^^^^
"
?

But I wonder, shouldn't the DTOs contain unique pinmux node names, which 
cannot accidentally overlap with the base DT or other DTO node names ?

>> +               groups = "msiof0_clk", "msiof0_txd", "msiof0_rxd";
>> +               function = "msiof0";
>> +       };
>> +};
>> +
>> +/*
>> + * PWM1 uses PWM1_B pin configuration for pin GP2_13. This conflicts
>> + * with SPI_1 CE_1 signal which is also on pin GP2_13. Disable PWM1
>> + * in case this hat is in use.
>> + */
>> +&pwm1 {
>> +       status = "disabled";
>> +};
> 
> Please move this node disabling pwm1 to the top, for compatibility
> with dynamic DT overlays.
Could you expand on that a bit ? What difference does the placement of 
this node make within the DTSO ? Please pardon my ignorance.

The rest of the review items are addressed in V2.

Thank you for your help!

-- 
Best regards,
Marek Vasut

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Geert Uytterhoeven]

Hi Marek,

On Tue, 8 Sept 2026 at 19:02, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 9/8/26 2:02 PM, Geert Uytterhoeven wrote:
> >> +&pfc {
> >> +       msiof0_pins: spi-ws-2ch-canfd0 {        /* SPI_0 */
> >
> > Node name should be "msiof0".
>
> Do we also have to fix up
> arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts this:
>
> "
>   755         msiof1_pins: sound {
>                            ^^^^^
> "
> ?

Might be a good idea, to increase consistency.

> But I wonder, shouldn't the DTOs contain unique pinmux node names, which
> cannot accidentally overlap with the base DT or other DTO node names ?

In general, the answer is yes.
In this case it is about pin control subnodes. If the base DTS already
uses msiof0, its original user needs to be disabled by the overlay
anyway.

> >> +               groups = "msiof0_clk", "msiof0_txd", "msiof0_rxd";
> >> +               function = "msiof0";
> >> +       };
> >> +};
> >> +
> >> +/*
> >> + * PWM1 uses PWM1_B pin configuration for pin GP2_13. This conflicts
> >> + * with SPI_1 CE_1 signal which is also on pin GP2_13. Disable PWM1
> >> + * in case this hat is in use.
> >> + */
> >> +&pwm1 {
> >> +       status = "disabled";
> >> +};
> >
> > Please move this node disabling pwm1 to the top, for compatibility
> > with dynamic DT overlays.
> Could you expand on that a bit ? What difference does the placement of
> this node make within the DTSO ? Please pardon my ignorance.

In case of a dynamic overlay, pwm1 must be disabled before SPI_1 is
probed.  Otherwise the latter will fail with -EBUSY due to the
conflicting pin being still in use.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Marek Vasut]

On 9/9/26 9:56 AM, Geert Uytterhoeven wrote:

Hello Geert,

> On Tue, 8 Sept 2026 at 19:02, Marek Vasut <marek.vasut@mailbox.org> wrote:
>> On 9/8/26 2:02 PM, Geert Uytterhoeven wrote:
>>>> +&pfc {
>>>> +       msiof0_pins: spi-ws-2ch-canfd0 {        /* SPI_0 */
>>>
>>> Node name should be "msiof0".
>>
>> Do we also have to fix up
>> arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts this:
>>
>> "
>>    755         msiof1_pins: sound {
>>                             ^^^^^
>> "
>> ?
> 
> Might be a good idea, to increase consistency.

Submitted as

[PATCH] arm64: dts: renesas: sparrow-hawk: Align MSIOF1 PFC node name 
with label

>> But I wonder, shouldn't the DTOs contain unique pinmux node names, which
>> cannot accidentally overlap with the base DT or other DTO node names ?
> 
> In general, the answer is yes.
> In this case it is about pin control subnodes. If the base DTS already
> uses msiof0, its original user needs to be disabled by the overlay
> anyway.

The original DTS does not use MSIOF0 .

I think the proper solution here would be DT connector ?

>>>> +               groups = "msiof0_clk", "msiof0_txd", "msiof0_rxd";
>>>> +               function = "msiof0";
>>>> +       };
>>>> +};
>>>> +
>>>> +/*
>>>> + * PWM1 uses PWM1_B pin configuration for pin GP2_13. This conflicts
>>>> + * with SPI_1 CE_1 signal which is also on pin GP2_13. Disable PWM1
>>>> + * in case this hat is in use.
>>>> + */
>>>> +&pwm1 {
>>>> +       status = "disabled";
>>>> +};
>>>
>>> Please move this node disabling pwm1 to the top, for compatibility
>>> with dynamic DT overlays.
>> Could you expand on that a bit ? What difference does the placement of
>> this node make within the DTSO ? Please pardon my ignorance.
> 
> In case of a dynamic overlay, pwm1 must be disabled before SPI_1 is
> probed.  Otherwise the latter will fail with -EBUSY due to the
> conflicting pin being still in use.

TIL, thank you.

-- 
Best regards,
Marek Vasut

Re: [PATCH] arm64: dts: renesas: sparrow-hawk: Add overlay for WaveShare 2CH CANFD HAT

[Geert Uytterhoeven]

Hi Marek,

On Wed, 9 Sept 2026 at 17:16, Marek Vasut <marek.vasut@mailbox.org> wrote:
> On 9/9/26 9:56 AM, Geert Uytterhoeven wrote:
> > On Tue, 8 Sept 2026 at 19:02, Marek Vasut <marek.vasut@mailbox.org> wrote:
> >> On 9/8/26 2:02 PM, Geert Uytterhoeven wrote:
> >>>> +&pfc {
> >>>> +       msiof0_pins: spi-ws-2ch-canfd0 {        /* SPI_0 */
> >>>
> >>> Node name should be "msiof0".
> >>
> >> Do we also have to fix up
> >> arch/arm64/boot/dts/renesas/r8a779g3-sparrow-hawk.dts this:
> >>
> >> "
> >>    755         msiof1_pins: sound {
> >>                             ^^^^^
> >> "
> >> ?
> >
> > Might be a good idea, to increase consistency.
>
> Submitted as
>
> [PATCH] arm64: dts: renesas: sparrow-hawk: Align MSIOF1 PFC node name
> with label

Thanks!

> >> But I wonder, shouldn't the DTOs contain unique pinmux node names, which
> >> cannot accidentally overlap with the base DT or other DTO node names ?
> >
> > In general, the answer is yes.
> > In this case it is about pin control subnodes. If the base DTS already
> > uses msiof0, its original user needs to be disabled by the overlay
> > anyway.
>
> The original DTS does not use MSIOF0 .
>
> I think the proper solution here would be DT connector ?

Keeping an eye on Hervé's work...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds