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From: "Jernej Škrabec" <jernej.skrabec@gmail.com>
To: Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Guo Ren <guoren@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>, Radu Rendec <radu@rendec.net>,
	Samuel Holland <samuel.holland@sifive.com>,
	Daniel Lezcano <daniel.lezcano@kernel.org>,
	Anup Patel <anup@brainfault.org>, Han Gao <gaohan@iscas.ac.cn>,
	Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	Jerome Brunet <jbrunet+clk@baylibre.com>,
	Chen-Yu Tsai <wens@kernel.org>,
	Samuel Holland <samuel@sholland.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Maxime Ripard <mripard@kernel.org>,
	Linus Walleij <linusw@kernel.org>,
	Andre Przywara <andre.przywara@arm.com>,
	gaohan@iscas.ac.cn
Cc: Han Gao <rabenda.cn@gmail.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@sifive.com>,
	Conor Dooley <conor@kernel.org>,
	devicetree@vger.kernel.org, linux-csky@vger.kernel.org,
	linux-sunxi@lists.linux.dev, linux-clk@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, linux-rtc@vger.kernel.org,
	linux-gpio@vger.kernel.org
Subject: Re: [PATCH 06/19] clk: sunxi-ng: add support for the Allwinner V861 CCU
Date: Sun, 15 Nov 2026 08:31:11 +0100	[thread overview]
Message-ID: <c8OwiyQSR8ivEFULfFWNow@gmail.com> (raw)
In-Reply-To: <20261114-v861-v1-6-eb71ec3ee523@iscas.ac.cn>

Dne petek, 13. november 2026 ob 23:33:32 Srednjeevropski standardni čas je Han Gao via B4 Relay napisal(a):
> From: Han Gao <gaohan@iscas.ac.cn>
> 
> Add the main CCU driver for the V861, based on the A523 one. The CPU
> PLL, the CPU subsystem clocks and the E907 clocks are left to the
> firmware.
> 
> Unlike on the A523, the second divider of the 27 MHz output is a power
> of two. pll-audio-4x does not pass rate changes up, as its parent also
> feeds the UART clock mux.
> 
> Signed-off-by: Han Gao <gaohan@iscas.ac.cn>

Do you have any user manual for it? Or at least BSP code? It's hard to
review patches without any of those references.

Best regards,
Jernej



  parent reply	other threads:[~2026-11-15  7:31 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-13 22:33 [PATCH 00/19] riscv: add initial support for the Allwinner V861 and Avaota F2 Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 01/19] riscv: sunxi: describe the wider Allwinner SoC family Han Gao via B4 Relay
2026-11-14 13:13   ` Guo Ren
2026-11-13 22:33 ` [PATCH 02/19] dt-bindings: riscv: cpus: add the XuanTie C907 Han Gao via B4 Relay
2026-11-14 12:56   ` Guo Ren
2026-11-13 22:33 ` [PATCH 03/19] dt-bindings: interrupt-controller: add the Allwinner V861 PLIC Han Gao via B4 Relay
2026-11-14 13:07   ` Guo Ren
2026-11-14 13:29   ` Guo Ren
2026-11-13 22:33 ` [PATCH 04/19] dt-bindings: timer: add the Allwinner V861 CLINT Han Gao via B4 Relay
2026-11-14 13:08   ` Guo Ren
2026-11-14 13:30   ` Guo Ren
2026-11-13 22:33 ` [PATCH 05/19] dt-bindings: clock: sunxi-ng: document the Allwinner V861 CCUs Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 06/19] clk: sunxi-ng: add support for the Allwinner V861 CCU Han Gao via B4 Relay
2026-11-13 22:46   ` sashiko-bot
2026-11-15  7:31   ` Jernej Škrabec [this message]
2026-11-13 22:33 ` [PATCH 07/19] clk: sunxi-ng: add support for the Allwinner V861 PRCM CCU Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 08/19] dt-bindings: rtc: sun6i: add the Allwinner V861 RTC Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 09/19] clk: sunxi-ng: sun6i-rtc: allow variants without a 32k fanout mux Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 10/19] clk: sunxi-ng: sun6i-rtc: allow another 24 MHz to 32k divider ratio Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 11/19] clk: sunxi-ng: sun6i-rtc: add Allwinner V861 support Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 12/19] dt-bindings: pinctrl: add the Allwinner V861 pin controllers Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 13/19] pinctrl: sunxi: allow a per-controller IRQ register base Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 14/19] pinctrl: sunxi: add support for the Allwinner V861 PIO Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 15/19] pinctrl: sunxi: add support for the Allwinner V861 R-PIO Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 16/19] riscv: dts: allwinner: add the Allwinner V861 SoC Han Gao via B4 Relay
2026-11-14 13:23   ` Guo Ren
2026-11-13 22:33 ` [PATCH 17/19] dt-bindings: riscv: sunxi: add the YuzukiHD Avaota F2 Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 18/19] riscv: dts: allwinner: add the YuzukiHD Avaota F2 board Han Gao via B4 Relay
2026-11-13 22:33 ` [PATCH 19/19] MAINTAINERS: add an entry for the Allwinner V861 SoC Han Gao via B4 Relay
2026-11-14 13:15   ` Guo Ren
2026-11-15  5:11   ` Icenowy Zheng
2026-11-15  7:32     ` Jernej Škrabec
2026-11-15  7:46       ` Chen-Yu Tsai

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