* [PATCH 0/2] dt-bindings: arm64: dts: Intel SoCFPGA: rsu-handle on svc for U-Boot
@ 2026-05-06 12:42 tze.yee.ng
2026-05-06 12:42 ` [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc tze.yee.ng
2026-05-06 12:42 ` [PATCH 2/2] arm64: dts: socfpga: add rsu-handle to svc on QSPI SoCDK boards tze.yee.ng
0 siblings, 2 replies; 5+ messages in thread
From: tze.yee.ng @ 2026-05-06 12:42 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Mahesh Rao, linux-kernel, devicetree
Cc: Tze Yee Ng, Adrian Ng Ho Yin, Nazim Amirul
From: Tze Yee Ng <tze.yee.ng@altera.com>
When Linux passes a device tree to U-Boot for remote system update (RSU),
U-Boot needs to know which QSPI partition holds the boot image. Add an
optional rsu-handle property on the Intel service-layer (svc) node: it is
a phandle to the board's QSPI boot partition (typically labeled
qspi_boot).
Patch 1 documents rsu-handle in the intel,stratix10-svc binding (shared by
Stratix 10, Agilex, and Agilex5 svc compatibles) and extends the example
so the qspi_boot label and reg cells are valid for dt_binding_check.
Patch 2 labels the firmware svc node as "svc" in the Stratix 10, Agilex,
and Agilex5 SoC .dtsi files, and sets rsu-handle = <&qspi_boot> via &svc
only on board .dts files that already define qspi_boot. Boards without
that partition are unchanged and avoid an unresolved phandle.
Tze Yee Ng (2):
dt-bindings: firmware: document rsu-handle for intel stratix10-svc
arm64: dts: socfpga: add rsu-handle to svc on QSPI SoCDK boards
.../firmware/intel,stratix10-svc.yaml | 25 +++++++++++++++++++
.../boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
.../dts/altera/socfpga_stratix10_socdk.dts | 4 +++
.../altera/socfpga_stratix10_socdk_nand.dts | 4 +++
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
.../boot/dts/intel/socfpga_agilex3_socdk.dts | 4 +++
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
.../boot/dts/intel/socfpga_agilex5_socdk.dts | 4 +++
.../dts/intel/socfpga_agilex5_socdk_013b.dts | 4 +++
.../intel/socfpga_agilex5_socdk_modular.dts | 4 +++
.../boot/dts/intel/socfpga_agilex_socdk.dts | 4 +++
.../boot/dts/intel/socfpga_n5x_socdk.dts | 4 +++
12 files changed, 60 insertions(+), 3 deletions(-)
--
2.43.7
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc
2026-05-06 12:42 [PATCH 0/2] dt-bindings: arm64: dts: Intel SoCFPGA: rsu-handle on svc for U-Boot tze.yee.ng
@ 2026-05-06 12:42 ` tze.yee.ng
2026-05-06 13:12 ` Krzysztof Kozlowski
2026-05-06 13:22 ` Rob Herring (Arm)
2026-05-06 12:42 ` [PATCH 2/2] arm64: dts: socfpga: add rsu-handle to svc on QSPI SoCDK boards tze.yee.ng
1 sibling, 2 replies; 5+ messages in thread
From: tze.yee.ng @ 2026-05-06 12:42 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Mahesh Rao, linux-kernel, devicetree
Cc: Tze Yee Ng, Adrian Ng Ho Yin, Nazim Amirul
From: Tze Yee Ng <tze.yee.ng@altera.com>
Add the optional rsu-handle property to the intel,stratix10-svc binding.
It holds a phandle to the QSPI boot partition (qspi_boot) for U-Boot
remote system update (RSU) handoff.
Extend the example with a minimal QSPI fixed-partitions node so the
qspi_boot label is defined where rsu-handle is used.
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
.../firmware/intel,stratix10-svc.yaml | 25 +++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
index b42cfa78b28b..5b90058f4f6b 100644
--- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
+++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
@@ -58,6 +58,12 @@ properties:
iommus:
maxItems: 1
+ rsu-handle:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle to the QSPI boot partition node (qspi_boot), used by U-Boot
+ during remote system update flow.
+
fpga-mgr:
$ref: /schemas/fpga/intel,stratix10-soc-fpga-mgr.yaml
description: Optional child node for fpga manager to perform fabric configuration.
@@ -94,11 +100,30 @@ examples:
};
};
+ qspi@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0x0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ };
+ };
+ };
+
firmware {
svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
+ rsu-handle = <&qspi_boot>;
fpga-mgr {
compatible = "intel,stratix10-soc-fpga-mgr";
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: socfpga: add rsu-handle to svc on QSPI SoCDK boards
2026-05-06 12:42 [PATCH 0/2] dt-bindings: arm64: dts: Intel SoCFPGA: rsu-handle on svc for U-Boot tze.yee.ng
2026-05-06 12:42 ` [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc tze.yee.ng
@ 2026-05-06 12:42 ` tze.yee.ng
1 sibling, 0 replies; 5+ messages in thread
From: tze.yee.ng @ 2026-05-06 12:42 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Mahesh Rao, linux-kernel, devicetree
Cc: Tze Yee Ng, Adrian Ng Ho Yin, Nazim Amirul
From: Tze Yee Ng <tze.yee.ng@altera.com>
Label the firmware svc node as "svc" in the Stratix 10, Agilex, and
Agilex5 SoC base include files so board DTS can override it by phandle.
Set rsu-handle = <&qspi_boot> on &svc only in board DTs that define
the qspi_boot partition, so boards without that partition do not
reference an undefined phandle.
Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
---
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 2 +-
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 4 ++++
arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 2 +-
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 4 ++++
arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 4 ++++
11 files changed, 35 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
index 0d9cad0c0351..64e9e1d8a852 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
@@ -70,7 +70,7 @@ l2_shared: cache {
};
firmware {
- svc {
+ svc: svc {
compatible = "intel,stratix10-svc";
method = "smc";
memory-region = <&service_reserved>;
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
index e2a1cea7f3da..f4c9f9bb26aa 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts
@@ -134,3 +134,7 @@ root: partition@4200000 {
};
};
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
index 7951ce46ae1f..1f3e4b50412d 100644
--- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
+++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk_nand.dts
@@ -184,3 +184,7 @@ qspi_rootfs: partition@3fe0000 {
};
};
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
index 0dfbafde8822..6440b4c6818a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi
@@ -61,7 +61,7 @@ cpu3: cpu@3 {
};
firmware {
- svc {
+ svc: svc {
compatible = "intel,agilex-svc";
method = "smc";
memory-region = <&service_reserved>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
index 14b299f19f3a..af8b75107216 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex3_socdk.dts
@@ -130,3 +130,7 @@ &uart0 {
&watchdog0 {
status = "okay";
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 02e62d954e94..d415b762f328 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -80,7 +80,7 @@ L3: l3-cache {
};
firmware {
- svc {
+ svc: svc {
compatible = "intel,agilex5-svc";
method = "smc";
memory-region = <&service_reserved>;
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index 262bb3e8e5c7..0985e70dfe44 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -110,3 +110,7 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
index f71e1280c778..5948f125ba0b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_013b.dts
@@ -124,3 +124,7 @@ &uart0 {
&watchdog0 {
status = "okay";
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
index 1831402d8808..78be156208d9 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk_modular.dts
@@ -107,3 +107,7 @@ &uart0 {
&watchdog0 {
status = "okay";
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
index 8f8a5423ba02..d277b7073dbf 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts
@@ -136,3 +136,7 @@ root: partition@4200000 {
};
};
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
index d7d500f50a07..ac8cf8b7257b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts
@@ -126,3 +126,7 @@ &usb0 {
&watchdog0 {
status = "okay";
};
+
+&svc {
+ rsu-handle = <&qspi_boot>;
+};
--
2.43.7
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc
2026-05-06 12:42 ` [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc tze.yee.ng
@ 2026-05-06 13:12 ` Krzysztof Kozlowski
2026-05-06 13:22 ` Rob Herring (Arm)
1 sibling, 0 replies; 5+ messages in thread
From: Krzysztof Kozlowski @ 2026-05-06 13:12 UTC (permalink / raw)
To: tze.yee.ng, Dinh Nguyen, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Mahesh Rao, linux-kernel, devicetree
Cc: Adrian Ng Ho Yin, Nazim Amirul
On 06/05/2026 14:42, tze.yee.ng@altera.com wrote:
> From: Tze Yee Ng <tze.yee.ng@altera.com>
>
> Add the optional rsu-handle property to the intel,stratix10-svc binding.
> It holds a phandle to the QSPI boot partition (qspi_boot) for U-Boot
> remote system update (RSU) handoff.
>
> Extend the example with a minimal QSPI fixed-partitions node so the
> qspi_boot label is defined where rsu-handle is used.
Not really relevant to the binding.
>
> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
> ---
> .../firmware/intel,stratix10-svc.yaml | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> index b42cfa78b28b..5b90058f4f6b 100644
> --- a/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> +++ b/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.yaml
> @@ -58,6 +58,12 @@ properties:
> iommus:
> maxItems: 1
>
> + rsu-handle:
Missing prefix but OTOH suffix "handle" is redundant.
> + $ref: /schemas/types.yaml#/definitions/phandle
> + description:
> + Phandle to the QSPI boot partition node (qspi_boot), used by U-Boot
> + during remote system update flow.
Do not explain what U-Boot does but explain the hardware - how is that
partition related anyhow hardware-wise to this SVC. I don't see that
connection and we do not add properties for SW.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc
2026-05-06 12:42 ` [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc tze.yee.ng
2026-05-06 13:12 ` Krzysztof Kozlowski
@ 2026-05-06 13:22 ` Rob Herring (Arm)
1 sibling, 0 replies; 5+ messages in thread
From: Rob Herring (Arm) @ 2026-05-06 13:22 UTC (permalink / raw)
To: tze.yee.ng
Cc: Adrian Ng Ho Yin, Conor Dooley, linux-kernel, devicetree,
Krzysztof Kozlowski, Mahesh Rao, Nazim Amirul, Dinh Nguyen
On Wed, 06 May 2026 05:42:20 -0700, tze.yee.ng@altera.com wrote:
> From: Tze Yee Ng <tze.yee.ng@altera.com>
>
> Add the optional rsu-handle property to the intel,stratix10-svc binding.
> It holds a phandle to the QSPI boot partition (qspi_boot) for U-Boot
> remote system update (RSU) handoff.
>
> Extend the example with a minimal QSPI fixed-partitions node so the
> qspi_boot label is defined where rsu-handle is used.
>
> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
> ---
> .../firmware/intel,stratix10-svc.yaml | 25 +++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
My bot found errors running 'make dt_binding_check' on your patch:
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.example.dtb: qspi@0 (jedec,spi-nor): $nodename:0: 'qspi@0' does not match '^(flash|.*sram|nand)(@.*)?$'
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.example.dtb: qspi@0 (jedec,spi-nor): reg:0: [0, 4096] is too long
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/firmware/intel,stratix10-svc.example.dtb: qspi@0 (jedec,spi-nor): Unevaluated properties are not allowed ('#address-cells', '#size-cells', 'partitions' were unexpected)
from schema $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.kernel.org/project/devicetree/patch/09822cb8171f90d50c018f2f1fae5e5aab737301.1778070377.git.tze.yee.ng@altera.com
The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-05-06 13:22 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-05-06 12:42 [PATCH 0/2] dt-bindings: arm64: dts: Intel SoCFPGA: rsu-handle on svc for U-Boot tze.yee.ng
2026-05-06 12:42 ` [PATCH 1/2] dt-bindings: firmware: document rsu-handle for intel stratix10-svc tze.yee.ng
2026-05-06 13:12 ` Krzysztof Kozlowski
2026-05-06 13:22 ` Rob Herring (Arm)
2026-05-06 12:42 ` [PATCH 2/2] arm64: dts: socfpga: add rsu-handle to svc on QSPI SoCDK boards tze.yee.ng
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