Re: [PATCH v7 3/7] clk: qcom: Add generic clkref_en support

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 7/2/26 9:36 AM, Qiang Yu wrote:
> Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
> a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
> register controls whether refclk is gated through to the PHY side.
> 
> These clkref controls are different from typical GCC branch clocks:
> - only a single enable bit is present, without branch-style config bits
> - regulators must be voted before enable and unvoted after disable
> 
> Model this as a dedicated clk_ref clock type with custom clk_ops instead
> of reusing struct clk_branch semantics.
> 
> Also provide a common registration/probe API so the same clkref model
> can be reused regardless of where clkref_en registers are placed, e.g.
> TCSR on glymur and TLMM on SM8750.
> 
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> ---

[...]

> +struct qcom_clk_ref_provider {
> +	struct qcom_clk_ref *refs;
> +	size_t num_refs;
> +};

If you define num_refs first, then you can have refs be a
zero-length array with __counted_by(num_refs) and make provider
a single allocation, like:

512946cf0f32 ("nvmem: rockchip-otp: alloc clks with main struct")

otherwise someone will come around and "fix" it in a day or two

otherwise

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
 
Konrad