* [PATCH] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0
@ 2026-06-09 13:16 muhammad.nazim.amirul.nazle.asmade
2026-06-11 22:35 ` Dinh Nguyen
0 siblings, 1 reply; 2+ messages in thread
From: muhammad.nazim.amirul.nazle.asmade @ 2026-06-09 13:16 UTC (permalink / raw)
To: dinguyen; +Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Extend the gmac0 interrupt list to support 8 TX and 8 RX per-channel
interrupts in addition to the combined macirq, enabling per-channel
interrupt handling for improved DMA performance.
Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
.../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 36 +++++++++++++++++--
1 file changed, 34 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index b06c6d5d60ee..c936f8db1bd0 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -557,8 +557,40 @@ gmac0: ethernet@10810000 {
compatible = "altr,socfpga-stmmac-agilex5",
"snps,dwxgmac-2.10";
reg = <0x10810000 0x3500>;
- interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "macirq";
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "macirq",
+ "tx-queue-0",
+ "tx-queue-1",
+ "tx-queue-2",
+ "tx-queue-3",
+ "tx-queue-4",
+ "tx-queue-5",
+ "tx-queue-6",
+ "tx-queue-7",
+ "rx-queue-0",
+ "rx-queue-1",
+ "rx-queue-2",
+ "rx-queue-3",
+ "rx-queue-4",
+ "rx-queue-5",
+ "rx-queue-6",
+ "rx-queue-7";
resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
reset-names = "stmmaceth", "ahb";
clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
--
2.43.7
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0
2026-06-09 13:16 [PATCH] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0 muhammad.nazim.amirul.nazle.asmade
@ 2026-06-11 22:35 ` Dinh Nguyen
0 siblings, 0 replies; 2+ messages in thread
From: Dinh Nguyen @ 2026-06-11 22:35 UTC (permalink / raw)
To: muhammad.nazim.amirul.nazle.asmade
Cc: robh, krzk+dt, conor+dt, devicetree, linux-kernel
On 6/9/26 22:16, muhammad.nazim.amirul.nazle.asmade@altera.com wrote:
> From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
>
> Extend the gmac0 interrupt list to support 8 TX and 8 RX per-channel
> interrupts in addition to the combined macirq, enabling per-channel
> interrupt handling for improved DMA performance.
>
> Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
> ---
> .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 36 +++++++++++++++++--
> 1 file changed, 34 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index b06c6d5d60ee..c936f8db1bd0 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -557,8 +557,40 @@ gmac0: ethernet@10810000 {
> compatible = "altr,socfpga-stmmac-agilex5",
> "snps,dwxgmac-2.10";
> reg = <0x10810000 0x3500>;
> - interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> - interrupt-names = "macirq";
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq",
> + "tx-queue-0",
> + "tx-queue-1",
> + "tx-queue-2",
> + "tx-queue-3",
> + "tx-queue-4",
> + "tx-queue-5",
> + "tx-queue-6",
> + "tx-queue-7",
> + "rx-queue-0",
> + "rx-queue-1",
> + "rx-queue-2",
> + "rx-queue-3",
> + "rx-queue-4",
> + "rx-queue-5",
> + "rx-queue-6",
> + "rx-queue-7";
> resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> reset-names = "stmmaceth", "ahb";
> clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
Applied!
Thanks,
Dinh
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2026-06-09 13:16 [PATCH] arm64: dts: socfpga: agilex5: Add per-channel interrupts to gmac0 muhammad.nazim.amirul.nazle.asmade
2026-06-11 22:35 ` Dinh Nguyen
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