Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Ben Dooks <ben.dooks@codethink.co.uk>]

On 26/03/2025 17:55, Conor Dooley wrote:
> On Wed, Mar 26, 2025 at 02:20:55PM +0000, Pinkesh Vaghela wrote:
>> On Tue, Mar 25, 2025 at 7:06 PM, Emil Renner Berthing wrote:
>>> Pinkesh Vaghela wrote:
>>>> +     soc {
>>>> +             compatible = "simple-bus";
>>>> +             ranges;
>>>> +             interrupt-parent = <&plic>;
>>>> +             #address-cells = <2>;
>>>> +             #size-cells = <2>;
>>>
>>> Hi Pinkesh,
>>>
>>> Thank your for the patches!
>>>
>>> Should this not be marked dma-noncoherent to avoid having to mark each
>>> peripheral as such?
>>
>> Thanks for your feedback.
>>
>> We have not added "dma-noncoherent" because there are no DMA-capable
>> peripherals in the devicetree yet.
>> We planned to add this later when we add any DMA capable devices
>> i.e. sdhci, gmac, sata, pcie, spi.
>>
>> Do you recommend to add this property in current version?
> 
> If the bus is not cache coherent, then it should be marked as such now.

If it was like any other P550, then the DMA has to go via the cache 
coherent part of the interconnect which is a different address space
that maps into the same bus the P550 and cache controllers are on.

You just need to add the right node to map the DMA addresses and then
have the pain of what happens when there's no memory in the 32bit
address space.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html