From: Conor Dooley <conor@kernel.org>
To: Conor Dooley <conor@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Cc: Conor Dooley <conor.dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Samuel Holland <samuel.holland@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Min Lin <linmin@eswincomputing.com>,
Pritesh Patel <pritesh.patel@einfochips.com>,
Yangyu Chen <cyy@cyyself.name>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
Yu Chien Peter Lin <peterlin@andestech.com>,
Charlie Jenkins <charlie@rivosinc.com>,
Kanak Shilledar <kanakshilledar@gmail.com>,
Darshan Prajapati <darshan.prajapati@einfochips.com>,
Neil Armstrong <neil.armstrong@linaro.org>,
Heiko Stuebner <heiko@sntech.de>,
Aradhya Bhatia <a-bhatia1@ti.com>,
rafal@milecki.pl, Anup Patel <anup@brainfault.org>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: (subset) [PATCH v2 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC
Date: Fri, 21 Mar 2025 16:21:50 +0000 [thread overview]
Message-ID: <20250321-trimness-unwind-0ffafee4ac8a@spud> (raw)
In-Reply-To: <20250320105449.2094192-1-pinkesh.vaghela@einfochips.com>
From: Conor Dooley <conor.dooley@microchip.com>
On Thu, 20 Mar 2025 16:24:39 +0530, Pinkesh Vaghela wrote:
> Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> P550 CPU cluster and the first development board that uses it, the
> SiFive HiFive Premier P550.
>
> This patch series adds initial device tree and also adds ESWIN
> architecture support.
>
> [...]
Applied to riscv-cache-for-next, but too late for this merge window.
They'll be 6.16 material, the commit hashes below will change when I
rebase on top of 6.15-rc1.
[05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
https://git.kernel.org/conor/c/a506a819af37
[06/10] cache: sifive_ccache: Add ESWIN EIC7700 support
https://git.kernel.org/conor/c/4a9d4db6ba17
Thanks,
Conor.
prev parent reply other threads:[~2025-03-21 16:23 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-20 10:54 [PATCH v2 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 02/10] riscv: Add Kconfig option for ESWIN platforms Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 03/10] dt-bindings: vendor-prefixes: add eswin Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board Pinkesh Vaghela
2025-03-21 21:54 ` Rob Herring (Arm)
2025-03-20 10:54 ` [PATCH v2 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT Pinkesh Vaghela
2025-03-20 10:54 ` [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC Pinkesh Vaghela
2025-03-25 13:35 ` Emil Renner Berthing
2025-03-26 14:20 ` Pinkesh Vaghela
2025-03-26 17:55 ` Conor Dooley
2025-03-26 18:13 ` Ben Dooks
2025-03-27 9:52 ` Emil Renner Berthing
2025-03-20 10:54 ` [PATCH v2 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree Pinkesh Vaghela
2025-03-21 16:21 ` Conor Dooley [this message]
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