[PATCH v2 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC

[PATCH v2 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC

[Pinkesh Vaghela]

Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
P550 CPU cluster and the first development board that uses it, the
SiFive HiFive Premier P550.

This patch series adds initial device tree and also adds ESWIN
architecture support.

Boot-tested using intiramfs with Linux 6.14.0-rc2 on HiFive Premier
P550 board using U-Boot 2024.01 and OpenSBI 1.4.

Changes in v2:
- Added "Acked-by" tag of "Conor Dooley" for Patches 1, 2, 3, 7 and 8
- Added "Reviewed-by" tag of "Matthias Brugger" for Patch 4
- Updated MAINTAINERS file
  - Add the path for the eswin binding file
- Updated sifive,ccache0.yaml
  - Add restrictions for "cache-size" property based on the
    compatible string
- Link to v1: https://lore.kernel.org/lkml/20250311073432.4068512-1-pinkesh.vaghela@einfochips.com/

Darshan Prajapati (3):
  dt-bindings: riscv: Add SiFive P550 CPU compatible
  dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC
  dt-bindings: timer: Add ESWIN EIC7700 CLINT

Min Lin (2):
  riscv: dts: add initial support for EIC7700 SoC
  riscv: dts: eswin: add HiFive Premier P550 board device tree

Pinkesh Vaghela (2):
  riscv: Add Kconfig option for ESWIN platforms
  cache: sifive_ccache: Add ESWIN EIC7700 support

Pritesh Patel (3):
  dt-bindings: vendor-prefixes: add eswin
  dt-bindings: riscv: Add SiFive HiFive Premier P550 board
  dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC
    compatibility

 .../bindings/cache/sifive,ccache0.yaml        |  44 ++-
 .../sifive,plic-1.0.0.yaml                    |   1 +
 .../devicetree/bindings/riscv/cpus.yaml       |   1 +
 .../devicetree/bindings/riscv/eswin.yaml      |  29 ++
 .../bindings/timer/sifive,clint.yaml          |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 MAINTAINERS                                   |   8 +
 arch/riscv/Kconfig.socs                       |   6 +
 arch/riscv/boot/dts/Makefile                  |   1 +
 arch/riscv/boot/dts/eswin/Makefile            |   2 +
 .../dts/eswin/eic7700-hifive-premier-p550.dts |  29 ++
 arch/riscv/boot/dts/eswin/eic7700.dtsi        | 344 ++++++++++++++++++
 drivers/cache/sifive_ccache.c                 |   2 +
 13 files changed, 467 insertions(+), 3 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
 create mode 100644 arch/riscv/boot/dts/eswin/Makefile
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi

-- 
2.25.1

[PATCH v2 01/10] dt-bindings: riscv: Add SiFive P550 CPU compatible

[Pinkesh Vaghela]

From: Darshan Prajapati <darshan.prajapati@einfochips.com>

Update Documentation for supporting SiFive P550 based CPU

Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/riscv/cpus.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index 2c72f148a74b..3ee7468001f6 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -51,6 +51,7 @@ properties:
               - sifive,e5
               - sifive,e7
               - sifive,e71
+              - sifive,p550
               - sifive,rocket0
               - sifive,s7
               - sifive,u5
-- 
2.25.1

[PATCH v2 02/10] riscv: Add Kconfig option for ESWIN platforms

[Pinkesh Vaghela]

Create a config option to build ESWIN SoC specific resources

Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 arch/riscv/Kconfig.socs | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
index 1916cf7ba450..35594e365ca6 100644
--- a/arch/riscv/Kconfig.socs
+++ b/arch/riscv/Kconfig.socs
@@ -1,5 +1,11 @@
 menu "SoC selection"
 
+config ARCH_ESWIN
+	bool "ESWIN SoCs"
+	help
+	  This enables support for ESWIN SoC platform hardware,
+	  including the ESWIN EIC7700 SoC.
+
 config ARCH_MICROCHIP_POLARFIRE
 	def_bool ARCH_MICROCHIP
 
-- 
2.25.1

[PATCH v2 03/10] dt-bindings: vendor-prefixes: add eswin

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add new vendor string to dt bindings.
This new vendor string is used by
- ESWIN EIC770X SoC
- HiFive Premier P550 board which uses EIC7700 SoC.

Link: https://www.eswin.com/en/
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 5079ca6ce1d1..07ff140e67dc 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -490,6 +490,8 @@ patternProperties:
     description: Espressif Systems Co. Ltd.
   "^est,.*":
     description: ESTeem Wireless Modems
+  "^eswin,.*":
+    description: Beijing ESWIN Technology Group Co. Ltd.
   "^ettus,.*":
     description: NI Ettus Research
   "^eukrea,.*":
-- 
2.25.1

[PATCH v2 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

Add DT binding documentation for the ESWIN EIC7700 SoC and
HiFive Premier P550 Board

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Reviewed-by: Matthias Brugger <matthias.bgg@kernel.org>
---
 .../devicetree/bindings/riscv/eswin.yaml      | 29 +++++++++++++++++++
 MAINTAINERS                                   |  7 +++++
 2 files changed, 36 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml

diff --git a/Documentation/devicetree/bindings/riscv/eswin.yaml b/Documentation/devicetree/bindings/riscv/eswin.yaml
new file mode 100644
index 000000000000..c603c45eef22
--- /dev/null
+++ b/Documentation/devicetree/bindings/riscv/eswin.yaml
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/riscv/eswin.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ESWIN SoC-based boards
+
+maintainers:
+  - Min Lin <linmin@eswincomputing.com>
+  - Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
+  - Pritesh Patel <pritesh.patel@einfochips.com>
+
+description:
+  ESWIN SoC-based boards
+
+properties:
+  $nodename:
+    const: '/'
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - sifive,hifive-premier-p550
+          - const: eswin,eic7700
+
+additionalProperties: true
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 25c86f47353d..fc3c9191b00f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8572,6 +8572,13 @@ L:	linux-can@vger.kernel.org
 S:	Maintained
 F:	drivers/net/can/usb/esd_usb.c
 
+ESWIN DEVICETREES
+M:	Min Lin <linmin@eswincomputing.com>
+M:	Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
+M:	Pritesh Patel <pritesh.patel@einfochips.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/riscv/eswin.yaml
+
 ET131X NETWORK DRIVER
 M:	Mark Einon <mark.einon@gmail.com>
 S:	Odd Fixes
-- 
2.25.1

Re: [PATCH v2 04/10] dt-bindings: riscv: Add SiFive HiFive Premier P550 board

[Rob Herring (Arm)]

On Thu, 20 Mar 2025 16:24:43 +0530, Pinkesh Vaghela wrote:
> From: Pritesh Patel <pritesh.patel@einfochips.com>
> 
> Add DT binding documentation for the ESWIN EIC7700 SoC and
> HiFive Premier P550 Board
> 
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> Reviewed-by: Matthias Brugger <matthias.bgg@kernel.org>
> ---
>  .../devicetree/bindings/riscv/eswin.yaml      | 29 +++++++++++++++++++
>  MAINTAINERS                                   |  7 +++++
>  2 files changed, 36 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/riscv/eswin.yaml
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v2 05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility

[Pinkesh Vaghela]

From: Pritesh Patel <pritesh.patel@einfochips.com>

This cache controller is also used on the ESWIN EIC7700 SoC.
However, it have 256KB private L2 Cache and shared L3 Cache of 4MB.
So add dedicated compatible string for it.

Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 .../bindings/cache/sifive,ccache0.yaml        | 44 +++++++++++++++++--
 1 file changed, 41 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index 7e8cebe21584..579bacb66f34 100644
--- a/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -39,6 +39,7 @@ properties:
           - const: cache
       - items:
           - enum:
+              - eswin,eic7700-l3-cache
               - starfive,jh7100-ccache
               - starfive,jh7110-ccache
           - const: sifive,ccache0
@@ -55,10 +56,10 @@ properties:
     enum: [2, 3]
 
   cache-sets:
-    enum: [1024, 2048]
+    enum: [1024, 2048, 4096]
 
   cache-size:
-    const: 2097152
+    enum: [2097152, 4194304]
 
   cache-unified: true
 
@@ -89,6 +90,7 @@ allOf:
         compatible:
           contains:
             enum:
+              - eswin,eic7700-l3-cache
               - sifive,fu740-c000-ccache
               - starfive,jh7100-ccache
               - starfive,jh7110-ccache
@@ -108,6 +110,22 @@ allOf:
             Must contain entries for DirError, DataError and DataFail signals.
           maxItems: 3
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: eswin,eic7700-l3-cache
+
+    then:
+      properties:
+        cache-size:
+          const: 4194304
+
+    else:
+      properties:
+        cache-size:
+          const: 2097152
+
   - if:
       properties:
         compatible:
@@ -122,11 +140,31 @@ allOf:
         cache-sets:
           const: 2048
 
-    else:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - microchip,mpfs-ccache
+              - sifive,fu540-c000-ccache
+
+    then:
       properties:
         cache-sets:
           const: 1024
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - eswin,eic7700-l3-cache
+
+    then:
+      properties:
+        cache-sets:
+          const: 4096
+
   - if:
       properties:
         compatible:
-- 
2.25.1

[PATCH v2 06/10] cache: sifive_ccache: Add ESWIN EIC7700 support

[Pinkesh Vaghela]

This adds support for the ESWIN EIC7700 SoC which also features this
SiFive composable cache controller.

Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
---
 drivers/cache/sifive_ccache.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/cache/sifive_ccache.c b/drivers/cache/sifive_ccache.c
index 6874b72ec59d..e1a283805ea7 100644
--- a/drivers/cache/sifive_ccache.c
+++ b/drivers/cache/sifive_ccache.c
@@ -118,6 +118,8 @@ static void ccache_config_read(void)
 }
 
 static const struct of_device_id sifive_ccache_ids[] = {
+	{ .compatible = "eswin,eic7700-l3-cache",
+	  .data = (void *)(QUIRK_NONSTANDARD_CACHE_OPS) },
 	{ .compatible = "sifive,fu540-c000-ccache" },
 	{ .compatible = "sifive,fu740-c000-ccache" },
 	{ .compatible = "starfive,jh7100-ccache",
-- 
2.25.1

[PATCH v2 07/10] dt-bindings: interrupt-controller: Add ESWIN EIC7700 PLIC

[Pinkesh Vaghela]

From: Darshan Prajapati <darshan.prajapati@einfochips.com>

Add compatible string for ESWIN EIC7700 PLIC.

Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 3dfe425909d1..ea7093fde060 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -58,6 +58,7 @@ properties:
       - items:
           - enum:
               - canaan,k210-plic
+              - eswin,eic7700-plic
               - sifive,fu540-c000-plic
               - spacemit,k1-plic
               - starfive,jh7100-plic
-- 
2.25.1

[PATCH v2 08/10] dt-bindings: timer: Add ESWIN EIC7700 CLINT

[Pinkesh Vaghela]

From: Darshan Prajapati <darshan.prajapati@einfochips.com>

Add compatible string for ESWIN EIC7700 CLINT.

Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
 Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 76d83aea4e2b..eb03a0602315 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -30,6 +30,7 @@ properties:
       - items:
           - enum:
               - canaan,k210-clint       # Canaan Kendryte K210
+              - eswin,eic7700-clint     # ESWIN EIC7700
               - sifive,fu540-c000-clint # SiFive FU540
               - spacemit,k1-clint       # SpacemiT K1
               - starfive,jh7100-clint   # StarFive JH7100
-- 
2.25.1

[PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Pinkesh Vaghela]

From: Min Lin <linmin@eswincomputing.com>

Add initial support for EIC7700 SoC that uses a SiFive Quad-Core
P550 CPU cluster.

This file is expected to grow as more device drivers are added to the
kernel.

Signed-off-by: Min Lin <linmin@eswincomputing.com>
Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
---
 MAINTAINERS                            |   1 +
 arch/riscv/boot/dts/eswin/eic7700.dtsi | 344 +++++++++++++++++++++++++
 2 files changed, 345 insertions(+)
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi

diff --git a/MAINTAINERS b/MAINTAINERS
index fc3c9191b00f..2c29023c6725 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8578,6 +8578,7 @@ M:	Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
 M:	Pritesh Patel <pritesh.patel@einfochips.com>
 S:	Maintained
 F:	Documentation/devicetree/bindings/riscv/eswin.yaml
+F:	arch/riscv/boot/dts/eswin/
 
 ET131X NETWORK DRIVER
 M:	Mark Einon <mark.einon@gmail.com>
diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
new file mode 100644
index 000000000000..9cef940f07e4
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <1000000>;
+
+		cpu0: cpu@0 {
+			compatible = "sifive,p550", "riscv";
+			device_type = "cpu";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_0>;
+			reg = <0x0>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
+					       "zba", "zbb", "zicsr", "zifencei";
+			tlb-split;
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu1: cpu@1 {
+			compatible = "sifive,p550", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_1>;
+			reg = <0x1>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
+					       "zba", "zbb", "zicsr", "zifencei";
+			tlb-split;
+
+			cpu1_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu2: cpu@2 {
+			compatible = "sifive,p550", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_2>;
+			reg = <0x2>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
+					       "zba", "zbb", "zicsr", "zifencei";
+			tlb-split;
+
+			cpu2_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		cpu3: cpu@3 {
+			compatible = "sifive,p550", "riscv";
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			d-tlb-sets = <1>;
+			d-tlb-size = <32>;
+			device_type = "cpu";
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			i-tlb-sets = <1>;
+			i-tlb-size = <32>;
+			mmu-type = "riscv,sv48";
+			next-level-cache = <&l2_cache_3>;
+			reg = <0x3>;
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
+					       "zba", "zbb", "zicsr", "zifencei";
+			tlb-split;
+
+			cpu3_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				#interrupt-cells = <1>;
+				interrupt-controller;
+			};
+		};
+
+		l2_cache_0: l2-cache0 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			next-level-cache = <&ccache>;
+		};
+
+		l2_cache_1: l2-cache1 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			next-level-cache = <&ccache>;
+		};
+
+		l2_cache_2: l2-cache2 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			next-level-cache = <&ccache>;
+		};
+
+		l2_cache_3: l2-cache3 {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-sets = <512>;
+			cache-size = <262144>;
+			cache-unified;
+			next-level-cache = <&ccache>;
+		};
+	};
+
+	pmu {
+		compatible = "riscv,pmu";
+		riscv,event-to-mhpmcounters =
+				<0x00001 0x00001 0x00000001>,
+				<0x00002 0x00002 0x00000004>,
+				<0x00004 0x00006 0x00000078>,
+				<0x10009 0x10009 0x00000078>,
+				<0x10019 0x10019 0x00000078>,
+				<0x10021 0x10021 0x00000078>;
+		riscv,event-to-mhpmevent =
+				<0x00004 0x00000000 0x00000202>,
+				<0x00005 0x00000000 0x00004000>,
+				<0x00006 0x00000000 0x00002001>,
+				<0x10009 0x00000000 0x00000102>,
+				<0x10019 0x00000000 0x00001002>,
+				<0x10021 0x00000000 0x00000802>;
+		riscv,raw-event-to-mhpmcounters =
+				<0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>,
+				<0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>,
+				<0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>,
+				<0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>,
+				<0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>,
+				<0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>,
+				<0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>,
+				<0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>,
+				<0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>,
+				<0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>,
+				<0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>,
+				<0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>,
+				<0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>,
+				<0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>,
+				<0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>,
+				<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		clint: timer@2000000 {
+			compatible = "eswin,eic7700-clint", "sifive,clint0";
+			reg = <0x0 0x02000000 0x0 0x10000>;
+			interrupts-extended =
+				<&cpu0_intc 3>, <&cpu0_intc 7>,
+				<&cpu1_intc 3>, <&cpu1_intc 7>,
+				<&cpu2_intc 3>, <&cpu2_intc 7>,
+				<&cpu3_intc 3>, <&cpu3_intc 7>;
+		};
+
+		ccache: cache-controller@2010000 {
+			compatible = "eswin,eic7700-l3-cache", "sifive,ccache0", "cache";
+			reg = <0x0 0x2010000 0x0 0x4000>;
+			interrupts = <1>, <3>, <4>, <2>;
+			cache-block-size = <64>;
+			cache-level = <3>;
+			cache-sets = <4096>;
+			cache-size = <4194304>;
+			cache-unified;
+		};
+
+		plic: interrupt-controller@c000000 {
+			compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0";
+			reg = <0x0 0xc000000 0x0 0x4000000>;
+			interrupt-controller;
+			interrupts-extended =
+				<&cpu0_intc 11>, <&cpu0_intc 9>,
+				<&cpu1_intc 11>, <&cpu1_intc 9>,
+				<&cpu2_intc 11>, <&cpu2_intc 9>,
+				<&cpu3_intc 11>, <&cpu3_intc 9>;
+			riscv,ndev = <520>;
+			#address-cells = <0>;
+			#interrupt-cells = <1>;
+		};
+
+		uart0: serial@50900000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50900000 0x0 0x10000>;
+			interrupts = <100>;
+			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart1: serial@50910000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50910000 0x0 0x10000>;
+			interrupts = <101>;
+			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart2: serial@50920000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50920000 0x0 0x10000>;
+			interrupts = <102>;
+			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart3: serial@50930000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50930000 0x0 0x10000>;
+			interrupts = <103>;
+			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		uart4: serial@50940000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x50940000 0x0 0x10000>;
+			interrupts = <104>;
+			clock-frequency = <200000000>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			status = "disabled";
+		};
+
+		gpio@51600000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0x51600000 0x0 0x80>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			porta: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupts =
+					<303>, <304>, <305>, <306>, <307>, <308>, <309>,
+					<310>, <311>, <312>, <313>, <314>, <315>, <316>,
+					<317>, <318>, <319>, <320>, <321>, <322>, <323>,
+					<324>, <325>, <326>, <327>, <328>, <329>, <330>,
+					<331>, <332>, <333>, <334>;
+				gpio-controller;
+				ngpios = <32>;
+				#gpio-cells = <2>;
+			};
+
+			portb: gpio-port@1 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <1>;
+				gpio-controller;
+				ngpios = <32>;
+				#gpio-cells = <2>;
+			};
+
+			portc: gpio-port@2 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <2>;
+				gpio-controller;
+				ngpios = <32>;
+				#gpio-cells = <2>;
+			};
+
+			portd: gpio-port@3 {
+				compatible = "snps,dw-apb-gpio-port";
+				reg = <3>;
+				gpio-controller;
+				ngpios = <16>;
+				#gpio-cells = <2>;
+			};
+		};
+	};
+};
-- 
2.25.1

Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Emil Renner Berthing]

Pinkesh Vaghela wrote:
> From: Min Lin <linmin@eswincomputing.com>
>
> Add initial support for EIC7700 SoC that uses a SiFive Quad-Core
> P550 CPU cluster.
>
> This file is expected to grow as more device drivers are added to the
> kernel.
>
> Signed-off-by: Min Lin <linmin@eswincomputing.com>
> Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
> Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
> Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> Tested-by: Samuel Holland <samuel.holland@sifive.com>
> Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> ---
>  MAINTAINERS                            |   1 +
>  arch/riscv/boot/dts/eswin/eic7700.dtsi | 344 +++++++++++++++++++++++++
>  2 files changed, 345 insertions(+)
>  create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fc3c9191b00f..2c29023c6725 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -8578,6 +8578,7 @@ M:	Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
>  M:	Pritesh Patel <pritesh.patel@einfochips.com>
>  S:	Maintained
>  F:	Documentation/devicetree/bindings/riscv/eswin.yaml
> +F:	arch/riscv/boot/dts/eswin/
>
>  ET131X NETWORK DRIVER
>  M:	Mark Einon <mark.einon@gmail.com>
> diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> new file mode 100644
> index 000000000000..9cef940f07e4
> --- /dev/null
> +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> @@ -0,0 +1,344 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd.
> + */
> +
> +/dts-v1/;
> +
> +/ {
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		timebase-frequency = <1000000>;
> +
> +		cpu0: cpu@0 {
> +			compatible = "sifive,p550", "riscv";
> +			device_type = "cpu";
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <32>;
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <32>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2_cache_0>;
> +			reg = <0x0>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> +					       "zba", "zbb", "zicsr", "zifencei";
> +			tlb-split;
> +
> +			cpu0_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu1: cpu@1 {
> +			compatible = "sifive,p550", "riscv";
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <32>;
> +			device_type = "cpu";
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <32>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2_cache_1>;
> +			reg = <0x1>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> +					       "zba", "zbb", "zicsr", "zifencei";
> +			tlb-split;
> +
> +			cpu1_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu2: cpu@2 {
> +			compatible = "sifive,p550", "riscv";
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <32>;
> +			device_type = "cpu";
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <32>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2_cache_2>;
> +			reg = <0x2>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> +					       "zba", "zbb", "zicsr", "zifencei";
> +			tlb-split;
> +
> +			cpu2_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		cpu3: cpu@3 {
> +			compatible = "sifive,p550", "riscv";
> +			d-cache-block-size = <64>;
> +			d-cache-sets = <128>;
> +			d-cache-size = <32768>;
> +			d-tlb-sets = <1>;
> +			d-tlb-size = <32>;
> +			device_type = "cpu";
> +			i-cache-block-size = <64>;
> +			i-cache-sets = <128>;
> +			i-cache-size = <32768>;
> +			i-tlb-sets = <1>;
> +			i-tlb-size = <32>;
> +			mmu-type = "riscv,sv48";
> +			next-level-cache = <&l2_cache_3>;
> +			reg = <0x3>;
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> +					       "zba", "zbb", "zicsr", "zifencei";
> +			tlb-split;
> +
> +			cpu3_intc: interrupt-controller {
> +				compatible = "riscv,cpu-intc";
> +				#interrupt-cells = <1>;
> +				interrupt-controller;
> +			};
> +		};
> +
> +		l2_cache_0: l2-cache0 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <512>;
> +			cache-size = <262144>;
> +			cache-unified;
> +			next-level-cache = <&ccache>;
> +		};
> +
> +		l2_cache_1: l2-cache1 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <512>;
> +			cache-size = <262144>;
> +			cache-unified;
> +			next-level-cache = <&ccache>;
> +		};
> +
> +		l2_cache_2: l2-cache2 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <512>;
> +			cache-size = <262144>;
> +			cache-unified;
> +			next-level-cache = <&ccache>;
> +		};
> +
> +		l2_cache_3: l2-cache3 {
> +			compatible = "cache";
> +			cache-block-size = <64>;
> +			cache-level = <2>;
> +			cache-sets = <512>;
> +			cache-size = <262144>;
> +			cache-unified;
> +			next-level-cache = <&ccache>;
> +		};
> +	};
> +
> +	pmu {
> +		compatible = "riscv,pmu";
> +		riscv,event-to-mhpmcounters =
> +				<0x00001 0x00001 0x00000001>,
> +				<0x00002 0x00002 0x00000004>,
> +				<0x00004 0x00006 0x00000078>,
> +				<0x10009 0x10009 0x00000078>,
> +				<0x10019 0x10019 0x00000078>,
> +				<0x10021 0x10021 0x00000078>;
> +		riscv,event-to-mhpmevent =
> +				<0x00004 0x00000000 0x00000202>,
> +				<0x00005 0x00000000 0x00004000>,
> +				<0x00006 0x00000000 0x00002001>,
> +				<0x10009 0x00000000 0x00000102>,
> +				<0x10019 0x00000000 0x00001002>,
> +				<0x10021 0x00000000 0x00000802>;
> +		riscv,raw-event-to-mhpmcounters =
> +				<0x00000000 0x00000000 0xffffffff 0xfc0000ff 0x00000078>,
> +				<0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>,
> +				<0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>,
> +				<0x00000000 0x00000003 0xfffffffc 0x000000ff 0x00000078>,
> +				<0x00000000 0x00000004 0xffffffc0 0x000000ff 0x00000078>,
> +				<0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>,
> +				<0x00000000 0x00000006 0xfffffe00 0x110204ff 0x00000078>,
> +				<0x00000000 0x00000007 0xffffffff 0xf00000ff 0x00000078>,
> +				<0x00000000 0x00000008 0xfffffe04 0x000000ff 0x00000078>,
> +				<0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>,
> +				<0x00000000 0x0000000a 0xffffffff 0xf00000ff 0x00000078>,
> +				<0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>,
> +				<0x00000000 0x0000000c 0xfffffff0 0x000000ff 0x00000078>,
> +				<0x00000000 0x0000000d 0xffffffff 0x800000ff 0x00000078>,
> +				<0x00000000 0x0000000e 0xffffffff 0xf80000ff 0x00000078>,
> +				<0x00000000 0x0000000f 0xfffffffc 0x000000ff 0x00000078>;
> +	};
> +
> +	soc {
> +		compatible = "simple-bus";
> +		ranges;
> +		interrupt-parent = <&plic>;
> +		#address-cells = <2>;
> +		#size-cells = <2>;

Hi Pinkesh,

Thank your for the patches!

Should this not be marked dma-noncoherent to avoid having to mark each
peripheral as such?

> +
> +		clint: timer@2000000 {
> +			compatible = "eswin,eic7700-clint", "sifive,clint0";
> +			reg = <0x0 0x02000000 0x0 0x10000>;
> +			interrupts-extended =
> +				<&cpu0_intc 3>, <&cpu0_intc 7>,
> +				<&cpu1_intc 3>, <&cpu1_intc 7>,
> +				<&cpu2_intc 3>, <&cpu2_intc 7>,
> +				<&cpu3_intc 3>, <&cpu3_intc 7>;
> +		};
> +
> +		ccache: cache-controller@2010000 {
> +			compatible = "eswin,eic7700-l3-cache", "sifive,ccache0", "cache";
> +			reg = <0x0 0x2010000 0x0 0x4000>;
> +			interrupts = <1>, <3>, <4>, <2>;
> +			cache-block-size = <64>;
> +			cache-level = <3>;
> +			cache-sets = <4096>;
> +			cache-size = <4194304>;
> +			cache-unified;
> +		};
> +
> +		plic: interrupt-controller@c000000 {
> +			compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0";
> +			reg = <0x0 0xc000000 0x0 0x4000000>;
> +			interrupt-controller;
> +			interrupts-extended =
> +				<&cpu0_intc 11>, <&cpu0_intc 9>,
> +				<&cpu1_intc 11>, <&cpu1_intc 9>,
> +				<&cpu2_intc 11>, <&cpu2_intc 9>,
> +				<&cpu3_intc 11>, <&cpu3_intc 9>;
> +			riscv,ndev = <520>;
> +			#address-cells = <0>;
> +			#interrupt-cells = <1>;
> +		};
> +
> +		uart0: serial@50900000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x50900000 0x0 0x10000>;
> +			interrupts = <100>;
> +			clock-frequency = <200000000>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart1: serial@50910000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x50910000 0x0 0x10000>;
> +			interrupts = <101>;
> +			clock-frequency = <200000000>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart2: serial@50920000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x50920000 0x0 0x10000>;
> +			interrupts = <102>;
> +			clock-frequency = <200000000>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart3: serial@50930000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x50930000 0x0 0x10000>;
> +			interrupts = <103>;
> +			clock-frequency = <200000000>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		uart4: serial@50940000 {
> +			compatible = "snps,dw-apb-uart";
> +			reg = <0x0 0x50940000 0x0 0x10000>;
> +			interrupts = <104>;
> +			clock-frequency = <200000000>;
> +			reg-io-width = <4>;
> +			reg-shift = <2>;
> +			status = "disabled";
> +		};
> +
> +		gpio@51600000 {
> +			compatible = "snps,dw-apb-gpio";
> +			reg = <0x0 0x51600000 0x0 0x80>;
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +
> +			porta: gpio-port@0 {

Maybe these labels could be something like gpioA, gpioB, etc. to not be
confused with an HDMI port fx.

> +				compatible = "snps,dw-apb-gpio-port";
> +				reg = <0>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +				interrupts =
> +					<303>, <304>, <305>, <306>, <307>, <308>, <309>,
> +					<310>, <311>, <312>, <313>, <314>, <315>, <316>,
> +					<317>, <318>, <319>, <320>, <321>, <322>, <323>,
> +					<324>, <325>, <326>, <327>, <328>, <329>, <330>,
> +					<331>, <332>, <333>, <334>;
> +				gpio-controller;
> +				ngpios = <32>;
> +				#gpio-cells = <2>;
> +			};
> +
> +			portb: gpio-port@1 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				reg = <1>;
> +				gpio-controller;
> +				ngpios = <32>;
> +				#gpio-cells = <2>;
> +			};
> +
> +			portc: gpio-port@2 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				reg = <2>;
> +				gpio-controller;
> +				ngpios = <32>;
> +				#gpio-cells = <2>;
> +			};
> +
> +			portd: gpio-port@3 {
> +				compatible = "snps,dw-apb-gpio-port";
> +				reg = <3>;
> +				gpio-controller;
> +				ngpios = <16>;
> +				#gpio-cells = <2>;
> +			};
> +		};
> +	};
> +};
> --
> 2.25.1

Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Pinkesh Vaghela]

Hi Emil,

On Tue, Mar 25, 2025 at 7:06 PM, Emil Renner Berthing wrote:
> Pinkesh Vaghela wrote:
> > From: Min Lin <linmin@eswincomputing.com>
> >
> > Add initial support for EIC7700 SoC that uses a SiFive Quad-Core
> > P550 CPU cluster.
> >
> > This file is expected to grow as more device drivers are added to the
> > kernel.
> >
> > Signed-off-by: Min Lin <linmin@eswincomputing.com>
> > Co-developed-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Signed-off-by: Pritesh Patel <pritesh.patel@einfochips.com>
> > Co-developed-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
> > Signed-off-by: Darshan Prajapati <darshan.prajapati@einfochips.com>
> > Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
> > Tested-by: Samuel Holland <samuel.holland@sifive.com>
> > Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
> > ---
> >  MAINTAINERS                            |   1 +
> >  arch/riscv/boot/dts/eswin/eic7700.dtsi | 344
> > +++++++++++++++++++++++++
> >  2 files changed, 345 insertions(+)
> >  create mode 100644 arch/riscv/boot/dts/eswin/eic7700.dtsi
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > fc3c9191b00f..2c29023c6725 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -8578,6 +8578,7 @@ M:      Pinkesh Vaghela
> <pinkesh.vaghela@einfochips.com>
> >  M:   Pritesh Patel <pritesh.patel@einfochips.com>
> >  S:   Maintained
> >  F:   Documentation/devicetree/bindings/riscv/eswin.yaml
> > +F:   arch/riscv/boot/dts/eswin/
> >
> >  ET131X NETWORK DRIVER
> >  M:   Mark Einon <mark.einon@gmail.com>
> > diff --git a/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > new file mode 100644
> > index 000000000000..9cef940f07e4
> > --- /dev/null
> > +++ b/arch/riscv/boot/dts/eswin/eic7700.dtsi
> > @@ -0,0 +1,344 @@
> > +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> > +/*
> > + * Copyright (c) 2024 Beijing ESWIN Computing Technology Co., Ltd.
> > + */
> > +
> > +/dts-v1/;
> > +
> > +/ {
> > +     #address-cells = <2>;
> > +     #size-cells = <2>;
> > +
> > +     cpus {
> > +             #address-cells = <1>;
> > +             #size-cells = <0>;
> > +             timebase-frequency = <1000000>;
> > +
> > +             cpu0: cpu@0 {
> > +                     compatible = "sifive,p550", "riscv";
> > +                     device_type = "cpu";
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-sets = <128>;
> > +                     d-cache-size = <32768>;
> > +                     d-tlb-sets = <1>;
> > +                     d-tlb-size = <32>;
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-sets = <128>;
> > +                     i-cache-size = <32768>;
> > +                     i-tlb-sets = <1>;
> > +                     i-tlb-size = <32>;
> > +                     mmu-type = "riscv,sv48";
> > +                     next-level-cache = <&l2_cache_0>;
> > +                     reg = <0x0>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> > +                                            "zba", "zbb", "zicsr", "zifencei";
> > +                     tlb-split;
> > +
> > +                     cpu0_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu1: cpu@1 {
> > +                     compatible = "sifive,p550", "riscv";
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-sets = <128>;
> > +                     d-cache-size = <32768>;
> > +                     d-tlb-sets = <1>;
> > +                     d-tlb-size = <32>;
> > +                     device_type = "cpu";
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-sets = <128>;
> > +                     i-cache-size = <32768>;
> > +                     i-tlb-sets = <1>;
> > +                     i-tlb-size = <32>;
> > +                     mmu-type = "riscv,sv48";
> > +                     next-level-cache = <&l2_cache_1>;
> > +                     reg = <0x1>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> > +                                            "zba", "zbb", "zicsr", "zifencei";
> > +                     tlb-split;
> > +
> > +                     cpu1_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu2: cpu@2 {
> > +                     compatible = "sifive,p550", "riscv";
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-sets = <128>;
> > +                     d-cache-size = <32768>;
> > +                     d-tlb-sets = <1>;
> > +                     d-tlb-size = <32>;
> > +                     device_type = "cpu";
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-sets = <128>;
> > +                     i-cache-size = <32768>;
> > +                     i-tlb-sets = <1>;
> > +                     i-tlb-size = <32>;
> > +                     mmu-type = "riscv,sv48";
> > +                     next-level-cache = <&l2_cache_2>;
> > +                     reg = <0x2>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> > +                                            "zba", "zbb", "zicsr", "zifencei";
> > +                     tlb-split;
> > +
> > +                     cpu2_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             cpu3: cpu@3 {
> > +                     compatible = "sifive,p550", "riscv";
> > +                     d-cache-block-size = <64>;
> > +                     d-cache-sets = <128>;
> > +                     d-cache-size = <32768>;
> > +                     d-tlb-sets = <1>;
> > +                     d-tlb-size = <32>;
> > +                     device_type = "cpu";
> > +                     i-cache-block-size = <64>;
> > +                     i-cache-sets = <128>;
> > +                     i-cache-size = <32768>;
> > +                     i-tlb-sets = <1>;
> > +                     i-tlb-size = <32>;
> > +                     mmu-type = "riscv,sv48";
> > +                     next-level-cache = <&l2_cache_3>;
> > +                     reg = <0x3>;
> > +                     riscv,isa-base = "rv64i";
> > +                     riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "h", "sscofpmf",
> > +                                            "zba", "zbb", "zicsr", "zifencei";
> > +                     tlb-split;
> > +
> > +                     cpu3_intc: interrupt-controller {
> > +                             compatible = "riscv,cpu-intc";
> > +                             #interrupt-cells = <1>;
> > +                             interrupt-controller;
> > +                     };
> > +             };
> > +
> > +             l2_cache_0: l2-cache0 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-sets = <512>;
> > +                     cache-size = <262144>;
> > +                     cache-unified;
> > +                     next-level-cache = <&ccache>;
> > +             };
> > +
> > +             l2_cache_1: l2-cache1 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-sets = <512>;
> > +                     cache-size = <262144>;
> > +                     cache-unified;
> > +                     next-level-cache = <&ccache>;
> > +             };
> > +
> > +             l2_cache_2: l2-cache2 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-sets = <512>;
> > +                     cache-size = <262144>;
> > +                     cache-unified;
> > +                     next-level-cache = <&ccache>;
> > +             };
> > +
> > +             l2_cache_3: l2-cache3 {
> > +                     compatible = "cache";
> > +                     cache-block-size = <64>;
> > +                     cache-level = <2>;
> > +                     cache-sets = <512>;
> > +                     cache-size = <262144>;
> > +                     cache-unified;
> > +                     next-level-cache = <&ccache>;
> > +             };
> > +     };
> > +
> > +     pmu {
> > +             compatible = "riscv,pmu";
> > +             riscv,event-to-mhpmcounters =
> > +                             <0x00001 0x00001 0x00000001>,
> > +                             <0x00002 0x00002 0x00000004>,
> > +                             <0x00004 0x00006 0x00000078>,
> > +                             <0x10009 0x10009 0x00000078>,
> > +                             <0x10019 0x10019 0x00000078>,
> > +                             <0x10021 0x10021 0x00000078>;
> > +             riscv,event-to-mhpmevent =
> > +                             <0x00004 0x00000000 0x00000202>,
> > +                             <0x00005 0x00000000 0x00004000>,
> > +                             <0x00006 0x00000000 0x00002001>,
> > +                             <0x10009 0x00000000 0x00000102>,
> > +                             <0x10019 0x00000000 0x00001002>,
> > +                             <0x10021 0x00000000 0x00000802>;
> > +             riscv,raw-event-to-mhpmcounters =
> > +                             <0x00000000 0x00000000 0xffffffff 0xfc0000ff
> 0x00000078>,
> > +                             <0x00000000 0x00000001 0xffffffff 0xfffe07ff 0x00000078>,
> > +                             <0x00000000 0x00000002 0xffffffff 0xfffe00ff 0x00000078>,
> > +                             <0x00000000 0x00000003 0xfffffffc 0x000000ff
> 0x00000078>,
> > +                             <0x00000000 0x00000004 0xffffffc0 0x000000ff
> 0x00000078>,
> > +                             <0x00000000 0x00000005 0xffffffff 0xfffffdff 0x00000078>,
> > +                             <0x00000000 0x00000006 0xfffffe00 0x110204ff
> 0x00000078>,
> > +                             <0x00000000 0x00000007 0xffffffff 0xf00000ff
> 0x00000078>,
> > +                             <0x00000000 0x00000008 0xfffffe04 0x000000ff
> 0x00000078>,
> > +                             <0x00000000 0x00000009 0xffffffff 0xffffc0ff 0x00000078>,
> > +                             <0x00000000 0x0000000a 0xffffffff 0xf00000ff
> 0x00000078>,
> > +                             <0x00000000 0x0000000b 0xffffffff 0xfffffcff 0x00000078>,
> > +                             <0x00000000 0x0000000c 0xfffffff0 0x000000ff
> 0x00000078>,
> > +                             <0x00000000 0x0000000d 0xffffffff 0x800000ff
> 0x00000078>,
> > +                             <0x00000000 0x0000000e 0xffffffff 0xf80000ff
> 0x00000078>,
> > +                             <0x00000000 0x0000000f 0xfffffffc 0x000000ff
> 0x00000078>;
> > +     };
> > +
> > +     soc {
> > +             compatible = "simple-bus";
> > +             ranges;
> > +             interrupt-parent = <&plic>;
> > +             #address-cells = <2>;
> > +             #size-cells = <2>;
> 
> Hi Pinkesh,
> 
> Thank your for the patches!
> 
> Should this not be marked dma-noncoherent to avoid having to mark each
> peripheral as such?

Thanks for your feedback.

We have not added "dma-noncoherent" because there are no DMA-capable
peripherals in the devicetree yet.
We planned to add this later when we add any DMA capable devices
i.e. sdhci, gmac, sata, pcie, spi.

Do you recommend to add this property in current version?

> 
> > +
> > +             clint: timer@2000000 {
> > +                     compatible = "eswin,eic7700-clint", "sifive,clint0";
> > +                     reg = <0x0 0x02000000 0x0 0x10000>;
> > +                     interrupts-extended =
> > +                             <&cpu0_intc 3>, <&cpu0_intc 7>,
> > +                             <&cpu1_intc 3>, <&cpu1_intc 7>,
> > +                             <&cpu2_intc 3>, <&cpu2_intc 7>,
> > +                             <&cpu3_intc 3>, <&cpu3_intc 7>;
> > +             };
> > +
> > +             ccache: cache-controller@2010000 {
> > +                     compatible = "eswin,eic7700-l3-cache", "sifive,ccache0",
> "cache";
> > +                     reg = <0x0 0x2010000 0x0 0x4000>;
> > +                     interrupts = <1>, <3>, <4>, <2>;
> > +                     cache-block-size = <64>;
> > +                     cache-level = <3>;
> > +                     cache-sets = <4096>;
> > +                     cache-size = <4194304>;
> > +                     cache-unified;
> > +             };
> > +
> > +             plic: interrupt-controller@c000000 {
> > +                     compatible = "eswin,eic7700-plic", "sifive,plic-1.0.0";
> > +                     reg = <0x0 0xc000000 0x0 0x4000000>;
> > +                     interrupt-controller;
> > +                     interrupts-extended =
> > +                             <&cpu0_intc 11>, <&cpu0_intc 9>,
> > +                             <&cpu1_intc 11>, <&cpu1_intc 9>,
> > +                             <&cpu2_intc 11>, <&cpu2_intc 9>,
> > +                             <&cpu3_intc 11>, <&cpu3_intc 9>;
> > +                     riscv,ndev = <520>;
> > +                     #address-cells = <0>;
> > +                     #interrupt-cells = <1>;
> > +             };
> > +
> > +             uart0: serial@50900000 {
> > +                     compatible = "snps,dw-apb-uart";
> > +                     reg = <0x0 0x50900000 0x0 0x10000>;
> > +                     interrupts = <100>;
> > +                     clock-frequency = <200000000>;
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart1: serial@50910000 {
> > +                     compatible = "snps,dw-apb-uart";
> > +                     reg = <0x0 0x50910000 0x0 0x10000>;
> > +                     interrupts = <101>;
> > +                     clock-frequency = <200000000>;
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart2: serial@50920000 {
> > +                     compatible = "snps,dw-apb-uart";
> > +                     reg = <0x0 0x50920000 0x0 0x10000>;
> > +                     interrupts = <102>;
> > +                     clock-frequency = <200000000>;
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart3: serial@50930000 {
> > +                     compatible = "snps,dw-apb-uart";
> > +                     reg = <0x0 0x50930000 0x0 0x10000>;
> > +                     interrupts = <103>;
> > +                     clock-frequency = <200000000>;
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             uart4: serial@50940000 {
> > +                     compatible = "snps,dw-apb-uart";
> > +                     reg = <0x0 0x50940000 0x0 0x10000>;
> > +                     interrupts = <104>;
> > +                     clock-frequency = <200000000>;
> > +                     reg-io-width = <4>;
> > +                     reg-shift = <2>;
> > +                     status = "disabled";
> > +             };
> > +
> > +             gpio@51600000 {
> > +                     compatible = "snps,dw-apb-gpio";
> > +                     reg = <0x0 0x51600000 0x0 0x80>;
> > +                     #address-cells = <1>;
> > +                     #size-cells = <0>;
> > +
> > +                     porta: gpio-port@0 {
> 
> Maybe these labels could be something like gpioA, gpioB, etc. to not be
> confused with an HDMI port fx.

The gpio node labels are based on the example provided in
"snps,dw-apb-gpio.yaml" dt-binding and other dtsi.

Could you clarify more on how these labels cause confusion with HDMI
port as I don't see any example for HDMI port using name as porta, portb?

Regards,
Pinkesh

> 
> > +                             compatible = "snps,dw-apb-gpio-port";
> > +                             reg = <0>;
> > +                             interrupt-controller;
> > +                             #interrupt-cells = <2>;
> > +                             interrupts =
> > +                                     <303>, <304>, <305>, <306>, <307>, <308>, <309>,
> > +                                     <310>, <311>, <312>, <313>, <314>, <315>, <316>,
> > +                                     <317>, <318>, <319>, <320>, <321>, <322>, <323>,
> > +                                     <324>, <325>, <326>, <327>, <328>, <329>, <330>,
> > +                                     <331>, <332>, <333>, <334>;
> > +                             gpio-controller;
> > +                             ngpios = <32>;
> > +                             #gpio-cells = <2>;
> > +                     };
> > +
> > +                     portb: gpio-port@1 {
> > +                             compatible = "snps,dw-apb-gpio-port";
> > +                             reg = <1>;
> > +                             gpio-controller;
> > +                             ngpios = <32>;
> > +                             #gpio-cells = <2>;
> > +                     };
> > +
> > +                     portc: gpio-port@2 {
> > +                             compatible = "snps,dw-apb-gpio-port";
> > +                             reg = <2>;
> > +                             gpio-controller;
> > +                             ngpios = <32>;
> > +                             #gpio-cells = <2>;
> > +                     };
> > +
> > +                     portd: gpio-port@3 {
> > +                             compatible = "snps,dw-apb-gpio-port";
> > +                             reg = <3>;
> > +                             gpio-controller;
> > +                             ngpios = <16>;
> > +                             #gpio-cells = <2>;
> > +                     };
> > +             };
> > +     };
> > +};
> > --
> > 2.25.1

Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 948 bytes --]

On Wed, Mar 26, 2025 at 02:20:55PM +0000, Pinkesh Vaghela wrote:
> On Tue, Mar 25, 2025 at 7:06 PM, Emil Renner Berthing wrote:
> > Pinkesh Vaghela wrote:
> > > +     soc {
> > > +             compatible = "simple-bus";
> > > +             ranges;
> > > +             interrupt-parent = <&plic>;
> > > +             #address-cells = <2>;
> > > +             #size-cells = <2>;
> > 
> > Hi Pinkesh,
> > 
> > Thank your for the patches!
> > 
> > Should this not be marked dma-noncoherent to avoid having to mark each
> > peripheral as such?
> 
> Thanks for your feedback.
> 
> We have not added "dma-noncoherent" because there are no DMA-capable
> peripherals in the devicetree yet.
> We planned to add this later when we add any DMA capable devices
> i.e. sdhci, gmac, sata, pcie, spi.
> 
> Do you recommend to add this property in current version?

If the bus is not cache coherent, then it should be marked as such now.

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Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Ben Dooks]

On 26/03/2025 17:55, Conor Dooley wrote:
> On Wed, Mar 26, 2025 at 02:20:55PM +0000, Pinkesh Vaghela wrote:
>> On Tue, Mar 25, 2025 at 7:06 PM, Emil Renner Berthing wrote:
>>> Pinkesh Vaghela wrote:
>>>> +     soc {
>>>> +             compatible = "simple-bus";
>>>> +             ranges;
>>>> +             interrupt-parent = <&plic>;
>>>> +             #address-cells = <2>;
>>>> +             #size-cells = <2>;
>>>
>>> Hi Pinkesh,
>>>
>>> Thank your for the patches!
>>>
>>> Should this not be marked dma-noncoherent to avoid having to mark each
>>> peripheral as such?
>>
>> Thanks for your feedback.
>>
>> We have not added "dma-noncoherent" because there are no DMA-capable
>> peripherals in the devicetree yet.
>> We planned to add this later when we add any DMA capable devices
>> i.e. sdhci, gmac, sata, pcie, spi.
>>
>> Do you recommend to add this property in current version?
> 
> If the bus is not cache coherent, then it should be marked as such now.

If it was like any other P550, then the DMA has to go via the cache 
coherent part of the interconnect which is a different address space
that maps into the same bus the P550 and cache controllers are on.

You just need to add the right node to map the DMA addresses and then
have the pain of what happens when there's no memory in the 32bit
address space.


-- 
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html

Re: [PATCH v2 09/10] riscv: dts: add initial support for EIC7700 SoC

[Emil Renner Berthing]

Pinkesh Vaghela wrote:
> >
> > Hi Pinkesh,
> >
> > Thank your for the patches!
> >
> > Should this not be marked dma-noncoherent to avoid having to mark each
> > peripheral as such?
>
> Thanks for your feedback.
>
> We have not added "dma-noncoherent" because there are no DMA-capable
> peripherals in the devicetree yet.
> We planned to add this later when we add any DMA capable devices
> i.e. sdhci, gmac, sata, pcie, spi.
>
> Do you recommend to add this property in current version?

Yeah, Conor also answered this already.

> > > +             gpio@51600000 {
> > > +                     compatible = "snps,dw-apb-gpio";
> > > +                     reg = <0x0 0x51600000 0x0 0x80>;
> > > +                     #address-cells = <1>;
> > > +                     #size-cells = <0>;
> > > +
> > > +                     porta: gpio-port@0 {
> >
> > Maybe these labels could be something like gpioA, gpioB, etc. to not be
> > confused with an HDMI port fx.
>
> The gpio node labels are based on the example provided in
> "snps,dw-apb-gpio.yaml" dt-binding and other dtsi.
>
> Could you clarify more on how these labels cause confusion with HDMI
> port as I don't see any example for HDMI port using name as porta, portb?

Sure. Try git grep 'port.*:' -- '*.dts*' and you'll see that "port" labels are
used for many things that aren't GPIOs. It'll be a lot easier to scan through
the device tree and see what <&gpioA 27 0> references.

/Emil

[PATCH v2 10/10] riscv: dts: eswin: add HiFive Premier P550 board device tree

[Pinkesh Vaghela]

From: Min Lin <linmin@eswincomputing.com>

Add initial board data for HiFive Premier P550 Development board

Currently the data populated in this DT file describes the board
DRAM configuration, UART and GPIO.

Signed-off-by: Min Lin <linmin@eswincomputing.com>
Co-developed-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Signed-off-by: Pinkesh Vaghela <pinkesh.vaghela@einfochips.com>
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Tested-by: Samuel Holland <samuel.holland@sifive.com>
---
 arch/riscv/boot/dts/Makefile                  |  1 +
 arch/riscv/boot/dts/eswin/Makefile            |  2 ++
 .../dts/eswin/eic7700-hifive-premier-p550.dts | 29 +++++++++++++++++++
 3 files changed, 32 insertions(+)
 create mode 100644 arch/riscv/boot/dts/eswin/Makefile
 create mode 100644 arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts

diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
index bff887d38abe..286a9939a8cb 100644
--- a/arch/riscv/boot/dts/Makefile
+++ b/arch/riscv/boot/dts/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0
 subdir-y += allwinner
 subdir-y += canaan
+subdir-y += eswin
 subdir-y += microchip
 subdir-y += renesas
 subdir-y += sifive
diff --git a/arch/riscv/boot/dts/eswin/Makefile b/arch/riscv/boot/dts/eswin/Makefile
new file mode 100644
index 000000000000..224101ae471e
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/Makefile
@@ -0,0 +1,2 @@
+# SPDX-License-Identifier: GPL-2.0
+dtb-$(CONFIG_ARCH_ESWIN) += eic7700-hifive-premier-p550.dtb
diff --git a/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
new file mode 100644
index 000000000000..131ed1fc6b2e
--- /dev/null
+++ b/arch/riscv/boot/dts/eswin/eic7700-hifive-premier-p550.dts
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2024, Beijing ESWIN Computing Technology Co., Ltd.
+ */
+
+/dts-v1/;
+
+#include "eic7700.dtsi"
+
+/ {
+	compatible = "sifive,hifive-premier-p550", "eswin,eic7700";
+	model = "SiFive HiFive Premier P550";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
-- 
2.25.1

Re: (subset) [PATCH v2 00/10] Basic device tree support for ESWIN EIC7700 RISC-V SoC

[Conor Dooley]

From: Conor Dooley <conor.dooley@microchip.com>

On Thu, 20 Mar 2025 16:24:39 +0530, Pinkesh Vaghela wrote:
> Add support for ESWIN EIC7700 SoC consisting of SiFive Quad-Core
> P550 CPU cluster and the first development board that uses it, the
> SiFive HiFive Premier P550.
> 
> This patch series adds initial device tree and also adds ESWIN
> architecture support.
> 
> [...]

Applied to riscv-cache-for-next, but too late for this merge window.
They'll be 6.16 material, the commit hashes below will change when I
rebase on top of 6.15-rc1.

[05/10] dt-bindings: cache: sifive,ccache0: Add ESWIN EIC7700 SoC compatibility
        https://git.kernel.org/conor/c/a506a819af37
[06/10] cache: sifive_ccache: Add ESWIN EIC7700 support
        https://git.kernel.org/conor/c/4a9d4db6ba17

Thanks,
Conor.