Re: [PATCH v3 7/9] iio: adc: ti-ads1262: support triggered buffer sampling

[David Lechner <dlechner@baylibre.com>]

On 8/9/26 3:28 AM, Kurt Borja wrote:
> On Sat Aug 8, 2026 at 1:39 PM -05, David Lechner wrote:
>> On 8/7/26 10:58 PM, Kurt Borja wrote:
>>> Add triggered buffer support and a data-ready (DRDY) hardware trigger.
>>>

...

>>
>>> +	u8 tx[11] __aligned(IIO_DMA_MINALIGN);
>>> +	u8 rx[11] __aligned(IIO_DMA_MINALIGN);
>>
>> don't need second one to be aligned, they aren't independent.
> 
> Ah, I forgot this observation in the last version. These are used in a
> full-duplex transfer, wouldn't that require for both to be on its own
> cache line? I just started learning about DMA.

No. In this case, it works roughly like this...

- We fill the TX buffer before the transfer. (CPU access to memory may
  just live in the cache at this point and not actually be sent to RAM)
- We request to start the SPI transfer.
- The core SPI code flushes (or maybe I should say invalidates) the cache
  on the TX buffer. This ensures that what we wrote with the CPU available
  to DMA.
- The actual SPI transfer happens that uses DMA to access both TX and
  RX buffers. (Again, could just live in a cache and not be sent to RAM)
- The SPI core code flushes the cache on the RX buffer. This ensures
  that when the CPU reads the memory, it will see what the DMA just
  wrote.

Since there isn't a time when CPU and DMA both write to the cache line
at the same time before a flush, there is never a time we could have
an issue with stale data replacing data that had not been flushed.

It does mean that we can't update the tx buffer for the next message
until after this message is done, but we have to do that anyway.

What does cause problems is if we just had a regular unrelated variable
after this in the cache line and the driver updated it during a SPI
transfer. If this new value was just living in the CPU cache, then
when the RX flush happened, it would write over that new value with
stale data from the DMA's version of the cache.


> 
> [...]
> 
>>> +static int ads1262_enable_and_read_last(struct ads1262 *st,
>>> +					const struct iio_chan_spec *spec,
>>> +					__be32 *val)
>>> +{
>>> +	struct ads1262_channel *chan;
>>> +	int ret;
>>> +
>>> +	lockdep_assert_held(&st->xfer_lock);
>>
>> What happens if something else (e.g. gpio in the future) decides to do a
>> register write here. If it wins the race, will it unintentionally read the
>> data? So do we also need to read the stored data via command here too?
> 
> On each trigger, we are holding the lock before we enable the first
> channel, until after we read the final conversion. So we don't really
> care if there's concurrent activity in-between triggers. Am I missing
> something?
> 
The datasheet doesn't seem clear on it, so I don't know if you are
missing something or not, that is why I asked. :-)

It looks to me like the way this is working is that that when data
is ready, on the very next SPI transfer, the data is placed in the
RX buffer no matter what is in the TX buffer. So I was imagining that
if we got a DRDY interrupt, but someone happened to set a gpio output
at the same time and the gpio request won the race for the lock, then
when the gpio request was made, it would receive the RX data and trigger
the next conversion while setting the gpio output, then then what was
supposed to be receiving the data would receive I don't know what.