[PATCH 1/3] dt-bindings: Add EBDEE vendor prefix

[PATCH 1/3] dt-bindings: Add EBDEE vendor prefix

[Pufan Jin]

Shanghai Xin'yI Electronics Technology Co., Ltd. (EBDEE) manufactures
the EdgeBoard series of embedded compute cards, including Zynq
UltraScale+ based designs.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index ba2002969..9c7375d4f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -483,6 +483,8 @@ patternProperties:
     description: Zhejiang Ebang Communication Co., Ltd
   "^ebbg,.*":
     description: EBBG
+  "^ebdee,.*":
+    description: Shanghai Xin'yi Electronics Technology Co., Ltd. (EBDEE)
   "^ebs-systart,.*":
     description: EBS-SYSTART GmbH
   "^ebv,.*":
-- 
2.55.0

Re: [PATCH 1/3] dt-bindings: Add EBDEE vendor prefix

[Krzysztof Kozlowski]

On 03/10/2026 21:46, Pufan Jin wrote:
> Shanghai Xin'yI Electronics Technology Co., Ltd. (EBDEE) manufactures
> the EdgeBoard series of embedded compute cards, including Zynq
> UltraScale+ based designs.
> 

What does EBDEE mean? What is the company website?

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: Add EBDEE vendor prefix

[Pufan Jin]

On 2026/10/4 05:14, Krzysztof Kozlowski wrote:
> On 03/10/2026 21:46, Pufan Jin wrote:
>> Shanghai Xin'yI Electronics Technology Co., Ltd. (EBDEE) manufactures
>> the EdgeBoard series of embedded compute cards, including Zynq
>> UltraScale+ based designs.
>>
> What does EBDEE mean? What is the company website?
>
> Best regards,
> Krzysztof

Hi Krzysztof,


Thank you for pointing this out. "EBDEE" was an improper local acronym
derived from "EdgeBoard Developer Edition".

The actual commercial brand and manufacturer of the board is ALINX
(Shanghai Xin'yi Electronics Technology Co., Ltd.). The official
company website is:
https://www.alinx.com/

I have dropped the "ebdee" prefix and replaced it with "alinx" in v2
to properly match the manufacturer and board schematics.

Best regards,
Pufan Jin

[PATCH 2/3] dt-bindings: soc: xilinx: Add EBDEE EdgeBoard FZ3A

[Pufan Jin]

Document the EBDEE EdgeBoard FZ3A compatible for the ZynqMP board.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
index c9f99e0df..ead3a3c34 100644
--- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
+++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml
@@ -46,6 +46,7 @@ properties:
 
       - items:
           - enum:
+              - ebdee,edgeboard-fz3a
               - xlnx,zynqmp-zc1751
           - const: xlnx,zynqmp
 
-- 
2.55.0

[PATCH 3/3] arm64: zynqmp: Add EBDEE EdgeBoard FZ3A development board

[Pufan Jin]

The EBDEE EdgeBoard FZ3A is a compute carrier board built around the
MYIR MYS-CZU3EG SoM with a Zynq UltraScale+ XCZU3EG.

Enable the board peripherals wired to the PS, including Ethernet, I2C,
storage, PCIe, USB, DisplayPort, UARTs, and AMS temperature sensing.

Signed-off-by: Pufan Jin <2254650260@qq.com>
---
 arch/arm64/boot/dts/xilinx/Makefile           |   1 +
 .../xilinx/zynqmp-ebdee-edgeboard-fz3a.dts    | 272 ++++++++++++++++++
 2 files changed, 273 insertions(+)
 create mode 100644 arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts

diff --git a/arch/arm64/boot/dts/xilinx/Makefile b/arch/arm64/boot/dts/xilinx/Makefile
index 70fac0b27..e31d6ee2a 100644
--- a/arch/arm64/boot/dts/xilinx/Makefile
+++ b/arch/arm64/boot/dts/xilinx/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_ZYNQMP) += avnet-ultra96-rev1.dtb
+dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-ebdee-edgeboard-fz3a.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1232-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1254-revA.dtb
 dtb-$(CONFIG_ARCH_ZYNQMP) += zynqmp-zc1751-xm015-dc1.dtb
diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts
new file mode 100644
index 000000000..bbe9610e3
--- /dev/null
+++ b/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device tree for EBDEE EdgeBoard FZ3A carrier board
+ * populated with the MYIR MYS-CZU3EG SoM
+ * (Xilinx ZynqMP XCZU3EG, quad Cortex-A53 + PL, 2GB DDR4, 8GB eMMC).
+ *
+ * Copyright (c) 2026 Pufan Jin
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+
+/ {
+	model = "EBDEE EdgeBoard FZ3A (MYIR MYS-CZU3EG SoM)";
+	compatible = "ebdee,edgeboard-fz3a", "xlnx,zynqmp";
+
+	aliases {
+		ethernet0 = &gem3;
+		i2c0 = &i2c0;
+		i2c1 = &i2c1;
+		mmc0 = &sdhci0;
+		mmc1 = &sdhci1;
+		serial0 = &uart1;
+		serial1 = &uart0;
+		spi0 = &qspi;
+		usb0 = &usb0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	dpcon: connector {
+		compatible = "dp-connector";
+		label = "mini-DP";
+		type = "mini";
+
+		port {
+			dpcon_in: endpoint {
+				remote-endpoint = <&dpsub_dp_out>;
+			};
+		};
+	};
+
+	dp_aclk: clock-dp-aclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	gtr_refclk0: clock-gtr-ref0 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	gtr_refclk1: clock-gtr-ref1 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <26000000>;
+	};
+
+	gtr_refclk2: clock-gtr-ref2 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <27000000>;
+	};
+
+	/*
+	 * The PM firmware on this ZU3EG does not report the LPD_LSBUS
+	 * clock id as valid, so <&zynqmp_clk LPD_LSBUS> resolves to no
+	 * clock at all and drivers that require their bus clock fail to
+	 * probe.
+	 */
+	lpd_lsbus: clock-lpd-lsbus {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x7ff00000>;
+	};
+
+	vcc_3v3_pcie: regulator-pcie {
+		compatible = "regulator-fixed";
+		regulator-name = "pcie-reset";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		gpios = <&gpio 37 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-always-on;
+		regulator-boot-on;
+	};
+
+	reserved_memory: reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux_cma: cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			alloc-ranges = <0x0 0x0 0x0 0x80000000>;
+			size = <0x0 0x20000000>;	/* 512MB */
+			linux,cma-default;
+		};
+	};
+};
+
+&ams_pl {
+	status = "okay";
+};
+
+&ams_ps {
+	status = "okay";
+};
+
+&dwc3_0 {
+	dr_mode = "host";
+	maximum-speed = "super-speed";
+	snps,dis_enblslpm_quirk;
+	snps,dis_u2_susphy_quirk;
+	snps,hsphy_interface = "ulpi";
+	snps,usb3_lpm_capable;
+	status = "okay";
+};
+
+&gem3 {
+	clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
+		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
+		 <&zynqmp_clk GEM_TSU>;
+	phy-mode = "rgmii-id";
+	status = "okay";
+};
+
+&gpio {
+	status = "okay";
+};
+
+&i2c0 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c0_default>;
+	status = "okay";
+};
+
+&i2c1 {
+	clock-frequency = <400000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_i2c1_default>;
+	status = "okay";
+};
+
+&out_dp {
+	dpsub_dp_out: endpoint {
+		remote-endpoint = <&dpcon_in>;
+	};
+};
+
+&pcie {
+	phys = <&psgtr 0 PHY_TYPE_PCIE 0 0>;
+
+	status = "okay";
+};
+
+&pinctrl0 {
+	status = "okay";
+
+	pinctrl_i2c0_default: i2c0-default {
+		conf {
+			bias-pull-up;
+			groups = "i2c0_8_grp";
+		};
+
+		mux {
+			function = "i2c0";
+			groups = "i2c0_8_grp";
+		};
+	};
+
+	pinctrl_i2c1_default: i2c1-default {
+		conf {
+			bias-pull-up;
+			groups = "i2c1_8_grp";
+		};
+
+		mux {
+			function = "i2c1";
+			groups = "i2c1_8_grp";
+		};
+	};
+
+	pinctrl_usb0_default: usb0-default {
+		mux {
+			function = "usb0";
+			groups = "usb0_0_grp";
+		};
+	};
+};
+
+&psgtr {
+	clocks = <&gtr_refclk0>, <&gtr_refclk1>, <&gtr_refclk2>;
+	clock-names = "ref0", "ref1", "ref2";
+
+	status = "okay";
+};
+
+&qspi {
+	num-cs = <1>;
+	status = "okay";
+
+	flash: flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "jedec,spi-nor";
+		reg = <0x0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
+&sdhci0 {
+	no-1-8-v;
+	status = "okay";
+};
+
+&sdhci1 {
+	disable-wp;
+	no-1-8-v;
+	status = "okay";
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&usb0 {
+	phy-names = "usb3-phy";
+	phys = <&psgtr 1 PHY_TYPE_USB3 0 1>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_usb0_default>;
+	reset-gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
+
+	status = "okay";
+};
+
+&zynqmp_dpdma {
+	status = "okay";
+};
+
+&zynqmp_dpsub {
+	clocks = <&dp_aclk>,
+		 <&zynqmp_clk DP_AUDIO_REF>,
+		 <&zynqmp_clk DP_VIDEO_REF>;
+	clock-names = "dp_apb_clk", "dp_aud_clk", "dp_vtc_pixel_clk_in";
+	phy-names = "dp-phy0", "dp-phy1";
+	phys = <&psgtr 3 PHY_TYPE_DP 0 2>,
+	       <&psgtr 2 PHY_TYPE_DP 1 2>;
+	status = "okay";
+};
-- 
2.55.0

Re: [PATCH 3/3] arm64: zynqmp: Add EBDEE EdgeBoard FZ3A development board

[sashiko-bot]

Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider:
- [High] dt: zynqmp: peripherals fail to probe due to missing LPD_LSBUS clock override
- [Medium] dt: zynqmp: missing non-removable and bus-width properties for eMMC
--

commit cf011196c14a8a65736d50052e13ac3e134bc620
Author: Pufan Jin <2254650260@qq.com>
Subject: arm64: zynqmp: Add EBDEE EdgeBoard FZ3A development board

This commit adds the device tree for the EBDEE EdgeBoard FZ3A carrier
board built around the MYIR MYS-CZU3EG SoM. It enables various board
peripherals including Ethernet, I2C, eMMC, PCIe, USB, DisplayPort,
and UARTs.

> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts b/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts
> new file mode 100644
> --- /dev/null
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp-ebdee-edgeboard-fz3a.dts
[ ... ]
> +	/*
> +	 * The PM firmware on this ZU3EG does not report the LPD_LSBUS
> +	 * clock id as valid, so <&zynqmp_clk LPD_LSBUS> resolves to no
> +	 * clock at all and drivers that require their bus clock fail to
> +	 * probe.
> +	 */
> +	lpd_lsbus: clock-lpd-lsbus {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <100000000>;
> +	};
[ ... ]
> +&gem3 {
> +	clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
> +		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
> +		 <&zynqmp_clk GEM_TSU>;
> +	phy-mode = "rgmii-id";
> +	status = "okay";
> +};
[ ... ]
> +&sdhci0 {
> +	no-1-8-v;
> +	status = "okay";
> +};

[Severity: High]
Since the PM firmware's LPD_LSBUS clock is broken as noted above, will sdhci0
fail to probe without a clock override? The base device tree maps LPD_LSBUS to
sdhci0, so it seems it will inherit the broken clock if not explicitly
overridden here like it was for gem3.

[Severity: Medium]
The commit message states this board has an 8GB eMMC. Should this node
include the non-removable and bus-width = <8>; properties? Without them,
does the MMC core treat this as a removable SD card and run at a degraded
1-bit or 4-bit bus width?

[ ... ]
> +&uart0 {
> +	status = "okay";
> +};

[Severity: High]
Will this console UART also fail to probe without the lpd_lsbus clock
workaround? If it inherits the broken LPD_LSBUS clock from the base device
tree, does that result in no console output on boot?

-- 
Sashiko AI review · https://sashiko.dev/#/patchset/tencent_E21E2A584AF8EE0505C2C0809838621C8209@qq.com?part=3

Re: [PATCH 3/3] arm64: zynqmp: Add EBDEE EdgeBoard FZ3A development board

[Andrew Lunn]

> +&gem3 {
> +	clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
> +		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
> +		 <&zynqmp_clk GEM_TSU>;
> +	phy-mode = "rgmii-id";
> +	status = "okay";
> +};

No MDIO bus? No phy-handle?

   Andrew

Re: [PATCH 3/3] arm64: zynqmp: Add EBDEE EdgeBoard FZ3A development board

[Pufan Jin]

On 2026/10/5 05:25, Andrew Lunn wrote:
>> +&gem3 {
>> +	clocks = <&lpd_lsbus>, <&zynqmp_clk GEM3_REF>,
>> +		 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
>> +		 <&zynqmp_clk GEM_TSU>;
>> +	phy-mode = "rgmii-id";
>> +	status = "okay";
>> +};
> No MDIO bus? No phy-handle?
>
>     Andrew
Hi Andrew,

Thanks for the review. In v1, the mdio node and phy-handle were omitted,
relying on the Cadence MACB driver's MDIO auto-probing, which was 
incomplete.

According to the hardware schematics and live register readback, the board
has an on-board Micrel KSZ9031RNX Gigabit PHY strapped to MDIO address 1
(PHYAD[2:0] = 001b, PHY ID 0x00221620).

In v2, I have added an explicit mdio bus node with the PHY at reg = <1>:

```
     mdio {
         phy0: ethernet-phy@1 {
             reg = <1>;
             compatible = "ethernet-phy-id0022.1620";
         };
     };
```

and referenced it with phy-handle = <&phy0> under phy-mode = "rgmii-id".

This has been validated on physical hardware at 1000 Mbps Full Duplex
with zero CRC/frame errors.

Best regards,
Pufan Jin