* [RFC PATCH pre-v3 13/14] mtd: nand: add sunxi HW ECC support
From: Boris BREZILLON @ 2014-01-30 13:41 UTC (permalink / raw)
To: Maxime Ripard, Rob Landley, Russell King, David Woodhouse,
Grant Likely, Brian Norris, Jason Gunthorpe, Arnd Bergmann
Cc: Boris BREZILLON, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dev-3kdeTeqwOZ9EV1b7eY7vFQ
In-Reply-To: <1391006064-28890-1-git-send-email-b.brezillon.dev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Add HW ECC support for the sunxi NAND Flash Controller.
Signed-off-by: Boris BREZILLON <b.brezillon.dev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/mtd/nand/sunxi_nand.c | 279 +++++++++++++++++++++++++++++++++++++++--
1 file changed, 266 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
index 1014b2a..b90268f 100644
--- a/drivers/mtd/nand/sunxi_nand.c
+++ b/drivers/mtd/nand/sunxi_nand.c
@@ -163,6 +163,11 @@ struct sunxi_nand_chip_sel {
#define DEFAULT_NAME_FORMAT "nand@%d"
#define MAX_NAME_SIZE (sizeof("nand@") + 2)
+struct sunxi_nand_hw_ecc {
+ int mode;
+ struct nand_ecclayout layout;
+};
+
struct sunxi_nand_chip {
struct list_head node;
struct nand_chip nand;
@@ -402,6 +407,126 @@ static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
}
+static int sunxi_nfc_hwecc_read_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf,
+ int oob_required, int page)
+{
+ struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
+ struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecclayout *layout = ecc->layout;
+ struct sunxi_nand_hw_ecc *data = ecc->priv;
+ unsigned int max_bitflips = 0;
+ int offset;
+ u32 tmp;
+ int i;
+
+ tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
+ tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE |
+ NFC_ECC_BLOCK_SIZE);
+ tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT);
+ writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
+
+ for (i = 0; i < mtd->writesize / ecc->size; i++) {
+ if (i)
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i * ecc->size, -1);
+ chip->read_buf(mtd, NULL, chip->ecc.size);
+ offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, offset, -1);
+ while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
+ ;
+ tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD | (1 << 30);
+ writel(tmp, nfc->regs + NFC_REG_CMD);
+ sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+ memcpy_fromio(buf + (i * ecc->size), nfc->regs + NFC_RAM0_BASE,
+ chip->ecc.size);
+
+ if (readl(nfc->regs + NFC_REG_ECC_ST) & 0x1) {
+ mtd->ecc_stats.failed++;
+ } else {
+ tmp = readl(nfc->regs + NFC_REG_ECC_CNT0) & 0xff;
+ mtd->ecc_stats.corrected += tmp;
+ max_bitflips = max_t(unsigned int, max_bitflips, tmp);
+ }
+ }
+
+ if (oob_required) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
+ chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
+ }
+
+ tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
+ tmp &= ~NFC_ECC_EN;
+
+ writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
+
+ return max_bitflips;
+}
+
+static int sunxi_nfc_hwecc_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ const uint8_t *buf,
+ int oob_required)
+{
+ struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
+ struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
+ struct nand_ecc_ctrl *ecc = &chip->ecc;
+ struct nand_ecclayout *layout = ecc->layout;
+ struct sunxi_nand_hw_ecc *data = ecc->priv;
+ int offset;
+ u32 tmp;
+ int i;
+ int j;
+
+ tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
+ tmp &= ~(NFC_ECC_MODE | NFC_ECC_PIPELINE | NFC_ECC_BLOCK_SIZE |
+ NFC_ECC_BLOCK_SIZE);
+ tmp |= NFC_ECC_EN | (data->mode << NFC_ECC_MODE_SHIFT);
+
+ writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
+
+ for (i = 0; i < mtd->writesize / ecc->size; i++) {
+ if (i)
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, i * ecc->size, -1);
+
+ chip->write_buf(mtd, buf + (i * ecc->size), ecc->size);
+ offset = mtd->writesize + layout->eccpos[i * ecc->bytes] - 4;
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, offset, -1);
+ while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
+ ;
+
+ /* Fill OOB data in */
+ for (j = 0; j < 4; j++) {
+ if (oob_required) {
+ offset = layout->eccpos[i * ecc->size] - 4;
+ writeb(chip->oob_poi[offset + j],
+ nfc->regs + NFC_REG_USER_DATA_BASE + j);
+ } else {
+ writeb(0xff,
+ nfc->regs + NFC_REG_USER_DATA_BASE + j);
+ }
+ }
+
+ tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
+ NFC_ACCESS_DIR | (1 << 30);
+ writel(tmp, nfc->regs + NFC_REG_CMD);
+ sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
+ }
+
+ if (oob_required && chip->ecc.layout->oobfree[0].length > 2) {
+ chip->cmdfunc(mtd, NAND_CMD_RNDIN, mtd->writesize, -1);
+ chip->write_buf(mtd, chip->oob_poi,
+ chip->ecc.layout->oobfree[0].length - 2);
+ }
+
+ tmp = readl(nfc->regs + NFC_REG_ECC_CTL);
+ tmp &= ~(NFC_ECC_EN | NFC_ECC_PIPELINE);
+
+ writel(tmp, nfc->regs + NFC_REG_ECC_CTL);
+
+ return 0;
+}
+
static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
const struct nand_sdr_timings *timings)
{
@@ -504,6 +629,144 @@ static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
return sunxi_nand_chip_set_timings(chip, timings);
}
+static int sunxi_nand_chip_hwecc_init(struct device *dev,
+ struct sunxi_nand_chip *chip,
+ struct mtd_info *mtd,
+ struct device_node *np)
+{
+ struct nand_chip *nand = &chip->nand;
+ struct nand_ecc_ctrl *ecc = &nand->ecc;
+ struct sunxi_nand_hw_ecc *data;
+ struct nand_ecclayout *layout;
+ int nsectors;
+ int i;
+ int j;
+
+ data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ ecc->read_page = sunxi_nfc_hwecc_read_page;
+ ecc->write_page = sunxi_nfc_hwecc_write_page;
+
+ if (nand->ecc_strength_ds <= 16) {
+ nand->ecc_strength_ds = 16;
+ data->mode = 0;
+ } else if (nand->ecc_strength_ds <= 24) {
+ nand->ecc_strength_ds = 24;
+ data->mode = 1;
+ } else if (nand->ecc_strength_ds <= 28) {
+ nand->ecc_strength_ds = 28;
+ data->mode = 2;
+ } else if (nand->ecc_strength_ds <= 32) {
+ nand->ecc_strength_ds = 32;
+ data->mode = 3;
+ } else if (nand->ecc_strength_ds <= 40) {
+ nand->ecc_strength_ds = 40;
+ data->mode = 4;
+ } else if (nand->ecc_strength_ds <= 48) {
+ nand->ecc_strength_ds = 48;
+ data->mode = 5;
+ } else if (nand->ecc_strength_ds <= 56) {
+ nand->ecc_strength_ds = 56;
+ data->mode = 6;
+ } else if (nand->ecc_strength_ds <= 60) {
+ nand->ecc_strength_ds = 60;
+ data->mode = 7;
+ } else if (nand->ecc_strength_ds <= 64) {
+ nand->ecc_strength_ds = 64;
+ data->mode = 8;
+ } else {
+ dev_err(dev, "unsupported strength\n");
+ return -ENOTSUPP;
+ }
+
+ /* HW ECC always request ECC bytes for 1024 bytes blocks */
+ ecc->bytes = ((nand->ecc_strength_ds * fls(8 * 1024)) + 7) / 8;
+
+ /* HW ECC always work with even numbers of ECC bytes */
+ if (ecc->bytes % 2)
+ ecc->bytes++;
+ ecc->strength = nand->ecc_strength_ds;
+ ecc->size = nand->ecc_step_ds;
+
+ layout = &data->layout;
+ nsectors = mtd->writesize / ecc->size;
+
+ if (mtd->oobsize < ((ecc->bytes + 4) * nsectors))
+ return -EINVAL;
+
+ layout->eccbytes = (ecc->bytes * nsectors);
+
+ /*
+ * The first 2 bytes are used for BB markers.
+ * We merge the 4 user available bytes from HW ECC with this
+ * first section, hence why the + 2 operation (- 2 + 4).
+ */
+ layout->oobfree[0].length = mtd->oobsize + 2 -
+ ((ecc->bytes + 4) * nsectors);
+ layout->oobfree[0].offset = 2;
+ for (i = 0; i < nsectors; i++) {
+ /*
+ * The first 4 ECC block bytes are already counted in the first
+ * obbfree entry.
+ */
+ if (i) {
+ layout->oobfree[i].offset =
+ layout->oobfree[i - 1].offset +
+ layout->oobfree[i - 1].length +
+ ecc->bytes;
+ layout->oobfree[i].length = 4;
+ }
+
+ for (j = 0; j < ecc->bytes; j++)
+ layout->eccpos[(ecc->bytes * i) + j] =
+ layout->oobfree[i].offset +
+ layout->oobfree[i].length + j;
+ }
+
+ ecc->layout = layout;
+ ecc->priv = data;
+
+ return 0;
+}
+
+static int sunxi_nand_chip_ecc_init(struct device *dev,
+ struct sunxi_nand_chip *chip,
+ struct mtd_info *mtd,
+ struct device_node *np)
+{
+ struct nand_chip *nand = &chip->nand;
+ u32 strength;
+ u32 blk_size;
+ int ret;
+
+ nand->ecc.mode = of_get_nand_ecc_mode(np);
+
+ if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
+ nand->ecc_step_ds = blk_size;
+ nand->ecc_strength_ds = strength;
+ }
+
+ switch (nand->ecc.mode) {
+ case NAND_ECC_SOFT_BCH:
+ nand->ecc.size = nand->ecc_step_ds;
+ nand->ecc.bytes = ((nand->ecc_strength_ds *
+ fls(8 * nand->ecc_step_ds)) + 7) / 8;
+ break;
+ case NAND_ECC_HW:
+ ret = sunxi_nand_chip_hwecc_init(dev, chip, mtd, np);
+ if (ret)
+ return ret;
+ break;
+ case NAND_ECC_NONE:
+ default:
+ break;
+ }
+
+ return 0;
+}
+
static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
struct device_node *np)
{
@@ -512,8 +775,6 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
struct mtd_part_parser_data ppdata;
struct mtd_info *mtd;
struct nand_chip *nand;
- u32 strength;
- u32 blk_size;
int nsels;
int ret;
int i;
@@ -586,7 +847,6 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
nand->write_buf = sunxi_nfc_write_buf;
nand->read_byte = sunxi_nfc_read_byte;
- nand->ecc.mode = of_get_nand_ecc_mode(np);
if (of_get_nand_on_flash_bbt(np))
nand->bbt_options |= NAND_BBT_USE_FLASH;
@@ -602,16 +862,9 @@ static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
if (ret)
return ret;
- if (nand->ecc.mode == NAND_ECC_SOFT_BCH) {
- if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
- nand->ecc_step_ds = blk_size;
- nand->ecc_strength_ds = strength;
- }
-
- nand->ecc.size = nand->ecc_step_ds;
- nand->ecc.bytes = (((nand->ecc_strength_ds *
- fls(8 * nand->ecc_step_ds)) + 7) / 8);
- }
+ ret = sunxi_nand_chip_ecc_init(dev, chip, mtd, np);
+ if (ret)
+ return ret;
ret = nand_scan_tail(mtd);
if (ret)
--
1.7.9.5
^ permalink raw reply related
* Extending OPP bindings
From: Sudeep Holla @ 2014-01-30 13:43 UTC (permalink / raw)
To: devicetree@vger.kernel.org
Cc: Sudeep.Holla, linux-arm-kernel@lists.infradead.org,
linux-pm@vger.kernel.org, Lorenzo Pieralisi, Mark Rutland,
Charles Garcia-Tobin, Rob Herring, grant.likely@linaro.org,
Morten Rasmussen, Shawn Guo, mturquette@linaro.org, Mark Brown,
Nishanth Menon
Hi all,
I am looking into a couple shortcomings in the current OPP bindings and
how to address them. Feel free to add to the list if you think of any more
issues that needs to be addressed or if and how any problem mentioned below
can be handled with the existing bindings.
1. indexing: currently there are no indices in the operating-points.
It's assumed that the list is either in ascending or descending
order of frequency but not explicit in the binding document.
There are arch/arm/boot/dts/* files with opps in both styles.
Few other bindings like thermal defines bindings like
cooling-{min,max}-state assuming some order which is broken IMO.
One such use-case that came up recently[0] is the c-state latencies
which could be different for each OPP. It would be good if the
latencies are specified with the indices to OPP table to avoid
inconsistency between the bindings.
It's mainly to avoid issues due to inconsistency and duplication
on data(frequency) in multiple bindings requiring it.
Once we have indices to each on the OPP entries, then other binding
using it can refer to OPP with phandle and OPP index/specifier pairs
very similar to clock provider and consumer.
2. sharing opps: I have tried to address this issue previously[1] but unable
to conclude yet on this.
3. latencies(*): currently the latency that the CPU/memory access is unavailable
during an OPP transition is generic i.e. same from any OPP to any
other OPP. Does it make sense to have this per-OPP entry ?
4. power(*): A measure of maximum power dissipation in an OPP state.
This might be useful measure for power aware scheduling ?
(*) these are already part of P-state in ACPI(refer struct acpi_processor_px
in include/acpi/processor.h)
Apart from these I have seen on-going discussion for Samsung Exynos CPUFreq[2]
which might have some feedback for OPP bindings.
It would be good to consolidate the shortcomings found so far, that could
help in extending the current OPP bindings.
Regards,
Sudeep
[0] http://www.spinics.net/lists/arm-kernel/msg301971.html
[1] http://www.spinics.net/lists/cpufreq/msg07911.html
[2] http://www.spinics.net/lists/cpufreq/msg09169.html
^ permalink raw reply
* [RFC PATCH pre-v3 07/14] of: mtd: add documentation for the ONFI NAND timing mode property
From: Boris BREZILLON @ 2014-01-30 13:46 UTC (permalink / raw)
To: Maxime Ripard, Rob Landley, Russell King, David Woodhouse,
Grant Likely, Brian Norris, Jason Gunthorpe, Arnd Bergmann
Cc: Boris BREZILLON, devicetree, linux-doc, linux-kernel,
linux-arm-kernel, linux-mtd, dev
In-Reply-To: <1391006064-28890-1-git-send-email-b.brezillon.dev@gmail.com>
Add documentation for the ONFI NAND timing mode property.
Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
---
Changes since v2:
- fix description of the nand-timing-mode property: the mode property is
a mask containing all supported modes, each mode is encoded as a bit
position
Documentation/devicetree/bindings/mtd/nand.txt | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documentation/devicetree/bindings/mtd/nand.txt
index 0c962296..60c7112 100644
--- a/Documentation/devicetree/bindings/mtd/nand.txt
+++ b/Documentation/devicetree/bindings/mtd/nand.txt
@@ -8,3 +8,10 @@
E.g. : nand-ecc-level = <4 512>; /* 4 bits / 512 bytes */
- nand-bus-width : 8 or 16 bus width if not present 8
- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false
+- onfi,nand-timing-mode: an integer encoding the supported ONFI timing modes of
+ the NAND chip. Each supported mode is represented as a bit position (i.e. :
+ mode 0 and 1 => (1 << 0) | (1 << 1) = 0x3).
+ This is only used when the chip does not support the ONFI standard.
+ The last bit set represent the closest mode fulfilling the NAND chip timings.
+ For a full description of the different timing modes see this document:
+ www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v4] gpio: Driver for SYSCON-based GPIOs
From: Linus Walleij @ 2014-01-30 13:54 UTC (permalink / raw)
To: Alexander Shiyan, Arnd Bergmann, Olof Johansson, Kevin Hilman
Cc: linux-gpio@vger.kernel.org, Alexandre Courbot, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org
In-Reply-To: <1389632203-22806-1-git-send-email-shc_work@mail.ru>
On Mon, Jan 13, 2014 at 5:56 PM, Alexander Shiyan <shc_work@mail.ru> wrote:
> SYSCON driver was designed for using memory areas (registers)
> that are used in several subsystems. There are systems (CPUs)
> which use bits in one register for various purposes and thus
> should be handled by various kernel subsystems. This driver
> allows you to use the individual SYSCON bits as GPIOs.
> ARM CLPS711X SYSFLG1 input lines has been added as first user
> of this driver.
>
> Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Oh the pain. I am so ambivalent of this patch as it obfuscates
some stuff about the hardware that the driver should know,
while at the same time being elegant in a way.
What does the ARM SoC maintainers think about this approach?
Arnd, Olof, Kevin: is this something you'd like to see deployed?
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH] ARM: keystone: dts: disable "msmcsram" clock
From: Ivan Khoronzhuk @ 2014-01-30 13:58 UTC (permalink / raw)
To: Shilimkar, Santosh, robh+dt@kernel.org, galak@codeaurora.org
Cc: pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, linux@arm.linux.org.uk,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <448912EABC71F84BBCADFD3C67C4BE52A0B4B6@DBDE04.ent.ti.com>
Ok. I will delete node for this clock from DT and send v1
On 01/30/2014 03:25 PM, Shilimkar, Santosh wrote:
> Disable is not good idea since it conveys wrong info....
>
> Hyperlink case was different.
>
> Sent from my Android phone using TouchDown (www.nitrodesk.com)
>
> -----Original Message-----
> *From:* Khoronzhuk, Ivan [ivan.khoronzhuk@ti.com]
> *Received:* Thursday, 30 Jan 2014, 6:45am
> *To:* robh+dt@kernel.org [robh+dt@kernel.org]; galak@codeaurora.org
> [galak@codeaurora.org]
> *CC:* pawel.moll@arm.com [pawel.moll@arm.com]; mark.rutland@arm.com
> [mark.rutland@arm.com]; ijc+devicetree@hellion.org.uk
> [ijc+devicetree@hellion.org.uk]; linux@arm.linux.org.uk
> [linux@arm.linux.org.uk]; devicetree@vger.kernel.org
> [devicetree@vger.kernel.org]; linux-arm-kernel@lists.infradead.org
> [linux-arm-kernel@lists.infradead.org]; linux-kernel@vger.kernel.org
> [linux-kernel@vger.kernel.org]; Shilimkar, Santosh [santosh.shilimkar@ti.com];
> Khoronzhuk, Ivan [ivan.khoronzhuk@ti.com]
> *Subject:* [PATCH] ARM: keystone: dts: disable "msmcsram" clock
>
> At late init all unused clocks are disabled. So clocks that were not
> get before will be gated. In Keysone 2 SoC we have at least one
> necessary clock that is not used by any driver - "msmcsram". This
> clock is necessary, because it supplies the Multicore Shared Memory
> Controller (MSMC). The MSMC provides memory protection for accesses to
> the MSMC SRAM and DDR3 memory from system masters. It also manages
> traffic among mastering peripherals and the EMIF.
>
> This means that MSMC clock is always needed by SoC and cannot be gated.
> It is only one from necessary clocks that was not used by any driver.
> So to avoid its gating at late init we have to disable it in DT.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
> ---
> arch/arm/boot/dts/keystone-clocks.dtsi | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/boot/dts/keystone-clocks.dtsi
> b/arch/arm/boot/dts/keystone-clocks.dtsi
> index 2363593..e7aea2e 100644
> --- a/arch/arm/boot/dts/keystone-clocks.dtsi
> +++ b/arch/arm/boot/dts/keystone-clocks.dtsi
> @@ -332,6 +332,7 @@ clocks {
> compatible = "ti,keystone,psc-clock";
> clocks = <&chipclk1>;
> clock-output-names = "msmcsram";
> + status = "disabled";
> reg = <0x02350038 0xb00>, <0x0235001c 0x400>;
> reg-names = "control", "domain";
> domain-id = <7>;
> --
> 1.8.3.2
>
^ permalink raw reply
* Re: [RFC PATCH V3 2/4] arm64: dts: APM X-Gene PCIe device tree nodes
From: Arnd Bergmann @ 2014-01-30 14:09 UTC (permalink / raw)
To: Tanmay Inamdar
Cc: devicetree, jcm, linux-doc, Catalin Marinas, patches,
linux-kernel, Jason Gunthorpe, Grant Likely, Rob Herring,
Rob Landley, linux-pci, Bjorn Helgaas, linux-arm-kernel
In-Reply-To: <1390599168-13150-3-git-send-email-tinamdar@apm.com>
On Friday 24 January 2014, Tanmay Inamdar wrote:
> + pcie3: pcie@1f500000 {
> + reg-names = "csr", "cfg";
> + ranges = <0x01000000 0x0 0x00000000 0xa0 0x00000000 0x0 0x00010000 /* mem */
> + 0x02000000 0x0 0x10000000 0xa0 0x10000000 0x0 0x80000000>; /* io */
The two comments are wrong for this instance.
Arnd
^ permalink raw reply
* Re: [RFC PATCH V3 1/4] pci: APM X-Gene PCIe controller driver
From: Arnd Bergmann @ 2014-01-30 14:16 UTC (permalink / raw)
To: Tanmay Inamdar
Cc: Bjorn Helgaas, Jason Gunthorpe, Grant Likely, Rob Herring,
Catalin Marinas, Rob Landley, linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, patches-qTEPVZfXA3Y,
jcm-H+wXaHxf7aLQT0dZR+AlfA
In-Reply-To: <1390599168-13150-2-git-send-email-tinamdar-qTEPVZfXA3Y@public.gmane.org>
On Friday 24 January 2014, Tanmay Inamdar wrote:
> +static void xgene_pcie_fixup_bridge(struct pci_dev *dev)
> +{
> + int i;
> +
> + /* Hide the PCI host BARs from the kernel as their content doesn't
> + * fit well in the resource management
> + */
> + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
> + dev->resource[i].start = dev->resource[i].end = 0;
> + dev->resource[i].flags = 0;
> + }
> + dev_info(&dev->dev, "Hiding X-Gene pci host bridge resources %s\n",
> + pci_name(dev));
> +}
> +DECLARE_PCI_FIXUP_HEADER(XGENE_PCIE_VENDORID, XGENE_PCIE_DEVICEID,
> + xgene_pcie_fixup_bridge);
Shouldn't this be gone now that the host bridge is correctly shown
at the domain root?
> +static int xgene_pcie_setup(int nr, struct pci_sys_data *sys)
> +{
> + struct xgene_pcie_port *pp = sys->private_data;
> + struct resource *io = &pp->realio;
> +
> + io->start = sys->domain * SZ_64K;
> + io->end = io->start + SZ_64K;
> + io->flags = pp->io.res.flags;
> + io->name = "PCI IO";
> + pci_ioremap_io(io->start, pp->io.res.start);
> +
> + pci_add_resource_offset(&sys->resources, io, sys->io_offset);
> + sys->mem_offset = pp->mem.res.start - pp->mem.pci_addr;
> + pci_add_resource_offset(&sys->resources, &pp->mem.res,
> + sys->mem_offset);
> + return 1;
> +}
Thanks for bringing back the I/O space handling.
You don't seem to set sys->io_offset anywhere, but each of the
ports listed in your DT starts a local bus I/O register range
at port 0.
AFAICT, you need to add (somewhere)
sys->io_offset = pp->realio.start - pp->io.pci_addr;
but there could be something else missing. You clearly haven't
tested if the I/O space actually works.
If you want to try out the I/O space, I'd suggest using an Intel
e1000 network card, which has both memory and i/o space. There
is a patch at http://www.spinics.net/lists/linux-pci/msg27684.html
that lets you check the I/O registers on it, or you can go
through /dev/port from user space.
I also haven't seen your patch that adds pci_ioremap_io() for
arm64. It would be helpful to keep it in the same patch
series, since it won't build without this patch.
Arnd
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^ permalink raw reply
* Re: [RFC PATCH V3 0/4] APM X-Gene PCIe controller
From: Arnd Bergmann @ 2014-01-30 14:17 UTC (permalink / raw)
To: Tanmay Inamdar
Cc: devicetree, jcm, linux-doc, Catalin Marinas, patches,
linux-kernel, Jason Gunthorpe, Grant Likely, Rob Herring,
Rob Landley, linux-pci, Bjorn Helgaas, linux-arm-kernel
In-Reply-To: <1390599168-13150-1-git-send-email-tinamdar@apm.com>
On Friday 24 January 2014, Tanmay Inamdar wrote:
> This patch adds support for AppliedMicro X-Gene PCIe host controller. The
> driver is tested on X-Gene platform with different gen1/2/3 PCIe endpoint
> cards.
>
> X-Gene PCIe controller driver has depedency on the pcie arch support for
> arm64. The arm64 pcie arch support is not yet part of mainline Linux kernel
> and approach for arch support is under discussion with arm64 maintainers.
> The reference patch can be found here --> https://lkml.org/lkml/2013/10/23/244
>
> If someone wishes to test PCIe on X-Gene, arch support patch must be applied
> before the patches in this patch set.
This is starting to look really good now. I have a few small comments left,
otherwise it can get merged. As mentioned in one of my review comments, it
would be good to have the arch support patch posted along with the driver.
Arnd
^ permalink raw reply
* [PATCH] dt-bindings: add vendor-prefix for neonode
From: Heiko Stübner @ 2014-01-30 14:18 UTC (permalink / raw)
To: Rob Herring
Cc: Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
From: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
Neonode Inc. is the Manufacturer of the zforce infraread touchscreens
used in a lot of ebook readers and supported by the zforce_ts driver.
Signed-off-by: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
---
Dmitry, the input maintainer, didn't want to carry the vendor-prefix
addition [0], therefore add it separately.
[0] http://permalink.gmane.org/gmane.linux.kernel.input/33887
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index edbb8d8..32a60a9 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -47,6 +47,7 @@ maxim Maxim Integrated Products
microchip Microchip Technology Inc.
mosaixtech Mosaix Technologies, Inc.
national National Semiconductor
+neonode Neonode Inc.
nintendo Nintendo
nvidia NVIDIA
nxp NXP Semiconductors
--
1.7.10.4
--
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the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [RFC PATCH V3 0/4] APM X-Gene PCIe controller
From: Arnd Bergmann @ 2014-01-30 14:21 UTC (permalink / raw)
To: Tanmay Inamdar
Cc: Bjorn Helgaas, Dann Frazier, Jason Gunthorpe, Grant Likely,
Rob Herring, Catalin Marinas, Rob Landley,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm,
linux-doc, linux-kernel@vger.kernel.org, patches, Jon Masters
In-Reply-To: <CACoXjc=LSrLK=kd9GJoHWJovVDC+TfH2bZO-2Ht9jMoBrL9eag@mail.gmail.com>
On Thursday 30 January 2014, Tanmay Inamdar wrote:
> >
> > When you repost, please make sure you fix whatever problem is
> > preventing your email from appearing on the vger mailing lists. I
> > won't apply things that haven't appeared on the linux-pci list,
> > because that list is the opportunity for other people to review them.
> >
> You are absolutely right. If the patches are not reaching mailing
> list, they should not appear on archive list as well. However I am
> seeing my patches recorded on archives. So I am not sure if they are
> actually getting dropped on linux-pci or any other mailing list.
>
> http://www.spinics.net/lists/linux-pci/msg28198.html
> http://article.gmane.org/gmane.linux.kernel.pci/28442/match=tanmay+inamdar
Very strange. I can also confirm that I received the patches through
the linux-arm-kernel and devicetree mailing lists without problems.
Arnd
^ permalink raw reply
* [PATCH 4/5] Documentation: devicetree: sja1000: add reg-io-width binding
From: Florian Vaussard @ 2014-01-30 14:29 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde
Cc: linux-can, netdev, linux-kernel, florian.vaussard, Grant Likely,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree
In-Reply-To: <1391092168-21246-1-git-send-email-florian.vaussard@epfl.ch>
Add the reg-io-width property to describe the width of the memory
accesses.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
---
Documentation/devicetree/bindings/net/can/sja1000.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt
index f2105a4..b4a6d53 100644
--- a/Documentation/devicetree/bindings/net/can/sja1000.txt
+++ b/Documentation/devicetree/bindings/net/can/sja1000.txt
@@ -12,6 +12,10 @@ Required properties:
Optional properties:
+- reg-io-width : Specify the size (in bytes) of the IO accesses that
+ should be performed on the device. Valid value is 1, 2 or 4.
+ Default to 1 (8 bits).
+
- nxp,external-clock-frequency : Frequency of the external oscillator
clock in Hz. Note that the internal clock frequency used by the
SJA1000 is half of that value. If not specified, a default value
--
1.8.1.2
^ permalink raw reply related
* [PATCH 5/5] can: sja1000: of: add read/write routines for 8, 16 and 32-bit register access
From: Florian Vaussard @ 2014-01-30 14:29 UTC (permalink / raw)
To: Wolfgang Grandegger, Marc Kleine-Budde
Cc: linux-can, netdev, linux-kernel, florian.vaussard, Grant Likely,
Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree
In-Reply-To: <1391092168-21246-1-git-send-email-florian.vaussard@epfl.ch>
Add routines for 8, 16 and 32-bit access like in sja1000_platform.c
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
---
drivers/net/can/sja1000/sja1000_of_platform.c | 41 +++++++++++++++++++++++----
1 file changed, 36 insertions(+), 5 deletions(-)
diff --git a/drivers/net/can/sja1000/sja1000_of_platform.c b/drivers/net/can/sja1000/sja1000_of_platform.c
index 8ebb4af..a9a0696 100644
--- a/drivers/net/can/sja1000/sja1000_of_platform.c
+++ b/drivers/net/can/sja1000/sja1000_of_platform.c
@@ -55,17 +55,39 @@ MODULE_LICENSE("GPL v2");
#define SJA1000_OFP_CAN_CLOCK (16000000 / 2)
-static u8 sja1000_ofp_read_reg(const struct sja1000_priv *priv, int reg)
+static u8 sja1000_ofp_read_reg8(const struct sja1000_priv *priv, int reg)
{
return ioread8(priv->reg_base + reg);
}
-static void sja1000_ofp_write_reg(const struct sja1000_priv *priv,
- int reg, u8 val)
+static void sja1000_ofp_write_reg8(const struct sja1000_priv *priv,
+ int reg, u8 val)
{
iowrite8(val, priv->reg_base + reg);
}
+static u8 sja1000_ofp_read_reg16(const struct sja1000_priv *priv, int reg)
+{
+ return ioread8(priv->reg_base + reg * 2);
+}
+
+static void sja1000_ofp_write_reg16(const struct sja1000_priv *priv,
+ int reg, u8 val)
+{
+ iowrite8(val, priv->reg_base + reg * 2);
+}
+
+static u8 sja1000_ofp_read_reg32(const struct sja1000_priv *priv, int reg)
+{
+ return ioread8(priv->reg_base + reg * 4);
+}
+
+static void sja1000_ofp_write_reg32(const struct sja1000_priv *priv,
+ int reg, u8 val)
+{
+ iowrite8(val, priv->reg_base + reg * 4);
+}
+
static int sja1000_ofp_remove(struct platform_device *ofdev)
{
struct net_device *dev = platform_get_drvdata(ofdev);
@@ -121,8 +143,17 @@ static int sja1000_ofp_probe(struct platform_device *ofdev)
priv = netdev_priv(dev);
- priv->read_reg = sja1000_ofp_read_reg;
- priv->write_reg = sja1000_ofp_write_reg;
+ of_property_read_u32(np, "reg-io-width", &prop);
+ if (prop == 4) {
+ priv->read_reg = sja1000_ofp_read_reg32;
+ priv->write_reg = sja1000_ofp_write_reg32;
+ } else if (prop == 2) {
+ priv->read_reg = sja1000_ofp_read_reg16;
+ priv->write_reg = sja1000_ofp_write_reg16;
+ } else {
+ priv->read_reg = sja1000_ofp_read_reg8;
+ priv->write_reg = sja1000_ofp_write_reg8;
+ }
err = of_property_read_u32(np, "nxp,external-clock-frequency", &prop);
if (!err)
--
1.8.1.2
^ permalink raw reply related
* Re: [PATCH] ARM: keystone: dts: disable "msmcsram" clock
From: Santosh Shilimkar @ 2014-01-30 14:31 UTC (permalink / raw)
To: Ivan Khoronzhuk
Cc: robh+dt@kernel.org, galak@codeaurora.org, pawel.moll@arm.com,
mark.rutland@arm.com, ijc+devicetree@hellion.org.uk,
linux@arm.linux.org.uk, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
In-Reply-To: <52EA5A8F.7070107@ti.com>
On Thursday 30 January 2014 08:58 AM, Ivan Khoronzhuk wrote:
> Ok. I will delete node for this clock from DT and send v1
>
Sorry for the html reply first of all. That node should never have
been actually added since the clock is not suppose to be touched even
in low power states. Change log should say something like this ...
"MSMC is the coherency interconnect and all the coherent masters are
connected to it including devices which are not under Linux OS control.
MSMC clock should not be toched even in low power states."
So drop the clock node o.w without 'clk_ignore_unused' will disable
the clock leading to system stall.
I wil try get these in rc's since its a bug fix
Regards,
Santosh
^ permalink raw reply
* Re: [PATCH V2 0/4] misc: xgene: Add support for APM X-Gene SoC Queue Manager/Traffic Manager
From: Arnd Bergmann @ 2014-01-30 14:35 UTC (permalink / raw)
To: Ravi Patel
Cc: devicetree@vger.kernel.org, Jon Masters, Greg KH, patches@apm.com,
linux-kernel, Loc Ho, netdev, Keyur Chudgar, davem,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <CAN1v_Ps9U=yjG-G40FK+L9SLaAQp7s8j9mg9DNoiGwqjMiGtiQ@mail.gmail.com>
On Tuesday 28 January 2014, Ravi Patel wrote:
> On Tue, Jan 14, 2014 at 7:15 AM, Arnd Bergmann <arnd@arndb.de> wrote:
-
> > For the DT binding, I would suggest using something along the lines of
> > what we have for clocks, pinctrl and dmaengine. OMAP doesn't use this
> > (yet), but now would be a good time to standardize it. The QMTM node
> > should define a "#mailbox-cells" property that indicates how many
> > 32-bit cells a qmtm needs to describe the connection between the
> > controller and the slave. My best guess is that this would be hardcoded
> > to <3>, using two cells for a 64-bit FIFO bus address, and a 32-bit cell
> > for the slave-id signal number. All other parameters that you have in
> > the big table in the qmtm driver at the moment can then get moved into
> > the slave drivers, as they are constant per type of slave. This will
> > simplify the QMTM driver.
> >
> > In the slave, you should have a "mailboxes" property with a phandle
> > to the qmtm followed by the three cells to identify the actual
> > queue. If it's possible that a device uses more than one rx and
> > one tx queue, we also need a "mailbox-names" property to identify
> > the individual queues.
>
> We explored on DT bindings suggestion given by you. We have come
> up with a sample DT binding for how it will look like. Herewith we have
> provided the same. Would you please review and give us your
> comments before we change our driver and DTS file to accomodate it?
>
> Sample DTS node for QM:
> qmlite: qmtm@17030000 {
> compatible = "apm,xgene-qmtm-lite";
I would use 'mailbox@17030000' as the node name, as the name part
is supposed to be descriptive of the function rather than the implemention.
> reg = <0x0 0x17030000 0x0 0x10000>,
> <0x0 0x10000000 0x0 0x400000>;
> interrupts = <0x0 0x40 0x4>,
> <0x0 0x3c 0x4>;
> status = "ok";
> #clock-cells = <1>;
> clocks = <&qmlclk 0>;
> #mailbox-cells = <3>;
> };
The #clock-cells seems misplaced here, unless this is also a clock
provider, which I don't think it is.
>
> Sample DTS node for Ethernet:
> menet: ethernet@17020000 {
> compatible = "apm,xgene-enet";
> status = "disabled";
> reg = <0x0 0x17020000 0x0 0x30>,
> <0x0 0x17020000 0x0 0x10000>,
> <0x0 0x17020000 0x0 0x20>;
Unrelated, but it seems strange to have three register sets of different
sizes at the same offset.
> mailboxes = <&qmlite 0x0 0x1000002c 0x0000>,
> <&qmlite 0x0 0x10000052 0x0020>,
> <&qmlite 0x0 0x10000060 0x0f00>
> mailbox-names = "mb-tx", "mb-fp", "mb-rx";
I would leave out the "mb-" part of the strings and just document them
as "tx", "rx" and "fp".
> interrupts = <0x0 0x38 0x4>,
> <0x0 0x39 0x4>,
> <0x0 0x3a 0x4>;
> #clock-cells = <1>;
Same comment about #clock-cells here.
> clocks = <ð8clk 0>;
> local-mac-address = <0x0 0x11 0x3a 0x8a 0x5a 0x78>;
> max-frame-size = <0x233a>;
> phyid = <3>;
> phy-mode = "rgmii";
> };
>
> The mailbox node in DTS has following format:
> mailbox = <&parent 'higher 32 bit bus address' 'lower 32 bit bus
> address' 'signal id'>
sounds good.
> Ethernet driver will call following function in platform_probe:
> mailbox_get(dev, "mb-tx");
> mailbox_get API will return the the context of allocated and configured mailbox.
> For now, mailbox_get API will be implemented in xgene QMTM driver.
> Eventually when mailbox framework in Linux will be standardized, we
> will use it instead.
Ok.
> > For the in-kernel interfaces, we should probably start a conversation
> > with the owners of the mailbox drivers to get a common API, for now
> > I'd suggest you just leave it as it is, and only adapt for the new
> > binding.
>
> Sure. For now we will put our driver mostly as is in the
> drivers/mailbox. Can you please help us identify the owners of the
> mailbox drivers? As you suggested, we can start conversation with them
> to define common in kernel APIs.
Please talk to "Suman Anna" <s-anna@ti.com> for the TI part and Rob
Herring <robh@kernel.org> for pl320. The pl320 driver was written
by Mark Langsdorf for Calxeda, but I don't have an updated email
address for him and assume that the calxeda address is no longer
functional.
Arnd
^ permalink raw reply
* Re: [RFC PATCH pre-v3 08/14] mtd: nand: add sunxi NAND flash controller support
From: Russell King - ARM Linux @ 2014-01-30 14:36 UTC (permalink / raw)
To: Boris BREZILLON
Cc: Maxime Ripard, Rob Landley, David Woodhouse, Grant Likely,
Brian Norris, Jason Gunthorpe, Arnd Bergmann, devicetree,
linux-doc, linux-kernel, linux-arm-kernel, linux-mtd, dev
In-Reply-To: <1391089176-8147-1-git-send-email-b.brezillon.dev@gmail.com>
Boris,
Can you please explain to me why you mail all your patches _To:_ me?
As in, why do I appear in the To: line of all the patches you seem to
mail out, whether or not they're relevant to me. I see this very
regularly from you - virtually all patches I see on the LAKML mailing
list from you are always sent To: me as well.
Take for instance this one. It doesn't match up with anything in
MAINTAINERS for me. It doesn't even touch a file that I've touched.
Yet somehow you think that I should be in the To: header.
Being in the To: header means that you expect the recipient to do
something with your email. The Cc: header is to circulate copies of
your email to people who may be interested.
I'm neither for this stuff. Please stop this.
Thanks.
On Thu, Jan 30, 2014 at 02:39:36PM +0100, Boris BREZILLON wrote:
> Add support for the sunxi NAND Flash Controller (NFC).
>
> Signed-off-by: Boris BREZILLON <b.brezillon.dev@gmail.com>
> ---
> Hello,
>
> This version fixes a bug in the R/B GPIO config block.
> The timing config order is now respected, but I'll wait for Jason work
> regarding timing config in NAND core code before posting the 3rd version
> of this series.
>
> Best Regards,
>
> Boris
>
> Changes since v2:
> - fix R/B GPIO retrieval/config bug
> - fix timings configuration order (set mode 0 -> scan -> set best supported
> mode)
>
> drivers/mtd/nand/Kconfig | 6 +
> drivers/mtd/nand/Makefile | 1 +
> drivers/mtd/nand/sunxi_nand.c | 758 +++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 765 insertions(+)
> create mode 100644 drivers/mtd/nand/sunxi_nand.c
>
> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
> index 93ae6a6..784dd42 100644
> --- a/drivers/mtd/nand/Kconfig
> +++ b/drivers/mtd/nand/Kconfig
> @@ -510,4 +510,10 @@ config MTD_NAND_XWAY
> Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
> to the External Bus Unit (EBU).
>
> +config MTD_NAND_SUNXI
> + tristate "Support for NAND on Allwinner SoCs"
> + depends on ARCH_SUNXI
> + help
> + Enables support for NAND Flash chips on Allwinner SoCs.
> +
> endif # MTD_NAND
> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
> index bbea7a6..e3b4a34 100644
> --- a/drivers/mtd/nand/Makefile
> +++ b/drivers/mtd/nand/Makefile
> @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
> obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
> obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
> obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
> +obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>
> nand-objs := nand_base.o nand_bbt.o
> diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
> new file mode 100644
> index 0000000..1014b2a
> --- /dev/null
> +++ b/drivers/mtd/nand/sunxi_nand.c
> @@ -0,0 +1,758 @@
> +/*
> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev@gmail.com>
> + *
> + * Derived from:
> + * https://github.com/yuq/sunxi-nfc-mtd
> + * Copyright (C) 2013 Qiang Yu <yuq825@gmail.com>
> + *
> + * https://github.com/hno/Allwinner-Info
> + * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
> + *
> + * Copyright (C) 2013 Dmitriy B. <rzk333@gmail.com>
> + * Copyright (C) 2013 Sergey Lapin <slapin@ossfans.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/dma-mapping.h>
> +#include <linux/slab.h>
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/platform_device.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/of_gpio.h>
> +#include <linux/of_mtd.h>
> +#include <linux/mtd/mtd.h>
> +#include <linux/mtd/nand.h>
> +#include <linux/mtd/partitions.h>
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/dmaengine.h>
> +#include <linux/gpio.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +
> +#define NFC_REG_CTL 0x0000
> +#define NFC_REG_ST 0x0004
> +#define NFC_REG_INT 0x0008
> +#define NFC_REG_TIMING_CTL 0x000C
> +#define NFC_REG_TIMING_CFG 0x0010
> +#define NFC_REG_ADDR_LOW 0x0014
> +#define NFC_REG_ADDR_HIGH 0x0018
> +#define NFC_REG_SECTOR_NUM 0x001C
> +#define NFC_REG_CNT 0x0020
> +#define NFC_REG_CMD 0x0024
> +#define NFC_REG_RCMD_SET 0x0028
> +#define NFC_REG_WCMD_SET 0x002C
> +#define NFC_REG_IO_DATA 0x0030
> +#define NFC_REG_ECC_CTL 0x0034
> +#define NFC_REG_ECC_ST 0x0038
> +#define NFC_REG_DEBUG 0x003C
> +#define NFC_REG_ECC_CNT0 0x0040
> +#define NFC_REG_ECC_CNT1 0x0044
> +#define NFC_REG_ECC_CNT2 0x0048
> +#define NFC_REG_ECC_CNT3 0x004c
> +#define NFC_REG_USER_DATA_BASE 0x0050
> +#define NFC_REG_SPARE_AREA 0x00A0
> +#define NFC_RAM0_BASE 0x0400
> +#define NFC_RAM1_BASE 0x0800
> +
> +/*define bit use in NFC_CTL*/
> +#define NFC_EN (1 << 0)
> +#define NFC_RESET (1 << 1)
> +#define NFC_BUS_WIDYH (1 << 2)
> +#define NFC_RB_SEL (1 << 3)
> +#define NFC_CE_SEL (7 << 24)
> +#define NFC_CE_CTL (1 << 6)
> +#define NFC_CE_CTL1 (1 << 7)
> +#define NFC_PAGE_SIZE (0xf << 8)
> +#define NFC_SAM (1 << 12)
> +#define NFC_RAM_METHOD (1 << 14)
> +#define NFC_DEBUG_CTL (1 << 31)
> +
> +/*define bit use in NFC_ST*/
> +#define NFC_RB_B2R (1 << 0)
> +#define NFC_CMD_INT_FLAG (1 << 1)
> +#define NFC_DMA_INT_FLAG (1 << 2)
> +#define NFC_CMD_FIFO_STATUS (1 << 3)
> +#define NFC_STA (1 << 4)
> +#define NFC_NATCH_INT_FLAG (1 << 5)
> +#define NFC_RB_STATE0 (1 << 8)
> +#define NFC_RB_STATE1 (1 << 9)
> +#define NFC_RB_STATE2 (1 << 10)
> +#define NFC_RB_STATE3 (1 << 11)
> +
> +/*define bit use in NFC_INT*/
> +#define NFC_B2R_INT_ENABLE (1 << 0)
> +#define NFC_CMD_INT_ENABLE (1 << 1)
> +#define NFC_DMA_INT_ENABLE (1 << 2)
> +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
> + NFC_CMD_INT_ENABLE | \
> + NFC_DMA_INT_ENABLE)
> +
> +
> +/*define bit use in NFC_CMD*/
> +#define NFC_CMD_LOW_BYTE (0xff << 0)
> +#define NFC_CMD_HIGH_BYTE (0xff << 8)
> +#define NFC_ADR_NUM (0x7 << 16)
> +#define NFC_SEND_ADR (1 << 19)
> +#define NFC_ACCESS_DIR (1 << 20)
> +#define NFC_DATA_TRANS (1 << 21)
> +#define NFC_SEND_CMD1 (1 << 22)
> +#define NFC_WAIT_FLAG (1 << 23)
> +#define NFC_SEND_CMD2 (1 << 24)
> +#define NFC_SEQ (1 << 25)
> +#define NFC_DATA_SWAP_METHOD (1 << 26)
> +#define NFC_ROW_AUTO_INC (1 << 27)
> +#define NFC_SEND_CMD3 (1 << 28)
> +#define NFC_SEND_CMD4 (1 << 29)
> +#define NFC_CMD_TYPE (3 << 30)
> +
> +/* define bit use in NFC_RCMD_SET*/
> +#define NFC_READ_CMD (0xff << 0)
> +#define NFC_RANDOM_READ_CMD0 (0xff << 8)
> +#define NFC_RANDOM_READ_CMD1 (0xff << 16)
> +
> +/*define bit use in NFC_WCMD_SET*/
> +#define NFC_PROGRAM_CMD (0xff << 0)
> +#define NFC_RANDOM_WRITE_CMD (0xff << 8)
> +#define NFC_READ_CMD0 (0xff << 16)
> +#define NFC_READ_CMD1 (0xff << 24)
> +
> +/*define bit use in NFC_ECC_CTL*/
> +#define NFC_ECC_EN (1 << 0)
> +#define NFC_ECC_PIPELINE (1 << 3)
> +#define NFC_ECC_EXCEPTION (1 << 4)
> +#define NFC_ECC_BLOCK_SIZE (1 << 5)
> +#define NFC_RANDOM_EN (1 << 9)
> +#define NFC_RANDOM_DIRECTION (1 << 10)
> +#define NFC_ECC_MODE_SHIFT 12
> +#define NFC_ECC_MODE (0xf << NFC_ECC_MODE_SHIFT)
> +#define NFC_RANDOM_SEED (0x7fff << 16)
> +
> +
> +
> +enum sunxi_nand_rb_type {
> + RB_NONE,
> + RB_NATIVE,
> + RB_GPIO,
> +};
> +
> +struct sunxi_nand_rb {
> + enum sunxi_nand_rb_type type;
> + union {
> + int gpio;
> + int nativeid;
> + } info;
> +};
> +
> +struct sunxi_nand_chip_sel {
> + u8 cs;
> + struct sunxi_nand_rb rb;
> +};
> +
> +#define DEFAULT_NAME_FORMAT "nand@%d"
> +#define MAX_NAME_SIZE (sizeof("nand@") + 2)
> +
> +struct sunxi_nand_chip {
> + struct list_head node;
> + struct nand_chip nand;
> + struct mtd_info mtd;
> + char default_name[MAX_NAME_SIZE];
> + unsigned long clk_rate;
> + int selected;
> + int nsels;
> + struct sunxi_nand_chip_sel sels[0];
> +};
> +
> +static inline struct sunxi_nand_chip *to_sunxi_nand(struct mtd_info *mtd)
> +{
> + return container_of(mtd, struct sunxi_nand_chip, mtd);
> +}
> +
> +struct sunxi_nfc {
> + struct nand_hw_control controller;
> + void __iomem *regs;
> + int irq;
> + struct clk *ahb_clk;
> + struct clk *sclk;
> + unsigned long assigned_cs;
> + unsigned long clk_rate;
> + struct list_head chips;
> + struct completion complete;
> +};
> +
> +static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
> +{
> + return container_of(ctrl, struct sunxi_nfc, controller);
> +}
> +
> +static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
> +{
> + struct sunxi_nfc *nfc = dev_id;
> + u32 st = readl(nfc->regs + NFC_REG_ST);
> + u32 ien = readl(nfc->regs + NFC_REG_INT);
> +
> + if (!(ien & st))
> + return IRQ_NONE;
> +
> + if ((ien & st) == ien)
> + complete(&nfc->complete);
> +
> + writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
> + writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
> + unsigned int timeout_ms)
> +{
> + init_completion(&nfc->complete);
> +
> + writel(flags, nfc->regs + NFC_REG_INT);
> + if (!timeout_ms)
> + wait_for_completion(&nfc->complete);
> + else if (!wait_for_completion_timeout(&nfc->complete,
> + msecs_to_jiffies(timeout_ms)))
> + return -ETIMEDOUT;
> +
> + return 0;
> +}
> +
> +static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + struct sunxi_nand_rb *rb;
> + unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
> + int ret;
> +
> + if (sunxi_nand->selected < 0)
> + return 0;
> +
> + rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
> +
> + switch (rb->type) {
> + case RB_NATIVE:
> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
> + (NFC_RB_STATE0 << rb->info.nativeid));
> + if (ret)
> + break;
> +
> + sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
> + (NFC_RB_STATE0 << rb->info.nativeid));
> + break;
> + case RB_GPIO:
> + ret = gpio_get_value(rb->info.gpio);
> + break;
> + case RB_NONE:
> + default:
> + ret = 0;
> + dev_err(&mtd->dev, "cannot check R/B NAND status!");
> + break;
> + }
> +
> + return ret;
> +}
> +
> +static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct nand_chip *nand = &sunxi_nand->nand;
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + struct sunxi_nand_chip_sel *sel;
> + u32 ctl;
> +
> + if (chip > 0 && chip >= sunxi_nand->nsels)
> + return;
> +
> + if (chip == sunxi_nand->selected)
> + return;
> +
> + ctl = readl(nfc->regs + NFC_REG_CTL) &
> + ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
> +
> + if (chip >= 0) {
> + sel = &sunxi_nand->sels[chip];
> +
> + ctl |= (sel->cs << 24) | NFC_EN |
> + (((nand->page_shift - 10) & 0xf) << 8);
> + if (sel->rb.type == RB_NONE) {
> + nand->dev_ready = NULL;
> + } else {
> + nand->dev_ready = sunxi_nfc_dev_ready;
> + if (sel->rb.type == RB_NATIVE)
> + ctl |= (sel->rb.info.nativeid << 3);
> + }
> +
> + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
> +
> + if (nfc->clk_rate != sunxi_nand->clk_rate) {
> + clk_set_rate(nfc->sclk, sunxi_nand->clk_rate);
> + nfc->clk_rate = sunxi_nand->clk_rate;
> + }
> + }
> +
> + writel(ctl, nfc->regs + NFC_REG_CTL);
> +
> + sunxi_nand->selected = chip;
> +}
> +
> +static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + int cnt;
> + int offs = 0;
> + u32 tmp;
> +
> + while (len > offs) {
> + cnt = len - offs;
> + if (cnt > 1024)
> + cnt = 1024;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> + writel(cnt, nfc->regs + NFC_REG_CNT);
> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
> + writel(tmp, nfc->regs + NFC_REG_CMD);
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> + if (buf)
> + memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
> + cnt);
> + offs += cnt;
> + }
> +}
> +
> +static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
> + int len)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + int cnt;
> + int offs = 0;
> + u32 tmp;
> +
> + while (len > offs) {
> + cnt = len - offs;
> + if (cnt > 1024)
> + cnt = 1024;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> + writel(cnt, nfc->regs + NFC_REG_CNT);
> + memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
> + NFC_ACCESS_DIR;
> + writel(tmp, nfc->regs + NFC_REG_CMD);
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> + offs += cnt;
> + }
> +}
> +
> +static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
> +{
> + uint8_t ret;
> +
> + sunxi_nfc_read_buf(mtd, &ret, 1);
> +
> + return ret;
> +}
> +
> +static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
> + unsigned int ctrl)
> +{
> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
> + u32 tmp;
> +
> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
> + ;
> +
> + if (ctrl & NAND_CTRL_CHANGE) {
> + tmp = readl(nfc->regs + NFC_REG_CTL);
> + if (ctrl & NAND_NCE)
> + tmp |= NFC_CE_CTL;
> + else
> + tmp &= ~NFC_CE_CTL;
> + writel(tmp, nfc->regs + NFC_REG_CTL);
> + }
> +
> + if (dat == NAND_CMD_NONE)
> + return;
> +
> + if (ctrl & NAND_CLE) {
> + writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
> + } else {
> + writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
> + writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
> + }
> +
> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
> +}
> +
> +static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
> + const struct nand_sdr_timings *timings)
> +{
> + u32 min_clk_period = 0;
> +
> + /* T1 <=> tCLS */
> + if (timings->tCLS_min > min_clk_period)
> + min_clk_period = timings->tCLS_min;
> +
> + /* T2 <=> tCLH */
> + if (timings->tCLH_min > min_clk_period)
> + min_clk_period = timings->tCLH_min;
> +
> + /* T3 <=> tCS */
> + if (timings->tCS_min > min_clk_period)
> + min_clk_period = timings->tCS_min;
> +
> + /* T4 <=> tCH */
> + if (timings->tCH_min > min_clk_period)
> + min_clk_period = timings->tCH_min;
> +
> + /* T5 <=> tWP */
> + if (timings->tWP_min > min_clk_period)
> + min_clk_period = timings->tWP_min;
> +
> + /* T6 <=> tWH */
> + if (timings->tWH_min > min_clk_period)
> + min_clk_period = timings->tWH_min;
> +
> + /* T7 <=> tALS */
> + if (timings->tALS_min > min_clk_period)
> + min_clk_period = timings->tALS_min;
> +
> + /* T8 <=> tDS */
> + if (timings->tDS_min > min_clk_period)
> + min_clk_period = timings->tDS_min;
> +
> + /* T9 <=> tDH */
> + if (timings->tDH_min > min_clk_period)
> + min_clk_period = timings->tDH_min;
> +
> + /* T10 <=> tRR */
> + if (timings->tRR_min > (min_clk_period * 3))
> + min_clk_period = (timings->tRR_min + 2) / 3;
> +
> + /* T11 <=> tALH */
> + if (timings->tALH_min > min_clk_period)
> + min_clk_period = timings->tALH_min;
> +
> + /* T12 <=> tRP */
> + if (timings->tRP_min > min_clk_period)
> + min_clk_period = timings->tRP_min;
> +
> + /* T13 <=> tREH */
> + if (timings->tREH_min > min_clk_period)
> + min_clk_period = timings->tREH_min;
> +
> + /* T14 <=> tRC */
> + if (timings->tRC_min > (min_clk_period * 2))
> + min_clk_period = (timings->tRC_min + 1) / 2;
> +
> + /* T15 <=> tWC */
> + if (timings->tWC_min > (min_clk_period * 2))
> + min_clk_period = (timings->tWC_min + 1) / 2;
> +
> +
> + /* min_clk_period = (NAND-clk-period * 2) */
> + if (min_clk_period < 1000)
> + min_clk_period = 1000;
> +
> + min_clk_period /= 1000;
> + chip->clk_rate = (2 * 1000000000) / min_clk_period;
> +
> + /* TODO: configure T16-T19 */
> +
> + return 0;
> +}
> +
> +static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
> + struct device_node *np)
> +{
> + const struct nand_sdr_timings *timings;
> + int ret;
> +
> + ret = onfi_get_async_timing_mode(&chip->nand);
> + if (ret == ONFI_TIMING_MODE_UNKNOWN) {
> + ret = of_get_nand_onfi_timing_mode(np);
> + if (ret < 0)
> + return ret;
> + }
> +
> + ret = fls(ret);
> + if (!ret)
> + return -EINVAL;
> +
> + timings = onfi_async_timing_mode_to_sdr_timings(ret - 1);
> + if (IS_ERR(timings))
> + return PTR_ERR(timings);
> +
> + return sunxi_nand_chip_set_timings(chip, timings);
> +}
> +
> +static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
> + struct device_node *np)
> +{
> + const struct nand_sdr_timings *timings;
> + struct sunxi_nand_chip *chip;
> + struct mtd_part_parser_data ppdata;
> + struct mtd_info *mtd;
> + struct nand_chip *nand;
> + u32 strength;
> + u32 blk_size;
> + int nsels;
> + int ret;
> + int i;
> + u32 tmp;
> +
> + if (!of_get_property(np, "reg", &nsels))
> + return -EINVAL;
> +
> + nsels /= sizeof(u32);
> + if (!nsels)
> + return -EINVAL;
> +
> + chip = devm_kzalloc(dev,
> + sizeof(*chip) +
> + (nsels * sizeof(struct sunxi_nand_chip_sel)),
> + GFP_KERNEL);
> + if (!chip)
> + return -ENOMEM;
> +
> + chip->nsels = nsels;
> + chip->selected = -1;
> +
> + for (i = 0; i < nsels; i++) {
> + ret = of_property_read_u32_index(np, "reg", i, &tmp);
> + if (ret)
> + return ret;
> +
> + if (tmp > 7)
> + return -EINVAL;
> +
> + if (test_and_set_bit(tmp, &nfc->assigned_cs))
> + return -EINVAL;
> +
> + chip->sels[i].cs = tmp;
> +
> + if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
> + tmp < 2) {
> + chip->sels[i].rb.type = RB_NATIVE;
> + chip->sels[i].rb.info.nativeid = tmp;
> + } else {
> + ret = of_get_named_gpio(np, "rb-gpios", i);
> + if (ret >= 0) {
> + tmp = ret;
> + chip->sels[i].rb.type = RB_GPIO;
> + chip->sels[i].rb.info.gpio = tmp;
> + ret = devm_gpio_request(dev, tmp, "nand-rb");
> + if (ret)
> + return ret;
> +
> + ret = gpio_direction_input(tmp);
> + if (ret)
> + return ret;
> + } else {
> + chip->sels[i].rb.type = RB_NONE;
> + }
> + }
> + }
> +
> + timings = onfi_async_timing_mode_to_sdr_timings(0);
> + if (IS_ERR(timings))
> + return PTR_ERR(timings);
> +
> + ret = sunxi_nand_chip_set_timings(chip, timings);
> +
> + nand = &chip->nand;
> + nand->controller = &nfc->controller;
> + nand->select_chip = sunxi_nfc_select_chip;
> + nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
> + nand->read_buf = sunxi_nfc_read_buf;
> + nand->write_buf = sunxi_nfc_write_buf;
> + nand->read_byte = sunxi_nfc_read_byte;
> +
> + nand->ecc.mode = of_get_nand_ecc_mode(np);
> + if (of_get_nand_on_flash_bbt(np))
> + nand->bbt_options |= NAND_BBT_USE_FLASH;
> +
> + mtd = &chip->mtd;
> + mtd->priv = nand;
> + mtd->owner = THIS_MODULE;
> +
> + ret = nand_scan_ident(mtd, nsels, NULL);
> + if (ret)
> + return ret;
> +
> + ret = sunxi_nand_chip_init_timings(chip, np);
> + if (ret)
> + return ret;
> +
> + if (nand->ecc.mode == NAND_ECC_SOFT_BCH) {
> + if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
> + nand->ecc_step_ds = blk_size;
> + nand->ecc_strength_ds = strength;
> + }
> +
> + nand->ecc.size = nand->ecc_step_ds;
> + nand->ecc.bytes = (((nand->ecc_strength_ds *
> + fls(8 * nand->ecc_step_ds)) + 7) / 8);
> + }
> +
> + ret = nand_scan_tail(mtd);
> + if (ret)
> + return ret;
> +
> + if (of_property_read_string(np, "nand-name", &mtd->name)) {
> + snprintf(chip->default_name, MAX_NAME_SIZE,
> + DEFAULT_NAME_FORMAT, chip->sels[i].cs);
> + mtd->name = chip->default_name;
> + }
> +
> + ppdata.of_node = np;
> + ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
> + if (!ret)
> + return ret;
> +
> + list_add_tail(&chip->node, &nfc->chips);
> +
> + return 0;
> +}
> +
> +static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
> +{
> + struct device_node *np = dev->of_node;
> + struct device_node *nand_np;
> + int nchips = of_get_child_count(np);
> + int ret;
> +
> + if (nchips > 8)
> + return -EINVAL;
> +
> + for_each_child_of_node(np, nand_np) {
> + ret = sunxi_nand_chip_init(dev, nfc, nand_np);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int sunxi_nfc_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct resource *r;
> + struct sunxi_nfc *nfc;
> + int ret;
> +
> + nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
> + if (!nfc) {
> + dev_err(dev, "failed to allocate NFC struct\n");
> + return -ENOMEM;
> + }
> +
> + spin_lock_init(&nfc->controller.lock);
> + init_waitqueue_head(&nfc->controller.wq);
> + INIT_LIST_HEAD(&nfc->chips);
> +
> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + nfc->regs = devm_ioremap_resource(dev, r);
> + if (IS_ERR(nfc->regs)) {
> + dev_err(dev, "failed to remap iomem\n");
> + return PTR_ERR(nfc->regs);
> + }
> +
> + nfc->irq = platform_get_irq(pdev, 0);
> + if (nfc->irq < 0) {
> + dev_err(dev, "failed to retrieve irq\n");
> + return nfc->irq;
> + }
> +
> + nfc->ahb_clk = devm_clk_get(dev, "ahb_clk");
> + if (IS_ERR(nfc->ahb_clk)) {
> + dev_err(dev, "failed to retrieve ahb_clk\n");
> + return PTR_ERR(nfc->ahb_clk);
> + }
> +
> + ret = clk_prepare_enable(nfc->ahb_clk);
> + if (ret)
> + return ret;
> +
> + nfc->sclk = devm_clk_get(dev, "sclk");
> + if (IS_ERR(nfc->sclk)) {
> + dev_err(dev, "failed to retrieve nand_clk\n");
> + ret = PTR_ERR(nfc->sclk);
> + goto out_ahb_clk_unprepare;
> + }
> +
> + ret = clk_prepare_enable(nfc->sclk);
> + if (ret)
> + goto out_ahb_clk_unprepare;
> +
> + /* Reset NFC */
> + writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RESET,
> + nfc->regs + NFC_REG_CTL);
> + while (readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)
> + ;
> +
> + writel(0, nfc->regs + NFC_REG_INT);
> + ret = devm_request_irq(dev, nfc->irq, sunxi_nfc_interrupt,
> + 0, "sunxi-nand", nfc);
> + if (ret)
> + goto out_sclk_unprepare;
> +
> + platform_set_drvdata(pdev, nfc);
> +
> + writel(0x100, nfc->regs + NFC_REG_TIMING_CTL);
> + writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG);
> +
> + ret = sunxi_nand_chips_init(dev, nfc);
> + if (ret) {
> + dev_err(dev, "failed to init nand chips\n");
> + goto out_sclk_unprepare;
> + }
> +
> + return 0;
> +
> +out_sclk_unprepare:
> + clk_disable_unprepare(nfc->sclk);
> +out_ahb_clk_unprepare:
> + clk_disable_unprepare(nfc->ahb_clk);
> +
> + return ret;
> +}
> +
> +static const struct of_device_id sunxi_nfc_ids[] = {
> + { .compatible = "allwinner,sun4i-nand" },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
> +
> +static struct platform_driver sunxi_nfc_driver = {
> + .driver = {
> + .name = "sunxi_nand",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(sunxi_nfc_ids),
> + },
> + .probe = sunxi_nfc_probe,
> +};
> +module_platform_driver(sunxi_nfc_driver);
> +
> +MODULE_LICENSE("GPL v2");
> +MODULE_AUTHOR("Boris BREZILLON");
> +MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
> +MODULE_ALIAS("platform:sunxi_nfc");
> --
> 1.7.9.5
>
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* Re: [PATCH 4/5] Documentation: devicetree: sja1000: add reg-io-width binding
From: Rob Herring @ 2014-01-30 14:45 UTC (permalink / raw)
To: Florian Vaussard
Cc: Wolfgang Grandegger, Marc Kleine-Budde,
linux-can-u79uwXL29TY76Z2rM5mHXA, netdev,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Grant Likely, Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell,
Kumar Gala, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1391092168-21246-5-git-send-email-florian.vaussard-p8DiymsW2f8@public.gmane.org>
On Thu, Jan 30, 2014 at 8:29 AM, Florian Vaussard
<florian.vaussard-p8DiymsW2f8@public.gmane.org> wrote:
> Add the reg-io-width property to describe the width of the memory
> accesses.
>
> Cc: Grant Likely <grant.likely-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Signed-off-by: Florian Vaussard <florian.vaussard-p8DiymsW2f8@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
> Documentation/devicetree/bindings/net/can/sja1000.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/net/can/sja1000.txt b/Documentation/devicetree/bindings/net/can/sja1000.txt
> index f2105a4..b4a6d53 100644
> --- a/Documentation/devicetree/bindings/net/can/sja1000.txt
> +++ b/Documentation/devicetree/bindings/net/can/sja1000.txt
> @@ -12,6 +12,10 @@ Required properties:
>
> Optional properties:
>
> +- reg-io-width : Specify the size (in bytes) of the IO accesses that
> + should be performed on the device. Valid value is 1, 2 or 4.
> + Default to 1 (8 bits).
> +
> - nxp,external-clock-frequency : Frequency of the external oscillator
> clock in Hz. Note that the internal clock frequency used by the
> SJA1000 is half of that value. If not specified, a default value
> --
> 1.8.1.2
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* [PATCH 0/4] ARM:sti: Add STiD127 platform and board support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, patrice.chotard, alexandre.torgue,
maxime.coquelin
From: Patrice Chotard <patrice.chotard@st.com>
This patch-set adds basic support for STMicroelectronics STiD127
with B2112 board support. STiD127 is dual-core ARM Cortex-A9 CPU
to function as a cable modem or in combination with a back end
as a gateway set top box.
Alexandre TORGUE (4):
ARM: STi: add stid127 soc support
pinctrl: st: add stid127 support
ARM: dts: Add support of STid127 Soc.
ARM: dts: add B2112 board support
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
arch/arm/mach-sti/board-dt.c | 6 +
drivers/pinctrl/pinctrl-st.c | 25 ++++
7 files changed, 474 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi
--
1.7.9.5
^ permalink raw reply
* [PATCH 1/4] ARM: STi: add stid127 soc support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-F5mvAk5X5gdBDgjK7y7TUQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Linus Walleij, Grant Likely,
Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: maxime.coquelin-qxv4g6HH51o, alexandre.torgue-qxv4g6HH51o,
patrice.chotard-qxv4g6HH51o, Giuseppe Cavallaro
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
From: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
This patch adds support to STiD127 SoC.
The main adaptation is the L2 cache way size compare to STiH41x SoCs.
Signed-off-by: alexandre torgue <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
---
arch/arm/mach-sti/board-dt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-sti/board-dt.c b/arch/arm/mach-sti/board-dt.c
index 1217fb5..be018a9 100644
--- a/arch/arm/mach-sti/board-dt.c
+++ b/arch/arm/mach-sti/board-dt.c
@@ -9,6 +9,7 @@
#include <linux/irq.h>
#include <linux/of_platform.h>
+#include <linux/of.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach/arch.h>
@@ -18,6 +19,10 @@ void __init stih41x_l2x0_init(void)
{
u32 way_size = 0x4;
u32 aux_ctrl;
+
+ if (of_machine_is_compatible("st,stid127"))
+ way_size = 0x3;
+
/* may be this can be encoded in macros like BIT*() */
aux_ctrl = (0x1 << L2X0_AUX_CTRL_SHARE_OVERRIDE_SHIFT) |
(0x1 << L2X0_AUX_CTRL_DATA_PREFETCH_SHIFT) |
@@ -36,6 +41,7 @@ static void __init stih41x_machine_init(void)
static const char *stih41x_dt_match[] __initdata = {
"st,stih415",
"st,stih416",
+ "st,stid127",
NULL
};
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/4] pinctrl: st: add stid127 support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, patrice.chotard, alexandre.torgue,
maxime.coquelin
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add STid127 PIOs (psouth, pwest, peast) in pinctrl.
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
drivers/pinctrl/pinctrl-st.c | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9cadc68..01227de 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -336,6 +336,27 @@ static const struct st_pctl_data stih416_data = {
.alt = 0, .oe = 40, .pu = 50, .od = 60, .rt = 100,
};
+/* STid127 data */
+static const struct st_pctl_data stid127_data = {
+ .rt_style = st_retime_style_dedicated,
+ /* reuse stih416 delays as they are identical */
+ .input_delays = stih416_delays,
+ .ninput_delays = 14,
+ /* reuse stih416 delays as they are identical */
+ .output_delays = stih416_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 8, .pu = 10, .od = 12, .rt = 14,
+};
+
+static const struct st_pctl_data stid127_psouth_data = {
+ .rt_style = st_retime_style_dedicated,
+ .input_delays = stid127_delays,
+ .ninput_delays = 14,
+ .output_delays = stid127_delays,
+ .noutput_delays = 14,
+ .alt = 0, .oe = 7, .pu = 9, .od = 11, .rt = 13,
+};
+
/* Low level functions.. */
static inline int st_gpio_bank(int gpio)
{
@@ -1264,6 +1285,10 @@ static struct of_device_id st_pctl_of_match[] = {
{ .compatible = "st,stih416-rear-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-fe-pinctrl", .data = &stih416_data},
{ .compatible = "st,stih416-fvdp-lite-pinctrl", .data = &stih416_data},
+ { .compatible = "st,stid127-pwest-pinctrl", .data = &stid127_data },
+ { .compatible = "st,stid127-psouth-pinctrl",
+ .data = &stid127_psouth_data },
+ { .compatible = "st,stid127-peast-pinctrl", .data = &stid127_data },
{ /* sentinel */ }
};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 3/4] ARM: dts: Add support of STid127 Soc.
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: Giuseppe Cavallaro, patrice.chotard, alexandre.torgue,
maxime.coquelin
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
The STid127 integrates all harware components to function as a cable modem
or, in combination with a back end device, as a Gateway set top boxe.
Supported devices:
-UART0
-UART2
Signed-off-by: alexandre torgue <alexandre.torgue@st.com>
---
arch/arm/boot/dts/stid127-clock.dtsi | 31 ++++
arch/arm/boot/dts/stid127-pinctrl.dtsi | 245 ++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stid127.dtsi | 130 +++++++++++++++++
3 files changed, 406 insertions(+)
create mode 100644 arch/arm/boot/dts/stid127-clock.dtsi
create mode 100644 arch/arm/boot/dts/stid127-pinctrl.dtsi
create mode 100644 arch/arm/boot/dts/stid127.dtsi
diff --git a/arch/arm/boot/dts/stid127-clock.dtsi b/arch/arm/boot/dts/stid127-clock.dtsi
new file mode 100644
index 0000000..c6cafa9
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-clock.dtsi
@@ -0,0 +1,31 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics (R&D) Limited
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ clocks {
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: arm_periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ };
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ CLK_IC_LP_HD: clockgenA0@29 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <100000000>;
+ clock-output-names = "CLK_IC_LP_HD";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127-pinctrl.dtsi b/arch/arm/boot/dts/stid127-pinctrl.dtsi
new file mode 100644
index 0000000..3fa66f3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-pinctrl.dtsi
@@ -0,0 +1,245 @@
+/*
+ * Copyright (C) 2012 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "st-pincfg.h"
+/ {
+ aliases {
+ gpio0 = &PIO0;
+ gpio1 = &PIO1;
+ gpio2 = &PIO2;
+ gpio3 = &PIO3;
+ gpio4 = &PIO4;
+ gpio5 = &PIO5;
+ gpio6 = &PIO6;
+ gpio7 = &PIO7;
+ gpio8 = &PIO8;
+ gpio9 = &PIO9;
+ gpio10 = &PIO10;
+ gpio11 = &PIO11;
+ gpio12 = &PIO12;
+ gpio13 = &PIO13;
+ gpio14 = &PIO14;
+ gpio15 = &PIO15;
+ gpio16 = &PIO16;
+ gpio17 = &PIO17;
+ gpio18 = &PIO18;
+ gpio19 = &PIO19;
+ gpio20 = &PIO20;
+ gpio21 = &PIO21;
+ gpio22 = &PIO22;
+
+ };
+
+ soc {
+ pin-controller-pwest {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-pwest-pinctrl";
+ st,syscfg = <&syscfg_pwest>;
+ ranges = <0 0xfebe0000 0x8000>;
+
+ PIO0: gpio@febe0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 149 0>;
+ st,bank-name = "PIO0";
+ };
+ PIO1: gpio@febe1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 150 0>;
+ st,bank-name = "PIO1";
+ };
+ PIO2: gpio@febe2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 151 0>;
+ st,bank-name = "PIO2";
+ };
+ PIO3: gpio@febe3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 152 0>;
+ st,bank-name = "PIO3";
+ };
+ PIO4: gpio@febe4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 153 0>;
+ st,bank-name = "PIO4";
+ };
+ PIO5: gpio@febe5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 154 0>;
+ st,bank-name = "PIO5";
+ };
+ PIO6: gpio@febe6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 155 0>;
+ st,bank-name = "PIO6";
+ };
+ PIO7: gpio@febe7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 156 0>;
+ st,bank-name = "PIO7";
+ };
+ uart0 {
+ pinctrl_uart0: uart0 {
+ st,pins {
+ tx = <&PIO3 2 ALT2 OUT>;
+ rx = <&PIO3 0 ALT2 IN>;
+ };
+ };
+ };
+
+ };
+
+ pin-controller-psouth {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-psouth-pinctrl";
+ st,syscfg = <&syscfg_psouth>;
+ ranges = <0 0xfef70000 0x7000>;
+
+ PIO8: gpio@fef70000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0 0x100>;
+ interrupts = <0 157 0>;
+ st,bank-name = "PIO8";
+ };
+ PIO9: gpio@fef71000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 158 0>;
+ st,bank-name = "PIO9";
+ };
+ PIO10: gpio@fef72000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 159 0>;
+ st,bank-name = "PIO10";
+ };
+ PIO11: gpio@fef73000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 160 0>;
+ st,bank-name = "PIO11";
+ };
+ PIO12: gpio@fef74000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 161 0>;
+ st,bank-name = "PIO12";
+ };
+ PIO13: gpio@fef75000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 162 0>;
+ st,bank-name = "PIO13";
+ };
+ PIO14: gpio@fef76000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 163 0>;
+ st,bank-name = "PIO14";
+ };
+ };
+
+ pin-controller-peast {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "st,stid127-peast-pinctrl";
+ st,syscfg = <&syscfg_peast>;
+ ranges = <0 0xfebc0000 0x8000>;
+
+ PIO15: gpio@febc0000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = < 0 0x100>;
+ interrupts = <0 164 0>;
+ st,bank-name = "PIO15";
+ };
+ PIO16: gpio@febc1000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x1000 0x100>;
+ interrupts = <0 165 0>;
+ st,bank-name = "PIO16";
+ };
+ PIO17: gpio@febc2000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x2000 0x100>;
+ interrupts = <0 166 0>;
+ st,bank-name = "PIO17";
+ };
+ PIO18: gpio@febc3000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x3000 0x100>;
+ interrupts = <0 167 0>;
+ st,bank-name = "PIO18";
+ };
+ PIO19: gpio@febc4000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x4000 0x100>;
+ interrupts = <0 168 0>;
+ st,bank-name = "PIO19";
+ };
+ PIO20: gpio@febc5000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x5000 0x100>;
+ interrupts = <0 169 0>;
+ st,bank-name = "PIO20";
+ };
+ PIO21: gpio@febc6000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x6000 0x100>;
+ interrupts = <0 170 0>;
+ st,bank-name = "PIO21";
+ };
+ PIO22: gpio@febc7000 {
+ gpio-controller;
+ #gpio-cells = <1>;
+ reg = <0x7000 0x100>;
+ interrupts = <0 171 0>;
+ st,bank-name = "PIO22";
+ };
+ uart2 {
+ pinctrl_uart2: uart2-0 {
+ st,pins {
+ tx = <&PIO20 1 ALT3 OUT>;
+ rx = <&PIO20 2 ALT3 IN>;
+ };
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stid127.dtsi b/arch/arm/boot/dts/stid127.dtsi
new file mode 100644
index 0000000..a6f0b8fe
--- /dev/null
+++ b/arch/arm/boot/dts/stid127.dtsi
@@ -0,0 +1,130 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author(s): Giuseppe Cavallaro <peppe.cavallaro@st.com>
+ * Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stid127-pinctrl.dtsi"
+#include "stid127-clock.dtsi"
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@fffe1000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0xfffe1000 0x1000>,
+ <0xfffe0100 0x100>;
+ };
+
+ scu@fffe0000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0xfffe0000 0x1000>;
+ };
+
+ timer@fffe0200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0xfffe0200 0x100>;
+ interrupts = <1 11 0x04>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfffe2000 0x1000>;
+ arm,data-latency = <3 2 2>;
+ arm,tag-latency = <1 1 1>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ syscfg_west:west-syscfg@febf0000{
+ compatible = "st,stid127-west-syscfg", "syscon";
+ reg = <0xfebf0000 0x1000>;
+ };
+
+ syscfg_south:south-syscfg@fefa0000{
+ compatible = "st,stid127-south-syscfg", "syscon";
+ reg = <0xfefa0000 0x1000>;
+ };
+
+ syscfg_docsis:docsis-syscfg@fef90000{
+ compatible = "st,stid127-docsys-syscfg", "syscon";
+ reg = <0xfef90000 0x1000>;
+ };
+
+ syscfg_cpu:cpu-syscfg@fe9a0000{
+ compatible = "st,stid127-cpu-syscfg", "syscon";
+ reg = <0xfe9a0000 0x1000>;
+ };
+
+ syscfg_hd:hd-syscfg@fe930000{
+ compatible = "st,stid127-hd-syscfg", "syscon";
+ reg = <0xfe930000 0x1000>;
+ };
+
+ syscfg_pwest:pwest-syscfg@fec00000{
+ compatible = "st,stid127-pwest-syscfg", "syscon";
+ reg = <0xfec00000 0x1000>;
+ };
+
+ syscfg_psouth:psouth-syscfg@fefd0000{
+ compatible = "st,stid127-psouth-syscfg", "syscon";
+ reg = <0xfefd0000 0x1000>;
+ };
+
+ syscfg_peast:peast-syscfg@febd0000{
+ compatible = "st,stid127-peast-syscfg", "syscon";
+ reg = <0xfebd0000 0x1000>;
+ };
+
+ /* Comms block ASCs in SASG2 */
+ uart0: serial@fe530000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe530000 0x2c>;
+ interrupts = <0 25 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart0>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+
+ uart2: serial@fe532000{
+ compatible = "st,asc";
+ status = "disabled";
+ reg = <0xfe532000 0x2c>;
+ interrupts = <0 27 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ clocks = <&CLK_IC_LP_HD>;
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* [PATCH 4/4] ARM: dts: add B2112 board support
From: Patrice CHOTARD @ 2014-01-30 14:55 UTC (permalink / raw)
To: Srinivas Kandagatla, Stuart Menefy, Russell King,
linux-arm-kernel, kernel, linux-kernel, Linus Walleij,
Grant Likely, Rob Herring, devicetree
Cc: maxime.coquelin, alexandre.torgue, patrice.chotard,
Giuseppe Cavallaro
In-Reply-To: <1391093744-19905-1-git-send-email-patrice.chotard@st.com>
From: Alexandre TORGUE <alexandre.torgue@st.com>
Add support for B2112 board based on STiD127 SoC.
Signed-off-by: Alexandre Torgue <alexandre.torgue@st.com>
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
---
arch/arm/boot/dts/Makefile | 3 ++-
arch/arm/boot/dts/stid127-b2112.dts | 35 +++++++++++++++++++++++++++++++++++
2 files changed, 37 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stid127-b2112.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index d57c1a6..7173dca 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -247,7 +247,8 @@ dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih415-b2000.dtb \
stih416-b2000.dtb \
stih415-b2020.dtb \
- stih416-b2020.dtb
+ stih416-b2020.dtb \
+ stid127-b2112.dtb
dtb-$(CONFIG_ARCH_SUNXI) += \
sun4i-a10-a1000.dtb \
sun4i-a10-cubieboard.dtb \
diff --git a/arch/arm/boot/dts/stid127-b2112.dts b/arch/arm/boot/dts/stid127-b2112.dts
new file mode 100644
index 0000000..b4507e3
--- /dev/null
+++ b/arch/arm/boot/dts/stid127-b2112.dts
@@ -0,0 +1,35 @@
+/*
+ * Copyright (C) 2013 STMicroelectronics Limited.
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stid127.dtsi"
+
+/ {
+ model = "STiD127 B2112 Board";
+ compatible = "st,stid127", "st,stid127-b2112";
+
+ memory{
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &uart2;
+ };
+
+ aliases {
+ ttyAS0 = &uart2;
+ };
+
+ soc {
+ uart2: serial@fe532000{
+ status = "okay";
+ };
+ };
+};
--
1.7.9.5
^ permalink raw reply related
* Re: [RFC PATCH pre-v3 08/14] mtd: nand: add sunxi NAND flash controller support
From: Boris BREZILLON @ 2014-01-30 15:04 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: Maxime Ripard, Rob Landley, David Woodhouse, Grant Likely,
Brian Norris, Jason Gunthorpe, Arnd Bergmann,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dev-3kdeTeqwOZ9EV1b7eY7vFQ
In-Reply-To: <20140130143641.GZ15937-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
Hello Russel,
On 30/01/2014 15:36, Russell King - ARM Linux wrote:
> Boris,
>
> Can you please explain to me why you mail all your patches _To:_ me?
> As in, why do I appear in the To: line of all the patches you seem to
> mail out, whether or not they're relevant to me. I see this very
> regularly from you - virtually all patches I see on the LAKML mailing
> list from you are always sent To: me as well.
>
> Take for instance this one. It doesn't match up with anything in
> MAINTAINERS for me. It doesn't even touch a file that I've touched.
> Yet somehow you think that I should be in the To: header.
>
> Being in the To: header means that you expect the recipient to do
> something with your email. The Cc: header is to circulate copies of
> your email to people who may be interested.
>
> I'm neither for this stuff. Please stop this.
Sorry for the inconvenience.
I'm using get_maintainer.pl script to retrieve the list of concerned
people, and you appears in that list for patches 10,11,12 and 14 of this
series.
Moreover I was told to send the whole series (not just specific patches
to people who might be concerned).
I obviously misuse this script, so please tell me how I should know which
patch I should send to whom.
Thanks.
Best Regards,
Boris
>
> Thanks.
>
> On Thu, Jan 30, 2014 at 02:39:36PM +0100, Boris BREZILLON wrote:
>> Add support for the sunxi NAND Flash Controller (NFC).
>>
>> Signed-off-by: Boris BREZILLON <b.brezillon.dev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> Hello,
>>
>> This version fixes a bug in the R/B GPIO config block.
>> The timing config order is now respected, but I'll wait for Jason work
>> regarding timing config in NAND core code before posting the 3rd version
>> of this series.
>>
>> Best Regards,
>>
>> Boris
>>
>> Changes since v2:
>> - fix R/B GPIO retrieval/config bug
>> - fix timings configuration order (set mode 0 -> scan -> set best supported
>> mode)
>>
>> drivers/mtd/nand/Kconfig | 6 +
>> drivers/mtd/nand/Makefile | 1 +
>> drivers/mtd/nand/sunxi_nand.c | 758 +++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 765 insertions(+)
>> create mode 100644 drivers/mtd/nand/sunxi_nand.c
>>
>> diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
>> index 93ae6a6..784dd42 100644
>> --- a/drivers/mtd/nand/Kconfig
>> +++ b/drivers/mtd/nand/Kconfig
>> @@ -510,4 +510,10 @@ config MTD_NAND_XWAY
>> Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
>> to the External Bus Unit (EBU).
>>
>> +config MTD_NAND_SUNXI
>> + tristate "Support for NAND on Allwinner SoCs"
>> + depends on ARCH_SUNXI
>> + help
>> + Enables support for NAND Flash chips on Allwinner SoCs.
>> +
>> endif # MTD_NAND
>> diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
>> index bbea7a6..e3b4a34 100644
>> --- a/drivers/mtd/nand/Makefile
>> +++ b/drivers/mtd/nand/Makefile
>> @@ -49,5 +49,6 @@ obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
>> obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
>> obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
>> obj-$(CONFIG_MTD_NAND_BCM47XXNFLASH) += bcm47xxnflash/
>> +obj-$(CONFIG_MTD_NAND_SUNXI) += sunxi_nand.o
>>
>> nand-objs := nand_base.o nand_bbt.o
>> diff --git a/drivers/mtd/nand/sunxi_nand.c b/drivers/mtd/nand/sunxi_nand.c
>> new file mode 100644
>> index 0000000..1014b2a
>> --- /dev/null
>> +++ b/drivers/mtd/nand/sunxi_nand.c
>> @@ -0,0 +1,758 @@
>> +/*
>> + * Copyright (C) 2013 Boris BREZILLON <b.brezillon.dev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * Derived from:
>> + * https://github.com/yuq/sunxi-nfc-mtd
>> + * Copyright (C) 2013 Qiang Yu <yuq825-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + *
>> + * https://github.com/hno/Allwinner-Info
>> + * Copyright (C) 2013 Henrik Nordström <Henrik Nordström>
>> + *
>> + * Copyright (C) 2013 Dmitriy B. <rzk333-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> + * Copyright (C) 2013 Sergey Lapin <slapin-9cOl001CZnBAfugRpC6u6w@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/dma-mapping.h>
>> +#include <linux/slab.h>
>> +#include <linux/module.h>
>> +#include <linux/moduleparam.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/of_gpio.h>
>> +#include <linux/of_mtd.h>
>> +#include <linux/mtd/mtd.h>
>> +#include <linux/mtd/nand.h>
>> +#include <linux/mtd/partitions.h>
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/dmaengine.h>
>> +#include <linux/gpio.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/io.h>
>> +
>> +#define NFC_REG_CTL 0x0000
>> +#define NFC_REG_ST 0x0004
>> +#define NFC_REG_INT 0x0008
>> +#define NFC_REG_TIMING_CTL 0x000C
>> +#define NFC_REG_TIMING_CFG 0x0010
>> +#define NFC_REG_ADDR_LOW 0x0014
>> +#define NFC_REG_ADDR_HIGH 0x0018
>> +#define NFC_REG_SECTOR_NUM 0x001C
>> +#define NFC_REG_CNT 0x0020
>> +#define NFC_REG_CMD 0x0024
>> +#define NFC_REG_RCMD_SET 0x0028
>> +#define NFC_REG_WCMD_SET 0x002C
>> +#define NFC_REG_IO_DATA 0x0030
>> +#define NFC_REG_ECC_CTL 0x0034
>> +#define NFC_REG_ECC_ST 0x0038
>> +#define NFC_REG_DEBUG 0x003C
>> +#define NFC_REG_ECC_CNT0 0x0040
>> +#define NFC_REG_ECC_CNT1 0x0044
>> +#define NFC_REG_ECC_CNT2 0x0048
>> +#define NFC_REG_ECC_CNT3 0x004c
>> +#define NFC_REG_USER_DATA_BASE 0x0050
>> +#define NFC_REG_SPARE_AREA 0x00A0
>> +#define NFC_RAM0_BASE 0x0400
>> +#define NFC_RAM1_BASE 0x0800
>> +
>> +/*define bit use in NFC_CTL*/
>> +#define NFC_EN (1 << 0)
>> +#define NFC_RESET (1 << 1)
>> +#define NFC_BUS_WIDYH (1 << 2)
>> +#define NFC_RB_SEL (1 << 3)
>> +#define NFC_CE_SEL (7 << 24)
>> +#define NFC_CE_CTL (1 << 6)
>> +#define NFC_CE_CTL1 (1 << 7)
>> +#define NFC_PAGE_SIZE (0xf << 8)
>> +#define NFC_SAM (1 << 12)
>> +#define NFC_RAM_METHOD (1 << 14)
>> +#define NFC_DEBUG_CTL (1 << 31)
>> +
>> +/*define bit use in NFC_ST*/
>> +#define NFC_RB_B2R (1 << 0)
>> +#define NFC_CMD_INT_FLAG (1 << 1)
>> +#define NFC_DMA_INT_FLAG (1 << 2)
>> +#define NFC_CMD_FIFO_STATUS (1 << 3)
>> +#define NFC_STA (1 << 4)
>> +#define NFC_NATCH_INT_FLAG (1 << 5)
>> +#define NFC_RB_STATE0 (1 << 8)
>> +#define NFC_RB_STATE1 (1 << 9)
>> +#define NFC_RB_STATE2 (1 << 10)
>> +#define NFC_RB_STATE3 (1 << 11)
>> +
>> +/*define bit use in NFC_INT*/
>> +#define NFC_B2R_INT_ENABLE (1 << 0)
>> +#define NFC_CMD_INT_ENABLE (1 << 1)
>> +#define NFC_DMA_INT_ENABLE (1 << 2)
>> +#define NFC_INT_MASK (NFC_B2R_INT_ENABLE | \
>> + NFC_CMD_INT_ENABLE | \
>> + NFC_DMA_INT_ENABLE)
>> +
>> +
>> +/*define bit use in NFC_CMD*/
>> +#define NFC_CMD_LOW_BYTE (0xff << 0)
>> +#define NFC_CMD_HIGH_BYTE (0xff << 8)
>> +#define NFC_ADR_NUM (0x7 << 16)
>> +#define NFC_SEND_ADR (1 << 19)
>> +#define NFC_ACCESS_DIR (1 << 20)
>> +#define NFC_DATA_TRANS (1 << 21)
>> +#define NFC_SEND_CMD1 (1 << 22)
>> +#define NFC_WAIT_FLAG (1 << 23)
>> +#define NFC_SEND_CMD2 (1 << 24)
>> +#define NFC_SEQ (1 << 25)
>> +#define NFC_DATA_SWAP_METHOD (1 << 26)
>> +#define NFC_ROW_AUTO_INC (1 << 27)
>> +#define NFC_SEND_CMD3 (1 << 28)
>> +#define NFC_SEND_CMD4 (1 << 29)
>> +#define NFC_CMD_TYPE (3 << 30)
>> +
>> +/* define bit use in NFC_RCMD_SET*/
>> +#define NFC_READ_CMD (0xff << 0)
>> +#define NFC_RANDOM_READ_CMD0 (0xff << 8)
>> +#define NFC_RANDOM_READ_CMD1 (0xff << 16)
>> +
>> +/*define bit use in NFC_WCMD_SET*/
>> +#define NFC_PROGRAM_CMD (0xff << 0)
>> +#define NFC_RANDOM_WRITE_CMD (0xff << 8)
>> +#define NFC_READ_CMD0 (0xff << 16)
>> +#define NFC_READ_CMD1 (0xff << 24)
>> +
>> +/*define bit use in NFC_ECC_CTL*/
>> +#define NFC_ECC_EN (1 << 0)
>> +#define NFC_ECC_PIPELINE (1 << 3)
>> +#define NFC_ECC_EXCEPTION (1 << 4)
>> +#define NFC_ECC_BLOCK_SIZE (1 << 5)
>> +#define NFC_RANDOM_EN (1 << 9)
>> +#define NFC_RANDOM_DIRECTION (1 << 10)
>> +#define NFC_ECC_MODE_SHIFT 12
>> +#define NFC_ECC_MODE (0xf << NFC_ECC_MODE_SHIFT)
>> +#define NFC_RANDOM_SEED (0x7fff << 16)
>> +
>> +
>> +
>> +enum sunxi_nand_rb_type {
>> + RB_NONE,
>> + RB_NATIVE,
>> + RB_GPIO,
>> +};
>> +
>> +struct sunxi_nand_rb {
>> + enum sunxi_nand_rb_type type;
>> + union {
>> + int gpio;
>> + int nativeid;
>> + } info;
>> +};
>> +
>> +struct sunxi_nand_chip_sel {
>> + u8 cs;
>> + struct sunxi_nand_rb rb;
>> +};
>> +
>> +#define DEFAULT_NAME_FORMAT "nand@%d"
>> +#define MAX_NAME_SIZE (sizeof("nand@") + 2)
>> +
>> +struct sunxi_nand_chip {
>> + struct list_head node;
>> + struct nand_chip nand;
>> + struct mtd_info mtd;
>> + char default_name[MAX_NAME_SIZE];
>> + unsigned long clk_rate;
>> + int selected;
>> + int nsels;
>> + struct sunxi_nand_chip_sel sels[0];
>> +};
>> +
>> +static inline struct sunxi_nand_chip *to_sunxi_nand(struct mtd_info *mtd)
>> +{
>> + return container_of(mtd, struct sunxi_nand_chip, mtd);
>> +}
>> +
>> +struct sunxi_nfc {
>> + struct nand_hw_control controller;
>> + void __iomem *regs;
>> + int irq;
>> + struct clk *ahb_clk;
>> + struct clk *sclk;
>> + unsigned long assigned_cs;
>> + unsigned long clk_rate;
>> + struct list_head chips;
>> + struct completion complete;
>> +};
>> +
>> +static inline struct sunxi_nfc *to_sunxi_nfc(struct nand_hw_control *ctrl)
>> +{
>> + return container_of(ctrl, struct sunxi_nfc, controller);
>> +}
>> +
>> +static irqreturn_t sunxi_nfc_interrupt(int irq, void *dev_id)
>> +{
>> + struct sunxi_nfc *nfc = dev_id;
>> + u32 st = readl(nfc->regs + NFC_REG_ST);
>> + u32 ien = readl(nfc->regs + NFC_REG_INT);
>> +
>> + if (!(ien & st))
>> + return IRQ_NONE;
>> +
>> + if ((ien & st) == ien)
>> + complete(&nfc->complete);
>> +
>> + writel(st & NFC_INT_MASK, nfc->regs + NFC_REG_ST);
>> + writel(~st & ien & NFC_INT_MASK, nfc->regs + NFC_REG_INT);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +static int sunxi_nfc_wait_int(struct sunxi_nfc *nfc, u32 flags,
>> + unsigned int timeout_ms)
>> +{
>> + init_completion(&nfc->complete);
>> +
>> + writel(flags, nfc->regs + NFC_REG_INT);
>> + if (!timeout_ms)
>> + wait_for_completion(&nfc->complete);
>> + else if (!wait_for_completion_timeout(&nfc->complete,
>> + msecs_to_jiffies(timeout_ms)))
>> + return -ETIMEDOUT;
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nfc_dev_ready(struct mtd_info *mtd)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + struct sunxi_nand_rb *rb;
>> + unsigned long timeo = (sunxi_nand->nand.state == FL_ERASING ? 400 : 20);
>> + int ret;
>> +
>> + if (sunxi_nand->selected < 0)
>> + return 0;
>> +
>> + rb = &sunxi_nand->sels[sunxi_nand->selected].rb;
>> +
>> + switch (rb->type) {
>> + case RB_NATIVE:
>> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
>> + (NFC_RB_STATE0 << rb->info.nativeid));
>> + if (ret)
>> + break;
>> +
>> + sunxi_nfc_wait_int(nfc, NFC_RB_B2R, timeo);
>> + ret = !!(readl(nfc->regs + NFC_REG_ST) &
>> + (NFC_RB_STATE0 << rb->info.nativeid));
>> + break;
>> + case RB_GPIO:
>> + ret = gpio_get_value(rb->info.gpio);
>> + break;
>> + case RB_NONE:
>> + default:
>> + ret = 0;
>> + dev_err(&mtd->dev, "cannot check R/B NAND status!");
>> + break;
>> + }
>> +
>> + return ret;
>> +}
>> +
>> +static void sunxi_nfc_select_chip(struct mtd_info *mtd, int chip)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct nand_chip *nand = &sunxi_nand->nand;
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + struct sunxi_nand_chip_sel *sel;
>> + u32 ctl;
>> +
>> + if (chip > 0 && chip >= sunxi_nand->nsels)
>> + return;
>> +
>> + if (chip == sunxi_nand->selected)
>> + return;
>> +
>> + ctl = readl(nfc->regs + NFC_REG_CTL) &
>> + ~(NFC_CE_SEL | NFC_RB_SEL | NFC_EN);
>> +
>> + if (chip >= 0) {
>> + sel = &sunxi_nand->sels[chip];
>> +
>> + ctl |= (sel->cs << 24) | NFC_EN |
>> + (((nand->page_shift - 10) & 0xf) << 8);
>> + if (sel->rb.type == RB_NONE) {
>> + nand->dev_ready = NULL;
>> + } else {
>> + nand->dev_ready = sunxi_nfc_dev_ready;
>> + if (sel->rb.type == RB_NATIVE)
>> + ctl |= (sel->rb.info.nativeid << 3);
>> + }
>> +
>> + writel(mtd->writesize, nfc->regs + NFC_REG_SPARE_AREA);
>> +
>> + if (nfc->clk_rate != sunxi_nand->clk_rate) {
>> + clk_set_rate(nfc->sclk, sunxi_nand->clk_rate);
>> + nfc->clk_rate = sunxi_nand->clk_rate;
>> + }
>> + }
>> +
>> + writel(ctl, nfc->regs + NFC_REG_CTL);
>> +
>> + sunxi_nand->selected = chip;
>> +}
>> +
>> +static void sunxi_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + int cnt;
>> + int offs = 0;
>> + u32 tmp;
>> +
>> + while (len > offs) {
>> + cnt = len - offs;
>> + if (cnt > 1024)
>> + cnt = 1024;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> + writel(cnt, nfc->regs + NFC_REG_CNT);
>> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD;
>> + writel(tmp, nfc->regs + NFC_REG_CMD);
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> + if (buf)
>> + memcpy_fromio(buf + offs, nfc->regs + NFC_RAM0_BASE,
>> + cnt);
>> + offs += cnt;
>> + }
>> +}
>> +
>> +static void sunxi_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
>> + int len)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + int cnt;
>> + int offs = 0;
>> + u32 tmp;
>> +
>> + while (len > offs) {
>> + cnt = len - offs;
>> + if (cnt > 1024)
>> + cnt = 1024;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> + writel(cnt, nfc->regs + NFC_REG_CNT);
>> + memcpy_toio(nfc->regs + NFC_RAM0_BASE, buf + offs, cnt);
>> + tmp = NFC_DATA_TRANS | NFC_DATA_SWAP_METHOD |
>> + NFC_ACCESS_DIR;
>> + writel(tmp, nfc->regs + NFC_REG_CMD);
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> + offs += cnt;
>> + }
>> +}
>> +
>> +static uint8_t sunxi_nfc_read_byte(struct mtd_info *mtd)
>> +{
>> + uint8_t ret;
>> +
>> + sunxi_nfc_read_buf(mtd, &ret, 1);
>> +
>> + return ret;
>> +}
>> +
>> +static void sunxi_nfc_cmd_ctrl(struct mtd_info *mtd, int dat,
>> + unsigned int ctrl)
>> +{
>> + struct sunxi_nand_chip *sunxi_nand = to_sunxi_nand(mtd);
>> + struct sunxi_nfc *nfc = to_sunxi_nfc(sunxi_nand->nand.controller);
>> + u32 tmp;
>> +
>> + while ((readl(nfc->regs + NFC_REG_ST) & NFC_CMD_FIFO_STATUS))
>> + ;
>> +
>> + if (ctrl & NAND_CTRL_CHANGE) {
>> + tmp = readl(nfc->regs + NFC_REG_CTL);
>> + if (ctrl & NAND_NCE)
>> + tmp |= NFC_CE_CTL;
>> + else
>> + tmp &= ~NFC_CE_CTL;
>> + writel(tmp, nfc->regs + NFC_REG_CTL);
>> + }
>> +
>> + if (dat == NAND_CMD_NONE)
>> + return;
>> +
>> + if (ctrl & NAND_CLE) {
>> + writel(NFC_SEND_CMD1 | dat, nfc->regs + NFC_REG_CMD);
>> + } else {
>> + writel(dat, nfc->regs + NFC_REG_ADDR_LOW);
>> + writel(NFC_SEND_ADR, nfc->regs + NFC_REG_CMD);
>> + }
>> +
>> + sunxi_nfc_wait_int(nfc, NFC_CMD_INT_FLAG, 0);
>> +}
>> +
>> +static int sunxi_nand_chip_set_timings(struct sunxi_nand_chip *chip,
>> + const struct nand_sdr_timings *timings)
>> +{
>> + u32 min_clk_period = 0;
>> +
>> + /* T1 <=> tCLS */
>> + if (timings->tCLS_min > min_clk_period)
>> + min_clk_period = timings->tCLS_min;
>> +
>> + /* T2 <=> tCLH */
>> + if (timings->tCLH_min > min_clk_period)
>> + min_clk_period = timings->tCLH_min;
>> +
>> + /* T3 <=> tCS */
>> + if (timings->tCS_min > min_clk_period)
>> + min_clk_period = timings->tCS_min;
>> +
>> + /* T4 <=> tCH */
>> + if (timings->tCH_min > min_clk_period)
>> + min_clk_period = timings->tCH_min;
>> +
>> + /* T5 <=> tWP */
>> + if (timings->tWP_min > min_clk_period)
>> + min_clk_period = timings->tWP_min;
>> +
>> + /* T6 <=> tWH */
>> + if (timings->tWH_min > min_clk_period)
>> + min_clk_period = timings->tWH_min;
>> +
>> + /* T7 <=> tALS */
>> + if (timings->tALS_min > min_clk_period)
>> + min_clk_period = timings->tALS_min;
>> +
>> + /* T8 <=> tDS */
>> + if (timings->tDS_min > min_clk_period)
>> + min_clk_period = timings->tDS_min;
>> +
>> + /* T9 <=> tDH */
>> + if (timings->tDH_min > min_clk_period)
>> + min_clk_period = timings->tDH_min;
>> +
>> + /* T10 <=> tRR */
>> + if (timings->tRR_min > (min_clk_period * 3))
>> + min_clk_period = (timings->tRR_min + 2) / 3;
>> +
>> + /* T11 <=> tALH */
>> + if (timings->tALH_min > min_clk_period)
>> + min_clk_period = timings->tALH_min;
>> +
>> + /* T12 <=> tRP */
>> + if (timings->tRP_min > min_clk_period)
>> + min_clk_period = timings->tRP_min;
>> +
>> + /* T13 <=> tREH */
>> + if (timings->tREH_min > min_clk_period)
>> + min_clk_period = timings->tREH_min;
>> +
>> + /* T14 <=> tRC */
>> + if (timings->tRC_min > (min_clk_period * 2))
>> + min_clk_period = (timings->tRC_min + 1) / 2;
>> +
>> + /* T15 <=> tWC */
>> + if (timings->tWC_min > (min_clk_period * 2))
>> + min_clk_period = (timings->tWC_min + 1) / 2;
>> +
>> +
>> + /* min_clk_period = (NAND-clk-period * 2) */
>> + if (min_clk_period < 1000)
>> + min_clk_period = 1000;
>> +
>> + min_clk_period /= 1000;
>> + chip->clk_rate = (2 * 1000000000) / min_clk_period;
>> +
>> + /* TODO: configure T16-T19 */
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nand_chip_init_timings(struct sunxi_nand_chip *chip,
>> + struct device_node *np)
>> +{
>> + const struct nand_sdr_timings *timings;
>> + int ret;
>> +
>> + ret = onfi_get_async_timing_mode(&chip->nand);
>> + if (ret == ONFI_TIMING_MODE_UNKNOWN) {
>> + ret = of_get_nand_onfi_timing_mode(np);
>> + if (ret < 0)
>> + return ret;
>> + }
>> +
>> + ret = fls(ret);
>> + if (!ret)
>> + return -EINVAL;
>> +
>> + timings = onfi_async_timing_mode_to_sdr_timings(ret - 1);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + return sunxi_nand_chip_set_timings(chip, timings);
>> +}
>> +
>> +static int sunxi_nand_chip_init(struct device *dev, struct sunxi_nfc *nfc,
>> + struct device_node *np)
>> +{
>> + const struct nand_sdr_timings *timings;
>> + struct sunxi_nand_chip *chip;
>> + struct mtd_part_parser_data ppdata;
>> + struct mtd_info *mtd;
>> + struct nand_chip *nand;
>> + u32 strength;
>> + u32 blk_size;
>> + int nsels;
>> + int ret;
>> + int i;
>> + u32 tmp;
>> +
>> + if (!of_get_property(np, "reg", &nsels))
>> + return -EINVAL;
>> +
>> + nsels /= sizeof(u32);
>> + if (!nsels)
>> + return -EINVAL;
>> +
>> + chip = devm_kzalloc(dev,
>> + sizeof(*chip) +
>> + (nsels * sizeof(struct sunxi_nand_chip_sel)),
>> + GFP_KERNEL);
>> + if (!chip)
>> + return -ENOMEM;
>> +
>> + chip->nsels = nsels;
>> + chip->selected = -1;
>> +
>> + for (i = 0; i < nsels; i++) {
>> + ret = of_property_read_u32_index(np, "reg", i, &tmp);
>> + if (ret)
>> + return ret;
>> +
>> + if (tmp > 7)
>> + return -EINVAL;
>> +
>> + if (test_and_set_bit(tmp, &nfc->assigned_cs))
>> + return -EINVAL;
>> +
>> + chip->sels[i].cs = tmp;
>> +
>> + if (!of_property_read_u32_index(np, "allwinner,rb", i, &tmp) &&
>> + tmp < 2) {
>> + chip->sels[i].rb.type = RB_NATIVE;
>> + chip->sels[i].rb.info.nativeid = tmp;
>> + } else {
>> + ret = of_get_named_gpio(np, "rb-gpios", i);
>> + if (ret >= 0) {
>> + tmp = ret;
>> + chip->sels[i].rb.type = RB_GPIO;
>> + chip->sels[i].rb.info.gpio = tmp;
>> + ret = devm_gpio_request(dev, tmp, "nand-rb");
>> + if (ret)
>> + return ret;
>> +
>> + ret = gpio_direction_input(tmp);
>> + if (ret)
>> + return ret;
>> + } else {
>> + chip->sels[i].rb.type = RB_NONE;
>> + }
>> + }
>> + }
>> +
>> + timings = onfi_async_timing_mode_to_sdr_timings(0);
>> + if (IS_ERR(timings))
>> + return PTR_ERR(timings);
>> +
>> + ret = sunxi_nand_chip_set_timings(chip, timings);
>> +
>> + nand = &chip->nand;
>> + nand->controller = &nfc->controller;
>> + nand->select_chip = sunxi_nfc_select_chip;
>> + nand->cmd_ctrl = sunxi_nfc_cmd_ctrl;
>> + nand->read_buf = sunxi_nfc_read_buf;
>> + nand->write_buf = sunxi_nfc_write_buf;
>> + nand->read_byte = sunxi_nfc_read_byte;
>> +
>> + nand->ecc.mode = of_get_nand_ecc_mode(np);
>> + if (of_get_nand_on_flash_bbt(np))
>> + nand->bbt_options |= NAND_BBT_USE_FLASH;
>> +
>> + mtd = &chip->mtd;
>> + mtd->priv = nand;
>> + mtd->owner = THIS_MODULE;
>> +
>> + ret = nand_scan_ident(mtd, nsels, NULL);
>> + if (ret)
>> + return ret;
>> +
>> + ret = sunxi_nand_chip_init_timings(chip, np);
>> + if (ret)
>> + return ret;
>> +
>> + if (nand->ecc.mode == NAND_ECC_SOFT_BCH) {
>> + if (!of_get_nand_ecc_level(np, &strength, &blk_size)) {
>> + nand->ecc_step_ds = blk_size;
>> + nand->ecc_strength_ds = strength;
>> + }
>> +
>> + nand->ecc.size = nand->ecc_step_ds;
>> + nand->ecc.bytes = (((nand->ecc_strength_ds *
>> + fls(8 * nand->ecc_step_ds)) + 7) / 8);
>> + }
>> +
>> + ret = nand_scan_tail(mtd);
>> + if (ret)
>> + return ret;
>> +
>> + if (of_property_read_string(np, "nand-name", &mtd->name)) {
>> + snprintf(chip->default_name, MAX_NAME_SIZE,
>> + DEFAULT_NAME_FORMAT, chip->sels[i].cs);
>> + mtd->name = chip->default_name;
>> + }
>> +
>> + ppdata.of_node = np;
>> + ret = mtd_device_parse_register(mtd, NULL, &ppdata, NULL, 0);
>> + if (!ret)
>> + return ret;
>> +
>> + list_add_tail(&chip->node, &nfc->chips);
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nand_chips_init(struct device *dev, struct sunxi_nfc *nfc)
>> +{
>> + struct device_node *np = dev->of_node;
>> + struct device_node *nand_np;
>> + int nchips = of_get_child_count(np);
>> + int ret;
>> +
>> + if (nchips > 8)
>> + return -EINVAL;
>> +
>> + for_each_child_of_node(np, nand_np) {
>> + ret = sunxi_nand_chip_init(dev, nfc, nand_np);
>> + if (ret)
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +static int sunxi_nfc_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct resource *r;
>> + struct sunxi_nfc *nfc;
>> + int ret;
>> +
>> + nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
>> + if (!nfc) {
>> + dev_err(dev, "failed to allocate NFC struct\n");
>> + return -ENOMEM;
>> + }
>> +
>> + spin_lock_init(&nfc->controller.lock);
>> + init_waitqueue_head(&nfc->controller.wq);
>> + INIT_LIST_HEAD(&nfc->chips);
>> +
>> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + nfc->regs = devm_ioremap_resource(dev, r);
>> + if (IS_ERR(nfc->regs)) {
>> + dev_err(dev, "failed to remap iomem\n");
>> + return PTR_ERR(nfc->regs);
>> + }
>> +
>> + nfc->irq = platform_get_irq(pdev, 0);
>> + if (nfc->irq < 0) {
>> + dev_err(dev, "failed to retrieve irq\n");
>> + return nfc->irq;
>> + }
>> +
>> + nfc->ahb_clk = devm_clk_get(dev, "ahb_clk");
>> + if (IS_ERR(nfc->ahb_clk)) {
>> + dev_err(dev, "failed to retrieve ahb_clk\n");
>> + return PTR_ERR(nfc->ahb_clk);
>> + }
>> +
>> + ret = clk_prepare_enable(nfc->ahb_clk);
>> + if (ret)
>> + return ret;
>> +
>> + nfc->sclk = devm_clk_get(dev, "sclk");
>> + if (IS_ERR(nfc->sclk)) {
>> + dev_err(dev, "failed to retrieve nand_clk\n");
>> + ret = PTR_ERR(nfc->sclk);
>> + goto out_ahb_clk_unprepare;
>> + }
>> +
>> + ret = clk_prepare_enable(nfc->sclk);
>> + if (ret)
>> + goto out_ahb_clk_unprepare;
>> +
>> + /* Reset NFC */
>> + writel(readl(nfc->regs + NFC_REG_CTL) | NFC_RESET,
>> + nfc->regs + NFC_REG_CTL);
>> + while (readl(nfc->regs + NFC_REG_CTL) & NFC_RESET)
>> + ;
>> +
>> + writel(0, nfc->regs + NFC_REG_INT);
>> + ret = devm_request_irq(dev, nfc->irq, sunxi_nfc_interrupt,
>> + 0, "sunxi-nand", nfc);
>> + if (ret)
>> + goto out_sclk_unprepare;
>> +
>> + platform_set_drvdata(pdev, nfc);
>> +
>> + writel(0x100, nfc->regs + NFC_REG_TIMING_CTL);
>> + writel(0x7ff, nfc->regs + NFC_REG_TIMING_CFG);
>> +
>> + ret = sunxi_nand_chips_init(dev, nfc);
>> + if (ret) {
>> + dev_err(dev, "failed to init nand chips\n");
>> + goto out_sclk_unprepare;
>> + }
>> +
>> + return 0;
>> +
>> +out_sclk_unprepare:
>> + clk_disable_unprepare(nfc->sclk);
>> +out_ahb_clk_unprepare:
>> + clk_disable_unprepare(nfc->ahb_clk);
>> +
>> + return ret;
>> +}
>> +
>> +static const struct of_device_id sunxi_nfc_ids[] = {
>> + { .compatible = "allwinner,sun4i-nand" },
>> + { /* sentinel */ }
>> +};
>> +MODULE_DEVICE_TABLE(of, sunxi_nfc_ids);
>> +
>> +static struct platform_driver sunxi_nfc_driver = {
>> + .driver = {
>> + .name = "sunxi_nand",
>> + .owner = THIS_MODULE,
>> + .of_match_table = of_match_ptr(sunxi_nfc_ids),
>> + },
>> + .probe = sunxi_nfc_probe,
>> +};
>> +module_platform_driver(sunxi_nfc_driver);
>> +
>> +MODULE_LICENSE("GPL v2");
>> +MODULE_AUTHOR("Boris BREZILLON");
>> +MODULE_DESCRIPTION("Allwinner NAND Flash Controller driver");
>> +MODULE_ALIAS("platform:sunxi_nfc");
>> --
>> 1.7.9.5
>>
--
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^ permalink raw reply
* Re: [PATCH v3 0/2] Qualcomm Universal Peripheral (QUP) I2C controller
From: Ivan T. Ivanov @ 2014-01-30 15:30 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Mark Rutland, linux-doc@vger.kernel.org,
linux-i2c@vger.kernel.org, Matt Porter, Wolfram Sang,
Bjorn Andersson, Grant Likely, James Ralston,
devicetree@vger.kernel.org, Pawel Moll, Ian Campbell,
linux-arm-msm, Rob Herring, Jean Delvare, Andy Shevchenko,
linux-arm-kernel@lists.infradead.org, Bill Brown,
Greg Kroah-Hartman, linux-kernel@vger.kernel.org
In-Reply-To: <CAJAp7Oj_D1QvG9nBWTVrW1QVEpqi2cTTc9c6Um25DDzidCjW1w@mail.gmail.com>
Hi Bjorn,
On Wed, 2014-01-29 at 08:32 -0800, Bjorn Andersson wrote:
> On Wed, Jan 29, 2014 at 12:14 AM, Ivan T. Ivanov <iivanov@mm-sol.com> wrote:
> >
> > Hi Bjorn,
> >
> > On Fri, 2014-01-17 at 15:03 -0800, Bjorn Andersson wrote:
> >> Continuing on Ivans i2c-qup series.
> >>
> >
> > Do you plan to send v4 of this driver? I would like to address
> > the remaining errors and suggestions and send a new version.
> >
> Hi Ivan,
>
> Yes I'm planning to send out a new revision of the patch set.
>
> I've incorporated fixes from the review comments here and my colleague
> concluded through some testing that block read did not work, so we've
> fixed that as well.
Busted. I have not test it.
>
> What have been holding me from submitting a new patchset is the 3
> functions that does polling of state and status updates;
> * qup_i2c_poll_state() reads the state register up to 1000 times,
> hoping we reach the expected state, will delay 100uS and then continue
> with 1000 more retries.
> According to the data sheet a state transition is supposed to take
> up to 2 bus cycles. Only time I can see that this would take longer
> time are all error states, but the data sheet is not very clear
> regarding this.
>
> * qup_i2c_wait_idle() reads the status register up to 1000 times,
> hoping the fifo gets drained and the bus go idle, if that fails it
> sleeps for the time we expect it to take to drain a full fifo and then
> loops another 1000 times. This waits for the fifo to have drained and
> the bus to go idle. On a read we get to this state if we issue the
> write and then hit the error state, so we would reset the entire
> block. On write we will only wait for the buffer not to be full before
> returning.
>
> * qup_i2c_wait_clock_ready() waits up to 300 bus-clocks for the i2c
> bus to go idle or forced low, I don't know why it retries 300 times.
> This is called at the end of a write, possibly to wait for the fifo to
> drain.
>
>
> All three loops are in line with how it's been in codeaurora since the
> beginning of time, but I at least need to figure out some good names
> for those "magic numbers".
Sure. I have keep them this way, just because I don't have information
for internal trickery of the block.
Thanks,
Ivan
>
> Regards,
> Bjorn
^ permalink raw reply
* [PATCH] arm: document "mach-virt" platform.
From: Ian Campbell @ 2014-01-30 16:11 UTC (permalink / raw)
To: linux-kernel
Cc: Ian Campbell, Rob Herring, Pawel Moll, Mark Rutland, Kumar Gala,
Olof Johansson, Arnd Bergmann, Marc Zyngier, Will Deacon,
Stefano Stabellini, devicetree, linux-arm-kernel
mach-virt has existed for a while but it is not written down what it actually
consists of. Although it seems a bit unusual to document a binding for an
entire platform since mach-virt is entirely virtual it is helpful to have
something to refer to in the absence of a single concrete implementation.
I've done my best to capture the requirements based on the git log and my
memory/understanding.
While here remove the xenvm dts example, the Xen tools will now build a
suitable mach-virt compatible dts when launching the guest.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
---
I'm not sure which tree this sort of thing should go though, sorry for the
huge Cc.
---
.../devicetree/bindings/arm/mach-virt.txt | 32 ++++++++
arch/arm/boot/dts/xenvm-4.2.dts | 81 --------------------
2 files changed, 32 insertions(+), 81 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/mach-virt.txt
delete mode 100644 arch/arm/boot/dts/xenvm-4.2.dts
diff --git a/Documentation/devicetree/bindings/arm/mach-virt.txt b/Documentation/devicetree/bindings/arm/mach-virt.txt
new file mode 100644
index 0000000..562bcda
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
@@ -0,0 +1,32 @@
+* Mach-virt "Dummy Virtual Machine" platform
+
+"mach-virt" is the smallest, dumbest platform possible, to be used as
+a guest for Xen, KVM and other hypervisors. It has no
+properties/functionality of its own and is driven entirely by device
+tree.
+
+This document defines the requirements for such a platform.
+
+* Required properties:
+
+- compatible: should be one of:
+ "linux,dummy-virt"
+ "xen,xenvm"
+
+In addition to the standard nodes (chosen, cpus, memory etc) the
+platform is required to provide certain other basic functionality
+which must be described in the device tree:
+
+ The platform must provide an ARM Generic Interrupt Controller
+ (GIC), defined in Documentation/devicetree/bindings/arm/gic.txt.
+
+ The platform must provide ARM architected timer, defined in
+ Documentation/devicetree/bindings/arm/arch_timer.txt.
+
+ If the platform is SMP then it must provide the Power State
+ Coordination Interface (PSCI) described in
+ Documentation/devicetree/bindings/arm/psci.txt.
+
+The platform may also provide hypervisor specific functionality
+(e.g. PV I/O), if it does so then this functionality must be
+discoverable (directly or indirectly) via device tree.
diff --git a/arch/arm/boot/dts/xenvm-4.2.dts b/arch/arm/boot/dts/xenvm-4.2.dts
deleted file mode 100644
index 3369151..0000000
--- a/arch/arm/boot/dts/xenvm-4.2.dts
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Xen Virtual Machine for unprivileged guests
- *
- * Based on ARM Ltd. Versatile Express CoreTile Express (single CPU)
- * Cortex-A15 MPCore (V2P-CA15)
- *
- */
-
-/dts-v1/;
-
-/ {
- model = "XENVM-4.2";
- compatible = "xen,xenvm-4.2", "xen,xenvm";
- interrupt-parent = <&gic>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- chosen {
- /* this field is going to be adjusted by the hypervisor */
- bootargs = "console=hvc0 root=/dev/xvda";
- };
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
-
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <0>;
- };
-
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a15";
- reg = <1>;
- };
- };
-
- psci {
- compatible = "arm,psci";
- method = "hvc";
- cpu_off = <1>;
- cpu_on = <2>;
- };
-
- memory@80000000 {
- device_type = "memory";
- /* this field is going to be adjusted by the hypervisor */
- reg = <0 0x80000000 0 0x08000000>;
- };
-
- gic: interrupt-controller@2c001000 {
- compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- #address-cells = <0>;
- interrupt-controller;
- reg = <0 0x2c001000 0 0x1000>,
- <0 0x2c002000 0 0x100>;
- };
-
- timer {
- compatible = "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- };
-
- hypervisor {
- compatible = "xen,xen-4.2", "xen,xen";
- /* this field is going to be adjusted by the hypervisor */
- reg = <0 0xb0000000 0 0x20000>;
- /* this field is going to be adjusted by the hypervisor */
- interrupts = <1 15 0xf08>;
- };
-
- motherboard {
- arm,v2m-memory-map = "rs1";
- };
-};
--
1.7.10.4
^ permalink raw reply related
* Re: [PATCH] arm: document "mach-virt" platform.
From: Christopher Covington @ 2014-01-30 16:54 UTC (permalink / raw)
To: Ian Campbell
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Pawel Moll, Stefano Stabellini,
Marc Zyngier, Will Deacon, Rob Herring, Arnd Bergmann, Kumar Gala,
Olof Johansson, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1391098262-15944-1-git-send-email-ian.campbell-Sxgqhf6Nn4DQT0dZR+AlfA@public.gmane.org>
Hi Ian,
On 01/30/2014 11:11 AM, Ian Campbell wrote:
> mach-virt has existed for a while but it is not written down what it actually
> consists of. Although it seems a bit unusual to document a binding for an
> entire platform since mach-virt is entirely virtual it is helpful to have
> something to refer to in the absence of a single concrete implementation.
>
> I've done my best to capture the requirements based on the git log and my
> memory/understanding.
>
> While here remove the xenvm dts example, the Xen tools will now build a
> suitable mach-virt compatible dts when launching the guest.
[...]
> +++ b/Documentation/devicetree/bindings/arm/mach-virt.txt
> @@ -0,0 +1,32 @@
> +* Mach-virt "Dummy Virtual Machine" platform
> +
> +"mach-virt" is the smallest, dumbest platform possible, to be used as
> +a guest for Xen, KVM and other hypervisors.
The platform is also useful to, and used by, simulators like QEMU in TCG mode.
> It has no
> +properties/functionality of its own and is driven entirely by device
> +tree.
I find this wording confusing. I read it as saying the platform has no
properties or functionality. Perhaps you could phrase it slightly differently,
such as having no properties or functionality beyond what's described in the
device tree.
> +This document defines the requirements for such a platform.
> +
> +* Required properties:
> +
> +- compatible: should be one of:
> + "linux,dummy-virt"
> + "xen,xenvm"
> +
> +In addition to the standard nodes (chosen, cpus, memory etc) the
> +platform is required to provide certain other basic functionality
> +which must be described in the device tree:
> +
> + The platform must provide an ARM Generic Interrupt Controller
> + (GIC), defined in Documentation/devicetree/bindings/arm/gic.txt.
> +
> + The platform must provide ARM architected timer, defined in
> + Documentation/devicetree/bindings/arm/arch_timer.txt.
> +
> + If the platform is SMP then it must provide the Power State
> + Coordination Interface (PSCI) described in
> + Documentation/devicetree/bindings/arm/psci.txt.
> +
> +The platform may also provide hypervisor specific functionality
> +(e.g. PV I/O), if it does so then this functionality must be
> +discoverable (directly or indirectly) via device tree.
I think it would be informative to provide pointers here to commonly used
paravirtualized devices, especially VirtIO PCI/MMIO.
Thanks,
Christopher
--
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