* [PATCH v6 7/8] ARM: dts: sun5i: Add support for mmc
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +++++++++++++++
arch/arm/boot/dts/sun5i-a10s.dtsi | 44 ++++++++++++++++++++++
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15 ++++++++
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15 ++++++++
arch/arm/boot/dts/sun5i-a13.dtsi | 37 +++++++++++++++++++
5 files changed, 141 insertions(+)
diff --git a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
index 3c9f8b3..5c7b454 100644
--- a/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts
@@ -34,7 +34,37 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxino_micro>;
+ cd-gpios = <&pio 6 1 0>; /* PG1 */
+ status = "okay";
+ };
+
+ mmc1: mmc@01c10000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ pinctrl-1 = <&mmc1_cd_pin_olinuxino_micro>;
+ cd-gpios = <&pio 6 13 0>; /* PG13 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxino_micro: mmc0_cd_pin@0 {
+ allwinner,pins = "PG1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
+ mmc1_cd_pin_olinuxino_micro: mmc1_cd_pin@0 {
+ allwinner,pins = "PG13";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = "PE3";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a10s.dtsi b/arch/arm/boot/dts/sun5i-a10s.dtsi
index 327e87b..b6d1de0 100644
--- a/arch/arm/boot/dts/sun5i-a10s.dtsi
+++ b/arch/arm/boot/dts/sun5i-a10s.dtsi
@@ -293,6 +293,36 @@
#size-cells = <0>;
};
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -363,6 +393,20 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc1_pins_a: mmc1@0 {
+ allwinner,pins = "PG3","PG4","PG5","PG6","PG7","PG8";
+ allwinner,function = "mmc1";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer@01c20c00 {
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
index fe2ce0a..2f08bb2 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts
@@ -20,7 +20,22 @@
compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxinom>;
+ cd-gpios = <&pio 6 0 0>; /* PG0 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxinom: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
led_pins_olinuxinom: led_pins@0 {
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
index a4ba5ff..a7280f5 100644
--- a/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
+++ b/arch/arm/boot/dts/sun5i-a13-olinuxino.dts
@@ -19,7 +19,22 @@
compatible = "olimex,a13-olinuxino", "allwinner,sun5i-a13";
soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_olinuxino>;
+ cd-gpios = <&pio 6 0 0>; /* PG0 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
+ mmc0_cd_pin_olinuxino: mmc0_cd_pin@0 {
+ allwinner,pins = "PG0";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = "PG9";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun5i-a13.dtsi b/arch/arm/boot/dts/sun5i-a13.dtsi
index f49eb13..040d304 100644
--- a/arch/arm/boot/dts/sun5i-a13.dtsi
+++ b/arch/arm/boot/dts/sun5i-a13.dtsi
@@ -274,6 +274,36 @@
#size-cells = <1>;
ranges;
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -326,6 +356,13 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer@01c20c00 {
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 6/8] ARM: dts: sun4i: Add support for mmc
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8 ++++
arch/arm/boot/dts/sun4i-a10.dtsi | 54 ++++++++++++++++++++++++++++
3 files changed, 70 insertions(+)
diff --git a/arch/arm/boot/dts/sun4i-a10-a1000.dts b/arch/arm/boot/dts/sun4i-a10-a1000.dts
index d4b081d..a879ef3 100644
--- a/arch/arm/boot/dts/sun4i-a10-a1000.dts
+++ b/arch/arm/boot/dts/sun4i-a10-a1000.dts
@@ -35,6 +35,14 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
emac_power_pin_a1000: emac_power_pin@0 {
allwinner,pins = "PH15";
diff --git a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
index b139ee6..20b976a 100644
--- a/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
+++ b/arch/arm/boot/dts/sun4i-a10-cubieboard.dts
@@ -33,6 +33,14 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
led_pins_cubieboard: led_pins@0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi
index 9044c53..cd14961 100644
--- a/arch/arm/boot/dts/sun4i-a10.dtsi
+++ b/arch/arm/boot/dts/sun4i-a10.dtsi
@@ -330,6 +330,46 @@
#size-cells = <0>;
};
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <32>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <33>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <34>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <35>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
intc: interrupt-controller@01c20400 {
compatible = "allwinner,sun4i-ic";
reg = <0x01c20400 0x400>;
@@ -400,6 +440,20 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
};
timer@01c20c00 {
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 5/8] ARM: dts: sun7i: Add support for mmc
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 +++
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++
arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++
4 files changed, 100 insertions(+)
diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
index 5c51cb8..ae800b6 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
@@ -34,6 +34,14 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
led_pins_cubieboard2: led_pins@0 {
allwinner,pins = "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
index f9dcb61..370cef84 100644
--- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
+++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
@@ -19,6 +19,14 @@
compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
soc@01c00000 {
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
led_pins_cubietruck: led_pins@0 {
allwinner,pins = "PH7", "PH11", "PH20", "PH21";
diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
index ead3013..685ec06 100644
--- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
+++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
@@ -34,7 +34,30 @@
};
};
+ mmc0: mmc@01c0f000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ pinctrl-1 = <&mmc0_cd_pin_reference_design>;
+ cd-gpios = <&pio 7 1 0>; /* PH1 */
+ status = "okay";
+ };
+
+ mmc3: mmc@01c12000 {
+ pinctrl-names = "default", "default";
+ pinctrl-0 = <&mmc3_pins_a>;
+ pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
+ cd-gpios = <&pio 7 11 0>; /* PH11 */
+ status = "okay";
+ };
+
pinctrl@01c20800 {
+ mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
+ allwinner,pins = "PH11";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
led_pins_olinuxino: led_pins@0 {
allwinner,pins = "PH2";
allwinner,function = "gpio_out";
diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
index 9ff0948..5b55414 100644
--- a/arch/arm/boot/dts/sun7i-a20.dtsi
+++ b/arch/arm/boot/dts/sun7i-a20.dtsi
@@ -355,6 +355,46 @@
#size-cells = <0>;
};
+ mmc0: mmc@01c0f000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ahb_gates 8>, <&mmc0_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 32 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc1: mmc@01c10000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ahb_gates 9>, <&mmc1_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 33 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@01c11000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c11000 0x1000>;
+ clocks = <&ahb_gates 10>, <&mmc2_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 34 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ mmc3: mmc@01c12000 {
+ compatible = "allwinner,sun5i-a13-mmc";
+ reg = <0x01c12000 0x1000>;
+ clocks = <&ahb_gates 11>, <&mmc3_clk>;
+ clock-names = "ahb", "mod";
+ interrupts = <0 35 4>;
+ bus-width = <4>;
+ status = "disabled";
+ };
+
pio: pinctrl@01c20800 {
compatible = "allwinner,sun7i-a20-pinctrl";
reg = <0x01c20800 0x400>;
@@ -432,6 +472,27 @@
allwinner,drive = <0>;
allwinner,pull = <0>;
};
+
+ mmc0_pins_a: mmc0@0 {
+ allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
+ allwinner,function = "mmc0";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
+
+ mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
+ allwinner,pins = "PH1";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <0>;
+ allwinner,pull = <1>;
+ };
+
+ mmc3_pins_a: mmc3@0 {
+ allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
+ allwinner,function = "mmc3";
+ allwinner,drive = <3>;
+ allwinner,pull = <0>;
+ };
};
timer@01c20c00 {
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
This is based on the driver Allwinner ships in their Android kernel sources.
Initial porting to upstream kernels done by David Lanzendörfer, additional
fixes and cleanups by Hans de Goede.
It uses dma in bus-master mode using a built-in designware idmac controller,
which is identical to the one found in the mmc-dw hosts.
The rest of the host is not identical to mmc-dw.
Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
drivers/mmc/host/Kconfig | 7
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mmc.c | 876 ++++++++++++++++++++++++++++++++++++++++++
drivers/mmc/host/sunxi-mmc.h | 239 +++++++++++
4 files changed, 1124 insertions(+)
create mode 100644 drivers/mmc/host/sunxi-mmc.c
create mode 100644 drivers/mmc/host/sunxi-mmc.h
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 1384f67..7caf266 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -689,3 +689,10 @@ config MMC_REALTEK_PCI
help
Say Y here to include driver code to support SD/MMC card interface
of Realtek PCI-E card reader
+
+config MMC_SUNXI
+ tristate "Allwinner sunxi SD/MMC Host Controller support"
+ depends on ARCH_SUNXI
+ help
+ This selects support for the SD/MMC Host Controller on
+ Allwinner sunxi SoCs.
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 3483b6b..f3c7c243 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -54,6 +54,8 @@ obj-$(CONFIG_MMC_WMT) += wmt-sdmmc.o
obj-$(CONFIG_MMC_REALTEK_PCI) += rtsx_pci_sdmmc.o
+obj-$(CONFIG_MMC_SUNXI) += sunxi-mmc.o
+
obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
new file mode 100644
index 0000000..2dc446c
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.c
@@ -0,0 +1,876 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh-jFKXxz0WcGyYHARAtoI1EgC/G2K4zDHf@public.gmane.org>
+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include <linux/clk/sunxi.h>
+
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+#include <linux/scatterlist.h>
+#include <linux/dma-mapping.h>
+#include <linux/slab.h>
+#include <linux/regulator/consumer.h>
+
+#include <linux/of_address.h>
+#include <linux/of_gpio.h>
+#include <linux/of_platform.h>
+
+#include <linux/mmc/host.h>
+#include <linux/mmc/sd.h>
+#include <linux/mmc/sdio.h>
+#include <linux/mmc/mmc.h>
+#include <linux/mmc/core.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/slot-gpio.h>
+
+#include "sunxi-mmc.h"
+
+static int sunxi_mmc_init_host(struct mmc_host *mmc)
+{
+ u32 rval;
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ int ret;
+
+ ret = clk_prepare_enable(smc_host->clk_ahb);
+ if (ret) {
+ dev_err(mmc_dev(smc_host->mmc), "AHB clk err %d\n", ret);
+ return ret;
+ }
+ ret = clk_prepare_enable(smc_host->clk_mod);
+ if (ret) {
+ dev_err(mmc_dev(smc_host->mmc), "MOD clk err %d\n", ret);
+ clk_disable_unprepare(smc_host->clk_ahb);
+ return ret;
+ }
+
+ /* reset controller */
+ rval = mci_readl(smc_host, REG_GCTRL) | SDXC_HARDWARE_RESET;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ mci_writel(smc_host, REG_FTRGL, 0x20070008);
+ mci_writel(smc_host, REG_TMOUT, 0xffffffff);
+ mci_writel(smc_host, REG_IMASK, smc_host->sdio_imask);
+ mci_writel(smc_host, REG_RINTR, 0xffffffff);
+ mci_writel(smc_host, REG_DBGC, 0xdeb);
+ mci_writel(smc_host, REG_FUNS, 0xceaa0000);
+ mci_writel(smc_host, REG_DLBA, smc_host->sg_dma);
+ rval = mci_readl(smc_host, REG_GCTRL)|SDXC_INTERRUPT_ENABLE_BIT;
+ rval &= ~SDXC_ACCESS_DONE_DIRECT;
+ mci_writel(smc_host, REG_GCTRL, rval);
+
+ return 0;
+}
+
+static void sunxi_mmc_exit_host(struct sunxi_mmc_host *smc_host)
+{
+ mci_writel(smc_host, REG_GCTRL, SDXC_HARDWARE_RESET);
+ clk_disable_unprepare(smc_host->clk_ahb);
+ clk_disable_unprepare(smc_host->clk_mod);
+}
+
+/* /\* UHS-I Operation Modes */
+/* * DS 25MHz 12.5MB/s 3.3V */
+/* * HS 50MHz 25MB/s 3.3V */
+/* * SDR12 25MHz 12.5MB/s 1.8V */
+/* * SDR25 50MHz 25MB/s 1.8V */
+/* * SDR50 100MHz 50MB/s 1.8V */
+/* * SDR104 208MHz 104MB/s 1.8V */
+/* * DDR50 50MHz 50MB/s 1.8V */
+/* * MMC Operation Modes */
+/* * DS 26MHz 26MB/s 3/1.8/1.2V */
+/* * HS 52MHz 52MB/s 3/1.8/1.2V */
+/* * HSDDR 52MHz 104MB/s 3/1.8/1.2V */
+/* * HS200 200MHz 200MB/s 1.8/1.2V */
+/* * */
+/* * Spec. Timing */
+/* * SD3.0 */
+/* * Fcclk Tcclk Fsclk Tsclk Tis Tih odly RTis RTih */
+/* * 400K 2.5us 24M 41ns 5ns 5ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 5ns 5ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 6ns 2ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 6ns 0.8ns 2 6.67ns 3.33ns */
+/* * 104M 9.6ns 600M 1.67ns 3ns 0.8ns 1 7.93ns 1.67ns */
+/* * 208M 4.8ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+
+/* * 25M 40ns 300M 3.33ns 5ns 5ns 2 13.34ns 6.66ns */
+/* * 50M 20ns 300M 3.33ns 6ns 2ns 2 13.34ns 6.66ns */
+/* * 50MDDR 20ns 300M 3.33ns 6ns 0.8ns 1 6.67ns 3.33ns */
+/* * 104M 9.6ns 300M 3.33ns 3ns 0.8ns 0 7.93ns 1.67ns */
+/* * 208M 4.8ns 300M 3.33ns 1.4ns 0.8ns 0 3.13ns 1.67ns */
+
+/* * eMMC4.5 */
+/* * 400K 2.5us 24M 41ns 3ns 3ns 1 2209ns 41ns */
+/* * 25M 40ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50M 20ns 600M 1.67ns 3ns 3ns 3 14.99ns 5.01ns */
+/* * 50MDDR 20ns 600M 1.67ns 2.5ns 2.5ns 2 6.67ns 3.33ns */
+/* * 200M 5ns 600M 1.67ns 1.4ns 0.8ns 1 3.33ns 1.67ns */
+/* *\/ */
+
+static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host,
+ struct mmc_data *data)
+{
+ struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu;
+ struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma;
+ int i, max_len = (1 << host->idma_des_size_bits);
+
+ for (i = 0; i < data->sg_len; i++) {
+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
+ SDXC_IDMAC_DES0_DIC;
+
+ if (data->sg[i].length == max_len)
+ pdes[i].buf_size = 0; /* 0 == max_len */
+ else
+ pdes[i].buf_size = data->sg[i].length;
+
+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
+ }
+
+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
+
+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
+}
+
+static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data)
+{
+ if (data->flags & MMC_DATA_WRITE)
+ return DMA_TO_DEVICE;
+ else
+ return DMA_FROM_DEVICE;
+}
+
+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
+ struct mmc_data *data)
+{
+ u32 dma_len;
+ u32 i;
+ u32 temp;
+ struct scatterlist *sg;
+
+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ if (dma_len == 0) {
+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
+ return -ENOMEM;
+ }
+
+ for_each_sg(data->sg, sg, data->sg_len, i) {
+ if (sg->offset & 3 || sg->length & 3) {
+ dev_err(mmc_dev(smc_host->mmc),
+ "unaligned scatterlist: os %x length %d\n",
+ sg->offset, sg->length);
+ return -EINVAL;
+ }
+ }
+
+ sunxi_mmc_init_idma_des(smc_host, data);
+
+ temp = mci_readl(smc_host, REG_GCTRL);
+ temp |= SDXC_DMA_ENABLE_BIT;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ temp |= SDXC_DMA_RESET;
+ mci_writel(smc_host, REG_GCTRL, temp);
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
+
+ if (!(data->flags & MMC_DATA_WRITE))
+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
+
+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
+
+ return 0;
+}
+
+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
+ struct mmc_request *req)
+{
+ u32 cmd_val = SDXC_START | SDXC_RESPONSE_EXPIRE | SDXC_STOP_ABORT_CMD
+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
+ u32 ri = 0;
+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
+
+ mci_writel(host, REG_CARG, 0);
+ mci_writel(host, REG_CMDR, cmd_val);
+
+ do {
+ ri = mci_readl(host, REG_RINTR);
+ } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
+ time_before(jiffies, expire));
+
+ if (ri & SDXC_INTERRUPT_ERROR_BIT) {
+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
+ if (req->stop)
+ req->stop->resp[0] = -ETIMEDOUT;
+ } else {
+ if (req->stop)
+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+}
+
+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
+{
+ struct mmc_command *cmd = smc_host->mrq->cmd;
+ struct mmc_data *data = smc_host->mrq->data;
+
+ /* For some cmds timeout is normal with sd/mmc cards */
+ if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESPONSE_TIMEOUT &&
+ (cmd->opcode == SD_IO_SEND_OP_COND || cmd->opcode == SD_IO_RW_DIRECT))
+ return;
+
+ dev_err(mmc_dev(smc_host->mmc),
+ "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n",
+ smc_host->mmc->index, cmd->opcode,
+ data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "",
+ smc_host->int_sum & SDXC_RESPONSE_ERROR ? " RE" : "",
+ smc_host->int_sum & SDXC_RESPONSE_CRC_ERROR ? " RCE" : "",
+ smc_host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "",
+ smc_host->int_sum & SDXC_RESPONSE_TIMEOUT ? " RTO" : "",
+ smc_host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "",
+ smc_host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "",
+ smc_host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "",
+ smc_host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "",
+ smc_host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : ""
+ );
+}
+
+static void sunxi_mmc_finalize_request(struct sunxi_mmc_host *host)
+{
+ struct mmc_request *mrq;
+ unsigned long iflags;
+
+ spin_lock_irqsave(&host->lock, iflags);
+
+ mrq = host->mrq;
+ if (!mrq) {
+ spin_unlock_irqrestore(&host->lock, iflags);
+ dev_err(mmc_dev(host->mmc), "no request to finalize\n");
+ return;
+ }
+
+ if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) {
+ sunxi_mmc_dump_errinfo(host);
+ mrq->cmd->error = -ETIMEDOUT;
+ if (mrq->data)
+ mrq->data->error = -ETIMEDOUT;
+ if (mrq->stop)
+ mrq->stop->error = -ETIMEDOUT;
+ } else {
+ if (mrq->cmd->flags & MMC_RSP_136) {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP3);
+ mrq->cmd->resp[1] = mci_readl(host, REG_RESP2);
+ mrq->cmd->resp[2] = mci_readl(host, REG_RESP1);
+ mrq->cmd->resp[3] = mci_readl(host, REG_RESP0);
+ } else {
+ mrq->cmd->resp[0] = mci_readl(host, REG_RESP0);
+ }
+ if (mrq->data)
+ mrq->data->bytes_xfered =
+ mrq->data->blocks * mrq->data->blksz;
+ }
+
+ if (mrq->data) {
+ struct mmc_data *data = mrq->data;
+ u32 temp;
+
+ mci_writel(host, REG_IDST, 0x337);
+ mci_writel(host, REG_DMAC, 0);
+ temp = mci_readl(host, REG_GCTRL);
+ mci_writel(host, REG_GCTRL, temp|SDXC_DMA_RESET);
+ temp &= ~SDXC_DMA_ENABLE_BIT;
+ mci_writel(host, REG_GCTRL, temp);
+ temp |= SDXC_FIFO_RESET;
+ mci_writel(host, REG_GCTRL, temp);
+ dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len,
+ sunxi_mmc_get_dma_dir(data));
+ }
+
+ mci_writel(host, REG_RINTR, 0xffff);
+
+ dev_dbg(mmc_dev(host->mmc), "req done, resp %08x %08x %08x %08x\n",
+ mrq->cmd->resp[0], mrq->cmd->resp[1],
+ mrq->cmd->resp[2], mrq->cmd->resp[3]);
+
+ host->mrq = NULL;
+ host->int_sum = 0;
+ host->wait_dma = 0;
+
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ if (mrq->data && mrq->data->error) {
+ dev_err(mmc_dev(host->mmc),
+ "data error, sending stop command\n");
+ sunxi_mmc_send_manual_stop(host, mrq);
+ }
+
+ mmc_request_done(host->mmc, mrq);
+}
+
+static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id)
+{
+ struct sunxi_mmc_host *host = dev_id;
+ u32 finalize = 0;
+ u32 sdio_int = 0;
+ u32 msk_int;
+ u32 idma_int;
+
+ spin_lock(&host->lock);
+
+ idma_int = mci_readl(host, REG_IDST);
+ msk_int = mci_readl(host, REG_MISTA);
+
+ dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n",
+ host->mrq, msk_int, idma_int);
+
+ if (host->mrq) {
+ if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT)
+ host->wait_dma = 0;
+
+ host->int_sum |= msk_int;
+
+ /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finishing the req */
+ if ((host->int_sum & SDXC_RESPONSE_TIMEOUT) &&
+ !(host->int_sum & SDXC_COMMAND_DONE))
+ mci_writel(host, REG_IMASK,
+ host->sdio_imask | SDXC_COMMAND_DONE);
+ else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT)
+ finalize = 1; /* Don't wait for dma on error */
+ else if (host->int_sum & SDXC_INTERRUPT_DONE_BIT && !host->wait_dma)
+ finalize = 1; /* Done */
+
+ if (finalize) {
+ mci_writel(host, REG_IMASK, host->sdio_imask);
+ mci_writel(host, REG_IDIE, 0);
+ }
+ }
+
+ if (msk_int & SDXC_SDIO_INTERRUPT)
+ sdio_int = 1;
+
+ mci_writel(host, REG_RINTR, msk_int);
+ mci_writel(host, REG_IDST, idma_int);
+
+ spin_unlock(&host->lock);
+
+ if (finalize)
+ tasklet_schedule(&host->tasklet);
+
+ if (sdio_int)
+ mmc_signal_sdio_irq(host->mmc);
+
+ return IRQ_HANDLED;
+}
+
+static void sunxi_mmc_tasklet(unsigned long data)
+{
+ struct sunxi_mmc_host *smc_host = (struct sunxi_mmc_host *) data;
+ sunxi_mmc_finalize_request(smc_host);
+}
+
+static void sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en)
+{
+ unsigned long expire = jiffies + msecs_to_jiffies(2000);
+ u32 rval;
+
+ rval = mci_readl(host, REG_CLKCR);
+ rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON);
+
+ if (oclk_en)
+ rval |= SDXC_CARD_CLOCK_ON;
+
+ if (!host->io_flag)
+ rval |= SDXC_LOW_POWER_ON;
+
+ mci_writel(host, REG_CLKCR, rval);
+
+ rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER;
+ if (host->voltage_switching)
+ rval |= SDXC_VOLTAGE_SWITCH;
+ mci_writel(host, REG_CMDR, rval);
+
+ do {
+ rval = mci_readl(host, REG_CMDR);
+ } while (time_before(jiffies, expire) && (rval & SDXC_START));
+
+ if (rval & SDXC_START) {
+ dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n");
+ host->ferror = 1;
+ }
+}
+
+static void sunxi_mmc_set_clk_dly(struct sunxi_mmc_host *smc_host,
+ u32 oclk_dly, u32 sclk_dly)
+{
+ unsigned long iflags;
+ struct clk_hw *hw = __clk_get_hw(smc_host->clk_mod);
+
+ spin_lock_irqsave(&smc_host->lock, iflags);
+ clk_sunxi_mmc_phase_control(hw, sclk_dly, oclk_dly);
+ spin_unlock_irqrestore(&smc_host->lock, iflags);
+}
+
+struct sunxi_mmc_clk_dly mmc_clk_dly[MMC_CLK_MOD_NUM] = {
+ { MMC_CLK_400K, 0, 7 },
+ { MMC_CLK_25M, 0, 5 },
+ { MMC_CLK_50M, 3, 5 },
+ { MMC_CLK_50MDDR, 2, 4 },
+ { MMC_CLK_50MDDR_8BIT, 2, 4 },
+ { MMC_CLK_100M, 1, 4 },
+ { MMC_CLK_200M, 1, 4 },
+};
+
+static void sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *smc_host,
+ unsigned int rate)
+{
+ u32 newrate;
+ u32 src_clk;
+ u32 oclk_dly;
+ u32 sclk_dly;
+ u32 temp;
+ struct sunxi_mmc_clk_dly *dly = NULL;
+
+ newrate = clk_round_rate(smc_host->clk_mod, rate);
+ if (smc_host->clk_mod_rate == newrate) {
+ dev_dbg(mmc_dev(smc_host->mmc), "clk already %d, rounded %d\n",
+ rate, newrate);
+ return;
+ }
+
+ dev_dbg(mmc_dev(smc_host->mmc), "setting clk to %d, rounded %d\n",
+ rate, newrate);
+
+ /* setting clock rate */
+ clk_disable(smc_host->clk_mod);
+ clk_set_rate(smc_host->clk_mod, newrate);
+ clk_enable(smc_host->clk_mod);
+ smc_host->clk_mod_rate = newrate = clk_get_rate(smc_host->clk_mod);
+ dev_dbg(mmc_dev(smc_host->mmc), "clk is now %d\n", newrate);
+
+ sunxi_mmc_oclk_onoff(smc_host, 0);
+ /* clear internal divider */
+ temp = mci_readl(smc_host, REG_CLKCR);
+ temp &= ~0xff;
+ mci_writel(smc_host, REG_CLKCR, temp);
+
+ /* determine delays */
+ if (rate <= 400000) {
+ dly = &mmc_clk_dly[MMC_CLK_400K];
+ } else if (rate <= 25000000) {
+ dly = &mmc_clk_dly[MMC_CLK_25M];
+ } else if (rate <= 50000000) {
+ if (smc_host->ddr) {
+ if (smc_host->bus_width == 8)
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR_8BIT];
+ else
+ dly = &mmc_clk_dly[MMC_CLK_50MDDR];
+ } else {
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+ }
+ } else if (rate <= 104000000) {
+ dly = &mmc_clk_dly[MMC_CLK_100M];
+ } else if (rate <= 208000000) {
+ dly = &mmc_clk_dly[MMC_CLK_200M];
+ } else {
+ dly = &mmc_clk_dly[MMC_CLK_50M];
+ }
+
+ oclk_dly = dly->oclk_dly;
+ sclk_dly = dly->sclk_dly;
+
+ src_clk = clk_get_rate(clk_get_parent(smc_host->clk_mod));
+
+ if (src_clk >= 300000000 && src_clk <= 400000000) {
+ if (oclk_dly)
+ oclk_dly--;
+ if (sclk_dly)
+ sclk_dly--;
+ }
+
+ sunxi_mmc_set_clk_dly(smc_host, oclk_dly, sclk_dly);
+ sunxi_mmc_oclk_onoff(smc_host, 1);
+
+ /* oclk_onoff sets various irq status bits, clear these */
+ mci_writel(smc_host, REG_RINTR,
+ mci_readl(smc_host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT);
+}
+
+static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ u32 temp;
+ s32 err;
+
+ /* Set the power state */
+ switch (ios->power_mode) {
+ case MMC_POWER_ON:
+ break;
+
+ case MMC_POWER_UP:
+ if (!IS_ERR(host->vmmc)) {
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, ios->vdd);
+ udelay(200);
+ }
+
+ err = sunxi_mmc_init_host(mmc);
+ if (err) {
+ host->ferror = 1;
+ return;
+ }
+ enable_irq(host->irq);
+
+ dev_dbg(mmc_dev(host->mmc), "power on!\n");
+ host->ferror = 0;
+ break;
+
+ case MMC_POWER_OFF:
+ dev_dbg(mmc_dev(host->mmc), "power off!\n");
+ disable_irq(host->irq);
+ sunxi_mmc_exit_host(host);
+ if (!IS_ERR(host->vmmc))
+ mmc_regulator_set_ocr(host->mmc, host->vmmc, 0);
+ host->ferror = 0;
+ break;
+ }
+
+ /* set bus width */
+ switch (ios->bus_width) {
+ case MMC_BUS_WIDTH_1:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH1);
+ host->bus_width = 1;
+ break;
+ case MMC_BUS_WIDTH_4:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH4);
+ host->bus_width = 4;
+ break;
+ case MMC_BUS_WIDTH_8:
+ mci_writel(host, REG_WIDTH, SDXC_WIDTH8);
+ host->bus_width = 8;
+ break;
+ }
+
+ /* set ddr mode */
+ temp = mci_readl(host, REG_GCTRL);
+ if (ios->timing == MMC_TIMING_UHS_DDR50) {
+ temp |= SDXC_DDR_MODE;
+ host->ddr = 1;
+ } else {
+ temp &= ~SDXC_DDR_MODE;
+ host->ddr = 0;
+ }
+ mci_writel(host, REG_GCTRL, temp);
+
+ /* set up clock */
+ if (ios->clock && ios->power_mode) {
+ dev_dbg(mmc_dev(host->mmc), "ios->clock: %d\n", ios->clock);
+ sunxi_mmc_clk_set_rate(host, ios->clock);
+ usleep_range(50000, 55000);
+ }
+}
+
+static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ unsigned long flags;
+ int ret;
+ u32 imask;
+
+ spin_lock_irqsave(&smc_host->lock, flags);
+
+ /* Make sure the controller is in a sane state before enabling irqs */
+ ret = sunxi_mmc_init_host(host->mmc);
+ if (ret) {
+ spin_unlock_irqrestore(&smc_host->lock, flags);
+ return ret;
+ }
+
+ imask = mci_readl(smc_host, REG_IMASK);
+ if (enable) {
+ smc_host->sdio_imask = SDXC_SDIO_INTERRUPT;
+ imask |= SDXC_SDIO_INTERRUPT;
+ } else {
+ smc_host->sdio_imask = 0;
+ imask &= ~SDXC_SDIO_INTERRUPT;
+ }
+ mci_writel(smc_host, REG_IMASK, imask);
+ spin_unlock_irqrestore(&smc_host->lock, flags);
+}
+
+static void sunxi_mmc_hw_reset(struct mmc_host *mmc)
+{
+ struct sunxi_mmc_host *smc_host = mmc_priv(mmc);
+ mci_writel(smc_host, REG_HWRST, 0);
+ udelay(10);
+ mci_writel(smc_host, REG_HWRST, 1);
+ udelay(300);
+}
+
+static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
+{
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+ struct mmc_command *cmd = mrq->cmd;
+ struct mmc_data *data = mrq->data;
+ unsigned long iflags;
+ u32 imask = SDXC_INTERRUPT_ERROR_BIT;
+ u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f);
+ u32 byte_cnt = 0;
+ int ret;
+
+ if (!mmc_gpio_get_cd(mmc) || host->ferror) {
+ dev_dbg(mmc_dev(host->mmc), "no medium present\n");
+ mrq->cmd->error = -ENOMEDIUM;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+
+ if (data) {
+ byte_cnt = data->blksz * data->blocks;
+ mci_writel(host, REG_BLKSZ, data->blksz);
+ mci_writel(host, REG_BCNTR, byte_cnt);
+ ret = sunxi_mmc_prepare_dma(host, data);
+ if (ret < 0) {
+ dev_err(mmc_dev(host->mmc), "prepare DMA failed\n");
+ cmd->error = ret;
+ cmd->data->error = ret;
+ mmc_request_done(host->mmc, mrq);
+ return;
+ }
+ }
+
+ if (cmd->opcode == MMC_GO_IDLE_STATE) {
+ cmd_val |= SDXC_SEND_INIT_SEQUENCE;
+ imask |= SDXC_COMMAND_DONE;
+ }
+
+ if (cmd->opcode == SD_SWITCH_VOLTAGE) {
+ cmd_val |= SDXC_VOLTAGE_SWITCH;
+ imask |= SDXC_VOLTAGE_CHANGE_DONE;
+ host->voltage_switching = 1;
+ sunxi_mmc_oclk_onoff(host, 1);
+ }
+
+ if (cmd->flags & MMC_RSP_PRESENT) {
+ cmd_val |= SDXC_RESPONSE_EXPIRE;
+ if (cmd->flags & MMC_RSP_136)
+ cmd_val |= SDXC_LONG_RESPONSE;
+ if (cmd->flags & MMC_RSP_CRC)
+ cmd_val |= SDXC_CHECK_RESPONSE_CRC;
+
+ if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) {
+ cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER;
+ if (cmd->data->flags & MMC_DATA_STREAM) {
+ imask |= SDXC_AUTO_COMMAND_DONE;
+ cmd_val |= SDXC_SEQUENCE_MODE | SDXC_SEND_AUTO_STOP;
+ }
+ if (cmd->data->stop) {
+ imask |= SDXC_AUTO_COMMAND_DONE;
+ cmd_val |= SDXC_SEND_AUTO_STOP;
+ } else
+ imask |= SDXC_DATA_OVER;
+
+ if (cmd->data->flags & MMC_DATA_WRITE)
+ cmd_val |= SDXC_WRITE;
+ else
+ host->wait_dma = 1;
+ } else
+ imask |= SDXC_COMMAND_DONE;
+ } else
+ imask |= SDXC_COMMAND_DONE;
+
+ dev_dbg(mmc_dev(host->mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n",
+ cmd_val & 0x3f, cmd_val, cmd->arg, imask,
+ mrq->data ? mrq->data->blksz * mrq->data->blocks : 0);
+
+ spin_lock_irqsave(&host->lock, iflags);
+ host->mrq = mrq;
+ mci_writel(host, REG_IMASK, host->sdio_imask | imask);
+ spin_unlock_irqrestore(&host->lock, iflags);
+
+ mci_writel(host, REG_CARG, cmd->arg);
+ mci_writel(host, REG_CMDR, cmd_val);
+}
+
+static const struct of_device_id sunxi_mmc_of_match[] = {
+ { .compatible = "allwinner,sun4i-a10-mmc", },
+ { .compatible = "allwinner,sun5i-a13-mmc", },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match);
+
+static struct mmc_host_ops sunxi_mmc_ops = {
+ .request = sunxi_mmc_request,
+ .set_ios = sunxi_mmc_set_ios,
+ .get_ro = mmc_gpio_get_ro,
+ .get_cd = mmc_gpio_get_cd,
+ .enable_sdio_irq = sunxi_mmc_enable_sdio_irq,
+ .hw_reset = sunxi_mmc_hw_reset,
+};
+
+static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host,
+ struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ int ret;
+
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc"))
+ host->idma_des_size_bits = 13;
+ else
+ host->idma_des_size_bits = 16;
+
+ host->vmmc = devm_regulator_get_optional(&pdev->dev, "vmmc");
+ if (IS_ERR(host->vmmc) && PTR_ERR(host->vmmc) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ host->reg_base = devm_ioremap_resource(&pdev->dev,
+ platform_get_resource(pdev, IORESOURCE_MEM, 0));
+ if (IS_ERR(host->reg_base))
+ return PTR_ERR(host->reg_base);
+
+ host->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
+ if (IS_ERR(host->clk_ahb)) {
+ dev_err(&pdev->dev, "Could not get ahb clock\n");
+ return PTR_ERR(host->clk_ahb);
+ }
+
+ host->clk_mod = devm_clk_get(&pdev->dev, "mod");
+ if (IS_ERR(host->clk_mod)) {
+ dev_err(&pdev->dev, "Could not get mod clock\n");
+ return PTR_ERR(host->clk_mod);
+ }
+
+ /* Make sure the controller is in a sane state before enabling irqs */
+ ret = sunxi_mmc_init_host(host->mmc);
+ if (ret)
+ return ret;
+
+ host->irq = platform_get_irq(pdev, 0);
+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
+ "sunxi-mmc", host);
+ if (ret == 0)
+ disable_irq(host->irq);
+
+ /* And put it back in reset */
+ sunxi_mmc_exit_host(host);
+
+ return ret;
+}
+
+static int sunxi_mmc_probe(struct platform_device *pdev)
+{
+ struct sunxi_mmc_host *host;
+ struct mmc_host *mmc;
+ int ret;
+
+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
+ if (!mmc) {
+ dev_err(&pdev->dev, "mmc alloc host failed\n");
+ return -ENOMEM;
+ }
+
+ ret = mmc_of_parse(mmc);
+ if (ret)
+ goto error_free_host;
+
+ host = mmc_priv(mmc);
+ host->mmc = mmc;
+ spin_lock_init(&host->lock);
+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
+
+ ret = sunxi_mmc_resource_request(host, pdev);
+ if (ret)
+ goto error_free_host;
+
+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
+ &host->sg_dma, GFP_KERNEL);
+ if (!host->sg_cpu) {
+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
+ ret = -ENOMEM;
+ goto error_free_host;
+ }
+
+ mmc->ops = &sunxi_mmc_ops;
+ mmc->max_blk_count = 8192;
+ mmc->max_blk_size = 4096;
+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
+ /* 400kHz ~ 50MHz */
+ mmc->f_min = 400000;
+ mmc->f_max = 50000000;
+ /* available voltages */
+ if (!IS_ERR(host->vmmc))
+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
+ else
+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+
+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
+
+ ret = mmc_add_host(mmc);
+
+ if (ret)
+ goto error_free_dma;
+
+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
+ platform_set_drvdata(pdev, mmc);
+ return 0;
+
+error_free_dma:
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+error_free_host:
+ mmc_free_host(mmc);
+ return ret;
+}
+
+static int sunxi_mmc_remove(struct platform_device *pdev)
+{
+ struct mmc_host *mmc = platform_get_drvdata(pdev);
+ struct sunxi_mmc_host *host = mmc_priv(mmc);
+
+ mmc_remove_host(mmc);
+ sunxi_mmc_exit_host(host);
+ tasklet_disable(&host->tasklet);
+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
+ mmc_free_host(mmc);
+
+ return 0;
+}
+
+static struct platform_driver sunxi_mmc_driver = {
+ .driver = {
+ .name = "sunxi-mmc",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
+ },
+ .probe = sunxi_mmc_probe,
+ .remove = sunxi_mmc_remove,
+};
+module_platform_driver(sunxi_mmc_driver);
+
+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>");
+MODULE_ALIAS("platform:sunxi-mmc");
diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
new file mode 100644
index 0000000..cbd6d49
--- /dev/null
+++ b/drivers/mmc/host/sunxi-mmc.h
@@ -0,0 +1,239 @@
+/*
+ * Driver for sunxi SD/MMC host controllers
+ * (C) Copyright 2014-2015 Reuuimlla Technology Co., Ltd.
+ * (C) Copyright 2014-2015 Aaron Maoye <leafy.myeh-jFKXxz0WcGyYHARAtoI1EgC/G2K4zDHf@public.gmane.org>
+ * (C) Copyright 2014-2015 O2S GmbH <www.o2s.ch>
+ * (C) Copyright 2014-2015 David Lanzendörfer <david.lanzendoerfer@o2s.ch>
+ * (C) Copyright 2014-2015 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#ifndef __SUNXI_MCI_H__
+#define __SUNXI_MCI_H__
+
+/* register offset define */
+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
+#define SDXC_REG_CHDA (0x90)
+#define SDXC_REG_CBDA (0x94)
+
+#define mci_readl(host, reg) \
+ readl((host)->reg_base + SDXC_##reg)
+#define mci_writel(host, reg, value) \
+ writel((value), (host)->reg_base + SDXC_##reg)
+
+/* global control register bits */
+#define SDXC_SOFT_RESET BIT(0)
+#define SDXC_FIFO_RESET BIT(1)
+#define SDXC_DMA_RESET BIT(2)
+#define SDXC_HARDWARE_RESET (SDXC_SOFT_RESET|SDXC_FIFO_RESET|SDXC_DMA_RESET)
+#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
+#define SDXC_DMA_ENABLE_BIT BIT(5)
+#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
+#define SDXC_POSEDGE_LATCH_DATA BIT(9)
+#define SDXC_DDR_MODE BIT(10)
+#define SDXC_MEMORY_ACCESS_DONE BIT(29)
+#define SDXC_ACCESS_DONE_DIRECT BIT(30)
+#define SDXC_ACCESS_BY_AHB BIT(31)
+#define SDXC_ACCESS_BY_DMA (0U << 31)
+/* clock control bits */
+#define SDXC_CARD_CLOCK_ON BIT(16)
+#define SDXC_LOW_POWER_ON BIT(17)
+/* bus width */
+#define SDXC_WIDTH1 (0)
+#define SDXC_WIDTH4 (1)
+#define SDXC_WIDTH8 (2)
+/* smc command bits */
+#define SDXC_RESPONSE_EXPIRE BIT(6)
+#define SDXC_LONG_RESPONSE BIT(7)
+#define SDXC_CHECK_RESPONSE_CRC BIT(8)
+#define SDXC_DATA_EXPIRE BIT(9)
+#define SDXC_WRITE BIT(10)
+#define SDXC_SEQUENCE_MODE BIT(11)
+#define SDXC_SEND_AUTO_STOP BIT(12)
+#define SDXC_WAIT_PRE_OVER BIT(13)
+#define SDXC_STOP_ABORT_CMD BIT(14)
+#define SDXC_SEND_INIT_SEQUENCE BIT(15)
+#define SDXC_UPCLK_ONLY BIT(21)
+#define SDXC_READ_CEATA_DEV BIT(22)
+#define SDXC_CCS_EXPIRE BIT(23)
+#define SDXC_ENABLE_BIT_BOOT BIT(24)
+#define SDXC_ALT_BOOT_OPTIONS BIT(25)
+#define SDXC_BOOT_ACK_EXPIRE BIT(26)
+#define SDXC_BOOT_ABORT BIT(27)
+#define SDXC_VOLTAGE_SWITCH BIT(28)
+#define SDXC_USE_HOLD_REGISTER BIT(29)
+#define SDXC_START BIT(31)
+/* interrupt bits */
+#define SDXC_RESPONSE_ERROR BIT(1)
+#define SDXC_COMMAND_DONE BIT(2)
+#define SDXC_DATA_OVER BIT(3)
+#define SDXC_TX_DATA_REQUEST BIT(4)
+#define SDXC_RX_DATA_REQUEST BIT(5)
+#define SDXC_RESPONSE_CRC_ERROR BIT(6)
+#define SDXC_DATA_CRC_ERROR BIT(7)
+#define SDXC_RESPONSE_TIMEOUT BIT(8)
+#define SDXC_DATA_TIMEOUT BIT(9)
+#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
+#define SDXC_FIFO_RUN_ERROR BIT(11)
+#define SDXC_HARD_WARE_LOCKED BIT(12)
+#define SDXC_START_BIT_ERROR BIT(13)
+#define SDXC_AUTO_COMMAND_DONE BIT(14)
+#define SDXC_END_BIT_ERROR BIT(15)
+#define SDXC_SDIO_INTERRUPT BIT(16)
+#define SDXC_CARD_INSERT BIT(30)
+#define SDXC_CARD_REMOVE BIT(31)
+#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESPONSE_ERROR | SDXC_RESPONSE_CRC_ERROR | \
+ SDXC_DATA_CRC_ERROR | SDXC_RESPONSE_TIMEOUT | \
+ SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
+ SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | \
+ SDXC_END_BIT_ERROR) /* 0xbbc2 */
+#define SDXC_INTERRUPT_DONE_BIT (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
+ SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
+/* status */
+#define SDXC_RXWL_FLAG BIT(0)
+#define SDXC_TXWL_FLAG BIT(1)
+#define SDXC_FIFO_EMPTY BIT(2)
+#define SDXC_FIFO_FULL BIT(3)
+#define SDXC_CARD_PRESENT BIT(8)
+#define SDXC_CARD_DATA_BUSY BIT(9)
+#define SDXC_DATA_FSM_BUSY BIT(10)
+#define SDXC_DMA_REQUEST BIT(31)
+#define SDXC_FIFO_SIZE (16)
+/* Function select */
+#define SDXC_CEATA_ON (0xceaaU << 16)
+#define SDXC_SEND_IRQ_RESPONSE BIT(0)
+#define SDXC_SDIO_READ_WAIT BIT(1)
+#define SDXC_ABORT_READ_DATA BIT(2)
+#define SDXC_SEND_CCSD BIT(8)
+#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
+#define SDXC_CEATA_DEV_INTERRUPT_ENABLE_BIT BIT(10)
+/* IDMA controller bus mod bit field */
+#define SDXC_IDMAC_SOFT_RESET BIT(0)
+#define SDXC_IDMAC_FIX_BURST BIT(1)
+#define SDXC_IDMAC_IDMA_ON BIT(7)
+#define SDXC_IDMAC_REFETCH_DES BIT(31)
+/* IDMA status bit field */
+#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
+#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
+#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
+#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
+#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_TX BIT(10)
+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_RX BIT(10)
+#define SDXC_IDMAC_IDLE (0U << 13)
+#define SDXC_IDMAC_SUSPEND (1U << 13)
+#define SDXC_IDMAC_DESC_READ (2U << 13)
+#define SDXC_IDMAC_DESC_CHECK (3U << 13)
+#define SDXC_IDMAC_READ_REQUEST_WAIT (4U << 13)
+#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5U << 13)
+#define SDXC_IDMAC_READ (6U << 13)
+#define SDXC_IDMAC_WRITE (7U << 13)
+#define SDXC_IDMAC_DESC_CLOSE (8U << 13)
+
+/*
+* If the idma-des-size-bits of property is ie 13, bufsize bits are:
+* Bits 0-12: buf1 size
+* Bits 13-25: buf2 size
+* Bits 26-31: not used
+* Since we only ever set buf1 size, we can simply store it directly.
+*/
+#define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */
+#define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */
+#define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */
+#define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */
+#define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */
+#define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */
+#define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */
+
+struct sunxi_idma_des {
+ u32 config;
+ u32 buf_size;
+ u32 buf_addr_ptr1;
+ u32 buf_addr_ptr2;
+};
+
+struct sunxi_mmc_host {
+ struct mmc_host *mmc;
+ struct regulator *vmmc;
+
+ /* IO mapping base */
+ void __iomem *reg_base;
+
+ spinlock_t lock;
+ struct tasklet_struct tasklet;
+
+ /* clock management */
+ struct clk *clk_ahb;
+ struct clk *clk_mod;
+
+ /* ios information */
+ u32 clk_mod_rate;
+ u32 bus_width;
+ u32 idma_des_size_bits;
+ u32 ddr;
+ u32 voltage_switching;
+
+ /* irq */
+ int irq;
+ u32 int_sum;
+ u32 sdio_imask;
+
+ /* flags */
+ u32 power_on:1;
+ u32 io_flag:1;
+ u32 wait_dma:1;
+
+ dma_addr_t sg_dma;
+ void *sg_cpu;
+
+ struct mmc_request *mrq;
+ u32 ferror;
+};
+
+#define MMC_CLK_400K 0
+#define MMC_CLK_25M 1
+#define MMC_CLK_50M 2
+#define MMC_CLK_50MDDR 3
+#define MMC_CLK_50MDDR_8BIT 4
+#define MMC_CLK_100M 5
+#define MMC_CLK_200M 6
+#define MMC_CLK_MOD_NUM 7
+
+struct sunxi_mmc_clk_dly {
+ u32 mode;
+ u32 oclk_dly;
+ u32 sclk_dly;
+};
+
+#endif
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 3/8] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
From: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
---
include/linux/clk/sunxi.h | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
create mode 100644 include/linux/clk/sunxi.h
diff --git a/include/linux/clk/sunxi.h b/include/linux/clk/sunxi.h
new file mode 100644
index 0000000..1ef5c89
--- /dev/null
+++ b/include/linux/clk/sunxi.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright 2013 - Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __LINUX_CLK_SUNXI_H_
+#define __LINUX_CLK_SUNXI_H_
+
+#include <linux/clk.h>
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output);
+
+#endif
^ permalink raw reply related
* [PATCH v6 2/8] clk: sunxi: Implement MMC phase control
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
From: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
---
drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
1 file changed, 35 insertions(+)
diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
index abb6c5a..33b9977 100644
--- a/drivers/clk/sunxi/clk-sunxi.c
+++ b/drivers/clk/sunxi/clk-sunxi.c
@@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
/**
+ * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
+ */
+
+void clk_sunxi_mmc_phase_control(struct clk_hw *hw, u8 sample, u8 output)
+{
+ #define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
+ #define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
+
+ struct clk_composite *composite = to_clk_composite(hw);
+ struct clk_hw *rate_hw = composite->rate_hw;
+ struct clk_factors *factors = to_clk_factors(rate_hw);
+ unsigned long flags = 0;
+ u32 reg;
+
+ if (factors->lock)
+ spin_lock_irqsave(factors->lock, flags);
+
+ reg = readl(factors->reg);
+
+ /* set sample clock phase control */
+ reg &= ~(0x7 << 20);
+ reg |= ((sample & 0x7) << 20);
+
+ /* set output clock phase control */
+ reg &= ~(0x7 << 8);
+ reg |= ((output & 0x7) << 8);
+
+ writel(reg, factors->reg);
+
+ if (factors->lock)
+ spin_unlock_irqrestore(factors->lock, flags);
+}
+
+
+/**
* sunxi_factors_clk_setup() - Setup function for factor clocks
*/
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 1/8] clk: sunxi: factors: automatic reparenting support
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140215233011.30460.27261.stgit-GPtPHOohwllnsqa/0SyWJQ@public.gmane.org>
From: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
This commit implements .determine_rate, so that our factor clocks can be
reparented when needed.
Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
---
drivers/clk/sunxi/clk-factors.c | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/drivers/clk/sunxi/clk-factors.c b/drivers/clk/sunxi/clk-factors.c
index 9e23264..3806d97 100644
--- a/drivers/clk/sunxi/clk-factors.c
+++ b/drivers/clk/sunxi/clk-factors.c
@@ -77,6 +77,41 @@ static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
return rate;
}
+static long clk_factors_determine_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *best_parent_rate,
+ struct clk **best_parent_p)
+{
+ struct clk *clk = hw->clk, *parent, *best_parent = NULL;
+ int i, num_parents;
+ unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
+
+ /* find the parent that can help provide the fastest rate <= rate */
+ num_parents = __clk_get_num_parents(clk);
+ for (i = 0; i < num_parents; i++) {
+ parent = clk_get_parent_by_index(clk, i);
+ if (!parent)
+ continue;
+ if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
+ parent_rate = __clk_round_rate(parent, rate);
+ else
+ parent_rate = __clk_get_rate(parent);
+
+ child_rate = clk_factors_round_rate(hw, rate, &parent_rate);
+
+ if (child_rate <= rate && child_rate > best_child_rate) {
+ best_parent = parent;
+ best = parent_rate;
+ best_child_rate = child_rate;
+ }
+ }
+
+ if (best_parent)
+ *best_parent_p = best_parent;
+ *best_parent_rate = best;
+
+ return best_child_rate;
+}
+
static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
@@ -113,6 +148,7 @@ static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
}
const struct clk_ops clk_factors_ops = {
+ .determine_rate = clk_factors_determine_rate,
.recalc_rate = clk_factors_recalc_rate,
.round_rate = clk_factors_round_rate,
.set_rate = clk_factors_set_rate,
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply related
* [PATCH v6 0/8]
From: David Lanzendörfer @ 2014-02-15 23:33 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo, Maxime Ripard,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Hello
The following patchset adds support for the SD/MMC host found in the Allwinner SoCs.
It contains all the necessary modifications for clock environment and also the device
tree script modification which add it to all the boards using it.
The clock environment function needed for phase offset configuration has
been proposed and implemented by Emilio.
A lot of work and cleanup has been done by Hans de Goede. Special thanks to him!
This patchset is the 4th attempt to send this driver upstream.
Changes since v1:
-Using mmc_of_parse instead of diy dt parsing
-Adding nodes for all mmc controller to the dtsi files,
including sofar unused controllers
-Using generic GPIO slot library for WP/CD
-Adding additional MMC device nodes into DTSI files
Changes since v2:
-Add missing Signed-off-by tags
-Stop using __raw_readl / __raw_writel so that barriers are properly used
-Adding missing new lines
-Adding missing patch for automatic reparenting of clocks
Changes since v3:
-Move clk_enable / disable into host_init / exit (Hans)
-Fix hang on boot caused by irq storm (Hans)
Changes since v4:
-moving sunxi-mci.{c/h} to sunxi-mmc.{c/h}
-removing camel cases from the defines in sunxi-mmc.h
-moving defines out of the struct definition
since this is bad coding style
-adding documentation for the device tree binding
Changes since v5:
-adding host initialization for when the sdio irq is enabled
(just to make sure having a defined state at all time)
-add mmc support fixup: set pullup on cd pins
-fixup: Don't set MMC_CAP_NEEDS_POLL / MMC_CAP_4_BIT_DATA
---
David Lanzendörfer (5):
ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
ARM: dts: sun7i: Add support for mmc
ARM: dts: sun4i: Add support for mmc
ARM: dts: sun5i: Add support for mmc
ARM: sunxi: Add documentation for driver for SD/MMC hosts found on Allwinner sunxi SoCs
Emilio López (2):
clk: sunxi: factors: automatic reparenting support
clk: sunxi: Implement MMC phase control
Hans de Goede (1):
ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
.../devicetree/bindings/mmc/sunxi-mmc.txt | 32 +
arch/arm/boot/dts/sun4i-a10-a1000.dts | 8
arch/arm/boot/dts/sun4i-a10-cubieboard.dts | 8
arch/arm/boot/dts/sun4i-a10.dtsi | 54 +
arch/arm/boot/dts/sun5i-a10s-olinuxino-micro.dts | 30 +
arch/arm/boot/dts/sun5i-a10s.dtsi | 44 +
arch/arm/boot/dts/sun5i-a13-olinuxino-micro.dts | 15
arch/arm/boot/dts/sun5i-a13-olinuxino.dts | 15
arch/arm/boot/dts/sun5i-a13.dtsi | 37 +
arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8
arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8
arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +
arch/arm/boot/dts/sun7i-a20.dtsi | 61 +
drivers/clk/sunxi/clk-factors.c | 36 +
drivers/clk/sunxi/clk-sunxi.c | 35 +
drivers/mmc/host/Kconfig | 7
drivers/mmc/host/Makefile | 2
drivers/mmc/host/sunxi-mmc.c | 876 ++++++++++++++++++++
drivers/mmc/host/sunxi-mmc.h | 239 +++++
include/linux/clk/sunxi.h | 22 +
20 files changed, 1560 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sunxi-mmc.txt
create mode 100644 drivers/mmc/host/sunxi-mmc.c
create mode 100644 drivers/mmc/host/sunxi-mmc.h
create mode 100644 include/linux/clk/sunxi.h
--
Signature
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/groups/opt_out.
^ permalink raw reply
* Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache
From: Nicolas Pitre @ 2014-02-15 22:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Andrew Lunn, Jason Cooper, Sebastian Hesselbarth, Gregory Clement,
linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <201402152212.02580.arnd-r2nGTMty4D4@public.gmane.org>
On Sat, 15 Feb 2014, Arnd Bergmann wrote:
> On Saturday 15 February 2014, Andrew Lunn wrote:
> > None of the _defconfig's ever turn on
> > CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
> > not find any usage of it.
> >
> > So i see two options:
> >
> > 1) Remove the wr-override from the DT binding and use
> > CACHE_FEROCEON_L2_WRITETHROUGH.
> >
> > 2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
> > the right thing at runtime.
> >
> > I suspect i will go for 1), it is simpler.
>
> Yes, fair enough. I'd hope we could just kill the option altogether,
> but it's probably hard to find anyone who would remember what it
> was introduced for, unless Nico knows.
There was a time when we didn't know what cache mode was the best
performance wise. The right answer is "it depends on the work load" of
course. Hence it was made optional for people to play with and choose
for themselves.
Nicolas
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Russell King - ARM Linux @ 2014-02-15 22:03 UTC (permalink / raw)
To: Tomasz Figa
Cc: Arnd Bergmann, linux-arm-kernel, mark.rutland, devicetree,
Ulf Hansson, Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc,
Chris Ball, robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam,
Sascha Hauer
In-Reply-To: <52FFDDA6.6020607@gmail.com>
On Sat, Feb 15, 2014 at 10:35:34PM +0100, Tomasz Figa wrote:
> If you change your hardware in an incompatible way and such change can't
> be detected automatically (i.e. the chip is non-discoverable) then I
> don't know how you could let the OS know about this change in any other
> way than providing it with the information it needs.
I'm not talking about such major changes. I'm talking about minor
changes where the SDIO device may change, but everything else stays
compatible.
Why should such a situation be forced down the path of having a different
DT file to specify the different SDIO device, when the SDIO device itself
is discoverable? For example, BRCM4329 to a BRCM4330.
Look, let's think seriously about this. Let's say we have a platform
where there's already two different DT files - one for models with a
single CPU, and a different DT file for a quad CPU. This is fine,
users generally know which model they have, and can choose between
the two without much difficulty - because this information is part of
their decision making process when buying the product.
How, let's say that the SDIO chip becomes obsolete, and has to be
replaced later in the production run. The external form, fit and
function remain the same, it's just the internals have now changed.
Now, if we go down Arnd's route, then we need to have not two DT files,
but now four. One for single CPU with BRCM4329, quad CPU with the
same, and then those two with a BRCM4330.
Now, how does the user choose which DT file is right for their device?
Do they:
(a) ask the manufacturer, leading to hundreds of support requests.
(b) open the device up, invalidating the warranty to find out what chips
are inside.
(c) something else (please specify)
What I'm trying to get here is the perspective from the other side - the
/user/ perspective, and the problems that making the wrong decision here
brings. It has huge implications, and can make the difference between
"shall we use a mainline kernel, or shall we keep our own kernel/use an
ancient vendor's kernel with our own private hacks so we can reduce our
support costs".
I'm already seeing exactly this kind of problem on the horizon, because
I know of a platform where there was a bug in part of the hardware -
and enabling support for some interface features screws up on those
with the hardware bug. So, there's already _four_ DT files to think
about for this hardware platform. If Arnd's suggestion goes forward,
then we end up with _six_. It doesn't take much to see where this
leads.
Meanwhile, these kinds of differences could be dealt with using
/board specific code/ in the old days to read on-SoC configuration and
adjust things appropriately - and transparently to the user.
DT is _our_ convenience as kernel hackers. It is a big _inconvenience_
to the user when a particular product goes through a revision.
So, never ever forget that "oh, we can just deal with it with a different
DT file" makes our lives easier at the expense of our users, and without
users, we've lost.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Tomasz Figa @ 2014-02-15 21:35 UTC (permalink / raw)
To: Russell King - ARM Linux, Arnd Bergmann
Cc: linux-arm-kernel, mark.rutland, devicetree, Ulf Hansson,
Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc, Chris Ball,
robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam, Sascha Hauer
In-Reply-To: <20140215205159.GL30257@n2100.arm.linux.org.uk>
On 15.02.2014 21:52, Russell King - ARM Linux wrote:
> On Sat, Feb 15, 2014 at 05:21:11PM +0100, Arnd Bergmann wrote:
>> On Saturday 15 February 2014 14:22:30 Tomasz Figa wrote:
>>> On 15.02.2014 14:09, Arnd Bergmann wrote:
>>>
>>>> For spi-mode SDIO devices I'm assuming it's similar, except that
>>>> you'd describe the actual SDIO device in the board info rather than
>>>> create a fake SDIO controller. Still not discoverable unless I'm
>>>> missing your point.
>>>
>>> I'm not sure if we should assume that SPI = MMC over SPI. I believe
>>> there might be a custom protocol involved as well.
>>
>> In case of SD/MMC, you essentially have three separate command sets:
>> SPI, MMC and SD, and each of them has multiple versions. MMC and SD
>> compatible devices generally also support the SPI command set (IIRC
>> it is required,
>
> SPI support is mandatory for SDIO as well.
>
> SDIO has CIS (remember card information structures... like PCMCIA)
> which identifies the various different logical functions of the device,
> giving class information, vendor information etc.
>
> So... certainly the type of the attached device is discoverable even
> on SPI.
It certainly is, assuming that you properly configure the
non-discoverable part.
>> If a device supports both SDIO and SPI, I think a straightforward
>> implementation would be to use the exact same command set, but
>> you are right that this isn't the only possibility, and the SD/MMC
>> shows how they can be slightly different already.
>
> Given that the SPI mode is mandatory for SDIO cards, why would you
> also implement another SPI mode with different commands?
Well, isn't this embedded world we're living in a constant race between
software and hardware engineers, where the former invent more and more
generic solutions to cover wider ranges of hardware with nice
abstractions, while the latter invent more quirky hardware designs to
destroy the effort of the former? Cute embedded nonsense hacks and so...
>>> Stepping aside from SPI, I already gave an example of a WLAN chip that
>>> supports multiple control busses [1]. In addition to the commonly used
>>> SDIO, it supports USB and HSIC as well:
>>>
>>> [1] http://www.marvell.com/wireless/assets/marvell_avastar_88w8797.pdf
>>>
>>> Moreover, some of Samsung boards use HSIC to communicate with modem
>>> chips, which have exactly the same problem as we're trying to solve here
>>> - they need to be powered on to be discovered.
>>
>> Thanks, this definitely makes a good example. I see that it also
>> supports SPI mode for SDIO as mentioned in your link.
>
> Well, USB is another discoverable bus. As HSIC is a derivative of USB,
> I'd be surprised if it weren't discoverable there too.
>
> So, out of everything identified so far, we have no undiscoverable buses.
>
>> Agreed. Putting the same chip on USB or HSIC has the exact same
>> requirements, since we also have a discoverable bus, but actually
>> finding the device likely involves some power-on sequencing before
>> the bus controller can find it.
>
> That's partly the nature of integrating something onto a board where you
> want maximal power savings. It's basically that dreaded word which
> software people seem to hate: "embedded".
>
This isn't something we can ignore, though.
>> * Arnd's proposal (change bus code to probe nonstandard devices
>> from DT if we can't easily detect them):
>> + Matches what we already do for PCI (at least on powerpc)
>> and AMBA/Primecell devices: If a device can't be probed
>> using the standard method, we treat it as nondiscoverable
>> and describe it using DT.
>> + Devices can have arbitrary complex requirements without
>> impacting the core, since all code is contained in the
>> driver for the nonstandard device.
>> + Properties that are required for probing and runtime
>> configuration only have to be set once (e.g. you may
>> need clk_get() for probing and clk_set_rate() for
>> runtime-pm).
>> + Devices that have alternative bus interfaces like 88w8797
>> can implement the power-on code in a central place per
>> driver, and can reuse the code they have for nondiscoverable
>> buses on the buses that are normally discoverable but
>> broken here.
>> - Still need to modify each subsystem to have alternate
>> ways of probing, and match up devices later.
>> - Has to be implemented in each driver that needs it, making
>> it harder to share code for drivers with the same need
>> (e.g. every device that just needs an external reset
>> trigger).
>
> - requires different DT if the chip is changed, which causes problems
> for users to identify which out of zillions of DT files they should
> use for their exact platform.
That's how things work in embedded world, unfortunately. As Arnd stated
in one of his previous replies, different chips use to have different
power-up sequences and set of data the driver needs to know.
If you change your hardware in an incompatible way and such change can't
be detected automatically (i.e. the chip is non-discoverable) then I
don't know how you could let the OS know about this change in any other
way than providing it with the information it needs.
> - have to work out how to match up the fake device with a probed device
> when it becomes available: existing SDIO drivers all assume that the
> card has been through a fairly complex initialisation sequence already.
> - multi-function SDIO is much harder to deal with since you have mutliple
> drivers involved, and the SDIO device as a whole needs initialisation
> before anyone can drive it.
> - adds complexity to the SDIO drivers; they would have to know whether
> they're embedded or on a plug-in card.
>
The three points above could be eliminated by adopting the solution I
proposed [1]. Moreover it could be analogically implemented for other
bus types and use almost identical DT bindings.
[1] http://thread.gmane.org/gmane.linux.kernel.mmc/24728/focus=24864
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache
From: Arnd Bergmann @ 2014-02-15 21:12 UTC (permalink / raw)
To: Andrew Lunn
Cc: Jason Cooper, Sebastian Hesselbarth, Gregory Clement, linux ARM,
devicetree-u79uwXL29TY76Z2rM5mHXA, Nicolas Pitre
In-Reply-To: <20140215135930.GA26088-g2DYL2Zd6BY@public.gmane.org>
On Saturday 15 February 2014, Andrew Lunn wrote:
> None of the _defconfig's ever turn on
> CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
> not find any usage of it.
>
> So i see two options:
>
> 1) Remove the wr-override from the DT binding and use
> CACHE_FEROCEON_L2_WRITETHROUGH.
>
> 2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
> the right thing at runtime.
>
> I suspect i will go for 1), it is simpler.
Yes, fair enough. I'd hope we could just kill the option altogether,
but it's probably hard to find anyone who would remember what it
was introduced for, unless Nico knows.
Git history points to
commit 4360bb41920ffacd4a935fa692768129ee5bef4e
Author: Ronen Shitrit <rshitrit-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Date: Tue Sep 23 15:28:10 2008 +0300
[ARM] Kirkwood: add support for L2 cache WB/WT selection
Feroceon L2 cache can work in eighther write through or write back mode
on Kirkwood. Add the option to configure this mode according to Kconfig.
Signed-off-by: Ronen Shitrit <rshitrit-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Nicolas Pitre <nico-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Arnd
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Russell King - ARM Linux @ 2014-02-15 20:52 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Tomasz Figa, linux-arm-kernel, mark.rutland, devicetree,
Ulf Hansson, Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc,
Chris Ball, robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam,
Sascha Hauer
In-Reply-To: <1528854.BAQRr94nzx@wuerfel>
On Sat, Feb 15, 2014 at 05:21:11PM +0100, Arnd Bergmann wrote:
> On Saturday 15 February 2014 14:22:30 Tomasz Figa wrote:
> > On 15.02.2014 14:09, Arnd Bergmann wrote:
> >
> > > For spi-mode SDIO devices I'm assuming it's similar, except that
> > > you'd describe the actual SDIO device in the board info rather than
> > > create a fake SDIO controller. Still not discoverable unless I'm
> > > missing your point.
> >
> > I'm not sure if we should assume that SPI = MMC over SPI. I believe
> > there might be a custom protocol involved as well.
>
> In case of SD/MMC, you essentially have three separate command sets:
> SPI, MMC and SD, and each of them has multiple versions. MMC and SD
> compatible devices generally also support the SPI command set (IIRC
> it is required,
SPI support is mandatory for SDIO as well.
SDIO has CIS (remember card information structures... like PCMCIA)
which identifies the various different logical functions of the device,
giving class information, vendor information etc.
So... certainly the type of the attached device is discoverable even
on SPI.
> If a device supports both SDIO and SPI, I think a straightforward
> implementation would be to use the exact same command set, but
> you are right that this isn't the only possibility, and the SD/MMC
> shows how they can be slightly different already.
Given that the SPI mode is mandatory for SDIO cards, why would you
also implement another SPI mode with different commands?
> > Stepping aside from SPI, I already gave an example of a WLAN chip that
> > supports multiple control busses [1]. In addition to the commonly used
> > SDIO, it supports USB and HSIC as well:
> >
> > [1] http://www.marvell.com/wireless/assets/marvell_avastar_88w8797.pdf
> >
> > Moreover, some of Samsung boards use HSIC to communicate with modem
> > chips, which have exactly the same problem as we're trying to solve here
> > - they need to be powered on to be discovered.
>
> Thanks, this definitely makes a good example. I see that it also
> supports SPI mode for SDIO as mentioned in your link.
Well, USB is another discoverable bus. As HSIC is a derivative of USB,
I'd be surprised if it weren't discoverable there too.
So, out of everything identified so far, we have no undiscoverable buses.
> Agreed. Putting the same chip on USB or HSIC has the exact same
> requirements, since we also have a discoverable bus, but actually
> finding the device likely involves some power-on sequencing before
> the bus controller can find it.
That's partly the nature of integrating something onto a board where you
want maximal power savings. It's basically that dreaded word which
software people seem to hate: "embedded".
> * Arnd's proposal (change bus code to probe nonstandard devices
> from DT if we can't easily detect them):
> + Matches what we already do for PCI (at least on powerpc)
> and AMBA/Primecell devices: If a device can't be probed
> using the standard method, we treat it as nondiscoverable
> and describe it using DT.
> + Devices can have arbitrary complex requirements without
> impacting the core, since all code is contained in the
> driver for the nonstandard device.
> + Properties that are required for probing and runtime
> configuration only have to be set once (e.g. you may
> need clk_get() for probing and clk_set_rate() for
> runtime-pm).
> + Devices that have alternative bus interfaces like 88w8797
> can implement the power-on code in a central place per
> driver, and can reuse the code they have for nondiscoverable
> buses on the buses that are normally discoverable but
> broken here.
> - Still need to modify each subsystem to have alternate
> ways of probing, and match up devices later.
> - Has to be implemented in each driver that needs it, making
> it harder to share code for drivers with the same need
> (e.g. every device that just needs an external reset
> trigger).
- requires different DT if the chip is changed, which causes problems
for users to identify which out of zillions of DT files they should
use for their exact platform.
- have to work out how to match up the fake device with a probed device
when it becomes available: existing SDIO drivers all assume that the
card has been through a fairly complex initialisation sequence already.
- multi-function SDIO is much harder to deal with since you have mutliple
drivers involved, and the SDIO device as a whole needs initialisation
before anyone can drive it.
- adds complexity to the SDIO drivers; they would have to know whether
they're embedded or on a plug-in card.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* Re: [PATCH v5 1/6] spmi: Linux driver framework for SPMI
From: Greg Kroah-Hartman @ 2014-02-15 19:23 UTC (permalink / raw)
To: Josh Cartwright
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, Sagar Dharia,
Gilad Avidov, Michael Bohan, Kenneth Heitke, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala, devicetree
In-Reply-To: <1391468739-20987-2-git-send-email-joshc@codeaurora.org>
On Mon, Feb 03, 2014 at 05:05:33PM -0600, Josh Cartwright wrote:
> From: Kenneth Heitke <kheitke@codeaurora.org>
>
> System Power Management Interface (SPMI) is a specification
> developed by the MIPI (Mobile Industry Process Interface) Alliance
> optimized for the real time control of Power Management ICs (PMIC).
>
> SPMI is a two-wire serial interface that supports up to 4 master
> devices and up to 16 logical slaves.
>
> The framework supports message APIs, multiple busses (1 controller
> per bus) and multiple clients/slave devices per controller.
>
> Signed-off-by: Kenneth Heitke <kheitke@codeaurora.org>
> Signed-off-by: Michael Bohan <mbohan@codeaurora.org>
> Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Looks good, nice bus code.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Arnd Bergmann @ 2014-02-15 16:21 UTC (permalink / raw)
To: Tomasz Figa
Cc: linux-arm-kernel, Russell King - ARM Linux, mark.rutland,
devicetree, Ulf Hansson, Pawel Moll, Ian Campbell, Tomasz Figa,
linux-mmc, Chris Ball, robh+dt, Kumar Gala, Olof Johansson,
Fabio Estevam, Sascha Hauer
In-Reply-To: <52FF6A16.5080201@gmail.com>
On Saturday 15 February 2014 14:22:30 Tomasz Figa wrote:
> On 15.02.2014 14:09, Arnd Bergmann wrote:
>
> > For spi-mode SDIO devices I'm assuming it's similar, except that
> > you'd describe the actual SDIO device in the board info rather than
> > create a fake SDIO controller. Still not discoverable unless I'm
> > missing your point.
>
> I'm not sure if we should assume that SPI = MMC over SPI. I believe
> there might be a custom protocol involved as well.
In case of SD/MMC, you essentially have three separate command sets:
SPI, MMC and SD, and each of them has multiple versions. MMC and SD
compatible devices generally also support the SPI command set (IIRC
it is required, but I'm not completely sure), and on the bus
the main difference seems to be that you have only 1-bit serial
signalling, while MMC also supports 4-bit and 8-bit parallel
transmission.
If a device supports both SDIO and SPI, I think a straightforward
implementation would be to use the exact same command set, but
you are right that this isn't the only possibility, and the SD/MMC
shows how they can be slightly different already.
> Stepping aside from SPI, I already gave an example of a WLAN chip that
> supports multiple control busses [1]. In addition to the commonly used
> SDIO, it supports USB and HSIC as well:
>
> [1] http://www.marvell.com/wireless/assets/marvell_avastar_88w8797.pdf
>
> Moreover, some of Samsung boards use HSIC to communicate with modem
> chips, which have exactly the same problem as we're trying to solve here
> - they need to be powered on to be discovered.
Thanks, this definitely makes a good example. I see that it also
supports SPI mode for SDIO as mentioned in your link.
> So I really don't think we should be limiting this to MMC alone by any
> means.
Agreed. Putting the same chip on USB or HSIC has the exact same
requirements, since we also have a discoverable bus, but actually
finding the device likely involves some power-on sequencing before
the bus controller can find it.
> Now I don't really know why we want that badly to represent low level
> control parts of such devices as children of control buses of their
> enumerable parts. Could you tell me what benefits it has to justify the
> added complexity of having to instantiate fake devices in respective
> devices, even though they can be fully detected later?
It's not that I "badly want" to do it one way or another, I'm just
trying to find arguments either way, since as Russell points out
whatever we decide to do in DT is what we're stuck with for the
long term future.
Let me try to summarize what we found so far:
* Common aspects:
* we need a way to attach properties for run-time configuration
to devices on discoverable buses when the configuration
is not discoverable. In your 88w8797 example, this includes
the use of the GPIO pins, runtime power management (clocks,
regulators) and the attached codecs.
* We may want to connect the same device to either a discoverable
or a nondiscoverable bus, ideally using the same binding and
sharing code whereever possible.
* Olof's proposal (add properties or a child node to the host
controller node with just power-on sequencing information):
+ We only need one implementation for each bus, possibly shared
across buses to some degree, and can handle lots of devices
without having to touch their individual drivers.
+ A logical extension of things we already do on SD cards
(CD/WP GPIOs, external clocks and voltages supplied to
standard compliant devices as part of the normal probing)
- The shared code may get rather complex to deal with all
possible corner cases we run into over the years.
- Somewhat harder to do if you have to attach the power
information to a device node for a USB hub port, rather
than an SDIO controller that only has one slave device.
* Arnd's proposal (change bus code to probe nonstandard devices
from DT if we can't easily detect them):
+ Matches what we already do for PCI (at least on powerpc)
and AMBA/Primecell devices: If a device can't be probed
using the standard method, we treat it as nondiscoverable
and describe it using DT.
+ Devices can have arbitrary complex requirements without
impacting the core, since all code is contained in the
driver for the nonstandard device.
+ Properties that are required for probing and runtime
configuration only have to be set once (e.g. you may
need clk_get() for probing and clk_set_rate() for
runtime-pm).
+ Devices that have alternative bus interfaces like 88w8797
can implement the power-on code in a central place per
driver, and can reuse the code they have for nondiscoverable
buses on the buses that are normally discoverable but
broken here.
- Still need to modify each subsystem to have alternate
ways of probing, and match up devices later.
- Has to be implemented in each driver that needs it, making
it harder to share code for drivers with the same need
(e.g. every device that just needs an external reset
trigger).
Arnd
^ permalink raw reply
* Re: [PATCH 1/2] clk: fixed-rate: use full DT node name
From: Emilio López @ 2014-02-15 15:18 UTC (permalink / raw)
To: Stephen Warren, Mike Turquette
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1392358613-19962-1-git-send-email-swarren-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
Hello Stephen,
El 14/02/14 03:16, Stephen Warren escribió:
> clk-fixed-rate currently names clocks according to a node's name without
> the unit address. When faced with the legal and technically correct DT
> structure below, this causes rgistration attempts for 3 clocks with the
> same name, 2 of which fail.
>
> clocks {
> compatible = "simple-bus";
> #address-cells = <1>;
> #size-cells = <0>;
>
> clk_mmc: clock@0 {
> compatible = "fixed-clock";
> reg = <0>;
> ...
> clk_i2c: clock@1 {
> compatible = "fixed-clock";
> reg = <1>;
> ...
> clk_spi: clock@2 {
> compatible = "fixed-clock";
> reg = <2>;
> ...
>
> Solve this by naming the clocks after the full node name rather than the
> short version (e.g. /clocks/clock@0).
An alternative that doesn't require any change in the driver would be to
use the optional but recommended clock-output-names property from the
common clock binding.
Your DT would then look something like the following
> ...
> clk_mmc: clk@0 {
> compatible = "fixed-clock";
> clock-output-names = "mmc";
> ...
> clk_i2c: clk@1 {
> compatible = "fixed-clock";
> clock-output-names = "i2c";
> ...
> clk_spi: clk@2 {
> compatible = "fixed-clock";
> clock-output-names = "spi";
> ...
Cheers,
Emilio
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 01/17] Documentation: i2c: describe devicetree method for instantiating devices
From: Wolfram Sang @ 2014-02-15 14:48 UTC (permalink / raw)
To: linux-i2c
Cc: devicetree, linux-arm-kernel, Rob Landley, linux-doc,
linux-kernel
In-Reply-To: <1392026654-5343-2-git-send-email-wsa@the-dreams.de>
[-- Attachment #1: Type: text/plain, Size: 222 bytes --]
On Mon, Feb 10, 2014 at 11:03:55AM +0100, Wolfram Sang wrote:
> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
> Cc: devicetree@vger.kernel.org
> Cc: linux-arm-kernel@lists.infradead.org
Applied to for-current, thanks!
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache
From: Andrew Lunn @ 2014-02-15 13:59 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Andrew Lunn, Jason Cooper, Sebastian Hesselbarth, Gregory Clement,
linux ARM, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2979047.tn4oVevojb@wuerfel>
On Sat, Feb 15, 2014 at 02:23:23PM +0100, Arnd Bergmann wrote:
> On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote:
> > Instantiate the L2 cache from DT. Indicate in DT where the cache
> > control register is and if write through should be made.
> >
> > Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> > cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >
>
> I guess this answers part of my question for patch 5, but I also
> wonder if the run-time setting is correct now with the hardcoded
> #ifdef in arch/arm/mm/proc-feroceon.S checkign for the
> Kconfig option. Presumably the code should match whatever is
> set in the cache control register.
Humm, yes, good point.
None of the _defconfig's ever turn on
CACHE_FEROCEON_L2_WRITETHROUGH. I also did a quick google and could
not find any usage of it.
So i see two options:
1) Remove the wr-override from the DT binding and use
CACHE_FEROCEON_L2_WRITETHROUGH.
2) Remove CACHE_FEROCEON_L2_WRITETHROUGH and make proc-feroceon.S do
the right thing at runtime.
I suspect i will go for 1), it is simpler.
Thanks
Andrew
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/2] mfd: twl4030-madc: Add devicetree support.
From: Belisko Marek @ 2014-02-15 13:37 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Rob Herring, Pawel Moll, Mark Rutland,
ijc+devicetree@hellion.org.uk, Kumar Gala, Rob Landley,
Russell King - ARM Linux, Grant Likely,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org, LKML,
linux-arm-kernel, Dr. H. Nikolaus Schaller
In-Reply-To: <20140214174040.GB26969@earth.universe>
Hi Sebastian,
On Fri, Feb 14, 2014 at 6:40 PM, Sebastian Reichel <sre@ring0.de> wrote:
> Hi Marek,
>
> I have prepared a patchset, which adds DT bindings for twl4030-madc
> using the standard IIO DT API. I have not yet send the patchset,
> since I have not yet found the time to test the patchset. I will
> send them as RFC now.
Great. I'll look on that today evening and test on gta04 board. Thanks.
I think my patch can be dropped :).
>
> -- Sebastian
BR,
marek
--
as simple and primitive as possible
-------------------------------------------------
Marek Belisko - OPEN-NANDRA
Freelance Developer
Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
twitter: #opennandra
web: http://open-nandra.com
^ permalink raw reply
* Re: [RFCv1 2/4] mfd: twl4030-madc: Add DT support and convert to IIO framework
From: Belisko Marek @ 2014-02-15 13:31 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Sebastian Reichel, Jonathan Cameron, Lee Jones, Samuel Ortiz,
Lars-Peter Clausen, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Grant Likely, LKML,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-iio-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1392403586-30540-2-git-send-email-sre-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
Hi Sebastian,
On Fri, Feb 14, 2014 at 7:46 PM, Sebastian Reichel <sre-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org> wrote:
> This converts twl4030-madc module to use the Industrial IO ADC
> framework and adds device tree support.
>
> Signed-off-by: Sebastian Reichel <sre-8fiUuRrzOP0dnm+yROfE0A@public.gmane.org>
> ---
> drivers/mfd/twl4030-madc.c | 121 ++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 114 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/mfd/twl4030-madc.c b/drivers/mfd/twl4030-madc.c
> index 5458561..4da61c4 100644
> --- a/drivers/mfd/twl4030-madc.c
> +++ b/drivers/mfd/twl4030-madc.c
> @@ -47,6 +47,10 @@
> #include <linux/gfp.h>
> #include <linux/err.h>
>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/machine.h>
> +#include <linux/iio/driver.h>
> +
> /*
> * struct twl4030_madc_data - a container for madc info
> * @dev - pointer to device structure for madc
> @@ -59,10 +63,72 @@ struct twl4030_madc_data {
> struct device *dev;
> struct mutex lock; /* mutex protecting this data structure */
> struct twl4030_madc_request requests[TWL4030_MADC_NUM_METHODS];
> + bool use_second_irq;
> int imr;
> int isr;
> };
>
> +static int twl4030_madc_read(struct iio_dev *iio_dev,
> + const struct iio_chan_spec *chan,
> + int *val, int *val2, long mask)
> +{
> + struct twl4030_madc_data *madc = iio_priv(iio_dev);
> + struct twl4030_madc_request req;
> + int channel = chan->channel;
> + int ret;
> +
> + req.method = madc->use_second_irq ? TWL4030_MADC_SW2 : TWL4030_MADC_SW1;
> +
> + req.channels = BIT(channel);
> + req.active = 0;
> + req.func_cb = NULL;
> + req.raw = (mask & IIO_CHAN_INFO_PROCESSED) ? false : true;
> + req.do_avg = (mask & IIO_CHAN_INFO_AVERAGE_RAW) ? true : false;
> +
> + ret = twl4030_madc_conversion(&req);
> + if (ret < 0)
> + return ret;
> +
> + *val = req.rbuf[channel];
> +
> + return IIO_VAL_INT;
> +}
> +
> +static const struct iio_info twl4030_madc_iio_info = {
> + .read_raw = &twl4030_madc_read,
> + .driver_module = THIS_MODULE,
> +};
> +
> +#define ADC_CHANNEL(_channel, _type, _name, _mask) { \
> + .type = _type, \
> + .scan_type = IIO_ST('u', 10, 16, 0), \
> + .channel = _channel, \
> + .info_mask_separate = _mask, \
> + .datasheet_name = _name, \
> + .indexed = 1, \
> +}
> +
> +static const struct iio_chan_spec twl4030_madc_iio_channels[] = {
> + ADC_CHANNEL(0, IIO_VOLTAGE, "ADCIN0", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(1, IIO_TEMP, "ADCIN1", BIT(IIO_CHAN_INFO_PROCESSED) |
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(2, IIO_VOLTAGE, "ADCIN2", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(3, IIO_VOLTAGE, "ADCIN3", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(4, IIO_VOLTAGE, "ADCIN4", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(5, IIO_VOLTAGE, "ADCIN5", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(6, IIO_VOLTAGE, "ADCIN6", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(7, IIO_VOLTAGE, "ADCIN7", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(8, IIO_VOLTAGE, "ADCIN8", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(9, IIO_VOLTAGE, "ADCIN9", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(10, IIO_CURRENT, "ADCIN10", BIT(IIO_CHAN_INFO_PROCESSED) |
> + BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(11, IIO_VOLTAGE, "ADCIN11", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(12, IIO_VOLTAGE, "ADCIN12", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(13, IIO_VOLTAGE, "ADCIN13", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(14, IIO_VOLTAGE, "ADCIN14", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> + ADC_CHANNEL(15, IIO_VOLTAGE, "ADCIN15", BIT(IIO_CHAN_INFO_AVERAGE_RAW)),
> +};
> +
> static struct twl4030_madc_data *twl4030_madc;
>
> struct twl4030_prescale_divider_ratios {
> @@ -702,28 +768,49 @@ static int twl4030_madc_probe(struct platform_device *pdev)
> {
> struct twl4030_madc_data *madc;
> struct twl4030_madc_platform_data *pdata = dev_get_platdata(&pdev->dev);
> + struct device_node *np = pdev->dev.of_node;
> int irq, ret;
> u8 regval;
> + struct iio_dev *iio_dev = NULL;
>
> - if (!pdata) {
> + if (!pdata && !np) {
> dev_err(&pdev->dev, "platform_data not available\n");
> return -EINVAL;
> }
> - madc = devm_kzalloc(&pdev->dev, sizeof(*madc), GFP_KERNEL);
> - if (!madc)
> +
> + iio_dev = devm_iio_device_alloc(&pdev->dev,
> + sizeof(struct twl4030_madc_data));
> + if (!iio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> return -ENOMEM;
> + }
>
> + madc = iio_priv(iio_dev);
> madc->dev = &pdev->dev;
>
> + iio_dev->name = dev_name(&pdev->dev);
> + iio_dev->dev.parent = &pdev->dev;
> + iio_dev->dev.of_node = pdev->dev.of_node;
> + iio_dev->info = &twl4030_madc_iio_info;
> + iio_dev->modes = INDIO_DIRECT_MODE;
> + iio_dev->channels = twl4030_madc_iio_channels;
> + iio_dev->num_channels = 16;
> +
> /*
> * Phoenix provides 2 interrupt lines. The first one is connected to
> * the OMAP. The other one can be connected to the other processor such
> * as modem. Hence two separate ISR and IMR registers.
> */
> - madc->imr = (pdata->irq_line == 1) ?
> + if (pdata)
> + madc->use_second_irq = pdata->irq_line != 1;
> + else
> + madc->use_second_irq = false;
Can we add some property to use second IRQ also in DT?
> +
> + madc->imr = (madc->use_second_irq == 1) ?
> TWL4030_MADC_IMR1 : TWL4030_MADC_IMR2;
> - madc->isr = (pdata->irq_line == 1) ?
> + madc->isr = (madc->use_second_irq == 1) ?
> TWL4030_MADC_ISR1 : TWL4030_MADC_ISR2;
> +
> ret = twl4030_madc_set_power(madc, 1);
> if (ret < 0)
> return ret;
> @@ -768,7 +855,7 @@ static int twl4030_madc_probe(struct platform_device *pdev)
> }
> }
>
> - platform_set_drvdata(pdev, madc);
> + platform_set_drvdata(pdev, iio_dev);
> mutex_init(&madc->lock);
>
> irq = platform_get_irq(pdev, 0);
> @@ -780,7 +867,15 @@ static int twl4030_madc_probe(struct platform_device *pdev)
> goto err_i2c;
> }
> twl4030_madc = madc;
> +
> + ret = iio_device_register(iio_dev);
> + if (ret) {
> + dev_dbg(&pdev->dev, "could not register iio device\n");
> + goto err_i2c;
> + }
> +
> return 0;
> +
> err_i2c:
> twl4030_madc_set_current_generator(madc, 0, 0);
> err_current_generator:
> @@ -790,20 +885,32 @@ err_current_generator:
>
> static int twl4030_madc_remove(struct platform_device *pdev)
> {
> - struct twl4030_madc_data *madc = platform_get_drvdata(pdev);
> + struct iio_dev *iio_dev = platform_get_drvdata(pdev);
> + struct twl4030_madc_data *madc = iio_priv(iio_dev);
>
> twl4030_madc_set_current_generator(madc, 0, 0);
> twl4030_madc_set_power(madc, 0);
>
> + iio_device_unregister(iio_dev);
> +
> return 0;
> }
>
> +#ifdef CONFIG_OF
> +static const struct of_device_id twl_madc_of_match[] = {
> + {.compatible = "ti,twl4030-madc", },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, twl_madc_of_match);
> +#endif
> +
> static struct platform_driver twl4030_madc_driver = {
> .probe = twl4030_madc_probe,
> .remove = twl4030_madc_remove,
> .driver = {
> .name = "twl4030_madc",
> .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(twl_madc_of_match),
> },
> };
>
> --
> 1.8.5.3
>
BR,
marek
--
as simple and primitive as possible
-------------------------------------------------
Marek Belisko - OPEN-NANDRA
Freelance Developer
Ruska Nova Ves 219 | Presov, 08005 Slovak Republic
Tel: +421 915 052 184
skype: marekwhite
twitter: #opennandra
web: http://open-nandra.com
^ permalink raw reply
* Re: [PATCH v2 10/23] ARM: MM: Add DT binding for Feroceon L2 cache
From: Arnd Bergmann @ 2014-02-15 13:23 UTC (permalink / raw)
To: Andrew Lunn
Cc: Jason Cooper, Sebastian Hesselbarth, Gregory Clement, linux ARM,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1392459621-24003-11-git-send-email-andrew-g2DYL2Zd6BY@public.gmane.org>
On Saturday 15 February 2014 11:20:08 Andrew Lunn wrote:
> Instantiate the L2 cache from DT. Indicate in DT where the cache
> control register is and if write through should be made.
>
> Signed-off-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
I guess this answers part of my question for patch 5, but I also
wonder if the run-time setting is correct now with the hardcoded
#ifdef in arch/arm/mm/proc-feroceon.S checkign for the
Kconfig option. Presumably the code should match whatever is
set in the cache control register.
Arnd
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Tomasz Figa @ 2014-02-15 13:22 UTC (permalink / raw)
To: Arnd Bergmann, linux-arm-kernel
Cc: Russell King - ARM Linux, mark.rutland, devicetree, Ulf Hansson,
Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc, Chris Ball,
robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam, Sascha Hauer
In-Reply-To: <1580658.FIe4en5bEU@wuerfel>
On 15.02.2014 14:09, Arnd Bergmann wrote:
> On Saturday 15 February 2014 12:27:33 Russell King - ARM Linux wrote:
>> On Sat, Feb 15, 2014 at 01:18:02PM +0100, Arnd Bergmann wrote:
>>> If a wlan adapter has both SPI and SDIO front-ends, the external
>>> dependencies (reset, clock, voltage, ...) will be the same, and
>>> from the kernel perspective the main difference is that SPI cannot
>>> be probed at all, while SDIO can be probed as long as the device
>>> is powered on already.
>>
>> Remember that MMC/SD/SDIO cards can be driven by either a MMC host
>> interface, or a SPI interface. Both are probe-able.
>
> I knew about MMC/SD cards being required to understand simple SPI,
> I wasn't sure about SDIO. My understanding however is that you
> have to use the mmc_spi host driver to actually use MMC/SD devices
> as a block device, and that requires having either a DT description
> for the host or an spi_board_info, which I would not consider
> discoverable.
>
> For spi-mode SDIO devices I'm assuming it's similar, except that
> you'd describe the actual SDIO device in the board info rather than
> create a fake SDIO controller. Still not discoverable unless I'm
> missing your point.
I'm not sure if we should assume that SPI = MMC over SPI. I believe
there might be a custom protocol involved as well.
Stepping aside from SPI, I already gave an example of a WLAN chip that
supports multiple control busses [1]. In addition to the commonly used
SDIO, it supports USB and HSIC as well:
[1] http://www.marvell.com/wireless/assets/marvell_avastar_88w8797.pdf
Moreover, some of Samsung boards use HSIC to communicate with modem
chips, which have exactly the same problem as we're trying to solve here
- they need to be powered on to be discovered.
So I really don't think we should be limiting this to MMC alone by any
means.
Now I don't really know why we want that badly to represent low level
control parts of such devices as children of control buses of their
enumerable parts. Could you tell me what benefits it has to justify the
added complexity of having to instantiate fake devices in respective
devices, even though they can be fully detected later?
Best regards,
Tomasz
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Arnd Bergmann @ 2014-02-15 13:09 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Russell King - ARM Linux, mark.rutland, devicetree, Ulf Hansson,
Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc, Tomasz Figa,
Chris Ball, robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam,
Sascha Hauer
In-Reply-To: <20140215122733.GK30257@n2100.arm.linux.org.uk>
On Saturday 15 February 2014 12:27:33 Russell King - ARM Linux wrote:
> On Sat, Feb 15, 2014 at 01:18:02PM +0100, Arnd Bergmann wrote:
> > If a wlan adapter has both SPI and SDIO front-ends, the external
> > dependencies (reset, clock, voltage, ...) will be the same, and
> > from the kernel perspective the main difference is that SPI cannot
> > be probed at all, while SDIO can be probed as long as the device
> > is powered on already.
>
> Remember that MMC/SD/SDIO cards can be driven by either a MMC host
> interface, or a SPI interface. Both are probe-able.
I knew about MMC/SD cards being required to understand simple SPI,
I wasn't sure about SDIO. My understanding however is that you
have to use the mmc_spi host driver to actually use MMC/SD devices
as a block device, and that requires having either a DT description
for the host or an spi_board_info, which I would not consider
discoverable.
For spi-mode SDIO devices I'm assuming it's similar, except that
you'd describe the actual SDIO device in the board info rather than
create a fake SDIO controller. Still not discoverable unless I'm
missing your point.
Arnd
^ permalink raw reply
* Re: [PATCH 1/3] mmc: add support for power-on sequencing through DT
From: Russell King - ARM Linux @ 2014-02-15 12:27 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel, mark.rutland, devicetree, Ulf Hansson,
Pawel Moll, Ian Campbell, Tomasz Figa, linux-mmc, Tomasz Figa,
Chris Ball, robh+dt, Kumar Gala, Olof Johansson, Fabio Estevam,
Sascha Hauer
In-Reply-To: <3871646.18hjUjnpmg@wuerfel>
On Sat, Feb 15, 2014 at 01:18:02PM +0100, Arnd Bergmann wrote:
> If a wlan adapter has both SPI and SDIO front-ends, the external
> dependencies (reset, clock, voltage, ...) will be the same, and
> from the kernel perspective the main difference is that SPI cannot
> be probed at all, while SDIO can be probed as long as the device
> is powered on already.
Remember that MMC/SD/SDIO cards can be driven by either a MMC host
interface, or a SPI interface. Both are probe-able.
--
FTTC broadband for 0.8mile line: 5.8Mbps down 500kbps up. Estimation
in database were 13.1 to 19Mbit for a good line, about 7.5+ for a bad.
Estimate before purchase was "up to 13.2Mbit".
^ permalink raw reply
* Re: [PATCH v3 2/6] iio: pulse: add TI ECAP driver
From: Jonathan Cameron @ 2014-02-15 12:19 UTC (permalink / raw)
To: Matt Porter, Grant Likely, Rob Herring, Benoît Cousson,
Tony Lindgren, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Thierry Reding
Cc: Linux IIO List, Linux Kernel Mailing List, Devicetree List,
Linux PWM List, Linux OMAP List, Linux ARM Kernel List
In-Reply-To: <1391626901-31684-3-git-send-email-mporter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 05/02/14 19:01, Matt Porter wrote:
> Adds support for capturing PWM signals using the TI ECAP peripheral.
> This driver supports triggered buffer capture of pulses on multiple
> ECAP instances. In addition, the driver supports configurable polarity
> of the signal to be captured.
>
> Signed-off-by: Matt Porter <mporter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Ignoring the ABI questions - there are a few bits and bobs inline.
Sorry again that it took me so long to take a look at this.
Ouch, still far too much unread email in my inbox.
> ---
> drivers/iio/pulse/Kconfig | 20 ++
> drivers/iio/pulse/Makefile | 6 +
> drivers/iio/pulse/tiecap.c | 491 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 517 insertions(+)
> create mode 100644 drivers/iio/pulse/Kconfig
> create mode 100644 drivers/iio/pulse/Makefile
> create mode 100644 drivers/iio/pulse/tiecap.c
>
> diff --git a/drivers/iio/pulse/Kconfig b/drivers/iio/pulse/Kconfig
> new file mode 100644
> index 0000000..9864d4b
> --- /dev/null
> +++ b/drivers/iio/pulse/Kconfig
> @@ -0,0 +1,20 @@
> +#
> +# Pulse Capture Devices
> +#
> +# When adding new entries keep the list in alphabetical order
> +
> +menu "Pulse Capture Devices"
> +
> +config IIO_TIECAP
> + tristate "TI ECAP Pulse Capture"
> + depends on SOC_AM33XX
Looks like it rather more specifically depends on the pwm supplied on
that soc. I haven't checked but a dependency on that would seem
more logical to me. Pitty it doesn't have a generic interface, because
then we could relax the dependency and it would allow you to get a lot
more build coverage.
> + select IIO_BUFFER
> + select IIO_TRIGGERED_BUFFER
> + help
> + If you say yes here you get support for the TI ECAP peripheral
> + in pulse capture mode.
> +
> + This driver can also be built as a module. If so, the module
> + will be called tiecap
> +
> +endmenu
> diff --git a/drivers/iio/pulse/Makefile b/drivers/iio/pulse/Makefile
> new file mode 100644
> index 0000000..94d4b00
> --- /dev/null
> +++ b/drivers/iio/pulse/Makefile
> @@ -0,0 +1,6 @@
> +#
> +# Makefile for IIO PWM Capture Devices
> +#
> +
> +# When adding new entries keep the list in alphabetical order
> +obj-$(CONFIG_IIO_TIECAP) += tiecap.o
> diff --git a/drivers/iio/pulse/tiecap.c b/drivers/iio/pulse/tiecap.c
> new file mode 100644
> index 0000000..fd96745
> --- /dev/null
> +++ b/drivers/iio/pulse/tiecap.c
> @@ -0,0 +1,491 @@
> +/*
> + * ECAP IIO pulse capture driver
> + *
> + * Copyright (C) 2014 Linaro Limited
> + * Author: Matt Porter <mporter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/err.h>
> +#include <linux/iio/buffer.h>
> +#include <linux/iio/iio.h>
> +#include <linux/iio/sysfs.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/iio/trigger_consumer.h>
> +#include <linux/iio/triggered_buffer.h>
> +#include <linux/io.h>
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_runtime.h>
> +
> +#include "../../pwm/pwm-tipwmss.h"
If we need functions from in there, surely it should be in
include/linux/pwm instead of burried in the driver tree?
> +
> +/* ECAP regs and bits */
Please add prefixes to all of these. i.e. #define ECAP_CAP1
etc.
This is to avoid the possibility of a naming clash if these rather
short names ever turn in in one of the headers included above.
> +#define CAP1 0x08
> +#define CAP2 0x0c
> +#define ECCTL1 0x28
> +#define ECCTL1_RUN_FREE BIT(15)
> +#define ECCTL1_CAPLDEN BIT(8)
> +#define ECCTL1_CAP2POL BIT(2)
> +#define ECCTL1_CTRRST1 BIT(1)
> +#define ECCTL1_CAP1POL BIT(0)
> +#define ECCTL2 0x2a
> +#define ECCTL2_SYNCO_SEL_DIS BIT(7)
> +#define ECCTL2_TSCTR_FREERUN BIT(4)
> +#define ECCTL2_REARM BIT(3)
> +#define ECCTL2_STOP_WRAP_2 BIT(1)
> +#define ECEINT 0x2c
> +#define ECFLG 0x2e
> +#define ECCLR 0x30
> +#define ECINT_CTRCMP BIT(7)
> +#define ECINT_CTRPRD BIT(6)
> +#define ECINT_CTROVF BIT(5)
> +#define ECINT_CEVT4 BIT(4)
> +#define ECINT_CEVT3 BIT(3)
> +#define ECINT_CEVT2 BIT(2)
> +#define ECINT_CEVT1 BIT(1)
> +#define ECINT_ALL (ECINT_CTRCMP | \
> + ECINT_CTRPRD | \
> + ECINT_CTROVF | \
> + ECINT_CEVT4 | \
> + ECINT_CEVT3 | \
> + ECINT_CEVT2 | \
> + ECINT_CEVT1)
> +
> +/* ECAP driver flags */
> +#define ECAP_POLARITY_HIGH BIT(1)
> +#define ECAP_ENABLED BIT(0)
> +
> +struct ecap_context {
> + u32 cap1;
> + u32 cap2;
> + u16 ecctl1;
> + u16 ecctl2;
> + u16 eceint;
> +};
> +
> +struct ecap_state {
> + unsigned long flags;
> + unsigned int clk_rate;
> + void __iomem *regs;
> + u32 *buf;
> + struct ecap_context ctx;
> +};
> +
> +#define dev_to_ecap_state(d) iio_priv(dev_to_iio_dev(d))
> +
> +static const struct iio_chan_spec ecap_channels[] = {
> + {
> + .type = IIO_PULSE,
> + .info_mask_separate =
> + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE),
> + .scan_index = 0,
> + .scan_type = {
> + .sign = 'u',
> + .realbits = 32,
> + .storagebits = 32,
> + .endianness = IIO_LE,
> + },
> + },
> + IIO_CHAN_SOFT_TIMESTAMP(1)
> +};
> +
> +static ssize_t ecap_attr_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct ecap_state *state = dev_to_ecap_state(dev);
> +
> + return sprintf(buf, "%d\n",
> + test_bit(ECAP_POLARITY_HIGH, &state->flags));
> +}
> +
This function needs a name indicating what attr. There may be only one
now, but who knows in future.
> +static ssize_t ecap_attr_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf,
> + size_t len)
> +{
> + int ret;
> + bool val;
> + struct ecap_state *state = dev_to_ecap_state(dev);
> +
> + if (test_bit(ECAP_ENABLED, &state->flags))
> + return -EINVAL;
> +
Not obvious how a boolean value corresponds to a polarity. If we change to
the abi I suggested earlier, I'd have this as in_waveformX_inverted.
> + ret = strtobool(buf, &val);
> + if (ret)
> + return ret;
> +
> + if (val)
> + set_bit(ECAP_POLARITY_HIGH, &state->flags);
> + else
> + clear_bit(ECAP_POLARITY_HIGH, &state->flags);
> +
> + return len;
> +}
> +
> +static IIO_DEVICE_ATTR(pulse_polarity, S_IRUGO | S_IWUSR,
> + ecap_attr_show, ecap_attr_store, 0);
> +
> +static struct attribute *ecap_attributes[] = {
> + &iio_dev_attr_pulse_polarity.dev_attr.attr,
> + NULL,
> +};
> +
> +static struct attribute_group ecap_attribute_group = {
> + .attrs = ecap_attributes,
> +};
> +
> +static int ecap_read_raw(struct iio_dev *idev,
> + struct iio_chan_spec const *ch, int *val,
> + int *val2, long mask)
> +{
> + struct ecap_state *state = iio_priv(idev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
Just don't provide the BIT(IIO_CHAN_INFO_RAW) in the info_mask_separate
and there will be no userspace interface. Thus indicating it can't be
read better than returning a 'fake' value.
> + /*
> + * Always return 0 as a pulse width sample
> + * is only valid in a triggered condition
> + */
> + *val = 0;
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SCALE:
> + *val = 0;
> + *val2 = NSEC_PER_SEC / state->clk_rate;
> + return IIO_VAL_INT_PLUS_NANO;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static const struct iio_info ecap_info = {
> + .driver_module = THIS_MODULE,
> + .attrs = &ecap_attribute_group,
> + .read_raw = &ecap_read_raw,
> +};
> +
> +static irqreturn_t ecap_trigger_handler(int irq, void *private)
> +{
> + struct iio_poll_func *pf = private;
> + struct iio_dev *idev = pf->indio_dev;
> + struct ecap_state *state = iio_priv(idev);
> +
> + /* Read pulse counter value */
> + *state->buf = readl(state->regs + CAP2);
> +
To get more accurate timestamps, you could grab that in the top half handler.
See how ad7887 does it for example using the utility function
iio_pollfunc_store_time.
> + iio_push_to_buffers_with_timestamp(idev, state->buf, iio_get_time_ns());
> +
> + iio_trigger_notify_done(idev->trig);
> +
> + return IRQ_HANDLED;
> +};
> +
> +
> +static const struct iio_trigger_ops iio_interrupt_trigger_ops = {
> + .owner = THIS_MODULE,
> +};
> +
> +static irqreturn_t ecap_interrupt_handler(int irq, void *private)
> +{
> + struct iio_dev *idev = private;
> + struct ecap_state *state = iio_priv(idev);
> + u16 ints;
> +
> + iio_trigger_poll(idev->trig, 0);
> +
Do you want to clear the interrupt here, or in the try renable callback
for the trigger? That would only be called after the data has been grabbed.
> + /* Clear CAP2 interrupt */
> + ints = readw(state->regs + ECFLG);
> + if (ints & ECINT_CEVT2)
> + writew(ECINT_CEVT2, state->regs + ECCLR);
> + else
> + dev_warn(&idev->dev, "unhandled interrupt flagged: %04x\n",
> + ints);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static int ecap_buffer_predisable(struct iio_dev *idev)
> +{
> + struct ecap_state *state = iio_priv(idev);
> + int ret = 0;
> + u16 ecctl2;
> +
> + /* Stop capture */
> + clear_bit(ECAP_ENABLED, &state->flags);
> + ecctl2 = readw(state->regs + ECCTL2) & ~ECCTL2_TSCTR_FREERUN;
> + writew(ecctl2, state->regs + ECCTL2);
> +
> + /* Disable and clear all interrupts */
> + writew(0, state->regs + ECEINT);
> + writew(ECINT_ALL, state->regs + ECCLR);
> +
By ordering convention this should be in reverse order of the postenable,
hence this predisable call should be first in the function.
Not sure it matters in reality but is more 'obviously' correct which
is always a good thing.
> + ret = iio_triggered_buffer_predisable(idev);
> +
> + pm_runtime_put_sync(idev->dev.parent);
> +
> + return ret;
> +}
> +
> +static int ecap_buffer_postenable(struct iio_dev *idev)
> +{
> + struct ecap_state *state = iio_priv(idev);
> + int ret = 0;
> + u16 ecctl1, ecctl2;
> +
> + pm_runtime_get_sync(idev->dev.parent);
> +
> + /* Configure pulse polarity */
> + ecctl1 = readw(state->regs + ECCTL1);
> + if (test_bit(ECAP_POLARITY_HIGH, &state->flags)) {
> + /* CAP1 rising, CAP2 falling */
> + ecctl1 |= ECCTL1_CAP2POL;
> + ecctl1 &= ~ECCTL1_CAP1POL;
> + } else {
> + /* CAP1 falling, CAP2 rising */
> + ecctl1 &= ~ECCTL1_CAP2POL;
> + ecctl1 |= ECCTL1_CAP1POL;
> + }
> + writew(ecctl1, state->regs + ECCTL1);
> +
> + /* Enable CAP2 interrupt */
> + writew(ECINT_CEVT2, state->regs + ECEINT);
> +
> + /* Enable capture */
> + ecctl2 = readw(state->regs + ECCTL2);
> + ecctl2 |= ECCTL2_TSCTR_FREERUN | ECCTL2_REARM;
> + writew(ecctl2, state->regs + ECCTL2);
> + set_bit(ECAP_ENABLED, &state->flags);
> +
> + ret = iio_triggered_buffer_postenable(idev);
> +
> + return ret;
> +}
> +
> +static const struct iio_buffer_setup_ops ecap_buffer_setup_ops = {
> + .postenable = &ecap_buffer_postenable,
> + .predisable = &ecap_buffer_predisable,
> +};
> +
> +static void ecap_init_hw(struct iio_dev *idev)
> +{
> + struct ecap_state *state = iio_priv(idev);
> +
> + clear_bit(ECAP_ENABLED, &state->flags);
> + set_bit(ECAP_POLARITY_HIGH, &state->flags);
> +
> + writew(ECCTL1_RUN_FREE | ECCTL1_CAPLDEN |
> + ECCTL1_CAP2POL | ECCTL1_CTRRST1,
> + state->regs + ECCTL1);
> +
> + writew(ECCTL2_SYNCO_SEL_DIS | ECCTL2_STOP_WRAP_2,
> + state->regs + ECCTL2);
> +}
> +
> +static const struct of_device_id ecap_of_ids[] = {
> + { .compatible = "ti,am33xx-ecap" },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, ecap_of_ids);
> +
> +static int ecap_probe(struct platform_device *pdev)
> +{
> + int irq, ret;
> + struct iio_dev *idev;
> + struct ecap_state *state;
> + struct resource *r;
> + struct clk *clk;
> + struct iio_trigger *trig;
> + u16 status;
> +
> + idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct ecap_state));
> + if (!idev)
> + return -ENOMEM;
> +
> + state = iio_priv(idev);
> +
> + clk = devm_clk_get(&pdev->dev, "fck");
> + if (IS_ERR(clk)) {
> + dev_err(&pdev->dev, "failed to get clock\n");
> + return PTR_ERR(clk);
> + }
> +
> + state->clk_rate = clk_get_rate(clk);
> + if (!state->clk_rate) {
> + dev_err(&pdev->dev, "failed to get clock rate\n");
> + return -EINVAL;
> + }
> +
> + platform_set_drvdata(pdev, idev);
> +
> + idev->dev.parent = &pdev->dev;
> + idev->name = dev_name(&pdev->dev);
> + idev->modes = INDIO_DIRECT_MODE;
> + idev->info = &ecap_info;
> + idev->channels = ecap_channels;
> + /* One h/w capture and one s/w timestamp channel per instance */
Note that the timestamp may or may not be enabled... Technically it's
possible to enable the timestamp and not the channel - that's just rather
odd though funnily enough it would give access to the period of the waveform
in this case...
> + idev->num_channels = ARRAY_SIZE(ecap_channels);
> +
> + trig = devm_iio_trigger_alloc(&pdev->dev, "%s-dev%d",
> + idev->name, idev->id);
> + if (!trig)
> + return -ENOMEM;
> + trig->dev.parent = idev->dev.parent;
> + iio_trigger_set_drvdata(trig, idev);
> + trig->ops = &iio_interrupt_trigger_ops;
> +
> + ret = iio_trigger_register(trig);
> + if (ret) {
> + dev_err(&pdev->dev, "failed to register trigger\n");
> + return ret;
> + }
> +
> + ret = iio_triggered_buffer_setup(idev, NULL,
> + &ecap_trigger_handler,
> + &ecap_buffer_setup_ops);
> + if (ret)
> + return ret;
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "no irq is specified\n");
> + return irq;
> + }
> + ret = devm_request_irq(&pdev->dev, irq,
> + &ecap_interrupt_handler,
> + 0, dev_name(&pdev->dev), idev);
> + if (ret) {
> + dev_err(&pdev->dev, "unable to request irq\n");
> + goto uninit_buffer;
> + }
> +
> + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + state->regs = devm_ioremap_resource(&pdev->dev, r);
> + if (IS_ERR(state->regs)) {
> + dev_err(&pdev->dev, "unable to remap registers\n");
> + ret = PTR_ERR(state->regs);
> + goto uninit_buffer;
> + };
> +
> + ret = iio_device_register(idev);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "unable to register device\n");
> + goto uninit_buffer;
> + }
> +
Unless I missed something scan_bytes won't contain the correct size until
the channels have been enabled from userspace.
There would be nothing to stop you allocating 'enough' space here. But then
if you do that, you might as well do it directly in the state structure
rather than with this separate allocation.
> + state->buf = devm_kzalloc(&idev->dev, idev->scan_bytes, GFP_KERNEL);
> + if (!state->buf) {
> + ret = -ENOMEM;
> + goto uninit_buffer;
> + }
> +
> + pm_runtime_enable(&pdev->dev);
> + pm_runtime_get_sync(&pdev->dev);
> +
Does this initialize capture?
> + status = pwmss_submodule_state_change(pdev->dev.parent,
> + PWMSS_ECAPCLK_EN);
> + if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
> + dev_err(&pdev->dev, "failed to enable PWMSS config space clock\n");
> + ret = -EINVAL;
> + goto pwmss_clk_failure;
> + }
> +
> + ecap_init_hw(idev);
> +
> + pm_runtime_put_sync(&pdev->dev);
> +
> + return 0;
> +
> +pwmss_clk_failure:
> + pm_runtime_put_sync(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> + iio_device_unregister(idev);
> +
> +uninit_buffer:
> + iio_triggered_buffer_cleanup(idev);
> +
> + return ret;
> +}
> +
> +static int ecap_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *idev = platform_get_drvdata(pdev);
> +
> + pm_runtime_get_sync(&pdev->dev);
> +
> + pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
> +
> + pm_runtime_put_sync(&pdev->dev);
> + pm_runtime_disable(&pdev->dev);
> +
> + iio_device_unregister(idev);
I'd normally expect the device unregister to be the first element of remove
(and the last of probe) given it is responsible for providing the user
space interfaces. Can you explain why this doesn't make sense here?
> + iio_triggered_buffer_cleanup(idev);
> +
> + return 0;
> +}
> +
> +#ifdef CONFIG_PM_SLEEP
> +static int ecap_suspend(struct device *dev)
> +{
> + struct ecap_state *state = dev_to_ecap_state(dev);
> +
> + pm_runtime_get_sync(dev);
> + state->ctx.cap1 = readl(state->regs + CAP1);
> + state->ctx.cap2 = readl(state->regs + CAP2);
> + state->ctx.eceint = readw(state->regs + ECEINT);
> + state->ctx.ecctl1 = readw(state->regs + ECCTL1);
> + state->ctx.ecctl2 = readw(state->regs + ECCTL2);
> + pm_runtime_put_sync(dev);
> +
> + /* If capture was active, disable ECAP */
> + if (test_bit(ECAP_ENABLED, &state->flags))
> + pm_runtime_put_sync(dev);
> +
> + return 0;
> +}
> +
> +static int ecap_resume(struct device *dev)
> +{
> + struct ecap_state *state = dev_to_ecap_state(dev);
> +
> + /* If capture was active, enable ECAP */
> + if (test_bit(ECAP_ENABLED, &state->flags))
> + pm_runtime_get_sync(dev);
> +
> + pm_runtime_get_sync(dev);
> + writel(state->ctx.cap1, state->regs + CAP1);
> + writel(state->ctx.cap2, state->regs + CAP2);
> + writew(state->ctx.eceint, state->regs + ECEINT);
> + writew(state->ctx.ecctl1, state->regs + ECCTL1);
> + writew(state->ctx.ecctl2, state->regs + ECCTL2);
> + pm_runtime_put_sync(dev);
> +
> + return 0;
> +}
> +#endif
> +
> +static SIMPLE_DEV_PM_OPS(ecap_pm_ops, ecap_suspend, ecap_resume);
> +
> +static struct platform_driver ecap_iio_driver = {
> + .driver = {
> + .name = "ecap",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(ecap_of_ids),
> + .pm = &ecap_pm_ops,
> + },
> + .probe = ecap_probe,
> + .remove = ecap_remove,
> +};
> +
> +module_platform_driver(ecap_iio_driver);
> +
> +MODULE_DESCRIPTION("ECAP IIO pulse capture driver");
> +MODULE_AUTHOR("Matt Porter <mporter-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>");
> +MODULE_LICENSE("GPL");
>
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox