* Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
From: Mark Rutland @ 2014-02-18 12:23 UTC (permalink / raw)
To: Mohit KUMAR DCG
Cc: arnd-r2nGTMty4D4@public.gmane.org, Pratyush ANAND, Viresh Kumar,
Kishon Vijay Abraham I, spear-devel,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <2CC2A0A4A178534D93D5159BF3BCB66189FD2CAFB1-8vAmw3ZAcdzhJTuQ9jeba9BPR1lH4CV8@public.gmane.org>
On Thu, Feb 13, 2014 at 05:19:11AM +0000, Mohit KUMAR DCG wrote:
> Hello Mark,
>
> > -----Original Message-----
> > From: Mark Rutland [mailto:mark.rutland-5wv7dgnIgG8@public.gmane.org]
> > Sent: Wednesday, February 12, 2014 11:50 PM
> > To: Mohit KUMAR DCG
> > Cc: arnd-r2nGTMty4D4@public.gmane.org; Pratyush ANAND; Viresh Kumar; Kishon Vijay Abraham I;
> > spear-devel; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > Subject: Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
> >
> > On Tue, Feb 11, 2014 at 09:29:59AM +0000, Mohit Kumar wrote:
> > > From: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > >
> > > ST miphy40lp can be used with PCIe, SATA and Super Speed USB
> > > controllers. SPEAr13XX SoCs use this phy for PCIe and SATA.
> > >
> > > Signed-off-by: Pratyush Anand <pratyush.anand-qxv4g6HH51o@public.gmane.org>
> > > Cc: Mohit Kumar <mohit.kumar-qxv4g6HH51o@public.gmane.org>
> > > Cc: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
> > > Cc: Viresh Kumar <viresh.linux-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > > Cc: Kishon Vijay Abraham I <kishon-l0cyMroinI0@public.gmane.org>
> > > Cc: spear-devel-nkJGhpqTU55BDgjK7y7TUQ@public.gmane.org
> > > Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> > > ---
> > > .../devicetree/bindings/phy/st-miphy40lp.txt | 18
> > ++++++++++++++++++
> > > 1 files changed, 18 insertions(+), 0 deletions(-) create mode 100644
> > > Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > >
> > > diff --git a/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > new file mode 100644
> > > index 0000000..1c8d04c
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/phy/st-miphy40lp.txt
> > > @@ -0,0 +1,18 @@
> > > +ST miphy40lp DT detail
> > > +===================================
> > > +
> > > +miphy40lp is a phy controller from ST Microelectronics which supports
> > > +PCIe, SATA and Super Speed USB host and devices. It has been used in
> > SPEAr13xx SOCs.
> > > +
> > > +Required properties:
> > > +- compatible : should be "st,miphy40lp-phy"
> > > + Other supported soc specific compatible:
> > > + "st,spear1310-miphy"
> > > + "st,spear1340-miphy"
> > > +- reg : offset and length of the PHY register set.
> > > +- misc: phandle for the syscon node to access misc registers
> >
> > This is very vague. What is this used for?
>
> - These are Spear SoC specific miscellaneous registers. Here these are used for
> to configure sata/pcie aux clock.
> >
> > > +- phy-id: Instance id of the phy.
> > > +- #phy-cells : from the generic PHY bindings, must be 1.
> > > + - 1st cell: phandle to the phy node.
> > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > > + and 2 for Super Speed USB.
> >
> > One cell or two?
>
> - No of cells are two, is this the question?
The description of #phy-cells says it must be 1. Presumably it must be
2.
Thanks,
Mark
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^ permalink raw reply
* [PATCH v2] of_mdio: fix phy interrupt passing
From: Ben Dooks @ 2014-02-18 12:16 UTC (permalink / raw)
To: grant.likely
Cc: linux-kernel, devicetree, linux-kernel, netdev, linux-sh,
sergei.shtylyov, Ben Dooks
The of_mdiobus_register_phy() is not setting phy->irq thus causing
some drivers to incorrectly assume that the PHY does not have an
IRQ associated with it. Not only do some drivers report no IRQ
they do not install an interrupt handler for the PHY.
Simplify the code setting irq and set the phy->irq at the same
time so that we cover the following issues, which should cover
all the cases the code will find:
- Set phy->irq if node has irq property and mdio->irq is NULL
- Set phy->irq if node has no irq and mdio->irq is not NULL
- Leave phy->irq as PHY_POLL default if none of the above
This fixes the issue:
net eth0: attached PHY 1 (IRQ -1) to driver Micrel KSZ8041RNLI
to the correct:
net eth0: attached PHY 1 (IRQ 416) to driver Micrel KSZ8041RNLI
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
---
Since v1:
- Updated phy->irq setting code
- Deal with issue if mdio->irq array NULL
Notes:
It was discussed if this should be two patches, but we end up
making enough changes in #2 the same area as #1 means that we
basically rewrite #1 in #2. So keep it as 1 patch.
---
drivers/of/of_mdio.c | 16 +++++++++-------
1 file changed, 9 insertions(+), 7 deletions(-)
diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
index 875b7b6..46d95fc 100644
--- a/drivers/of/of_mdio.c
+++ b/drivers/of/of_mdio.c
@@ -44,7 +44,7 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi
{
struct phy_device *phy;
bool is_c45;
- int rc, prev_irq;
+ int rc;
u32 max_speed = 0;
is_c45 = of_device_is_compatible(child,
@@ -54,12 +54,14 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi
if (!phy || IS_ERR(phy))
return 1;
- if (mdio->irq) {
- prev_irq = mdio->irq[addr];
- mdio->irq[addr] =
- irq_of_parse_and_map(child, 0);
- if (!mdio->irq[addr])
- mdio->irq[addr] = prev_irq;
+ rc = irq_of_parse_and_map(child, 0);
+ if (rc > 0) {
+ phy->irq = rc;
+ if (mdio->irq)
+ mdio->irq[addr] = rc;
+ } else {
+ if (mdio->irq)
+ phy->irq = mdio->irq[addr];
}
/* Associate the OF node with the device structure so it
--
1.8.5.3
^ permalink raw reply related
* Re: [PATCH 0/9] OMAP DSS DT bindings documentation
From: Archit Taneja @ 2014-02-18 12:09 UTC (permalink / raw)
To: Tomi Valkeinen, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1392294752-18762-1-git-send-email-tomi.valkeinen-l0cyMroinI0@public.gmane.org>
Hi,
On Thursday 13 February 2014 06:02 PM, Tomi Valkeinen wrote:
> Hi,
>
> Here is DT binding documentation for OMAP Display Subsystem. I've sent these
> earlier as part of the whole DSS DT series, but I'm now sending them separately
> to get comments for them.
>
> These patches are essentially the same as what I already sent earlier. The only
> difference is that I added clock information for omap3 and omap4 platforms.
Reviewed-by: Archit Taneja <archit-l0cyMroinI0@public.gmane.org>
Archit
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^ permalink raw reply
* Re: [PATCH v4 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Arnd Bergmann @ 2014-02-18 11:55 UTC (permalink / raw)
To: Sachin Kamat
Cc: devicetree@vger.kernel.org, linux-samsung-soc, Pankaj Dubey,
Tomasz Figa, sunil joshi, Kukjin Kim, Rahul Sharma,
linux-arm-kernel, Rahul Sharma
In-Reply-To: <CAK9yfHwcteO78JG4OhRZtMcpAd-aN85sxqELJ3ZLW0D0PXoZ7w@mail.gmail.com>
On Tuesday 18 February 2014 17:11:43 Sachin Kamat wrote:
> On 18 February 2014 16:33, Arnd Bergmann <arnd@arndb.de> wrote:
> > On Tuesday 18 February 2014 16:27:54 Rahul Sharma wrote:
> >>
> >> +static struct map_desc exynos5260_iodesc[] __initdata = {
> >> + {
> >> + .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
> >> + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
> >> + .length = SZ_4K,
> >> + .type = MT_DEVICE,
> >> + },
> >> +};
> > As I commented before, I think we really shouldn't do this any more: There
> > is no excuse why you still need to add SoC specific code here. Please put
> > the SYSRAM into DT and make a proper abstraction for it so you don't have
> > to modify the kernel every time a new SoC variant comes out.
>
> Do we have any bindings already defined for this kind of stuff or is
> this implemented in
> any other platform/architecture for reference?
>
It depends on how the sram is used. There is a generic binding in
Documentation/devicetree/bindings/misc/sram.txt that may be appropriate here.
Arnd
^ permalink raw reply
* Re: [PATCH 1/9] Doc/DT: Add OMAP DSS DT Bindings
From: Archit Taneja @ 2014-02-18 11:54 UTC (permalink / raw)
To: Tomi Valkeinen, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1392294752-18762-2-git-send-email-tomi.valkeinen-l0cyMroinI0@public.gmane.org>
Hi,
On Thursday 13 February 2014 06:02 PM, Tomi Valkeinen wrote:
> Add device tree bindings for OMAP Display Subsystem for the following
> SoCs: OMAP2, OMAP3, OMAP4.
>
> Signed-off-by: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> ---
<snip>
> +A shortened example of the board description for OMAP4 Panda board, defined in
> +omap4-panda.dts.
> +
> +The Panda board has a DVI and a HDMI connector, and the board contains a TFP410
> +chip (MIPI DPI to DVI encoder) and a TPD12S015 chip (HDMI ESD protection & level
> +shifter). The video pipelines for the connectors are formed as follows:
> +
> +DSS Core --(MIPI DPI)--> TFP410 --(DVI)--> DVI Connector
> +OMAP HDMI --(HDMI)--> TPD12S015 --(HDMI)--> HDMI COnnector
Nitpick - 'CO' -> 'Co'
Archit
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^ permalink raw reply
* Re: [PATCH] net: add init-regs for of_phy support
From: Mark Rutland @ 2014-02-18 11:54 UTC (permalink / raw)
To: Ben Dooks
Cc: Florian Fainelli, Sergei Shtylyov, netdev,
devicetree@vger.kernel.org, Linux-sh list, David Miller
In-Reply-To: <530316EE.5010104@codethink.co.uk>
On Tue, Feb 18, 2014 at 08:16:46AM +0000, Ben Dooks wrote:
> On 17/02/14 20:48, Florian Fainelli wrote:
>
> [snip]
>
> >>> - fixing up some design mistake?
> >>> - accounting for a specific board design?
> >>
> >>
> >> Kind of both. This was invented to defy the necessity of having platform
> >> fixup in the DT case (where there should be no board file to place it into).
> >> I have already described that platform fixup necessary on the Renesas
> >> Lager/Koelsch boards where the LED0 signat is connected to ETH_LINK signal
> >> on the SoC and the PHY reset sets the LED control bits to default 0 which
> >> means that LED0 will be LINK/ACTIVITY signal and thus blink on activity and
> >> cause ETH_LINK to bounce off/on after each packet.
> >>
> >>
> >>> In any case a PHY fixup would do the job for you.
> >>
> >>
> >> Not in any case. In case of DT we have no place for it, so should invent
> >> something involving DT.
> >
> > How is DT different than any machine probing mechanism here? The way
> > to involve DT is to do the following:
> >
> > if (of_machine_is_compatible("renesas,foo-board-with-broken-micrel-phy"))
> > phy_register_fixup(&foo_board_with_broken_micrel_phy);
>
> Oh yes, but now I have to do that for Linux, for $BSD, and for
> anything else I want to run on the device. I thought dt was meant
> to allow us to describe the hardware.
It does allow you to describe the hardware. Arbitrary register writes
aren't a description of the hardware, they're a sequence of instructions
that tells the OS nothing about the hardware and limit the ability of an
OS to do something different that might be better.
It's already the case that the OS has to have some knowledge of the
hardware that's implicit in a binding. We don't expect to have to
include bytecode to tell the OS how to poke a particular UART when it
can figure that out from a compatible string.
> If this is the case, let's just call this linuxtree and let everyone
> else get on with their own thing again.
This doesn't follow at all. Any OS needs to have some understanding of
the hardware it will try to poke. Describing a specific sequence of
writes in a DT is no more operating system independent than identifying
the hardware and expecting the OS to have a driver for it. The
requirements aren't any more suited to an individual OS in either case.
>
> See also comment below.
>
> > If your machine compatible string does not allow you to uniquely
> > identify your machine, this is a DT problem, as this should really be
> > the case. If you do not want to add this code to wherever this is
> > relevant in arch/arm/mach-shmobile/board-*.c, neither is
> > drivers/net/phy/phy_device.c this the place to add it.
>
> So where should it be added? If we keep piling stuff into board files
> in arch/arm.... then we're just back to the pre-dt case and going to
> keep getting shouted at.
The general trend has been to allocate new compatible strings for
components and let individual drivers handle this.
As far as I can see your case doesn't involve any components external to
the PHY, so should probably live in a PHY driver. The PHY can have a
specific compatible string with the generic string as a fallback (if it
works to some degree without special poking).
I don't see that we need anything board-specific.
>
> > Dealing with quirks applying to industry standard blocks is to update
> > the relevant driver, based on information provided by the specifically
> > affected systems. Failure to identify either of those correctly is a
> > problem that must not lead to a generic "let's override PHY registers
> > from DT" type of solution.
> >
> > As usual, mechanism vs policy applies even more when DT is involved.
>
> There's an industry standard for the access method, but every PHY seems
> to have different extra setup registers for their own cases.
So? Have a driver for each PHY, or fixups for each PHY in a shared
driver.
Cheers,
Mark.
^ permalink raw reply
* [PATCH RFC v4 3/3] Documentation: arm: define DT idle states bindings
From: Lorenzo Pieralisi @ 2014-02-18 11:47 UTC (permalink / raw)
To: devicetree
Cc: Mark Rutland, Mike Turquette, Tomasz Figa, Mark Hambleton,
Lorenzo Pieralisi, Russell King, Sebastian Capella, Nicolas Pitre,
Daniel Lezcano, linux-arm-kernel, Grant Likely, Dave Martin,
Charles Garcia Tobin, Kevin Hilman, linux-pm, Kumar Gala,
Rob Herring, Vincent Guittot, Antti Miettinen, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
In-Reply-To: <1392724051-11950-1-git-send-email-lorenzo.pieralisi@arm.com>
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.
Therefore, this patch aims at standardizing idle state device tree bindings for
ARM platforms. Bindings define idle state parameters inclusive of entry methods
and state latencies, to allow operating systems to retrieve the configuration
entries from the device tree and initialize the related power management
drivers, paving the way for common code in the kernel to deal with idle
states and removing the need for static data in current and previous kernel
versions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cpus.txt | 10 +
Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++
2 files changed, 791 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.txt b/Documentation/devicetree/bindings/arm/cpus.txt
index 9130435..fd1fd8d 100644
--- a/Documentation/devicetree/bindings/arm/cpus.txt
+++ b/Documentation/devicetree/bindings/arm/cpus.txt
@@ -191,6 +191,13 @@ nodes to be present and contain the properties described below.
property identifying a 64-bit zero-initialised
memory location.
+ - cpu-idle-states
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition:
+ # List of phandles to idle state nodes supported
+ by this cpu [1].
+
Example 1 (dual-cluster big.LITTLE system 32-bit):
cpus {
@@ -382,3 +389,6 @@ cpus {
cpu-release-addr = <0 0x20000000>;
};
};
+
+[1] ARM Linux kernel documentation - idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
diff --git a/Documentation/devicetree/bindings/arm/idle-states.txt b/Documentation/devicetree/bindings/arm/idle-states.txt
new file mode 100644
index 0000000..f9a48a1
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/idle-states.txt
@@ -0,0 +1,781 @@
+==========================================
+ARM idle states binding description
+==========================================
+
+==========================================
+1 - Introduction
+==========================================
+
+ARM systems contain HW capable of managing power consumption dynamically,
+where cores can be put in different low-power states (ranging from simple
+wfi to power gating) according to OSPM policies. The CPU states representing
+the range of dynamic idle states that a processor can enter at run-time, can be
+specified through device tree bindings representing the parameters required
+to enter/exit specific idle states on a given processor.
+
+According to the Server Base System Architecture document (SBSA, [4]), the
+power states an ARM CPU can be put into are identified by the following list:
+
+- Running
+- Idle_standby
+- Idle_retention
+- Sleep
+- Off
+
+The power states described in the SBSA document define the basic CPU states on
+top of which ARM platforms implement power management schemes that allow an OS
+PM implementation to put the processor in different idle states (which include
+states listed above; "off" state is not an idle state since it does not have
+wake-up capabilities, hence it is not considered in this document).
+
+Idle state parameters (eg entry latency) are platform specific and need to be
+characterized with bindings that provide the required information to OSPM
+code so that it can build the required tables and use them at runtime.
+
+The device tree binding definition for ARM idle states is the subject of this
+document.
+
+===========================================
+2 - idle-states node
+===========================================
+
+ARM processor idle states are defined within the idle-states node, which is
+a direct child of the cpus node and provides a container where the processor
+idle states, defined as device tree nodes, are listed.
+
+- idle-states node
+
+ Usage: Optional - On ARM systems, is a container of processor idle
+ states nodes. If the system does not provide CPU
+ power management capabilities or the processor just
+ supports idle_standby an idle-states node is not
+ required.
+
+ Description: idle-states node is a container node, where its
+ subnodes describe the CPU idle states.
+
+ Node name must be "idle-states".
+
+ The idle-states node's parent node must be the cpus node.
+
+ The idle-states node's child nodes can be:
+
+ - one or more state nodes
+
+ Any other configuration is considered invalid.
+
+ An idle-states node defines the following properties:
+
+ - entry-method
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Describes the method by which a CPU enters the
+ idle states. This property is required and must be
+ one of:
+
+ - "arm,psci-cpu-suspend"
+ ARM PSCI firmware interface, CPU suspend
+ method[3].
+
+ - "[vendor],[method]"
+ An implementation dependent string with
+ format "vendor,method", where vendor is a string
+ denoting the name of the manufacturer and
+ method is a string specifying the mechanism
+ used to enter the idle state.
+
+The nodes describing the idle states (state) can only be defined within the
+idle-states node.
+
+Any other configuration is consider invalid and therefore must be ignored.
+
+===========================================
+3 - state node
+===========================================
+
+A state node represents an idle state description and must be defined as
+follows:
+
+- state node
+
+ Description: must be child of either the idle-states node or
+ a state node.
+
+ The state node name shall follow standard device tree naming
+ rules ([6], 2.2.1 "Node names"), in particular state nodes which
+ are siblings within a single common parent must be given a unique name.
+
+ The idle state entered by executing the wfi instruction (idle_standby
+ SBSA,[4][5]) is considered standard on all ARM platforms and therefore
+ must not be listed.
+
+ A state node can contain state child nodes. A state node with
+ children represents a hierarchical state, which is a superset of
+ the child states. Hierarchical states require all CPUs on which
+ they are valid (ie cpu nodes [1] containing cpu-idle-states arrays
+ having a phandle to the state) to request the state in order for it
+ to be entered.
+
+ A state node defines the following properties:
+
+ - compatible
+ Usage: Required
+ Value type: <stringlist>
+ Definition: Must be "arm,idle-state".
+
+ - index
+ Usage: Required
+ Value type: <u32>
+ Definition: It represents the idle state index.
+ An increasing index value implies less power
+ consumption. Index must be given a sequential
+ value = {0, 1, ....}, starting from 0.
+ Phandles in the cpu nodes [1] cpu-idle-states
+ array property are not allowed to point at idle
+ state nodes having the same index value.
+
+ - logic-state-retained
+ Usage: See definition
+ Value type: <none>
+ Definition: if present logic is retained on state entry,
+ otherwise it is lost.
+
+ - cache-state-retained
+ Usage: See definition
+ Value type: <none>
+ Definition: if present cache memory is retained on state entry,
+ otherwise it is lost.
+
+ - entry-method-param
+ Usage: See definition.
+ Value type: <u32>
+ Definition: Depends on the idle-states node entry-method
+ property value. Refer to the entry-method bindings
+ for this property value definition.
+
+ - entry-latency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to enter the idle state.
+
+ - exit-latency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing worst case latency
+ in microseconds required to exit the idle state.
+
+ - min-residency
+ Usage: Required
+ Value type: <prop-encoded-array>
+ Definition: u32 value representing time in microseconds
+ required for the CPU to be in the idle state to
+ break even in power consumption terms compared
+ to idle state idle_standby ([4][5]).
+
+ - power-domains
+ Usage: Optional
+ Value type: <prop-encoded-array>
+ Definition: List of power domain specifiers ([2]) describing
+ the power domains that are affected by the idle
+ state entry. All devices whose power-domain phandle
+ points at one of the power domains listed in this
+ property are affected by the idle state entry.
+
+
+===========================================
+4 - Examples
+===========================================
+
+Example 1 (ARM 64-bit, 16-cpu system):
+
+pd_clusters: power-domain-clusters@80002000 {
+ compatible = "arm,power-controller";
+ reg = <0x0 0x80002000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ pd_cores: power-domain-cores@80000000 {
+ compatible = "arm,power-controller";
+ reg = <0x0 0x80000000 0x0 0x1000>;
+ #power-domain-cells = <1>;
+ };
+};
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <2>;
+
+ idle-states {
+ entry-method = "arm,psci-cpu-suspend";
+
+ CLUSTER_RET_0: cluster-ret-0 {
+ /* cluster retention */
+ compatible = "arm,idle-state";
+ index = <2>;
+ logic-state-retained;
+ cache-state-retained;
+ entry-method-param = <0x1010000>;
+ entry-latency = <50>;
+ exit-latency = <100>;
+ min-residency = <250>;
+ power-domains = <&pd_clusters 0>;
+ CPU_RET_0_0: cpu-ret-0 {
+ /* cpu retention */
+ compatible = "arm,idle-state";
+ index = <0>;
+ cache-state-retained;
+ entry-method-param = <0x0010000>;
+ entry-latency = <20>;
+ exit-latency = <40>;
+ min-residency = <30>;
+ power-domains = <&pd_cores 0>,
+ <&pd_cores 1>,
+ <&pd_cores 2>,
+ <&pd_cores 3>,
+ <&pd_cores 4>,
+ <&pd_cores 5>,
+ <&pd_cores 6>,
+ <&pd_cores 7>;
+ };
+ };
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ /* cluster sleep */
+ compatible = "arm,idle-state";
+ index = <3>;
+ entry-method-param = <0x1010000>;
+ entry-latency = <600>;
+ exit-latency = <1100>;
+ min-residency = <2700>;
+ power-domains = <&pd_clusters 0>;
+ CPU_SLEEP_0_0: cpu-sleep-0 {
+ /* cpu sleep */
+ compatible = "arm,idle-state";
+ index = <1>;
+ entry-method-param = <0x0010000>;
+ entry-latency = <250>;
+ exit-latency = <500>;
+ min-residency = <350>;
+ power-domains = <&pd_cores 0>,
+ <&pd_cores 1>,
+ <&pd_cores 2>,
+ <&pd_cores 3>,
+ <&pd_cores 4>,
+ <&pd_cores 5>,
+ <&pd_cores 6>,
+ <&pd_cores 7>;
+ };
+ };
+ CLUSTER_RET_1: cluster-ret-1 {
+ /* cluster retention */
+ compatible = "arm,idle-state";
+ index = <2>;
+ logic-state-retained;
+ cache-state-retained;
+ entry-method-param = <0x1010000>;
+ entry-latency = <50>;
+ exit-latency = <100>;
+ min-residency = <270>;
+ power-domains = <&pd_clusters 1>;
+ CPU_RET_1_0: cpu-ret-0 {
+ /* cpu retention */
+ compatible = "arm,idle-state";
+ index = <0>;
+ cache-state-retained;
+ entry-method-param = <0x0010000>;
+ entry-latency = <20>;
+ exit-latency = <40>;
+ min-residency = <30>;
+ power-domains = <&pd_cores 8>,
+ <&pd_cores 9>,
+ <&pd_cores 10>,
+ <&pd_cores 11>,
+ <&pd_cores 12>,
+ <&pd_cores 13>,
+ <&pd_cores 14>,
+ <&pd_cores 15>;
+ };
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ /* cluster sleep */
+ compatible = "arm,idle-state";
+ index = <3>;
+ entry-method-param = <0x1010000>;
+ entry-latency = <500>;
+ exit-latency = <1200>;
+ min-residency = <3500>;
+ power-domains = <&pd_clusters 1>;
+ CPU_SLEEP_1_0: cpu-sleep-0 {
+ /* cpu sleep */
+ compatible = "arm,idle-state";
+ index = <1>;
+ entry-method-param = <0x0010000>;
+ entry-latency = <70>;
+ exit-latency = <100>;
+ min-residency = <100>;
+ power-domains = <&pd_cores 8>,
+ <&pd_cores 9>,
+ <&pd_cores 10>,
+ <&pd_cores 11>,
+ <&pd_cores 12>,
+ <&pd_cores 13>,
+ <&pd_cores 14>,
+ <&pd_cores 15>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L1_0>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_0: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 0>;
+ };
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 0>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L1_1>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_1: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 1>;
+ };
+ };
+
+ CPU2: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_2>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_2: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 2>;
+ };
+ };
+
+ CPU3: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_3>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_3: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 3>;
+ };
+ };
+
+ CPU4: cpu@10000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L1_4>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_4: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 4>;
+ };
+ };
+
+ CPU5: cpu@10001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10001>;
+ enable-method = "psci";
+ next-level-cache = <&L1_5>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_5: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 5>;
+ };
+ };
+
+ CPU6: cpu@10100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_6>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_6: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 6>;
+ };
+ };
+
+ CPU7: cpu@10101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a57";
+ reg = <0x0 0x10101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_7>;
+ cpu-idle-states = <&CPU_RET_0_0 &CPU_SLEEP_0_0
+ &CLUSTER_RET_0 &CLUSTER_SLEEP_0>;
+ L1_7: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 7>;
+ };
+ };
+
+ CPU8: cpu@100000000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&L1_8>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_8: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 8>;
+ };
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 1>;
+ };
+ };
+
+ CPU9: cpu@100000001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&L1_9>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_9: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 9>;
+ };
+ };
+
+ CPU10: cpu@100000100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_10>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_10: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 10>;
+ };
+ };
+
+ CPU11: cpu@100000101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_11>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_11: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 11>;
+ };
+ };
+
+ CPU12: cpu@100010000 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10000>;
+ enable-method = "psci";
+ next-level-cache = <&L1_12>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_12: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 12>;
+ };
+ };
+
+ CPU13: cpu@100010001 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10001>;
+ enable-method = "psci";
+ next-level-cache = <&L1_13>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_13: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 13>;
+ };
+ };
+
+ CPU14: cpu@100010100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10100>;
+ enable-method = "psci";
+ next-level-cache = <&L1_14>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_14: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 14>;
+ };
+ };
+
+ CPU15: cpu@100010101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1 0x10101>;
+ enable-method = "psci";
+ next-level-cache = <&L1_15>;
+ cpu-idle-states = <&CPU_RET_1_0 &CPU_SLEEP_1_0
+ &CLUSTER_RET_1 &CLUSTER_SLEEP_1>;
+ L1_15: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 15>;
+ };
+ };
+};
+
+Example 2 (ARM 32-bit, 8-cpu system, two clusters):
+
+pd_clusters: power-domain-clusters@80002000 {
+ compatible = "arm,power-controller";
+ reg = <0x80002000 0x1000>;
+ #power-domain-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ pd_cores: power-domain-cores@80000000 {
+ compatible = "arm,power-controller";
+ reg = <0x80000000 0x1000>;
+ #power-domain-cells = <1>;
+ };
+};
+
+cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ idle-states {
+ entry-method = "arm,psci-cpu-suspend";
+
+ CLUSTER_SLEEP_0: cluster-sleep-0 {
+ compatible = "arm,idle-state";
+ index = <1>;
+ entry-method-param = <0x1010000>;
+ entry-latency = <1000>;
+ exit-latency = <1500>;
+ min-residency = <1500>;
+ power-domains = <&pd_clusters 0>;
+ CPU_SLEEP_0_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ index = <0>;
+ entry-method-param = <0x0010000>;
+ entry-latency = <400>;
+ exit-latency = <500>;
+ min-residency = <300>;
+ power-domains = <&pd_cores 0>,
+ <&pd_cores 1>,
+ <&pd_cores 2>,
+ <&pd_cores 3>;
+ };
+ };
+
+ CLUSTER_SLEEP_1: cluster-sleep-1 {
+ compatible = "arm,idle-state";
+ index = <1>;
+ entry-method-param = <0x1010000>;
+ entry-latency = <800>;
+ exit-latency = <2000>;
+ min-residency = <6500>;
+ power-domains = <&pd_clusters 1>;
+ CPU_SLEEP_1_0: cpu-sleep-0 {
+ compatible = "arm,idle-state";
+ index = <0>;
+ entry-method-param = <0x0010000>;
+ entry-latency = <300>;
+ exit-latency = <500>;
+ min-residency = <500>;
+ power-domains = <&pd_cores 4>,
+ <&pd_cores 5>,
+ <&pd_cores 6>,
+ <&pd_cores 7>;
+ };
+ };
+ };
+
+ CPU0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ next-level-cache = <&L1_0>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ L1_0: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 0>;
+ };
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 0>;
+ };
+ };
+
+ CPU1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ next-level-cache = <&L1_1>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ L1_1: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 1>;
+ };
+ };
+
+ CPU2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ next-level-cache = <&L1_2>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ L1_2: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 2>;
+ };
+ };
+
+ CPU3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ next-level-cache = <&L1_3>;
+ cpu-idle-states = <&CPU_SLEEP_0_0 &CLUSTER_SLEEP_0>;
+ L1_3: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ power-domain = <&pd_cores 3>;
+ };
+ };
+
+ CPU4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ next-level-cache = <&L1_4>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ L1_4: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 4>;
+ };
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ power-domain = <&pd_clusters 1>;
+ };
+ };
+
+ CPU5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ next-level-cache = <&L1_5>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ L1_5: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 5>;
+ };
+ };
+
+ CPU6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ next-level-cache = <&L1_6>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ L1_6: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 6>;
+ };
+ };
+
+ CPU7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ next-level-cache = <&L1_7>;
+ cpu-idle-states = <&CPU_SLEEP_1_0 &CLUSTER_SLEEP_1>;
+ L1_7: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ power-domain = <&pd_cores 7>;
+ };
+ };
+};
+
+===========================================
+4 - References
+===========================================
+
+[1] ARM Linux Kernel documentation - CPUs bindings
+ Documentation/devicetree/bindings/arm/cpus.txt
+
+[2] ARM Linux Kernel documentation - power domain bindings
+ Documentation/devicetree/bindings/power/power_domain.txt
+
+[3] ARM Linux Kernel documentation - PSCI bindings
+ Documentation/devicetree/bindings/arm/psci.txt
+
+[4] ARM Server Base System Architecture (SBSA)
+ http://infocenter.arm.com/help/index.jsp
+
+[5] ARM Architecture Reference Manuals
+ http://infocenter.arm.com/help/index.jsp
+
+[6] ePAPR standard
+ https://www.power.org/documentation/epapr-version-1-1/
--
1.8.4
^ permalink raw reply related
* [PATCH RFC v4 2/3] Documentation: arm: add cache DT bindings
From: Lorenzo Pieralisi @ 2014-02-18 11:47 UTC (permalink / raw)
To: devicetree
Cc: Mark Rutland, Mike Turquette, Tomasz Figa, Mark Hambleton,
Lorenzo Pieralisi, Russell King, Sebastian Capella, Nicolas Pitre,
Daniel Lezcano, linux-arm-kernel, Grant Likely, Dave Martin,
Charles Garcia Tobin, Kevin Hilman, linux-pm, Kumar Gala,
Rob Herring, Vincent Guittot, Antti Miettinen, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
In-Reply-To: <1392724051-11950-1-git-send-email-lorenzo.pieralisi@arm.com>
On ARM systems the cache topology cannot be probed at runtime, in
particular, it is impossible to probe which CPUs share a given cache
level. Power management software requires this knowledge to implement
optimized power down sequences, hence this patch adds a document that
defines the DT cache bindings for ARM systems. The bindings supersede
cache bindings in the ePAPR (PowerPC bindings), because caches geometry for
architected caches is probeable on ARM systems. This patch also adds
properties that are specific to ARM architected caches to the existing ones
defined in the ePAPR v1.1, as bindings extensions.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/cache.txt | 167 +++++
1 file changed, 167 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cache.txt b/Documentation/devicetree/bindings/arm/cache.txt
new file mode 100644
index 0000000..3af3d28
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/cache.txt
@@ -0,0 +1,167 @@
+==========================================
+ARM processors cache binding description
+==========================================
+
+Device tree bindings for cache nodes are already part of the ePAPR standard
+v1.1 ([2]) for PowerPC platforms. This document defines the cache bindings
+for caches on ARM processor systems.
+
+On ARM based systems most of the cache properties related to cache geometry
+are probeable in HW (please refer to the processor TRMs in [1] for register
+details), hence, unless otherwise stated, the properties defined in ePAPR for
+internal, multi-level and shared caches ([2], 3.7.3, 3.8) are to be considered
+superseded on ARM.
+
+On ARM, caches are either architected (directly controlled by the processor
+through coprocessor instructions and tightly coupled with the processor
+implementation) or unarchitected (controlled through a memory mapped
+interface, implemented as a stand-alone IP external to the processor
+implementation).
+
+This document provides the device tree bindings for ARM architected caches.
+
+- ARM architected cache node
+
+ Description: must be a direct child of the cpu node.
+ A system can contain multiple architected cache nodes
+ per cpu node, linked through the next-level-cache phandle.
+ The next-level-cache property in the cpu node points to
+ the first level of architected cache for the CPU.
+ The next-level-cache links ordering must represent the
+ system cache hierarchy in the system, with the upper
+ cache level represented by a cache node with a missing
+ next-level-cache property.
+
+ ARM architected cache node defines the following properties:
+
+ - compatible
+ Usage: Required
+ Value type: <string>
+ Definition: value shall be "arm,arch-cache".
+
+ - power-domain
+ Usage: Optional
+ Value type: phandle
+ Definition: A phandle and power domain specifier as defined by
+ bindings of power domain specified by the
+ phandle [3].
+
+Example(dual-cluster big.LITTLE system 32-bit)
+
+ cpus {
+ #size-cells = <0>;
+ #address-cells = <1>;
+
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x0>;
+ next-level-cache = <&L1_0>;
+
+ L1_0: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ };
+
+ L2_0: l2-cache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x1>;
+ next-level-cache = <&L1_1>;
+
+ L1_1: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x2>;
+ next-level-cache = <&L1_2>;
+
+ L1_2: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a15";
+ reg = <0x3>;
+ next-level-cache = <&L1_3>;
+
+ L1_3: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_0>;
+ };
+ };
+
+ cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x100>;
+ next-level-cache = <&L1_4>;
+
+ L1_4: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ };
+
+ L2_1: l2-cache {
+ compatible = "arm,arch-cache";
+ };
+ };
+
+ cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x101>;
+ next-level-cache = <&L1_5>;
+
+ L1_5: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ };
+ };
+
+ cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x102>;
+ next-level-cache = <&L1_6>;
+
+ L1_6: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ };
+ };
+
+ cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0x103>;
+ next-level-cache = <&L1_7>;
+
+ L1_7: l1-cache {
+ compatible = "arm,arch-cache";
+ next-level-cache = <&L2_1>;
+ };
+ };
+ };
+
+[1] ARM Architecture Reference Manuals
+ http://infocenter.arm.com/help/index.jsp
+
+[2] ePAPR standard
+ https://www.power.org/documentation/epapr-version-1-1/
+
+[3] Kernel documentation - power domain bindings
+ Documentation/devicetree/bindings/power/power_domain.txt
--
1.8.4
^ permalink raw reply related
* [PATCH RFC v4 1/3] Documentation: devicetree: psci: define CPU suspend parameter
From: Lorenzo Pieralisi @ 2014-02-18 11:47 UTC (permalink / raw)
To: devicetree
Cc: Mark Rutland, Mike Turquette, Tomasz Figa, Mark Hambleton,
Lorenzo Pieralisi, Russell King, Sebastian Capella, Nicolas Pitre,
Daniel Lezcano, linux-arm-kernel, Grant Likely, Dave Martin,
Charles Garcia Tobin, Kevin Hilman, linux-pm, Kumar Gala,
Rob Herring, Vincent Guittot, Antti Miettinen, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
In-Reply-To: <1392724051-11950-1-git-send-email-lorenzo.pieralisi@arm.com>
OS layers built on top of PSCI to enter low-power states require the
power_state parameter to be passed to the PSCI CPU suspend method.
This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.
This patch adds a property in the PSCI bindings that describes how
the CPU suspend power_state parameter should be defined in DT in
all device nodes that rely on PSCI CPU suspend method usage.
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
---
Documentation/devicetree/bindings/arm/psci.txt | 11 +++++
1 file changed, 11 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/psci.txt b/Documentation/devicetree/bindings/arm/psci.txt
index 433afe9..797c48f 100644
--- a/Documentation/devicetree/bindings/arm/psci.txt
+++ b/Documentation/devicetree/bindings/arm/psci.txt
@@ -42,6 +42,14 @@ Main node optional properties:
- migrate : Function ID for MIGRATE operation
+Device tree nodes that require usage of PSCI CPU_SUSPEND function (ie idle
+states bindings[1]) must specify the following properties:
+
+- entry-method-param
+ Usage: Required for idle states bindings [1].
+ Value type: <u32>
+ Definition: power_state parameter to pass to the PSCI
+ suspend call.
Example:
@@ -53,3 +61,6 @@ Example:
cpu_on = <0x95c10002>;
migrate = <0x95c10003>;
};
+
+[1] Kernel documentation - ARM idle states bindings
+ Documentation/devicetree/bindings/arm/idle-states.txt
--
1.8.4
^ permalink raw reply related
* [PATCH RFC v4 0/3] ARM: defining idle states DT bindings
From: Lorenzo Pieralisi @ 2014-02-18 11:47 UTC (permalink / raw)
To: devicetree
Cc: Mark Rutland, Mike Turquette, Tomasz Figa, Mark Hambleton,
Lorenzo Pieralisi, Russell King, Sebastian Capella, Nicolas Pitre,
Daniel Lezcano, linux-arm-kernel, Grant Likely, Dave Martin,
Charles Garcia Tobin, Kevin Hilman, linux-pm, Kumar Gala,
Rob Herring, Vincent Guittot, Antti Miettinen, Peter De Schrijver,
Stephen Boyd, Amit Kucheria
This is v4 of a previous posting:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-February/231635.html
This patchset depends on the following bindings to be approved and augmented
to cater for hierarchical power domains in DT:
http://lists.infradead.org/pipermail/linux-arm-kernel/2014-January/224928.html
Changes in v4:
- Made entry-method global
- Renamed power_state parameter
- Augmented examples with retention states and node tags
- Reworded index property definition in the state node
- Changed the naming scheme for state nodes to default DT
- Defined idle_standby idle state (need not be listed)
- Clarified SBSA nomenclature and usage in the bindings
Changes in v3:
- Renamed C-states to "idle states" in patches and cover letter
- Added SBSA definitions
- Added power_state parameter to PSCI
- Removed OPP dependency
- Split latency into entry/exit latencies
- Reintroduced processor and cache retention boolean
- Made power_state generic parameter for all entry methods
- Redefined idle state hierarchy
Changes in v2:
- Updated cache bindings according to review
- Added power domain phandle to cache bindings
- Added power domains to C-states bindings
- Removed useless reg property from C-states bindings
- Removed cpu-map references from C-states bindings
- Added dependency on OPP in C-states parameters
- Added C-state state hierarchy
ARM based systems embed power management HW that allows SW to enter
low-power states according to run-time criteria based on parameters (eg
power state entry/exit latency) that define how an idle state has to be
managed and its respective properties. ARM partners implement HW power
management schemes through custom HW, with power controllers and relative
control mechanisms differing on both HW implementations and the way SW can
control them. This differentiation forces PM software in the kernel to cope
with states differences in power management drivers, which cause code
fragmentation and duplication of functionality.
Most of the power control scheme HW parameters are not probeable on ARM
platforms from a SW point of view, hence, in order to tackle the drivers
fragmentation problem, this patch series defines device tree bindings to
describe idle states parameters on ARM platforms.
Device tree bindings for idle states also require the introduction of device
tree bindings for processor caches, since idle states entry/exit require
SW cache maintainance; in some ARM systems, where firmware does not
support power down interfaces, cache maintainance must be carried out in the
OS power management layer, which then requires a description of the cache
topology through device tree nodes.
Idle states device tree standardization shares most of the concepts and
definitions with the ongoing ACPI ARM C-state bindings proposal so that
both standards can contain a coherent set of parameters, simplifying the
way SW will have to handle the respective device drivers.
Lorenzo Pieralisi (3):
Documentation: devicetree: psci: define CPU suspend parameter
Documentation: arm: add cache DT bindings
Documentation: arm: define DT idle states bindings
Documentation/devicetree/bindings/arm/cache.txt | 167 +
Documentation/devicetree/bindings/arm/cpus.txt | 10 +
Documentation/devicetree/bindings/arm/idle-states.txt | 781 +++++
Documentation/devicetree/bindings/arm/psci.txt | 11 +
4 files changed, 969 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/cache.txt
create mode 100644 Documentation/devicetree/bindings/arm/idle-states.txt
--
1.8.4
^ permalink raw reply
* Re: [PATCH v4 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Sachin Kamat @ 2014-02-18 11:41 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Rahul Sharma, linux-samsung-soc, devicetree@vger.kernel.org,
linux-arm-kernel, Kukjin Kim, Tomasz Figa, sunil joshi,
Rahul Sharma, Pankaj Dubey
In-Reply-To: <2203874.7pS2uKgoKp@wuerfel>
Hi Arnd,
On 18 February 2014 16:33, Arnd Bergmann <arnd@arndb.de> wrote:
> On Tuesday 18 February 2014 16:27:54 Rahul Sharma wrote:
>> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
>> index 7654f19..1cc52c9 100644
>> --- a/arch/arm/mach-exynos/common.c
>> +++ b/arch/arm/mach-exynos/common.c
>> @@ -176,6 +176,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
>> },
>> };
>>
>> +static struct map_desc exynos5260_iodesc[] __initdata = {
>> + {
>> + .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
>> + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
>> + .length = SZ_4K,
>> + .type = MT_DEVICE,
>> + },
>> +};
>> +
>> static struct map_desc exynos5_iodesc[] __initdata = {
>> {
>> .virtual = (unsigned long)S3C_VA_SYS,
>> @@ -331,6 +340,8 @@ static void __init exynos_map_io(void)
>> iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
>> if (soc_is_exynos5250())
>> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
>> + if (soc_is_exynos5260())
>> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
>> }
>
> As I commented before, I think we really shouldn't do this any more: There
> is no excuse why you still need to add SoC specific code here. Please put
> the SYSRAM into DT and make a proper abstraction for it so you don't have
> to modify the kernel every time a new SoC variant comes out.
Do we have any bindings already defined for this kind of stuff or is
this implemented in
any other platform/architecture for reference?
--
With warm regards,
Sachin
^ permalink raw reply
* [RFC PATCH v3 9/9] staging: imx-drm: Update TODO
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: David Airlie, Greg Kroah-Hartman, Shawn Guo, Fabio Estevam,
Grant Likely, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
The device tree bindings are updated regardless of the common display
framework and in the meantime the HDMI driver was included.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
drivers/staging/imx-drm/TODO | 5 -----
1 file changed, 5 deletions(-)
diff --git a/drivers/staging/imx-drm/TODO b/drivers/staging/imx-drm/TODO
index 6a9da94..29636fb 100644
--- a/drivers/staging/imx-drm/TODO
+++ b/drivers/staging/imx-drm/TODO
@@ -1,15 +1,10 @@
TODO:
- get DRM Maintainer review for this code
-- Wait for common display framework to hit mainline and update the IPU
- driver to use it. This will most probably make changes to the devicetree
- bindings necessary.
-- Factor out more code to common helper functions
- decide where to put the base driver. It is not specific to a subsystem
and would be used by DRM/KMS and media/V4L2
Missing features (not necessarily for moving out of staging):
-- Add i.MX6 HDMI support
- Add support for IC (Image converter)
- Add support for CSI (CMOS Sensor interface)
- Add support for VDIC (Video Deinterlacer)
--
1.8.5.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC PATCH v3 8/9] ARM: dts: imx6qdl: Add IPU DI ports and endpoints, move imx-drm node to dtsi
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Greg Kroah-Hartman, dri-devel, kernel,
Grant Likely, linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
This patch connects IPU and display encoder (HDMI, LVDS, MIPI)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Each encoder with an associated input multiplexer has multiple
input ports in the device tree. The order and reg property of
the ports must correspond to the multiplexer input order.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx6dl.dtsi | 22 +++---
arch/arm/boot/dts/imx6q-sabresd.dts | 4 -
arch/arm/boot/dts/imx6q.dtsi | 124 +++++++++++++++++++++++++++--
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 6 --
arch/arm/boot/dts/imx6qdl.dtsi | 138 ++++++++++++++++++++++++++++++++-
5 files changed, 263 insertions(+), 31 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 6dc3970..8ba94b8 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -70,6 +70,15 @@
};
};
};
+
+ imx-drm {
+ compatible = "fsl,imx-drm";
+ ports = <&ipu1_di0>, <&ipu1_di1>;
+ };
+};
+
+&hdmi {
+ compatible = "fsl,imx6dl-hdmi";
};
&ldb {
@@ -79,17 +88,4 @@
clock-names = "di0_pll", "di1_pll",
"di0_sel", "di1_sel",
"di0", "di1";
-
- lvds-channel@0 {
- crtcs = <&ipu1 0>, <&ipu1 1>;
- };
-
- lvds-channel@1 {
- crtcs = <&ipu1 0>, <&ipu1 1>;
- };
-};
-
-&hdmi {
- compatible = "fsl,imx6dl-hdmi";
- crtcs = <&ipu1 0>, <&ipu1 1>;
};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 66f220a..9cbdfe7 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -20,10 +20,6 @@
compatible = "fsl,imx6q-sabresd", "fsl,imx6q";
};
-&imx_drm {
- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
-};
-
&sata {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 187fe33..db356e6 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -132,13 +132,84 @@
};
ipu2: ipu@02800000 {
- #crtc-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,imx6q-ipu";
reg = <0x02800000 0x400000>;
interrupts = <0 8 0x4 0 7 0x4>;
clocks = <&clks 133>, <&clks 134>, <&clks 137>;
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
+
+ ipu2_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu2_di0_disp0: endpoint@0 {
+ };
+
+ ipu2_di0_hdmi: endpoint@1 {
+ remote-endpoint = <&hdmi_mux_2>;
+ };
+
+ ipu2_di0_mipi: endpoint@2 {
+ };
+
+ ipu2_di0_lvds0: endpoint@3 {
+ remote-endpoint = <&lvds0_mux_2>;
+ };
+
+ ipu2_di0_lvds1: endpoint@4 {
+ remote-endpoint = <&lvds1_mux_2>;
+ };
+ };
+
+ ipu2_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu2_di1_hdmi: endpoint@1 {
+ remote-endpoint = <&hdmi_mux_3>;
+ };
+
+ ipu2_di1_mipi: endpoint@2 {
+ };
+
+ ipu2_di1_lvds0: endpoint@3 {
+ remote-endpoint = <&lvds0_mux_3>;
+ };
+
+ ipu2_di1_lvds1: endpoint@4 {
+ remote-endpoint = <&lvds1_mux_3>;
+ };
+ };
+ };
+ };
+
+ imx-drm {
+ compatible = "fsl,imx-drm";
+ ports = <&ipu1_di0>, <&ipu1_di1>, <&ipu2_di0>, <&ipu2_di1>;
+ };
+};
+
+&hdmi {
+ compatible = "fsl,imx6q-hdmi";
+
+ port@2 {
+ reg = <2>;
+
+ hdmi_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_hdmi>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ hdmi_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_hdmi>;
};
};
};
@@ -152,15 +223,56 @@
"di0", "di1";
lvds-channel@0 {
- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+ port@2 {
+ reg = <2>;
+
+ lvds0_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_lvds0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ lvds0_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_lvds0>;
+ };
+ };
};
lvds-channel@1 {
- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+ port@2 {
+ reg = <2>;
+
+ lvds1_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_lvds1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ lvds1_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_lvds1>;
+ };
+ };
};
};
-&hdmi {
- compatible = "fsl,imx6q-hdmi";
- crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>;
+&mipi_dsi {
+ port@2 {
+ reg = <2>;
+
+ mipi_mux_2: endpoint {
+ remote-endpoint = <&ipu2_di0_mipi>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ mipi_mux_3: endpoint {
+ remote-endpoint = <&ipu2_di1_mipi>;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index dfca3e0..e75e11b 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -62,12 +62,6 @@
};
};
- imx_drm: imx-drm {
- compatible = "fsl,imx-drm";
- crtcs = <&ipu1 0>, <&ipu1 1>;
- connectors = <&ldb>;
- };
-
sound {
compatible = "fsl,imx6q-sabresd-wm8962",
"fsl,imx-audio-wm8962";
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 930ebe0..368168c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1358,23 +1358,87 @@
status = "disabled";
lvds-channel@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0>;
status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds0_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_lvds0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds0_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_lvds0>;
+ };
+ };
+
+ port@4 {
+ lvds0: endpoint {
+ };
+ };
};
lvds-channel@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <1>;
status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ lvds1_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_lvds1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ lvds1_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_lvds1>;
+ };
+ };
+
+ port@4 {
+ lvds1: endpoint {
+ };
+ };
};
};
hdmi: hdmi@0120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x00120000 0x9000>;
interrupts = <0 115 0x04>;
gpr = <&gpr>;
clocks = <&clks 123>, <&clks 124>;
clock-names = "iahb", "isfr";
status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
};
dcic1: dcic@020e4000 {
@@ -1588,8 +1652,27 @@
reg = <0x021dc000 0x4000>;
};
- mipi@021e0000 { /* MIPI-DSI */
+ mipi_dsi: mipi@021e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x021e0000 0x4000>;
+ status = "disabled";
+
+ port@0 {
+ reg = <0>;
+
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_mipi>;
+ };
+ };
};
vdoa@021e4000 {
@@ -1643,13 +1726,64 @@
};
ipu1: ipu@02400000 {
- #crtc-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,imx6q-ipu";
reg = <0x02400000 0x400000>;
interrupts = <0 6 0x4 0 5 0x4>;
clocks = <&clks 130>, <&clks 131>, <&clks 132>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
+
+ ipu1_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu1_di0_disp0: endpoint@0 {
+ };
+
+ ipu1_di0_hdmi: endpoint@1 {
+ remote-endpoint = <&hdmi_mux_0>;
+ };
+
+ ipu1_di0_mipi: endpoint@2 {
+ remote-endpoint = <&mipi_mux_0>;
+ };
+
+ ipu1_di0_lvds0: endpoint@3 {
+ remote-endpoint = <&lvds0_mux_0>;
+ };
+
+ ipu1_di0_lvds1: endpoint@4 {
+ remote-endpoint = <&lvds1_mux_0>;
+ };
+ };
+
+ ipu1_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu1_di0_disp1: endpoint@0 {
+ };
+
+ ipu1_di1_hdmi: endpoint@1 {
+ remote-endpoint = <&hdmi_mux_1>;
+ };
+
+ ipu1_di1_mipi: endpoint@2 {
+ remote-endpoint = <&mipi_mux_1>;
+ };
+
+ ipu1_di1_lvds0: endpoint@3 {
+ remote-endpoint = <&lvds0_mux_1>;
+ };
+
+ ipu1_di1_lvds1: endpoint@4 {
+ remote-endpoint = <&lvds1_mux_1>;
+ };
+ };
};
};
};
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 7/9] ARM: dts: imx53: Add IPU DI ports and endpoints, move imx-drm node to dtsi
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Greg Kroah-Hartman, dri-devel, kernel,
Grant Likely, linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
This patch connects IPU and display encoder (VGA, LVDS)
device tree nodes, as well as parallel displays on the DISP0
and DISP1 outputs, using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and encoders or panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx53-m53evk.dts | 17 +++++-----
arch/arm/boot/dts/imx53-mba53.dts | 15 +++++----
arch/arm/boot/dts/imx53-qsb.dts | 17 +++++-----
arch/arm/boot/dts/imx53.dtsi | 64 +++++++++++++++++++++++++++++++++++---
4 files changed, 89 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts
index ee6107b..0298adc 100644
--- a/arch/arm/boot/dts/imx53-m53evk.dts
+++ b/arch/arm/boot/dts/imx53-m53evk.dts
@@ -23,7 +23,6 @@
soc {
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
- crtcs = <&ipu 1>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
@@ -44,6 +43,12 @@
};
};
};
+
+ port {
+ display1_in: endpoint {
+ remote-endpoint = <&ipu_di1_disp1>;
+ };
+ };
};
backlight {
@@ -53,12 +58,6 @@
default-brightness-level = <6>;
};
- imx-drm {
- compatible = "fsl,imx-drm";
- crtcs = <&ipu 1>;
- connectors = <&display1>;
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -227,6 +226,10 @@
};
};
+&ipu_di1_disp1 {
+ remote-endpoint = <&display1_in>;
+};
+
&nfc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_nand_1>;
diff --git a/arch/arm/boot/dts/imx53-mba53.dts b/arch/arm/boot/dts/imx53-mba53.dts
index 9b6e769..3c3d69e 100644
--- a/arch/arm/boot/dts/imx53-mba53.dts
+++ b/arch/arm/boot/dts/imx53-mba53.dts
@@ -38,15 +38,14 @@
compatible = "fsl,imx-parallel-display";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_disp1_1>;
- crtcs = <&ipu 1>;
interface-pix-fmt = "rgb24";
status = "disabled";
- };
- imx-drm {
- compatible = "fsl,imx-drm";
- crtcs = <&ipu 1>;
- connectors = <&disp1>, <&tve>;
+ port {
+ display1_in: endpoint {
+ remote-endpoint = <&ipu_di1_disp1>;
+ };
+ };
};
reg_3p2v: 3p2v {
@@ -147,6 +146,10 @@
};
};
+&ipu_di1_disp1 {
+ remote-endpoint = <&display1_in>;
+};
+
&cspi {
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx53-qsb.dts b/arch/arm/boot/dts/imx53-qsb.dts
index 3cb4f77..8b25428 100644
--- a/arch/arm/boot/dts/imx53-qsb.dts
+++ b/arch/arm/boot/dts/imx53-qsb.dts
@@ -23,7 +23,6 @@
display0: display@di0 {
compatible = "fsl,imx-parallel-display";
- crtcs = <&ipu 0>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp0_1>;
@@ -46,6 +45,12 @@
pixelclk-active = <0>;
};
};
+
+ port {
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
};
gpio-keys {
@@ -72,12 +77,6 @@
};
};
- imx-drm {
- compatible = "fsl,imx-drm";
- crtcs = <&ipu 0>;
- connectors = <&display0>;
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -132,6 +131,10 @@
status = "okay";
};
+&ipu_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi
index 4307e80..5b89b91 100644
--- a/arch/arm/boot/dts/imx53.dtsi
+++ b/arch/arm/boot/dts/imx53.dtsi
@@ -45,6 +45,11 @@
};
};
+ imx-drm {
+ compatible = "fsl,imx-drm";
+ ports = <&ipu_di0>, <&ipu_di1>;
+ };
+
tzic: tz-interrupt-controller@0fffc000 {
compatible = "fsl,imx53-tzic", "fsl,tzic";
interrupt-controller;
@@ -85,13 +90,49 @@
ranges;
ipu: ipu@18000000 {
- #crtc-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
+
+ ipu_di0: port@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+
+ ipu_di0_disp0: endpoint@0 {
+ reg = <0>;
+ };
+
+ ipu_di0_lvds0: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds0_in>;
+ };
+ };
+
+ ipu_di1: port@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+
+ ipu_di1_disp1: endpoint@0 {
+ reg = <0>;
+ };
+
+ ipu_di1_lvds1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&lvds1_in>;
+ };
+
+ ipu_di1_tve: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&tve_in>;
+ };
+ };
};
aips@50000000 { /* AIPS1 */
@@ -838,14 +879,24 @@
lvds-channel@0 {
reg = <0>;
- crtcs = <&ipu 0>;
status = "disabled";
+
+ port {
+ lvds0_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+ };
};
lvds-channel@1 {
reg = <1>;
- crtcs = <&ipu 1>;
status = "disabled";
+
+ port {
+ lvds1_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+ };
};
};
@@ -1103,8 +1154,13 @@
interrupts = <92>;
clocks = <&clks 69>, <&clks 116>;
clock-names = "tve", "di_sel";
- crtcs = <&ipu 1>;
status = "disabled";
+
+ port {
+ tve_in: endpoint {
+ remote-endpoint = <&ipu_di1_tve>;
+ };
+ };
};
vpu: vpu@63ff4000 {
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 6/9] ARM: dts: imx51: Add IPU ports and endpoints, move imx-drm node to dtsi
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: David Airlie, Greg Kroah-Hartman, Shawn Guo, Fabio Estevam,
Grant Likely, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
This patch connects IPU and and parallel display device tree
nodes using the OF graph bindings described in
Documentation/devicetree/bindings/media/video-interfaces.txt
The IPU ports correspond to the two display interfaces. The
order of endpoints in the ports is arbitrary.
Since the imx-drm node now only needs to contain links to the
display interfaces, it can be moved to the SoC dtsi level. At
the board level, only connections between the display interface
ports and panels have to be added.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx51-apf51dev.dts | 11 ++++++++++-
arch/arm/boot/dts/imx51-babbage.dts | 28 ++++++++++++++++++++--------
arch/arm/boot/dts/imx51.dtsi | 22 +++++++++++++++++++++-
3 files changed, 51 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 5a7f552..d3f9814 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -18,7 +18,6 @@
display@di1 {
compatible = "fsl,imx-parallel-display";
- crtcs = <&ipu 0>;
interface-pix-fmt = "bgr666";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
@@ -41,6 +40,12 @@
pixelclk-active = <0>;
};
};
+
+ port {
+ display_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
};
gpio-keys {
@@ -122,3 +127,7 @@
};
};
};
+
+&ipu_di0_disp0 {
+ remote-endpoint = <&display_in>;
+};
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index 6ff15a0..6719271 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -23,7 +23,6 @@
display0: display@di0 {
compatible = "fsl,imx-parallel-display";
- crtcs = <&ipu 0>;
interface-pix-fmt = "rgb24";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp1_1>;
@@ -41,11 +40,16 @@
vsync-len = <10>;
};
};
+
+ port {
+ display0_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
};
display1: display@di1 {
compatible = "fsl,imx-parallel-display";
- crtcs = <&ipu 1>;
interface-pix-fmt = "rgb565";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp2_1>;
@@ -68,6 +72,12 @@
pixelclk-active = <0>;
};
};
+
+ port {
+ display1_in: endpoint {
+ remote-endpoint = <&ipu_di1_disp1>;
+ };
+ };
};
gpio-keys {
@@ -81,12 +91,6 @@
};
};
- imx-drm {
- compatible = "fsl,imx-drm";
- crtcs = <&ipu 0>, <&ipu 1>;
- connectors = <&display0>, <&display1>;
- };
-
sound {
compatible = "fsl,imx51-babbage-sgtl5000",
"fsl,imx-audio-sgtl5000";
@@ -264,6 +268,14 @@
};
};
+&ipu_di0_disp0 {
+ remote-endpoint = <&display0_in>;
+};
+
+&ipu_di1_disp1 {
+ remote-endpoint = <&display1_in>;
+};
+
&ssi2 {
fsl,mode = "i2s-slave";
status = "okay";
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 4bcdd3a..536644c 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -79,6 +79,11 @@
};
};
+ imx-drm {
+ compatible = "fsl,imx-drm";
+ ports = <&ipu_di0>, <&ipu_di1>;
+ };
+
soc {
#address-cells = <1>;
#size-cells = <1>;
@@ -92,13 +97,28 @@
};
ipu: ipu@40000000 {
- #crtc-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,imx51-ipu";
reg = <0x40000000 0x20000000>;
interrupts = <11 10>;
clocks = <&clks 59>, <&clks 110>, <&clks 61>;
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
+
+ ipu_di0: port@2 {
+ reg = <2>;
+
+ ipu_di0_disp0: endpoint {
+ };
+ };
+
+ ipu_di1: port@3 {
+ reg = <3>;
+
+ ipu_di1_disp1: endpoint {
+ };
+ };
};
aips@70000000 { /* AIPS1 */
--
1.8.5.3
--
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^ permalink raw reply related
* [RFC PATCH v3 5/9] staging: imx-drm: Document imx-hdmi device tree bindings
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Philipp Zabel, David Airlie,
Greg Kroah-Hartman, dri-devel, kernel, Grant Likely, Shawn Guo,
linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
This patch adds device tree binding documentation for the HDMI transmitter
on i.MX6.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
.../devicetree/bindings/staging/imx-drm/hdmi.txt | 53 ++++++++++++++++++++++
1 file changed, 53 insertions(+)
create mode 100644 Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt b/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
new file mode 100644
index 0000000..7dcd673a
--- /dev/null
+++ b/Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
@@ -0,0 +1,53 @@
+Device-Tree bindings for HDMI Transmitter
+
+HDMI Transmitter
+================
+
+The LVDS Display Bridge device tree node contains up to two lvds-channel
+nodes describing each of the two LVDS encoder channels of the bridge.
+
+Required properties:
+ - #address-cells : should be <1>
+ - #size-cells : should be <0>
+ - compatible : should be "fsl,imx6q-hdmi" or "fsl,imx6dl-hdmi".
+ - gpr : should be <&gpr>.
+ The phandle points to the iomuxc-gpr region containing the HDMI
+ multiplexer control register.
+ - clocks, clock-names : phandles to the HDMI iahb and isrf clocks, as described
+ in Documentation/devicetree/bindings/clock/clock-bindings.txt and
+ Documentation/devicetree/bindings/clock/imx6q-clock.txt.
+ - port@[0-4]: Up to four port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt,
+ corresponding to the four inputs to the HDMI multiplexer.
+
+example:
+
+ gpr: iomuxc-gpr@020e0000 {
+ /* ... */
+ };
+
+ hdmi: hdmi@0120000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x00120000 0x9000>;
+ interrupts = <0 115 0x04>;
+ gpr = <&gpr>;
+ clocks = <&clks 123>, <&clks 124>;
+ clock-names = "iahb", "isfr";
+
+ port@0 {
+ reg = <0>;
+
+ hdmi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_hdmi>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ hdmi_mux_1: endpoint {
+ remote-endpoint = <&ipu1_di1_hdmi>;
+ };
+ };
+ };
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 4/9] staging: imx-drm: Document updated imx-drm device tree bindings
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Philipp Zabel, David Airlie,
Greg Kroah-Hartman, dri-devel, kernel, Grant Likely, Shawn Guo,
linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
This patch updates the device tree binding documentation for i.MX IPU/display
nodes using the OF graph bindings documented in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
.../bindings/staging/imx-drm/fsl-imx-drm.txt | 48 +++++++++++++++++++---
.../devicetree/bindings/staging/imx-drm/ldb.txt | 20 +++++++--
2 files changed, 59 insertions(+), 9 deletions(-)
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
index b876d49..bfa19a4 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/fsl-imx-drm.txt
@@ -1,3 +1,22 @@
+Freescale i.MX DRM master device
+================================
+
+The freescale i.MX DRM master device is a virtual device needed to list all
+IPU or other display interface nodes that comprise the graphics subsystem.
+
+Required properties:
+- compatible: Should be "fsl,imx-drm"
+- ports: Should contain a list of phandles pointing to display interface ports
+ of IPU devices
+
+example:
+
+imx-drm {
+ compatible = "fsl,imx-drm";
+ ports = <&ipu_di0>;
+};
+
+
Freescale i.MX IPUv3
====================
@@ -7,18 +26,31 @@ Required properties:
datasheet
- interrupts: Should contain sync interrupt and error interrupt,
in this order.
-- #crtc-cells: 1, See below
- resets: phandle pointing to the system reset controller and
reset line index, see reset/fsl,imx-src.txt for details
+Optional properties:
+- port@[0-3]: Port nodes with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ Ports 0 and 1 should correspond to CSI0 and CSI1,
+ ports 2 and 3 should correspond to DI0 and DI1, respectively.
example:
ipu: ipu@18000000 {
- #crtc-cells = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
compatible = "fsl,imx53-ipu";
reg = <0x18000000 0x080000000>;
interrupts = <11 10>;
resets = <&src 2>;
+
+ ipu_di0: port@2 {
+ reg = <2>;
+
+ ipu_di0_disp0: endpoint {
+ remote-endpoint = <&display_in>;
+ };
+ };
};
Parallel display support
@@ -26,19 +58,25 @@ Parallel display support
Required properties:
- compatible: Should be "fsl,imx-parallel-display"
-- crtc: the crtc this display is connected to, see below
Optional properties:
- interface_pix_fmt: How this display is connected to the
- crtc. Currently supported types: "rgb24", "rgb565", "bgr666"
+ display interface. Currently supported types: "rgb24", "rgb565", "bgr666"
- edid: verbatim EDID data block describing attached display.
- ddc: phandle describing the i2c bus handling the display data
channel
+- port: A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
example:
display@di0 {
compatible = "fsl,imx-parallel-display";
edid = [edid-data];
- crtc = <&ipu 0>;
interface-pix-fmt = "rgb24";
+
+ port {
+ display_in: endpoint {
+ remote-endpoint = <&ipu_di0_disp0>;
+ };
+ };
};
diff --git a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
index ed93778..578a1fc 100644
--- a/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
+++ b/Documentation/devicetree/bindings/staging/imx-drm/ldb.txt
@@ -50,12 +50,14 @@ have a look at Documentation/devicetree/bindings/video/display-timing.txt.
Required properties:
- reg : should be <0> or <1>
- - crtcs : a list of phandles with index pointing to the IPU display interfaces
- that can be used as video source for this channel.
- fsl,data-mapping : should be "spwg" or "jeida"
This describes how the color bits are laid out in the
serialized LVDS signal.
- fsl,data-width : should be <18> or <24>
+ - port: A port node with endpoint definitions as defined in
+ Documentation/devicetree/bindings/media/video-interfaces.txt.
+ On i.MX6, there should be four ports (port@[0-3]) that correspond
+ to the four LVDS multiplexer inputs.
example:
@@ -77,23 +79,33 @@ ldb: ldb@53fa8008 {
lvds-channel@0 {
reg = <0>;
- crtcs = <&ipu 0>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {
/* ... */
};
+
+ port {
+ lvds0_in: endpoint {
+ remote-endpoint = <&ipu_di0_lvds0>;
+ };
+ };
};
lvds-channel@1 {
reg = <1>;
- crtcs = <&ipu 1>;
fsl,data-mapping = "spwg";
fsl,data-width = <24>;
display-timings {
/* ... */
};
+
+ port {
+ lvds1_in: endpoint {
+ remote-endpoint = <&ipu_di1_lvds1>;
+ };
+ };
};
};
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 3/9] staging: imx-drm-core: Use OF graph to find components and connections between encoder and crtcs
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Greg Kroah-Hartman, dri-devel, kernel,
Grant Likely, linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
This patch adds support to find the involved components connected to the
IPU display interface ports using the OF graph bindings documented in
Documentation/devicetree/bindings/media/video-interfaces.txt
Each display interface needs to have an associated port node in the
device tree. We can associate this node with the crtc platform device
and use it to find the crtc corresponding to a given port node instead
of using a combination of parent device node and id number, as before.
Explicitly converting the void* cookie to the port device tree node
allows to get rid of the ipu_id and di_id fields. The multiplexer
setting on i.MX6 now can be obtained from the port id (reg property)
in the device tree.
The imx-drm node now needs a ports property that contains phandles
to each of the IPU display interface port nodes. From there, all
attached encoders are scanned and enabled encoders are added to a
waiting list.
The bind order makes sure that once all components are probed, crtcs
are bound before encoders, so that imx_drm_encoder_parse_of can be
called from the encoder bind callbacks.
For parsing the OF graph, temporary copies of the V4L2 OF graph
helpers are used, that can be removed again once those are available
at a generic place.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/staging/imx-drm/imx-drm-core.c | 203 ++++++++++++++++++++++-----------
drivers/staging/imx-drm/imx-drm.h | 5 +-
drivers/staging/imx-drm/imx-hdmi.c | 2 +-
drivers/staging/imx-drm/imx-ldb.c | 4 +-
drivers/staging/imx-drm/ipuv3-crtc.c | 47 ++++++--
5 files changed, 185 insertions(+), 76 deletions(-)
diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index 98a97a2..92246d9 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -30,6 +30,11 @@
struct imx_drm_crtc;
+struct imx_drm_component {
+ struct device_node *of_node;
+ struct list_head list;
+};
+
struct imx_drm_device {
struct drm_device *drm;
struct imx_drm_crtc *crtc[MAX_CRTC];
@@ -41,9 +46,7 @@ struct imx_drm_crtc {
struct drm_crtc *crtc;
int pipe;
struct imx_drm_crtc_helper_funcs imx_drm_helper_funcs;
- void *cookie;
- int id;
- int mux_id;
+ struct device_node *port;
};
static int legacyfb_depth = 16;
@@ -341,14 +344,11 @@ err_kms:
/*
* imx_drm_add_crtc - add a new crtc
- *
- * The return value if !NULL is a cookie for the caller to pass to
- * imx_drm_remove_crtc later.
*/
int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
struct imx_drm_crtc **new_crtc,
const struct imx_drm_crtc_helper_funcs *imx_drm_helper_funcs,
- void *cookie, int id)
+ struct device_node *port)
{
struct imx_drm_device *imxdrm = drm->dev_private;
struct imx_drm_crtc *imx_drm_crtc;
@@ -370,9 +370,7 @@ int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
imx_drm_crtc->imx_drm_helper_funcs = *imx_drm_helper_funcs;
imx_drm_crtc->pipe = imxdrm->pipes++;
- imx_drm_crtc->cookie = cookie;
- imx_drm_crtc->id = id;
- imx_drm_crtc->mux_id = imx_drm_crtc->pipe;
+ imx_drm_crtc->port = port;
imx_drm_crtc->crtc = crtc;
imxdrm->crtc[imx_drm_crtc->pipe] = imx_drm_crtc;
@@ -416,21 +414,26 @@ int imx_drm_remove_crtc(struct imx_drm_crtc *imx_drm_crtc)
EXPORT_SYMBOL_GPL(imx_drm_remove_crtc);
/*
- * Find the DRM CRTC possible mask for the device node cookie/id.
+ * Find the DRM CRTC possible mask for the connected endpoint.
*
* The encoder possible masks are defined by their position in the
* mode_config crtc_list. This means that CRTCs must not be added
* or removed once the DRM device has been fully initialised.
*/
static uint32_t imx_drm_find_crtc_mask(struct imx_drm_device *imxdrm,
- void *cookie, int id)
+ struct device_node *endpoint)
{
+ struct device_node *port;
unsigned i;
+ port = imx_drm_of_get_remote_port(endpoint);
+ if (!port)
+ return 0;
+ of_node_put(port);
+
for (i = 0; i < MAX_CRTC; i++) {
struct imx_drm_crtc *imx_drm_crtc = imxdrm->crtc[i];
- if (imx_drm_crtc && imx_drm_crtc->id == id &&
- imx_drm_crtc->cookie == cookie)
+ if (imx_drm_crtc && imx_drm_crtc->port == port)
return drm_crtc_mask(imx_drm_crtc->crtc);
}
@@ -441,26 +444,20 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np)
{
struct imx_drm_device *imxdrm = drm->dev_private;
+ struct device_node *ep = NULL;
uint32_t crtc_mask = 0;
- int i, ret = 0;
-
- for (i = 0; !ret; i++) {
- struct of_phandle_args args;
- uint32_t mask;
- int id;
+ int i;
- ret = of_parse_phandle_with_args(np, "crtcs", "#crtc-cells", i,
- &args);
- if (ret == -ENOENT)
+ for (i = 0; ; i++) {
+ ep = imx_drm_of_get_next_endpoint(np, ep);
+ if (!ep)
break;
- if (ret < 0)
- return ret;
- id = args.args_count > 0 ? args.args[0] : 0;
- crtc_mask |= imx_drm_find_crtc_mask(imxdrm, args.np, id);
- of_node_put(args.np);
+ crtc_mask |= imx_drm_find_crtc_mask(imxdrm, ep);
}
+ if (ep)
+ of_node_put(ep);
if (i == 0 || !crtc_mask)
return -ENOENT;
@@ -473,11 +470,36 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
}
EXPORT_SYMBOL_GPL(imx_drm_encoder_parse_of);
-int imx_drm_encoder_get_mux_id(struct drm_encoder *encoder)
+/*
+ * @node: device tree node containing encoder input ports
+ * @encoder: drm_encoder
+ */
+int imx_drm_encoder_get_mux_id(struct device_node *node,
+ struct drm_encoder *encoder)
{
struct imx_drm_crtc *imx_crtc = imx_drm_find_crtc(encoder->crtc);
+ struct device_node *ep = NULL;
+ struct device_node *port;
+ int id, ret;
+
+ if (!node || !imx_crtc)
+ return -EINVAL;
+
+ do {
+ ep = imx_drm_of_get_next_endpoint(node, ep);
+ if (!ep)
+ break;
- return imx_crtc ? imx_crtc->mux_id : -EINVAL;
+ port = imx_drm_of_get_remote_port(ep);
+ of_node_put(port);
+ if (port == imx_crtc->port) {
+ ret = of_property_read_u32(ep->parent, "reg", &id);
+ of_node_put(ep);
+ return ret ? ret : id;
+ }
+ } while (ep);
+
+ return -EINVAL;
}
EXPORT_SYMBOL_GPL(imx_drm_encoder_get_mux_id);
@@ -520,48 +542,29 @@ static struct drm_driver imx_drm_driver = {
.patchlevel = 0,
};
-static int compare_parent_of(struct device *dev, void *data)
-{
- struct of_phandle_args *args = data;
- return dev->parent && dev->parent->of_node == args->np;
-}
-
static int compare_of(struct device *dev, void *data)
{
- return dev->of_node == data;
-}
-
-static int imx_drm_add_components(struct device *master, struct master *m)
-{
- struct device_node *np = master->of_node;
- unsigned i;
- int ret;
-
- for (i = 0; ; i++) {
- struct of_phandle_args args;
+ struct device_node *np = data;
- ret = of_parse_phandle_with_fixed_args(np, "crtcs", 1,
- i, &args);
- if (ret)
- break;
-
- ret = component_master_add_child(m, compare_parent_of, &args);
- of_node_put(args.np);
-
- if (ret)
- return ret;
+ /* Special case for LDB, one device for two channels */
+ if (of_node_cmp(np->name, "lvds-channel") == 0) {
+ np = of_get_parent(np);
+ of_node_put(np);
}
- for (i = 0; ; i++) {
- struct device_node *node;
+ return dev->of_node == np;
+}
- node = of_parse_phandle(np, "connectors", i);
- if (!node)
- break;
+static LIST_HEAD(imx_drm_components);
- ret = component_master_add_child(m, compare_of, node);
- of_node_put(node);
+static int imx_drm_add_components(struct device *master, struct master *m)
+{
+ struct imx_drm_component *component;
+ int ret;
+ list_for_each_entry(component, &imx_drm_components, list) {
+ ret = component_master_add_child(m, compare_of,
+ component->of_node);
if (ret)
return ret;
}
@@ -584,9 +587,81 @@ static const struct component_master_ops imx_drm_ops = {
.unbind = imx_drm_unbind,
};
+static struct imx_drm_component *imx_drm_find_component(struct device *dev,
+ struct device_node *node)
+{
+ struct imx_drm_component *component;
+
+ list_for_each_entry(component, &imx_drm_components, list)
+ if (component->of_node == node)
+ return component;
+
+ return NULL;
+}
+
+static int imx_drm_add_component(struct device *dev, struct device_node *node)
+{
+ struct imx_drm_component *component;
+
+ if (imx_drm_find_component(dev, node))
+ return 0;
+
+ component = devm_kzalloc(dev, sizeof(*component), GFP_KERNEL);
+ if (!component)
+ return -ENOMEM;
+
+ component->of_node = node;
+ list_add_tail(&component->list, &imx_drm_components);
+
+ return 0;
+}
+
static int imx_drm_platform_probe(struct platform_device *pdev)
{
+ struct device_node *ep, *port, *remote;
int ret;
+ int i;
+
+ /*
+ * Bind the IPU display interface ports first, so that
+ * imx_drm_encoder_parse_of called from encoder .bind callbacks
+ * works as expected.
+ */
+ for (i = 0; ; i++) {
+ port = of_parse_phandle(pdev->dev.of_node, "ports", i);
+ if (!port)
+ break;
+
+ ret = imx_drm_add_component(&pdev->dev, port);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (i == 0) {
+ dev_err(&pdev->dev, "missing 'ports' property\n");
+ return -ENODEV;
+ }
+
+ /* Then bind all encoders */
+ for (i = 0; ; i++) {
+ port = of_parse_phandle(pdev->dev.of_node, "ports", i);
+ if (!port)
+ break;
+
+ for_each_child_of_node(port, ep) {
+ remote = imx_drm_of_get_remote_port_parent(ep);
+ if (!remote || !of_device_is_available(remote)) {
+ of_node_put(remote);
+ continue;
+ }
+
+ ret = imx_drm_add_component(&pdev->dev, remote);
+ of_node_put(remote);
+ if (ret < 0)
+ return ret;
+ }
+ of_node_put(port);
+ }
ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
if (ret)
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index 793a80b..447ddd7 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -30,7 +30,7 @@ struct imx_drm_crtc_helper_funcs {
int imx_drm_add_crtc(struct drm_device *drm, struct drm_crtc *crtc,
struct imx_drm_crtc **new_crtc,
const struct imx_drm_crtc_helper_funcs *imx_helper_funcs,
- void *cookie, int id);
+ struct device_node *port);
int imx_drm_remove_crtc(struct imx_drm_crtc *);
int imx_drm_init_drm(struct platform_device *pdev,
int preferred_bpp);
@@ -49,7 +49,8 @@ int imx_drm_panel_format_pins(struct drm_encoder *encoder,
int imx_drm_panel_format(struct drm_encoder *encoder,
u32 interface_pix_fmt);
-int imx_drm_encoder_get_mux_id(struct drm_encoder *encoder);
+int imx_drm_encoder_get_mux_id(struct device_node *node,
+ struct drm_encoder *encoder);
int imx_drm_encoder_parse_of(struct drm_device *drm,
struct drm_encoder *encoder, struct device_node *np);
diff --git a/drivers/staging/imx-drm/imx-hdmi.c b/drivers/staging/imx-drm/imx-hdmi.c
index a677e33..8509814 100644
--- a/drivers/staging/imx-drm/imx-hdmi.c
+++ b/drivers/staging/imx-drm/imx-hdmi.c
@@ -1453,7 +1453,7 @@ static void imx_hdmi_encoder_prepare(struct drm_encoder *encoder)
static void imx_hdmi_encoder_commit(struct drm_encoder *encoder)
{
struct imx_hdmi *hdmi = container_of(encoder, struct imx_hdmi, encoder);
- int mux = imx_drm_encoder_get_mux_id(encoder);
+ int mux = imx_drm_encoder_get_mux_id(hdmi->dev->of_node, encoder);
imx_hdmi_set_ipu_di_mux(hdmi, mux);
diff --git a/drivers/staging/imx-drm/imx-ldb.c b/drivers/staging/imx-drm/imx-ldb.c
index 5168c76..301c430 100644
--- a/drivers/staging/imx-drm/imx-ldb.c
+++ b/drivers/staging/imx-drm/imx-ldb.c
@@ -168,7 +168,7 @@ static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
u32 pixel_fmt;
unsigned long serial_clk;
unsigned long di_clk = mode->clock * 1000;
- int mux = imx_drm_encoder_get_mux_id(encoder);
+ int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
/* dual channel LVDS mode */
@@ -203,7 +203,7 @@ static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
struct imx_ldb *ldb = imx_ldb_ch->ldb;
int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
- int mux = imx_drm_encoder_get_mux_id(encoder);
+ int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
if (dual) {
clk_prepare_enable(ldb->clk[0]);
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index e646017..a8d0178 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -350,10 +350,8 @@ static int ipu_crtc_init(struct ipu_crtc *ipu_crtc,
return ret;
}
- ret = imx_drm_add_crtc(drm, &ipu_crtc->base,
- &ipu_crtc->imx_crtc,
- &ipu_crtc_helper_funcs,
- ipu_crtc->dev->parent->of_node, pdata->di);
+ ret = imx_drm_add_crtc(drm, &ipu_crtc->base, &ipu_crtc->imx_crtc,
+ &ipu_crtc_helper_funcs, ipu_crtc->dev->of_node);
if (ret) {
dev_err(ipu_crtc->dev, "adding crtc failed with %d.\n", ret);
goto err_put_resources;
@@ -401,6 +399,28 @@ err_put_resources:
return ret;
}
+static struct device_node *ipu_drm_get_port_by_id(struct device_node *parent,
+ int port_id)
+{
+ struct device_node *port;
+ int id, ret;
+
+ port = of_get_child_by_name(parent, "port");
+ while (port) {
+ ret = of_property_read_u32(port, "reg", &id);
+ if (!ret && id == port_id)
+ return port;
+
+ do {
+ port = of_get_next_child(parent, port);
+ if (!port)
+ return NULL;
+ } while (of_node_cmp(port->name, "port"));
+ }
+
+ return NULL;
+}
+
static int ipu_drm_bind(struct device *dev, struct device *master, void *data)
{
struct ipu_client_platformdata *pdata = dev->platform_data;
@@ -441,16 +461,29 @@ static const struct component_ops ipu_crtc_ops = {
static int ipu_drm_probe(struct platform_device *pdev)
{
+ struct device *dev = &pdev->dev;
+ struct ipu_client_platformdata *pdata = dev->platform_data;
int ret;
- if (!pdev->dev.platform_data)
+ if (!dev->platform_data)
return -EINVAL;
- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+ if (!dev->of_node) {
+ /* Associate crtc device with the corresponding DI port node */
+ dev->of_node = ipu_drm_get_port_by_id(dev->parent->of_node,
+ pdata->di + 2);
+ if (!dev->of_node) {
+ dev_err(dev, "missing port@%d node in %s\n",
+ pdata->di + 2, dev->parent->of_node->full_name);
+ return -ENODEV;
+ }
+ }
+
+ ret = dma_set_coherent_mask(dev, DMA_BIT_MASK(32));
if (ret)
return ret;
- return component_add(&pdev->dev, &ipu_crtc_ops);
+ return component_add(dev, &ipu_crtc_ops);
}
static int ipu_drm_remove(struct platform_device *pdev)
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 2/9] staging: imx-drm: Add temporary copies of v4l2-of parsing functions
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Philipp Zabel, David Airlie,
Greg Kroah-Hartman, dri-devel, kernel, Grant Likely, Shawn Guo,
linux-arm-kernel
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
From: Philipp Zabel <philipp.zabel@gmail.com>
The existing v4l2-of parser functions for the video interface bindings
described in Documentation/device-tree/bindings/media/video-interfaces.txt
are useful for DRM drivers, too. They will be moved to drivers/media
so they can be used by drm drivers, too. Until then, duplicate the
v4l2-of parser functions temporarily.
Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com>
---
drivers/staging/imx-drm/Makefile | 2 +-
drivers/staging/imx-drm/imx-drm-of.c | 132 +++++++++++++++++++++++++++++++++++
drivers/staging/imx-drm/imx-drm.h | 6 ++
3 files changed, 139 insertions(+), 1 deletion(-)
create mode 100644 drivers/staging/imx-drm/imx-drm-of.c
diff --git a/drivers/staging/imx-drm/Makefile b/drivers/staging/imx-drm/Makefile
index 129e3a3..743b875 100644
--- a/drivers/staging/imx-drm/Makefile
+++ b/drivers/staging/imx-drm/Makefile
@@ -1,5 +1,5 @@
-imxdrm-objs := imx-drm-core.o
+imxdrm-objs := imx-drm-core.o imx-drm-of.o
obj-$(CONFIG_DRM_IMX) += imxdrm.o
diff --git a/drivers/staging/imx-drm/imx-drm-of.c b/drivers/staging/imx-drm/imx-drm-of.c
new file mode 100644
index 0000000..e14b4f3
--- /dev/null
+++ b/drivers/staging/imx-drm/imx-drm-of.c
@@ -0,0 +1,132 @@
+/*
+ * Video Interface OF binding parsing library
+ *
+ * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
+ * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
+ *
+ * Copyright (C) 2012 Renesas Electronics Corp.
+ * Author: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of version 2 of the GNU General Public License as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/of.h>
+
+/**
+ * imx_drm_of_get_next_endpoint() - get next endpoint node
+ * @parent: pointer to the parent device node
+ * @prev: previous endpoint node, or NULL to get first
+ *
+ * Return: An 'endpoint' node pointer with refcount incremented. Refcount
+ * of the passed @prev node is decremented.
+ */
+struct device_node *imx_drm_of_get_next_endpoint(
+ const struct device_node *parent, struct device_node *prev)
+{
+ struct device_node *endpoint;
+ struct device_node *port = NULL;
+
+ if (!parent)
+ return NULL;
+
+ if (!prev) {
+ struct device_node *node;
+ /*
+ * It's the first call, we have to find a port subnode
+ * within this node or within an optional 'ports' node.
+ */
+ node = of_get_child_by_name(parent, "ports");
+ if (node)
+ parent = node;
+
+ port = of_get_child_by_name(parent, "port");
+
+ if (port) {
+ /* Found a port, get an endpoint. */
+ endpoint = of_get_next_child(port, NULL);
+ of_node_put(port);
+ } else {
+ endpoint = NULL;
+ }
+
+ if (!endpoint)
+ pr_err("%s(): no endpoint nodes specified for %s\n",
+ __func__, parent->full_name);
+ of_node_put(node);
+ } else {
+ port = of_get_parent(prev);
+ if (!port) {
+ /* Hm, has someone given us the root node ?... */
+ of_node_put(prev);
+ return NULL;
+ }
+
+ endpoint = of_get_next_child(port, prev);
+ if (endpoint) {
+ of_node_put(port);
+ return endpoint;
+ }
+
+ /* No more endpoints under this port, try the next one. */
+ do {
+ port = of_get_next_child(parent, port);
+ if (!port)
+ return NULL;
+ } while (of_node_cmp(port->name, "port"));
+
+ /* Pick up the first endpoint in this port. */
+ endpoint = of_get_next_child(port, NULL);
+ of_node_put(port);
+ }
+
+ return endpoint;
+}
+EXPORT_SYMBOL_GPL(imx_drm_of_get_next_endpoint);
+
+/**
+ * imx_drm_of_get_remote_port_parent() - get remote port's parent node
+ * @node: pointer to a local endpoint device_node
+ *
+ * Return: Remote device node associated with remote endpoint node linked
+ * to @node. Use of_node_put() on it when done.
+ */
+struct device_node *imx_drm_of_get_remote_port_parent(
+ const struct device_node *node)
+{
+ struct device_node *np;
+ unsigned int depth;
+
+ /* Get remote endpoint node. */
+ np = of_parse_phandle(node, "remote-endpoint", 0);
+
+ /* Walk 3 levels up only if there is 'ports' node. */
+ for (depth = 3; depth && np; depth--) {
+ np = of_get_next_parent(np);
+ if (depth == 2 && of_node_cmp(np->name, "ports"))
+ break;
+ }
+ return np;
+}
+EXPORT_SYMBOL(imx_drm_of_get_remote_port_parent);
+
+/**
+ * imx_drm_of_get_remote_port() - get remote port node
+ * @node: pointer to a local endpoint device_node
+ *
+ * Return: Remote port node associated with remote endpoint node linked
+ * to @node. Use of_node_put() on it when done.
+ */
+struct device_node *imx_drm_of_get_remote_port(const struct device_node *node)
+{
+ struct device_node *np;
+
+ /* Get remote endpoint node. */
+ np = of_parse_phandle(node, "remote-endpoint", 0);
+ if (!np)
+ return NULL;
+ return of_get_next_parent(np);
+}
+EXPORT_SYMBOL_GPL(imx_drm_of_get_remote_port);
diff --git a/drivers/staging/imx-drm/imx-drm.h b/drivers/staging/imx-drm/imx-drm.h
index aa21028..793a80b 100644
--- a/drivers/staging/imx-drm/imx-drm.h
+++ b/drivers/staging/imx-drm/imx-drm.h
@@ -58,4 +58,10 @@ int imx_drm_connector_mode_valid(struct drm_connector *connector,
void imx_drm_connector_destroy(struct drm_connector *connector);
void imx_drm_encoder_destroy(struct drm_encoder *encoder);
+struct device_node *imx_drm_of_get_next_endpoint(
+ const struct device_node *parent, struct device_node *prev);
+struct device_node *imx_drm_of_get_remote_port_parent(
+ const struct device_node *node);
+struct device_node *imx_drm_of_get_remote_port(const struct device_node *node);
+
#endif /* _IMX_DRM_H_ */
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 1/9] staging: imx-drm-core: don't request probe deferral in imx_drm_encoder_parse_of
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: devel, devicetree, Philipp Zabel, David Airlie,
Greg Kroah-Hartman, dri-devel, kernel, Grant Likely, Shawn Guo,
linux-arm-kernel, Lucas Stach
In-Reply-To: <1392723370-4772-1-git-send-email-p.zabel@pengutronix.de>
From: Lucas Stach <l.stach@pengutronix.de>
Since imx_drm_encoder_parse_of is called from the encoder bind callbacks,
it is too late to request probe deferral. Rather the core should make sure
that the crtcs are bound before the encoders, after all needed components
are probed.
This fixes probe failure when using the LDB on i.MX6.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
drivers/staging/imx-drm/imx-drm-core.c | 16 ++++------------
1 file changed, 4 insertions(+), 12 deletions(-)
diff --git a/drivers/staging/imx-drm/imx-drm-core.c b/drivers/staging/imx-drm/imx-drm-core.c
index dcba518..98a97a2 100644
--- a/drivers/staging/imx-drm/imx-drm-core.c
+++ b/drivers/staging/imx-drm/imx-drm-core.c
@@ -457,21 +457,13 @@ int imx_drm_encoder_parse_of(struct drm_device *drm,
return ret;
id = args.args_count > 0 ? args.args[0] : 0;
- mask = imx_drm_find_crtc_mask(imxdrm, args.np, id);
+ crtc_mask |= imx_drm_find_crtc_mask(imxdrm, args.np, id);
of_node_put(args.np);
-
- /*
- * If we failed to find the CRTC(s) which this encoder is
- * supposed to be connected to, it's because the CRTC has
- * not been registered yet. Defer probing, and hope that
- * the required CRTC is added later.
- */
- if (mask == 0)
- return -EPROBE_DEFER;
-
- crtc_mask |= mask;
}
+ if (i == 0 || !crtc_mask)
+ return -ENOENT;
+
encoder->possible_crtcs = crtc_mask;
/* FIXME: this is the mask of outputs which can clone this output. */
--
1.8.5.3
^ permalink raw reply related
* [RFC PATCH v3 0/9] imx-drm dt bindings
From: Philipp Zabel @ 2014-02-18 11:36 UTC (permalink / raw)
To: Russell King - ARM Linux
Cc: David Airlie, Greg Kroah-Hartman, Shawn Guo, Fabio Estevam,
Grant Likely, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
devel-gWbeCf7V1WCQmaza687I9mD2FQJk+8+b,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
Hi,
here is an updated and more complete version of the imx-drm DT binding
series. These patches apply on top of Russell's second preview of the
imx-drm cleanup series on v3.14-rc2. I have added device tree bindings
between IPU and the encoders as documented in
Documentation/devicetree/bindings/media/video-interfaces.txt
and used those to determine the possible_crtcs and mux_id.
The crtc cookie is replaced with a the port device tree node,
which is unique and therefore allows to get rid of the di_id
comparison. Storing the multiplexer input numbers in the device
tree removes the need to know the ipu_id. This should also allow
to replace IPU2 with LCDIF on i.MX6 Solo more easily.
In v3 also connections between display interface ports and encoders are
used to find all necessary components, so that only the display interfaces
have to be configured in the imx-drm node. This allows to move the imx-drm
node into the SoC level dtsi. I've also updated the existing i.MX51 and
i.MX53 device trees this time and updated/added the devicetree binding
documentation.
Patch 2/9 adds a temporary copy of the v4l2_of parser functions. Those
are going to be moved to some place where they can be used by drm drivers,
eventually, so those local copies can be dropped again.
regards
Philipp
Lucas Stach (1):
staging: imx-drm-core: don't request probe deferral in
imx_drm_encoder_parse_of
Philipp Zabel (8):
staging: imx-drm: Add temporary copies of v4l2-of parsing functions
staging: imx-drm-core: Use OF graph to find components and connections
between encoder and crtcs
staging: imx-drm: Document updated imx-drm device tree bindings
staging: imx-drm: Document imx-hdmi device tree bindings
ARM: dts: imx51: Add IPU ports and endpoints, move imx-drm node to
dtsi
ARM: dts: imx53: Add IPU DI ports and endpoints, move imx-drm node to
dtsi
ARM: dts: imx6qdl: Add IPU DI ports and endpoints, move imx-drm node
to dtsi
staging: imx-drm: Update TODO
.../bindings/staging/imx-drm/fsl-imx-drm.txt | 48 ++++-
.../devicetree/bindings/staging/imx-drm/hdmi.txt | 53 +++++
.../devicetree/bindings/staging/imx-drm/ldb.txt | 20 +-
arch/arm/boot/dts/imx51-apf51dev.dts | 11 +-
arch/arm/boot/dts/imx51-babbage.dts | 28 ++-
arch/arm/boot/dts/imx51.dtsi | 22 ++-
arch/arm/boot/dts/imx53-m53evk.dts | 17 +-
arch/arm/boot/dts/imx53-mba53.dts | 15 +-
arch/arm/boot/dts/imx53-qsb.dts | 17 +-
arch/arm/boot/dts/imx53.dtsi | 64 +++++-
arch/arm/boot/dts/imx6dl.dtsi | 22 +--
arch/arm/boot/dts/imx6q-sabresd.dts | 4 -
arch/arm/boot/dts/imx6q.dtsi | 124 +++++++++++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 6 -
arch/arm/boot/dts/imx6qdl.dtsi | 138 ++++++++++++-
drivers/staging/imx-drm/Makefile | 2 +-
drivers/staging/imx-drm/TODO | 5 -
drivers/staging/imx-drm/imx-drm-core.c | 217 ++++++++++++++-------
drivers/staging/imx-drm/imx-drm-of.c | 132 +++++++++++++
drivers/staging/imx-drm/imx-drm.h | 11 +-
drivers/staging/imx-drm/imx-hdmi.c | 2 +-
drivers/staging/imx-drm/imx-ldb.c | 4 +-
drivers/staging/imx-drm/ipuv3-crtc.c | 47 ++++-
23 files changed, 842 insertions(+), 167 deletions(-)
create mode 100644 Documentation/devicetree/bindings/staging/imx-drm/hdmi.txt
create mode 100644 drivers/staging/imx-drm/imx-drm-of.c
--
1.8.5.3
--
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^ permalink raw reply
* Re: [PATCH RESEND v11 2/2] dma: Add Freescale eDMA engine driver support
From: Vinod Koul @ 2014-02-18 11:29 UTC (permalink / raw)
To: Jingchang Lu
Cc: dan.j.williams-ral2JQCrhuEAvxtiuMwx3w, arnd-r2nGTMty4D4,
shawn.guo-QSEj5FYQhm4dnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, swarren-3lzwWm7+Weoh9ZMKESR00Q,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dmaengine-u79uwXL29TY76Z2rM5mHXA, Alison Wang
In-Reply-To: <1392689832-17011-3-git-send-email-b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
On Tue, Feb 18, 2014 at 10:17:12AM +0800, Jingchang Lu wrote:
> Add Freescale enhanced direct memory(eDMA) controller support.
> This module can be found on Vybrid and LS-1 SoCs.
>
> Signed-off-by: Alison Wang <b18965-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Signed-off-by: Jingchang Lu <b35083-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> Acked-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Applied, thanks
--
~Vinod
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^ permalink raw reply
* Re: [PATCH v3 1/3] dma: Support multiple interleaved frames with non-contiguous memory
From: Srikanth Thokala @ 2014-02-18 11:28 UTC (permalink / raw)
To: Jassi Brar
Cc: Srikanth Thokala, Williams, Dan J, Koul, Vinod,
michal.simek-gjFFaj9aHVfQT0dZR+AlfA, Grant Likely,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, devicetree-u79uwXL29TY76Z2rM5mHXA,
Levente Kurusa, Lars-Peter Clausen, lkml,
dmaengine-u79uwXL29TY76Z2rM5mHXA, Andy Shevchenko,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <CAJe_Zhc_GNNSDWNFuk+cMHEqxfSCJB_ey=Bf+SwJK-nS=u9ceg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Feb 17, 2014 at 3:27 PM, Jassi Brar <jaswinder.singh-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> On 15 February 2014 17:30, Srikanth Thokala <sthokal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org> wrote:
>> The current implementation of interleaved DMA API support multiple
>> frames only when the memory is contiguous by incrementing src_start/
>> dst_start members of interleaved template.
>>
>> But, when the memory is non-contiguous it will restrict slave device
>> to not submit multiple frames in a batch. This patch handles this
>> issue by allowing the slave device to send array of interleaved dma
>> templates each having a different memory location.
>>
> How fragmented could be memory in your case? Is it inefficient to
> submit separate transfers for each segment/frame?
> It will help if you could give a typical example (chunk size and gap
> in bytes) of what you worry about.
With scatter-gather engine feature in the hardware, submitting separate
transfers for each frame look inefficient. As an example, our DMA engine
supports up to 16 video frames, with each frame (a typical video frame
size) being contiguous in memory but frames are scattered into different
locations. We could not definitely submit frame by frame as it would be
software overhead (HW interrupting for each frame) resulting in video lags.
By this approach, it will allow slave device to submit multiple frames at
once.
Srikanth
>
> Thanks,
> Jassi
> --
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
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> Please read the FAQ at http://www.tux.org/lkml/
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^ permalink raw reply
* Re: [PATCH 1/2] clk: fixed-rate: use full DT node name
From: Mark Rutland @ 2014-02-18 11:23 UTC (permalink / raw)
To: Stephen Warren
Cc: Mike Turquette,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <52FE4798.3010605-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
On Fri, Feb 14, 2014 at 04:43:04PM +0000, Stephen Warren wrote:
> On 02/14/2014 03:35 AM, Mark Rutland wrote:
> > On Fri, Feb 14, 2014 at 06:16:52AM +0000, Stephen Warren wrote:
> >> clk-fixed-rate currently names clocks according to a node's name without
> >> the unit address. When faced with the legal and technically correct DT
> >> structure below, this causes rgistration attempts for 3 clocks with the
> >> same name, 2 of which fail.
> >>
> >> clocks {
> >> compatible = "simple-bus";
> >> #address-cells = <1>;
> >> #size-cells = <0>;
> >>
> >> clk_mmc: clock@0 {
> >> compatible = "fixed-clock";
> >> reg = <0>;
> >> ...
> >> clk_i2c: clock@1 {
> >> compatible = "fixed-clock";
> >> reg = <1>;
> >> ...
> >> clk_spi: clock@2 {
> >> compatible = "fixed-clock";
> >> reg = <2>;
> >> ...
> >
> > I'd argue that this case isn't valid.
>
> Well, it's very widely used, and was the result of numerous discussions
> of how this kind of thing should be represented:-/
Maybe we have to live with it then. :/
>
> > The fixed-clock binding doesn't define a reg, yet simple bus binding
> > implies that the reg property of child nodes should be interpretted as
> > the same address space as their parent (MMIO in this case?). The
> > fixed-clock nodes reg proeprties clearly aren't MMIO addresses.
> >
> > Additionally, the _requred_ ranges property is missing.
>
> Perhaps we need to invent a simple-container instead then?
As you mention in your other reply, it makes some sense to omit ranges
if the address space is disjoint. My concern is that the address space
is meaningless and arbitrary. If we had a real disjoint address space
we'd have another kind of bus node as the container.
>
> > It's just nonsensical; rename them to clock_{0,1,..} instead and get rid
> > of the reg properties. Then they're named uniquely.
>
> That's not legal either. DT node names are supposed to represent the
> type of device/object (i.e. just "clock"), not the identity of the
> device/object (i.e. not include IDs etc.). Hence, the node name needs to
> be "clock" for all of them, and the unit address must be used to
> differentiate them.
As far as I can see from ePAPR, the only requriement is:
The node-name shall start with a lower or uppercase character and
should describe the general class of device.
IMO clock_1 describes the general class of device as well as clock@1,
while also not filling a unexpected property with a meaningless value.
Thanks,
Mark.
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^ permalink raw reply
* Re: [PATCH v4 1/3] ARM: EXYNOS: initial board support for exynos5260 SoC
From: Arnd Bergmann @ 2014-02-18 11:03 UTC (permalink / raw)
To: Rahul Sharma
Cc: linux-samsung-soc, devicetree, linux-arm-kernel, kgene.kim,
tomasz.figa, joshi, r.sh.open, Pankaj Dubey
In-Reply-To: <1392721076-26630-2-git-send-email-rahul.sharma@samsung.com>
On Tuesday 18 February 2014 16:27:54 Rahul Sharma wrote:
> diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
> index 7654f19..1cc52c9 100644
> --- a/arch/arm/mach-exynos/common.c
> +++ b/arch/arm/mach-exynos/common.c
> @@ -176,6 +176,15 @@ static struct map_desc exynos5250_iodesc[] __initdata = {
> },
> };
>
> +static struct map_desc exynos5260_iodesc[] __initdata = {
> + {
> + .virtual = (unsigned long)S5P_VA_SYSRAM_NS,
> + .pfn = __phys_to_pfn(EXYNOS5260_PA_SYSRAM_NS),
> + .length = SZ_4K,
> + .type = MT_DEVICE,
> + },
> +};
> +
> static struct map_desc exynos5_iodesc[] __initdata = {
> {
> .virtual = (unsigned long)S3C_VA_SYS,
> @@ -331,6 +340,8 @@ static void __init exynos_map_io(void)
> iotable_init(exynos4x12_iodesc, ARRAY_SIZE(exynos4x12_iodesc));
> if (soc_is_exynos5250())
> iotable_init(exynos5250_iodesc, ARRAY_SIZE(exynos5250_iodesc));
> + if (soc_is_exynos5260())
> + iotable_init(exynos5260_iodesc, ARRAY_SIZE(exynos5260_iodesc));
> }
As I commented before, I think we really shouldn't do this any more: There
is no excuse why you still need to add SoC specific code here. Please put
the SYSRAM into DT and make a proper abstraction for it so you don't have
to modify the kernel every time a new SoC variant comes out.
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index 37ea261..790009e 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -51,6 +51,7 @@ static void __init exynos5_dt_machine_init(void)
>
> static char const *exynos5_dt_compat[] __initdata = {
> "samsung,exynos5250",
> + "samsung,exynos5260",
> "samsung,exynos5420",
> "samsung,exynos5440",
> NULL
This one is ok, but I'd suggest also adding a generic "samsung,exynos5" string here,
for the same reason.
> diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
> index 31164b3..0110df3 100644
> --- a/arch/arm/plat-samsung/include/plat/cpu.h
> +++ b/arch/arm/plat-samsung/include/plat/cpu.h
> @@ -46,6 +46,7 @@ extern unsigned long samsung_cpu_id;
> #define EXYNOS4_CPU_MASK 0xFFFE0000
>
> #define EXYNOS5250_SOC_ID 0x43520000
> +#define EXYNOS5260_SOC_ID 0xE5260000
> #define EXYNOS5420_SOC_ID 0xE5420000
> #define EXYNOS5440_SOC_ID 0xE5440000
> #define EXYNOS5_SOC_MASK 0xFFFFF000
> @@ -68,6 +69,7 @@ IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK)
> IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK)
> +IS_SAMSUNG_CPU(exynos5260, EXYNOS5260_SOC_ID, EXYNOS5_SOC_MASK)
> IS_SAMSUNG_CPU(exynos5420, EXYNOS5420_SOC_ID, EXYNOS5_SOC_MASK)
> IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
>
> @@ -148,6 +150,12 @@ IS_SAMSUNG_CPU(exynos5440, EXYNOS5440_SOC_ID, EXYNOS5_SOC_MASK)
> # define soc_is_exynos5250() 0
> #endif
>
> +#if defined(CONFIG_SOC_EXYNOS5260)
> +# define soc_is_exynos5260() is_samsung_exynos5260()
> +#else
> +# define soc_is_exynos5260() 0
> +#endif
> +
> #if defined(CONFIG_SOC_EXYNOS5420)
> # define soc_is_exynos5420() is_samsung_exynos5420()
> #else
This doesn't seem to be used anywhere.
Arnd
^ permalink raw reply
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