* [PATCH v4 6/7] ARM: dts: imx6qdl: Add power-domain information to gpc node
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
The PGC that is part of GPC controls isolation and power sequencing of the
power domains. The PU power domain will be handled by the generic pm domain
framework and needs a phandle to the PU regulator to turn off power when
the domain is disabled.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 253d82c..fd1be55 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -598,9 +598,22 @@
};
gpc: gpc@020dc000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
+ pu-supply = <®_pu>;
+
+ pd_pu: pu-power-domain@020dc260 {
+ compatible = "fsl,imx6q-power-domain";
+ reg = <0x020dc260 0x10>;
+ };
+
+ pd_arm: cpu-power-domain@020dc2a0 {
+ compatible = "fsl,imx6q-power-domain";
+ reg = <0x020dc2a0 0x10>;
+ };
};
gpr: iomuxc-gpr@020e0000 {
--
1.8.5.3
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* [PATCH v4 5/7] ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp delay
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
The PU regulator is enabled during boot, but not necessarily always-on.
It can be disabled by the generic pm domain framework when the PU power
domain is shut down. The ramp delay of 150 us might be a bit conservative,
the value is taken from the Freescale kernel.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index fb28b2e..253d82c 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -515,7 +515,8 @@
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
- regulator-always-on;
+ regulator-enable-ramp-delay = <150>;
+ regulator-boot-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
--
1.8.5.3
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* [PATCH v4 4/7] ARM: imx6: gpc: Add observed worst case latencies
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
This avoids the "... latency exceeded, new value ..." warnings
emitted by the power domain framework code whenever the PU domain
is enabled or disabled.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/mach-imx/gpc.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index c126d22..427d1d1 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -225,6 +225,8 @@ static struct generic_pm_domain imx6q_pu_domain = {
.name = "PU",
.power_off = imx6q_pm_pu_power_off,
.power_on = imx6q_pm_pu_power_on,
+ .power_off_latency_ns = 25000,
+ .power_on_latency_ns = 2000000,
};
int imx6q_pm_clk_add(struct device *dev)
@@ -289,6 +291,13 @@ int imx6q_pm_clk_remove(struct device *dev)
return 0;
}
+static struct gpd_timing_data pu_timing_data = {
+ .stop_latency_ns = 2000,
+ .start_latency_ns = 2000,
+ .save_state_latency_ns = 5000,
+ .restore_state_latency_ns = 20000000, /* VPU firmware reload */
+};
+
static int imx6q_pm_notifier_call(struct notifier_block *nb,
unsigned long event, void *data)
{
@@ -303,7 +312,7 @@ static int imx6q_pm_notifier_call(struct notifier_block *nb,
if (!np || np != imx6q_pu_domain.of_node)
return NOTIFY_DONE;
- ret = pm_genpd_of_add_device(np, dev);
+ ret = __pm_genpd_of_add_device(np, dev, &pu_timing_data);
if (ret)
dev_err(dev, "failed to add to power domain: %d\n",
ret);
--
1.8.5.3
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* [PATCH v4 3/7] ARM: imx6: gpc: Add pm clock support to PU power domain
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Drivers still handle clocks themselves, we only enable pm clocks of the
GPU and VPU devices in the PU power domain temporarily during powerup
so that the reset machinery can work.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
arch/arm/mach-imx/gpc.c | 74 +++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index abddcc1..c126d22 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -18,6 +18,7 @@
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
+#include <linux/pm_clock.h>
#include <linux/pm_domain.h>
#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
@@ -182,6 +183,7 @@ static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
{
+ struct pm_domain_data *pdd;
int ret;
u32 val;
int sw, sw2iso;
@@ -192,6 +194,10 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
return ret;
}
+ /* Enable PM clocks for all devices in the PU domain */
+ list_for_each_entry(pdd, &genpd->dev_list, list_node)
+ pm_clk_resume(pdd->dev);
+
/* Gate off PU domain when GPU/VPU when powered down */
writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
@@ -208,6 +214,10 @@ static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
/* Wait ISO + ISO2SW IPG clock cycles */
ndelay((sw + sw2iso) * 1000 / 66);
+ /* Disable PM clocks for all devices in the PU domain */
+ list_for_each_entry(pdd, &genpd->dev_list, list_node)
+ pm_clk_suspend(pdd->dev);
+
return 0;
}
@@ -217,6 +227,68 @@ static struct generic_pm_domain imx6q_pu_domain = {
.power_on = imx6q_pm_pu_power_on,
};
+int imx6q_pm_clk_add(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ const char *con_id;
+ struct clk *clk;
+ int i = 0;
+
+ /* Add and prepare named clocks */
+ while (!of_property_read_string_index(np, "clock-names", i, &con_id)) {
+ pm_clk_add(dev, con_id);
+ clk = of_clk_get(np, i);
+ if (!IS_ERR(clk)) {
+ clk_prepare(clk);
+ clk_put(clk);
+ }
+ i++;
+ }
+
+ /* If no named clocks are given, add and prepare unnamed clock */
+ if (i == 1 && of_find_property(dev->of_node, "clocks", NULL)) {
+ pm_clk_add(dev, NULL);
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ clk_prepare(clk);
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
+int imx6q_pm_clk_remove(struct device *dev)
+{
+ struct device_node *np = dev->of_node;
+ const char *con_id;
+ struct clk *clk;
+ int i = 0;
+
+ /* Remove and unprepare named clocks */
+ while (!of_property_read_string_index(np, "clock-names", i, &con_id)) {
+ pm_clk_remove(dev, con_id);
+ clk = of_clk_get(np, i);
+ if (!IS_ERR(clk)) {
+ clk_unprepare(clk);
+ clk_put(clk);
+ }
+ i++;
+ }
+
+ /* If no named clocks are given, remove and unprepare unnamed clock */
+ if (i == 1 && of_find_property(dev->of_node, "clocks", NULL)) {
+ pm_clk_remove(dev, NULL);
+ clk = of_clk_get(np, 0);
+ if (!IS_ERR(clk)) {
+ clk_unprepare(clk);
+ clk_put(clk);
+ }
+ }
+
+ return 0;
+}
+
static int imx6q_pm_notifier_call(struct notifier_block *nb,
unsigned long event, void *data)
{
@@ -235,6 +307,7 @@ static int imx6q_pm_notifier_call(struct notifier_block *nb,
if (ret)
dev_err(dev, "failed to add to power domain: %d\n",
ret);
+ imx6q_pm_clk_add(dev);
break;
case BUS_NOTIFY_UNBOUND_DRIVER:
genpd = dev_to_genpd(dev);
@@ -245,6 +318,7 @@ static int imx6q_pm_notifier_call(struct notifier_block *nb,
if (ret)
dev_err(dev, "failed to remove from power domain: %d\n",
ret);
+ imx6q_pm_clk_remove(dev);
break;
}
--
1.8.5.3
--
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* [PATCH v4 2/7] ARM: imx6: gpc: Add PU power domain for GPU/VPU
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
When generic pm domain support is enabled, the PGC can be used
to completely gate power to the PU power domain containing GPU3D,
GPU2D, and VPU cores.
This code triggers the PGC powerdown sequence to disable the GPU/VPU
isolation cells and gate power and then disables the PU regulator.
To reenable, the reverse powerup sequence is triggered after the PU
regulaotor is enabled again.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v3:
- Use fsl,power-domain property name to link devices to power domains
---
arch/arm/mach-imx/Kconfig | 2 +
arch/arm/mach-imx/gpc.c | 173 ++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 175 insertions(+)
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 33567aa..3c58f2e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -808,6 +808,7 @@ config SOC_IMX6Q
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
select PM_OPP if PM
+ select PM_GENERIC_DOMAINS if PM
help
This enables support for Freescale i.MX6 Quad processor.
@@ -827,6 +828,7 @@ config SOC_IMX6SL
select PL310_ERRATA_588369 if CACHE_PL310
select PL310_ERRATA_727915 if CACHE_PL310
select PL310_ERRATA_769419 if CACHE_PL310
+ select PM_GENERIC_DOMAINS if PM
help
This enables support for Freescale i.MX6 SoloLite processor.
diff --git a/arch/arm/mach-imx/gpc.c b/arch/arm/mach-imx/gpc.c
index 586e017..abddcc1 100644
--- a/arch/arm/mach-imx/gpc.c
+++ b/arch/arm/mach-imx/gpc.c
@@ -10,19 +10,32 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <linux/clk.h>
+#include <linux/delay.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/regulator/consumer.h>
#include <linux/irqchip/arm-gic.h>
#include "common.h"
+#include "hardware.h"
+#define GPC_CNTR 0x000
#define GPC_IMR1 0x008
+#define GPC_PGC_GPU_PDN 0x260
+#define GPC_PGC_GPU_PUPSCR 0x264
+#define GPC_PGC_GPU_PDNSCR 0x268
#define GPC_PGC_CPU_PDN 0x2a0
#define IMR_NUM 4
+#define GPU_VPU_PUP_REQ BIT(1)
+#define GPU_VPU_PDN_REQ BIT(0)
+
static void __iomem *gpc_base;
static u32 gpc_wake_irqs[IMR_NUM];
static u32 gpc_saved_imrs[IMR_NUM];
@@ -138,3 +151,163 @@ void __init imx_gpc_init(void)
gic_arch_extn.irq_unmask = imx_gpc_irq_unmask;
gic_arch_extn.irq_set_wake = imx_gpc_irq_set_wake;
}
+
+static struct regulator *pu_reg;
+
+static int imx6q_pm_pu_power_off(struct generic_pm_domain *genpd)
+{
+ u32 val;
+ int iso, iso2sw;
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PDNSCR);
+ iso = val & 0x3f;
+ iso2sw = (val >> 8) & 0x3f;
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Request GPC to power down GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PDN_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((iso + iso2sw) * 1000 / 66);
+
+ regulator_disable(pu_reg);
+
+ return 0;
+}
+
+static int imx6q_pm_pu_power_on(struct generic_pm_domain *genpd)
+{
+ int ret;
+ u32 val;
+ int sw, sw2iso;
+
+ ret = regulator_enable(pu_reg);
+ if (ret) {
+ pr_err("%s: failed to enable regulator: %d\n", __func__, ret);
+ return ret;
+ }
+
+ /* Gate off PU domain when GPU/VPU when powered down */
+ writel_relaxed(0x1, gpc_base + GPC_PGC_GPU_PDN);
+
+ /* Read ISO and ISO2SW power down delays */
+ val = readl_relaxed(gpc_base + GPC_PGC_GPU_PUPSCR);
+ sw = val & 0x3f;
+ sw2iso = (val >> 8) & 0x3f;
+
+ /* Request GPC to power up GPU/VPU */
+ val = readl_relaxed(gpc_base + GPC_CNTR);
+ val |= GPU_VPU_PUP_REQ;
+ writel_relaxed(val, gpc_base + GPC_CNTR);
+
+ /* Wait ISO + ISO2SW IPG clock cycles */
+ ndelay((sw + sw2iso) * 1000 / 66);
+
+ return 0;
+}
+
+static struct generic_pm_domain imx6q_pu_domain = {
+ .name = "PU",
+ .power_off = imx6q_pm_pu_power_off,
+ .power_on = imx6q_pm_pu_power_on,
+};
+
+static int imx6q_pm_notifier_call(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct generic_pm_domain *genpd;
+ struct device *dev = data;
+ struct device_node *np;
+ int ret;
+
+ switch (event) {
+ case BUS_NOTIFY_BIND_DRIVER:
+ np = of_parse_phandle(dev->of_node, "fsl,power-domain", 0);
+ if (!np || np != imx6q_pu_domain.of_node)
+ return NOTIFY_DONE;
+
+ ret = pm_genpd_of_add_device(np, dev);
+ if (ret)
+ dev_err(dev, "failed to add to power domain: %d\n",
+ ret);
+ break;
+ case BUS_NOTIFY_UNBOUND_DRIVER:
+ genpd = dev_to_genpd(dev);
+ if (IS_ERR(genpd) || genpd != &imx6q_pu_domain)
+ return NOTIFY_DONE;
+
+ ret = pm_genpd_remove_device(genpd, dev);
+ if (ret)
+ dev_err(dev, "failed to remove from power domain: %d\n",
+ ret);
+ break;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static struct notifier_block imx6q_platform_nb = {
+ .notifier_call = imx6q_pm_notifier_call,
+};
+
+static int imx_gpc_probe(struct platform_device *pdev)
+{
+ struct device_node *np;
+ bool is_off;
+ int ret;
+
+ np = of_get_child_by_name(pdev->dev.of_node, "pu-power-domain");
+ if (!np) {
+ dev_err(&pdev->dev, "missing pu-power-domain node\n");
+ return -EINVAL;
+ }
+ imx6q_pu_domain.of_node = np;
+
+ pu_reg = devm_regulator_get(&pdev->dev, "pu");
+ if (IS_ERR(pu_reg)) {
+ ret = PTR_ERR(pu_reg);
+ dev_err(&pdev->dev, "failed to get pu regulator: %d\n", ret);
+ return ret;
+ }
+
+ /* The regulator is initially enabled */
+ ret = regulator_enable(pu_reg);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed to enable pu regulator: %d\n", ret);
+ return ret;
+ }
+
+ is_off = IS_ENABLED(CONFIG_PM_RUNTIME);
+ if (is_off)
+ imx6q_pm_pu_power_off(&imx6q_pu_domain);
+
+ pm_genpd_init(&imx6q_pu_domain, NULL, is_off);
+ bus_register_notifier(&platform_bus_type, &imx6q_platform_nb);
+
+ return 0;
+}
+
+static struct of_device_id imx_gpc_dt_ids[] = {
+ { .compatible = "fsl,imx6q-gpc" },
+ { }
+};
+
+static struct platform_driver imx_gpc_driver = {
+ .driver = {
+ .name = "imx-gpc",
+ .owner = THIS_MODULE,
+ .of_match_table = imx_gpc_dt_ids,
+ },
+ .probe = imx_gpc_probe,
+};
+
+static int __init imx_pgc_init(void)
+{
+ return platform_driver_register(&imx_gpc_driver);
+}
+subsys_initcall(imx_pgc_init);
--
1.8.5.3
--
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^ permalink raw reply related
* [PATCH v4 1/7] Documentation: Add device tree bindings for Freescale i.MX GPC
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
In-Reply-To: <1392737687-25003-1-git-send-email-p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
The i.MX6 contains a power controller that controls power gating and
sequencing for the SoC's power domains.
Signed-off-by: Philipp Zabel <p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
Changes since v3:
- Updated documentation to use fsl,power-domain property name
and pu-power-domain as node name.
- Removed address-cells/size-cells
---
.../devicetree/bindings/power/fsl,imx-gpc.txt | 58 ++++++++++++++++++++++
1 file changed, 58 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
new file mode 100644
index 0000000..05927a7
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
@@ -0,0 +1,58 @@
+Freescale i.MX General Power Controller
+=======================================
+
+The i.MX6Q General Power Control (GPC) block contains DVFS load tracking
+counters and Power Gating Control (PGC) for the CPU and PU (GPU/VPU) power
+domains.
+
+Required properties:
+- compatible: Should be "fsl,imx6q-gpc"
+- reg: should be register base and length as documented in the
+ datasheet
+- interrupts: Should contain GPC interrupt request 1
+- pu-supply: Link to the LDO regulator powering the PU power domain
+
+The gpc node should contain a 'pu-power-domain' subnode that serves as a
+phandle target for devices belonging to the PU power domain:
+
+Power domains controlled by a PGC register set
+==============================================
+
+Required properties:
+- compatible: Should be "fsl,imx6q-power-domain"
+- reg: should be register base and length as documented in the
+ datasheet
+
+Specifying power domain for IP modules
+======================================
+
+IP cores belonging to a power domain should contain a 'power-domain' property
+that is a phandle pointing to the power-domain subnode of the gpc device node.
+
+Required properties:
+- fsl,power-domain: A phandle pointing to the power-domain device tree node
+
+
+Example:
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupts = <0 89 0x04 0 90 0x04>;
+ pu-supply = <®_pu>;
+
+ pd_pu: pu-power-domain@020dc260 {
+ compatible = "fsl,imx6q-power-domain";
+ reg = <0x020dc260 0x10>;
+ };
+ };
+
+Example of a device that is part of a power domain:
+
+ vpu: vpu@02040000 {
+ reg = <0x02040000 0x3c000>;
+ /* ... */
+ fsl,power-domain = <&pd_pu>;
+ /* ... */
+ };
+
--
1.8.5.3
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^ permalink raw reply related
* [PATCH v4 0/7] i.MX6 PU power domain support
From: Philipp Zabel @ 2014-02-18 15:34 UTC (permalink / raw)
To: Shawn Guo
Cc: Rob Herring, Mark Rutland, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Philipp Zabel
The i.MX6Q can gate off the CPU and PU (GPU/VPU) power domains using the
Power Gating Controller (PGC) in the GPC register space. The CPU power
domain is already handled by wait state code, but the PU power domain can
be controlled using the generic power domain framework and power off the PU
supply regulator if all devices in the power domain are (runtime) suspended.
This patchset adds a GPC platform device initialized at subsys_initcall time
(after anatop regulators) that binds to the gpc device tree node and sets up
the PU power domain:
gpc: gpc@020dc000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupts = <0 89 0x04 0 90 0x04>;
pu-supply = <®_pu>;
pd_pu: pu-power-domain@020dc260 {
compatible = "fsl,imx6q-power-domain";
reg = <0x020dc260 0x10>;
};
pd_arm: cpu-power-domain@020dc2a0 {
compatible = "fsl,imx6q-power-domain";
reg = <0x020dc2a0 0x10>;
};
};
The cpu-power-domain node is included for completeness' sake, it is not
currently used by the code.
It registers a platform bus notifier so that it can add GPU and VPU devices
to the power domain when they are bound. If finds devices to be added to the
power domain by scanning the device tree for nodes that contain a
power-domain = <&pd_pu>;
property.
For i.MX6QDL there is only one power domain that can be disabled at runtime,
on i.MX6SL there is an additional DISPLAY power domain, which is not yet
handled by the code.
Changes since v3:
- Use fsl,power-domain property name to link devices to power domains
regards
Philipp
Philipp Zabel (7):
Documentation: Add device tree bindings for Freescale i.MX GPC
ARM: imx6: gpc: Add PU power domain for GPU/VPU
ARM: imx6: gpc: Add pm clock support to PU power domain
ARM: imx6: gpc: Add observed worst case latencies
ARM: dts: imx6qdl: Allow disabling the PU regulator, add a enable ramp
delay
ARM: dts: imx6qdl: Add power-domain information to gpc node
ARM: dts: imx6sl: Add power-domain information to gpc node
.../devicetree/bindings/power/fsl,imx-gpc.txt | 58 +++++
arch/arm/boot/dts/imx6qdl.dtsi | 16 +-
arch/arm/boot/dts/imx6sl.dtsi | 18 ++
arch/arm/mach-imx/Kconfig | 2 +
arch/arm/mach-imx/gpc.c | 256 +++++++++++++++++++++
5 files changed, 349 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/power/fsl,imx-gpc.txt
--
1.8.5.3
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^ permalink raw reply
* Re: [PATCH v7 03/12] mfd: omap-usb-host: Use clock names as per function for reference clocks
From: Roger Quadros @ 2014-02-18 15:28 UTC (permalink / raw)
To: Lee Jones
Cc: tony-4v6yS6AI5VpBDgjK7y7TUQ, bcousson-rdvid1DuHRBWk0Htik3J/w,
balbi-l0cyMroinI0, nm-l0cyMroinI0, khilman-QSEj5FYQhm4dnm+yROfE0A,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, Samuel Ortiz
In-Reply-To: <20140214133330.GC13293@lee--X1>
On 02/14/2014 03:33 PM, Lee Jones wrote:
>>>> Use a meaningful name for the reference clocks so that it indicates the function.
>>>>
>>>> CC: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>>>> CC: Samuel Ortiz <sameo-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
>>>> Signed-off-by: Roger Quadros <rogerq-l0cyMroinI0@public.gmane.org>
>>>> ---
>>>> drivers/mfd/omap-usb-host.c | 6 +++---
>>>> 1 file changed, 3 insertions(+), 3 deletions(-)
>>>>
>>>> diff --git a/drivers/mfd/omap-usb-host.c b/drivers/mfd/omap-usb-host.c
>>>> index 60a3bed..ce620a8 100644
>>>> --- a/drivers/mfd/omap-usb-host.c
>>>> +++ b/drivers/mfd/omap-usb-host.c
>>>> @@ -714,21 +714,21 @@ static int usbhs_omap_probe(struct platform_device *pdev)
>>>> goto err_mem;
>>>> }
>>>>
>>>> - omap->xclk60mhsp1_ck = devm_clk_get(dev, "xclk60mhsp1_ck");
>>>> + omap->xclk60mhsp1_ck = devm_clk_get(dev, "refclk_60m_ext_p1");
>>>
>>> You can't do that. These changes will have to be in the same patch as
>>> the core change i.e. where they are initialised.
>>
>> I'm not touching them anywhere in this series. When core changes are you
>> referring to?
>
> The ones in:
> arch/arm/mach-omap2/cclock3xxx_data.c
OK, right. They are now no longer needed so I'll get rid of them.
In fact that change should either be in a separate patch or combined with PATCH 2
in this series. What do you suggest?
cheers,
-roger
>
>>>> if (IS_ERR(omap->xclk60mhsp1_ck)) {
>>>> ret = PTR_ERR(omap->xclk60mhsp1_ck);
>>>> dev_err(dev, "xclk60mhsp1_ck failed error:%d\n", ret);
>>>> goto err_mem;
>>>> }
>>>>
>>>> - omap->xclk60mhsp2_ck = devm_clk_get(dev, "xclk60mhsp2_ck");
>>>> + omap->xclk60mhsp2_ck = devm_clk_get(dev, "refclk_60m_ext_p2");
>>>> if (IS_ERR(omap->xclk60mhsp2_ck)) {
>>>> ret = PTR_ERR(omap->xclk60mhsp2_ck);
>>>> dev_err(dev, "xclk60mhsp2_ck failed error:%d\n", ret);
>>>> goto err_mem;
>>>> }
>>>>
>>>> - omap->init_60m_fclk = devm_clk_get(dev, "init_60m_fclk");
>>>> + omap->init_60m_fclk = devm_clk_get(dev, "refclk_60m_int");
>>>> if (IS_ERR(omap->init_60m_fclk)) {
>>>> ret = PTR_ERR(omap->init_60m_fclk);
>>>> dev_err(dev, "init_60m_fclk failed error:%d\n", ret);
>>>
>>
>
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^ permalink raw reply
* Re: [PATCH v7 5/8] ARM: dts: sun7i: Add support for mmc
From: Hans de Goede @ 2014-02-18 15:10 UTC (permalink / raw)
To: Maxime Ripard, David Lanzendörfer
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140218142221.GJ3142@lukather>
Hi,
On 02/18/2014 03:22 PM, Maxime Ripard wrote:
> On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
>> Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
>> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>> ---
>> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 +++
>> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 +++
>> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++
>> arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++
>> 4 files changed, 100 insertions(+)
>>
>
> I'd prefer to have three patches here:
> - One that add the controllers
> - One that add the pin muxing options
> - One that enable the controllers on the various boards.
>
>> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
>> index 5c51cb8..ae800b6 100644
>> --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
>> +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
>> @@ -34,6 +34,14 @@
>> };
>> };
>>
>> + mmc0: mmc@01c0f000 {
>> + pinctrl-names = "default", "default";
>> + pinctrl-0 = <&mmc0_pins_a>;
>> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
>
> This can be made a single pinctrl group, you don't need the pinctrl-1
> stuff, it only complicates the node.
Then how do we deal with boards which use a different gpio for card-detect ?
In that case we don't want to change the mux setting of the reference
design cd pin. IOW I believe that having 2 separate pinctrl settings for
this is the rigt thing todo. I would prefer using just mmc0_cd_pin_a instead
of _reference_design though.
Oh wait, you're probably talking about using:
pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin_reference_design>;
Yes that would be better.
>
>> + cd-gpios = <&pio 7 1 0>; /* PH1 */
>> + status = "okay";
>> + };
>> +
>> pinctrl@01c20800 {
>> led_pins_cubieboard2: led_pins@0 {
>> allwinner,pins = "PH20", "PH21";
>> diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
>> index f9dcb61..370cef84 100644
>> --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
>> +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
>> @@ -19,6 +19,14 @@
>> compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
>>
>> soc@01c00000 {
>> + mmc0: mmc@01c0f000 {
>> + pinctrl-names = "default", "default";
>> + pinctrl-0 = <&mmc0_pins_a>;
>> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
>> + cd-gpios = <&pio 7 1 0>; /* PH1 */
>> + status = "okay";
>> + };
>> +
>> pinctrl@01c20800 {
>> led_pins_cubietruck: led_pins@0 {
>> allwinner,pins = "PH7", "PH11", "PH20", "PH21";
>> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
>> index ead3013..685ec06 100644
>> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
>> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
>> @@ -34,7 +34,30 @@
>> };
>> };
>>
>> + mmc0: mmc@01c0f000 {
>> + pinctrl-names = "default", "default";
>> + pinctrl-0 = <&mmc0_pins_a>;
>> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
>> + cd-gpios = <&pio 7 1 0>; /* PH1 */
>> + status = "okay";
>> + };
>> +
>> + mmc3: mmc@01c12000 {
>> + pinctrl-names = "default", "default";
>> + pinctrl-0 = <&mmc3_pins_a>;
>> + pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
>> + cd-gpios = <&pio 7 11 0>; /* PH11 */
>> + status = "okay";
>> + };
>> +
>> pinctrl@01c20800 {
>> + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
>> + allwinner,pins = "PH11";
>> + allwinner,function = "gpio_in";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <1>;
>> + };
>> +
>> led_pins_olinuxino: led_pins@0 {
>> allwinner,pins = "PH2";
>> allwinner,function = "gpio_out";
>> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
>> index 9ff0948..5b55414 100644
>> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
>> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
>> @@ -355,6 +355,46 @@
>> #size-cells = <0>;
>> };
>>
>> + mmc0: mmc@01c0f000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c0f000 0x1000>;
>> + clocks = <&ahb_gates 8>, <&mmc0_clk>;
>> + clock-names = "ahb", "mod";
>> + interrupts = <0 32 4>;
>> + bus-width = <4>;
>
> This belongs to the board, the controller itself is able to handle
> several bus width.
I believe that providing some form of default in the dtsi makes sense
here and all boards we've seen sofar always use 4 bits, we can always
override this from the dts file itself.
>
>> + status = "disabled";
>> + };
>> +
>> + mmc1: mmc@01c10000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c10000 0x1000>;
>> + clocks = <&ahb_gates 9>, <&mmc1_clk>;
>> + clock-names = "ahb", "mod";
>> + interrupts = <0 33 4>;
>> + bus-width = <4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc2: mmc@01c11000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c11000 0x1000>;
>> + clocks = <&ahb_gates 10>, <&mmc2_clk>;
>> + clock-names = "ahb", "mod";
>> + interrupts = <0 34 4>;
>> + bus-width = <4>;
>> + status = "disabled";
>> + };
>> +
>> + mmc3: mmc@01c12000 {
>> + compatible = "allwinner,sun5i-a13-mmc";
>> + reg = <0x01c12000 0x1000>;
>> + clocks = <&ahb_gates 11>, <&mmc3_clk>;
>> + clock-names = "ahb", "mod";
>> + interrupts = <0 35 4>;
>> + bus-width = <4>;
>> + status = "disabled";
>> + };
>> +
>> pio: pinctrl@01c20800 {
>> compatible = "allwinner,sun7i-a20-pinctrl";
>> reg = <0x01c20800 0x400>;
>> @@ -432,6 +472,27 @@
>> allwinner,drive = <0>;
>> allwinner,pull = <0>;
>> };
>> +
>> + mmc0_pins_a: mmc0@0 {
>> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
>> + allwinner,function = "mmc0";
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> +
>> + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
>> + allwinner,pins = "PH1";
>> + allwinner,function = "gpio_in";
>> + allwinner,drive = <0>;
>> + allwinner,pull = <1>;
>> + };
>> +
>> + mmc3_pins_a: mmc3@0 {
>> + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
>> + allwinner,function = "mmc3";
>> + allwinner,drive = <3>;
>> + allwinner,pull = <0>;
>> + };
>> };
>>
>> timer@01c20c00 {
>>
>
> Looks good otherwise.
>
> Thanks!
> Maxime
>
Regards,
Hans
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^ permalink raw reply
* Re: [PATCH V6 03/12] phy: st-miphy40lp: Add binding information
From: Arnd Bergmann @ 2014-02-18 14:58 UTC (permalink / raw)
To: Mark Rutland
Cc: Mohit KUMAR DCG, Pratyush ANAND, Viresh Kumar,
Kishon Vijay Abraham I, spear-devel,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20140218122324.GA23267-NuALmloUBlrZROr8t4l/smS4ubULX0JqMm0uRHvK7Nw@public.gmane.org>
On Tuesday 18 February 2014, Mark Rutland wrote:
> >
> > - These are Spear SoC specific miscellaneous registers. Here these are used for
> > to configure sata/pcie aux clock.
> > >
> > > > +- phy-id: Instance id of the phy.
> > > > +- #phy-cells : from the generic PHY bindings, must be 1.
> > > > + - 1st cell: phandle to the phy node.
> > > > + - 2nd cell: 0 if phy (in 1st cell) is to be used for SATA, 1 for PCIe
> > > > + and 2 for Super Speed USB.
> > >
> > > One cell or two?
> >
> > - No of cells are two, is this the question?
>
> The description of #phy-cells says it must be 1. Presumably it must be 2.
The description here is counting the phandle, while we normally only
count the arguments following the phandle. #phy-cells=<1> is correct
here, but the description should be written a bit clearer.
Arnd
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^ permalink raw reply
* [PATCH 13/35] mtd: st_spi_fsm: Add device-tree binding documentation
From: Lee Jones @ 2014-02-18 14:55 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel
Cc: Angus.Clark, devicetree, lee.jones, DCG_UPD_stlinux_kernel,
linux-mtd, computersforpeace, dwmw2
In-Reply-To: <1392735362-1245-1-git-send-email-lee.jones@linaro.org>
Cc: devicetree@vger.kernel.org
Acked-by Angus Clark <angus.clark@st.com>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
---
Documentation/devicetree/bindings/mtd/st-fsm.txt | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mtd/st-fsm.txt
diff --git a/Documentation/devicetree/bindings/mtd/st-fsm.txt b/Documentation/devicetree/bindings/mtd/st-fsm.txt
new file mode 100644
index 0000000..c248939
--- /dev/null
+++ b/Documentation/devicetree/bindings/mtd/st-fsm.txt
@@ -0,0 +1,26 @@
+* ST-Microelectronics SPI FSM Serial (NOR) Flash Controller
+
+Required properties:
+ - compatible : Should be "st,spi-fsm"
+ - reg : Contains register's location and length.
+ - reg-names : Should contain the reg names "spi-fsm"
+ - interrupts : The interrupt number
+ - pinctrl-0 : Standard Pinctrl phandle (see: pinctrl/pinctrl-bindings.txt)
+
+Optional properties:
+ - st,syscfg : Phandle to boot-device system configuration registers
+ - st,boot-device-reg : Address of the aforementioned boot-device register(s)
+ - st,boot-device-spi : Expected boot-device value if booted via this device
+
+Example:
+ spifsm: spifsm@fe902000{
+ compatible = "st,spi-fsm";
+ reg = <0xfe902000 0x1000>;
+ reg-names = "spi-fsm";
+ pinctrl-0 = <&pinctrl_fsm>;
+ st,syscfg = <&syscfg_rear>;
+ st,boot-device-reg = <0x958>;
+ st,boot-device-spi = <0x1a>;
+ status = "okay";
+ };
+
--
1.8.3.2
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
^ permalink raw reply related
* Re: [PATCH v2] of_mdio: fix phy interrupt passing
From: Sergei Shtylyov @ 2014-02-18 14:48 UTC (permalink / raw)
To: Ben Dooks, grant.likely
Cc: linux-kernel, devicetree, linux-kernel, netdev, linux-sh
In-Reply-To: <1392725818-558-1-git-send-email-ben.dooks@codethink.co.uk>
Hello.
On 18-02-2014 16:16, Ben Dooks wrote:
> The of_mdiobus_register_phy() is not setting phy->irq thus causing
> some drivers to incorrectly assume that the PHY does not have an
> IRQ associated with it. Not only do some drivers report no IRQ
> they do not install an interrupt handler for the PHY.
> Simplify the code setting irq and set the phy->irq at the same
> time so that we cover the following issues, which should cover
> all the cases the code will find:
> - Set phy->irq if node has irq property and mdio->irq is NULL
> - Set phy->irq if node has no irq and mdio->irq is not NULL
> - Leave phy->irq as PHY_POLL default if none of the above
> This fixes the issue:
> net eth0: attached PHY 1 (IRQ -1) to driver Micrel KSZ8041RNLI
> to the correct:
> net eth0: attached PHY 1 (IRQ 416) to driver Micrel KSZ8041RNLI
> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
> ---
> Since v1:
> - Updated phy->irq setting code
> - Deal with issue if mdio->irq array NULL
> Notes:
> It was discussed if this should be two patches, but we end up
> making enough changes in #2 the same area as #1 means that we
> basically rewrite #1 in #2. So keep it as 1 patch.
> ---
> drivers/of/of_mdio.c | 16 +++++++++-------
> 1 file changed, 9 insertions(+), 7 deletions(-)
> diff --git a/drivers/of/of_mdio.c b/drivers/of/of_mdio.c
> index 875b7b6..46d95fc 100644
> --- a/drivers/of/of_mdio.c
> +++ b/drivers/of/of_mdio.c
[...]
> @@ -54,12 +54,14 @@ static int of_mdiobus_register_phy(struct mii_bus *mdio, struct device_node *chi
> if (!phy || IS_ERR(phy))
> return 1;
>
> - if (mdio->irq) {
> - prev_irq = mdio->irq[addr];
> - mdio->irq[addr] =
> - irq_of_parse_and_map(child, 0);
> - if (!mdio->irq[addr])
> - mdio->irq[addr] = prev_irq;
> + rc = irq_of_parse_and_map(child, 0);
> + if (rc > 0) {
> + phy->irq = rc;
> + if (mdio->irq)
> + mdio->irq[addr] = rc;
> + } else {
> + if (mdio->irq)
You could write that as *else if* and save a line of code...
> + phy->irq = mdio->irq[addr];
> }
WBR, Sergei
^ permalink raw reply
* Re: [PATCH v4 1/5] clk: sunxi: Add support for PLL6 on the A31
From: Emilio López @ 2014-02-18 14:47 UTC (permalink / raw)
To: Maxime Ripard, Mark Brown, Mike Turquette
Cc: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kevin.z.m.zh-Re5JQEeQqe8AvxtiuMwx3w,
sunny-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf,
shuge-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf,
zhuzhenhua-0TFLnhJekD6UEPyfVivIlAC/G2K4zDHf
In-Reply-To: <1391605507-30981-2-git-send-email-maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
El 05/02/14 10:05, Maxime Ripard escribió:
> The A31 has a slightly different PLL6 clock. Add support for this new clock in
> our driver.
>
> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Taken via sunxi-clk-for-mike.
Thanks!
Emilio
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^ permalink raw reply
* Re: [PATCH] dt/bindings: update fsl-fec regarding compatible and clocks
From: Shawn Guo @ 2014-02-18 14:46 UTC (permalink / raw)
To: Gerhard Sittig
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Philippe De Muyter
In-Reply-To: <20140218134430.GC4524-kDjWylLy9wD0K7fsECOQyeGNnDKD8DIp@public.gmane.org>
On Tue, Feb 18, 2014 at 02:44:30PM +0100, Gerhard Sittig wrote:
> > > > @@ -1,9 +1,26 @@
> > > > * Freescale Fast Ethernet Controller (FEC)
> > > >
> > > > Required properties:
> > > > -- compatible : Should be "fsl,<soc>-fec"
> > > > +- compatible : Should contain one of the following:
> > > > + "fsl,imx25-fec"
> > > > + "fsl,imx27-fec"
> > > > + "fsl,imx28-fec"
> > > > + "fsl,imx6q-fec"
> > > > + "fsl,mvf600-fec"
> > >
> > > This appears to miss all the PowerPC based SoCs. See
> > > git grep 'fsl,.*-fec' arch/*/boot/dts
> >
> > Hmm, this is a binding for IMX FEC/ENET, and the driver is
> > drivers/net/ethernet/freescale/fec_main.c.
>
> The binding text says otherwise. It claims to apply for
> "fsl,<soc>-fec" compatibles.
I should really list the compatibles specifically when I was creating
the document at day one. But honestly, I did not intend to cover
PowerPC chips with this document.
>
> It's funny how the first line of the source you point to talks
> about being a FEC driver for MPC8xx. :) But that doesn't matter
> here, as it's just a comment in some code.
>
> > I think I've listed all the compatibles that the driver
> > supports.
>
> You got it backwards. The binding is not the after-the-fact
> documentation of a specific Linux driver. Instead the Linux
> driver is (supposed to be) an implementation of what the binding
> specifies.
Yes, theoretically. But practically, well ...
> And in this case, there are several drivers, each
> managing a subset of the compatibles space, each supposed to
> follow the spec. See
>
> git grep 'fsl,.*-fec' drivers/net/ethernet
>
The spec was created without considering those drivers other than
fec_main. For example, the 'phy-mode' is documented as a required
property in the spec. But I do not think that's the case for drivers
fec_mpc52xx and fs_enet-main.
> > > > - reg : Address and length of the register set for the device
> > > > - interrupts : Should contain fec interrupt
> > > > +- clocks: phandle to the clocks feeding the FEC controller and phy. The
> > > > + following two are required:
> > > > + - "ipg": the peripheral access clock
> > > > + - "ahb": the bus clock for MAC
> > > > + The following two are optional:
> > > > + - "ptp": the sampling clock for PTP (IEEE 1588). On SoC like i.MX6Q,
> > > > + the clock could come from either the internal clock control module
> > > > + or external oscillator via pad depending on board design.
> > > > + - "enet_out": the phy reference clock provided by SoC via pad, which
> > > > + is available on SoC like i.MX28.
> > > > +- clock-names: Must contain the clock names described just above
> > > > +
> > >
> > > Listing 'clocks' under the "required properties" all of a sudden
> > > invalidates existing device trees, if they don't carry the
> > > property which before the change was not required, not even
> > > documented.
> >
> > Since the day we move to device tree clock lookup, the driver fec_main
> > does not probe at all if the property is absent.
>
> That's an implementation detail. It's not what the spec says,
> and neither is what the spec is to blindly follow after the / a
> driver created the fact. Instead, a binding gets designed, and
> the software follows.
>
> In reality, the doc may be behind as developers are more
> concerned about the code. But still when you "update" the
> binding, don't break compatibility! Even if you'd adjust all
> drivers you can spot, it's still only Linux and not all device
> tree users.
So what's your suggestion? Add the properties as the optional?
Shawn
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^ permalink raw reply
* Re: [PATCH v4] gpio: Driver for SYSCON-based GPIOs
From: Alexander Shiyan @ 2014-02-18 14:46 UTC (permalink / raw)
To: Linus Walleij
Cc: Arnd Bergmann, Olof Johansson, Kevin Hilman,
linux-gpio@vger.kernel.org, Alexandre Courbot, Rob Herring,
Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
devicetree@vger.kernel.org
In-Reply-To: <CACRpkdaVn0iNFYKE3HXWxnb4iCJorF0HSVG4Uvz8Q18SiF5PUQ@mail.gmail.com>
On Thu, 30 Jan 2014 14:54:36 +0100
Linus Walleij <linus.walleij@linaro.org> wrote:
> On Mon, Jan 13, 2014 at 5:56 PM, Alexander Shiyan <shc_work@mail.ru> wrote:
>
> > SYSCON driver was designed for using memory areas (registers)
> > that are used in several subsystems. There are systems (CPUs)
> > which use bits in one register for various purposes and thus
> > should be handled by various kernel subsystems. This driver
> > allows you to use the individual SYSCON bits as GPIOs.
> > ARM CLPS711X SYSFLG1 input lines has been added as first user
> > of this driver.
> >
> > Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
>
> Oh the pain. I am so ambivalent of this patch as it obfuscates
> some stuff about the hardware that the driver should know,
> while at the same time being elegant in a way.
>
> What does the ARM SoC maintainers think about this approach?
>
> Arnd, Olof, Kevin: is this something you'd like to see deployed?
>
> Yours,
> Linus Walleij
Ping.
--
Alexander Shiyan <shc_work@mail.ru>
^ permalink raw reply
* Re: [PATCH v4 0/2] Introduce AEMIF driver for Davinci/Keystone archs
From: Santosh Shilimkar @ 2014-02-18 14:41 UTC (permalink / raw)
To: gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r
Cc: Ivan Khoronzhuk, rob-VoJi6FS/r0vR7s880joybQ,
linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
grygorii.strashko-l0cyMroinI0, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ,
nsekhar-l0cyMroinI0
In-Reply-To: <1391629574-18955-1-git-send-email-ivan.khoronzhuk-l0cyMroinI0@public.gmane.org>
Greg,
On Wednesday 05 February 2014 02:46 PM, Ivan Khoronzhuk wrote:
> These patches introduce Async External Memory Interface (EMIF16/AEMIF)
> controller driver for Davinci/Keystone archs.
>
> For more informations see documentation:
> Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
> OMAP-L138 - http://www.ti.com/lit/ug/spruh77a/spruh77a.pdf
> Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
>
Can you please have a look at the series ? It has been on the list for
sometime and all the outstanding comments are addressed so far. If
you are ok with it, I would like to get these queued up for 3.15
via your tree.
> Based on
> git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
> keystone/master
>
> v3..v4:
> rebased on latest of linux-keystone.git keystone/master
>
> v2..v3 (https://lkml.org/lkml/2013/12/11/148):
> - memory: ti-aemif: introduce AEMIF driver
> changed to work with multiple AEMIF controllers
> corrected "copyright" to "authors" in header
> changed compatible "ti,omap-L138-aemif" to "ti,da850-aeimf"
> used NULL in clk_get() instead of "aemif" name
> driver can be build as loadable module
> treat all child nodes as cs nodes, it makes code simpler
>
> - memory: ti-aemif: add bindings for AEMIF driver
> deleted direct link driver/memory/ti-aemif.c
> clarified description of controller ranges property
> changed compatible "ti,omap-L138-aemif" to "ti,da850-aeimf"
> added cs number information in commit log
> removed compatible property from cs node, it makes code simpler
>
> v1..v2 (https://lkml.org/lkml/2013/11/21/170):
> - memory: ti-aemif: introduce AEMIF driver
> - memory: ti-aemif: add bindings for AEMIF driver
> added ti.cs-chipselect property instead of representing chipselect
> number in cs node name.
>
> Ivan Khoronzhuk (2):
> memory: ti-aemif: introduce AEMIF driver
> memory: ti-aemif: add bindings for AEMIF driver
>
> .../bindings/memory-controllers/ti-aemif.txt | 210 ++++++++++
> drivers/memory/Kconfig | 11 +
> drivers/memory/Makefile | 1 +
> drivers/memory/ti-aemif.c | 429 +++++++++++++++++++++
> 4 files changed, 651 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-aemif.txt
> create mode 100644 drivers/memory/ti-aemif.c
>
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^ permalink raw reply
* Re: [PATCH V2 1/2] mmc: omap_hsmmc: Add support for quirky omap3 hsmmc controller
From: Balaji T K @ 2014-02-18 14:36 UTC (permalink / raw)
To: Nishanth Menon
Cc: devicetree, linux-doc, Tony Lindgren, linux-mmc, Chris Ball,
Felipe Balbi, linux-kernel, linux-omap, linux-arm-kernel
In-Reply-To: <1392356749-32091-2-git-send-email-nm@ti.com>
On Friday 14 February 2014 11:15 AM, Nishanth Menon wrote:
> When device is booted using devicetree, platforms impacted by Erratum
> 2.1.1.128 is not detected easily in the mmc driver. This erratum
> indicates that the module cannot do multi-block transfers. Platforms
> such as LDP which use OMAP3 ES revision prior to ES3.0 are impacted by
> this.
>
> Provide a new compatible property "ti,omap3-pre-es3-hsmmc" to allow
> driver to determine if driver needs to implement quirks associated
> with the specific module version (primarily because the IP revision
> information is not sufficient for the same).
>
> Signed-off-by: Nishanth Menon <nm@ti.com>
looks good to me
Acked-by: Balaji T K <balajitk@ti.com>
> ---
> Changes since v1:
> - new compatible flag as suggested by Tony which contains
> the relevant controller flag to work around the erratum
>
> V1: https://patchwork.kernel.org/patch/3514851/
>
> .../devicetree/bindings/mmc/ti-omap-hsmmc.txt | 1 +
> drivers/mmc/host/omap_hsmmc.c | 26 +++++++++++++++++---
> 2 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> index 8c8908a..ce80561 100644
> --- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
> @@ -10,6 +10,7 @@ Required properties:
> - compatible:
> Should be "ti,omap2-hsmmc", for OMAP2 controllers
> Should be "ti,omap3-hsmmc", for OMAP3 controllers
> + Should be "ti,omap3-pre-es3-hsmmc" for OMAP3 controllers pre ES3.0
> Should be "ti,omap4-hsmmc", for OMAP4 controllers
> - ti,hwmods: Must be "mmc<n>", n is controller instance starting 1
>
> diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
> index 575f9cc..390f421 100644
> --- a/drivers/mmc/host/omap_hsmmc.c
> +++ b/drivers/mmc/host/omap_hsmmc.c
> @@ -192,6 +192,11 @@ struct omap_hsmmc_host {
> struct omap_mmc_platform_data *pdata;
> };
>
> +struct omap_mmc_of_data {
> + u32 reg_offset;
> + u8 controller_flags;
> +};
> +
> static int omap_hsmmc_card_detect(struct device *dev, int slot)
> {
> struct omap_hsmmc_host *host = dev_get_drvdata(dev);
> @@ -1678,18 +1683,29 @@ static void omap_hsmmc_debugfs(struct mmc_host *mmc)
> #endif
>
> #ifdef CONFIG_OF
> -static u16 omap4_reg_offset = 0x100;
> +static const struct omap_mmc_of_data omap3_pre_es3_mmc_of_data = {
> + /* See 35xx errata 2.1.1.128 in SPRZ278F */
> + .controller_flags = OMAP_HSMMC_BROKEN_MULTIBLOCK_READ,
> +};
> +
> +static const struct omap_mmc_of_data omap4_mmc_of_data = {
> + .reg_offset = 0x100,
> +};
>
> static const struct of_device_id omap_mmc_of_match[] = {
> {
> .compatible = "ti,omap2-hsmmc",
> },
> {
> + .compatible = "ti,omap3-pre-es3-hsmmc",
> + .data = &omap3_pre_es3_mmc_of_data,
> + },
> + {
> .compatible = "ti,omap3-hsmmc",
> },
> {
> .compatible = "ti,omap4-hsmmc",
> - .data = &omap4_reg_offset,
> + .data = &omap4_mmc_of_data,
> },
> {},
> };
> @@ -1759,6 +1775,7 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
> dma_cap_mask_t mask;
> unsigned tx_req, rx_req;
> struct pinctrl *pinctrl;
> + const struct omap_mmc_of_data *data;
>
> match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev);
> if (match) {
> @@ -1768,8 +1785,9 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
> return PTR_ERR(pdata);
>
> if (match->data) {
> - const u16 *offsetp = match->data;
> - pdata->reg_offset = *offsetp;
> + data = match->data;
> + pdata->reg_offset = data->reg_offset;
> + pdata->controller_flags |= data->controller_flags;
> }
> }
>
>
^ permalink raw reply
* Re: devicetree repository separation/migration
From: Jason Cooper @ 2014-02-18 14:34 UTC (permalink / raw)
To: Grant Likely, Rob Herring, Ian Campbell, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, galak-sgV2jX0FEOL9JmXXK+q4OQ,
rob-VoJi6FS/r0vR7s880joybQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
devicetree-spec-u79uwXL29TY76Z2rM5mHXA,
devicetree-compiler-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20140217180544.GU7862-u4khhh1J0LxI1Ri9qeTfzeTW4wlIGRCZ@public.gmane.org>
On Mon, Feb 17, 2014 at 01:05:44PM -0500, Jason Cooper wrote:
> Interested individuals can look through the irc archives for
> #devicetree.
oops, My mistake. They are supposed to be at irclogs.linaro.org, but it
hasn't been set up yet. You'll just have to ask nicely for someone to
go through their scrollback buffer. :)
thx,
Jason.
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^ permalink raw reply
* Re: [PATCH v7 5/8] ARM: dts: sun7i: Add support for mmc
From: Maxime Ripard @ 2014-02-18 14:22 UTC (permalink / raw)
To: David Lanzendörfer
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140217100241.15040.24836.stgit-pgFh0Jf6HD9Xzn/AsuzBOg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 5842 bytes --]
On Mon, Feb 17, 2014 at 11:02:41AM +0100, David Lanzendörfer wrote:
> Signed-off-by: David Lanzendörfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> arch/arm/boot/dts/sun7i-a20-cubieboard2.dts | 8 +++
> arch/arm/boot/dts/sun7i-a20-cubietruck.dts | 8 +++
> arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts | 23 +++++++++
> arch/arm/boot/dts/sun7i-a20.dtsi | 61 +++++++++++++++++++++++
> 4 files changed, 100 insertions(+)
>
I'd prefer to have three patches here:
- One that add the controllers
- One that add the pin muxing options
- One that enable the controllers on the various boards.
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> index 5c51cb8..ae800b6 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubieboard2.dts
> @@ -34,6 +34,14 @@
> };
> };
>
> + mmc0: mmc@01c0f000 {
> + pinctrl-names = "default", "default";
> + pinctrl-0 = <&mmc0_pins_a>;
> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
This can be made a single pinctrl group, you don't need the pinctrl-1
stuff, it only complicates the node.
> + cd-gpios = <&pio 7 1 0>; /* PH1 */
> + status = "okay";
> + };
> +
> pinctrl@01c20800 {
> led_pins_cubieboard2: led_pins@0 {
> allwinner,pins = "PH20", "PH21";
> diff --git a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> index f9dcb61..370cef84 100644
> --- a/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-cubietruck.dts
> @@ -19,6 +19,14 @@
> compatible = "cubietech,cubietruck", "allwinner,sun7i-a20";
>
> soc@01c00000 {
> + mmc0: mmc@01c0f000 {
> + pinctrl-names = "default", "default";
> + pinctrl-0 = <&mmc0_pins_a>;
> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
> + cd-gpios = <&pio 7 1 0>; /* PH1 */
> + status = "okay";
> + };
> +
> pinctrl@01c20800 {
> led_pins_cubietruck: led_pins@0 {
> allwinner,pins = "PH7", "PH11", "PH20", "PH21";
> diff --git a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> index ead3013..685ec06 100644
> --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-micro.dts
> @@ -34,7 +34,30 @@
> };
> };
>
> + mmc0: mmc@01c0f000 {
> + pinctrl-names = "default", "default";
> + pinctrl-0 = <&mmc0_pins_a>;
> + pinctrl-1 = <&mmc0_cd_pin_reference_design>;
> + cd-gpios = <&pio 7 1 0>; /* PH1 */
> + status = "okay";
> + };
> +
> + mmc3: mmc@01c12000 {
> + pinctrl-names = "default", "default";
> + pinctrl-0 = <&mmc3_pins_a>;
> + pinctrl-1 = <&mmc3_cd_pin_olinuxinom>;
> + cd-gpios = <&pio 7 11 0>; /* PH11 */
> + status = "okay";
> + };
> +
> pinctrl@01c20800 {
> + mmc3_cd_pin_olinuxinom: mmc3_cd_pin@0 {
> + allwinner,pins = "PH11";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <0>;
> + allwinner,pull = <1>;
> + };
> +
> led_pins_olinuxino: led_pins@0 {
> allwinner,pins = "PH2";
> allwinner,function = "gpio_out";
> diff --git a/arch/arm/boot/dts/sun7i-a20.dtsi b/arch/arm/boot/dts/sun7i-a20.dtsi
> index 9ff0948..5b55414 100644
> --- a/arch/arm/boot/dts/sun7i-a20.dtsi
> +++ b/arch/arm/boot/dts/sun7i-a20.dtsi
> @@ -355,6 +355,46 @@
> #size-cells = <0>;
> };
>
> + mmc0: mmc@01c0f000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ahb_gates 8>, <&mmc0_clk>;
> + clock-names = "ahb", "mod";
> + interrupts = <0 32 4>;
> + bus-width = <4>;
This belongs to the board, the controller itself is able to handle
several bus width.
> + status = "disabled";
> + };
> +
> + mmc1: mmc@01c10000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ahb_gates 9>, <&mmc1_clk>;
> + clock-names = "ahb", "mod";
> + interrupts = <0 33 4>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + mmc2: mmc@01c11000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c11000 0x1000>;
> + clocks = <&ahb_gates 10>, <&mmc2_clk>;
> + clock-names = "ahb", "mod";
> + interrupts = <0 34 4>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> + mmc3: mmc@01c12000 {
> + compatible = "allwinner,sun5i-a13-mmc";
> + reg = <0x01c12000 0x1000>;
> + clocks = <&ahb_gates 11>, <&mmc3_clk>;
> + clock-names = "ahb", "mod";
> + interrupts = <0 35 4>;
> + bus-width = <4>;
> + status = "disabled";
> + };
> +
> pio: pinctrl@01c20800 {
> compatible = "allwinner,sun7i-a20-pinctrl";
> reg = <0x01c20800 0x400>;
> @@ -432,6 +472,27 @@
> allwinner,drive = <0>;
> allwinner,pull = <0>;
> };
> +
> + mmc0_pins_a: mmc0@0 {
> + allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
> + allwinner,function = "mmc0";
> + allwinner,drive = <3>;
> + allwinner,pull = <0>;
> + };
> +
> + mmc0_cd_pin_reference_design: mmc0_cd_pin@0 {
> + allwinner,pins = "PH1";
> + allwinner,function = "gpio_in";
> + allwinner,drive = <0>;
> + allwinner,pull = <1>;
> + };
> +
> + mmc3_pins_a: mmc3@0 {
> + allwinner,pins = "PI4","PI5","PI6","PI7","PI8","PI9";
> + allwinner,function = "mmc3";
> + allwinner,drive = <3>;
> + allwinner,pull = <0>;
> + };
> };
>
> timer@01c20c00 {
>
Looks good otherwise.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* [PATCH 3/3] ARM: dts: imx6sl: add board file for BQ Cervantes
From: Heiko Stübner @ 2014-02-18 14:17 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
grant.likely-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <10555869.uLtJmrqZh3@phil>
From: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
i.MX6SL based ebook-reader released in 2013.
Signed-off-by: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
---
arch/arm/boot/dts/imx6sl-bq-cervantes.dts | 133 ++++++++++++++++++++++++++++++
1 file changed, 133 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sl-bq-cervantes.dts
diff --git a/arch/arm/boot/dts/imx6sl-bq-cervantes.dts b/arch/arm/boot/dts/imx6sl-bq-cervantes.dts
new file mode 100644
index 0000000..c54f498
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sl-bq-cervantes.dts
@@ -0,0 +1,133 @@
+/*
+ * Copyright (C) 2014 MundoReader S.L.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include "imx6sl.dtsi"
+
+/ {
+ model = "BQ Cervantes";
+ compatible = "fsl,imx6sl";
+
+ memory {
+ reg = <0x80000000 0x20000000>;
+ };
+
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_usdhc2_vmmc: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "usdhc2_vmmc";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&gpio3 29 0>;
+ enable-active-high;
+ };
+ };
+
+ soc {
+ gpio-keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ autorepeat;
+
+ button@0 {
+ gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_POWER>;
+ label = "GPIO Key Power";
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+
+ button@1 {
+ gpios = <&gpio3 24 GPIO_ACTIVE_LOW>;
+ linux,code = <KEY_HOME>;
+ label = "GPIO Key Home";
+ linux,input-type = <1>;
+ gpio-key,wakeup = <1>;
+ debounce-interval = <100>;
+ };
+ };
+
+ gpio-leds {
+ compatible = "gpio-leds";
+
+ green {
+ gpios = <&gpio5 7 GPIO_ACTIVE_LOW>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+ imx6sl-bqcervantes {
+ pinctrl_zforce: zforcegrp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_DAT3__GPIO5_IO06 0xc000
+ MX6SL_PAD_SD1_DAT5__GPIO5_IO09 0x80000000
+ >;
+ };
+ };
+};
+
+&i2c1 {
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ status = "okay";
+
+ zforce@50 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_zforce>;
+
+ compatible = "neonode,zforce";
+ reg = <0x50>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <6 IRQ_TYPE_LEVEL_LOW>;
+
+ gpios = <&gpio5 6 0 /* INT */
+ &gpio5 9 0>; /* RST */
+
+ x-size = <758>;
+ y-size = <1024>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&usdhc2 {
+ vmmc-supply = <®_usdhc2_vmmc>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
+ cd-gpios = <&gpio5 2 0>;
+ status = "okay";
+};
+
+&usdhc3 {
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc3>;
+ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
+ broken-cd;
+ status = "okay";
+};
--
1.8.5.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: imx6sl: move pingroups back into soc dtsi
From: Heiko Stübner @ 2014-02-18 14:17 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
grant.likely-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <10555869.uLtJmrqZh3@phil>
From: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
Using the delete-unreferenced flag, the pingroups can be kept globally but won't
be unecessarily included in dts files not using them.
Signed-off-by: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
---
arch/arm/boot/dts/imx6sl-evk.dts | 181 --------------------------------------
arch/arm/boot/dts/imx6sl.dtsi | 185 +++++++++++++++++++++++++++++++++++++++
2 files changed, 185 insertions(+), 181 deletions(-)
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index 889422c..07876e0 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -267,192 +267,11 @@
>;
};
- pinctrl_audmux3: audmux3grp {
- fsl,pins = <
- MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
- MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
- MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
- MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
- >;
- };
-
- pinctrl_ecspi1: ecspi1grp {
- fsl,pins = <
- MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
- MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
- MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
- >;
- };
-
- pinctrl_fec: fecgrp {
- fsl,pins = <
- MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
- MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
- MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
- MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
- MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
- MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
- MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
- >;
- };
-
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
- MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
- >;
- };
-
-
- pinctrl_i2c2: i2c2grp {
- fsl,pins = <
- MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
- MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
- >;
- };
-
pinctrl_led: ledgrp {
fsl,pins = <
MX6SL_PAD_HSIC_STROBE__GPIO3_IO20 0x17059
>;
};
-
- pinctrl_kpp: kppgrp {
- fsl,pins = <
- MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
- MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
- MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
- MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
- MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
- MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
- >;
- };
-
- pinctrl_uart1: uart1grp {
- fsl,pins = <
- MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
- MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
- >;
- };
-
- pinctrl_usbotg1: usbotg1grp {
- fsl,pins = <
- MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
- >;
- };
-
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
- MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
- MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
- MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
- MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
- MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
- MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
- MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
- MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
- MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
- >;
- };
-
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
- MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
- MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
- MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
- MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
- MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
- >;
- };
-
- pinctrl_usdhc3: usdhc3grp {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
- >;
- };
-
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
- >;
- };
-
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
- fsl,pins = <
- MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
- MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
- MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
- MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
- MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
- MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
- >;
- };
};
};
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index 3cb4941..2d176f0 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -797,3 +797,188 @@
};
};
};
+
+
+&iomuxc {
+ imx6sl {
+ /delete-unreferenced/ pinctrl_audmux3: audmux3grp {
+ fsl,pins = <
+ MX6SL_PAD_AUD_RXD__AUD3_RXD 0x4130b0
+ MX6SL_PAD_AUD_TXC__AUD3_TXC 0x4130b0
+ MX6SL_PAD_AUD_TXD__AUD3_TXD 0x4110b0
+ MX6SL_PAD_AUD_TXFS__AUD3_TXFS 0x4130b0
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_ecspi1: ecspi1grp {
+ fsl,pins = <
+ MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
+ MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
+ MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_fec: fecgrp {
+ fsl,pins = <
+ MX6SL_PAD_FEC_MDC__FEC_MDC 0x1b0b0
+ MX6SL_PAD_FEC_MDIO__FEC_MDIO 0x1b0b0
+ MX6SL_PAD_FEC_CRS_DV__FEC_RX_DV 0x1b0b0
+ MX6SL_PAD_FEC_RXD0__FEC_RX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_RXD1__FEC_RX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_TX_EN__FEC_TX_EN 0x1b0b0
+ MX6SL_PAD_FEC_TXD0__FEC_TX_DATA0 0x1b0b0
+ MX6SL_PAD_FEC_TXD1__FEC_TX_DATA1 0x1b0b0
+ MX6SL_PAD_FEC_REF_CLK__FEC_REF_OUT 0x4001b0a8
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C1_SCL__I2C1_SCL 0x4001b8b1
+ MX6SL_PAD_I2C1_SDA__I2C1_SDA 0x4001b8b1
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SL_PAD_I2C2_SCL__I2C2_SCL 0x4001b8b1
+ MX6SL_PAD_I2C2_SDA__I2C2_SDA 0x4001b8b1
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_kpp: kppgrp {
+ fsl,pins = <
+ MX6SL_PAD_KEY_ROW0__KEY_ROW0 0x1b010
+ MX6SL_PAD_KEY_ROW1__KEY_ROW1 0x1b010
+ MX6SL_PAD_KEY_ROW2__KEY_ROW2 0x1b0b0
+ MX6SL_PAD_KEY_COL0__KEY_COL0 0x110b0
+ MX6SL_PAD_KEY_COL1__KEY_COL1 0x110b0
+ MX6SL_PAD_KEY_COL2__KEY_COL2 0x110b0
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x1b0b1
+ MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x1b0b1
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usbotg1: usbotg1grp {
+ fsl,pins = <
+ MX6SL_PAD_EPDC_PWRCOM__USB_OTG1_ID 0x17059
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x17059
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x10059
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x17059
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x17059
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x17059
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x17059
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x17059
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x17059
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x17059
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x17059
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170b9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100b9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170b9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170b9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170b9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170b9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170b9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170b9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170b9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170b9
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD1_CMD__SD1_CMD 0x170f9
+ MX6SL_PAD_SD1_CLK__SD1_CLK 0x100f9
+ MX6SL_PAD_SD1_DAT0__SD1_DATA0 0x170f9
+ MX6SL_PAD_SD1_DAT1__SD1_DATA1 0x170f9
+ MX6SL_PAD_SD1_DAT2__SD1_DATA2 0x170f9
+ MX6SL_PAD_SD1_DAT3__SD1_DATA3 0x170f9
+ MX6SL_PAD_SD1_DAT4__SD1_DATA4 0x170f9
+ MX6SL_PAD_SD1_DAT5__SD1_DATA5 0x170f9
+ MX6SL_PAD_SD1_DAT6__SD1_DATA6 0x170f9
+ MX6SL_PAD_SD1_DAT7__SD1_DATA7 0x170f9
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x17059
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x10059
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x17059
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x17059
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x17059
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x17059
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170b9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100b9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170b9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170b9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170b9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170b9
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD2_CMD__SD2_CMD 0x170f9
+ MX6SL_PAD_SD2_CLK__SD2_CLK 0x100f9
+ MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x170f9
+ MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x170f9
+ MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x170f9
+ MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x170f9
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc3: usdhc3grp {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x17059
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x10059
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x17059
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x17059
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x17059
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x17059
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170b9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100b9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
+ >;
+ };
+
+ /delete-unreferenced/ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ fsl,pins = <
+ MX6SL_PAD_SD3_CMD__SD3_CMD 0x170f9
+ MX6SL_PAD_SD3_CLK__SD3_CLK 0x100f9
+ MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
+ MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
+ MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
+ MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
+ >;
+ };
+ };
+};
--
1.8.5.3
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* Re: [PATCH v7 3/8] ARM: sunxi: clk: export clk_sunxi_mmc_phase_control
From: Maxime Ripard @ 2014-02-18 14:17 UTC (permalink / raw)
To: David Lanzendörfer
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Mike Turquette, Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140217100228.15040.32391.stgit-pgFh0Jf6HD9Xzn/AsuzBOg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 425 bytes --]
On Mon, Feb 17, 2014 at 11:02:28AM +0100, David Lanzendörfer wrote:
> From: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
Again, your SoB is missing, and that can be squashed with the previous
patch.
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* [PATCH 1/3] dtc: add ability to make nodes conditional on them being referenced
From: Heiko Stübner @ 2014-02-18 14:16 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
grant.likely-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <10555869.uLtJmrqZh3@phil>
From: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
On i.MX, which carries a lot of pin-groups of which most are unused on
individual boards, they noticed that this plethora of nodes also results
in the runtime-lookup-performance also degrading [0].
A i.MX-specific solution defining the pingroups in the board files but
using macros to reference the pingroup-data was not well received
This patch is trying to solve this issue in a more general way, by
adding the ability to mark nodes as needing to be referenced somewhere
in the tree.
To mark a node a needing to be referenced it must be prefixed with
/delete-unreferenced/. This makes dtc check the nodes reference-status
when creating the flattened tree, dropping it if unreferenced.
For example, the i.MX6SL pingroup
/delete-unreferenced/ pinctrl_ecspi1_1: ecspi1grp-1 {
fsl,pins = <
MX6SL_PAD_ECSPI1_MISO__ECSPI1_MISO 0x100b1
MX6SL_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x100b1
MX6SL_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x100b1
>;
};
would only be included in the dtb if it got referenced somewhere
as pingroup via
node {
pinctrl-0 <&pinctrl_ecscpi1_1>;
};
[0] http://thread.gmane.org/gmane.linux.ports.arm.kernel/275912/
Signed-off-by: Heiko Stuebner <heiko.stuebner-HCpLIkUQxWGakBO8gow8eQ@public.gmane.org>
---
scripts/dtc/checks.c | 2 ++
scripts/dtc/dtc-lexer.l | 7 +++++++
scripts/dtc/dtc-parser.y | 5 +++++
scripts/dtc/dtc.h | 4 ++++
scripts/dtc/flattree.c | 3 +++
scripts/dtc/livetree.c | 14 ++++++++++++++
6 files changed, 35 insertions(+)
diff --git a/scripts/dtc/checks.c b/scripts/dtc/checks.c
index ee96a25..747ada8 100644
--- a/scripts/dtc/checks.c
+++ b/scripts/dtc/checks.c
@@ -472,6 +472,8 @@ static void fixup_phandle_references(struct check *c, struct node *dt,
phandle = get_node_phandle(dt, refnode);
*((cell_t *)(prop->val.val + m->offset)) = cpu_to_fdt32(phandle);
+
+ reference_node(refnode);
}
}
ERROR(phandle_references, NULL, NULL, fixup_phandle_references, NULL,
diff --git a/scripts/dtc/dtc-lexer.l b/scripts/dtc/dtc-lexer.l
index 3b41bfc..3b18e97 100644
--- a/scripts/dtc/dtc-lexer.l
+++ b/scripts/dtc/dtc-lexer.l
@@ -138,6 +138,13 @@ static int pop_input_file(void);
return DT_DEL_NODE;
}
+<*>"/delete-unreferenced/" {
+ DPRINT("Keyword: /delete-unreferenced/\n");
+ DPRINT("<PROPNODENAME>\n");
+ BEGIN(PROPNODENAME);
+ return DT_DEL_UNREFERENCED;
+ }
+
<*>{LABEL}: {
DPRINT("Label: %s\n", yytext);
yylval.labelref = xstrdup(yytext);
diff --git a/scripts/dtc/dtc-parser.y b/scripts/dtc/dtc-parser.y
index f412460..ae9108b 100644
--- a/scripts/dtc/dtc-parser.y
+++ b/scripts/dtc/dtc-parser.y
@@ -64,6 +64,7 @@ static unsigned char eval_char_literal(const char *s);
%token DT_BITS
%token DT_DEL_PROP
%token DT_DEL_NODE
+%token DT_DEL_UNREFERENCED
%token <propnodename> DT_PROPNODENAME
%token <literal> DT_LITERAL
%token <literal> DT_CHAR_LITERAL
@@ -461,6 +462,10 @@ subnode:
{
$$ = name_node(build_node_delete(), $2);
}
+ | DT_DEL_UNREFERENCED subnode
+ {
+ $$ = check_node_referenced($2);
+ }
| DT_LABEL subnode
{
add_label(&$2->labels, $1);
diff --git a/scripts/dtc/dtc.h b/scripts/dtc/dtc.h
index 264a20c..289c62b 100644
--- a/scripts/dtc/dtc.h
+++ b/scripts/dtc/dtc.h
@@ -158,6 +158,8 @@ struct node {
int addr_cells, size_cells;
struct label *labels;
+
+ int needs_reference, is_referenced;
};
#define for_each_label_withdel(l0, l) \
@@ -192,6 +194,8 @@ struct property *reverse_properties(struct property *first);
struct node *build_node(struct property *proplist, struct node *children);
struct node *build_node_delete(void);
struct node *name_node(struct node *node, char *name);
+struct node *check_node_referenced(struct node *node);
+struct node *reference_node(struct node *node);
struct node *chain_node(struct node *first, struct node *list);
struct node *merge_nodes(struct node *old_node, struct node *new_node);
diff --git a/scripts/dtc/flattree.c b/scripts/dtc/flattree.c
index 665dad7..a327592 100644
--- a/scripts/dtc/flattree.c
+++ b/scripts/dtc/flattree.c
@@ -266,6 +266,9 @@ static void flatten_tree(struct node *tree, struct emitter *emit,
if (tree->deleted)
return;
+ if (tree->needs_reference && !tree->is_referenced)
+ return;
+
emit->beginnode(etarget, tree->labels);
if (vi->flags & FTF_FULLPATH)
diff --git a/scripts/dtc/livetree.c b/scripts/dtc/livetree.c
index b61465f..98bb33d 100644
--- a/scripts/dtc/livetree.c
+++ b/scripts/dtc/livetree.c
@@ -134,6 +134,20 @@ struct node *name_node(struct node *node, char *name)
return node;
}
+struct node *check_node_referenced(struct node *node)
+{
+ node->needs_reference = 1;
+
+ return node;
+}
+
+struct node *reference_node(struct node *node)
+{
+ node->is_referenced = 1;
+
+ return node;
+}
+
struct node *merge_nodes(struct node *old_node, struct node *new_node)
{
struct property *new_prop, *old_prop;
--
1.8.5.3
--
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^ permalink raw reply related
* [PATCH 0/3] dtc handling unreferenced nodes and an imx board dts
From: Heiko Stübner @ 2014-02-18 14:15 UTC (permalink / raw)
To: Shawn Guo
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
grant.likely-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
After showcasing my dtc change as RFC before, this series shows essentially
where I want to go with the whole change - adding support for our ereaders
without duplicating the generic pinconfig nodes :-) . And also provides with
the dt change a user for the dtc flag addition.
That being said, the dtc change might need a bit more review and I also don't
know if it should go through the scripts/dtc variant like this or some
upstream and how the *_shipped files should be handled.
The patchset is done against linux-next from today, which includes both the
pingroups moved to the individual board files and the bindings for the zforce
touchscreen.
Heiko Stuebner (3):
dtc: add ability to make nodes conditional on them being referenced
ARM: dts: imx6sl: move pingroups back into soc dtsi
ARM: dts: imx6sl: add board file for BQ Cervantes
arch/arm/boot/dts/imx6sl-bq-cervantes.dts | 133 +++++++++++++++++++++
arch/arm/boot/dts/imx6sl-evk.dts | 181 -----------------------------
arch/arm/boot/dts/imx6sl.dtsi | 185 ++++++++++++++++++++++++++++++
scripts/dtc/checks.c | 2 +
scripts/dtc/dtc-lexer.l | 7 ++
scripts/dtc/dtc-parser.y | 5 +
scripts/dtc/dtc.h | 4 +
scripts/dtc/flattree.c | 3 +
scripts/dtc/livetree.c | 14 +++
9 files changed, 353 insertions(+), 181 deletions(-)
create mode 100644 arch/arm/boot/dts/imx6sl-bq-cervantes.dts
--
1.8.5.3
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^ permalink raw reply
* Re: [PATCH v7 2/8] clk: sunxi: Implement MMC phase control
From: Maxime Ripard @ 2014-02-18 14:15 UTC (permalink / raw)
To: Mike Turquette, David Lanzendörfer
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, Ulf Hansson, Laurent Pinchart,
Simon Baatz, Hans de Goede, Emilio López,
linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140217100221.15040.47203.stgit-pgFh0Jf6HD9Xzn/AsuzBOg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1498 bytes --]
Hi,
On Mon, Feb 17, 2014 at 11:02:21AM +0100, David Lanzendörfer wrote:
> From: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
>
> Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
You're missing your Signed-off-by here too. Remember, for every patch
you send, your Signed-off-by must be there, regardless wether you're
the author or not.
A commit log would be very much welcome too.
Now, down to the patch itself, I remember Mike saying that he would
prefer adding a function in the framework instead of hardcoding
it. Mike, what's your feeling on this? Would merging this seem
reasonnable to you as is, or do you want to take this to the
framework?
> ---
> drivers/clk/sunxi/clk-sunxi.c | 35 +++++++++++++++++++++++++++++++++++
> 1 file changed, 35 insertions(+)
>
> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
> index abb6c5a..33b9977 100644
> --- a/drivers/clk/sunxi/clk-sunxi.c
> +++ b/drivers/clk/sunxi/clk-sunxi.c
> @@ -377,6 +377,41 @@ static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
>
>
> /**
> + * clk_sunxi_mmc_phase_control() - configures MMC clock phase control
> + */
If you don't go the framework road, some documentation on what are the
arguments it takes and what it's supposed to return would be great.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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