* [PATCH v2 3/4] ARM: dts: vf610-twr: Enable SGTL5000 codec.
From: Xiubo Li @ 2014-02-19 7:42 UTC (permalink / raw)
To: linux-arm-kernel, shawn.guo
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, linux,
devicetree, linux-kernel, Xiubo Li
In-Reply-To: <1392795751-13351-1-git-send-email-Li.Xiubo@freescale.com>
This patch adds and enables SGTL5000 codec support.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/vf610-twr.dts | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index bcee3bb..0f4bff5 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -34,6 +34,20 @@
};
};
+ regulators {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg_3p3v: regulator@0 {
+ compatible = "regulator-fixed";
+ reg = <0>;
+ regulator-name = "3P3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+ };
};
&dspi0 {
@@ -72,6 +86,14 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
+
+ codec: sgtl5000@0a {
+ compatible = "fsl,sgtl5000";
+ reg = <0x0a>;
+ VDDA-supply = <®_3p3v>;
+ VDDIO-supply = <®_3p3v>;
+ clocks = <&clks VF610_CLK_SAI2>;
+ };
};
&iomuxc {
--
1.8.4
^ permalink raw reply related
* [PATCH v2 4/4] ARM: dts: vf610-twr: Add simple-card support.
From: Xiubo Li @ 2014-02-19 7:42 UTC (permalink / raw)
To: linux-arm-kernel, shawn.guo
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak, linux,
devicetree, linux-kernel, Xiubo Li
In-Reply-To: <1392795751-13351-1-git-send-email-Li.Xiubo@freescale.com>
This patch adds and enables simple-card support in DT node.
Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Cc: Shawn Guo <shawn.guo@linaro.org>
---
arch/arm/boot/dts/vf610-twr.dts | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/boot/dts/vf610-twr.dts b/arch/arm/boot/dts/vf610-twr.dts
index 0f4bff5..a553aa2 100644
--- a/arch/arm/boot/dts/vf610-twr.dts
+++ b/arch/arm/boot/dts/vf610-twr.dts
@@ -48,6 +48,35 @@
regulator-always-on;
};
};
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,widgets =
+ "Microphone", "Microphone Jack",
+ "Headphone", "Headphone Jack",
+ "Speaker", "Speaker Ext",
+ "Line", "Line In Jack";
+ simple-audio-card,routing =
+ "MIC_IN", "Microphone Jack",
+ "Microphone Jack", "Mic Bias",
+ "LINE_IN", "Line In Jack",
+ "Headphone Jack", "HP_OUT",
+ "Speaker Ext", "LINE_OUT";
+
+ simple-audio-card,cpu {
+ sound-dai = <&sai2>;
+ master-clkdir-out;
+ frame-master;
+ bitclock-master;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&codec>;
+ frame-master;
+ bitclock-master;
+ };
+ };
};
&dspi0 {
@@ -88,6 +117,7 @@
status = "okay";
codec: sgtl5000@0a {
+ #sound-dai-cells = <0>;
compatible = "fsl,sgtl5000";
reg = <0x0a>;
VDDA-supply = <®_3p3v>;
@@ -165,6 +195,7 @@
};
&sai2 {
+ #sound-dai-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai2>;
status = "okay";
--
1.8.4
^ permalink raw reply related
* [PATCH 1/2] ARM: dts: add device tree source for imx6sx SoC
From: Anson Huang @ 2014-02-19 7:47 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
Add device tree support for i.MX6SoloX SOC.
Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/imx6sx.dtsi | 524 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx.dtsi
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
new file mode 100644
index 0000000..6703b25
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2011, 2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx6sx-clock.h>
+#include "imx6sx-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <0 92 0x04>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 94 0x04>;
+ };
+
+ aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <0 26 0x04>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spba@0203c000 {
+ reg = <0x0203c000 0x4000>;
+ };
+ };
+
+ aipstz@0207c000 {
+ reg = <0x0207c000 0x4000>;
+ };
+
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6sx-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <0 55 0x04>;
+ clocks = <&clks IMX6SX_CLK_GPT_BUS>, <&clks IMX6SX_CLK_GPT_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <0 80 0x04>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6sx-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <0 87 0x04 0 88 0x04>;
+ #clock-cells = <1>;
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+ };
+
+ snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x020cc000 0x4000>;
+
+ snvs-rtc-lp@34 {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ reg = <0x34 0x58>;
+ interrupts = <0 19 0x04 0 20 0x04>;
+ };
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6q-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <0 91 0x04 0 96 0x04>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupts = <0 89 0x04>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6sx-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <0 2 0x04>;
+ clocks = <&clks IMX6SX_CLK_SDMA>, <&clks IMX6SX_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sx.bin";
+ };
+ };
+
+ aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ aipstz@0217c000 {
+ reg = <0x0217c000 0x4000>;
+ };
+
+ fec1: ethernet@02188000 {
+ compatible = "fsl,imx6sx-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <0 118 0x04 0 119 0x04>;
+ clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <0 24 0x04>;
+ clocks = <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x0219c000 0x4000>;
+ interrupts = <0 25 0x04>;
+ clocks = <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <0 36 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <0 37 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <0 38 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp@021ac000 {
+ compatible = "fsl,imx6sx-romcp", "syscon";
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc0: mmdc@021b0000 {
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ fec2: ethernet@021b4000 {
+ compatible = "fsl,imx6sx-fec";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <0 102 0x04 0 103 0x04>;
+ clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET2_REF_125M>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ status = "disabled";
+ };
+
+ tzasc@021d0000 {
+ reg = <0x021d0000 0x4000>;
+ interrupts = <0 108 0x04>;
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <0 27 0x04>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <0 35 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C4>;
+ status = "disabled";
+ };
+ };
+
+ aips-bus@02200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02200000 0x100000>;
+ ranges;
+
+ spba-bus@02200000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02240000 0x40000>;
+ ranges;
+
+ spba@0223c000 {
+ reg = <0x0223c000 0x4000>;
+ };
+ };
+
+ aipstz@0227c000 {
+ reg = <0x0227c000 0x4000>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+
+ enet1 {
+ pinctrl_enet1_1: enet1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
+ >;
+ };
+ };
+
+ enet2 {
+ pinctrl_enet2_1: enet2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b0
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b0
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b0
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b0
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
+ MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c3 {
+ pinctrl_i2c3_1: i2c3grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_2: i2c3grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c4 {
+ pinctrl_i2c4_1: i2c4grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
+ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
+ MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2_2: uart2grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
+ MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
+
+ };
+
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
+ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
+ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
+ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
+ >;
+ };
+ };
+};
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH 2/2] ARM: dts: imx6sx: add initial imx6sx sdb support
From: Anson Huang @ 2014-02-19 7:47 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1392796036-19094-1-git-send-email-b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Add initial imx6sx sdb board support with uart and usdhc enabled.
Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/imx6sx-sdb.dts | 41 ++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx-sdb.dts
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
new file mode 100644
index 0000000..3db4750
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+ model = "Freescale i.MX6 SoloX SDB Board";
+ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_1>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH 1/2] ARM: dts: add device tree source for imx6sx SoC
From: Anson Huang @ 2014-02-19 7:53 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add device tree support for i.MX6SoloX SOC.
Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/imx6sx.dtsi | 524 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 524 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx.dtsi
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
new file mode 100644
index 0000000..6703b25
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -0,0 +1,524 @@
+/*
+ * Copyright 2011, 2014 Freescale Semiconductor, Inc.
+ * Copyright 2011 Linaro Ltd.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <dt-bindings/clock/imx6sx-clock.h>
+#include "imx6sx-pinfunc.h"
+#include "skeleton.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart1;
+ serial1 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a9";
+ device_type = "cpu";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ };
+ };
+
+ intc: interrupt-controller@00a01000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-controller;
+ reg = <0x00a01000 0x1000>,
+ <0x00a00100 0x100>;
+ };
+
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ckil {
+ compatible = "fsl,imx-ckil", "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ osc {
+ compatible = "fsl,imx-osc", "fixed-clock";
+ clock-frequency = <24000000>;
+ };
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&intc>;
+ ranges;
+
+ L2: l2-cache@00a02000 {
+ compatible = "arm,pl310-cache";
+ reg = <0x00a02000 0x1000>;
+ interrupts = <0 92 0x04>;
+ cache-unified;
+ cache-level = <2>;
+ arm,tag-latency = <4 2 3>;
+ arm,data-latency = <4 2 3>;
+ };
+
+ pmu {
+ compatible = "arm,cortex-a9-pmu";
+ interrupts = <0 94 0x04>;
+ };
+
+ aips-bus@02000000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x100000>;
+ ranges;
+
+ spba-bus@02000000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02000000 0x40000>;
+ ranges;
+
+ uart1: serial@02020000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x02020000 0x4000>;
+ interrupts = <0 26 0x04>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ spba@0203c000 {
+ reg = <0x0203c000 0x4000>;
+ };
+ };
+
+ aipstz@0207c000 {
+ reg = <0x0207c000 0x4000>;
+ };
+
+ gpt: gpt@02098000 {
+ compatible = "fsl,imx6sx-gpt";
+ reg = <0x02098000 0x4000>;
+ interrupts = <0 55 0x04>;
+ clocks = <&clks IMX6SX_CLK_GPT_BUS>, <&clks IMX6SX_CLK_GPT_SERIAL>;
+ clock-names = "ipg", "per";
+ };
+
+ wdog1: wdog@020bc000 {
+ compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
+ reg = <0x020bc000 0x4000>;
+ interrupts = <0 80 0x04>;
+ clocks = <&clks IMX6SX_CLK_DUMMY>;
+ };
+
+ clks: ccm@020c4000 {
+ compatible = "fsl,imx6sx-ccm";
+ reg = <0x020c4000 0x4000>;
+ interrupts = <0 87 0x04 0 88 0x04>;
+ #clock-cells = <1>;
+ };
+
+ anatop: anatop@020c8000 {
+ compatible = "fsl,imx6sx-anatop", "fsl,imx6q-anatop",
+ "syscon", "simple-bus";
+ reg = <0x020c8000 0x1000>;
+ interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
+ };
+
+ snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x020cc000 0x4000>;
+
+ snvs-rtc-lp@34 {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ reg = <0x34 0x58>;
+ interrupts = <0 19 0x04 0 20 0x04>;
+ };
+ };
+
+ src: src@020d8000 {
+ compatible = "fsl,imx6q-src", "fsl,imx51-src";
+ reg = <0x020d8000 0x4000>;
+ interrupts = <0 91 0x04 0 96 0x04>;
+ #reset-cells = <1>;
+ };
+
+ gpc: gpc@020dc000 {
+ compatible = "fsl,imx6q-gpc";
+ reg = <0x020dc000 0x4000>;
+ interrupts = <0 89 0x04>;
+ };
+
+ iomuxc: iomuxc@020e0000 {
+ compatible = "fsl,imx6sx-iomuxc";
+ reg = <0x020e0000 0x4000>;
+ };
+
+ gpr: iomuxc-gpr@020e4000 {
+ compatible = "fsl,imx6sx-iomuxc-gpr", "syscon";
+ reg = <0x020e4000 0x4000>;
+ };
+
+ sdma: sdma@020ec000 {
+ compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
+ reg = <0x020ec000 0x4000>;
+ interrupts = <0 2 0x04>;
+ clocks = <&clks IMX6SX_CLK_SDMA>, <&clks IMX6SX_CLK_SDMA>;
+ clock-names = "ipg", "ahb";
+ #dma-cells = <3>;
+ fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6sx.bin";
+ };
+ };
+
+ aips-bus@02100000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02100000 0x100000>;
+ ranges;
+
+ aipstz@0217c000 {
+ reg = <0x0217c000 0x4000>;
+ };
+
+ fec1: ethernet@02188000 {
+ compatible = "fsl,imx6sx-fec";
+ reg = <0x02188000 0x4000>;
+ interrupts = <0 118 0x04 0 119 0x04>;
+ clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET_REF>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ status = "disabled";
+ };
+
+ usdhc3: usdhc@02198000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x02198000 0x4000>;
+ interrupts = <0 24 0x04>;
+ clocks = <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>, <&clks IMX6SX_CLK_USDHC3>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ usdhc4: usdhc@0219c000 {
+ compatible = "fsl,imx6sx-usdhc", "fsl,imx6sl-usdhc";
+ reg = <0x0219c000 0x4000>;
+ interrupts = <0 25 0x04>;
+ clocks = <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>, <&clks IMX6SX_CLK_USDHC4>;
+ clock-names = "ipg", "ahb", "per";
+ bus-width = <4>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@021a0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a0000 0x4000>;
+ interrupts = <0 36 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C1>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@021a4000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a4000 0x4000>;
+ interrupts = <0 37 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C2>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@021a8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021a8000 0x4000>;
+ interrupts = <0 38 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C3>;
+ status = "disabled";
+ };
+
+ romcp@021ac000 {
+ compatible = "fsl,imx6sx-romcp", "syscon";
+ reg = <0x021ac000 0x4000>;
+ };
+
+ mmdc0: mmdc@021b0000 {
+ compatible = "fsl,imx6q-mmdc";
+ reg = <0x021b0000 0x4000>;
+ };
+
+ fec2: ethernet@021b4000 {
+ compatible = "fsl,imx6sx-fec";
+ reg = <0x021b4000 0x4000>;
+ interrupts = <0 102 0x04 0 103 0x04>;
+ clocks = <&clks IMX6SX_CLK_ENET>, <&clks IMX6SX_CLK_ENET_AHB>,
+ <&clks IMX6SX_CLK_ENET_PTP>, <&clks IMX6SX_CLK_ENET2_REF_125M>;
+ clock-names = "ipg", "ahb", "ptp", "enet_clk_ref";
+ status = "disabled";
+ };
+
+ tzasc@021d0000 {
+ reg = <0x021d0000 0x4000>;
+ interrupts = <0 108 0x04>;
+ };
+
+ uart2: serial@021e8000 {
+ compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
+ reg = <0x021e8000 0x4000>;
+ interrupts = <0 27 0x04>;
+ clocks = <&clks IMX6SX_CLK_UART_IPG>, <&clks IMX6SX_CLK_UART_SERIAL>;
+ clock-names = "ipg", "per";
+ dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
+ dma-names = "rx", "tx";
+ status = "disabled";
+ };
+
+ i2c4: i2c@021f8000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6sx-i2c", "fsl,imx21-i2c";
+ reg = <0x021f8000 0x4000>;
+ interrupts = <0 35 0x04>;
+ clocks = <&clks IMX6SX_CLK_I2C4>;
+ status = "disabled";
+ };
+ };
+
+ aips-bus@02200000 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02200000 0x100000>;
+ ranges;
+
+ spba-bus@02200000 {
+ compatible = "fsl,spba-bus", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x02240000 0x40000>;
+ ranges;
+
+ spba@0223c000 {
+ reg = <0x0223c000 0x4000>;
+ };
+ };
+
+ aipstz@0227c000 {
+ reg = <0x0227c000 0x4000>;
+ };
+ };
+ };
+};
+
+&iomuxc {
+
+ enet1 {
+ pinctrl_enet1_1: enet1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
+ >;
+ };
+ };
+
+ enet2 {
+ pinctrl_enet2_1: enet2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b1
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b0
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b0
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b0
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b0
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
+ >;
+ };
+ };
+
+ i2c1 {
+ pinctrl_i2c1_1: i2c1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c1_2: i2c1grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x4001b8b1
+ MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c2 {
+ pinctrl_i2c2_1: i2c2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c3 {
+ pinctrl_i2c3_1: i2c3grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+
+ pinctrl_i2c3_2: i2c3grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ i2c4 {
+ pinctrl_i2c4_1: i2c4grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
+ MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
+ >;
+ };
+ };
+
+ uart1 {
+ pinctrl_uart1_1: uart1grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart1_2: uart1grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_ENET2_COL__UART1_RX 0x1b0b1
+ MX6SX_PAD_ENET2_CRS__UART1_TX 0x1b0b1
+ >;
+ };
+ };
+
+ uart2 {
+ pinctrl_uart2_1: uart2grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO07__UART2_RX 0x1b0b1
+ MX6SX_PAD_GPIO1_IO06__UART2_TX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2_2: uart2grp-2 {
+ fsl,pins = <
+ MX6SX_PAD_SD1_DATA0__UART2_RX 0x1b0b1
+ MX6SX_PAD_SD1_DATA1__UART2_TX 0x1b0b1
+ >;
+ };
+ };
+
+ usdhc3 {
+ pinctrl_usdhc3_1: usdhc3grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc3_1_100mhz: usdhc3grp-1-100mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
+ >;
+ };
+
+ pinctrl_usdhc3_1_200mhz: usdhc3grp-1-200mhz {
+ fsl,pins = <
+ MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
+ MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
+ MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
+ MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
+ MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
+ MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
+ MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
+ MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
+ MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
+ MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
+ >;
+ };
+
+ };
+
+ usdhc4 {
+ pinctrl_usdhc4_1: usdhc4grp-1 {
+ fsl,pins = <
+ MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
+ MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
+ MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
+ MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
+ MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
+ MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
+ MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x17059
+ MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x17059
+ MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x17059
+ MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x17059
+ >;
+ };
+ };
+};
--
1.7.9.5
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^ permalink raw reply related
* [PATCH 2/2] ARM: dts: imx6sx: add initial imx6sx sdb support
From: Anson Huang @ 2014-02-19 7:53 UTC (permalink / raw)
To: shawn.guo-QSEj5FYQhm4dnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1392796432-19127-1-git-send-email-b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Add initial imx6sx sdb board support with uart and usdhc enabled.
Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
---
arch/arm/boot/dts/imx6sx-sdb.dts | 41 ++++++++++++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6sx-sdb.dts
diff --git a/arch/arm/boot/dts/imx6sx-sdb.dts b/arch/arm/boot/dts/imx6sx-sdb.dts
new file mode 100644
index 0000000..3db4750
--- /dev/null
+++ b/arch/arm/boot/dts/imx6sx-sdb.dts
@@ -0,0 +1,41 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/dts-v1/;
+
+#include "imx6sx.dtsi"
+
+/ {
+ model = "Freescale i.MX6 SoloX SDB Board";
+ compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
+
+ memory {
+ reg = <0x80000000 0x40000000>;
+ };
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1_1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2_1>;
+ status = "okay";
+};
+
+&usdhc4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc4_1>;
+ bus-width = <8>;
+ non-removable;
+ no-1-8-v;
+ status = "okay";
+};
--
1.7.9.5
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^ permalink raw reply related
* Re: [PATCH v2 2/4] of: reimplement the matching method for __of_match_node()
From: Kevin Hao @ 2014-02-19 7:58 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: Rob Herring, Sebastian Hesselbarth, Grant Likely
In-Reply-To: <1392790862-18025-1-git-send-email-haokexin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 479 bytes --]
On Wed, Feb 19, 2014 at 02:21:02PM +0800, Kevin Hao wrote:
> + /*
> + * Matching compatible is better than matching type and name,
> + * and the specific compatible is better than the general.
> + */
> + if (matches->compatible[0] &&
> + __of_device_is_compatible_score(node,
> + matches->compatible, &score))
> + score = INT_MAX - 4 * score;
It seems that we also need to adjust the above as what we do for the type
and name. The v3 is coming.
Thanks,
Kevin
[-- Attachment #2: Type: application/pgp-signature, Size: 490 bytes --]
^ permalink raw reply
* Re: [PATCH 01/10] mfd: Add TI LMU driver
From: Lee Jones @ 2014-02-19 8:13 UTC (permalink / raw)
To: Milo Kim
Cc: Jingoo Han, Bryan Wu, Mark Brown, linux-kernel, devicetree,
Samuel Ortiz
In-Reply-To: <5303F3B5.6050806@ti.com>
> >>>>+ pdata->en_gpio = of_get_named_gpio(node, "ti,enable-gpio", 0);
> >>>
> >>>There is a global DT property for this already.
> >>
> >>I've not found it yet, but I agree it looks like general property.
> >>So I'll replace "ti,enable-gpio" with "ti,lmu-en-gpio".
> >
> >Just re-use "gpio-enable". No need for it to be vendor specific.
> >
>
> Got it. Thanks!
>
> This GPIO is used for enabling the device. So, "enable-gpio" is more
> appropriate name, isn't it?
Yes, I wrote it the wrong way round (typo).
Just grep for both, you will see which one to use.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v2] ARM/dts: hdmi-codec: panda/es dt entries
From: Peter Ujfalusi @ 2014-02-19 8:15 UTC (permalink / raw)
To: Paolo Pisati, bcousson, tony; +Cc: devicetree, linux-omap
In-Reply-To: <1392716606-7436-1-git-send-email-paolo.pisati@canonical.com>
Hi,
On 02/18/2014 11:43 AM, Paolo Pisati wrote:
> HDMI codec dummy entries for Panda/ES.
>
> Signed-off-by: Paolo Pisati <paolo.pisati@canonical.com>
> ---
> Depends on "0f7f3d1 ASoC: hdmi-codec: Add devicetree binding with documentation", eligible for a 3.14-rcX fix.
>
> arch/arm/boot/dts/omap4-panda-common.dtsi | 9 ++++++++-
> arch/arm/boot/dts/omap4-panda-es.dts | 3 ++-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> index 88c6a05..f4aeaa1 100644
> --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> @@ -36,9 +36,15 @@
> };
> };
>
> + hdmi_audio: hdmi_audio@0 {
> + compatible = "linux,hdmi-audio";
> + status = "okay";
> + };
> +
> sound: sound {
> compatible = "ti,abe-twl6040";
> ti,model = "PandaBoard";
> + ti,audio-codec = <&hdmi_audio>;
I don't think this is going to work. The omap-abe-twl6040 machine driver only
handles mcpdm and dmic right know.
'ti,audio-codec' is not even supported and it is kind of misleading naming in
this context since twl6040 is also a codec, so why only the dummy-hdmi codec
deserves to be called as codec.
Furthermore: we have the omap-hdmi-card machine driver to handle the HDMI
audio. It lacks DT support AFAIK but should not be a big deal to add the bindings.
To get the hdmi audio working you also need to have phandle for the omap-hdmi
DAI, the codec alone is not enough.
Is this patch actually works at all?
>
> ti,mclk-freq = <38400000>;
>
> @@ -57,7 +63,8 @@
> "HSMIC", "Headset Mic",
> "Headset Mic", "Headset Mic Bias",
> "AFML", "Line In",
> - "AFMR", "Line In";
> + "AFMR", "Line In",
> + "HDMI Out", "TX";
> };
>
> /* HS USB Port 1 Power */
> diff --git a/arch/arm/boot/dts/omap4-panda-es.dts b/arch/arm/boot/dts/omap4-panda-es.dts
> index 816d1c9..70152d6 100644
> --- a/arch/arm/boot/dts/omap4-panda-es.dts
> +++ b/arch/arm/boot/dts/omap4-panda-es.dts
> @@ -23,7 +23,8 @@
> "Line Out", "AUXL",
> "Line Out", "AUXR",
> "AFML", "Line In",
> - "AFMR", "Line In";
> + "AFMR", "Line In",
> + "HDMI Out", "TX";
> };
>
> /* PandaboardES has external pullups on SCL & SDA */
>
--
Péter
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^ permalink raw reply
* [PATCH v3 2/4] of: reimplement the matching method for __of_match_node()
From: Kevin Hao @ 2014-02-19 8:15 UTC (permalink / raw)
To: devicetree, linux-kernel
Cc: Kevin Hao, Rob Herring, Sebastian Hesselbarth, Grant Likely
In-Reply-To: <20140219075812.GE14031@pek-khao-d1.corp.ad.wrs.com>
In the current implementation of __of_match_node(), it will compare
each given match entry against all the node's compatible strings
with of_device_is_compatible().
To achieve multiple compatible strings per node with ordering from
specific to generic, this requires given matches to be ordered from
specific to generic. For most of the drivers this is not true and
also an alphabetical ordering is more sane there.
Therefore, we define a following priority order for the match, and
then scan all the entries to find the best match.
1. specific compatible && type && name
2. specific compatible && type
3. specific compatible && name
4. specific compatible
5. general compatible && type && name
6. general compatible && type
7. general compatible && name
8. general compatible
9. type && name
10. type
11. name
This is based on some pseudo-codes provided by Grant Likely.
Signed-off-by: Kevin Hao <haokexin@gmail.com>
[grant.likely: Changed multiplier to 4 which makes more sense]
Signed-off-by: Grant Likely <grant.likely@linaro.org>
---
v3: Also need to bail out when there does have a compatible member in match
entry, but it doesn't match with the device node's compatible.
v2: Fix the bug such as we get the same score for the following two match
entries:
name2 { }
struct of_device_id matches[] = {
{.name = "name2", },
{.name = "name2", .type = "type1", },
{}
};
drivers/of/base.c | 96 ++++++++++++++++++++++++++++++++++++++++++++-----------
1 file changed, 77 insertions(+), 19 deletions(-)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index ba195fbce4c6..8f79f006d86f 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -342,21 +342,28 @@ struct device_node *of_get_cpu_node(int cpu, unsigned int *thread)
}
EXPORT_SYMBOL(of_get_cpu_node);
-/** Checks if the given "compat" string matches one of the strings in
- * the device's "compatible" property
+/*
+ * Compare with the __of_device_is_compatible, this will return a score for the
+ * matching strings. The smaller value indicates the match for the more specific
+ * compatible string.
*/
-static int __of_device_is_compatible(const struct device_node *device,
- const char *compat)
+static int __of_device_is_compatible_score(const struct device_node *device,
+ const char *compat, int *pscore)
{
const char* cp;
int cplen, l;
+ int score = 0;
cp = __of_get_property(device, "compatible", &cplen);
if (cp == NULL)
return 0;
while (cplen > 0) {
- if (of_compat_cmp(cp, compat, strlen(compat)) == 0)
+ score++;
+ if (of_compat_cmp(cp, compat, strlen(compat)) == 0) {
+ if (pscore)
+ *pscore = score;
return 1;
+ }
l = strlen(cp) + 1;
cp += l;
cplen -= l;
@@ -368,6 +375,15 @@ static int __of_device_is_compatible(const struct device_node *device,
/** Checks if the given "compat" string matches one of the strings in
* the device's "compatible" property
*/
+static int __of_device_is_compatible(const struct device_node *device,
+ const char *compat)
+{
+ return __of_device_is_compatible_score(device, compat, NULL);
+}
+
+/** Checks if the given "compat" string matches one of the strings in
+ * the device's "compatible" property
+ */
int of_device_is_compatible(const struct device_node *device,
const char *compat)
{
@@ -734,25 +750,55 @@ static
const struct of_device_id *__of_match_node(const struct of_device_id *matches,
const struct device_node *node)
{
+ const struct of_device_id *best_match = NULL;
+ int best_score = 0;
+
if (!matches)
return NULL;
while (matches->name[0] || matches->type[0] || matches->compatible[0]) {
- int match = 1;
- if (matches->name[0])
- match &= node->name
- && !strcmp(matches->name, node->name);
- if (matches->type[0])
- match &= node->type
- && !strcmp(matches->type, node->type);
- if (matches->compatible[0])
- match &= __of_device_is_compatible(node,
- matches->compatible);
- if (match)
- return matches;
+ int score = 0;
+
+ /*
+ * Matching compatible is better than matching type and name,
+ * and the specific compatible is better than the general.
+ */
+ if (matches->compatible[0]) {
+ if (__of_device_is_compatible_score(node,
+ matches->compatible, &score))
+ score = INT_MAX - 4 * score;
+ else
+ score = INT_MIN;
+ }
+
+ /*
+ * Matching type is better than matching name, but matching
+ * both is even better than that.
+ */
+ if (matches->type[0]) {
+ if (node->type && !strcmp(matches->type, node->type))
+ score += 2;
+ else
+ score = INT_MIN;
+ }
+
+ /* Matching name is a bit better than not */
+ if (matches->name[0]) {
+ if (node->name && !strcmp(matches->name, node->name))
+ score++;
+ else
+ score = INT_MIN;
+ }
+
+ if (score > best_score) {
+ best_match = matches;
+ best_score = score;
+ }
+
matches++;
}
- return NULL;
+
+ return best_match;
}
/**
@@ -760,7 +806,19 @@ const struct of_device_id *__of_match_node(const struct of_device_id *matches,
* @matches: array of of device match structures to search in
* @node: the of device structure to match against
*
- * Low level utility function used by device matching.
+ * Low level utility function used by device matching. The priority order
+ * for the matching is:
+ * 1. specific compatible && type && name
+ * 2. specific compatible && type
+ * 3. specific compatible && name
+ * 4. specific compatible
+ * 5. general compatible && type && name
+ * 6. general compatible && type
+ * 7. general compatible && name
+ * 8. general compatible
+ * 9. type && name
+ * 10. type
+ * 11. name
*/
const struct of_device_id *of_match_node(const struct of_device_id *matches,
const struct device_node *node)
--
1.8.5.3
^ permalink raw reply related
* Re: [PATCH v3 2/6] drivers: of: add initialization code for reserved memory
From: Marek Szyprowski @ 2014-02-19 8:20 UTC (permalink / raw)
To: Grant Likely, linux-kernel, linux-arm-kernel, linaro-mm-sig,
devicetree, linux-doc
Cc: Kyungmin Park, Benjamin Herrenschmidt, Arnd Bergmann,
Michal Nazarewicz, Tomasz Figa, Sascha Hauer, Laura Abbott,
Rob Herring, Olof Johansson, Pawel Moll, Mark Rutland,
Stephen Warren, Ian Campbell, Tomasz Figa, Kumar Gala,
Nishanth Peethambaran, Marc, Josh Cartwright
In-Reply-To: <20140218165616.E1755C40517@trevor.secretlab.ca>
Hello,
On 2014-02-18 17:56, Grant Likely wrote:
> On Tue, 18 Feb 2014 14:37:57 +0100, Marek Szyprowski <m.szyprowski@samsung.com> wrote:
> > This patch adds device tree support for contiguous and reserved memory
> > regions defined in device tree.
> >
> > Large memory blocks can be reliably reserved only during early boot.
> > This must happen before the whole memory management subsystem is
> > initialized, because we need to ensure that the given contiguous blocks
> > are not yet allocated by kernel. Also it must happen before kernel
> > mappings for the whole low memory are created, to ensure that there will
> > be no mappings (for reserved blocks) or mapping with special properties
> > can be created (for CMA blocks). This all happens before device tree
> > structures are unflattened, so we need to get reserved memory layout
> > directly from fdt.
> >
> > Later, those reserved memory regions are assigned to devices on each
> > device structure initialization.
> >
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > [joshc: rework to implement new DT binding, provide mechanism for
> > plugging in new reserved-memory node handlers via
> > RESERVEDMEM_OF_DECLARE]
> > Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
> > [mszyprow: added generic memory reservation code]
> > Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> > ---
> > drivers/of/Kconfig | 5 +
> > drivers/of/Makefile | 1 +
> > drivers/of/fdt.c | 2 +
> > drivers/of/of_reserved_mem.c | 390 +++++++++++++++++++++++++++++++++++++
> > drivers/of/platform.c | 7 +
> > include/asm-generic/vmlinux.lds.h | 11 ++
> > include/linux/of_reserved_mem.h | 65 +++++++
> > 7 files changed, 481 insertions(+)
> > create mode 100644 drivers/of/of_reserved_mem.c
> > create mode 100644 include/linux/of_reserved_mem.h
> >
> > diff --git a/drivers/of/Kconfig b/drivers/of/Kconfig
> > index c6973f101a3e..f25931dfc6db 100644
> > --- a/drivers/of/Kconfig
> > +++ b/drivers/of/Kconfig
> > @@ -75,4 +75,9 @@ config OF_MTD
> > depends on MTD
> > def_bool y
> >
> > +config OF_RESERVED_MEM
> > + bool
> > + help
> > + Helpers to allow for reservation of memory regions
> > +
> > endmenu # OF
> > diff --git a/drivers/of/Makefile b/drivers/of/Makefile
> > index efd05102c405..ed9660adad77 100644
> > --- a/drivers/of/Makefile
> > +++ b/drivers/of/Makefile
> > @@ -9,3 +9,4 @@ obj-$(CONFIG_OF_MDIO) += of_mdio.o
> > obj-$(CONFIG_OF_PCI) += of_pci.o
> > obj-$(CONFIG_OF_PCI_IRQ) += of_pci_irq.o
> > obj-$(CONFIG_OF_MTD) += of_mtd.o
> > +obj-$(CONFIG_OF_RESERVED_MEM) += of_reserved_mem.o
>
> As mentioned previously, parts of this are absolutely non-optional and
> cannot be compiled out. If a region is marked as reserved with this
> binding, then the kernel must respect it. That part of the code must be
> always configured in.
How can I make it non-optional if all this code must be called from arch
specific early-boot init code to properly reserve memory. Do you want me
to add those calls to every architecture which supports OF?
> > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > index 758b4f8b30b7..c205c84e51a1 100644
> > --- a/drivers/of/fdt.c
> > +++ b/drivers/of/fdt.c
> > @@ -15,6 +15,7 @@
> > #include <linux/module.h>
> > #include <linux/of.h>
> > #include <linux/of_fdt.h>
> > +#include <linux/of_reserved_mem.h>
> > #include <linux/string.h>
> > #include <linux/errno.h>
> > #include <linux/slab.h>
> > @@ -907,6 +908,7 @@ void __init unflatten_device_tree(void)
> >
> > /* Get pointer to "/chosen" and "/aliases" nodes for use everywhere */
> > of_alias_scan(early_init_dt_alloc_memory_arch);
> > + of_reserved_mem_scan();
> > }
> >
> > /**
> > diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
> > new file mode 100644
> > index 000000000000..074d66e41da8
> > --- /dev/null
> > +++ b/drivers/of/of_reserved_mem.c
> > @@ -0,0 +1,390 @@
> > +/*
> > + * Device tree based initialization code for reserved memory.
> > + *
> > + * Copyright (c) 2013, The Linux Foundation. All Rights Reserved.
> > + * Copyright (c) 2013,2014 Samsung Electronics Co., Ltd.
> > + * http://www.samsung.com
> > + * Author: Marek Szyprowski <m.szyprowski@samsung.com>
> > + * Author: Josh Cartwright <joshc@codeaurora.org>
> > + *
> > + * This program is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License or (at your optional) any later version of the license.
> > + */
> > +
> > +#include <linux/err.h>
> > +#include <linux/of.h>
> > +#include <linux/of_fdt.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/mm.h>
> > +#include <linux/sizes.h>
> > +#include <linux/of_reserved_mem.h>
> > +
> > +#define MAX_RESERVED_REGIONS 16
> > +static struct reserved_mem reserved_mem[MAX_RESERVED_REGIONS];
> > +static int reserved_mem_count;
> > +
> > +#if defined(CONFIG_HAVE_MEMBLOCK)
> > +#include <linux/memblock.h>
> > +int __init __weak
> > +early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size,
> > + bool nomap)
> > +{
> > + if (memblock_is_region_reserved(base, size))
> > + return -EBUSY;
> > + if (nomap)
> > + return memblock_remove(base, size);
> > + return memblock_reserve(base, size);
> > +}
> > +
> > +int __init __weak
> > +early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, phys_addr_t align,
> > + phys_addr_t start, phys_addr_t end,
> > + bool nomap, phys_addr_t *res_base)
> > +{
> > + /*
> > + * We use __memblock_alloc_base() since memblock_alloc_base() panic()s.
> > + */
> > + phys_addr_t base = __memblock_alloc_base(size, align, end);
> > + if (!base)
> > + return -ENOMEM;
>
> Just realized this; this is actually a problem because an allocated
> range may end up conflicting with a static range. Reservations must be
> done in two passes. First pass should handle static ranges. Second pass
> for doing dynamic allocations.
Right... I will check if it is possible to avoid dual-pass, because we are
already parsing all nodes stored in FDT, what might be time consuming.
> > +
> > + if (base < start) {
> > + memblock_free(base, size);
> > + return -ENOMEM;
> > + }
> > +
> > + *res_base = base;
> > + if (nomap)
> > + return memblock_remove(base, size);
> > + return 0;
> > +}
> > +#else
> > +int __init __weak
> > +early_init_dt_reserve_memory_arch(phys_addr_t base, phys_addr_t size,
> > + bool nomap)
> > +{
> > + pr_error("Reserved memory not supported, ignoring range 0x%llx - 0x%llx%s\n",
> > + base, size, nomap ? " (nomap)" : "");
> > + return -ENOSYS;
> > +}
> > +
> > +int __init __weak
> > +early_init_dt_alloc_reserved_memory_arch(phys_addr_t size, phys_addr_t align,
> > + phys_addr_t start, phys_addr_t end,
> > + bool nomap, phys_addr_t *res_base)
> > +{
> > + pr_error("Reserved memory not supported, ignoring region 0x%llx%s\n",
> > + size, nomap ? " (nomap)" : "");
> > + return -ENOSYS;
> > +}
> > +#endif
> > +
> > +/**
> > + * res_mem_reserve_reg() - reserve all memory described in 'reg' property
> > + */
> > +static int __init
> > +res_mem_reserve_reg(unsigned long node, const char *uname, int nomap,
> > + phys_addr_t *res_base, phys_addr_t *res_size)
> > +{
> > + int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
> > + phys_addr_t base, size;
> > + unsigned long len;
> > + __be32 *prop;
> > +
> > + prop = of_get_flat_dt_prop(node, "reg", &len);
> > + if (!prop)
> > + return -ENOENT;
> > +
> > + if (len && len % t_len != 0) {
> > + pr_err("Reserved memory: invalid reg property in '%s', skipping node.\n",
> > + uname);
> > + return -EINVAL;
> > + }
> > +
> > + /* store base and size values from the first reg tuple */
> > + *res_base = 0;
> > + while (len > 0) {
> > + base = dt_mem_next_cell(dt_root_addr_cells, &prop);
> > + size = dt_mem_next_cell(dt_root_size_cells, &prop);
> > +
> > + if (base && size &&
> > + early_init_dt_reserve_memory_arch(base, size, nomap) == 0)
> > + pr_debug("Reserved memory: reserved region for node '%s': base %pa, size %ld MiB\n",
> > + uname, &base, (unsigned long)size / SZ_1M);
> > + else
> > + pr_info("Reserved memory: failed to reserve memory for node '%s': base %pa, size %ld MiB\n",
> > + uname, &base, (unsigned long)size / SZ_1M);
> > +
> > + len -= t_len;
> > +
> > + if (!(*res_base)) {
> > + *res_base = base;
> > + *res_size = size;
> > + }
> > + }
> > + return 0;
> > +}
> > +
> > +/**
> > + * res_mem_alloc_size() - allocate reserved memory described by 'size', 'align'
> > + * and 'alloc-ranges' properties
> > + */
> > +static int __init
> > +res_mem_alloc_size(unsigned long node, const char *uname, int nomap,
> > + phys_addr_t *res_base, phys_addr_t *res_size)
> > +{
> > + int t_len = (dt_root_addr_cells + dt_root_size_cells) * sizeof(__be32);
> > + phys_addr_t start = 0, end = 0;
> > + phys_addr_t base = 0, align = 0, size;
> > + unsigned long len;
> > + __be32 *prop;
> > + int ret;
> > +
> > + prop = of_get_flat_dt_prop(node, "size", &len);
> > + if (!prop)
> > + return -EINVAL;
> > +
> > + if (len != dt_root_size_cells * sizeof(__be32)) {
> > + pr_err("Reserved memory: invalid size property in '%s' node.\n",
> > + uname);
> > + return -EINVAL;
> > + }
> > + size = dt_mem_next_cell(dt_root_size_cells, &prop);
> > +
> > + prop = of_get_flat_dt_prop(node, "align", &len);
> > + if (prop) {
> > + if (len != dt_root_addr_cells * sizeof(__be32)) {
> > + pr_err("Reserved memory: invalid align property in '%s' node.\n",
> > + uname);
> > + return -EINVAL;
> > + }
> > + align = dt_mem_next_cell(dt_root_addr_cells, &prop);
> > + }
> > +
> > + prop = of_get_flat_dt_prop(node, "alloc-ranges", &len);
> > + if (prop) {
> > +
> > + if (len % t_len != 0) {
> > + pr_err("Reserved memory: invalid alloc-ranges property in '%s', skipping node.\n",
> > + uname);
> > + return -EINVAL;
> > + }
> > +
> > + base = 0;
> > +
> > + while (len > 0) {
> > + start = dt_mem_next_cell(dt_root_addr_cells, &prop);
> > + end = start + dt_mem_next_cell(dt_root_size_cells,
> > + &prop);
> > +
> > + ret = early_init_dt_alloc_reserved_memory_arch(size,
> > + align, start, end, nomap, &base);
> > + if (ret == 0) {
> > + pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n",
> > + uname, &base,
> > + (unsigned long)size / SZ_1M);
> > + break;
> > + }
> > + len -= t_len;
> > + }
> > +
> > + } else {
> > + ret = early_init_dt_alloc_reserved_memory_arch(size, align,
> > + 0, 0, nomap, &base);
> > + if (ret == 0)
> > + pr_debug("Reserved memory: allocated memory for '%s' node: base %pa, size %ld MiB\n",
> > + uname, &base, (unsigned long)size / SZ_1M);
> > + }
> > +
> > + if (base == 0) {
> > + pr_info("Reserved memory: failed to allocate memory for node '%s'\n",
> > + uname);
> > + return -ENOMEM;
> > + }
> > +
> > + *res_base = base;
> > + *res_size = size;
> > +
> > + return 0;
> > +}
> > +
> > +static const struct of_device_id __rmem_of_table_sentinel
> > + __used __section(__reservedmem_of_table_end);
> > +
> > +/**
> > + * res_mem_init_node() - call region specific reserved memory init code
> > + */
> > +static int __init
> > +res_mem_init_node(unsigned long node, const char *uname, phys_addr_t base,
> > + phys_addr_t size)
> > +{
> > + struct reserved_mem *rmem = &reserved_mem[reserved_mem_count];
> > + extern const struct of_device_id __reservedmem_of_table[];
> > + const struct of_device_id *i;
> > +
> > + if (reserved_mem_count == ARRAY_SIZE(reserved_mem)) {
> > + pr_err("Reserved memory: not enough space all defined regions.\n");
> > + return -ENOSPC;
> > + }
> > +
> > + rmem->base = base;
> > + rmem->size = size;
> > +
> > + for (i = __reservedmem_of_table; i < &__rmem_of_table_sentinel; i++) {
> > + reservedmem_of_init_fn initfn = i->data;
> > + const char *compat = i->compatible;
> > +
> > + if (!of_flat_dt_is_compatible(node, compat))
> > + continue;
> > +
> > + if (initfn(rmem, node, uname) == 0) {
> > + pr_info("Reserved memory: initialized node %s, compatible id %s\n",
> > + uname, compat);
> > + rmem->name = uname;
> > + reserved_mem_count++;
> > + return 0;
> > + }
> > + }
> > + return -EINVAL;
> > +}
> > +
> > +/**
> > + * fdt_scan_reserved_mem() - scan a single FDT node for reserved memory
> > + */
> > +static int __init
> > +fdt_scan_reserved_mem(unsigned long node, const char *uname, int depth,
> > + void *data)
> > +{
> > + phys_addr_t base, size;
> > + const char *status;
> > + int nomap;
> > + int err;
> > +
> > + status = of_get_flat_dt_prop(node, "status", NULL);
> > + if (status && strcmp(status, "okay") != 0 && strcmp(status, "ok") != 0)
> > + return 0;
> > +
> > + nomap = of_get_flat_dt_prop(node, "no-map", NULL) != NULL;
> > +
> > + err = res_mem_reserve_reg(node, uname, nomap, &base, &size);
> > + if (err == -ENOENT)
> > + err = res_mem_alloc_size(node, uname, nomap, &base, &size);
> > + if (err)
> > + goto end;
> > +
> > + res_mem_init_node(node, uname, base, size);
> > +end:
> > + /* scan next node */
> > + return 0;
> > +}
> > +
> > +/**
> > + * early_init_dt_scan_reserved_mem() - create reserved memory regions
> > + *
> > + * This function grabs memory from early allocator for device exclusive use
> > + * defined in device tree structures. It should be called by arch specific code
> > + * once the early allocator (i.e. memblock) has been fully activated.
> > + */
> > +void __init early_init_dt_scan_reserved_mem(void)
> > +{
> > + of_scan_flat_dt_by_path("/reserved-memory", fdt_scan_reserved_mem,
> > + NULL);
> > +}
>
> Just about everything above this point must be moved to fdt.c. Processing the
> static reserved regions must be non-optional code. You can factor out
> the table of reserved regions if you like, but I want the core
> functionality directly in fdt.c.
Ok, I will move it then.
> The dynamic allocation code can be optional, but that is because it
> describes dynamic regions that have no possibility of hardware already
> using them.
>
> > +
> > +/**
> > + * of_reserved_mem_scan() - scan and create structures required by reserved
> > + * memory regions
> > + *
> > + * This function creates all structures required by reserved memory regions
> > + * management code. It should be called by common code once the device tree
> > + * has been unflattened.
> > + */
> > +void __init of_reserved_mem_scan(void)
> > +{
> > + struct device_node *root, *np;
> > +
> > + root = of_find_node_by_path("/reserved-memory");
> > +
> > + if (of_n_addr_cells(root) != dt_root_addr_cells ||
> > + of_n_size_cells(root) != dt_root_size_cells)
> > + panic("Unsupported address or size cells for /reserved-memory node\n");
> > +
> > + for (np = NULL;;) {
> > + const char *name;
> > + int i;
> > +
> > + np = of_get_next_available_child(root, np);
> > + if (!np)
> > + break;
> > +
> > + name = kbasename(np->full_name);
> > + for (i = 0; i < reserved_mem_count; i++)
> > + if (strcmp(name, reserved_mem[i].name) == 0)
> > + reserved_mem[i].node = np;
>
> I've already commented on the above. kbasename is not a safe match.
Then please point me anything better to match FDT node with the
unflattened one. There
is no need to match the whole path, because both names comes from
'/reserved-memory'
node (one from FTD, one from unflattened structure).
> > + }
> > +}
> > +
> > +static inline struct reserved_mem *find_rmem(struct device_node *phandle)
> > +{
> > + unsigned int i;
> > + for (i = 0; i < reserved_mem_count; i++)
> > + if (reserved_mem[i].node == phandle)
> > + return &reserved_mem[i];
> > + return NULL;
> > +}
> > +
> > +/**
> > + * of_reserved_mem_device_init() - assign reserved memory region to given device
> > + *
> > + * This function assign memory region pointed by "memory-region" device tree
> > + * property to the given device.
> > + */
> > +void of_reserved_mem_device_init(struct device *dev)
> > +{
> > + struct device_node *np = dev->of_node;
> > + struct reserved_mem *rmem;
> > + struct of_phandle_args s;
> > + unsigned int i;
> > +
> > + for (i = 0; of_parse_phandle_with_args(np, "memory-region",
> > + "#memory-region-cells", i, &s) == 0; i++) {
> > +
> > + rmem = find_rmem(s.np);
> > + if (!rmem || !rmem->ops || !rmem->ops->device_init) {
> > + of_node_put(s.np);
> > + continue;
> > + }
> > +
> > + rmem->ops->device_init(rmem, dev, &s);
> > + dev_info(dev, "assigned reserved memory node %s\n",
> > + rmem->name);
> > + of_node_put(s.np);
> > + break;
> > + }
> > +}
> > +
> > +/**
> > + * of_reserved_mem_device_release() - release reserved memory device structures
> > + *
> > + * This function releases structures allocated for memory region handling for
> > + * the given device.
> > + */
> > +void of_reserved_mem_device_release(struct device *dev)
> > +{
> > + struct device_node *np = dev->of_node;
> > + struct reserved_mem *rmem;
> > + struct of_phandle_args s;
> > + unsigned int i;
> > +
> > + for (i = 0; of_parse_phandle_with_args(np, "memory-region",
> > + "#memory-region-cells", i, &s) == 0; i++) {
> > +
> > + rmem = find_rmem(s.np);
> > + if (rmem && rmem->ops && rmem->ops->device_release)
> > + rmem->ops->device_release(rmem, dev);
> > +
> > + of_node_put(s.np);
> > + }
> > +}
> > diff --git a/drivers/of/platform.c b/drivers/of/platform.c
> > index 404d1daebefa..3df0b1826e8b 100644
> > --- a/drivers/of/platform.c
> > +++ b/drivers/of/platform.c
> > @@ -21,6 +21,7 @@
> > #include <linux/of_device.h>
> > #include <linux/of_irq.h>
> > #include <linux/of_platform.h>
> > +#include <linux/of_reserved_mem.h>
> > #include <linux/platform_device.h>
> >
> > const struct of_device_id of_default_bus_match_table[] = {
> > @@ -220,6 +221,8 @@ static struct platform_device *of_platform_device_create_pdata(
> > dev->dev.bus = &platform_bus_type;
> > dev->dev.platform_data = platform_data;
> >
> > + of_reserved_mem_device_init(&dev->dev);
> > +
> > /* We do not fill the DMA ops for platform devices by default.
> > * This is currently the responsibility of the platform code
> > * to do such, possibly using a device notifier
> > @@ -227,6 +230,7 @@ static struct platform_device *of_platform_device_create_pdata(
> >
> > if (of_device_add(dev) != 0) {
> > platform_device_put(dev);
> > + of_reserved_mem_device_release(&dev->dev);
> > return NULL;
> > }
> >
> > @@ -282,6 +286,8 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
> > else
> > of_device_make_bus_id(&dev->dev);
> >
> > + of_reserved_mem_device_init(&dev->dev);
> > +
> > /* Allow the HW Peripheral ID to be overridden */
> > prop = of_get_property(node, "arm,primecell-periphid", NULL);
> > if (prop)
> > @@ -308,6 +314,7 @@ static struct amba_device *of_amba_device_create(struct device_node *node,
> > return dev;
> >
> > err_free:
> > + of_reserved_mem_device_release(&dev->dev);
> > amba_device_put(dev);
> > return NULL;
> > }
> > diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
> > index bc2121fa9132..f10f64fcc815 100644
> > --- a/include/asm-generic/vmlinux.lds.h
> > +++ b/include/asm-generic/vmlinux.lds.h
> > @@ -167,6 +167,16 @@
> > #define CLK_OF_TABLES()
> > #endif
> >
> > +#ifdef CONFIG_OF_RESERVED_MEM
> > +#define RESERVEDMEM_OF_TABLES() \
> > + . = ALIGN(8); \
> > + VMLINUX_SYMBOL(__reservedmem_of_table) = .; \
> > + *(__reservedmem_of_table) \
> > + *(__reservedmem_of_table_end)
> > +#else
> > +#define RESERVEDMEM_OF_TABLES()
> > +#endif
> > +
> > #define KERNEL_DTB() \
> > STRUCT_ALIGN(); \
> > VMLINUX_SYMBOL(__dtb_start) = .; \
> > @@ -490,6 +500,7 @@
> > TRACE_SYSCALLS() \
> > MEM_DISCARD(init.rodata) \
> > CLK_OF_TABLES() \
> > + RESERVEDMEM_OF_TABLES() \
> > CLKSRC_OF_TABLES() \
> > KERNEL_DTB() \
> > IRQCHIP_OF_MATCH_TABLE()
> > diff --git a/include/linux/of_reserved_mem.h b/include/linux/of_reserved_mem.h
> > new file mode 100644
> > index 000000000000..39a4fb17a5ea
> > --- /dev/null
> > +++ b/include/linux/of_reserved_mem.h
> > @@ -0,0 +1,65 @@
> > +#ifndef __OF_RESERVED_MEM_H
> > +#define __OF_RESERVED_MEM_H
> > +
> > +struct cma;
> > +struct platform_device;
> > +struct of_phandle_args;
> > +struct reserved_mem_ops;
> > +
> > +struct reserved_mem {
> > + const char *name;
> > + struct device_node *node;
> > + const struct reserved_mem_ops *ops;
> > + phys_addr_t base;
> > + phys_addr_t size;
> > + void *priv;
> > +};
> > +
> > +struct reserved_mem_ops {
> > + void (*device_init)(struct reserved_mem *rmem,
> > + struct device *dev,
> > + struct of_phandle_args *args);
> > + void (*device_release)(struct reserved_mem *rmem,
> > + struct device *dev);
> > +};
> > +
> > +typedef int (*reservedmem_of_init_fn)(struct reserved_mem *rmem,
> > + unsigned long node, const char *uname);
> > +
> > +#ifdef CONFIG_OF_RESERVED_MEM
> > +void of_reserved_mem_device_init(struct device *dev);
> > +void of_reserved_mem_device_release(struct device *dev);
> > +void early_init_dt_scan_reserved_mem(void);
> > +void of_reserved_mem_scan(void);
> > +
> > +int of_parse_flat_dt_reg(unsigned long node, const char *uname,
> > + phys_addr_t *base, phys_addr_t *size);
> > +int of_parse_flat_dt_size(unsigned long node, const char *uname,
> > + phys_addr_t *size);
> > +
> > +#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
> > + static const struct of_device_id __reservedmem_of_table_##name \
> > + __used __section(__reservedmem_of_table) \
> > + = { .compatible = compat, \
> > + .data = (init == (reservedmem_of_init_fn)NULL) ? \
> > + init : init }
> > +
> > +#else
> > +static inline void of_reserved_mem_device_init(struct device *dev) { }
> > +
> > +static inline
> > +void of_reserved_mem_device_release(struct device *pdev) { }
> > +
> > +static inline void early_init_dt_scan_reserved_mem(void) { }
> > +static inline void of_reserved_mem_scan(void) { }
> > +
> > +#define RESERVEDMEM_OF_DECLARE(name, compat, init) \
> > + static const struct of_device_id __reservedmem_of_table_##name \
> > + __attribute__((unused)) \
> > + = { .compatible = compat, \
> > + .data = (init == (reservedmem_of_init_fn)NULL) ? \
> > + init : init }
> > +
> > +#endif
> > +
> > +#endif /* __OF_RESERVED_MEM_H */
> > --
> > 1.7.9.5
> >
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
^ permalink raw reply
* Re: devicetree repository separation/migration
From: Sascha Hauer @ 2014-02-19 8:32 UTC (permalink / raw)
To: Jason Cooper
Cc: Grant Likely, Rob Herring, Ian Campbell, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, galak-sgV2jX0FEOL9JmXXK+q4OQ,
rob-VoJi6FS/r0vR7s880joybQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
devicetree-spec-u79uwXL29TY76Z2rM5mHXA,
devicetree-compiler-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20140218181854.GB7862-u4khhh1J0LxI1Ri9qeTfzeTW4wlIGRCZ@public.gmane.org>
On Tue, Feb 18, 2014 at 01:18:54PM -0500, Jason Cooper wrote:
> On Tue, Feb 18, 2014 at 04:57:50PM +0100, Sascha Hauer wrote:
> > On Mon, Feb 17, 2014 at 01:05:44PM -0500, Jason Cooper wrote:
> ...
> > > - Is the Linux development workflow ready for devicetree to move out
> > > of the Linux Kernel?
> >
> > I hope so since keeping the devicetrees in sync with the kernel is a
> > pain for all external users.
>
> Well, I haven't heard any screams yet. I suspect people are waiting for
> details on the exact form it would take before complaining...
>
> > > - How do we envision projects will use it? git submodule? reference
> > > a version tag? (this is primarily targeted at bootloaders that need
> > > to compile in a dtb or subset of a dtb into the bootloader)
> >
> > I would prefer to use it as a submodule.
>
> ok. I've often thought that was the right solution for several things
> (dtc.git inside the kernel tree), but no one ever seemed to speak of it
> or bring it up. Kinda like leprosy.
>
> It does add an extra step to build process for new users. Although that
> could be handled in the Makefile.
>
> > I'll likely need some barebox specific additions to the devicetrees.
> > Right now our idea is to leave the provided devicetrees untouched and
> > instead of compiling the board dts files directly we create
> > <boardname>-barebox.dts files which include the original board files.
> > That would allow us to provide additional information to barebox
> > without having to carry patches for the devicetrees.
>
> So the resulting <boardname>-barebox.dtb is compiled into the barebox
> binary? Is the dtb passed to the kernel independently upgradeable?
Yes, it's compiled into barebox. barebox uses it for probing from
devicetree. You can pass this devicetree to the kernel or provide
another one should you want or have to.
>
> Why not post binding/dts patches for 'barebox,...' attributes that you
> need?
I wasn't clear. The bindings themselves should be posted and merged
mainline. mtd partitions are a good example for what I mean. I don't
want to see them in the mainline dts files because that would mean my
partitioning would change with each mainline change. Nevertheless I have
the partitions in the barebox dts files.
Sascha
--
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^ permalink raw reply
* Re: [PATCH v7 2/8] clk: sunxi: Implement MMC phase control
From: Maxime Ripard @ 2014-02-19 8:36 UTC (permalink / raw)
To: Mike Turquette
Cc: David Lanzendörfer, devicetree-u79uwXL29TY76Z2rM5mHXA,
Ulf Hansson <ulf.hansson@linaro.org>, Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>, Simon Baatz <gmbnomis@gmail.com>, Hans de Goede <hdegoede@redhat.com>, Emilio López <emilio@elopez.com.ar>, linux-mmc@vger.kernel.org, Chris Ball <chris@printf.net>, linux-kernel@vger.kernel.org, H Hartley Sweeten <hsweeten@visionengravers.com>, linux-sunxi@googlegroups.com, Tejun Heo <tj@kernel.org>, Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140219052125.8345.70717@quantum>
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Hi Mike,
On Tue, Feb 18, 2014 at 09:21:25PM -0800, Mike Turquette wrote:
> Quoting Maxime Ripard (2014-02-18 06:15:32)
> > Hi,
> >
> > On Mon, Feb 17, 2014 at 11:02:21AM +0100, David Lanzendörfer wrote:
> > > From: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
> > >
> > > Signed-off-by: Emilio López <emilio-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
> >
> > You're missing your Signed-off-by here too. Remember, for every patch
> > you send, your Signed-off-by must be there, regardless wether you're
> > the author or not.
> >
> > A commit log would be very much welcome too.
> >
> > Now, down to the patch itself, I remember Mike saying that he would
> > prefer adding a function in the framework instead of hardcoding
> > it. Mike, what's your feeling on this? Would merging this seem
> > reasonnable to you as is, or do you want to take this to the
> > framework?
>
> Hi Maxime & Emilio,
>
> Maybe something like the following RFC? If it seems sufficient for this
> case then I will post to the wider list with an eye towards merging it
> for 3.15. I've Cc'd Dinh since this came up on the socfpga thread as
> well.
>
> Regards,
> Mike
>
>
>
> From 56fa297591be5c5e22df6d2ca43fccf285a45636 Mon Sep 17 00:00:00 2001
> From: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Date: Tue, 18 Feb 2014 20:33:50 -0800
> Subject: [PATCH] clk: introduce clk_set_phase function & callback
>
> A common operation for a clock signal generator is to shift the phase of
> that signal. This patch introduces a new function to the clk.h API to
> dynamically adjust the phase of a clock signal. Additionally this patch
> introduces support for the new function in the common clock framework
> via the .set_phase call back in struct clk_ops.
>
> Signed-off-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> This patch is totally untested. It may make your board burst into
> flames.
>
> drivers/clk/clk.c | 84 +++++++++++++++++++++++++++++++++++++++++---
> include/linux/clk-private.h | 1 +
> include/linux/clk-provider.h | 5 +++
> include/linux/clk.h | 29 +++++++++++++++
> 4 files changed, 115 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
> index ea2ca9f..635170a 100644
> --- a/drivers/clk/clk.c
> +++ b/drivers/clk/clk.c
> @@ -106,11 +106,11 @@ static void clk_summary_show_one(struct seq_file *s, struct clk *c, int level)
> if (!c)
> return;
>
> - seq_printf(s, "%*s%-*s %-11d %-12d %-10lu %-11lu",
> + seq_printf(s, "%*s%-*s %-11d %-12d %-10lu %-11lu %-3d",
> level * 3 + 1, "",
> 30 - level * 3, c->name,
> c->enable_count, c->prepare_count, clk_get_rate(c),
> - clk_get_accuracy(c));
> + clk_get_accuracy(c), clk_get_phase(c));
> seq_printf(s, "\n");
> }
>
> @@ -132,8 +132,8 @@ static int clk_summary_show(struct seq_file *s, void *data)
> {
> struct clk *c;
>
> - seq_printf(s, " clock enable_cnt prepare_cnt rate accuracy\n");
> - seq_printf(s, "---------------------------------------------------------------------------------\n");
> + seq_printf(s, " clock enable_cnt prepare_cnt rate accuracy phase\n");
> + seq_printf(s, "-----------------------------------------------------------------------------------------\n");
>
> clk_prepare_lock();
>
> @@ -171,6 +171,7 @@ static void clk_dump_one(struct seq_file *s, struct clk *c, int level)
> seq_printf(s, "\"prepare_count\": %d,", c->prepare_count);
> seq_printf(s, "\"rate\": %lu", clk_get_rate(c));
> seq_printf(s, "\"accuracy\": %lu", clk_get_accuracy(c));
> + seq_printf(s, "\"phase\": %d", clk_get_phase(c));
> }
>
> static void clk_dump_subtree(struct seq_file *s, struct clk *c, int level)
> @@ -257,6 +258,11 @@ static int clk_debug_create_one(struct clk *clk, struct dentry *pdentry)
> if (!d)
> goto err_out;
>
> + d = debugfs_create_u32("clk_phase", S_IRUGO, clk->dentry,
> + (u32 *)&clk->phase);
> + if (!d)
> + goto err_out;
> +
> d = debugfs_create_x32("clk_flags", S_IRUGO, clk->dentry,
> (u32 *)&clk->flags);
> if (!d)
> @@ -1766,6 +1772,76 @@ out:
> EXPORT_SYMBOL_GPL(clk_set_parent);
>
> /**
> + * clk_set_phase - adjust the phase shift of a clock signal
> + * @clk: clock signal source
> + * @degrees: number of degrees the signal is shifted
> + *
> + * Shifts the phase of a clock signal by the specified degrees. Returns 0 on
> + * success, -EERROR otherwise.
> + *
> + * This function makes no distiction about the input or reference signal that
> + * we adjust the clock signal phase against. For example phase locked-loop
> + * clock signal generators we may shift phase with respect to feedback clock
> + * signal input, but for other cases the clock phase may be shifted with
> + * respect to some other, unspecified signal.
> + *
> + * Additionally the concept of phase shift does not propagate through the clock
> + * tree hierarchy, which sets it appart from clock rates and clock accuracy. A
> + * parent clock phase attribute does not have an impact on the phase attribute
> + * of a child clock.
> + */
> +int clk_set_phase(struct clk *clk, int degrees)
Actually, while this is what I had in mind too, we'd need a bit more
control here. We have two phases to control (namely, input and
sample).
Maybe passing an additional enum to tell which phase we want to
adjust, that could easily be extended by new drivers need would fit
our need here?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH] pinctrl: add pinctrl driver for imx6sx
From: Shawn Guo @ 2014-02-19 8:39 UTC (permalink / raw)
To: Anson Huang
Cc: kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
dong.aisheng-QSEj5FYQhm4dnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1392793619-16767-1-git-send-email-b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
On Wed, Feb 19, 2014 at 03:06:59PM +0800, Anson Huang wrote:
> Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
> driver.
I haven't seen that Freescale announces this SoC. I would suggest we
wait for a while until we see the announcement telling that i.MX6 SoloX
is the name of this SoC.
Shawn
>
> Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> ---
> .../bindings/pinctrl/fsl,imx6sx-pinctrl.txt | 38 +
> arch/arm/boot/dts/imx6sx-pinfunc.h | 1544 ++++++++++++++++++++
> drivers/pinctrl/Kconfig | 8 +
> drivers/pinctrl/Makefile | 1 +
> drivers/pinctrl/pinctrl-imx6sx.c | 407 ++++++
> 5 files changed, 1998 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
> create mode 100755 arch/arm/boot/dts/imx6sx-pinfunc.h
> create mode 100644 drivers/pinctrl/pinctrl-imx6sx.c
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
> new file mode 100644
> index 0000000..67f62ba
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
> @@ -0,0 +1,38 @@
> +* Freescale IMX6 SoloX IOMUX Controller
> +
> +Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
> +and usage.
> +
> +Required properties:
> +- compatible: "fsl,imx6sx-iomuxc"
> +- fsl,pins: two integers array, represents a group of pins mux and config
> + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
> + pin working on a specific function, CONFIG is the pad setting value like
> + pull-up for this pin. Please refer to imx6sx datasheet for the valid pad
> + config settings.
> +
> +CONFIG bits definition:
> +PAD_CTL_HYS (1 << 16)
> +PAD_CTL_PUS_100K_DOWN (0 << 14)
> +PAD_CTL_PUS_47K_UP (1 << 14)
> +PAD_CTL_PUS_100K_UP (2 << 14)
> +PAD_CTL_PUS_22K_UP (3 << 14)
> +PAD_CTL_PUE (1 << 13)
> +PAD_CTL_PKE (1 << 12)
> +PAD_CTL_ODE (1 << 11)
> +PAD_CTL_SPEED_LOW (0 << 6)
> +PAD_CTL_SPEED_MED (1 << 6)
> +PAD_CTL_SPEED_HIGH (3 << 6)
> +PAD_CTL_DSE_DISABLE (0 << 3)
> +PAD_CTL_DSE_260ohm (1 << 3)
> +PAD_CTL_DSE_130ohm (2 << 3)
> +PAD_CTL_DSE_87ohm (3 << 3)
> +PAD_CTL_DSE_65ohm (4 << 3)
> +PAD_CTL_DSE_52ohm (5 << 3)
> +PAD_CTL_DSE_43ohm (6 << 3)
> +PAD_CTL_DSE_37ohm (7 << 3)
> +PAD_CTL_SRE_FAST (1 << 0)
> +PAD_CTL_SRE_SLOW (0 << 0)
> +
> +Refer to imx6sx-pinfunc.h in device tree source folder for all available
> +imx6sx PIN_FUNC_ID.
> diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-pinfunc.h
> new file mode 100755
> index 0000000..3e0b816
> --- /dev/null
> +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
> @@ -0,0 +1,1544 @@
> +/*
> + * Copyright 2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + */
> +
> +#ifndef __DTS_IMX6SX_PINFUNC_H
> +#define __DTS_IMX6SX_PINFUNC_H
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014 0x035C 0x07A8 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014 0x035C 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014 0x035C 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014 0x035C 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014 0x035C 0x0000 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014 0x035C 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014 0x035C 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014 0x035C 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018 0x0360 0x07AC 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018 0x0360 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018 0x0360 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018 0x0360 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018 0x0360 0x0000 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018 0x0360 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018 0x0360 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018 0x0360 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C 0x0364 0x07B0 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C 0x0364 0x0864 0x1 0x1
> +#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C 0x0364 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C 0x0364 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C 0x0364 0x0000 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C 0x0364 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C 0x0364 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C 0x0364 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020 0x0368 0x07B4 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020 0x0368 0x0868 0x1 0x1
> +#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020 0x0368 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020 0x0368 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020 0x0368 0x0000 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020 0x0368 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020 0x0368 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020 0x0368 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024 0x036C 0x0830 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024 0x036C 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024 0x036C 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024 0x036C 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024 0x036C 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024 0x036C 0x076C 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024 0x036C 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024 0x036C 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024 0x036C 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028 0x0370 0x0830 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028 0x0370 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028 0x0370 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028 0x0370 0x0764 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028 0x0370 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028 0x0370 0x0760 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028 0x0370 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028 0x0370 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028 0x0370 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C 0x0374 0x0838 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C 0x0374 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C 0x0374 0x086C 0x1 0x1
> +#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C 0x0374 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C 0x0374 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C 0x0374 0x082C 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C 0x0374 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C 0x0374 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C 0x0374 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030 0x0378 0x0838 0x0 0x1
> +#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030 0x0378 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030 0x0378 0x0870 0x1 0x1
> +#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030 0x0378 0x0770 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030 0x0378 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030 0x0378 0x082C 0x4 0x1
> +#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030 0x0378 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030 0x0378 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030 0x0378 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030 0x0378 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034 0x037C 0x0860 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034 0x037C 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034 0x037C 0x081C 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034 0x037C 0x069C 0x3 0x1
> +#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034 0x037C 0x0834 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034 0x037C 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034 0x037C 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034 0x037C 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034 0x037C 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038 0x0380 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038 0x0380 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038 0x0380 0x0820 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038 0x0380 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038 0x0380 0x0834 0x4 0x1
> +#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038 0x0380 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038 0x0380 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038 0x0380 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038 0x0380 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C 0x0384 0x0624 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C 0x0384 0x0828 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C 0x0384 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C 0x0384 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C 0x0384 0x070C 0x4 0x1
> +#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C 0x0384 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C 0x0384 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C 0x0384 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C 0x0384 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040 0x0388 0x085C 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040 0x0388 0x0824 0x1 0x2
> +#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040 0x0388 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040 0x0388 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040 0x0388 0x07EC 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040 0x0388 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040 0x0388 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040 0x0388 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040 0x0388 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044 0x038C 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044 0x038C 0x0000 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044 0x038C 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044 0x038C 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044 0x038C 0x07E8 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044 0x038C 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044 0x038C 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044 0x038C 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044 0x038C 0x0000 0x8 0x0
> +#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048 0x0390 0x0000 0x0 0x0
> +#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048 0x0390 0x0628 0x1 0x0
> +#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048 0x0390 0x0000 0x2 0x0
> +#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048 0x0390 0x0000 0x3 0x0
> +#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048 0x0390 0x07F0 0x4 0x0
> +#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048 0x0390 0x0000 0x5 0x0
> +#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048 0x0390 0x0000 0x6 0x0
> +#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048 0x0390 0x0000 0x7 0x0
> +#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048 0x0390 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C 0x0394 0x06A8 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C 0x0394 0x078C 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C 0x0394 0x0684 0x2 0x1
> +#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C 0x0394 0x07A8 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C 0x0394 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C 0x0394 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C 0x0394 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C 0x0394 0x0800 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C 0x0394 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C 0x0394 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050 0x0398 0x06AC 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050 0x0398 0x077C 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050 0x0398 0x0688 0x2 0x1
> +#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050 0x0398 0x07AC 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050 0x0398 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050 0x0398 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050 0x0398 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050 0x0398 0x0804 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050 0x0398 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050 0x0398 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054 0x039C 0x06B0 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054 0x039C 0x0788 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054 0x039C 0x067C 0x2 0x1
> +#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054 0x039C 0x07C8 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054 0x039C 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054 0x039C 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054 0x039C 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054 0x039C 0x07F4 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054 0x039C 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054 0x039C 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058 0x03A0 0x06B4 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058 0x03A0 0x0778 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058 0x03A0 0x0680 0x2 0x1
> +#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058 0x03A0 0x07D4 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058 0x03A0 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058 0x03A0 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058 0x03A0 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058 0x03A0 0x07FC 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058 0x03A0 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058 0x03A0 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C 0x03A4 0x06B8 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C 0x03A4 0x0794 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C 0x03A4 0x0000 0x2 0x0
> +#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C 0x03A4 0x07CC 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C 0x03A4 0x0858 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C 0x03A4 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C 0x03A4 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C 0x03A4 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C 0x03A4 0x0000 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C 0x03A4 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C 0x03A4 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060 0x03A8 0x06BC 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060 0x03A8 0x07A0 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060 0x03A8 0x0824 0x2 0x1
> +#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060 0x03A8 0x07D8 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060 0x03A8 0x0858 0x4 0x1
> +#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060 0x03A8 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060 0x03A8 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060 0x03A8 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060 0x03A8 0x0000 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060 0x03A8 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060 0x03A8 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064 0x03AC 0x06C0 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064 0x03AC 0x0798 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064 0x03AC 0x07C0 0x2 0x2
> +#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064 0x03AC 0x07D0 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064 0x03AC 0x0854 0x4 0x0
> +#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064 0x03AC 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064 0x03AC 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064 0x03AC 0x0000 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064 0x03AC 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064 0x03AC 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068 0x03B0 0x06C4 0x0 0x0
> +#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068 0x03B0 0x079C 0x1 0x1
> +#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068 0x03B0 0x07C4 0x2 0x2
> +#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068 0x03B0 0x07DC 0x3 0x0
> +#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068 0x03B0 0x0854 0x4 0x1
> +#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068 0x03B0 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068 0x03B0 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068 0x03B0 0x0000 0x7 0x0
> +#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068 0x03B0 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068 0x03B0 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C 0x03B4 0x0700 0x0 0x0
> +#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C 0x03B4 0x0790 0x1 0x1
> +#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C 0x03B4 0x0678 0x2 0x1
> +#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C 0x03B4 0x0844 0x3 0x2
> +#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C 0x03B4 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C 0x03B4 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C 0x03B4 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C 0x03B4 0x0000 0x7 0x0
> +#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C 0x03B4 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C 0x03B4 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070 0x03B8 0x0000 0x0 0x0
> +#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070 0x03B8 0x0784 0x1 0x1
> +#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070 0x03B8 0x0000 0x2 0x0
> +#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070 0x03B8 0x0848 0x3 0x2
> +#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070 0x03B8 0x0000 0x3 0x0
> +#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070 0x03B8 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070 0x03B8 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070 0x03B8 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070 0x03B8 0x070C 0x7 0x0
> +#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070 0x03B8 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070 0x03B8 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074 0x03BC 0x0704 0x0 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074 0x03BC 0x0780 0x1 0x1
> +#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074 0x03BC 0x0000 0x2 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074 0x03BC 0x0848 0x3 0x3
> +#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074 0x03BC 0x0000 0x3 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074 0x03BC 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074 0x03BC 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074 0x03BC 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074 0x03BC 0x0784 0x7 0x2
> +#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074 0x03BC 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074 0x03BC 0x0000 0x9 0x0
> +#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078 0x03C0 0x0708 0x0 0x0
> +#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078 0x03C0 0x07A4 0x1 0x1
> +#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078 0x03C0 0x0674 0x2 0x1
> +#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078 0x03C0 0x0844 0x3 0x3
> +#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078 0x03C0 0x0000 0x4 0x0
> +#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078 0x03C0 0x0000 0x5 0x0
> +#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078 0x03C0 0x0000 0x6 0x0
> +#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078 0x03C0 0x07F8 0x7 0x0
> +#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078 0x03C0 0x0000 0x8 0x0
> +#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078 0x03C0 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C 0x03C4 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C 0x03C4 0x0000 0x1 0x0
> +#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C 0x03C4 0x0654 0x2 0x1
> +#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C 0x03C4 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C 0x03C4 0x0828 0x4 0x1
> +#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C 0x03C4 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C 0x03C4 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C 0x03C4 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C 0x03C4 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C 0x03C4 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080 0x03C8 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080 0x03C8 0x0770 0x1 0x1
> +#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080 0x03C8 0x0648 0x2 0x1
> +#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080 0x03C8 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080 0x03C8 0x0000 0x4 0x0
> +#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080 0x03C8 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080 0x03C8 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080 0x03C8 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080 0x03C8 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080 0x03C8 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084 0x03CC 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084 0x03CC 0x0000 0x1 0x0
> +#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084 0x03CC 0x0638 0x2 0x1
> +#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084 0x03CC 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084 0x03CC 0x0000 0x4 0x0
> +#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084 0x03CC 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084 0x03CC 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084 0x03CC 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088 0x03D0 0x0764 0x0 0x1
> +#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088 0x03D0 0x0770 0x1 0x2
> +#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088 0x03D0 0x0000 0x2 0x0
> +#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088 0x03D0 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088 0x03D0 0x0000 0x4 0x0
> +#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088 0x03D0 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088 0x03D0 0x0860 0x6 0x1
> +#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088 0x03D0 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C 0x03D4 0x0768 0x0 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C 0x03D4 0x0000 0x1 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C 0x03D4 0x0658 0x2 0x1
> +#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C 0x03D4 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C 0x03D4 0x0000 0x4 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C 0x03D4 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C 0x03D4 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C 0x03D4 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C 0x03D4 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C 0x03D4 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090 0x03D8 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090 0x03D8 0x0760 0x1 0x1
> +#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090 0x03D8 0x0644 0x2 0x1
> +#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090 0x03D8 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090 0x03D8 0x0000 0x4 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090 0x03D8 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090 0x03D8 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090 0x03D8 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090 0x03D8 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090 0x03D8 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094 0x03DC 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094 0x03DC 0x0000 0x1 0x0
> +#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094 0x03DC 0x064C 0x2 0x1
> +#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094 0x03DC 0x0830 0x3 0x2
> +#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094 0x03DC 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094 0x03DC 0x0824 0x4 0x3
> +#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094 0x03DC 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094 0x03DC 0x0624 0x6 0x1
> +#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094 0x03DC 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094 0x03DC 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094 0x03DC 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098 0x03E0 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098 0x03E0 0x0764 0x1 0x2
> +#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098 0x03E0 0x0650 0x2 0x1
> +#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098 0x03E0 0x0830 0x3 0x3
> +#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098 0x03E0 0x0000 0x3 0x0
> +#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098 0x03E0 0x07F0 0x4 0x1
> +#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098 0x03E0 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098 0x03E0 0x0628 0x6 0x1
> +#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098 0x03E0 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098 0x03E0 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098 0x03E0 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C 0x03E4 0x0774 0x0 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C 0x03E4 0x0000 0x1 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C 0x03E4 0x07B8 0x2 0x1
> +#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C 0x03E4 0x082C 0x3 0x2
> +#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C 0x03E4 0x07EC 0x4 0x1
> +#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C 0x03E4 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C 0x03E4 0x085C 0x6 0x1
> +#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C 0x03E4 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C 0x03E4 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C 0x03E4 0x0000 0x9 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0 0x03E8 0x0000 0x0 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0 0x03E8 0x076C 0x1 0x1
> +#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0 0x03E8 0x07BC 0x2 0x1
> +#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0 0x03E8 0x082C 0x3 0x3
> +#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0 0x03E8 0x07E8 0x4 0x1
> +#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0 0x03E8 0x0000 0x5 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0 0x03E8 0x0000 0x6 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0 0x03E8 0x0000 0x7 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0 0x03E8 0x0000 0x8 0x0
> +#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0 0x03E8 0x0000 0x9 0x0
> +#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4 0x03EC 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4 0x03EC 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4 0x03EC 0x0854 0x2 0x2
> +#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4 0x03EC 0x0710 0x3 0x0
> +#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4 0x03EC 0x066C 0x4 0x0
> +#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4 0x03EC 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4 0x03EC 0x0820 0x6 0x1
> +#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4 0x03EC 0x0814 0x7 0x0
> +#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4 0x03EC 0x0000 0x8 0x0
> +#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8 0x03F0 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8 0x03F0 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8 0x03F0 0x0858 0x2 0x2
> +#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8 0x03F0 0x0000 0x2 0x0
> +#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8 0x03F0 0x0714 0x3 0x0
> +#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8 0x03F0 0x0670 0x4 0x0
> +#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8 0x03F0 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8 0x03F0 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8 0x03F0 0x0818 0x7 0x0
> +#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC 0x03F4 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC 0x03F4 0x0874 0x1 0x1
> +#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC 0x03F4 0x084C 0x2 0x2
> +#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC 0x03F4 0x0000 0x3 0x0
> +#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC 0x03F4 0x0000 0x4 0x0
> +#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC 0x03F4 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC 0x03F4 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC 0x03F4 0x0000 0x7 0x0
> +#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0 0x03F8 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0 0x03F8 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0 0x03F8 0x0850 0x2 0x2
> +#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0 0x03F8 0x0000 0x2 0x0
> +#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0 0x03F8 0x0000 0x3 0x0
> +#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0 0x03F8 0x0000 0x4 0x0
> +#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0 0x03F8 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0 0x03F8 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0 0x03F8 0x0000 0x7 0x0
> +#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4 0x03FC 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4 0x03FC 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4 0x03FC 0x07B8 0x2 0x2
> +#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4 0x03FC 0x0000 0x3 0x0
> +#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4 0x03FC 0x0664 0x4 0x0
> +#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4 0x03FC 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4 0x03FC 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4 0x03FC 0x0808 0x7 0x0
> +#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8 0x0400 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8 0x0400 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8 0x0400 0x0854 0x2 0x3
> +#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8 0x0400 0x0718 0x3 0x0
> +#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8 0x0400 0x0660 0x4 0x0
> +#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8 0x0400 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8 0x0400 0x081C 0x6 0x1
> +#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8 0x0400 0x0000 0x7 0x0
> +#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8 0x0400 0x0000 0x8 0x0
> +#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC 0x0404 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC 0x0404 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC 0x0404 0x0858 0x2 0x3
> +#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC 0x0404 0x0000 0x2 0x0
> +#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC 0x0404 0x071C 0x3 0x0
> +#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC 0x0404 0x065C 0x4 0x0
> +#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC 0x0404 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC 0x0404 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC 0x0404 0x080C 0x7 0x0
> +#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC 0x0404 0x0000 0x8 0x0
> +#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0 0x0408 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0 0x0408 0x0878 0x1 0x1
> +#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0 0x0408 0x084C 0x2 0x3
> +#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0 0x0408 0x068C 0x3 0x1
> +#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0 0x0408 0x0694 0x4 0x1
> +#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0 0x0408 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0 0x0408 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0 0x0408 0x0000 0x7 0x0
> +#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4 0x040C 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4 0x040C 0x0000 0x1 0x0
> +#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4 0x040C 0x0850 0x2 0x3
> +#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4 0x040C 0x0000 0x2 0x0
> +#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4 0x040C 0x0690 0x3 0x1
> +#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4 0x040C 0x0698 0x4 0x1
> +#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4 0x040C 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4 0x040C 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4 0x040C 0x0000 0x7 0x0
> +#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8 0x0410 0x0000 0x0 0x0
> +#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8 0x0410 0x0770 0x1 0x3
> +#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8 0x0410 0x07BC 0x2 0x2
> +#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8 0x0410 0x0000 0x3 0x0
> +#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8 0x0410 0x0668 0x4 0x0
> +#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8 0x0410 0x0000 0x5 0x0
> +#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8 0x0410 0x0000 0x6 0x0
> +#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8 0x0410 0x0810 0x7 0x0
> +#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC 0x0414 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC 0x0414 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC 0x0414 0x0634 0x2 0x1
> +#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC 0x0414 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC 0x0414 0x06DC 0x4 0x0
> +#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC 0x0414 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC 0x0414 0x0868 0x6 0x0
> +#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC 0x0414 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC 0x0414 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC 0x0414 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0 0x0418 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0 0x0418 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0 0x0418 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0 0x0418 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0 0x0418 0x06EC 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0 0x0418 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0 0x0418 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0 0x0418 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0 0x0418 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0 0x0418 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4 0x041C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4 0x041C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4 0x041C 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4 0x041C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4 0x041C 0x06F0 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4 0x041C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4 0x041C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4 0x041C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4 0x041C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4 0x041C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8 0x0420 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8 0x0420 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8 0x0420 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8 0x0420 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8 0x0420 0x06F4 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8 0x0420 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8 0x0420 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8 0x0420 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8 0x0420 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8 0x0420 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC 0x0424 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC 0x0424 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC 0x0424 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC 0x0424 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC 0x0424 0x06F8 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC 0x0424 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC 0x0424 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC 0x0424 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC 0x0424 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC 0x0424 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0 0x0428 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0 0x0428 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0 0x0428 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0 0x0428 0x0708 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0 0x0428 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0 0x0428 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0 0x0428 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0 0x0428 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0 0x0428 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4 0x042C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4 0x042C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4 0x042C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4 0x042C 0x0700 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4 0x042C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4 0x042C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4 0x042C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4 0x042C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4 0x042C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8 0x0430 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8 0x0430 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8 0x0430 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8 0x0430 0x0704 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8 0x0430 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8 0x0430 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8 0x0430 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8 0x0430 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8 0x0430 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC 0x0434 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC 0x0434 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC 0x0434 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC 0x0434 0x0000 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC 0x0434 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC 0x0434 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC 0x0434 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC 0x0434 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC 0x0434 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0 0x0438 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0 0x0438 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0 0x0438 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0 0x0438 0x06C4 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0 0x0438 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0 0x0438 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0 0x0438 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0 0x0438 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0 0x0438 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4 0x043C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4 0x043C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4 0x043C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4 0x043C 0x06C0 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4 0x043C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4 0x043C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4 0x043C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4 0x043C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4 0x043C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8 0x0440 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8 0x0440 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8 0x0440 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8 0x0440 0x06BC 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8 0x0440 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8 0x0440 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8 0x0440 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8 0x0440 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8 0x0440 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC 0x0444 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC 0x0444 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC 0x0444 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC 0x0444 0x06B8 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC 0x0444 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC 0x0444 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC 0x0444 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC 0x0444 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC 0x0444 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100 0x0448 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100 0x0448 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100 0x0448 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100 0x0448 0x06B4 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100 0x0448 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100 0x0448 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100 0x0448 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100 0x0448 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100 0x0448 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104 0x044C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104 0x044C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104 0x044C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104 0x044C 0x06B0 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104 0x044C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104 0x044C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104 0x044C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104 0x044C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104 0x044C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108 0x0450 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108 0x0450 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108 0x0450 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108 0x0450 0x06AC 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108 0x0450 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108 0x0450 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108 0x0450 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108 0x0450 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108 0x0450 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C 0x0454 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C 0x0454 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C 0x0454 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C 0x0454 0x06A8 0x4 0x1
> +#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C 0x0454 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C 0x0454 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C 0x0454 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C 0x0454 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C 0x0454 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110 0x0458 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110 0x0458 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110 0x0458 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110 0x0458 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110 0x0458 0x06A4 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110 0x0458 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110 0x0458 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110 0x0458 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110 0x0458 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110 0x0458 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114 0x045C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114 0x045C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114 0x045C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114 0x045C 0x06A0 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114 0x045C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114 0x045C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114 0x045C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114 0x045C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114 0x045C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118 0x0460 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118 0x0460 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118 0x0460 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118 0x0460 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118 0x0460 0x06D8 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118 0x0460 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118 0x0460 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118 0x0460 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118 0x0460 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118 0x0460 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C 0x0464 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C 0x0464 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C 0x0464 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C 0x0464 0x06D4 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C 0x0464 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C 0x0464 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C 0x0464 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C 0x0464 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C 0x0464 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120 0x0468 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120 0x0468 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120 0x0468 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120 0x0468 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120 0x0468 0x06D0 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120 0x0468 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120 0x0468 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120 0x0468 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120 0x0468 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120 0x0468 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124 0x046C 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124 0x046C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124 0x046C 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124 0x046C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124 0x046C 0x06CC 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124 0x046C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124 0x046C 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124 0x046C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124 0x046C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124 0x046C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128 0x0470 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128 0x0470 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128 0x0470 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128 0x0470 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128 0x0470 0x06C8 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128 0x0470 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128 0x0470 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128 0x0470 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128 0x0470 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128 0x0470 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C 0x0474 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C 0x0474 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C 0x0474 0x0000 0x2 0x0
> +#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C 0x0474 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C 0x0474 0x06FC 0x4 0x0
> +#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C 0x0474 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C 0x0474 0x0000 0x6 0x0
> +#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C 0x0474 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C 0x0474 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C 0x0474 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130 0x0478 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130 0x0478 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130 0x0478 0x063C 0x2 0x1
> +#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130 0x0478 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130 0x0478 0x06E0 0x4 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130 0x0478 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130 0x0478 0x0864 0x6 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130 0x0478 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130 0x0478 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130 0x0478 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134 0x047C 0x07E0 0x0 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134 0x047C 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134 0x047C 0x0630 0x2 0x1
> +#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134 0x047C 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134 0x047C 0x06E4 0x4 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134 0x047C 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134 0x047C 0x0870 0x6 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134 0x047C 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134 0x047C 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134 0x047C 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138 0x0480 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138 0x0480 0x0000 0x1 0x0
> +#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138 0x0480 0x062C 0x2 0x1
> +#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138 0x0480 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138 0x0480 0x0000 0x4 0x0
> +#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138 0x0480 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138 0x0480 0x069C 0x6 0x0
> +#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138 0x0480 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138 0x0480 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138 0x0480 0x0000 0x9 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C 0x0484 0x0000 0x0 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C 0x0484 0x07E0 0x1 0x1
> +#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C 0x0484 0x0640 0x2 0x1
> +#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C 0x0484 0x0000 0x3 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C 0x0484 0x06E8 0x4 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C 0x0484 0x0000 0x5 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C 0x0484 0x086C 0x6 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C 0x0484 0x0000 0x7 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C 0x0484 0x0000 0x8 0x0
> +#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C 0x0484 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140 0x0488 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140 0x0488 0x07BC 0x1 0x0
> +#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140 0x0488 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140 0x0488 0x072C 0x3 0x0
> +#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140 0x0488 0x079C 0x4 0x0
> +#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140 0x0488 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140 0x0488 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140 0x0488 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140 0x0488 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140 0x0488 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144 0x048C 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144 0x048C 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144 0x048C 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144 0x048C 0x0654 0x3 0x0
> +#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144 0x048C 0x078C 0x4 0x0
> +#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144 0x048C 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144 0x048C 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144 0x048C 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144 0x048C 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144 0x048C 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148 0x0490 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148 0x0490 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148 0x0490 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148 0x0490 0x0648 0x3 0x0
> +#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148 0x0490 0x0790 0x4 0x0
> +#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148 0x0490 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148 0x0490 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148 0x0490 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148 0x0490 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148 0x0490 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C 0x0494 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C 0x0494 0x07B8 0x1 0x0
> +#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C 0x0494 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C 0x0494 0x0720 0x3 0x0
> +#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C 0x0494 0x0798 0x4 0x0
> +#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C 0x0494 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C 0x0494 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C 0x0494 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C 0x0494 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C 0x0494 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150 0x0498 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150 0x0498 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150 0x0498 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150 0x0498 0x0754 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150 0x0498 0x0788 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150 0x0498 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150 0x0498 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150 0x0498 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150 0x0498 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150 0x0498 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154 0x049C 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154 0x049C 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154 0x049C 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154 0x049C 0x0758 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154 0x049C 0x0778 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154 0x049C 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154 0x049C 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154 0x049C 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154 0x049C 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154 0x049C 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158 0x04A0 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158 0x04A0 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158 0x04A0 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158 0x04A0 0x0750 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158 0x04A0 0x0784 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158 0x04A0 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158 0x04A0 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158 0x04A0 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158 0x04A0 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158 0x04A0 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C 0x04A4 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C 0x04A4 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C 0x04A4 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C 0x04A4 0x075C 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C 0x04A4 0x0780 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C 0x04A4 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C 0x04A4 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C 0x04A4 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C 0x04A4 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C 0x04A4 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160 0x04A8 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160 0x04A8 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160 0x04A8 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160 0x04A8 0x083C 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160 0x04A8 0x0650 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160 0x04A8 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160 0x04A8 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160 0x04A8 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160 0x04A8 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160 0x04A8 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164 0x04AC 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164 0x04AC 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164 0x04AC 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164 0x04AC 0x083C 0x3 0x1
> +#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164 0x04AC 0x064C 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164 0x04AC 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164 0x04AC 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164 0x04AC 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164 0x04AC 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164 0x04AC 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168 0x04B0 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168 0x04B0 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168 0x04B0 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168 0x04B0 0x0840 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168 0x04B0 0x0000 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168 0x04B0 0x0000 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168 0x04B0 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168 0x04B0 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168 0x04B0 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168 0x04B0 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168 0x04B0 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C 0x04B4 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C 0x04B4 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C 0x04B4 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C 0x04B4 0x0840 0x3 0x1
> +#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C 0x04B4 0x0000 0x3 0x0
> +#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C 0x04B4 0x0000 0x4 0x0
> +#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C 0x04B4 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C 0x04B4 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C 0x04B4 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C 0x04B4 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C 0x04B4 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170 0x04B8 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170 0x04B8 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170 0x04B8 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170 0x04B8 0x0658 0x3 0x0
> +#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170 0x04B8 0x077C 0x4 0x0
> +#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170 0x04B8 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170 0x04B8 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170 0x04B8 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170 0x04B8 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170 0x04B8 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174 0x04BC 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174 0x04BC 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174 0x04BC 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174 0x04BC 0x0724 0x3 0x0
> +#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174 0x04BC 0x0794 0x4 0x0
> +#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174 0x04BC 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174 0x04BC 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174 0x04BC 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174 0x04BC 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174 0x04BC 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178 0x04C0 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178 0x04C0 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178 0x04C0 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178 0x04C0 0x0644 0x3 0x0
> +#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178 0x04C0 0x07A4 0x4 0x0
> +#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178 0x04C0 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178 0x04C0 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178 0x04C0 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178 0x04C0 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178 0x04C0 0x0000 0x9 0x0
> +#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C 0x04C4 0x0000 0x0 0x0
> +#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C 0x04C4 0x0000 0x1 0x0
> +#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C 0x04C4 0x0000 0x2 0x0
> +#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C 0x04C4 0x0728 0x3 0x0
> +#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C 0x04C4 0x07A0 0x4 0x0
> +#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C 0x04C4 0x0000 0x5 0x0
> +#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C 0x04C4 0x0000 0x6 0x0
> +#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C 0x04C4 0x0000 0x7 0x0
> +#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C 0x04C4 0x0000 0x8 0x0
> +#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C 0x04C4 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180 0x04C8 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180 0x04C8 0x085C 0x1 0x2
> +#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180 0x04C8 0x0718 0x2 0x1
> +#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180 0x04C8 0x07A0 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180 0x04C8 0x06D4 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180 0x04C8 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180 0x04C8 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180 0x04C8 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180 0x04C8 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184 0x04CC 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184 0x04CC 0x0624 0x1 0x2
> +#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184 0x04CC 0x0714 0x2 0x1
> +#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184 0x04CC 0x0794 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184 0x04CC 0x06D0 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184 0x04CC 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184 0x04CC 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184 0x04CC 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184 0x04CC 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188 0x04D0 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188 0x04D0 0x0000 0x1 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188 0x04D0 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188 0x04D0 0x078C 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188 0x04D0 0x06CC 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188 0x04D0 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188 0x04D0 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188 0x04D0 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188 0x04D0 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C 0x04D4 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C 0x04D4 0x0860 0x1 0x2
> +#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C 0x04D4 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C 0x04D4 0x0790 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C 0x04D4 0x06C8 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C 0x04D4 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C 0x04D4 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C 0x04D4 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C 0x04D4 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190 0x04D8 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190 0x04D8 0x0000 0x1 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190 0x04D8 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190 0x04D8 0x0758 0x3 0x1
> +#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190 0x04D8 0x06D8 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190 0x04D8 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190 0x04D8 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190 0x04D8 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190 0x04D8 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194 0x04DC 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194 0x04DC 0x0628 0x1 0x2
> +#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194 0x04DC 0x0710 0x2 0x1
> +#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194 0x04DC 0x0798 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194 0x04DC 0x06A4 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194 0x04DC 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194 0x04DC 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194 0x04DC 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194 0x04DC 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198 0x04E0 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198 0x04E0 0x0000 0x1 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198 0x04E0 0x071C 0x2 0x1
> +#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198 0x04E0 0x079C 0x3 0x2
> +#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198 0x04E0 0x06A0 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198 0x04E0 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198 0x04E0 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198 0x04E0 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198 0x04E0 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C 0x04E4 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C 0x04E4 0x068C 0x1 0x2
> +#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C 0x04E4 0x0694 0x2 0x2
> +#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C 0x04E4 0x0754 0x3 0x1
> +#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C 0x04E4 0x06FC 0x4 0x1
> +#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C 0x04E4 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C 0x04E4 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C 0x04E4 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C 0x04E4 0x0000 0x9 0x0
> +#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0 0x04E8 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0 0x04E8 0x083C 0x1 0x4
> +#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0 0x04E8 0x0738 0x2 0x1
> +#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0 0x04E8 0x0778 0x3 0x2
> +#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0 0x04E8 0x06F4 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0 0x04E8 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0 0x04E8 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0 0x04E8 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4 0x04EC 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4 0x04EC 0x083C 0x1 0x5
> +#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4 0x04EC 0x0734 0x2 0x1
> +#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4 0x04EC 0x0788 0x3 0x2
> +#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4 0x04EC 0x06F0 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4 0x04EC 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4 0x04EC 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4 0x04EC 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8 0x04F0 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8 0x04F0 0x07B4 0x1 0x2
> +#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8 0x04F0 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8 0x04F0 0x07A4 0x3 0x2
> +#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8 0x04F0 0x06EC 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8 0x04F0 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8 0x04F0 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8 0x04F0 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC 0x04F4 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC 0x04F4 0x07B0 0x1 0x2
> +#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC 0x04F4 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC 0x04F4 0x077C 0x3 0x2
> +#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC 0x04F4 0x06E8 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC 0x04F4 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC 0x04F4 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC 0x04F4 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0 0x04F8 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0 0x04F8 0x0000 0x1 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0 0x04F8 0x0000 0x2 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0 0x04F8 0x075C 0x3 0x1
> +#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0 0x04F8 0x06F8 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0 0x04F8 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0 0x04F8 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0 0x04F8 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4 0x04FC 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4 0x04FC 0x0840 0x1 0x4
> +#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4 0x04FC 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4 0x04FC 0x0730 0x2 0x1
> +#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4 0x04FC 0x0780 0x3 0x2
> +#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4 0x04FC 0x06DC 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4 0x04FC 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4 0x04FC 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4 0x04FC 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8 0x0500 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8 0x0500 0x0840 0x1 0x5
> +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8 0x0500 0x0000 0x1 0x0
> +#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8 0x0500 0x073C 0x2 0x1
> +#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8 0x0500 0x0784 0x3 0x3
> +#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8 0x0500 0x06E0 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8 0x0500 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8 0x0500 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8 0x0500 0x0000 0x7 0x0
> +#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC 0x0504 0x0000 0x0 0x0
> +#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC 0x0504 0x0690 0x1 0x2
> +#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC 0x0504 0x0698 0x2 0x2
> +#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC 0x0504 0x0750 0x3 0x1
> +#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC 0x0504 0x06E4 0x4 0x1
> +#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC 0x0504 0x0000 0x5 0x0
> +#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC 0x0504 0x0000 0x6 0x0
> +#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC 0x0504 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0 0x0508 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0 0x0508 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0 0x0508 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0 0x0508 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0 0x0508 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0 0x0508 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4 0x050C 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4 0x050C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4 0x050C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4 0x050C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4 0x050C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4 0x050C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8 0x0510 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8 0x0510 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8 0x0510 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8 0x0510 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8 0x0510 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8 0x0510 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC 0x0514 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC 0x0514 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC 0x0514 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC 0x0514 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC 0x0514 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC 0x0514 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0 0x0518 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0 0x0518 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0 0x0518 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0 0x0518 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0 0x0518 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0 0x0518 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4 0x051C 0x0768 0x0 0x1
> +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4 0x051C 0x0000 0x1 0x0
> +#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4 0x051C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4 0x051C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4 0x051C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4 0x051C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4 0x051C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8 0x0520 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8 0x0520 0x0810 0x2 0x1
> +#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8 0x0520 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8 0x0520 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8 0x0520 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8 0x0520 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8 0x0520 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC 0x0524 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC 0x0524 0x0808 0x2 0x1
> +#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC 0x0524 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC 0x0524 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC 0x0524 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC 0x0524 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC 0x0524 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0 0x0528 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0 0x0528 0x0818 0x2 0x1
> +#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0 0x0528 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0 0x0528 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0 0x0528 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0 0x0528 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0 0x0528 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4 0x052C 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4 0x052C 0x0814 0x2 0x1
> +#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4 0x052C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4 0x052C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4 0x052C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4 0x052C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4 0x052C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8 0x0530 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8 0x0530 0x080C 0x2 0x1
> +#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8 0x0530 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8 0x0530 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8 0x0530 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8 0x0530 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8 0x0530 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC 0x0534 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC 0x0534 0x0000 0x1 0x0
> +#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC 0x0534 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC 0x0534 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC 0x0534 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC 0x0534 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC 0x0534 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC 0x0534 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0 0x0538 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0 0x0538 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0 0x0538 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0 0x0538 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0 0x0538 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0 0x0538 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0 0x0538 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4 0x053C 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4 0x053C 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4 0x053C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4 0x053C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4 0x053C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4 0x053C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4 0x053C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8 0x0540 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8 0x0540 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8 0x0540 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8 0x0540 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8 0x0540 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8 0x0540 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8 0x0540 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC 0x0544 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC 0x0544 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC 0x0544 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC 0x0544 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC 0x0544 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC 0x0544 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC 0x0544 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200 0x0548 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200 0x0548 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200 0x0548 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200 0x0548 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200 0x0548 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200 0x0548 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204 0x054C 0x0774 0x0 0x1
> +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204 0x054C 0x0000 0x1 0x0
> +#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204 0x054C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204 0x054C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204 0x054C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204 0x054C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204 0x054C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208 0x0550 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208 0x0550 0x07FC 0x2 0x1
> +#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208 0x0550 0x0000 0x3 0x0
> +#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208 0x0550 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208 0x0550 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208 0x0550 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208 0x0550 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208 0x0550 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C 0x0554 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C 0x0554 0x07F4 0x2 0x1
> +#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C 0x0554 0x0000 0x3 0x0
> +#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C 0x0554 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C 0x0554 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C 0x0554 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C 0x0554 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C 0x0554 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210 0x0558 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210 0x0558 0x0804 0x2 0x1
> +#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210 0x0558 0x0000 0x3 0x0
> +#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210 0x0558 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210 0x0558 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210 0x0558 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210 0x0558 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210 0x0558 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214 0x055C 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214 0x055C 0x0800 0x2 0x1
> +#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214 0x055C 0x0000 0x3 0x0
> +#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214 0x055C 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214 0x055C 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214 0x055C 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214 0x055C 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214 0x055C 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218 0x0560 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218 0x0560 0x07F8 0x2 0x1
> +#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218 0x0560 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218 0x0560 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218 0x0560 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218 0x0560 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218 0x0560 0x0000 0x9 0x0
> +#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C 0x0564 0x0000 0x0 0x0
> +#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C 0x0564 0x0000 0x1 0x0
> +#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C 0x0564 0x0000 0x2 0x0
> +#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C 0x0564 0x0000 0x5 0x0
> +#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C 0x0564 0x0000 0x6 0x0
> +#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C 0x0564 0x0000 0x7 0x0
> +#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C 0x0564 0x0000 0x8 0x0
> +#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C 0x0564 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220 0x0568 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220 0x0568 0x0668 0x1 0x1
> +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220 0x0568 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220 0x0568 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220 0x0568 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220 0x0568 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220 0x0568 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220 0x0568 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220 0x0568 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220 0x0568 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224 0x056C 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224 0x056C 0x0664 0x1 0x1
> +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224 0x056C 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224 0x056C 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224 0x056C 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224 0x056C 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224 0x056C 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224 0x056C 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224 0x056C 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224 0x056C 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228 0x0570 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228 0x0570 0x065C 0x1 0x1
> +#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228 0x0570 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228 0x0570 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228 0x0570 0x0838 0x4 0x2
> +#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228 0x0570 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228 0x0570 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228 0x0570 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228 0x0570 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228 0x0570 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228 0x0570 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C 0x0574 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C 0x0574 0x066C 0x1 0x1
> +#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C 0x0574 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C 0x0574 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C 0x0574 0x0838 0x4 0x3
> +#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C 0x0574 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C 0x0574 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C 0x0574 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C 0x0574 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C 0x0574 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C 0x0574 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230 0x0578 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230 0x0578 0x0670 0x1 0x1
> +#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230 0x0578 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230 0x0578 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230 0x0578 0x0834 0x4 0x2
> +#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230 0x0578 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230 0x0578 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230 0x0578 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230 0x0578 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234 0x057C 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234 0x057C 0x0660 0x1 0x1
> +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234 0x057C 0x065C 0x2 0x2
> +#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234 0x057C 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234 0x057C 0x0834 0x4 0x3
> +#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234 0x057C 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234 0x057C 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234 0x057C 0x069C 0x7 0x2
> +#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234 0x057C 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238 0x0580 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238 0x0580 0x0680 0x1 0x2
> +#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238 0x0580 0x07C8 0x2 0x1
> +#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238 0x0580 0x0740 0x3 0x1
> +#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238 0x0580 0x07F0 0x4 0x2
> +#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238 0x0580 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238 0x0580 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238 0x0580 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238 0x0580 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238 0x0580 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C 0x0584 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C 0x0584 0x067C 0x1 0x2
> +#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C 0x0584 0x07D4 0x2 0x1
> +#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C 0x0584 0x0748 0x3 0x1
> +#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C 0x0584 0x07E8 0x4 0x2
> +#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C 0x0584 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C 0x0584 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C 0x0584 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C 0x0584 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C 0x0584 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240 0x0588 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240 0x0588 0x0674 0x1 0x2
> +#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240 0x0588 0x07DC 0x2 0x1
> +#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240 0x0588 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240 0x0588 0x07C4 0x4 0x3
> +#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240 0x0588 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240 0x0588 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240 0x0588 0x0848 0x7 0x4
> +#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240 0x0588 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240 0x0588 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240 0x0588 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244 0x058C 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244 0x058C 0x0684 0x1 0x2
> +#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244 0x058C 0x07D0 0x2 0x1
> +#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244 0x058C 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244 0x058C 0x07C0 0x4 0x3
> +#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244 0x058C 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244 0x058C 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244 0x058C 0x0848 0x7 0x5
> +#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244 0x058C 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244 0x058C 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244 0x058C 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248 0x0590 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248 0x0590 0x0688 0x1 0x2
> +#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248 0x0590 0x07D8 0x2 0x1
> +#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248 0x0590 0x074C 0x3 0x1
> +#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248 0x0590 0x081C 0x4 0x2
> +#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248 0x0590 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248 0x0590 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248 0x0590 0x0858 0x7 0x4
> +#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248 0x0590 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248 0x0590 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248 0x0590 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C 0x0594 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C 0x0594 0x0678 0x1 0x2
> +#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C 0x0594 0x07CC 0x2 0x1
> +#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C 0x0594 0x0744 0x3 0x1
> +#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C 0x0594 0x07EC 0x4 0x2
> +#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C 0x0594 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C 0x0594 0x0824 0x6 0x4
> +#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C 0x0594 0x0858 0x7 0x5
> +#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C 0x0594 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C 0x0594 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C 0x0594 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250 0x0598 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250 0x0598 0x0844 0x1 0x0
> +#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250 0x0598 0x0740 0x2 0x0
> +#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250 0x0598 0x0680 0x3 0x0
> +#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250 0x0598 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250 0x0598 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250 0x0598 0x07E4 0x6 0x0
> +#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250 0x0598 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250 0x0598 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254 0x059C 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254 0x059C 0x0848 0x1 0x0
> +#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254 0x059C 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254 0x059C 0x0748 0x2 0x0
> +#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254 0x059C 0x067C 0x3 0x0
> +#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254 0x059C 0x07E4 0x4 0x1
> +#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254 0x059C 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254 0x059C 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254 0x059C 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254 0x059C 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258 0x05A0 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258 0x05A0 0x07C0 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258 0x05A0 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258 0x05A0 0x0674 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258 0x05A0 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258 0x05A0 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258 0x05A0 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258 0x05A0 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258 0x05A0 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258 0x05A0 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C 0x05A4 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C 0x05A4 0x07C4 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C 0x05A4 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C 0x05A4 0x0684 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C 0x05A4 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C 0x05A4 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C 0x05A4 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C 0x05A4 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C 0x05A4 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C 0x05A4 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260 0x05A8 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260 0x05A8 0x0844 0x1 0x1
> +#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260 0x05A8 0x074C 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260 0x05A8 0x0688 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260 0x05A8 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260 0x05A8 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260 0x05A8 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260 0x05A8 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260 0x05A8 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260 0x05A8 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264 0x05AC 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264 0x05AC 0x0848 0x1 0x1
> +#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264 0x05AC 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264 0x05AC 0x0744 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264 0x05AC 0x0678 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264 0x05AC 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264 0x05AC 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264 0x05AC 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264 0x05AC 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264 0x05AC 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264 0x05AC 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268 0x05B0 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268 0x05B0 0x0690 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268 0x05B0 0x0698 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268 0x05B0 0x0840 0x3 0x2
> +#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268 0x05B0 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268 0x05B0 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268 0x05B0 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268 0x05B0 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268 0x05B0 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268 0x05B0 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268 0x05B0 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C 0x05B4 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C 0x05B4 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C 0x05B4 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C 0x05B4 0x0840 0x3 0x3
> +#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C 0x05B4 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C 0x05B4 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C 0x05B4 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C 0x05B4 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C 0x05B4 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C 0x05B4 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C 0x05B4 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270 0x05B8 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270 0x05B8 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270 0x05B8 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270 0x05B8 0x083C 0x3 0x2
> +#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270 0x05B8 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270 0x05B8 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270 0x05B8 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270 0x05B8 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270 0x05B8 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270 0x05B8 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274 0x05BC 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274 0x05BC 0x068C 0x1 0x0
> +#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274 0x05BC 0x0694 0x2 0x0
> +#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274 0x05BC 0x083C 0x3 0x3
> +#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274 0x05BC 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274 0x05BC 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274 0x05BC 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274 0x05BC 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274 0x05BC 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274 0x05BC 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278 0x05C0 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278 0x05C0 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278 0x05C0 0x0724 0x2 0x1
> +#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278 0x05C0 0x0638 0x3 0x0
> +#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278 0x05C0 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278 0x05C0 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278 0x05C0 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278 0x05C0 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278 0x05C0 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278 0x05C0 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C 0x05C4 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C 0x05C4 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C 0x05C4 0x0728 0x2 0x1
> +#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C 0x05C4 0x0634 0x3 0x0
> +#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C 0x05C4 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C 0x05C4 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C 0x05C4 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C 0x05C4 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C 0x05C4 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C 0x05C4 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280 0x05C8 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280 0x05C8 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280 0x05C8 0x072C 0x2 0x1
> +#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280 0x05C8 0x062C 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280 0x05C8 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280 0x05C8 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280 0x05C8 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280 0x05C8 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280 0x05C8 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280 0x05C8 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284 0x05CC 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284 0x05CC 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284 0x05CC 0x0720 0x2 0x1
> +#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284 0x05CC 0x063C 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284 0x05CC 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284 0x05CC 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284 0x05CC 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284 0x05CC 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284 0x05CC 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284 0x05CC 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288 0x05D0 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288 0x05D0 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288 0x05D0 0x07B4 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288 0x05D0 0x0640 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288 0x05D0 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288 0x05D0 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288 0x05D0 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288 0x05D0 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288 0x05D0 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288 0x05D0 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C 0x05D4 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C 0x05D4 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C 0x05D4 0x07B0 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C 0x05D4 0x0630 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C 0x05D4 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C 0x05D4 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C 0x05D4 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C 0x05D4 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C 0x05D4 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C 0x05D4 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290 0x05D8 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290 0x05D8 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290 0x05D8 0x0850 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290 0x05D8 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290 0x05D8 0x0730 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290 0x05D8 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290 0x05D8 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290 0x05D8 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290 0x05D8 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290 0x05D8 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290 0x05D8 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294 0x05DC 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294 0x05DC 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294 0x05DC 0x0850 0x2 0x1
> +#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294 0x05DC 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294 0x05DC 0x0738 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294 0x05DC 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294 0x05DC 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294 0x05DC 0x0824 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294 0x05DC 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294 0x05DC 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294 0x05DC 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298 0x05E0 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298 0x05E0 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298 0x05E0 0x084C 0x2 0x0
> +#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298 0x05E0 0x0734 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298 0x05E0 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298 0x05E0 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298 0x05E0 0x0878 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298 0x05E0 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298 0x05E0 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298 0x05E0 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C 0x05E4 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C 0x05E4 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C 0x05E4 0x084C 0x2 0x1
> +#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C 0x05E4 0x073C 0x3 0x0
> +#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C 0x05E4 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C 0x05E4 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C 0x05E4 0x0874 0x6 0x0
> +#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C 0x05E4 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C 0x05E4 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C 0x05E4 0x0000 0x9 0x0
> +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0 0x05E8 0x0000 0x0 0x0
> +#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0 0x05E8 0x0000 0x1 0x0
> +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0 0x05E8 0x0000 0x2 0x0
> +#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0 0x05E8 0x0000 0x3 0x0
> +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0 0x05E8 0x0000 0x4 0x0
> +#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0 0x05E8 0x0000 0x5 0x0
> +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0 0x05E8 0x0000 0x6 0x0
> +#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0 0x05E8 0x0000 0x7 0x0
> +#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0 0x05E8 0x0000 0x8 0x0
> +#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0 0x05E8 0x0000 0x9 0x0
> +#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4 0x05EC 0x0000 0x0 0x0
> +#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4 0x05EC 0x0000 0x1 0x0
> +#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4 0x05EC 0x0000 0x2 0x0
> +#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4 0x05EC 0x07C4 0x3 0x1
> +#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4 0x05EC 0x0000 0x4 0x0
> +#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4 0x05EC 0x0000 0x5 0x0
> +#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8 0x05F0 0x0000 0x0 0x0
> +#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8 0x05F0 0x0000 0x1 0x0
> +#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8 0x05F0 0x0000 0x2 0x0
> +#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8 0x05F0 0x07C0 0x3 0x1
> +#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8 0x05F0 0x0000 0x4 0x0
> +#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8 0x05F0 0x0000 0x5 0x0
> +
> +#endif /* __DTS_IMX6SX_PINFUNC_H */
> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
> index be361b7..fc1825c7 100644
> --- a/drivers/pinctrl/Kconfig
> +++ b/drivers/pinctrl/Kconfig
> @@ -185,6 +185,14 @@ config PINCTRL_IMX6SL
> help
> Say Y here to enable the imx6sl pinctrl driver
>
> +config PINCTRL_IMX6SX
> + bool "IMX6SX pinctrl driver"
> + depends on OF
> + depends on SOC_IMX6SX
> + select PINCTRL_IMX
> + help
> + Say Y here to enable the imx6sx pinctrl driver
> +
> config PINCTRL_VF610
> bool "Freescale Vybrid VF610 pinctrl driver"
> depends on SOC_VF610
> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
> index 4b83588..bc791b4 100644
> --- a/drivers/pinctrl/Makefile
> +++ b/drivers/pinctrl/Makefile
> @@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
> obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
> +obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
> obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
> obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
> obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
> diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-imx6sx.c
> new file mode 100644
> index 0000000..09758a5
> --- /dev/null
> +++ b/drivers/pinctrl/pinctrl-imx6sx.c
> @@ -0,0 +1,407 @@
> +/*
> + * Copyright (C) 2014 Freescale Semiconductor, Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/err.h>
> +#include <linux/init.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/pinctrl/pinctrl.h>
> +
> +#include "pinctrl-imx.h"
> +
> +enum imx6sx_pads {
> + MX6Sx_PAD_RESERVE0 = 0,
> + MX6Sx_PAD_RESERVE1 = 1,
> + MX6Sx_PAD_RESERVE2 = 2,
> + MX6Sx_PAD_RESERVE3 = 3,
> + MX6Sx_PAD_RESERVE4 = 4,
> + MX6SX_PAD_GPIO1_IO00 = 5,
> + MX6SX_PAD_GPIO1_IO01 = 6,
> + MX6SX_PAD_GPIO1_IO02 = 7,
> + MX6SX_PAD_GPIO1_IO03 = 8,
> + MX6SX_PAD_GPIO1_IO04 = 9,
> + MX6SX_PAD_GPIO1_IO05 = 10,
> + MX6SX_PAD_GPIO1_IO06 = 11,
> + MX6SX_PAD_GPIO1_IO07 = 12,
> + MX6SX_PAD_GPIO1_IO08 = 13,
> + MX6SX_PAD_GPIO1_IO09 = 14,
> + MX6SX_PAD_GPIO1_IO10 = 15,
> + MX6SX_PAD_GPIO1_IO11 = 16,
> + MX6SX_PAD_GPIO1_IO12 = 17,
> + MX6SX_PAD_GPIO1_IO13 = 18,
> + MX6SX_PAD_CSI_DATA00 = 19,
> + MX6SX_PAD_CSI_DATA01 = 20,
> + MX6SX_PAD_CSI_DATA02 = 21,
> + MX6SX_PAD_CSI_DATA03 = 22,
> + MX6SX_PAD_CSI_DATA04 = 23,
> + MX6SX_PAD_CSI_DATA05 = 24,
> + MX6SX_PAD_CSI_DATA06 = 25,
> + MX6SX_PAD_CSI_DATA07 = 26,
> + MX6SX_PAD_CSI_HSYNC = 27,
> + MX6SX_PAD_CSI_MCLK = 28,
> + MX6SX_PAD_CSI_PIXCLK = 29,
> + MX6SX_PAD_CSI_VSYNC = 30,
> + MX6SX_PAD_ENET1_COL = 31,
> + MX6SX_PAD_ENET1_CRS = 32,
> + MX6SX_PAD_ENET1_MDC = 33,
> + MX6SX_PAD_ENET1_MDIO = 34,
> + MX6SX_PAD_ENET1_RX_CLK = 35,
> + MX6SX_PAD_ENET1_TX_CLK = 36,
> + MX6SX_PAD_ENET2_COL = 37,
> + MX6SX_PAD_ENET2_CRS = 38,
> + MX6SX_PAD_ENET2_RX_CLK = 39,
> + MX6SX_PAD_ENET2_TX_CLK = 40,
> + MX6SX_PAD_KEY_COL0 = 41,
> + MX6SX_PAD_KEY_COL1 = 42,
> + MX6SX_PAD_KEY_COL2 = 43,
> + MX6SX_PAD_KEY_COL3 = 44,
> + MX6SX_PAD_KEY_COL4 = 45,
> + MX6SX_PAD_KEY_ROW0 = 46,
> + MX6SX_PAD_KEY_ROW1 = 47,
> + MX6SX_PAD_KEY_ROW2 = 48,
> + MX6SX_PAD_KEY_ROW3 = 49,
> + MX6SX_PAD_KEY_ROW4 = 50,
> + MX6SX_PAD_LCD1_CLK = 51,
> + MX6SX_PAD_LCD1_DATA00 = 52,
> + MX6SX_PAD_LCD1_DATA01 = 53,
> + MX6SX_PAD_LCD1_DATA02 = 54,
> + MX6SX_PAD_LCD1_DATA03 = 55,
> + MX6SX_PAD_LCD1_DATA04 = 56,
> + MX6SX_PAD_LCD1_DATA05 = 57,
> + MX6SX_PAD_LCD1_DATA06 = 58,
> + MX6SX_PAD_LCD1_DATA07 = 59,
> + MX6SX_PAD_LCD1_DATA08 = 60,
> + MX6SX_PAD_LCD1_DATA09 = 61,
> + MX6SX_PAD_LCD1_DATA10 = 62,
> + MX6SX_PAD_LCD1_DATA11 = 63,
> + MX6SX_PAD_LCD1_DATA12 = 64,
> + MX6SX_PAD_LCD1_DATA13 = 65,
> + MX6SX_PAD_LCD1_DATA14 = 66,
> + MX6SX_PAD_LCD1_DATA15 = 67,
> + MX6SX_PAD_LCD1_DATA16 = 68,
> + MX6SX_PAD_LCD1_DATA17 = 69,
> + MX6SX_PAD_LCD1_DATA18 = 70,
> + MX6SX_PAD_LCD1_DATA19 = 71,
> + MX6SX_PAD_LCD1_DATA20 = 72,
> + MX6SX_PAD_LCD1_DATA21 = 73,
> + MX6SX_PAD_LCD1_DATA22 = 74,
> + MX6SX_PAD_LCD1_DATA23 = 75,
> + MX6SX_PAD_LCD1_ENABLE = 76,
> + MX6SX_PAD_LCD1_HSYNC = 77,
> + MX6SX_PAD_LCD1_RESET = 78,
> + MX6SX_PAD_LCD1_VSYNC = 79,
> + MX6SX_PAD_NAND_ALE = 80,
> + MX6SX_PAD_NAND_CE0_B = 81,
> + MX6SX_PAD_NAND_CE1_B = 82,
> + MX6SX_PAD_NAND_CLE = 83,
> + MX6SX_PAD_NAND_DATA00 = 84 ,
> + MX6SX_PAD_NAND_DATA01 = 85,
> + MX6SX_PAD_NAND_DATA02 = 86,
> + MX6SX_PAD_NAND_DATA03 = 87,
> + MX6SX_PAD_NAND_DATA04 = 88,
> + MX6SX_PAD_NAND_DATA05 = 89,
> + MX6SX_PAD_NAND_DATA06 = 90,
> + MX6SX_PAD_NAND_DATA07 = 91,
> + MX6SX_PAD_NAND_RE_B = 92,
> + MX6SX_PAD_NAND_READY_B = 93,
> + MX6SX_PAD_NAND_WE_B = 94,
> + MX6SX_PAD_NAND_WP_B = 95,
> + MX6SX_PAD_QSPI1A_DATA0 = 96,
> + MX6SX_PAD_QSPI1A_DATA1 = 97,
> + MX6SX_PAD_QSPI1A_DATA2 = 98,
> + MX6SX_PAD_QSPI1A_DATA3 = 99,
> + MX6SX_PAD_QSPI1A_DQS = 100,
> + MX6SX_PAD_QSPI1A_SCLK = 101,
> + MX6SX_PAD_QSPI1A_SS0_B = 102,
> + MX6SX_PAD_QSPI1A_SS1_B = 103,
> + MX6SX_PAD_QSPI1B_DATA0 = 104,
> + MX6SX_PAD_QSPI1B_DATA1 = 105,
> + MX6SX_PAD_QSPI1B_DATA2 = 106,
> + MX6SX_PAD_QSPI1B_DATA3 = 107,
> + MX6SX_PAD_QSPI1B_DQS = 108,
> + MX6SX_PAD_QSPI1B_SCLK = 109,
> + MX6SX_PAD_QSPI1B_SS0_B = 110,
> + MX6SX_PAD_QSPI1B_SS1_B = 111,
> + MX6SX_PAD_RGMII1_RD0 = 112,
> + MX6SX_PAD_RGMII1_RD1 = 113,
> + MX6SX_PAD_RGMII1_RD2 = 114,
> + MX6SX_PAD_RGMII1_RD3 = 115,
> + MX6SX_PAD_RGMII1_RX_CTL = 116,
> + MX6SX_PAD_RGMII1_RXC = 117,
> + MX6SX_PAD_RGMII1_TD0 = 118,
> + MX6SX_PAD_RGMII1_TD1 = 119,
> + MX6SX_PAD_RGMII1_TD2 = 120,
> + MX6SX_PAD_RGMII1_TD3 = 121,
> + MX6SX_PAD_RGMII1_TX_CTL = 122,
> + MX6SX_PAD_RGMII1_TXC = 123,
> + MX6SX_PAD_RGMII2_RD0 = 124,
> + MX6SX_PAD_RGMII2_RD1 = 125,
> + MX6SX_PAD_RGMII2_RD2 = 126,
> + MX6SX_PAD_RGMII2_RD3 = 127,
> + MX6SX_PAD_RGMII2_RX_CTL = 128,
> + MX6SX_PAD_RGMII2_RXC = 129,
> + MX6SX_PAD_RGMII2_TD0 = 130,
> + MX6SX_PAD_RGMII2_TD1 = 131,
> + MX6SX_PAD_RGMII2_TD2 = 132,
> + MX6SX_PAD_RGMII2_TD3 = 133,
> + MX6SX_PAD_RGMII2_TX_CTL = 134,
> + MX6SX_PAD_RGMII2_TXC = 135,
> + MX6SX_PAD_SD1_CLK = 136,
> + MX6SX_PAD_SD1_CMD = 137,
> + MX6SX_PAD_SD1_DATA0 = 138,
> + MX6SX_PAD_SD1_DATA1 = 139,
> + MX6SX_PAD_SD1_DATA2 = 140,
> + MX6SX_PAD_SD1_DATA3 = 141,
> + MX6SX_PAD_SD2_CLK = 142,
> + MX6SX_PAD_SD2_CMD = 143,
> + MX6SX_PAD_SD2_DATA0 = 144,
> + MX6SX_PAD_SD2_DATA1 = 145,
> + MX6SX_PAD_SD2_DATA2 = 146,
> + MX6SX_PAD_SD2_DATA3 = 147,
> + MX6SX_PAD_SD3_CLK = 148,
> + MX6SX_PAD_SD3_CMD = 149,
> + MX6SX_PAD_SD3_DATA0 = 150,
> + MX6SX_PAD_SD3_DATA1 = 151,
> + MX6SX_PAD_SD3_DATA2 = 152,
> + MX6SX_PAD_SD3_DATA3 = 153,
> + MX6SX_PAD_SD3_DATA4 = 154,
> + MX6SX_PAD_SD3_DATA5 = 155,
> + MX6SX_PAD_SD3_DATA6 = 156,
> + MX6SX_PAD_SD3_DATA7 = 157,
> + MX6SX_PAD_SD4_CLK = 158,
> + MX6SX_PAD_SD4_CMD = 159,
> + MX6SX_PAD_SD4_DATA0 = 160,
> + MX6SX_PAD_SD4_DATA1 = 161,
> + MX6SX_PAD_SD4_DATA2 = 162,
> + MX6SX_PAD_SD4_DATA3 = 163,
> + MX6SX_PAD_SD4_DATA4 = 164,
> + MX6SX_PAD_SD4_DATA5 = 165,
> + MX6SX_PAD_SD4_DATA6 = 166,
> + MX6SX_PAD_SD4_DATA7 = 167,
> + MX6SX_PAD_SD4_RESET_B = 168,
> + MX6SX_PAD_USB_H_DATA = 169,
> + MX6SX_PAD_USB_H_STROBE = 170,
> +};
> +
> +/* Pad names for the pinmux subsystem */
> +static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
> + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
> + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
> +};
> +
> +static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
> + .pins = imx6sx_pinctrl_pads,
> + .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
> +};
> +
> +static struct of_device_id imx6sx_pinctrl_of_match[] = {
> + { .compatible = "fsl,imx6sx-iomuxc", },
> + { /* sentinel */ }
> +};
> +
> +static int imx6sx_pinctrl_probe(struct platform_device *pdev)
> +{
> + return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
> +}
> +
> +static struct platform_driver imx6sx_pinctrl_driver = {
> + .driver = {
> + .name = "imx6sx-pinctrl",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
> + },
> + .probe = imx6sx_pinctrl_probe,
> + .remove = imx_pinctrl_remove,
> +};
> +
> +static int __init imx6sx_pinctrl_init(void)
> +{
> + return platform_driver_register(&imx6sx_pinctrl_driver);
> +}
> +arch_initcall(imx6sx_pinctrl_init);
> +
> +static void __exit imx6sx_pinctrl_exit(void)
> +{
> + platform_driver_unregister(&imx6sx_pinctrl_driver);
> +}
> +module_exit(imx6sx_pinctrl_exit);
> +
> +MODULE_AUTHOR("Anson Huang <Anson.Huang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>");
> +MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.9.5
>
>
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^ permalink raw reply
* RE: [PATCH] pinctrl: add pinctrl driver for imx6sx
From: Anson.Huang-KZfg59tc24xl57MIdRCFDg @ 2014-02-19 8:43 UTC (permalink / raw)
To: Shawn Guo
Cc: kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
dong.aisheng-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <20140219083920.GJ3010-rvtDTF3kK1ictlrPMvKcciBecyulp+rMXqFh9Ls21Oc@public.gmane.org>
Hi, Shawn
OK, I will hold on these patches until Freescale announce this SOC, please ignore the dts patches as well.
Best Regards.
Anson Huang
Freescale Semiconductor Shanghai
Tel:021-28937058
>-----Original Message-----
>From: Shawn Guo [mailto:shawn.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org]
>Sent: Wednesday, February 19, 2014 4:39 PM
>To: Huang Yongcai-B20788
>Cc: kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org; linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; dong.aisheng@linaro.org;
>devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
>kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>Subject: Re: [PATCH] pinctrl: add pinctrl driver for imx6sx
>
>On Wed, Feb 19, 2014 at 03:06:59PM +0800, Anson Huang wrote:
>> Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
>> driver.
>
>I haven't seen that Freescale announces this SoC. I would suggest we
>wait for a while until we see the announcement telling that i.MX6 SoloX
>is the name of this SoC.
>
>Shawn
>
>>
>> Signed-off-by: Anson Huang <b20788-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
>> ---
>> .../bindings/pinctrl/fsl,imx6sx-pinctrl.txt | 38 +
>> arch/arm/boot/dts/imx6sx-pinfunc.h | 1544
>++++++++++++++++++++
>> drivers/pinctrl/Kconfig | 8 +
>> drivers/pinctrl/Makefile | 1 +
>> drivers/pinctrl/pinctrl-imx6sx.c | 407 ++++++
>> 5 files changed, 1998 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-
>pinctrl.txt
>> create mode 100755 arch/arm/boot/dts/imx6sx-pinfunc.h
>> create mode 100644 drivers/pinctrl/pinctrl-imx6sx.c
>>
>> diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-
>pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
>> new file mode 100644
>> index 0000000..67f62ba
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pinctrl/fsl,imx6sx-pinctrl.txt
>> @@ -0,0 +1,38 @@
>> +* Freescale IMX6 SoloX IOMUX Controller
>> +
>> +Please refer to fsl,imx-pinctrl.txt in this directory for common binding
>part
>> +and usage.
>> +
>> +Required properties:
>> +- compatible: "fsl,imx6sx-iomuxc"
>> +- fsl,pins: two integers array, represents a group of pins mux and config
>> + setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
>> + pin working on a specific function, CONFIG is the pad setting value like
>> + pull-up for this pin. Please refer to imx6sx datasheet for the valid pad
>> + config settings.
>> +
>> +CONFIG bits definition:
>> +PAD_CTL_HYS (1 << 16)
>> +PAD_CTL_PUS_100K_DOWN (0 << 14)
>> +PAD_CTL_PUS_47K_UP (1 << 14)
>> +PAD_CTL_PUS_100K_UP (2 << 14)
>> +PAD_CTL_PUS_22K_UP (3 << 14)
>> +PAD_CTL_PUE (1 << 13)
>> +PAD_CTL_PKE (1 << 12)
>> +PAD_CTL_ODE (1 << 11)
>> +PAD_CTL_SPEED_LOW (0 << 6)
>> +PAD_CTL_SPEED_MED (1 << 6)
>> +PAD_CTL_SPEED_HIGH (3 << 6)
>> +PAD_CTL_DSE_DISABLE (0 << 3)
>> +PAD_CTL_DSE_260ohm (1 << 3)
>> +PAD_CTL_DSE_130ohm (2 << 3)
>> +PAD_CTL_DSE_87ohm (3 << 3)
>> +PAD_CTL_DSE_65ohm (4 << 3)
>> +PAD_CTL_DSE_52ohm (5 << 3)
>> +PAD_CTL_DSE_43ohm (6 << 3)
>> +PAD_CTL_DSE_37ohm (7 << 3)
>> +PAD_CTL_SRE_FAST (1 << 0)
>> +PAD_CTL_SRE_SLOW (0 << 0)
>> +
>> +Refer to imx6sx-pinfunc.h in device tree source folder for all available
>> +imx6sx PIN_FUNC_ID.
>> diff --git a/arch/arm/boot/dts/imx6sx-pinfunc.h b/arch/arm/boot/dts/imx6sx-
>pinfunc.h
>> new file mode 100755
>> index 0000000..3e0b816
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/imx6sx-pinfunc.h
>> @@ -0,0 +1,1544 @@
>> +/*
>> + * Copyright 2014 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + *
>> + */
>> +
>> +#ifndef __DTS_IMX6SX_PINFUNC_H
>> +#define __DTS_IMX6SX_PINFUNC_H
>> +
>> +/*
>> + * The pin function ID is a tuple of
>> + * <mux_reg conf_reg input_reg mux_mode input_val>
>> + */
>> +#define MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x0014
>0x035C 0x07A8 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO00__USDHC1_VSELECT 0x0014
>0x035C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__SPDIF_LOCK 0x0014
>0x035C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__CCM_WAIT 0x0014
>0x035C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__WDOG1_WDOG_ANY 0x0014
>0x035C 0x0000 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__GPIO1_IO_0 0x0014
>0x035C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__SNVS_HP_WRAPPER_VIO_5 0x0014
>0x035C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO00__PHY_DTB_1 0x0014
>0x035C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x0018
>0x0360 0x07AC 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO01__USDHC1_RESET_B 0x0018
>0x0360 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__SPDIF_SR_CLK 0x0018
>0x0360 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__CCM_STOP 0x0018
>0x0360 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__WDOG3_WDOG_B 0x0018
>0x0360 0x0000 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__GPIO1_IO_1 0x0018
>0x0360 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__SNVS_HP_WRAPPER_VIO_5_CTL 0x0018
>0x0360 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO01__PHY_DTB_0 0x0018
>0x0360 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x001C
>0x0364 0x07B0 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO02__USDHC1_CD_B 0x001C
>0x0364 0x0864 0x1 0x1
>> +#define MX6SX_PAD_GPIO1_IO02__CSI2_MCLK 0x001C
>0x0364 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__CCM_DI0_EXT_CLK 0x001C
>0x0364 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__WDOG1_WDOG_B 0x001C
>0x0364 0x0000 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__GPIO1_IO_2 0x001C
>0x0364 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__CCM_REF_EN_B 0x001C
>0x0364 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO02__PHY_TDI 0x001C
>0x0364 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x0020
>0x0368 0x07B4 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO03__USDHC1_WP 0x0020
>0x0368 0x0868 0x1 0x1
>> +#define MX6SX_PAD_GPIO1_IO03__ENET1_REF_CLK_25M 0x0020
>0x0368 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__CCM_DI1_EXT_CLK 0x0020
>0x0368 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__WDOG2_WDOG_B 0x0020
>0x0368 0x0000 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__GPIO1_IO_3 0x0020
>0x0368 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__CCM_PLL3_BYP 0x0020
>0x0368 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO03__PHY_TCK 0x0020
>0x0368 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__UART1_RX 0x0024
>0x036C 0x0830 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__UART1_TX 0x0024
>0x036C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__USDHC2_RESET_B 0x0024
>0x036C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__ENET1_MDC 0x0024
>0x036C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__OSC32K_32K_OUT 0x0024
>0x036C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__ENET2_REF_CLK2 0x0024
>0x036C 0x076C 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__GPIO1_IO_4 0x0024
>0x036C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__CCM_PLL2_BYP 0x0024
>0x036C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO04__PHY_TMS 0x0024
>0x036C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__UART1_RX 0x0028
>0x0370 0x0830 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO05__UART1_TX 0x0028
>0x0370 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__USDHC2_VSELECT 0x0028
>0x0370 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__ENET1_MDIO 0x0028
>0x0370 0x0764 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__ASRC_ASRC_EXT_CLK 0x0028
>0x0370 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__ENET1_REF_CLK1 0x0028
>0x0370 0x0760 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__GPIO1_IO_5 0x0028
>0x0370 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__SRC_TESTER_ACK 0x0028
>0x0370 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO05__PHY_TDO 0x0028
>0x0370 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__UART2_RX 0x002C
>0x0374 0x0838 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__UART2_TX 0x002C
>0x0374 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__USDHC2_CD_B 0x002C
>0x0374 0x086C 0x1 0x1
>> +#define MX6SX_PAD_GPIO1_IO06__ENET2_MDC 0x002C
>0x0374 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__CSI1_MCLK 0x002C
>0x0374 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__UART1_RTS_B 0x002C
>0x0374 0x082C 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__GPIO1_IO_6 0x002C
>0x0374 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__SRC_ANY_PU_RESET 0x002C
>0x0374 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO06__OCOTP_CTRL_WRAPPER_FUSE_LATCHED 0x002C
>0x0374 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__UART2_RX 0x0030
>0x0378 0x0838 0x0 0x1
>> +#define MX6SX_PAD_GPIO1_IO07__UART2_TX 0x0030
>0x0378 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__USDHC2_WP 0x0030
>0x0378 0x0870 0x1 0x1
>> +#define MX6SX_PAD_GPIO1_IO07__ENET2_MDIO 0x0030
>0x0378 0x0770 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__AUDMUX_MCLK 0x0030
>0x0378 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__UART1_CTS_B 0x0030
>0x0378 0x082C 0x4 0x1
>> +#define MX6SX_PAD_GPIO1_IO07__GPIO1_IO_7 0x0030
>0x0378 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__SRC_EARLY_RESET 0x0030
>0x0378 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__DCIC2_OUT 0x0030
>0x0378 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO07__VDEC_DEBUG_44 0x0030
>0x0378 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__USB_OTG1_OC 0x0034
>0x037C 0x0860 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__WDOG1_WDOG_B 0x0034
>0x037C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__SDMA_EXT_EVENT_0 0x0034
>0x037C 0x081C 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__CCM_PMIC_RDY 0x0034
>0x037C 0x069C 0x3 0x1
>> +#define MX6SX_PAD_GPIO1_IO08__UART2_RTS_B 0x0034
>0x037C 0x0834 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__GPIO1_IO_8 0x0034
>0x037C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__SRC_SYSTEM_RESET 0x0034
>0x037C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__DCIC1_OUT 0x0034
>0x037C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO08__VDEC_DEBUG_43 0x0034
>0x037C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__USB_OTG1_PWR 0x0038
>0x0380 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__WDOG2_WDOG_B 0x0038
>0x0380 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__SDMA_EXT_EVENT_1 0x0038
>0x0380 0x0820 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__CCM_OUT0 0x0038
>0x0380 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__UART2_CTS_B 0x0038
>0x0380 0x0834 0x4 0x1
>> +#define MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x0038
>0x0380 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__SRC_INT_BOOT 0x0038
>0x0380 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__OBSERVE_MUX_OUT_4 0x0038
>0x0380 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO09__VDEC_DEBUG_42 0x0038
>0x0380 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x003C
>0x0384 0x0624 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__SPDIF_EXT_CLK 0x003C
>0x0384 0x0828 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__PWM1_OUT 0x003C
>0x0384 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__CCM_OUT1 0x003C
>0x0384 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__CSI1_FIELD 0x003C
>0x0384 0x070C 0x4 0x1
>> +#define MX6SX_PAD_GPIO1_IO10__GPIO1_IO_10 0x003C
>0x0384 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__CSU_CSU_INT_DEB 0x003C
>0x0384 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__OBSERVE_MUX_OUT_3 0x003C
>0x0384 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO10__VDEC_DEBUG_41 0x003C
>0x0384 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__USB_OTG2_OC 0x0040
>0x0388 0x085C 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__SPDIF_IN 0x0040
>0x0388 0x0824 0x1 0x2
>> +#define MX6SX_PAD_GPIO1_IO11__PWM2_OUT 0x0040
>0x0388 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__CCM_CLKO1 0x0040
>0x0388 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__MLB_DATA 0x0040
>0x0388 0x07EC 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__GPIO1_IO_11 0x0040
>0x0388 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__CSU_CSU_ALARM_AUT_0 0x0040
>0x0388 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__OBSERVE_MUX_OUT_2 0x0040
>0x0388 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO11__VDEC_DEBUG_40 0x0040
>0x0388 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__USB_OTG2_PWR 0x0044
>0x038C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__SPDIF_OUT 0x0044
>0x038C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__PWM3_OUT 0x0044
>0x038C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__CCM_CLKO2 0x0044
>0x038C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__MLB_CLK 0x0044
>0x038C 0x07E8 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x0044
>0x038C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__CSU_CSU_ALARM_AUT_1 0x0044
>0x038C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__OBSERVE_MUX_OUT_1 0x0044
>0x038C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO12__VDEC_DEBUG_39 0x0044
>0x038C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY 0x0048
>0x0390 0x0000 0x0 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__ANATOP_OTG2_ID 0x0048
>0x0390 0x0628 0x1 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__PWM4_OUT 0x0048
>0x0390 0x0000 0x2 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__CCM_OUT2 0x0048
>0x0390 0x0000 0x3 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__MLB_SIG 0x0048
>0x0390 0x07F0 0x4 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__GPIO1_IO_13 0x0048
>0x0390 0x0000 0x5 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__CSU_CSU_ALARM_AUT_2 0x0048
>0x0390 0x0000 0x6 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__OBSERVE_MUX_OUT_0 0x0048
>0x0390 0x0000 0x7 0x0
>> +#define MX6SX_PAD_GPIO1_IO13__VDEC_DEBUG_38 0x0048
>0x0390 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA00__CSI1_DATA_2 0x004C
>0x0394 0x06A8 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA00__ESAI_TX_CLK 0x004C
>0x0394 0x078C 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x004C
>0x0394 0x0684 0x2 0x1
>> +#define MX6SX_PAD_CSI_DATA00__I2C1_SCL 0x004C
>0x0394 0x07A8 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA00__UART6_RI_B 0x004C
>0x0394 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA00__GPIO1_IO_14 0x004C
>0x0394 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA00__WEIM_DATA_23 0x004C
>0x0394 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA00__SAI1_TX_BCLK 0x004C
>0x0394 0x0800 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA00__VADC_DATA_4 0x004C
>0x0394 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA00__MMDC_DEBUG_37 0x004C
>0x0394 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA01__CSI1_DATA_3 0x0050
>0x0398 0x06AC 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA01__ESAI_TX_FS 0x0050
>0x0398 0x077C 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x0050
>0x0398 0x0688 0x2 0x1
>> +#define MX6SX_PAD_CSI_DATA01__I2C1_SDA 0x0050
>0x0398 0x07AC 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA01__UART6_DSR_B 0x0050
>0x0398 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA01__GPIO1_IO_15 0x0050
>0x0398 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA01__WEIM_DATA_22 0x0050
>0x0398 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA01__SAI1_TX_SYNC 0x0050
>0x0398 0x0804 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA01__VADC_DATA_5 0x0050
>0x0398 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA01__MMDC_DEBUG_38 0x0050
>0x0398 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA02__CSI1_DATA_4 0x0054
>0x039C 0x06B0 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA02__ESAI_RX_CLK 0x0054
>0x039C 0x0788 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA02__AUDMUX_AUD6_RXC 0x0054
>0x039C 0x067C 0x2 0x1
>> +#define MX6SX_PAD_CSI_DATA02__KPP_COL_5 0x0054
>0x039C 0x07C8 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA02__UART6_DTR_B 0x0054
>0x039C 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA02__GPIO1_IO_16 0x0054
>0x039C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA02__WEIM_DATA_21 0x0054
>0x039C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA02__SAI1_RX_BCLK 0x0054
>0x039C 0x07F4 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA02__VADC_DATA_6 0x0054
>0x039C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA02__MMDC_DEBUG_39 0x0054
>0x039C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA03__CSI1_DATA_5 0x0058
>0x03A0 0x06B4 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA03__ESAI_RX_FS 0x0058
>0x03A0 0x0778 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA03__AUDMUX_AUD6_RXFS 0x0058
>0x03A0 0x0680 0x2 0x1
>> +#define MX6SX_PAD_CSI_DATA03__KPP_ROW_5 0x0058
>0x03A0 0x07D4 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA03__UART6_DCD_B 0x0058
>0x03A0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA03__GPIO1_IO_17 0x0058
>0x03A0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA03__WEIM_DATA_20 0x0058
>0x03A0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA03__SAI1_RX_SYNC 0x0058
>0x03A0 0x07FC 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA03__VADC_DATA_7 0x0058
>0x03A0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA03__MMDC_DEBUG_40 0x0058
>0x03A0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA04__CSI1_DATA_6 0x005C
>0x03A4 0x06B8 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA04__ESAI_TX1 0x005C
>0x03A4 0x0794 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA04__SPDIF_OUT 0x005C
>0x03A4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_CSI_DATA04__KPP_COL_6 0x005C
>0x03A4 0x07CC 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA04__UART6_RX 0x005C
>0x03A4 0x0858 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA04__UART6_TX 0x005C
>0x03A4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x005C
>0x03A4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA04__WEIM_DATA_19 0x005C
>0x03A4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA04__PWM5_OUT 0x005C
>0x03A4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA04__VADC_DATA_8 0x005C
>0x03A4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA04__MMDC_DEBUG_41 0x005C
>0x03A4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA05__CSI1_DATA_7 0x0060
>0x03A8 0x06BC 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA05__ESAI_TX4_RX1 0x0060
>0x03A8 0x07A0 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA05__SPDIF_IN 0x0060
>0x03A8 0x0824 0x2 0x1
>> +#define MX6SX_PAD_CSI_DATA05__KPP_ROW_6 0x0060
>0x03A8 0x07D8 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA05__UART6_RX 0x0060
>0x03A8 0x0858 0x4 0x1
>> +#define MX6SX_PAD_CSI_DATA05__UART6_TX 0x0060
>0x03A8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x0060
>0x03A8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA05__WEIM_DATA_18 0x0060
>0x03A8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA05__PWM6_OUT 0x0060
>0x03A8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA05__VADC_DATA_9 0x0060
>0x03A8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA05__MMDC_DEBUG_42 0x0060
>0x03A8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA06__CSI1_DATA_8 0x0064
>0x03AC 0x06C0 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA06__ESAI_TX2_RX3 0x0064
>0x03AC 0x0798 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x0064
>0x03AC 0x07C0 0x2 0x2
>> +#define MX6SX_PAD_CSI_DATA06__KPP_COL_7 0x0064
>0x03AC 0x07D0 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA06__UART6_RTS_B 0x0064
>0x03AC 0x0854 0x4 0x0
>> +#define MX6SX_PAD_CSI_DATA06__GPIO1_IO_20 0x0064
>0x03AC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA06__WEIM_DATA_17 0x0064
>0x03AC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA06__DCIC2_OUT 0x0064
>0x03AC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA06__VADC_DATA_10 0x0064
>0x03AC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA06__MMDC_DEBUG_43 0x0064
>0x03AC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_DATA07__CSI1_DATA_9 0x0068
>0x03B0 0x06C4 0x0 0x0
>> +#define MX6SX_PAD_CSI_DATA07__ESAI_TX3_RX2 0x0068
>0x03B0 0x079C 0x1 0x1
>> +#define MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x0068
>0x03B0 0x07C4 0x2 0x2
>> +#define MX6SX_PAD_CSI_DATA07__KPP_ROW_7 0x0068
>0x03B0 0x07DC 0x3 0x0
>> +#define MX6SX_PAD_CSI_DATA07__UART6_CTS_B 0x0068
>0x03B0 0x0854 0x4 0x1
>> +#define MX6SX_PAD_CSI_DATA07__GPIO1_IO_21 0x0068
>0x03B0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_DATA07__WEIM_DATA_16 0x0068
>0x03B0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_DATA07__DCIC1_OUT 0x0068
>0x03B0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_CSI_DATA07__VADC_DATA_11 0x0068
>0x03B0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_DATA07__MMDC_DEBUG_44 0x0068
>0x03B0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__CSI1_HSYNC 0x006C
>0x03B4 0x0700 0x0 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__ESAI_TX0 0x006C
>0x03B4 0x0790 0x1 0x1
>> +#define MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x006C
>0x03B4 0x0678 0x2 0x1
>> +#define MX6SX_PAD_CSI_HSYNC__UART4_RTS_B 0x006C
>0x03B4 0x0844 0x3 0x2
>> +#define MX6SX_PAD_CSI_HSYNC__MQS_LEFT 0x006C
>0x03B4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__GPIO1_IO_22 0x006C
>0x03B4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__WEIM_DATA_25 0x006C
>0x03B4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__SAI1_TX_DATA_0 0x006C
>0x03B4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__VADC_DATA_2 0x006C
>0x03B4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_HSYNC__MMDC_DEBUG_35 0x006C
>0x03B4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_MCLK__CSI1_MCLK 0x0070
>0x03B8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_CSI_MCLK__ESAI_TX_HF_CLK 0x0070
>0x03B8 0x0784 0x1 0x1
>> +#define MX6SX_PAD_CSI_MCLK__OSC32K_32K_OUT 0x0070
>0x03B8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_CSI_MCLK__UART4_RX 0x0070
>0x03B8 0x0848 0x3 0x2
>> +#define MX6SX_PAD_CSI_MCLK__UART4_TX 0x0070
>0x03B8 0x0000 0x3 0x0
>> +#define MX6SX_PAD_CSI_MCLK__ANATOP_32K_OUT 0x0070
>0x03B8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_MCLK__GPIO1_IO_23 0x0070
>0x03B8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_MCLK__WEIM_DATA_26 0x0070
>0x03B8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_MCLK__CSI1_FIELD 0x0070
>0x03B8 0x070C 0x7 0x0
>> +#define MX6SX_PAD_CSI_MCLK__VADC_DATA_1 0x0070
>0x03B8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_MCLK__MMDC_DEBUG_34 0x0070
>0x03B8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__CSI1_PIXCLK 0x0074
>0x03BC 0x0704 0x0 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__ESAI_RX_HF_CLK 0x0074
>0x03BC 0x0780 0x1 0x1
>> +#define MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x0074
>0x03BC 0x0000 0x2 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__UART4_RX 0x0074
>0x03BC 0x0848 0x3 0x3
>> +#define MX6SX_PAD_CSI_PIXCLK__UART4_TX 0x0074
>0x03BC 0x0000 0x3 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__ANATOP_24M_OUT 0x0074
>0x03BC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x0074
>0x03BC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__WEIM_DATA_27 0x0074
>0x03BC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__ESAI_TX_HF_CLK 0x0074
>0x03BC 0x0784 0x7 0x2
>> +#define MX6SX_PAD_CSI_PIXCLK__VADC_CLK 0x0074
>0x03BC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_PIXCLK__MMDC_DEBUG_33 0x0074
>0x03BC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__CSI1_VSYNC 0x0078
>0x03C0 0x0708 0x0 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__ESAI_TX5_RX0 0x0078
>0x03C0 0x07A4 0x1 0x1
>> +#define MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x0078
>0x03C0 0x0674 0x2 0x1
>> +#define MX6SX_PAD_CSI_VSYNC__UART4_CTS_B 0x0078
>0x03C0 0x0844 0x3 0x3
>> +#define MX6SX_PAD_CSI_VSYNC__MQS_RIGHT 0x0078
>0x03C0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__GPIO1_IO_25 0x0078
>0x03C0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__WEIM_DATA_24 0x0078
>0x03C0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__SAI1_RX_DATA_0 0x0078
>0x03C0 0x07F8 0x7 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__VADC_DATA_3 0x0078
>0x03C0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_CSI_VSYNC__MMDC_DEBUG_36 0x0078
>0x03C0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET1_COL__ENET1_COL 0x007C
>0x03C4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET1_COL__ENET2_MDC 0x007C
>0x03C4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_ENET1_COL__AUDMUX_AUD4_TXC 0x007C
>0x03C4 0x0654 0x2 0x1
>> +#define MX6SX_PAD_ENET1_COL__UART1_RI_B 0x007C
>0x03C4 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_COL__SPDIF_EXT_CLK 0x007C
>0x03C4 0x0828 0x4 0x1
>> +#define MX6SX_PAD_ENET1_COL__GPIO2_IO_0 0x007C
>0x03C4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_COL__CSI2_DATA_23 0x007C
>0x03C4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET1_COL__LCDIF2_DATA_16 0x007C
>0x03C4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_COL__VDEC_DEBUG_37 0x007C
>0x03C4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET1_COL__PCIE_CTRL_DEBUG_31 0x007C
>0x03C4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET1_CRS__ENET1_CRS 0x0080
>0x03C8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET1_CRS__ENET2_MDIO 0x0080
>0x03C8 0x0770 0x1 0x1
>> +#define MX6SX_PAD_ENET1_CRS__AUDMUX_AUD4_TXD 0x0080
>0x03C8 0x0648 0x2 0x1
>> +#define MX6SX_PAD_ENET1_CRS__UART1_DCD_B 0x0080
>0x03C8 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_CRS__SPDIF_LOCK 0x0080
>0x03C8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_ENET1_CRS__GPIO2_IO_1 0x0080
>0x03C8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_CRS__CSI2_DATA_22 0x0080
>0x03C8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET1_CRS__LCDIF2_DATA_17 0x0080
>0x03C8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_CRS__VDEC_DEBUG_36 0x0080
>0x03C8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET1_CRS__PCIE_CTRL_DEBUG_30 0x0080
>0x03C8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET1_MDC__ENET1_MDC 0x0084
>0x03CC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET1_MDC__ENET2_MDC 0x0084
>0x03CC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_ENET1_MDC__AUDMUX_AUD3_RXFS 0x0084
>0x03CC 0x0638 0x2 0x1
>> +#define MX6SX_PAD_ENET1_MDC__ANATOP_24M_OUT 0x0084
>0x03CC 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_MDC__EPIT2_OUT 0x0084
>0x03CC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_ENET1_MDC__GPIO2_IO_2 0x0084
>0x03CC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_MDC__USB_OTG1_PWR 0x0084
>0x03CC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET1_MDC__PWM7_OUT 0x0084
>0x03CC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0x0088
>0x03D0 0x0764 0x0 0x1
>> +#define MX6SX_PAD_ENET1_MDIO__ENET2_MDIO 0x0088
>0x03D0 0x0770 0x1 0x2
>> +#define MX6SX_PAD_ENET1_MDIO__AUDMUX_MCLK 0x0088
>0x03D0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_ENET1_MDIO__OSC32K_32K_OUT 0x0088
>0x03D0 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_MDIO__EPIT1_OUT 0x0088
>0x03D0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_ENET1_MDIO__GPIO2_IO_3 0x0088
>0x03D0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_MDIO__USB_OTG1_OC 0x0088
>0x03D0 0x0860 0x6 0x1
>> +#define MX6SX_PAD_ENET1_MDIO__PWM8_OUT 0x0088
>0x03D0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_RX_CLK 0x008C
>0x03D4 0x0768 0x0 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__ENET1_REF_CLK_25M 0x008C
>0x03D4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__AUDMUX_AUD4_TXFS 0x008C
>0x03D4 0x0658 0x2 0x1
>> +#define MX6SX_PAD_ENET1_RX_CLK__UART1_DSR_B 0x008C
>0x03D4 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__SPDIF_OUT 0x008C
>0x03D4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__GPIO2_IO_4 0x008C
>0x03D4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__CSI2_DATA_21 0x008C
>0x03D4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__LCDIF2_DATA_18 0x008C
>0x03D4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__VDEC_DEBUG_35 0x008C
>0x03D4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET1_RX_CLK__PCIE_CTRL_DEBUG_29 0x008C
>0x03D4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_TX_CLK 0x0090
>0x03D8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x0090
>0x03D8 0x0760 0x1 0x1
>> +#define MX6SX_PAD_ENET1_TX_CLK__AUDMUX_AUD4_RXD 0x0090
>0x03D8 0x0644 0x2 0x1
>> +#define MX6SX_PAD_ENET1_TX_CLK__UART1_DTR_B 0x0090
>0x03D8 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__SPDIF_SR_CLK 0x0090
>0x03D8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__GPIO2_IO_5 0x0090
>0x03D8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__CSI2_DATA_20 0x0090
>0x03D8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__LCDIF2_DATA_19 0x0090
>0x03D8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__VDEC_DEBUG_34 0x0090
>0x03D8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET1_TX_CLK__PCIE_CTRL_DEBUG_28 0x0090
>0x03D8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET2_COL__ENET2_COL 0x0094
>0x03DC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET2_COL__ENET1_MDC 0x0094
>0x03DC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_ENET2_COL__AUDMUX_AUD4_RXC 0x0094
>0x03DC 0x064C 0x2 0x1
>> +#define MX6SX_PAD_ENET2_COL__UART1_RX 0x0094
>0x03DC 0x0830 0x3 0x2
>> +#define MX6SX_PAD_ENET2_COL__UART1_TX 0x0094
>0x03DC 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET2_COL__SPDIF_IN 0x0094
>0x03DC 0x0824 0x4 0x3
>> +#define MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x0094
>0x03DC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET2_COL__ANATOP_OTG1_ID 0x0094
>0x03DC 0x0624 0x6 0x1
>> +#define MX6SX_PAD_ENET2_COL__LCDIF2_DATA_20 0x0094
>0x03DC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET2_COL__VDEC_DEBUG_33 0x0094
>0x03DC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET2_COL__PCIE_CTRL_DEBUG_27 0x0094
>0x03DC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET2_CRS__ENET2_CRS 0x0098
>0x03E0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET2_CRS__ENET1_MDIO 0x0098
>0x03E0 0x0764 0x1 0x2
>> +#define MX6SX_PAD_ENET2_CRS__AUDMUX_AUD4_RXFS 0x0098
>0x03E0 0x0650 0x2 0x1
>> +#define MX6SX_PAD_ENET2_CRS__UART1_RX 0x0098
>0x03E0 0x0830 0x3 0x3
>> +#define MX6SX_PAD_ENET2_CRS__UART1_TX 0x0098
>0x03E0 0x0000 0x3 0x0
>> +#define MX6SX_PAD_ENET2_CRS__MLB_SIG 0x0098
>0x03E0 0x07F0 0x4 0x1
>> +#define MX6SX_PAD_ENET2_CRS__GPIO2_IO_7 0x0098
>0x03E0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET2_CRS__ANATOP_OTG2_ID 0x0098
>0x03E0 0x0628 0x6 0x1
>> +#define MX6SX_PAD_ENET2_CRS__LCDIF2_DATA_21 0x0098
>0x03E0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET2_CRS__VDEC_DEBUG_32 0x0098
>0x03E0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET2_CRS__PCIE_CTRL_DEBUG_26 0x0098
>0x03E0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_RX_CLK 0x009C
>0x03E4 0x0774 0x0 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x009C
>0x03E4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__I2C3_SCL 0x009C
>0x03E4 0x07B8 0x2 0x1
>> +#define MX6SX_PAD_ENET2_RX_CLK__UART1_RTS_B 0x009C
>0x03E4 0x082C 0x3 0x2
>> +#define MX6SX_PAD_ENET2_RX_CLK__MLB_DATA 0x009C
>0x03E4 0x07EC 0x4 0x1
>> +#define MX6SX_PAD_ENET2_RX_CLK__GPIO2_IO_8 0x009C
>0x03E4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__USB_OTG2_OC 0x009C
>0x03E4 0x085C 0x6 0x1
>> +#define MX6SX_PAD_ENET2_RX_CLK__LCDIF2_DATA_22 0x009C
>0x03E4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__VDEC_DEBUG_31 0x009C
>0x03E4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET2_RX_CLK__PCIE_CTRL_DEBUG_25 0x009C
>0x03E4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_TX_CLK 0x00A0
>0x03E8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x00A0
>0x03E8 0x076C 0x1 0x1
>> +#define MX6SX_PAD_ENET2_TX_CLK__I2C3_SDA 0x00A0
>0x03E8 0x07BC 0x2 0x1
>> +#define MX6SX_PAD_ENET2_TX_CLK__UART1_CTS_B 0x00A0
>0x03E8 0x082C 0x3 0x3
>> +#define MX6SX_PAD_ENET2_TX_CLK__MLB_CLK 0x00A0
>0x03E8 0x07E8 0x4 0x1
>> +#define MX6SX_PAD_ENET2_TX_CLK__GPIO2_IO_9 0x00A0
>0x03E8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__USB_OTG2_PWR 0x00A0
>0x03E8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__LCDIF2_DATA_23 0x00A0
>0x03E8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__VDEC_DEBUG_30 0x00A0
>0x03E8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_ENET2_TX_CLK__PCIE_CTRL_DEBUG_24 0x00A0
>0x03E8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_KEY_COL0__KPP_COL_0 0x00A4
>0x03EC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_COL0__USDHC3_CD_B 0x00A4
>0x03EC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_COL0__UART6_RTS_B 0x00A4
>0x03EC 0x0854 0x2 0x2
>> +#define MX6SX_PAD_KEY_COL0__ECSPI1_SCLK 0x00A4
>0x03EC 0x0710 0x3 0x0
>> +#define MX6SX_PAD_KEY_COL0__AUDMUX_AUD5_TXC 0x00A4
>0x03EC 0x066C 0x4 0x0
>> +#define MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x00A4
>0x03EC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_COL0__SDMA_EXT_EVENT_1 0x00A4
>0x03EC 0x0820 0x6 0x1
>> +#define MX6SX_PAD_KEY_COL0__SAI2_TX_BCLK 0x00A4
>0x03EC 0x0814 0x7 0x0
>> +#define MX6SX_PAD_KEY_COL0__VADC_DATA_0 0x00A4
>0x03EC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_KEY_COL1__KPP_COL_1 0x00A8
>0x03F0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET_B 0x00A8
>0x03F0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_COL1__UART6_RX 0x00A8
>0x03F0 0x0858 0x2 0x2
>> +#define MX6SX_PAD_KEY_COL1__UART6_TX 0x00A8
>0x03F0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_KEY_COL1__ECSPI1_MISO 0x00A8
>0x03F0 0x0714 0x3 0x0
>> +#define MX6SX_PAD_KEY_COL1__AUDMUX_AUD5_TXFS 0x00A8
>0x03F0 0x0670 0x4 0x0
>> +#define MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x00A8
>0x03F0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_COL1__USDHC3_RESET 0x00A8
>0x03F0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_COL1__SAI2_TX_SYNC 0x00A8
>0x03F0 0x0818 0x7 0x0
>> +#define MX6SX_PAD_KEY_COL2__KPP_COL_2 0x00AC
>0x03F4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_COL2__USDHC4_CD_B 0x00AC
>0x03F4 0x0874 0x1 0x1
>> +#define MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x00AC
>0x03F4 0x084C 0x2 0x2
>> +#define MX6SX_PAD_KEY_COL2__CAN1_TX 0x00AC
>0x03F4 0x0000 0x3 0x0
>> +#define MX6SX_PAD_KEY_COL2__CANFD_TX1 0x00AC
>0x03F4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_KEY_COL2__GPIO2_IO_12 0x00AC
>0x03F4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_COL2__WEIM_DATA_30 0x00AC
>0x03F4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_COL2__ECSPI1_RDY 0x00AC
>0x03F4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_KEY_COL3__KPP_COL_3 0x00B0
>0x03F8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_COL3__USDHC4_LCTL 0x00B0
>0x03F8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_COL3__UART5_RX 0x00B0
>0x03F8 0x0850 0x2 0x2
>> +#define MX6SX_PAD_KEY_COL3__UART5_TX 0x00B0
>0x03F8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_KEY_COL3__CAN2_TX 0x00B0
>0x03F8 0x0000 0x3 0x0
>> +#define MX6SX_PAD_KEY_COL3__CANFD_TX2 0x00B0
>0x03F8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_KEY_COL3__GPIO2_IO_13 0x00B0
>0x03F8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_COL3__WEIM_DATA_28 0x00B0
>0x03F8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_COL3__ECSPI1_SS2 0x00B0
>0x03F8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_KEY_COL4__KPP_COL_4 0x00B4
>0x03FC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_COL4__ENET2_MDC 0x00B4
>0x03FC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_COL4__I2C3_SCL 0x00B4
>0x03FC 0x07B8 0x2 0x2
>> +#define MX6SX_PAD_KEY_COL4__USDHC2_LCTL 0x00B4
>0x03FC 0x0000 0x3 0x0
>> +#define MX6SX_PAD_KEY_COL4__AUDMUX_AUD5_RXC 0x00B4
>0x03FC 0x0664 0x4 0x0
>> +#define MX6SX_PAD_KEY_COL4__GPIO2_IO_14 0x00B4
>0x03FC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_COL4__WEIM_CRE 0x00B4
>0x03FC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_COL4__SAI2_RX_BCLK 0x00B4
>0x03FC 0x0808 0x7 0x0
>> +#define MX6SX_PAD_KEY_ROW0__KPP_ROW_0 0x00B8
>0x0400 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_ROW0__USDHC3_WP 0x00B8
>0x0400 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_ROW0__UART6_CTS_B 0x00B8
>0x0400 0x0854 0x2 0x3
>> +#define MX6SX_PAD_KEY_ROW0__ECSPI1_MOSI 0x00B8
>0x0400 0x0718 0x3 0x0
>> +#define MX6SX_PAD_KEY_ROW0__AUDMUX_AUD5_TXD 0x00B8
>0x0400 0x0660 0x4 0x0
>> +#define MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x00B8
>0x0400 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_ROW0__SDMA_EXT_EVENT_0 0x00B8
>0x0400 0x081C 0x6 0x1
>> +#define MX6SX_PAD_KEY_ROW0__SAI2_TX_DATA_0 0x00B8
>0x0400 0x0000 0x7 0x0
>> +#define MX6SX_PAD_KEY_ROW0__GPU_IDLE 0x00B8
>0x0400 0x0000 0x8 0x0
>> +#define MX6SX_PAD_KEY_ROW1__KPP_ROW_1 0x00BC
>0x0404 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_ROW1__USDHC4_VSELECT 0x00BC
>0x0404 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_ROW1__UART6_RX 0x00BC
>0x0404 0x0858 0x2 0x3
>> +#define MX6SX_PAD_KEY_ROW1__UART6_TX 0x00BC
>0x0404 0x0000 0x2 0x0
>> +#define MX6SX_PAD_KEY_ROW1__ECSPI1_SS0 0x00BC
>0x0404 0x071C 0x3 0x0
>> +#define MX6SX_PAD_KEY_ROW1__AUDMUX_AUD5_RXD 0x00BC
>0x0404 0x065C 0x4 0x0
>> +#define MX6SX_PAD_KEY_ROW1__GPIO2_IO_16 0x00BC
>0x0404 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_ROW1__WEIM_DATA_31 0x00BC
>0x0404 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_ROW1__SAI2_RX_DATA_0 0x00BC
>0x0404 0x080C 0x7 0x0
>> +#define MX6SX_PAD_KEY_ROW1__M4_NMI 0x00BC
>0x0404 0x0000 0x8 0x0
>> +#define MX6SX_PAD_KEY_ROW2__KPP_ROW_2 0x00C0
>0x0408 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_ROW2__USDHC4_WP 0x00C0
>0x0408 0x0878 0x1 0x1
>> +#define MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x00C0
>0x0408 0x084C 0x2 0x3
>> +#define MX6SX_PAD_KEY_ROW2__CAN1_RX 0x00C0
>0x0408 0x068C 0x3 0x1
>> +#define MX6SX_PAD_KEY_ROW2__CANFD_RX1 0x00C0
>0x0408 0x0694 0x4 0x1
>> +#define MX6SX_PAD_KEY_ROW2__GPIO2_IO_17 0x00C0
>0x0408 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_ROW2__WEIM_DATA_29 0x00C0
>0x0408 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_ROW2__ECSPI1_SS3 0x00C0
>0x0408 0x0000 0x7 0x0
>> +#define MX6SX_PAD_KEY_ROW3__KPP_ROW_3 0x00C4
>0x040C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_ROW3__USDHC3_LCTL 0x00C4
>0x040C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_KEY_ROW3__UART5_RX 0x00C4
>0x040C 0x0850 0x2 0x3
>> +#define MX6SX_PAD_KEY_ROW3__UART5_TX 0x00C4
>0x040C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_KEY_ROW3__CAN2_RX 0x00C4
>0x040C 0x0690 0x3 0x1
>> +#define MX6SX_PAD_KEY_ROW3__CANFD_RX2 0x00C4
>0x040C 0x0698 0x4 0x1
>> +#define MX6SX_PAD_KEY_ROW3__GPIO2_IO_18 0x00C4
>0x040C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_ROW3__WEIM_DTACK_B 0x00C4
>0x040C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_ROW3__ECSPI1_SS1 0x00C4
>0x040C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_KEY_ROW4__KPP_ROW_4 0x00C8
>0x0410 0x0000 0x0 0x0
>> +#define MX6SX_PAD_KEY_ROW4__ENET2_MDIO 0x00C8
>0x0410 0x0770 0x1 0x3
>> +#define MX6SX_PAD_KEY_ROW4__I2C3_SDA 0x00C8
>0x0410 0x07BC 0x2 0x2
>> +#define MX6SX_PAD_KEY_ROW4__USDHC1_LCTL 0x00C8
>0x0410 0x0000 0x3 0x0
>> +#define MX6SX_PAD_KEY_ROW4__AUDMUX_AUD5_RXFS 0x00C8
>0x0410 0x0668 0x4 0x0
>> +#define MX6SX_PAD_KEY_ROW4__GPIO2_IO_19 0x00C8
>0x0410 0x0000 0x5 0x0
>> +#define MX6SX_PAD_KEY_ROW4__WEIM_ACLK_FREERUN 0x00C8
>0x0410 0x0000 0x6 0x0
>> +#define MX6SX_PAD_KEY_ROW4__SAI2_RX_SYNC 0x00C8
>0x0410 0x0810 0x7 0x0
>> +#define MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x00CC
>0x0414 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_CLK__LCDIF1_WR_RWN 0x00CC
>0x0414 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_CLK__AUDMUX_AUD3_RXC 0x00CC
>0x0414 0x0634 0x2 0x1
>> +#define MX6SX_PAD_LCD1_CLK__ENET1_1588_EVENT2_IN 0x00CC
>0x0414 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_CLK__CSI1_DATA_16 0x00CC
>0x0414 0x06DC 0x4 0x0
>> +#define MX6SX_PAD_LCD1_CLK__GPIO3_IO_0 0x00CC
>0x0414 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_CLK__USDHC1_WP 0x00CC
>0x0414 0x0868 0x6 0x0
>> +#define MX6SX_PAD_LCD1_CLK__SIM_M_HADDR_16 0x00CC
>0x0414 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_CLK__VADC_TEST_0 0x00CC
>0x0414 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_CLK__MMDC_DEBUG_0 0x00CC
>0x0414 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x00D0
>0x0418 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__WEIM_CS1_B 0x00D0
>0x0418 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__M4_TRACE_0 0x00D0
>0x0418 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__KITTEN_TRACE_0 0x00D0
>0x0418 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__CSI1_DATA_20 0x00D0
>0x0418 0x06EC 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__GPIO3_IO_1 0x00D0
>0x0418 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__SRC_BT_CFG_0 0x00D0
>0x0418 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__SIM_M_HADDR_21 0x00D0
>0x0418 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__VADC_TEST_5 0x00D0
>0x0418 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA00__MMDC_DEBUG_5 0x00D0
>0x0418 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x00D4
>0x041C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__WEIM_CS2_B 0x00D4
>0x041C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__M4_TRACE_1 0x00D4
>0x041C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__KITTEN_TRACE_1 0x00D4
>0x041C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__CSI1_DATA_21 0x00D4
>0x041C 0x06F0 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__GPIO3_IO_2 0x00D4
>0x041C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__SRC_BT_CFG_1 0x00D4
>0x041C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__SIM_M_HADDR_22 0x00D4
>0x041C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__VADC_TEST_6 0x00D4
>0x041C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA01__MMDC_DEBUG_6 0x00D4
>0x041C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x00D8
>0x0420 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__WEIM_CS3_B 0x00D8
>0x0420 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__M4_TRACE_2 0x00D8
>0x0420 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__KITTEN_TRACE_2 0x00D8
>0x0420 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__CSI1_DATA_22 0x00D8
>0x0420 0x06F4 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__GPIO3_IO_3 0x00D8
>0x0420 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__SRC_BT_CFG_2 0x00D8
>0x0420 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__SIM_M_HADDR_23 0x00D8
>0x0420 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__VADC_TEST_7 0x00D8
>0x0420 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA02__MMDC_DEBUG_7 0x00D8
>0x0420 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x00DC
>0x0424 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__WEIM_ADDR_24 0x00DC
>0x0424 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__M4_TRACE_3 0x00DC
>0x0424 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__KITTEN_TRACE_3 0x00DC
>0x0424 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__CSI1_DATA_23 0x00DC
>0x0424 0x06F8 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__GPIO3_IO_4 0x00DC
>0x0424 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__SRC_BT_CFG_3 0x00DC
>0x0424 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__SIM_M_HADDR_24 0x00DC
>0x0424 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__VADC_TEST_8 0x00DC
>0x0424 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA03__MMDC_DEBUG_8 0x00DC
>0x0424 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x00E0
>0x0428 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__WEIM_ADDR_25 0x00E0
>0x0428 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__KITTEN_TRACE_4 0x00E0
>0x0428 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__CSI1_VSYNC 0x00E0
>0x0428 0x0708 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA04__GPIO3_IO_5 0x00E0
>0x0428 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__SRC_BT_CFG_4 0x00E0
>0x0428 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__SIM_M_HADDR_25 0x00E0
>0x0428 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__VADC_TEST_9 0x00E0
>0x0428 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA04__MMDC_DEBUG_9 0x00E0
>0x0428 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x00E4
>0x042C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__WEIM_ADDR_26 0x00E4
>0x042C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__KITTEN_TRACE_5 0x00E4
>0x042C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__CSI1_HSYNC 0x00E4
>0x042C 0x0700 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA05__GPIO3_IO_6 0x00E4
>0x042C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__SRC_BT_CFG_5 0x00E4
>0x042C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__SIM_M_HADDR_26 0x00E4
>0x042C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__VADC_TEST_10 0x00E4
>0x042C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA05__MMDC_DEBUG_10 0x00E4
>0x042C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x00E8
>0x0430 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__WEIM_EB_B_2 0x00E8
>0x0430 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__KITTEN_TRACE_6 0x00E8
>0x0430 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__CSI1_PIXCLK 0x00E8
>0x0430 0x0704 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA06__GPIO3_IO_7 0x00E8
>0x0430 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__SRC_BT_CFG_6 0x00E8
>0x0430 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__SIM_M_HADDR_27 0x00E8
>0x0430 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__VADC_TEST_11 0x00E8
>0x0430 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA06__MMDC_DEBUG_11 0x00E8
>0x0430 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x00EC
>0x0434 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__WEIM_EB_B_3 0x00EC
>0x0434 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__KITTEN_TRACE_7 0x00EC
>0x0434 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__CSI1_MCLK 0x00EC
>0x0434 0x0000 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__GPIO3_IO_8 0x00EC
>0x0434 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__SRC_BT_CFG_7 0x00EC
>0x0434 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__SIM_M_HADDR_28 0x00EC
>0x0434 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__VADC_TEST_12 0x00EC
>0x0434 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA07__MMDC_DEBUG_12 0x00EC
>0x0434 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x00F0
>0x0438 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__WEIM_AD_8 0x00F0
>0x0438 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__KITTEN_TRACE_8 0x00F0
>0x0438 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__CSI1_DATA_9 0x00F0
>0x0438 0x06C4 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA08__GPIO3_IO_9 0x00F0
>0x0438 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__SRC_BT_CFG_8 0x00F0
>0x0438 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__SIM_M_HADDR_29 0x00F0
>0x0438 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__VADC_TEST_13 0x00F0
>0x0438 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA08__MMDC_DEBUG_13 0x00F0
>0x0438 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x00F4
>0x043C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__WEIM_AD_9 0x00F4
>0x043C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__KITTEN_TRACE_9 0x00F4
>0x043C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__CSI1_DATA_8 0x00F4
>0x043C 0x06C0 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA09__GPIO3_IO_10 0x00F4
>0x043C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__SRC_BT_CFG_9 0x00F4
>0x043C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__SIM_M_HADDR_30 0x00F4
>0x043C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__VADC_TEST_14 0x00F4
>0x043C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA09__MMDC_DEBUG_14 0x00F4
>0x043C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x00F8
>0x0440 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__WEIM_AD_10 0x00F8
>0x0440 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__KITTEN_TRACE_10 0x00F8
>0x0440 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__CSI1_DATA_7 0x00F8
>0x0440 0x06BC 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA10__GPIO3_IO_11 0x00F8
>0x0440 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__SRC_BT_CFG_10 0x00F8
>0x0440 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__SIM_M_HADDR_31 0x00F8
>0x0440 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__VADC_TEST_15 0x00F8
>0x0440 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA10__MMDC_DEBUG_15 0x00F8
>0x0440 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x00FC
>0x0444 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__WEIM_AD_11 0x00FC
>0x0444 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__KITTEN_TRACE_11 0x00FC
>0x0444 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__CSI1_DATA_6 0x00FC
>0x0444 0x06B8 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA11__GPIO3_IO_12 0x00FC
>0x0444 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__SRC_BT_CFG_11 0x00FC
>0x0444 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__SIM_M_HBURST_0 0x00FC
>0x0444 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__VADC_TEST_16 0x00FC
>0x0444 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA11__MMDC_DEBUG_16 0x00FC
>0x0444 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x0100
>0x0448 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__WEIM_AD_12 0x0100
>0x0448 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__KITTEN_TRACE_12 0x0100
>0x0448 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__CSI1_DATA_5 0x0100
>0x0448 0x06B4 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA12__GPIO3_IO_13 0x0100
>0x0448 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__SRC_BT_CFG_12 0x0100
>0x0448 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__SIM_M_HBURST_1 0x0100
>0x0448 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__VADC_TEST_17 0x0100
>0x0448 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA12__MMDC_DEBUG_17 0x0100
>0x0448 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x0104
>0x044C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__WEIM_AD_13 0x0104
>0x044C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__KITTEN_TRACE_13 0x0104
>0x044C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__CSI1_DATA_4 0x0104
>0x044C 0x06B0 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA13__GPIO3_IO_14 0x0104
>0x044C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__SRC_BT_CFG_13 0x0104
>0x044C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__SIM_M_HBURST_2 0x0104
>0x044C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__VADC_TEST_18 0x0104
>0x044C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA13__MMDC_DEBUG_18 0x0104
>0x044C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x0108
>0x0450 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__WEIM_AD_14 0x0108
>0x0450 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__KITTEN_TRACE_14 0x0108
>0x0450 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__CSI1_DATA_3 0x0108
>0x0450 0x06AC 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA14__GPIO3_IO_15 0x0108
>0x0450 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__SRC_BT_CFG_14 0x0108
>0x0450 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__SIM_M_HMASTLOCK 0x0108
>0x0450 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__VADC_TEST_19 0x0108
>0x0450 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA14__MMDC_DEBUG_19 0x0108
>0x0450 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x010C
>0x0454 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__WEIM_AD_15 0x010C
>0x0454 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__KITTEN_TRACE_15 0x010C
>0x0454 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__CSI1_DATA_2 0x010C
>0x0454 0x06A8 0x4 0x1
>> +#define MX6SX_PAD_LCD1_DATA15__GPIO3_IO_16 0x010C
>0x0454 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__SRC_BT_CFG_15 0x010C
>0x0454 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__SIM_M_HPROT_0 0x010C
>0x0454 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__VDEC_DEBUG_0 0x010C
>0x0454 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA15__MMDC_DEBUG_20 0x010C
>0x0454 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x0110
>0x0458 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__WEIM_ADDR_16 0x0110
>0x0458 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__M4_TRACE_CLK 0x0110
>0x0458 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__KITTEN_TRACE_CLK 0x0110
>0x0458 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__CSI1_DATA_1 0x0110
>0x0458 0x06A4 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__GPIO3_IO_17 0x0110
>0x0458 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__SRC_BT_CFG_24 0x0110
>0x0458 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__SIM_M_HPROT_1 0x0110
>0x0458 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__VDEC_DEBUG_1 0x0110
>0x0458 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA16__MMDC_DEBUG_21 0x0110
>0x0458 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x0114
>0x045C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__WEIM_ADDR_17 0x0114
>0x045C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__KITTEN_TRACE_CTL 0x0114
>0x045C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__CSI1_DATA_0 0x0114
>0x045C 0x06A0 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__GPIO3_IO_18 0x0114
>0x045C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__SRC_BT_CFG_25 0x0114
>0x045C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__SIM_M_HPROT_2 0x0114
>0x045C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__VDEC_DEBUG_2 0x0114
>0x045C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA17__MMDC_DEBUG_22 0x0114
>0x045C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x0118
>0x0460 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__WEIM_ADDR_18 0x0118
>0x0460 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__M4_EVENTO 0x0118
>0x0460 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__KITTEN_EVENTO 0x0118
>0x0460 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__CSI1_DATA_15 0x0118
>0x0460 0x06D8 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__GPIO3_IO_19 0x0118
>0x0460 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__SRC_BT_CFG_26 0x0118
>0x0460 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__SIM_M_HPROT_3 0x0118
>0x0460 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__VDEC_DEBUG_3 0x0118
>0x0460 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA18__MMDC_DEBUG_23 0x0118
>0x0460 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x011C
>0x0464 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__WEIM_ADDR_19 0x011C
>0x0464 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__M4_TRACE_SWO 0x011C
>0x0464 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__CSI1_DATA_14 0x011C
>0x0464 0x06D4 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__GPIO3_IO_20 0x011C
>0x0464 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__SRC_BT_CFG_27 0x011C
>0x0464 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__SIM_M_HREADYOUT 0x011C
>0x0464 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__VDEC_DEBUG_4 0x011C
>0x0464 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA19__MMDC_DEBUG_24 0x011C
>0x0464 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x0120
>0x0468 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__WEIM_ADDR_20 0x0120
>0x0468 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__PWM8_OUT 0x0120
>0x0468 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__ENET1_1588_EVENT2_OUT 0x0120
>0x0468 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__CSI1_DATA_13 0x0120
>0x0468 0x06D0 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__GPIO3_IO_21 0x0120
>0x0468 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__SRC_BT_CFG_28 0x0120
>0x0468 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__SIM_M_HRESP 0x0120
>0x0468 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__VDEC_DEBUG_5 0x0120
>0x0468 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA20__MMDC_DEBUG_25 0x0120
>0x0468 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x0124
>0x046C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__WEIM_ADDR_21 0x0124
>0x046C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__PWM7_OUT 0x0124
>0x046C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__ENET1_1588_EVENT3_OUT 0x0124
>0x046C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__CSI1_DATA_12 0x0124
>0x046C 0x06CC 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__GPIO3_IO_22 0x0124
>0x046C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__SRC_BT_CFG_29 0x0124
>0x046C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__SIM_M_HSIZE_0 0x0124
>0x046C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__VDEC_DEBUG_6 0x0124
>0x046C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA21__MMDC_DEBUG_26 0x0124
>0x046C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x0128
>0x0470 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__WEIM_ADDR_22 0x0128
>0x0470 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__PWM6_OUT 0x0128
>0x0470 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__ENET2_1588_EVENT2_OUT 0x0128
>0x0470 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__CSI1_DATA_11 0x0128
>0x0470 0x06C8 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__GPIO3_IO_23 0x0128
>0x0470 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__SRC_BT_CFG_30 0x0128
>0x0470 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__SIM_M_HSIZE_1 0x0128
>0x0470 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__VDEC_DEBUG_7 0x0128
>0x0470 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA22__MMDC_DEBUG_27 0x0128
>0x0470 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x012C
>0x0474 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__WEIM_ADDR_23 0x012C
>0x0474 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__PWM5_OUT 0x012C
>0x0474 0x0000 0x2 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__ENET2_1588_EVENT3_OUT 0x012C
>0x0474 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__CSI1_DATA_10 0x012C
>0x0474 0x06FC 0x4 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__GPIO3_IO_24 0x012C
>0x0474 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__SRC_BT_CFG_31 0x012C
>0x0474 0x0000 0x6 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__SIM_M_HSIZE_2 0x012C
>0x0474 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__VDEC_DEBUG_8 0x012C
>0x0474 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_DATA23__MMDC_DEBUG_28 0x012C
>0x0474 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x0130
>0x0478 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__LCDIF1_RD_E 0x0130
>0x0478 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__AUDMUX_AUD3_TXC 0x0130
>0x0478 0x063C 0x2 0x1
>> +#define MX6SX_PAD_LCD1_ENABLE__ENET1_1588_EVENT3_IN 0x0130
>0x0478 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__CSI1_DATA_17 0x0130
>0x0478 0x06E0 0x4 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__GPIO3_IO_25 0x0130
>0x0478 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__USDHC1_CD_B 0x0130
>0x0478 0x0864 0x6 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__SIM_M_HADDR_17 0x0130
>0x0478 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__VADC_TEST_1 0x0130
>0x0478 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_ENABLE__MMDC_DEBUG_1 0x0130
>0x0478 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x0134
>0x047C 0x07E0 0x0 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__LCDIF1_RS 0x0134
>0x047C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__AUDMUX_AUD3_TXD 0x0134
>0x047C 0x0630 0x2 0x1
>> +#define MX6SX_PAD_LCD1_HSYNC__ENET2_1588_EVENT2_IN 0x0134
>0x047C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__CSI1_DATA_18 0x0134
>0x047C 0x06E4 0x4 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__GPIO3_IO_26 0x0134
>0x047C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__USDHC2_WP 0x0134
>0x047C 0x0870 0x6 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__SIM_M_HADDR_18 0x0134
>0x047C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__VADC_TEST_2 0x0134
>0x047C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_HSYNC__MMDC_DEBUG_2 0x0134
>0x047C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_RESET__LCDIF1_RESET 0x0138
>0x0480 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_RESET__LCDIF1_CS 0x0138
>0x0480 0x0000 0x1 0x0
>> +#define MX6SX_PAD_LCD1_RESET__AUDMUX_AUD3_RXD 0x0138
>0x0480 0x062C 0x2 0x1
>> +#define MX6SX_PAD_LCD1_RESET__KITTEN_EVENTI 0x0138
>0x0480 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_RESET__M4_EVENTI 0x0138
>0x0480 0x0000 0x4 0x0
>> +#define MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x0138
>0x0480 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_RESET__CCM_PMIC_RDY 0x0138
>0x0480 0x069C 0x6 0x0
>> +#define MX6SX_PAD_LCD1_RESET__SIM_M_HADDR_20 0x0138
>0x0480 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_RESET__VADC_TEST_4 0x0138
>0x0480 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_RESET__MMDC_DEBUG_4 0x0138
>0x0480 0x0000 0x9 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x013C
>0x0484 0x0000 0x0 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__LCDIF1_BUSY 0x013C
>0x0484 0x07E0 0x1 0x1
>> +#define MX6SX_PAD_LCD1_VSYNC__AUDMUX_AUD3_TXFS 0x013C
>0x0484 0x0640 0x2 0x1
>> +#define MX6SX_PAD_LCD1_VSYNC__ENET2_1588_EVENT3_IN 0x013C
>0x0484 0x0000 0x3 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__CSI1_DATA_19 0x013C
>0x0484 0x06E8 0x4 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__GPIO3_IO_28 0x013C
>0x0484 0x0000 0x5 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__USDHC2_CD_B 0x013C
>0x0484 0x086C 0x6 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__SIM_M_HADDR_19 0x013C
>0x0484 0x0000 0x7 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__VADC_TEST_3 0x013C
>0x0484 0x0000 0x8 0x0
>> +#define MX6SX_PAD_LCD1_VSYNC__MMDC_DEBUG_3 0x013C
>0x0484 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_ALE__RAWNAND_ALE 0x0140
>0x0488 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_ALE__I2C3_SDA 0x0140
>0x0488 0x07BC 0x1 0x0
>> +#define MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x0140
>0x0488 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_ALE__ECSPI2_SS0 0x0140
>0x0488 0x072C 0x3 0x0
>> +#define MX6SX_PAD_NAND_ALE__ESAI_TX3_RX2 0x0140
>0x0488 0x079C 0x4 0x0
>> +#define MX6SX_PAD_NAND_ALE__GPIO4_IO_0 0x0140
>0x0488 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_ALE__WEIM_CS0_B 0x0140
>0x0488 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_ALE__TPSMP_HDATA_0 0x0140
>0x0488 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_ALE__ANATOP_USBPHY1_TSTI_TX_EN 0x0140
>0x0488 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_ALE__SDMA_DEBUG_PC_12 0x0140
>0x0488 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__RAWNAND_CE0_B 0x0144
>0x048C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__USDHC2_VSELECT 0x0144
>0x048C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x0144
>0x048C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__AUDMUX_AUD4_TXC 0x0144
>0x048C 0x0654 0x3 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__ESAI_TX_CLK 0x0144
>0x048C 0x078C 0x4 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__GPIO4_IO_1 0x0144
>0x048C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__WEIM_LBA_B 0x0144
>0x048C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__TPSMP_HDATA_3 0x0144
>0x048C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__ANATOP_USBPHY1_TSTI_TX_HIZ 0x0144
>0x048C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_CE0_B__SDMA_DEBUG_PC_9 0x0144
>0x048C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__RAWNAND_CE1_B 0x0148
>0x0490 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__USDHC3_RESET_B 0x0148
>0x0490 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x0148
>0x0490 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__AUDMUX_AUD4_TXD 0x0148
>0x0490 0x0648 0x3 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__ESAI_TX0 0x0148
>0x0490 0x0790 0x4 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__GPIO4_IO_2 0x0148
>0x0490 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__WEIM_OE 0x0148
>0x0490 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__TPSMP_HDATA_4 0x0148
>0x0490 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__ANATOP_USBPHY1_TSTI_TX_LS_MODE 0x0148
>0x0490 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_CE1_B__SDMA_DEBUG_PC_8 0x0148
>0x0490 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_CLE__RAWNAND_CLE 0x014C
>0x0494 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_CLE__I2C3_SCL 0x014C
>0x0494 0x07B8 0x1 0x0
>> +#define MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x014C
>0x0494 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_CLE__ECSPI2_SCLK 0x014C
>0x0494 0x0720 0x3 0x0
>> +#define MX6SX_PAD_NAND_CLE__ESAI_TX2_RX3 0x014C
>0x0494 0x0798 0x4 0x0
>> +#define MX6SX_PAD_NAND_CLE__GPIO4_IO_3 0x014C
>0x0494 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_CLE__WEIM_BCLK 0x014C
>0x0494 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_CLE__TPSMP_CLK 0x014C
>0x0494 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_CLE__ANATOP_USBPHY1_TSTI_TX_DP 0x014C
>0x0494 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_CLE__SDMA_DEBUG_PC_13 0x014C
>0x0494 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA00__RAWNAND_DATA00 0x0150
>0x0498 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA00__USDHC1_DATA4 0x0150
>0x0498 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x0150
>0x0498 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA00__ECSPI5_MISO 0x0150
>0x0498 0x0754 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA00__ESAI_RX_CLK 0x0150
>0x0498 0x0788 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA00__GPIO4_IO_4 0x0150
>0x0498 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA00__WEIM_AD_0 0x0150
>0x0498 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA00__TPSMP_HDATA_7 0x0150
>0x0498 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA00__ANATOP_USBPHY1_TSTO_RX_DISCON_DET 0x0150
>0x0498 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA00__SDMA_DEBUG_EVT_CHN_LINES_5 0x0150
>0x0498 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA01__RAWNAND_DATA01 0x0154
>0x049C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA01__USDHC1_DATA5 0x0154
>0x049C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x0154
>0x049C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA01__ECSPI5_MOSI 0x0154
>0x049C 0x0758 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA01__ESAI_RX_FS 0x0154
>0x049C 0x0778 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA01__GPIO4_IO_5 0x0154
>0x049C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA01__WEIM_AD_1 0x0154
>0x049C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA01__TPSMP_HDATA_8 0x0154
>0x049C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA01__ANATOP_USBPHY1_TSTO_RX_HS_RXD 0x0154
>0x049C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA01__SDMA_DEBUG_EVT_CHN_LINES_4 0x0154
>0x049C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA02__RAWNAND_DATA02 0x0158
>0x04A0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA02__USDHC1_DATA6 0x0158
>0x04A0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x0158
>0x04A0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA02__ECSPI5_SCLK 0x0158
>0x04A0 0x0750 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA02__ESAI_TX_HF_CLK 0x0158
>0x04A0 0x0784 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA02__GPIO4_IO_6 0x0158
>0x04A0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA02__WEIM_AD_2 0x0158
>0x04A0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA02__TPSMP_HDATA_9 0x0158
>0x04A0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA02__ANATOP_USBPHY2_TSTO_PLL_CLK20DIV 0x0158
>0x04A0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA02__SDMA_DEBUG_EVT_CHN_LINES_3 0x0158
>0x04A0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA03__RAWNAND_DATA03 0x015C
>0x04A4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA03__USDHC1_DATA7 0x015C
>0x04A4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x015C
>0x04A4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA03__ECSPI5_SS0 0x015C
>0x04A4 0x075C 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA03__ESAI_RX_HF_CLK 0x015C
>0x04A4 0x0780 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA03__GPIO4_IO_7 0x015C
>0x04A4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA03__WEIM_AD_3 0x015C
>0x04A4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA03__TPSMP_HDATA_10 0x015C
>0x04A4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA03__ANATOP_USBPHY1_TSTO_RX_SQUELCH 0x015C
>0x04A4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA03__SDMA_DEBUG_EVT_CHN_LINES_6 0x015C
>0x04A4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA04__RAWNAND_DATA04 0x0160
>0x04A8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA04__USDHC2_DATA4 0x0160
>0x04A8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA04__QSPI2_B_SS1_B 0x0160
>0x04A8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA04__UART3_RTS_B 0x0160
>0x04A8 0x083C 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA04__AUDMUX_AUD4_RXFS 0x0160
>0x04A8 0x0650 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA04__GPIO4_IO_8 0x0160
>0x04A8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA04__WEIM_AD_4 0x0160
>0x04A8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA04__TPSMP_HDATA_11 0x0160
>0x04A8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA04__ANATOP_USBPHY2_TSTO_RX_SQUELCH 0x0160
>0x04A8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA04__SDMA_DEBUG_CORE_STATE_0 0x0160
>0x04A8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA05__RAWNAND_DATA05 0x0164
>0x04AC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA05__USDHC2_DATA5 0x0164
>0x04AC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA05__QSPI2_B_DQS 0x0164
>0x04AC 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA05__UART3_CTS_B 0x0164
>0x04AC 0x083C 0x3 0x1
>> +#define MX6SX_PAD_NAND_DATA05__AUDMUX_AUD4_RXC 0x0164
>0x04AC 0x064C 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA05__GPIO4_IO_9 0x0164
>0x04AC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA05__WEIM_AD_5 0x0164
>0x04AC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA05__TPSMP_HDATA_12 0x0164
>0x04AC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA05__ANATOP_USBPHY2_TSTO_RX_DISCON_DET 0x0164
>0x04AC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA05__SDMA_DEBUG_CORE_STATE_1 0x0164
>0x04AC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA06__RAWNAND_DATA06 0x0168
>0x04B0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA06__USDHC2_DATA6 0x0168
>0x04B0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA06__QSPI2_A_SS1_B 0x0168
>0x04B0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA06__UART3_RX 0x0168
>0x04B0 0x0840 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA06__UART3_TX 0x0168
>0x04B0 0x0000 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA06__PWM3_OUT 0x0168
>0x04B0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA06__GPIO4_IO_10 0x0168
>0x04B0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA06__WEIM_AD_6 0x0168
>0x04B0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA06__TPSMP_HDATA_13 0x0168
>0x04B0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA06__ANATOP_USBPHY2_TSTO_RX_FS_RXD 0x0168
>0x04B0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA06__SDMA_DEBUG_CORE_STATE_2 0x0168
>0x04B0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_DATA07__RAWNAND_DATA07 0x016C
>0x04B4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_DATA07__USDHC2_DATA7 0x016C
>0x04B4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_DATA07__QSPI2_A_DQS 0x016C
>0x04B4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_DATA07__UART3_RX 0x016C
>0x04B4 0x0840 0x3 0x1
>> +#define MX6SX_PAD_NAND_DATA07__UART3_TX 0x016C
>0x04B4 0x0000 0x3 0x0
>> +#define MX6SX_PAD_NAND_DATA07__PWM4_OUT 0x016C
>0x04B4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_NAND_DATA07__GPIO4_IO_11 0x016C
>0x04B4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_DATA07__WEIM_AD_7 0x016C
>0x04B4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_DATA07__TPSMP_HDATA_14 0x016C
>0x04B4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_DATA07__ANATOP_USBPHY1_TSTO_RX_FS_RXD 0x016C
>0x04B4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_DATA07__SDMA_DEBUG_CORE_STATE_3 0x016C
>0x04B4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_RE_B__RAWNAND_RE_B 0x0170
>0x04B8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_RE_B__USDHC2_RESET_B 0x0170
>0x04B8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x0170
>0x04B8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_RE_B__AUDMUX_AUD4_TXFS 0x0170
>0x04B8 0x0658 0x3 0x0
>> +#define MX6SX_PAD_NAND_RE_B__ESAI_TX_FS 0x0170
>0x04B8 0x077C 0x4 0x0
>> +#define MX6SX_PAD_NAND_RE_B__GPIO4_IO_12 0x0170
>0x04B8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_RE_B__WEIM_RW 0x0170
>0x04B8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_RE_B__TPSMP_HDATA_5 0x0170
>0x04B8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_RE_B__ANATOP_USBPHY2_TSTO_RX_HS_RXD 0x0170
>0x04B8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_RE_B__SDMA_DEBUG_PC_7 0x0170
>0x04B8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_READY_B__RAWNAND_READY_B 0x0174
>0x04BC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_READY_B__USDHC1_VSELECT 0x0174
>0x04BC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x0174
>0x04BC 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_READY_B__ECSPI2_MISO 0x0174
>0x04BC 0x0724 0x3 0x0
>> +#define MX6SX_PAD_NAND_READY_B__ESAI_TX1 0x0174
>0x04BC 0x0794 0x4 0x0
>> +#define MX6SX_PAD_NAND_READY_B__GPIO4_IO_13 0x0174
>0x04BC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_READY_B__WEIM_EB_B_1 0x0174
>0x04BC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_READY_B__TPSMP_HDATA_2 0x0174
>0x04BC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_READY_B__ANATOP_USBPHY1_TSTI_TX_DN 0x0174
>0x04BC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_READY_B__SDMA_DEBUG_PC_10 0x0174
>0x04BC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_WE_B__RAWNAND_WE_B 0x0178
>0x04C0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_WE_B__USDHC4_VSELECT 0x0178
>0x04C0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x0178
>0x04C0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_WE_B__AUDMUX_AUD4_RXD 0x0178
>0x04C0 0x0644 0x3 0x0
>> +#define MX6SX_PAD_NAND_WE_B__ESAI_TX5_RX0 0x0178
>0x04C0 0x07A4 0x4 0x0
>> +#define MX6SX_PAD_NAND_WE_B__GPIO4_IO_14 0x0178
>0x04C0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_WE_B__WEIM_WAIT 0x0178
>0x04C0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_WE_B__TPSMP_HDATA_6 0x0178
>0x04C0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_WE_B__ANATOP_USBPHY1_TSTO_PLL_CLK20DIV 0x0178
>0x04C0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_WE_B__SDMA_DEBUG_PC_6 0x0178
>0x04C0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_NAND_WP_B__RAWNAND_WP_B 0x017C
>0x04C4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_NAND_WP_B__USDHC1_RESET_B 0x017C
>0x04C4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x017C
>0x04C4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_NAND_WP_B__ECSPI2_MOSI 0x017C
>0x04C4 0x0728 0x3 0x0
>> +#define MX6SX_PAD_NAND_WP_B__ESAI_TX4_RX1 0x017C
>0x04C4 0x07A0 0x4 0x0
>> +#define MX6SX_PAD_NAND_WP_B__GPIO4_IO_15 0x017C
>0x04C4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_NAND_WP_B__WEIM_EB_B_0 0x017C
>0x04C4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_NAND_WP_B__TPSMP_HDATA_1 0x017C
>0x04C4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_NAND_WP_B__ANATOP_USBPHY1_TSTI_TX_HS_MODE 0x017C
>0x04C4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_NAND_WP_B__SDMA_DEBUG_PC_11 0x017C
>0x04C4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA0__QSPI1_A_DATA_0 0x0180
>0x04C8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA0__USB_OTG2_OC 0x0180
>0x04C8 0x085C 0x1 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA0__ECSPI1_MOSI 0x0180
>0x04C8 0x0718 0x2 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA0__ESAI_TX4_RX1 0x0180
>0x04C8 0x07A0 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA0__CSI1_DATA_14 0x0180
>0x04C8 0x06D4 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x0180
>0x04C8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA0__WEIM_DATA_6 0x0180
>0x04C8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA0__SIM_M_HADDR_3 0x0180
>0x04C8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA0__SDMA_DEBUG_BUS_DEVICE_3 0x0180
>0x04C8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA1__QSPI1_A_DATA_1 0x0184
>0x04CC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA1__ANATOP_OTG1_ID 0x0184
>0x04CC 0x0624 0x1 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA1__ECSPI1_MISO 0x0184
>0x04CC 0x0714 0x2 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA1__ESAI_TX1 0x0184
>0x04CC 0x0794 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA1__CSI1_DATA_13 0x0184
>0x04CC 0x06D0 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA1__GPIO4_IO_17 0x0184
>0x04CC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA1__WEIM_DATA_5 0x0184
>0x04CC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA1__SIM_M_HADDR_4 0x0184
>0x04CC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA1__SDMA_DEBUG_PC_0 0x0184
>0x04CC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__QSPI1_A_DATA_2 0x0188
>0x04D0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__USB_OTG1_PWR 0x0188
>0x04D0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__ECSPI5_SS1 0x0188
>0x04D0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__ESAI_TX_CLK 0x0188
>0x04D0 0x078C 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA2__CSI1_DATA_12 0x0188
>0x04D0 0x06CC 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA2__GPIO4_IO_18 0x0188
>0x04D0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__WEIM_DATA_4 0x0188
>0x04D0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__SIM_M_HADDR_6 0x0188
>0x04D0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA2__SDMA_DEBUG_PC_1 0x0188
>0x04D0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__QSPI1_A_DATA_3 0x018C
>0x04D4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__USB_OTG1_OC 0x018C
>0x04D4 0x0860 0x1 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA3__ECSPI5_SS2 0x018C
>0x04D4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__ESAI_TX0 0x018C
>0x04D4 0x0790 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_DATA3__CSI1_DATA_11 0x018C
>0x04D4 0x06C8 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_DATA3__GPIO4_IO_19 0x018C
>0x04D4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__WEIM_DATA_3 0x018C
>0x04D4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__SIM_M_HADDR_7 0x018C
>0x04D4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_DATA3__SDMA_DEBUG_PC_2 0x018C
>0x04D4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__QSPI1_A_DQS 0x0190
>0x04D8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__CAN2_TX 0x0190
>0x04D8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__CANFD_TX2 0x0190
>0x04D8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__ECSPI5_MOSI 0x0190
>0x04D8 0x0758 0x3 0x1
>> +#define MX6SX_PAD_QSPI1A_DQS__CSI1_DATA_15 0x0190
>0x04D8 0x06D8 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_DQS__GPIO4_IO_20 0x0190
>0x04D8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__WEIM_DATA_7 0x0190
>0x04D8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__SIM_M_HADDR_13 0x0190
>0x04D8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_DQS__SDMA_DEBUG_BUS_DEVICE_4 0x0190
>0x04D8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_SCLK__QSPI1_A_SCLK 0x0194
>0x04DC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_SCLK__ANATOP_OTG2_ID 0x0194
>0x04DC 0x0628 0x1 0x2
>> +#define MX6SX_PAD_QSPI1A_SCLK__ECSPI1_SCLK 0x0194
>0x04DC 0x0710 0x2 0x1
>> +#define MX6SX_PAD_QSPI1A_SCLK__ESAI_TX2_RX3 0x0194
>0x04DC 0x0798 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_SCLK__CSI1_DATA_1 0x0194
>0x04DC 0x06A4 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_SCLK__GPIO4_IO_21 0x0194
>0x04DC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_SCLK__WEIM_DATA_0 0x0194
>0x04DC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_SCLK__SIM_M_HADDR_0 0x0194
>0x04DC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_SCLK__SDMA_DEBUG_PC_5 0x0194
>0x04DC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__QSPI1_A_SS0_B 0x0198
>0x04E0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__USB_OTG2_PWR 0x0198
>0x04E0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__ECSPI1_SS0 0x0198
>0x04E0 0x071C 0x2 0x1
>> +#define MX6SX_PAD_QSPI1A_SS0_B__ESAI_TX3_RX2 0x0198
>0x04E0 0x079C 0x3 0x2
>> +#define MX6SX_PAD_QSPI1A_SS0_B__CSI1_DATA_0 0x0198
>0x04E0 0x06A0 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_SS0_B__GPIO4_IO_22 0x0198
>0x04E0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__WEIM_DATA_1 0x0198
>0x04E0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__SIM_M_HADDR_1 0x0198
>0x04E0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_SS0_B__SDMA_DEBUG_PC_4 0x0198
>0x04E0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1A_SS1_B__QSPI1_A_SS1_B 0x019C
>0x04E4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1A_SS1_B__CAN1_RX 0x019C
>0x04E4 0x068C 0x1 0x2
>> +#define MX6SX_PAD_QSPI1A_SS1_B__CANFD_RX1 0x019C
>0x04E4 0x0694 0x2 0x2
>> +#define MX6SX_PAD_QSPI1A_SS1_B__ECSPI5_MISO 0x019C
>0x04E4 0x0754 0x3 0x1
>> +#define MX6SX_PAD_QSPI1A_SS1_B__CSI1_DATA_10 0x019C
>0x04E4 0x06FC 0x4 0x1
>> +#define MX6SX_PAD_QSPI1A_SS1_B__GPIO4_IO_23 0x019C
>0x04E4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1A_SS1_B__WEIM_DATA_2 0x019C
>0x04E4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1A_SS1_B__SIM_M_HADDR_12 0x019C
>0x04E4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1A_SS1_B__SDMA_DEBUG_PC_3 0x019C
>0x04E4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA0__QSPI1_B_DATA_0 0x01A0
>0x04E8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA0__UART3_CTS_B 0x01A0
>0x04E8 0x083C 0x1 0x4
>> +#define MX6SX_PAD_QSPI1B_DATA0__ECSPI3_MOSI 0x01A0
>0x04E8 0x0738 0x2 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA0__ESAI_RX_FS 0x01A0
>0x04E8 0x0778 0x3 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA0__CSI1_DATA_22 0x01A0
>0x04E8 0x06F4 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA0__GPIO4_IO_24 0x01A0
>0x04E8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA0__WEIM_DATA_14 0x01A0
>0x04E8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA0__SIM_M_HADDR_9 0x01A0
>0x04E8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA1__QSPI1_B_DATA_1 0x01A4
>0x04EC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA1__UART3_RTS_B 0x01A4
>0x04EC 0x083C 0x1 0x5
>> +#define MX6SX_PAD_QSPI1B_DATA1__ECSPI3_MISO 0x01A4
>0x04EC 0x0734 0x2 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA1__ESAI_RX_CLK 0x01A4
>0x04EC 0x0788 0x3 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA1__CSI1_DATA_21 0x01A4
>0x04EC 0x06F0 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA1__GPIO4_IO_25 0x01A4
>0x04EC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA1__WEIM_DATA_13 0x01A4
>0x04EC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA1__SIM_M_HADDR_8 0x01A4
>0x04EC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA2__QSPI1_B_DATA_2 0x01A8
>0x04F0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA2__I2C2_SDA 0x01A8
>0x04F0 0x07B4 0x1 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA2__ECSPI5_RDY 0x01A8
>0x04F0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA2__ESAI_TX5_RX0 0x01A8
>0x04F0 0x07A4 0x3 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA2__CSI1_DATA_20 0x01A8
>0x04F0 0x06EC 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA2__GPIO4_IO_26 0x01A8
>0x04F0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA2__WEIM_DATA_12 0x01A8
>0x04F0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA2__SIM_M_HADDR_5 0x01A8
>0x04F0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA3__QSPI1_B_DATA_3 0x01AC
>0x04F4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA3__I2C2_SCL 0x01AC
>0x04F4 0x07B0 0x1 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA3__ECSPI5_SS3 0x01AC
>0x04F4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA3__ESAI_TX_FS 0x01AC
>0x04F4 0x077C 0x3 0x2
>> +#define MX6SX_PAD_QSPI1B_DATA3__CSI1_DATA_19 0x01AC
>0x04F4 0x06E8 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_DATA3__GPIO4_IO_27 0x01AC
>0x04F4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA3__WEIM_DATA_11 0x01AC
>0x04F4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_DATA3__SIM_M_HADDR_2 0x01AC
>0x04F4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__QSPI1_B_DQS 0x01B0
>0x04F8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__CAN1_TX 0x01B0
>0x04F8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__CANFD_TX1 0x01B0
>0x04F8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__ECSPI5_SS0 0x01B0
>0x04F8 0x075C 0x3 0x1
>> +#define MX6SX_PAD_QSPI1B_DQS__CSI1_DATA_23 0x01B0
>0x04F8 0x06F8 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_DQS__GPIO4_IO_28 0x01B0
>0x04F8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__WEIM_DATA_15 0x01B0
>0x04F8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_DQS__SIM_M_HADDR_15 0x01B0
>0x04F8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_SCLK__QSPI1_B_SCLK 0x01B4
>0x04FC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_SCLK__UART3_RX 0x01B4
>0x04FC 0x0840 0x1 0x4
>> +#define MX6SX_PAD_QSPI1B_SCLK__UART3_TX 0x01B4
>0x04FC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_SCLK__ECSPI3_SCLK 0x01B4
>0x04FC 0x0730 0x2 0x1
>> +#define MX6SX_PAD_QSPI1B_SCLK__ESAI_RX_HF_CLK 0x01B4
>0x04FC 0x0780 0x3 0x2
>> +#define MX6SX_PAD_QSPI1B_SCLK__CSI1_DATA_16 0x01B4
>0x04FC 0x06DC 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_SCLK__GPIO4_IO_29 0x01B4
>0x04FC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_SCLK__WEIM_DATA_8 0x01B4
>0x04FC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_SCLK__SIM_M_HADDR_11 0x01B4
>0x04FC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_SS0_B__QSPI1_B_SS0_B 0x01B8
>0x0500 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_RX 0x01B8
>0x0500 0x0840 0x1 0x5
>> +#define MX6SX_PAD_QSPI1B_SS0_B__UART3_TX 0x01B8
>0x0500 0x0000 0x1 0x0
>> +#define MX6SX_PAD_QSPI1B_SS0_B__ECSPI3_SS0 0x01B8
>0x0500 0x073C 0x2 0x1
>> +#define MX6SX_PAD_QSPI1B_SS0_B__ESAI_TX_HF_CLK 0x01B8
>0x0500 0x0784 0x3 0x3
>> +#define MX6SX_PAD_QSPI1B_SS0_B__CSI1_DATA_17 0x01B8
>0x0500 0x06E0 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_SS0_B__GPIO4_IO_30 0x01B8
>0x0500 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_SS0_B__WEIM_DATA_9 0x01B8
>0x0500 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_SS0_B__SIM_M_HADDR_10 0x01B8
>0x0500 0x0000 0x7 0x0
>> +#define MX6SX_PAD_QSPI1B_SS1_B__QSPI1_B_SS1_B 0x01BC
>0x0504 0x0000 0x0 0x0
>> +#define MX6SX_PAD_QSPI1B_SS1_B__CAN2_RX 0x01BC
>0x0504 0x0690 0x1 0x2
>> +#define MX6SX_PAD_QSPI1B_SS1_B__CANFD_RX2 0x01BC
>0x0504 0x0698 0x2 0x2
>> +#define MX6SX_PAD_QSPI1B_SS1_B__ECSPI5_SCLK 0x01BC
>0x0504 0x0750 0x3 0x1
>> +#define MX6SX_PAD_QSPI1B_SS1_B__CSI1_DATA_18 0x01BC
>0x0504 0x06E4 0x4 0x1
>> +#define MX6SX_PAD_QSPI1B_SS1_B__GPIO4_IO_31 0x01BC
>0x0504 0x0000 0x5 0x0
>> +#define MX6SX_PAD_QSPI1B_SS1_B__WEIM_DATA_10 0x01BC
>0x0504 0x0000 0x6 0x0
>> +#define MX6SX_PAD_QSPI1B_SS1_B__SIM_M_HADDR_14 0x01BC
>0x0504 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x01C0
>0x0508 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__GPIO5_IO_0 0x01C0
>0x0508 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__CSI2_DATA_10 0x01C0
>0x0508 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__ANATOP_TESTI_0 0x01C0
>0x0508 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__RAWNAND_TESTER_TRIGGER 0x01C0
>0x0508 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RD0__PCIE_CTRL_DEBUG_0 0x01C0
>0x0508 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x01C4
>0x050C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__GPIO5_IO_1 0x01C4
>0x050C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__CSI2_DATA_11 0x01C4
>0x050C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__ANATOP_TESTI_1 0x01C4
>0x050C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__USDHC1_TESTER_TRIGGER 0x01C4
>0x050C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RD1__PCIE_CTRL_DEBUG_1 0x01C4
>0x050C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x01C8
>0x0510 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__GPIO5_IO_2 0x01C8
>0x0510 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__CSI2_DATA_12 0x01C8
>0x0510 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__ANATOP_TESTI_2 0x01C8
>0x0510 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__USDHC2_TESTER_TRIGGER 0x01C8
>0x0510 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RD2__PCIE_CTRL_DEBUG_2 0x01C8
>0x0510 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x01CC
>0x0514 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__GPIO5_IO_3 0x01CC
>0x0514 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__CSI2_DATA_13 0x01CC
>0x0514 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__ANATOP_TESTI_3 0x01CC
>0x0514 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__USDHC3_TESTER_TRIGGER 0x01CC
>0x0514 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RD3__PCIE_CTRL_DEBUG_3 0x01CC
>0x0514 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x01D0
>0x0518 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__GPIO5_IO_4 0x01D0
>0x0518 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__CSI2_DATA_14 0x01D0
>0x0518 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__ANATOP_TESTO_0 0x01D0
>0x0518 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__USDHC4_TESTER_TRIGGER 0x01D0
>0x0518 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RX_CTL__PCIE_CTRL_DEBUG_4 0x01D0
>0x0518 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x01D4
>0x051C 0x0768 0x0 0x1
>> +#define MX6SX_PAD_RGMII1_RXC__ENET1_RX_ER 0x01D4
>0x051C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__GPIO5_IO_5 0x01D4
>0x051C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__CSI2_DATA_15 0x01D4
>0x051C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__ANATOP_TESTO_1 0x01D4
>0x051C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__ECSPI1_TESTER_TRIGGER 0x01D4
>0x051C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_RXC__PCIE_CTRL_DEBUG_5 0x01D4
>0x051C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0x01D8
>0x0520 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__SAI2_RX_SYNC 0x01D8
>0x0520 0x0810 0x2 0x1
>> +#define MX6SX_PAD_RGMII1_TD0__GPIO5_IO_6 0x01D8
>0x0520 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__CSI2_DATA_16 0x01D8
>0x0520 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__ANATOP_TESTO_2 0x01D8
>0x0520 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__ECSPI2_TESTER_TRIGGER 0x01D8
>0x0520 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TD0__PCIE_CTRL_DEBUG_6 0x01D8
>0x0520 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0x01DC
>0x0524 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__SAI2_RX_BCLK 0x01DC
>0x0524 0x0808 0x2 0x1
>> +#define MX6SX_PAD_RGMII1_TD1__GPIO5_IO_7 0x01DC
>0x0524 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__CSI2_DATA_17 0x01DC
>0x0524 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__ANATOP_TESTO_3 0x01DC
>0x0524 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__ECSPI3_TESTER_TRIGGER 0x01DC
>0x0524 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TD1__PCIE_CTRL_DEBUG_7 0x01DC
>0x0524 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0x01E0
>0x0528 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__SAI2_TX_SYNC 0x01E0
>0x0528 0x0818 0x2 0x1
>> +#define MX6SX_PAD_RGMII1_TD2__GPIO5_IO_8 0x01E0
>0x0528 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__CSI2_DATA_18 0x01E0
>0x0528 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__ANATOP_TESTO_4 0x01E0
>0x0528 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__ECSPI4_TESTER_TRIGGER 0x01E0
>0x0528 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TD2__PCIE_CTRL_DEBUG_8 0x01E0
>0x0528 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0x01E4
>0x052C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__SAI2_TX_BCLK 0x01E4
>0x052C 0x0814 0x2 0x1
>> +#define MX6SX_PAD_RGMII1_TD3__GPIO5_IO_9 0x01E4
>0x052C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__CSI2_DATA_19 0x01E4
>0x052C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__ANATOP_TESTO_5 0x01E4
>0x052C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__ECSPI5_TESTER_TRIGGER 0x01E4
>0x052C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TD3__PCIE_CTRL_DEBUG_9 0x01E4
>0x052C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0x01E8
>0x0530 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__SAI2_RX_DATA_0 0x01E8
>0x0530 0x080C 0x2 0x1
>> +#define MX6SX_PAD_RGMII1_TX_CTL__GPIO5_IO_10 0x01E8
>0x0530 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__CSI2_DATA_0 0x01E8
>0x0530 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__ANATOP_TESTO_6 0x01E8
>0x0530 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__QSPI1_TESTER_TRIGGER 0x01E8
>0x0530 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TX_CTL__PCIE_CTRL_DEBUG_10 0x01E8
>0x0530 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0x01EC
>0x0534 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__ENET1_TX_ER 0x01EC
>0x0534 0x0000 0x1 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__SAI2_TX_DATA_0 0x01EC
>0x0534 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__GPIO5_IO_11 0x01EC
>0x0534 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__CSI2_DATA_1 0x01EC
>0x0534 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__ANATOP_TESTO_7 0x01EC
>0x0534 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__QSPI2_TESTER_TRIGGER 0x01EC
>0x0534 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII1_TXC__PCIE_CTRL_DEBUG_11 0x01EC
>0x0534 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x01F0
>0x0538 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__PWM4_OUT 0x01F0
>0x0538 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__GPIO5_IO_12 0x01F0
>0x0538 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__CSI2_DATA_2 0x01F0
>0x0538 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__ANATOP_TESTO_8 0x01F0
>0x0538 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__VDEC_DEBUG_18 0x01F0
>0x0538 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RD0__PCIE_CTRL_DEBUG_12 0x01F0
>0x0538 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x01F4
>0x053C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__PWM3_OUT 0x01F4
>0x053C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__GPIO5_IO_13 0x01F4
>0x053C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__CSI2_DATA_3 0x01F4
>0x053C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__ANATOP_TESTO_9 0x01F4
>0x053C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__VDEC_DEBUG_19 0x01F4
>0x053C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RD1__PCIE_CTRL_DEBUG_13 0x01F4
>0x053C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x01F8
>0x0540 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__PWM2_OUT 0x01F8
>0x0540 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__GPIO5_IO_14 0x01F8
>0x0540 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__CSI2_DATA_4 0x01F8
>0x0540 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__ANATOP_TESTO_10 0x01F8
>0x0540 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__VDEC_DEBUG_20 0x01F8
>0x0540 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RD2__PCIE_CTRL_DEBUG_14 0x01F8
>0x0540 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x01FC
>0x0544 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__PWM1_OUT 0x01FC
>0x0544 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__GPIO5_IO_15 0x01FC
>0x0544 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__CSI2_DATA_5 0x01FC
>0x0544 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__ANATOP_TESTO_11 0x01FC
>0x0544 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__VDEC_DEBUG_21 0x01FC
>0x0544 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RD3__PCIE_CTRL_DEBUG_15 0x01FC
>0x0544 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x0200
>0x0548 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__GPIO5_IO_16 0x0200
>0x0548 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__CSI2_DATA_6 0x0200
>0x0548 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__ANATOP_TESTO_12 0x0200
>0x0548 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__VDEC_DEBUG_22 0x0200
>0x0548 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RX_CTL__PCIE_CTRL_DEBUG_16 0x0200
>0x0548 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x0204
>0x054C 0x0774 0x0 0x1
>> +#define MX6SX_PAD_RGMII2_RXC__ENET2_RX_ER 0x0204
>0x054C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__GPIO5_IO_17 0x0204
>0x054C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__CSI2_DATA_7 0x0204
>0x054C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__ANATOP_TESTO_13 0x0204
>0x054C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__VDEC_DEBUG_23 0x0204
>0x054C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_RXC__PCIE_CTRL_DEBUG_17 0x0204
>0x054C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0x0208
>0x0550 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__SAI1_RX_SYNC 0x0208
>0x0550 0x07FC 0x2 0x1
>> +#define MX6SX_PAD_RGMII2_TD0__PWM8_OUT 0x0208
>0x0550 0x0000 0x3 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__GPIO5_IO_18 0x0208
>0x0550 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__CSI2_DATA_8 0x0208
>0x0550 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__ANATOP_TESTO_14 0x0208
>0x0550 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__VDEC_DEBUG_24 0x0208
>0x0550 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TD0__PCIE_CTRL_DEBUG_18 0x0208
>0x0550 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0x020C
>0x0554 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__SAI1_RX_BCLK 0x020C
>0x0554 0x07F4 0x2 0x1
>> +#define MX6SX_PAD_RGMII2_TD1__PWM7_OUT 0x020C
>0x0554 0x0000 0x3 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__GPIO5_IO_19 0x020C
>0x0554 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__CSI2_DATA_9 0x020C
>0x0554 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__ANATOP_TESTO_15 0x020C
>0x0554 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__VDEC_DEBUG_25 0x020C
>0x0554 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TD1__PCIE_CTRL_DEBUG_19 0x020C
>0x0554 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0x0210
>0x0558 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__SAI1_TX_SYNC 0x0210
>0x0558 0x0804 0x2 0x1
>> +#define MX6SX_PAD_RGMII2_TD2__PWM6_OUT 0x0210
>0x0558 0x0000 0x3 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__GPIO5_IO_20 0x0210
>0x0558 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__CSI2_VSYNC 0x0210
>0x0558 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__SJC_FAIL 0x0210
>0x0558 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__VDEC_DEBUG_26 0x0210
>0x0558 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TD2__PCIE_CTRL_DEBUG_20 0x0210
>0x0558 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0x0214
>0x055C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__SAI1_TX_BCLK 0x0214
>0x055C 0x0800 0x2 0x1
>> +#define MX6SX_PAD_RGMII2_TD3__PWM5_OUT 0x0214
>0x055C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__GPIO5_IO_21 0x0214
>0x055C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__CSI2_HSYNC 0x0214
>0x055C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__SJC_JTAG_ACT 0x0214
>0x055C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__VDEC_DEBUG_27 0x0214
>0x055C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TD3__PCIE_CTRL_DEBUG_21 0x0214
>0x055C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0x0218
>0x0560 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__SAI1_RX_DATA_0 0x0218
>0x0560 0x07F8 0x2 0x1
>> +#define MX6SX_PAD_RGMII2_TX_CTL__GPIO5_IO_22 0x0218
>0x0560 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__CSI2_FIELD 0x0218
>0x0560 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__SJC_DE_B 0x0218
>0x0560 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__VDEC_DEBUG_28 0x0218
>0x0560 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TX_CTL__PCIE_CTRL_DEBUG_22 0x0218
>0x0560 0x0000 0x9 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0x021C
>0x0564 0x0000 0x0 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__ENET2_TX_ER 0x021C
>0x0564 0x0000 0x1 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__SAI1_TX_DATA_0 0x021C
>0x0564 0x0000 0x2 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__GPIO5_IO_23 0x021C
>0x0564 0x0000 0x5 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__CSI2_PIXCLK 0x021C
>0x0564 0x0000 0x6 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__SJC_DONE 0x021C
>0x0564 0x0000 0x7 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__VDEC_DEBUG_29 0x021C
>0x0564 0x0000 0x8 0x0
>> +#define MX6SX_PAD_RGMII2_TXC__PCIE_CTRL_DEBUG_23 0x021C
>0x0564 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD1_CLK__USDHC1_CLK 0x0220
>0x0568 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_CLK__AUDMUX_AUD5_RXFS 0x0220
>0x0568 0x0668 0x1 0x1
>> +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_B 0x0220
>0x0568 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD1_CLK__GPT_CLK 0x0220
>0x0568 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_CLK__WDOG2_WDOG_RST_B_DEB 0x0220
>0x0568 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD1_CLK__GPIO6_IO_0 0x0220
>0x0568 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_CLK__ENET2_1588_EVENT1_OUT 0x0220
>0x0568 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_CLK__CCM_OUT1 0x0220
>0x0568 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD1_CLK__VADC_ADC_PROC_CLK 0x0220
>0x0568 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD1_CLK__MMDC_DEBUG_45 0x0220
>0x0568 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD1_CMD__USDHC1_CMD 0x0224
>0x056C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_CMD__AUDMUX_AUD5_RXC 0x0224
>0x056C 0x0664 0x1 0x1
>> +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_B 0x0224
>0x056C 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD1_CMD__GPT_COMPARE1 0x0224
>0x056C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_CMD__WDOG1_WDOG_RST_B_DEB 0x0224
>0x056C 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD1_CMD__GPIO6_IO_1 0x0224
>0x056C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_CMD__ENET2_1588_EVENT1_IN 0x0224
>0x056C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_CMD__CCM_CLKO1 0x0224
>0x056C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD1_CMD__VADC_EXT_SYSCLK 0x0224
>0x056C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD1_CMD__MMDC_DEBUG_46 0x0224
>0x056C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD1_DATA0__USDHC1_DATA0 0x0228
>0x0570 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_DATA0__AUDMUX_AUD5_RXD 0x0228
>0x0570 0x065C 0x1 0x1
>> +#define MX6SX_PAD_SD1_DATA0__CAAM_WRAPPER_RNG_OSC_OBS 0x0228
>0x0570 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD1_DATA0__GPT_CAPTURE1 0x0228
>0x0570 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_DATA0__UART2_RX 0x0228
>0x0570 0x0838 0x4 0x2
>> +#define MX6SX_PAD_SD1_DATA0__UART2_TX 0x0228
>0x0570 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD1_DATA0__GPIO6_IO_2 0x0228
>0x0570 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_DATA0__ENET1_1588_EVENT1_IN 0x0228
>0x0570 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_DATA0__CCM_OUT2 0x0228
>0x0570 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD1_DATA0__VADC_CLAMP_UP 0x0228
>0x0570 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD1_DATA0__MMDC_DEBUG_48 0x0228
>0x0570 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD1_DATA1__USDHC1_DATA1 0x022C
>0x0574 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_DATA1__AUDMUX_AUD5_TXC 0x022C
>0x0574 0x066C 0x1 0x1
>> +#define MX6SX_PAD_SD1_DATA1__PWM4_OUT 0x022C
>0x0574 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD1_DATA1__GPT_CAPTURE2 0x022C
>0x0574 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_DATA1__UART2_RX 0x022C
>0x0574 0x0838 0x4 0x3
>> +#define MX6SX_PAD_SD1_DATA1__UART2_TX 0x022C
>0x0574 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD1_DATA1__GPIO6_IO_3 0x022C
>0x0574 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_DATA1__ENET1_1588_EVENT1_OUT 0x022C
>0x0574 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_DATA1__CCM_CLKO2 0x022C
>0x0574 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD1_DATA1__VADC_CLAMP_DOWN 0x022C
>0x0574 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD1_DATA1__MMDC_DEBUG_47 0x022C
>0x0574 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD1_DATA2__USDHC1_DATA2 0x0230
>0x0578 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_DATA2__AUDMUX_AUD5_TXFS 0x0230
>0x0578 0x0670 0x1 0x1
>> +#define MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x0230
>0x0578 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD1_DATA2__GPT_COMPARE2 0x0230
>0x0578 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_DATA2__UART2_CTS_B 0x0230
>0x0578 0x0834 0x4 0x2
>> +#define MX6SX_PAD_SD1_DATA2__GPIO6_IO_4 0x0230
>0x0578 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_DATA2__ECSPI4_RDY 0x0230
>0x0578 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_DATA2__CCM_OUT0 0x0230
>0x0578 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD1_DATA2__VADC_EXT_PD_N 0x0230
>0x0578 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD1_DATA3__USDHC1_DATA3 0x0234
>0x057C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_TXD 0x0234
>0x057C 0x0660 0x1 0x1
>> +#define MX6SX_PAD_SD1_DATA3__AUDMUX_AUD5_RXD 0x0234
>0x057C 0x065C 0x2 0x2
>> +#define MX6SX_PAD_SD1_DATA3__GPT_COMPARE3 0x0234
>0x057C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD1_DATA3__UART2_RTS_B 0x0234
>0x057C 0x0834 0x4 0x3
>> +#define MX6SX_PAD_SD1_DATA3__GPIO6_IO_5 0x0234
>0x057C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD1_DATA3__ECSPI4_SS1 0x0234
>0x057C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD1_DATA3__CCM_PMIC_RDY 0x0234
>0x057C 0x069C 0x7 0x2
>> +#define MX6SX_PAD_SD1_DATA3__VADC_RST_N 0x0234
>0x057C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x0238
>0x0580 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_CLK__AUDMUX_AUD6_RXFS 0x0238
>0x0580 0x0680 0x1 0x2
>> +#define MX6SX_PAD_SD2_CLK__KPP_COL_5 0x0238
>0x0580 0x07C8 0x2 0x1
>> +#define MX6SX_PAD_SD2_CLK__ECSPI4_SCLK 0x0238
>0x0580 0x0740 0x3 0x1
>> +#define MX6SX_PAD_SD2_CLK__MLB_SIG 0x0238
>0x0580 0x07F0 0x4 0x2
>> +#define MX6SX_PAD_SD2_CLK__GPIO6_IO_6 0x0238
>0x0580 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_CLK__MQS_RIGHT 0x0238
>0x0580 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD2_CLK__WDOG1_WDOG_ANY 0x0238
>0x0580 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_CLK__VADC_CLAMP_CURRENT_5 0x0238
>0x0580 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_CLK__MMDC_DEBUG_29 0x0238
>0x0580 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x023C
>0x0584 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_CMD__AUDMUX_AUD6_RXC 0x023C
>0x0584 0x067C 0x1 0x2
>> +#define MX6SX_PAD_SD2_CMD__KPP_ROW_5 0x023C
>0x0584 0x07D4 0x2 0x1
>> +#define MX6SX_PAD_SD2_CMD__ECSPI4_MOSI 0x023C
>0x0584 0x0748 0x3 0x1
>> +#define MX6SX_PAD_SD2_CMD__MLB_CLK 0x023C
>0x0584 0x07E8 0x4 0x2
>> +#define MX6SX_PAD_SD2_CMD__GPIO6_IO_7 0x023C
>0x0584 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_CMD__MQS_LEFT 0x023C
>0x0584 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD2_CMD__WDOG3_WDOG_B 0x023C
>0x0584 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_CMD__VADC_CLAMP_CURRENT_4 0x023C
>0x0584 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_CMD__MMDC_DEBUG_30 0x023C
>0x0584 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x0240
>0x0588 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_DATA0__AUDMUX_AUD6_RXD 0x0240
>0x0588 0x0674 0x1 0x2
>> +#define MX6SX_PAD_SD2_DATA0__KPP_ROW_7 0x0240
>0x0588 0x07DC 0x2 0x1
>> +#define MX6SX_PAD_SD2_DATA0__PWM1_OUT 0x0240
>0x0588 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD2_DATA0__I2C4_SDA 0x0240
>0x0588 0x07C4 0x4 0x3
>> +#define MX6SX_PAD_SD2_DATA0__GPIO6_IO_8 0x0240
>0x0588 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_DATA0__ECSPI4_SS3 0x0240
>0x0588 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD2_DATA0__UART4_RX 0x0240
>0x0588 0x0848 0x7 0x4
>> +#define MX6SX_PAD_SD2_DATA0__UART4_TX 0x0240
>0x0588 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_DATA0__VADC_CLAMP_CURRENT_0 0x0240
>0x0588 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_DATA0__MMDC_DEBUG_50 0x0240
>0x0588 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x0244
>0x058C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_DATA1__AUDMUX_AUD6_TXC 0x0244
>0x058C 0x0684 0x1 0x2
>> +#define MX6SX_PAD_SD2_DATA1__KPP_COL_7 0x0244
>0x058C 0x07D0 0x2 0x1
>> +#define MX6SX_PAD_SD2_DATA1__PWM2_OUT 0x0244
>0x058C 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD2_DATA1__I2C4_SCL 0x0244
>0x058C 0x07C0 0x4 0x3
>> +#define MX6SX_PAD_SD2_DATA1__GPIO6_IO_9 0x0244
>0x058C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_DATA1__ECSPI4_SS2 0x0244
>0x058C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD2_DATA1__UART4_RX 0x0244
>0x058C 0x0848 0x7 0x5
>> +#define MX6SX_PAD_SD2_DATA1__UART4_TX 0x0244
>0x058C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_DATA1__VADC_CLAMP_CURRENT_1 0x0244
>0x058C 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_DATA1__MMDC_DEBUG_49 0x0244
>0x058C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x0248
>0x0590 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_DATA2__AUDMUX_AUD6_TXFS 0x0248
>0x0590 0x0688 0x1 0x2
>> +#define MX6SX_PAD_SD2_DATA2__KPP_ROW_6 0x0248
>0x0590 0x07D8 0x2 0x1
>> +#define MX6SX_PAD_SD2_DATA2__ECSPI4_SS0 0x0248
>0x0590 0x074C 0x3 0x1
>> +#define MX6SX_PAD_SD2_DATA2__SDMA_EXT_EVENT_0 0x0248
>0x0590 0x081C 0x4 0x2
>> +#define MX6SX_PAD_SD2_DATA2__GPIO6_IO_10 0x0248
>0x0590 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_DATA2__SPDIF_OUT 0x0248
>0x0590 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD2_DATA2__UART6_RX 0x0248
>0x0590 0x0858 0x7 0x4
>> +#define MX6SX_PAD_SD2_DATA2__UART6_TX 0x0248
>0x0590 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_DATA2__VADC_CLAMP_CURRENT_2 0x0248
>0x0590 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_DATA2__MMDC_DEBUG_32 0x0248
>0x0590 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x024C
>0x0594 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD2_DATA3__AUDMUX_AUD6_TXD 0x024C
>0x0594 0x0678 0x1 0x2
>> +#define MX6SX_PAD_SD2_DATA3__KPP_COL_6 0x024C
>0x0594 0x07CC 0x2 0x1
>> +#define MX6SX_PAD_SD2_DATA3__ECSPI4_MISO 0x024C
>0x0594 0x0744 0x3 0x1
>> +#define MX6SX_PAD_SD2_DATA3__MLB_DATA 0x024C
>0x0594 0x07EC 0x4 0x2
>> +#define MX6SX_PAD_SD2_DATA3__GPIO6_IO_11 0x024C
>0x0594 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD2_DATA3__SPDIF_IN 0x024C
>0x0594 0x0824 0x6 0x4
>> +#define MX6SX_PAD_SD2_DATA3__UART6_RX 0x024C
>0x0594 0x0858 0x7 0x5
>> +#define MX6SX_PAD_SD2_DATA3__UART6_TX 0x024C
>0x0594 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD2_DATA3__VADC_CLAMP_CURRENT_3 0x024C
>0x0594 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD2_DATA3__MMDC_DEBUG_31 0x024C
>0x0594 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x0250
>0x0598 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_CLK__UART4_CTS_B 0x0250
>0x0598 0x0844 0x1 0x0
>> +#define MX6SX_PAD_SD3_CLK__ECSPI4_SCLK 0x0250
>0x0598 0x0740 0x2 0x0
>> +#define MX6SX_PAD_SD3_CLK__AUDMUX_AUD6_RXFS 0x0250
>0x0598 0x0680 0x3 0x0
>> +#define MX6SX_PAD_SD3_CLK__LCDIF2_VSYNC 0x0250
>0x0598 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_CLK__GPIO7_IO_0 0x0250
>0x0598 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_CLK__LCDIF2_BUSY 0x0250
>0x0598 0x07E4 0x6 0x0
>> +#define MX6SX_PAD_SD3_CLK__TPSMP_HDATA_29 0x0250
>0x0598 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_CLK__SDMA_DEBUG_EVENT_CHANNEL_5 0x0250
>0x0598 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x0254
>0x059C 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_CMD__UART4_RX 0x0254
>0x059C 0x0848 0x1 0x0
>> +#define MX6SX_PAD_SD3_CMD__UART4_TX 0x0254
>0x059C 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD3_CMD__ECSPI4_MOSI 0x0254
>0x059C 0x0748 0x2 0x0
>> +#define MX6SX_PAD_SD3_CMD__AUDMUX_AUD6_RXC 0x0254
>0x059C 0x067C 0x3 0x0
>> +#define MX6SX_PAD_SD3_CMD__LCDIF2_HSYNC 0x0254
>0x059C 0x07E4 0x4 0x1
>> +#define MX6SX_PAD_SD3_CMD__GPIO7_IO_1 0x0254
>0x059C 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_CMD__LCDIF2_RS 0x0254
>0x059C 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_CMD__TPSMP_HDATA_28 0x0254
>0x059C 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_CMD__SDMA_DEBUG_EVENT_CHANNEL_4 0x0254
>0x059C 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x0258
>0x05A0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA0__I2C4_SCL 0x0258
>0x05A0 0x07C0 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA0__ECSPI2_SS1 0x0258
>0x05A0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA0__AUDMUX_AUD6_RXD 0x0258
>0x05A0 0x0674 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA0__LCDIF2_DATA_1 0x0258
>0x05A0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA0__GPIO7_IO_2 0x0258
>0x05A0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA0__DCIC1_OUT 0x0258
>0x05A0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA0__TPSMP_HDATA_30 0x0258
>0x05A0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA0__GPU_DEBUG_0 0x0258
>0x05A0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA0__SDMA_DEBUG_EVT_CHN_LINES_0 0x0258
>0x05A0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x025C
>0x05A4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA1__I2C4_SDA 0x025C
>0x05A4 0x07C4 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA1__ECSPI2_SS2 0x025C
>0x05A4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA1__AUDMUX_AUD6_TXC 0x025C
>0x05A4 0x0684 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA1__LCDIF2_DATA_0 0x025C
>0x05A4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA1__GPIO7_IO_3 0x025C
>0x05A4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA1__DCIC2_OUT 0x025C
>0x05A4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA1__TPSMP_HDATA_31 0x025C
>0x05A4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA1__GPU_DEBUG_1 0x025C
>0x05A4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA1__SDMA_DEBUG_EVT_CHN_LINES_1 0x025C
>0x05A4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x0260
>0x05A8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA2__UART4_RTS_B 0x0260
>0x05A8 0x0844 0x1 0x1
>> +#define MX6SX_PAD_SD3_DATA2__ECSPI4_SS0 0x0260
>0x05A8 0x074C 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA2__AUDMUX_AUD6_TXFS 0x0260
>0x05A8 0x0688 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA2__LCDIF2_CLK 0x0260
>0x05A8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA2__GPIO7_IO_4 0x0260
>0x05A8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA2__LCDIF2_WR_RWN 0x0260
>0x05A8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA2__TPSMP_HDATA_26 0x0260
>0x05A8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA2__GPU_DEBUG_2 0x0260
>0x05A8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA2__SDMA_DEBUG_EVENT_CHANNEL_2 0x0260
>0x05A8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x0264
>0x05AC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA3__UART4_RX 0x0264
>0x05AC 0x0848 0x1 0x1
>> +#define MX6SX_PAD_SD3_DATA3__UART4_TX 0x0264
>0x05AC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA3__ECSPI4_MISO 0x0264
>0x05AC 0x0744 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA3__AUDMUX_AUD6_TXD 0x0264
>0x05AC 0x0678 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA3__LCDIF2_ENABLE 0x0264
>0x05AC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA3__GPIO7_IO_5 0x0264
>0x05AC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA3__LCDIF2_RD_E 0x0264
>0x05AC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA3__TPSMP_HDATA_27 0x0264
>0x05AC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA3__GPU_DEBUG_3 0x0264
>0x05AC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA3__SDMA_DEBUG_EVENT_CHANNEL_3 0x0264
>0x05AC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x0268
>0x05B0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA4__CAN2_RX 0x0268
>0x05B0 0x0690 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA4__CANFD_RX2 0x0268
>0x05B0 0x0698 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA4__UART3_RX 0x0268
>0x05B0 0x0840 0x3 0x2
>> +#define MX6SX_PAD_SD3_DATA4__UART3_TX 0x0268
>0x05B0 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA4__LCDIF2_DATA_3 0x0268
>0x05B0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA4__GPIO7_IO_6 0x0268
>0x05B0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA4__ENET2_1588_EVENT0_IN 0x0268
>0x05B0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA4__TPSMP_HTRANS_1 0x0268
>0x05B0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA4__GPU_DEBUG_4 0x0268
>0x05B0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA4__SDMA_DEBUG_BUS_DEVICE_0 0x0268
>0x05B0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x026C
>0x05B4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA5__CAN1_TX 0x026C
>0x05B4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA5__CANFD_TX1 0x026C
>0x05B4 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA5__UART3_RX 0x026C
>0x05B4 0x0840 0x3 0x3
>> +#define MX6SX_PAD_SD3_DATA5__UART3_TX 0x026C
>0x05B4 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD3_DATA5__LCDIF2_DATA_2 0x026C
>0x05B4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA5__GPIO7_IO_7 0x026C
>0x05B4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA5__ENET2_1588_EVENT0_OUT 0x026C
>0x05B4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA5__SIM_M_HWRITE 0x026C
>0x05B4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA5__GPU_DEBUG_5 0x026C
>0x05B4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA5__SDMA_DEBUG_BUS_DEVICE_1 0x026C
>0x05B4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x0270
>0x05B8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA6__CAN2_TX 0x0270
>0x05B8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA6__CANFD_TX2 0x0270
>0x05B8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA6__UART3_RTS_B 0x0270
>0x05B8 0x083C 0x3 0x2
>> +#define MX6SX_PAD_SD3_DATA6__LCDIF2_DATA_4 0x0270
>0x05B8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA6__GPIO7_IO_8 0x0270
>0x05B8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA6__ENET1_1588_EVENT0_OUT 0x0270
>0x05B8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA6__TPSMP_HTRANS_0 0x0270
>0x05B8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA6__GPU_DEBUG_7 0x0270
>0x05B8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA6__SDMA_DEBUG_EVT_CHN_LINES_7 0x0270
>0x05B8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x0274
>0x05BC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD3_DATA7__CAN1_RX 0x0274
>0x05BC 0x068C 0x1 0x0
>> +#define MX6SX_PAD_SD3_DATA7__CANFD_RX1 0x0274
>0x05BC 0x0694 0x2 0x0
>> +#define MX6SX_PAD_SD3_DATA7__UART3_CTS_B 0x0274
>0x05BC 0x083C 0x3 0x3
>> +#define MX6SX_PAD_SD3_DATA7__LCDIF2_DATA_5 0x0274
>0x05BC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD3_DATA7__GPIO7_IO_9 0x0274
>0x05BC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD3_DATA7__ENET1_1588_EVENT0_IN 0x0274
>0x05BC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD3_DATA7__TPSMP_HDATA_DIR 0x0274
>0x05BC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD3_DATA7__GPU_DEBUG_6 0x0274
>0x05BC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD3_DATA7__SDMA_DEBUG_EVT_CHN_LINES_2 0x0274
>0x05BC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x0278
>0x05C0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_CLK__RAWNAND_DATA15 0x0278
>0x05C0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_CLK__ECSPI2_MISO 0x0278
>0x05C0 0x0724 0x2 0x1
>> +#define MX6SX_PAD_SD4_CLK__AUDMUX_AUD3_RXFS 0x0278
>0x05C0 0x0638 0x3 0x0
>> +#define MX6SX_PAD_SD4_CLK__LCDIF2_DATA_13 0x0278
>0x05C0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_CLK__GPIO6_IO_12 0x0278
>0x05C0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_CLK__ECSPI3_SS2 0x0278
>0x05C0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_CLK__TPSMP_HDATA_20 0x0278
>0x05C0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_CLK__VDEC_DEBUG_12 0x0278
>0x05C0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_CLK__SDMA_DEBUG_EVENT_CHANNEL_SEL 0x0278
>0x05C0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x027C
>0x05C4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_CMD__RAWNAND_DATA14 0x027C
>0x05C4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_CMD__ECSPI2_MOSI 0x027C
>0x05C4 0x0728 0x2 0x1
>> +#define MX6SX_PAD_SD4_CMD__AUDMUX_AUD3_RXC 0x027C
>0x05C4 0x0634 0x3 0x0
>> +#define MX6SX_PAD_SD4_CMD__LCDIF2_DATA_14 0x027C
>0x05C4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_CMD__GPIO6_IO_13 0x027C
>0x05C4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_CMD__ECSPI3_SS1 0x027C
>0x05C4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_CMD__TPSMP_HDATA_19 0x027C
>0x05C4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_CMD__VDEC_DEBUG_11 0x027C
>0x05C4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_CMD__SDMA_DEBUG_CORE_RUN 0x027C
>0x05C4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x0280
>0x05C8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA0__RAWNAND_DATA10 0x0280
>0x05C8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA0__ECSPI2_SS0 0x0280
>0x05C8 0x072C 0x2 0x1
>> +#define MX6SX_PAD_SD4_DATA0__AUDMUX_AUD3_RXD 0x0280
>0x05C8 0x062C 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA0__LCDIF2_DATA_12 0x0280
>0x05C8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA0__GPIO6_IO_14 0x0280
>0x05C8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA0__ECSPI3_SS3 0x0280
>0x05C8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA0__TPSMP_HDATA_21 0x0280
>0x05C8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA0__VDEC_DEBUG_13 0x0280
>0x05C8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA0__SDMA_DEBUG_MODE 0x0280
>0x05C8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x0284
>0x05CC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA1__RAWNAND_DATA11 0x0284
>0x05CC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA1__ECSPI2_SCLK 0x0284
>0x05CC 0x0720 0x2 0x1
>> +#define MX6SX_PAD_SD4_DATA1__AUDMUX_AUD3_TXC 0x0284
>0x05CC 0x063C 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA1__LCDIF2_DATA_11 0x0284
>0x05CC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA1__GPIO6_IO_15 0x0284
>0x05CC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA1__ECSPI3_RDY 0x0284
>0x05CC 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA1__TPSMP_HDATA_22 0x0284
>0x05CC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA1__VDEC_DEBUG_14 0x0284
>0x05CC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA1__SDMA_DEBUG_BUS_ERROR 0x0284
>0x05CC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x0288
>0x05D0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA2__RAWNAND_DATA12 0x0288
>0x05D0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA2__I2C2_SDA 0x0288
>0x05D0 0x07B4 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA2__AUDMUX_AUD3_TXFS 0x0288
>0x05D0 0x0640 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA2__LCDIF2_DATA_10 0x0288
>0x05D0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA2__GPIO6_IO_16 0x0288
>0x05D0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA2__ECSPI2_SS3 0x0288
>0x05D0 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA2__TPSMP_HDATA_23 0x0288
>0x05D0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA2__VDEC_DEBUG_15 0x0288
>0x05D0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA2__SDMA_DEBUG_BUS_RWB 0x0288
>0x05D0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x028C
>0x05D4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA3__RAWNAND_DATA13 0x028C
>0x05D4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA3__I2C2_SCL 0x028C
>0x05D4 0x07B0 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA3__AUDMUX_AUD3_TXD 0x028C
>0x05D4 0x0630 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA3__LCDIF2_DATA_9 0x028C
>0x05D4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA3__GPIO6_IO_17 0x028C
>0x05D4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA3__ECSPI2_RDY 0x028C
>0x05D4 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA3__TPSMP_HDATA_24 0x028C
>0x05D4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA3__VDEC_DEBUG_16 0x028C
>0x05D4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA3__SDMA_DEBUG_MATCHED_DMBUS 0x028C
>0x05D4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA4__USDHC4_DATA4 0x0290
>0x05D8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA4__RAWNAND_DATA09 0x0290
>0x05D8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA4__UART5_RX 0x0290
>0x05D8 0x0850 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA4__UART5_TX 0x0290
>0x05D8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA4__ECSPI3_SCLK 0x0290
>0x05D8 0x0730 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA4__LCDIF2_DATA_8 0x0290
>0x05D8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA4__GPIO6_IO_18 0x0290
>0x05D8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA4__SPDIF_OUT 0x0290
>0x05D8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA4__TPSMP_HDATA_16 0x0290
>0x05D8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA4__USB_OTG_HOST_MODE 0x0290
>0x05D8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA4__SDMA_DEBUG_RTBUFFER_WRITE 0x0290
>0x05D8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA5__USDHC4_DATA5 0x0294
>0x05DC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA5__RAWNAND_CE2_B 0x0294
>0x05DC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA5__UART5_RX 0x0294
>0x05DC 0x0850 0x2 0x1
>> +#define MX6SX_PAD_SD4_DATA5__UART5_TX 0x0294
>0x05DC 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA5__ECSPI3_MOSI 0x0294
>0x05DC 0x0738 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA5__LCDIF2_DATA_7 0x0294
>0x05DC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA5__GPIO6_IO_19 0x0294
>0x05DC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA5__SPDIF_IN 0x0294
>0x05DC 0x0824 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA5__TPSMP_HDATA_17 0x0294
>0x05DC 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA5__VDEC_DEBUG_9 0x0294
>0x05DC 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA5__SDMA_DEBUG_EVENT_CHANNEL_0 0x0294
>0x05DC 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA6__USDHC4_DATA6 0x0298
>0x05E0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA6__RAWNAND_CE3_B 0x0298
>0x05E0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA6__UART5_RTS_B 0x0298
>0x05E0 0x084C 0x2 0x0
>> +#define MX6SX_PAD_SD4_DATA6__ECSPI3_MISO 0x0298
>0x05E0 0x0734 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA6__LCDIF2_DATA_6 0x0298
>0x05E0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x0298
>0x05E0 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA6__USDHC4_WP 0x0298
>0x05E0 0x0878 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA6__TPSMP_HDATA_18 0x0298
>0x05E0 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA6__VDEC_DEBUG_10 0x0298
>0x05E0 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA6__SDMA_DEBUG_EVENT_CHANNEL_1 0x0298
>0x05E0 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_DATA7__USDHC4_DATA7 0x029C
>0x05E4 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_DATA7__RAWNAND_DATA08 0x029C
>0x05E4 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_DATA7__UART5_CTS_B 0x029C
>0x05E4 0x084C 0x2 0x1
>> +#define MX6SX_PAD_SD4_DATA7__ECSPI3_SS0 0x029C
>0x05E4 0x073C 0x3 0x0
>> +#define MX6SX_PAD_SD4_DATA7__LCDIF2_DATA_15 0x029C
>0x05E4 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x029C
>0x05E4 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_DATA7__USDHC4_CD_B 0x029C
>0x05E4 0x0874 0x6 0x0
>> +#define MX6SX_PAD_SD4_DATA7__TPSMP_HDATA_15 0x029C
>0x05E4 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_DATA7__USB_OTG_PWR_WAKE 0x029C
>0x05E4 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_DATA7__SDMA_DEBUG_YIELD 0x029C
>0x05E4 0x0000 0x9 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET_B 0x02A0
>0x05E8 0x0000 0x0 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__RAWNAND_DQS 0x02A0
>0x05E8 0x0000 0x1 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__USDHC4_RESET 0x02A0
>0x05E8 0x0000 0x2 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__AUDMUX_MCLK 0x02A0
>0x05E8 0x0000 0x3 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_RESET 0x02A0
>0x05E8 0x0000 0x4 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x02A0
>0x05E8 0x0000 0x5 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__LCDIF2_CS 0x02A0
>0x05E8 0x0000 0x6 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__TPSMP_HDATA_25 0x02A0
>0x05E8 0x0000 0x7 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__VDEC_DEBUG_17 0x02A0
>0x05E8 0x0000 0x8 0x0
>> +#define MX6SX_PAD_SD4_RESET_B__SDMA_DEBUG_BUS_DEVICE_2 0x02A0
>0x05E8 0x0000 0x9 0x0
>> +#define MX6SX_PAD_USB_H_DATA__USB_H_DATA 0x02A4
>0x05EC 0x0000 0x0 0x0
>> +#define MX6SX_PAD_USB_H_DATA__PWM2_OUT 0x02A4
>0x05EC 0x0000 0x1 0x0
>> +#define MX6SX_PAD_USB_H_DATA__ANATOP_24M_OUT 0x02A4
>0x05EC 0x0000 0x2 0x0
>> +#define MX6SX_PAD_USB_H_DATA__I2C4_SDA 0x02A4
>0x05EC 0x07C4 0x3 0x1
>> +#define MX6SX_PAD_USB_H_DATA__WDOG3_WDOG_B 0x02A4
>0x05EC 0x0000 0x4 0x0
>> +#define MX6SX_PAD_USB_H_DATA__GPIO7_IO_10 0x02A4
>0x05EC 0x0000 0x5 0x0
>> +#define MX6SX_PAD_USB_H_STROBE__USB_H_STROBE 0x02A8
>0x05F0 0x0000 0x0 0x0
>> +#define MX6SX_PAD_USB_H_STROBE__PWM1_OUT 0x02A8
>0x05F0 0x0000 0x1 0x0
>> +#define MX6SX_PAD_USB_H_STROBE__ANATOP_32K_OUT 0x02A8
>0x05F0 0x0000 0x2 0x0
>> +#define MX6SX_PAD_USB_H_STROBE__I2C4_SCL 0x02A8
>0x05F0 0x07C0 0x3 0x1
>> +#define MX6SX_PAD_USB_H_STROBE__WDOG3_WDOG_RST_B_DEB 0x02A8
>0x05F0 0x0000 0x4 0x0
>> +#define MX6SX_PAD_USB_H_STROBE__GPIO7_IO_11 0x02A8
>0x05F0 0x0000 0x5 0x0
>> +
>> +#endif /* __DTS_IMX6SX_PINFUNC_H */
>> diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
>> index be361b7..fc1825c7 100644
>> --- a/drivers/pinctrl/Kconfig
>> +++ b/drivers/pinctrl/Kconfig
>> @@ -185,6 +185,14 @@ config PINCTRL_IMX6SL
>> help
>> Say Y here to enable the imx6sl pinctrl driver
>>
>> +config PINCTRL_IMX6SX
>> + bool "IMX6SX pinctrl driver"
>> + depends on OF
>> + depends on SOC_IMX6SX
>> + select PINCTRL_IMX
>> + help
>> + Say Y here to enable the imx6sx pinctrl driver
>> +
>> config PINCTRL_VF610
>> bool "Freescale Vybrid VF610 pinctrl driver"
>> depends on SOC_VF610
>> diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
>> index 4b83588..bc791b4 100644
>> --- a/drivers/pinctrl/Makefile
>> +++ b/drivers/pinctrl/Makefile
>> @@ -32,6 +32,7 @@ obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
>> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
>> obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6dl.o
>> obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
>> +obj-$(CONFIG_PINCTRL_IMX6SX) += pinctrl-imx6sx.o
>> obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
>> obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
>> obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
>> diff --git a/drivers/pinctrl/pinctrl-imx6sx.c b/drivers/pinctrl/pinctrl-
>imx6sx.c
>> new file mode 100644
>> index 0000000..09758a5
>> --- /dev/null
>> +++ b/drivers/pinctrl/pinctrl-imx6sx.c
>> @@ -0,0 +1,407 @@
>> +/*
>> + * Copyright (C) 2014 Freescale Semiconductor, Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/err.h>
>> +#include <linux/init.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_device.h>
>> +#include <linux/pinctrl/pinctrl.h>
>> +
>> +#include "pinctrl-imx.h"
>> +
>> +enum imx6sx_pads {
>> + MX6Sx_PAD_RESERVE0 = 0,
>> + MX6Sx_PAD_RESERVE1 = 1,
>> + MX6Sx_PAD_RESERVE2 = 2,
>> + MX6Sx_PAD_RESERVE3 = 3,
>> + MX6Sx_PAD_RESERVE4 = 4,
>> + MX6SX_PAD_GPIO1_IO00 = 5,
>> + MX6SX_PAD_GPIO1_IO01 = 6,
>> + MX6SX_PAD_GPIO1_IO02 = 7,
>> + MX6SX_PAD_GPIO1_IO03 = 8,
>> + MX6SX_PAD_GPIO1_IO04 = 9,
>> + MX6SX_PAD_GPIO1_IO05 = 10,
>> + MX6SX_PAD_GPIO1_IO06 = 11,
>> + MX6SX_PAD_GPIO1_IO07 = 12,
>> + MX6SX_PAD_GPIO1_IO08 = 13,
>> + MX6SX_PAD_GPIO1_IO09 = 14,
>> + MX6SX_PAD_GPIO1_IO10 = 15,
>> + MX6SX_PAD_GPIO1_IO11 = 16,
>> + MX6SX_PAD_GPIO1_IO12 = 17,
>> + MX6SX_PAD_GPIO1_IO13 = 18,
>> + MX6SX_PAD_CSI_DATA00 = 19,
>> + MX6SX_PAD_CSI_DATA01 = 20,
>> + MX6SX_PAD_CSI_DATA02 = 21,
>> + MX6SX_PAD_CSI_DATA03 = 22,
>> + MX6SX_PAD_CSI_DATA04 = 23,
>> + MX6SX_PAD_CSI_DATA05 = 24,
>> + MX6SX_PAD_CSI_DATA06 = 25,
>> + MX6SX_PAD_CSI_DATA07 = 26,
>> + MX6SX_PAD_CSI_HSYNC = 27,
>> + MX6SX_PAD_CSI_MCLK = 28,
>> + MX6SX_PAD_CSI_PIXCLK = 29,
>> + MX6SX_PAD_CSI_VSYNC = 30,
>> + MX6SX_PAD_ENET1_COL = 31,
>> + MX6SX_PAD_ENET1_CRS = 32,
>> + MX6SX_PAD_ENET1_MDC = 33,
>> + MX6SX_PAD_ENET1_MDIO = 34,
>> + MX6SX_PAD_ENET1_RX_CLK = 35,
>> + MX6SX_PAD_ENET1_TX_CLK = 36,
>> + MX6SX_PAD_ENET2_COL = 37,
>> + MX6SX_PAD_ENET2_CRS = 38,
>> + MX6SX_PAD_ENET2_RX_CLK = 39,
>> + MX6SX_PAD_ENET2_TX_CLK = 40,
>> + MX6SX_PAD_KEY_COL0 = 41,
>> + MX6SX_PAD_KEY_COL1 = 42,
>> + MX6SX_PAD_KEY_COL2 = 43,
>> + MX6SX_PAD_KEY_COL3 = 44,
>> + MX6SX_PAD_KEY_COL4 = 45,
>> + MX6SX_PAD_KEY_ROW0 = 46,
>> + MX6SX_PAD_KEY_ROW1 = 47,
>> + MX6SX_PAD_KEY_ROW2 = 48,
>> + MX6SX_PAD_KEY_ROW3 = 49,
>> + MX6SX_PAD_KEY_ROW4 = 50,
>> + MX6SX_PAD_LCD1_CLK = 51,
>> + MX6SX_PAD_LCD1_DATA00 = 52,
>> + MX6SX_PAD_LCD1_DATA01 = 53,
>> + MX6SX_PAD_LCD1_DATA02 = 54,
>> + MX6SX_PAD_LCD1_DATA03 = 55,
>> + MX6SX_PAD_LCD1_DATA04 = 56,
>> + MX6SX_PAD_LCD1_DATA05 = 57,
>> + MX6SX_PAD_LCD1_DATA06 = 58,
>> + MX6SX_PAD_LCD1_DATA07 = 59,
>> + MX6SX_PAD_LCD1_DATA08 = 60,
>> + MX6SX_PAD_LCD1_DATA09 = 61,
>> + MX6SX_PAD_LCD1_DATA10 = 62,
>> + MX6SX_PAD_LCD1_DATA11 = 63,
>> + MX6SX_PAD_LCD1_DATA12 = 64,
>> + MX6SX_PAD_LCD1_DATA13 = 65,
>> + MX6SX_PAD_LCD1_DATA14 = 66,
>> + MX6SX_PAD_LCD1_DATA15 = 67,
>> + MX6SX_PAD_LCD1_DATA16 = 68,
>> + MX6SX_PAD_LCD1_DATA17 = 69,
>> + MX6SX_PAD_LCD1_DATA18 = 70,
>> + MX6SX_PAD_LCD1_DATA19 = 71,
>> + MX6SX_PAD_LCD1_DATA20 = 72,
>> + MX6SX_PAD_LCD1_DATA21 = 73,
>> + MX6SX_PAD_LCD1_DATA22 = 74,
>> + MX6SX_PAD_LCD1_DATA23 = 75,
>> + MX6SX_PAD_LCD1_ENABLE = 76,
>> + MX6SX_PAD_LCD1_HSYNC = 77,
>> + MX6SX_PAD_LCD1_RESET = 78,
>> + MX6SX_PAD_LCD1_VSYNC = 79,
>> + MX6SX_PAD_NAND_ALE = 80,
>> + MX6SX_PAD_NAND_CE0_B = 81,
>> + MX6SX_PAD_NAND_CE1_B = 82,
>> + MX6SX_PAD_NAND_CLE = 83,
>> + MX6SX_PAD_NAND_DATA00 = 84 ,
>> + MX6SX_PAD_NAND_DATA01 = 85,
>> + MX6SX_PAD_NAND_DATA02 = 86,
>> + MX6SX_PAD_NAND_DATA03 = 87,
>> + MX6SX_PAD_NAND_DATA04 = 88,
>> + MX6SX_PAD_NAND_DATA05 = 89,
>> + MX6SX_PAD_NAND_DATA06 = 90,
>> + MX6SX_PAD_NAND_DATA07 = 91,
>> + MX6SX_PAD_NAND_RE_B = 92,
>> + MX6SX_PAD_NAND_READY_B = 93,
>> + MX6SX_PAD_NAND_WE_B = 94,
>> + MX6SX_PAD_NAND_WP_B = 95,
>> + MX6SX_PAD_QSPI1A_DATA0 = 96,
>> + MX6SX_PAD_QSPI1A_DATA1 = 97,
>> + MX6SX_PAD_QSPI1A_DATA2 = 98,
>> + MX6SX_PAD_QSPI1A_DATA3 = 99,
>> + MX6SX_PAD_QSPI1A_DQS = 100,
>> + MX6SX_PAD_QSPI1A_SCLK = 101,
>> + MX6SX_PAD_QSPI1A_SS0_B = 102,
>> + MX6SX_PAD_QSPI1A_SS1_B = 103,
>> + MX6SX_PAD_QSPI1B_DATA0 = 104,
>> + MX6SX_PAD_QSPI1B_DATA1 = 105,
>> + MX6SX_PAD_QSPI1B_DATA2 = 106,
>> + MX6SX_PAD_QSPI1B_DATA3 = 107,
>> + MX6SX_PAD_QSPI1B_DQS = 108,
>> + MX6SX_PAD_QSPI1B_SCLK = 109,
>> + MX6SX_PAD_QSPI1B_SS0_B = 110,
>> + MX6SX_PAD_QSPI1B_SS1_B = 111,
>> + MX6SX_PAD_RGMII1_RD0 = 112,
>> + MX6SX_PAD_RGMII1_RD1 = 113,
>> + MX6SX_PAD_RGMII1_RD2 = 114,
>> + MX6SX_PAD_RGMII1_RD3 = 115,
>> + MX6SX_PAD_RGMII1_RX_CTL = 116,
>> + MX6SX_PAD_RGMII1_RXC = 117,
>> + MX6SX_PAD_RGMII1_TD0 = 118,
>> + MX6SX_PAD_RGMII1_TD1 = 119,
>> + MX6SX_PAD_RGMII1_TD2 = 120,
>> + MX6SX_PAD_RGMII1_TD3 = 121,
>> + MX6SX_PAD_RGMII1_TX_CTL = 122,
>> + MX6SX_PAD_RGMII1_TXC = 123,
>> + MX6SX_PAD_RGMII2_RD0 = 124,
>> + MX6SX_PAD_RGMII2_RD1 = 125,
>> + MX6SX_PAD_RGMII2_RD2 = 126,
>> + MX6SX_PAD_RGMII2_RD3 = 127,
>> + MX6SX_PAD_RGMII2_RX_CTL = 128,
>> + MX6SX_PAD_RGMII2_RXC = 129,
>> + MX6SX_PAD_RGMII2_TD0 = 130,
>> + MX6SX_PAD_RGMII2_TD1 = 131,
>> + MX6SX_PAD_RGMII2_TD2 = 132,
>> + MX6SX_PAD_RGMII2_TD3 = 133,
>> + MX6SX_PAD_RGMII2_TX_CTL = 134,
>> + MX6SX_PAD_RGMII2_TXC = 135,
>> + MX6SX_PAD_SD1_CLK = 136,
>> + MX6SX_PAD_SD1_CMD = 137,
>> + MX6SX_PAD_SD1_DATA0 = 138,
>> + MX6SX_PAD_SD1_DATA1 = 139,
>> + MX6SX_PAD_SD1_DATA2 = 140,
>> + MX6SX_PAD_SD1_DATA3 = 141,
>> + MX6SX_PAD_SD2_CLK = 142,
>> + MX6SX_PAD_SD2_CMD = 143,
>> + MX6SX_PAD_SD2_DATA0 = 144,
>> + MX6SX_PAD_SD2_DATA1 = 145,
>> + MX6SX_PAD_SD2_DATA2 = 146,
>> + MX6SX_PAD_SD2_DATA3 = 147,
>> + MX6SX_PAD_SD3_CLK = 148,
>> + MX6SX_PAD_SD3_CMD = 149,
>> + MX6SX_PAD_SD3_DATA0 = 150,
>> + MX6SX_PAD_SD3_DATA1 = 151,
>> + MX6SX_PAD_SD3_DATA2 = 152,
>> + MX6SX_PAD_SD3_DATA3 = 153,
>> + MX6SX_PAD_SD3_DATA4 = 154,
>> + MX6SX_PAD_SD3_DATA5 = 155,
>> + MX6SX_PAD_SD3_DATA6 = 156,
>> + MX6SX_PAD_SD3_DATA7 = 157,
>> + MX6SX_PAD_SD4_CLK = 158,
>> + MX6SX_PAD_SD4_CMD = 159,
>> + MX6SX_PAD_SD4_DATA0 = 160,
>> + MX6SX_PAD_SD4_DATA1 = 161,
>> + MX6SX_PAD_SD4_DATA2 = 162,
>> + MX6SX_PAD_SD4_DATA3 = 163,
>> + MX6SX_PAD_SD4_DATA4 = 164,
>> + MX6SX_PAD_SD4_DATA5 = 165,
>> + MX6SX_PAD_SD4_DATA6 = 166,
>> + MX6SX_PAD_SD4_DATA7 = 167,
>> + MX6SX_PAD_SD4_RESET_B = 168,
>> + MX6SX_PAD_USB_H_DATA = 169,
>> + MX6SX_PAD_USB_H_STROBE = 170,
>> +};
>> +
>> +/* Pad names for the pinmux subsystem */
>> +static const struct pinctrl_pin_desc imx6sx_pinctrl_pads[] = {
>> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE0),
>> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE1),
>> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE2),
>> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE3),
>> + IMX_PINCTRL_PIN(MX6Sx_PAD_RESERVE4),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO00),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO01),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO02),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO03),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO04),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO05),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO06),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO07),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO08),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO09),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO10),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO11),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO12),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_GPIO1_IO13),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA00),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA01),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA02),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA03),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA04),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA05),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA06),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_DATA07),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_HSYNC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_MCLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_PIXCLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_CSI_VSYNC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_COL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_CRS),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_MDIO),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_RX_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET1_TX_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_COL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_CRS),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_RX_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_ENET2_TX_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_COL4),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_KEY_ROW4),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA00),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA01),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA02),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA03),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA04),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA05),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA06),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA07),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA08),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA09),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA10),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA11),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA12),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA13),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA14),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA15),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA16),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA17),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA18),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA19),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA20),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA21),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA22),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_DATA23),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_ENABLE),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_HSYNC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_RESET),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_LCD1_VSYNC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_ALE),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE0_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CE1_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_CLE),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA00),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA01),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA02),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA03),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA04),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA05),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA06),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_DATA07),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_RE_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_READY_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WE_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_NAND_WP_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_DQS),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SCLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS0_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1A_SS1_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_DQS),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SCLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS0_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_QSPI1B_SS1_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RD3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RX_CTL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_RXC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TD3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TX_CTL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII1_TXC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RD3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RX_CTL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_RXC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TD3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TX_CTL),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_RGMII2_TXC),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_CMD),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD1_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_CMD),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD2_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_CMD),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA4),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA5),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA6),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD3_DATA7),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CLK),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_CMD),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA0),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA1),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA2),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA3),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA4),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA5),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA6),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_DATA7),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_SD4_RESET_B),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_DATA),
>> + IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
>> +};
>> +
>> +static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
>> + .pins = imx6sx_pinctrl_pads,
>> + .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
>> +};
>> +
>> +static struct of_device_id imx6sx_pinctrl_of_match[] = {
>> + { .compatible = "fsl,imx6sx-iomuxc", },
>> + { /* sentinel */ }
>> +};
>> +
>> +static int imx6sx_pinctrl_probe(struct platform_device *pdev)
>> +{
>> + return imx_pinctrl_probe(pdev, &imx6sx_pinctrl_info);
>> +}
>> +
>> +static struct platform_driver imx6sx_pinctrl_driver = {
>> + .driver = {
>> + .name = "imx6sx-pinctrl",
>> + .owner = THIS_MODULE,
>> + .of_match_table = of_match_ptr(imx6sx_pinctrl_of_match),
>> + },
>> + .probe = imx6sx_pinctrl_probe,
>> + .remove = imx_pinctrl_remove,
>> +};
>> +
>> +static int __init imx6sx_pinctrl_init(void)
>> +{
>> + return platform_driver_register(&imx6sx_pinctrl_driver);
>> +}
>> +arch_initcall(imx6sx_pinctrl_init);
>> +
>> +static void __exit imx6sx_pinctrl_exit(void)
>> +{
>> + platform_driver_unregister(&imx6sx_pinctrl_driver);
>> +}
>> +module_exit(imx6sx_pinctrl_exit);
>> +
>> +MODULE_AUTHOR("Anson Huang <Anson.Huang-KZfg59tc24xl57MIdRCFDg@public.gmane.org>");
>> +MODULE_DESCRIPTION("Freescale imx6sx pinctrl driver");
>> +MODULE_LICENSE("GPL v2");
>> --
>> 1.7.9.5
>>
>>
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^ permalink raw reply
* Re: devicetree repository separation/migration
From: Sascha Hauer @ 2014-02-19 9:08 UTC (permalink / raw)
To: Tim Bird
Cc: Olof Johansson, Jason Cooper, Grant Likely, Rob Herring,
Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala, Rob Landley,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-spec-u79uwXL29TY76Z2rM5mHXA,
devicetree-compiler-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CA+bK7J5+n2Se4cLv5WjR5B31ej7FdrGjPcjUULNrhb1UQ7=vmA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Tue, Feb 18, 2014 at 02:44:15PM -0800, Tim Bird wrote:
> I'm not in favor of separating the device tree information from the kernel.
>
> If we switch, then whatever synchronization issues other projects
> are having now with synching with the device tree info from the kernel will
> just then become the problem of the kernel developers, who will then
> have to sync with the device tree info from another repository. If the
> sync issues can't be solved now for them, why or how would it be solved
> post-separation for us? (It sounds like a zero-sum game of pain transfer
> to me.)
>
> I'm relatively unfamiliar with the arguments. Can someone provide
> a brief list of reasons this is needed, and how the inconvenience to Linux
> kernel developers will be minimized, should it proceed?
One of the reasons for doing devicetrees is to separate the hardware
description from the code so that:
- Other OSes (and bootloaders) can use the same description to start on
a given hardware
- A generic Kernel can be started on any hardware
- A hardware describes itself, makes itself more introspecitve so we can
go away from very specialized kernels
This can't be archieved when the devicetrees are constantly changing. So
we should separate the devicetrees from the kernel to make them usable
for other projects, but also to make the kernel more universally usable.
Compatibility issues will be far more obvious when kernel and
devicetrees are separated, but this will make people behave more
carefully and helps making the devicetree interface more stable and
usable.
Just to make that sure: It's an illusion that future kernels will be
100% compatible with old devicetrees, but we should at least follow a
best effort approach. If they are compatible enough to at least bring up
the hardware then this is at least enough to install a better
devicetree.
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: devicetree repository separation/migration
From: Sascha Hauer @ 2014-02-19 9:22 UTC (permalink / raw)
To: Olof Johansson
Cc: Jason Cooper, Grant Likely, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, Rob Landley,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-spec-u79uwXL29TY76Z2rM5mHXA,
devicetree-compiler-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAOesGMhvoB7vRf3H1kMaL5+MgZ2gJy=ZVNU0gsXVye9S4YGBOg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Tue, Feb 18, 2014 at 11:47:56AM -0800, Olof Johansson wrote:
> On Tue, Feb 18, 2014 at 10:18 AM, Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org> wrote:
> > On Tue, Feb 18, 2014 at 04:57:50PM +0100, Sascha Hauer wrote:
> >> On Mon, Feb 17, 2014 at 01:05:44PM -0500, Jason Cooper wrote:
> > ...
> >> > - Is the Linux development workflow ready for devicetree to move out
> >> > of the Linux Kernel?
> >>
> >> I hope so since keeping the devicetrees in sync with the kernel is a
> >> pain for all external users.
> >
> > Well, I haven't heard any screams yet. I suspect people are waiting for
> > details on the exact form it would take before complaining...
>
> I'M SCREAMING NOW. :-)
>
> Honestly though, I think we need to do this carefully. Even though we
> don't like it, there are still lots of bindings in flux and
> cross-dependencies between two independent repos will be a major pain.
>
> I think we have two options:
>
> 1. Bring out everything in the current kernel repo to a separate one,
> but do it my mirroring over. Changes go into the kernel repo first and
> then comes over to this one, but other projects can mirror the
> standalone repo without downloading a whole kernel tree.
>
> 2. Remove the kernel contents and move it over to the new repo. This
> should be done independently for each platform, and the maintainers
> get to decide if, when and how they do it. Some platforms are ready
> for it (some have been for a long time), others are not. And it's up
> to the maintainer, since they are the ones we will yell at when they
> make our life miserable by adding cross-dependencies with an external
> repo. Breakage due to the move is something we should have to put up
> with, etc.
Doing the move on a SoC/Maintainer basis is a good idea. I think the
move only makes sense for SoCs where the basic infrastructure devices
which are used by other devices are ironed out, namely interrupts,
GPIOs, DMA channels, pinctrl. As long as these are not present in a
devicetree it won't be usable by future kernels.
For i.MX I made the experience that the builtin barebox devicetree very
often is enough for my usecases so that I just throw a
imx_v6_v7_defcfonfig kernel to the board and don't have to think about
devicetrees anymore (This comes to an abrupt end when graphics is involved
though)
Sascha
--
Pengutronix e.K. | |
Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
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^ permalink raw reply
* Re: [PATCH v4 1/7] Documentation: Add device tree bindings for Freescale i.MX GPC
From: Philipp Zabel @ 2014-02-19 9:30 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Shawn Guo,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, Rob Herring, Thomas Abraham,
Tomasz Figa, Kyungmin Park, Kukjin Kim
In-Reply-To: <2328803.HhaG6blXIR@wuerfel>
Hi Arnd,
[adding Samsung guys into the loop]
Am Dienstag, den 18.02.2014, 19:10 +0100 schrieb Arnd Bergmann:
> On Tuesday 18 February 2014 16:34:41 Philipp Zabel wrote:
> > +
> > +Example of a device that is part of a power domain:
> > +
> > + vpu: vpu@02040000 {
> > + reg = <0x02040000 0x3c000>;
> > + /* ... */
> > + fsl,power-domain = <&pd_pu>;
> > + /* ... */
> > + };
> > +
>
> I'm really not too happy about platforms starting to add random
> bindings for power domains. Unfortunately I didn't catch exynos
> doing this first, but I don't want to see another platform like
> that.
>
> Can we please come up with a proper generic power domain binding
> first and then add platform specific users?
what is the process here? I've seen the samsung bindings and copied the
pattern. I guess the Exynos bindings are set in stone, and the i.MX
power domains can be handled using the same bindings.
regards
Philipp
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^ permalink raw reply
* Re: [PATCH v7 4/8] ARM: sunxi: Add driver for SD/MMC hosts found on Allwinner sunxi SoCs
From: Maxime Ripard @ 2014-02-19 9:46 UTC (permalink / raw)
To: Hans de Goede
Cc: David Lanzendörfer, devicetree-u79uwXL29TY76Z2rM5mHXA,
Ulf Hansson, Laurent Pinchart, Mike Turquette, Simon Baatz,
Emilio López, linux-mmc-u79uwXL29TY76Z2rM5mHXA, Chris Ball,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, H Hartley Sweeten,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Tejun Heo,
Guennadi Liakhovetski,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <5303C751.5090809-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 18865 bytes --]
Hi Hans,
On Tue, Feb 18, 2014 at 09:49:21PM +0100, Hans de Goede wrote:
> Hi,
>
> On 02/18/2014 04:37 PM, Maxime Ripard wrote:
>
> <snip>
>
> >>+
> >>+ for (i = 0; i < data->sg_len; i++) {
> >>+ pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN |
> >>+ SDXC_IDMAC_DES0_DIC;
> >>+
> >>+ if (data->sg[i].length == max_len)
> >>+ pdes[i].buf_size = 0; /* 0 == max_len */
> >>+ else
> >>+ pdes[i].buf_size = data->sg[i].length;
> >>+
> >>+ pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]);
> >>+ pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1];
> >>+ }
> >>+
> >>+ pdes[0].config |= SDXC_IDMAC_DES0_FD;
> >>+ pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD;
> >>+
> >>+ wmb(); /* Ensure idma_des hit main mem before we start the idmac */
> >
> >wmb ensure the proper ordering of the instructions, not flushing the
> >caches like what your comment implies.
>
> Since I put that comment there, allow me to explain. A modern ARM
> cpu core has 2 or more units handling stores. One for regular
> memory stores, and one for io-mem stores. Regular mem stores can
> be re-ordered, io stores cannot. Normally there is no "syncing"
> between the 2 store units. Cache flushing is not an issue here
> since the memory holding the descriptors for the idma controller
> is allocated cache coherent, which on arm means it is not cached.
>
> What is an issue here is the io-store starting the idmac hitting
> the io-mem before the descriptors hit the main-mem, the wmb()
> ensures this does not happen.
To expand a bit, my point was not that it was functionnally
wrong. Since you put a barrier in there, and that it resides in a
cache coherent section, we're fine.
My point was that the comment itself was misleading.
> >>+static int sunxi_mmc_prepare_dma(struct sunxi_mmc_host *smc_host,
> >>+ struct mmc_data *data)
> >>+{
> >>+ u32 dma_len;
> >>+ u32 i;
> >>+ u32 temp;
> >>+ struct scatterlist *sg;
> >>+
> >>+ dma_len = dma_map_sg(mmc_dev(smc_host->mmc), data->sg, data->sg_len,
> >>+ sunxi_mmc_get_dma_dir(data));
> >>+ if (dma_len == 0) {
> >>+ dev_err(mmc_dev(smc_host->mmc), "dma_map_sg failed\n");
> >>+ return -ENOMEM;
> >>+ }
> >>+
> >>+ for_each_sg(data->sg, sg, data->sg_len, i) {
> >>+ if (sg->offset & 3 || sg->length & 3) {
> >>+ dev_err(mmc_dev(smc_host->mmc),
> >>+ "unaligned scatterlist: os %x length %d\n",
> >>+ sg->offset, sg->length);
> >>+ return -EINVAL;
> >>+ }
> >>+ }
> >>+
> >>+ sunxi_mmc_init_idma_des(smc_host, data);
> >>+
> >>+ temp = mci_readl(smc_host, REG_GCTRL);
> >>+ temp |= SDXC_DMA_ENABLE_BIT;
> >>+ mci_writel(smc_host, REG_GCTRL, temp);
> >>+ temp |= SDXC_DMA_RESET;
> >>+ mci_writel(smc_host, REG_GCTRL, temp);
> >
> >Does it really need to be done in two steps?
>
> We don't know, so this is probably best left as is.
Ok.
> >
> >(Newline)
> >
> >>+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_SOFT_RESET);
> >>+
> >>+ if (!(data->flags & MMC_DATA_WRITE))
> >>+ mci_writel(smc_host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT);
> >>+
> >>+ mci_writel(smc_host, REG_DMAC, SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON);
> >>+
> >>+ return 0;
> >>+}
> >>+
> >>+static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host,
> >>+ struct mmc_request *req)
> >>+{
> >>+ u32 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | SDXC_STOP_ABORT_CMD
> >>+ | SDXC_CHECK_RESPONSE_CRC | MMC_STOP_TRANSMISSION;
> >>+ u32 ri = 0;
> >>+ unsigned long expire = jiffies + msecs_to_jiffies(1000);
> >>+
> >>+ mci_writel(host, REG_CARG, 0);
> >>+ mci_writel(host, REG_CMDR, cmd_val);
> >>+
> >>+ do {
> >>+ ri = mci_readl(host, REG_RINTR);
> >>+ } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) &&
> >>+ time_before(jiffies, expire));
> >>+
> >>+ if (ri & SDXC_INTERRUPT_ERROR_BIT) {
> >>+ dev_err(mmc_dev(host->mmc), "send stop command failed\n");
> >>+ if (req->stop)
> >>+ req->stop->resp[0] = -ETIMEDOUT;
> >>+ } else {
> >>+ if (req->stop)
> >>+ req->stop->resp[0] = mci_readl(host, REG_RESP0);
> >>+ }
> >>+
> >>+ mci_writel(host, REG_RINTR, 0xffff);
> >>+}
> >>+
> >>+static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *smc_host)
> >>+{
> >>+ struct mmc_command *cmd = smc_host->mrq->cmd;
> >>+ struct mmc_data *data = smc_host->mrq->data;
> >>+
> >>+ /* For some cmds timeout is normal with sd/mmc cards */
> >>+ if ((smc_host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == SDXC_RESP_TIMEOUT &&
> >>+ (cmd->opcode == SD_IO_SEND_OP_COND || cmd->opcode == SD_IO_RW_DIRECT))
> >>+ return;
> >>+
> >>+ dev_err(mmc_dev(smc_host->mmc),
> >
> >I'd rather put it at a debug loglevel.
>
> Erm, this only happens if something is seriously wrong.
Still. Something would be seriously wrong in the MMC
driver/controller. You don't want to bloat the whole kernel logs with
the dump of your registers just because the MMC is failing. This is of
no interest to anyone but someone that would actually try to debug
what's wrong.
> >>+ /* Make sure the controller is in a sane state before enabling irqs */
> >>+ ret = sunxi_mmc_init_host(host->mmc);
> >>+ if (ret)
> >>+ return ret;
> >>+
> >>+ host->irq = platform_get_irq(pdev, 0);
> >>+ ret = devm_request_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 0,
> >>+ "sunxi-mmc", host);
> >>+ if (ret == 0)
> >>+ disable_irq(host->irq);
> >
> >The disable_irq is useless here. Just exit.
>
> No it is not note the ret == 0, this is not an error handling path!
Doh... Right.
My bad.
> This is done under an if because we want to do the sunxi_mmc_exit_host
> regardless of the request_irq succeeding or not.
>
> >
> >>+
> >>+ /* And put it back in reset */
> >>+ sunxi_mmc_exit_host(host);
> >
> >Hu? If it's in reset, how can it generate some IRQs?
>
> Yes, that is why we do the whole dance of init controller, get irq,
> disable irq, drop it back in reset (until the mmc subsys does a power on
> of the mmc card / sdio dev).
>
> Sometime the controller asserts the irq in reset for some reason, so
> without the dance as soon as we do the devm_request_irq we get an irq,
> and worse, not only do we get an irq, we cannot clear it since writing to
> the interrupt status register does not work when the controller is in reset,
> so we get stuck re-entering the irq handler.
Hmmm, I see. It probably deserves some commenting here too then.
> >>+ return ret;
> >>+}
> >>+
> >>+static int sunxi_mmc_probe(struct platform_device *pdev)
> >>+{
> >>+ struct sunxi_mmc_host *host;
> >>+ struct mmc_host *mmc;
> >>+ int ret;
> >>+
> >>+ mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev);
> >>+ if (!mmc) {
> >>+ dev_err(&pdev->dev, "mmc alloc host failed\n");
> >>+ return -ENOMEM;
> >>+ }
> >>+
> >>+ ret = mmc_of_parse(mmc);
> >>+ if (ret)
> >>+ goto error_free_host;
> >>+
> >>+ host = mmc_priv(mmc);
> >>+ host->mmc = mmc;
> >>+ spin_lock_init(&host->lock);
> >>+ tasklet_init(&host->tasklet, sunxi_mmc_tasklet, (unsigned long)host);
> >>+
> >>+ ret = sunxi_mmc_resource_request(host, pdev);
> >>+ if (ret)
> >>+ goto error_free_host;
> >>+
> >>+ host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
> >>+ &host->sg_dma, GFP_KERNEL);
> >>+ if (!host->sg_cpu) {
> >>+ dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n");
> >>+ ret = -ENOMEM;
> >>+ goto error_free_host;
> >>+ }
> >>+
> >>+ mmc->ops = &sunxi_mmc_ops;
> >>+ mmc->max_blk_count = 8192;
> >>+ mmc->max_blk_size = 4096;
> >>+ mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des);
> >>+ mmc->max_seg_size = (1 << host->idma_des_size_bits);
> >>+ mmc->max_req_size = mmc->max_seg_size * mmc->max_segs;
> >>+ /* 400kHz ~ 50MHz */
> >>+ mmc->f_min = 400000;
> >>+ mmc->f_max = 50000000;
> >>+ /* available voltages */
> >>+ if (!IS_ERR(host->vmmc))
> >>+ mmc->ocr_avail = mmc_regulator_get_ocrmask(host->vmmc);
> >>+ else
> >>+ mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
> >>+
> >>+ mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
> >>+ MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | MMC_CAP_UHS_SDR50 |
> >>+ MMC_CAP_UHS_DDR50 | MMC_CAP_SDIO_IRQ | MMC_CAP_DRIVER_TYPE_A;
> >>+ mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP;
> >>+
> >>+ ret = mmc_add_host(mmc);
> >>+
> >>+ if (ret)
> >>+ goto error_free_dma;
> >>+
> >>+ dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq);
> >>+ platform_set_drvdata(pdev, mmc);
> >
> >This should be before the registration. Otherwise, you're racy.
>
> Nope, we only need this to get the data on sunxi_mmc_remove, everywhere
> else the data is found through the mmc-host struct.
Still, if anyone makes a following patch using the platform_device for
some reason, we will have a race condition, without any way to notice
it.
Plus, you're doing all the other bits of initialization of your
structures much earlier, why not be consistent and having all of them
at the same place?
> >
> >>+ return 0;
> >>+
> >>+error_free_dma:
> >>+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
> >>+error_free_host:
> >>+ mmc_free_host(mmc);
> >>+ return ret;
> >>+}
> >>+
> >>+static int sunxi_mmc_remove(struct platform_device *pdev)
> >>+{
> >>+ struct mmc_host *mmc = platform_get_drvdata(pdev);
> >>+ struct sunxi_mmc_host *host = mmc_priv(mmc);
> >>+
> >>+ mmc_remove_host(mmc);
> >>+ sunxi_mmc_exit_host(host);
> >>+ tasklet_disable(&host->tasklet);
> >>+ dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma);
> >>+ mmc_free_host(mmc);
> >>+
> >>+ return 0;
> >>+}
> >>+
> >>+static struct platform_driver sunxi_mmc_driver = {
> >>+ .driver = {
> >>+ .name = "sunxi-mmc",
> >>+ .owner = THIS_MODULE,
> >>+ .of_match_table = of_match_ptr(sunxi_mmc_of_match),
> >>+ },
> >>+ .probe = sunxi_mmc_probe,
> >>+ .remove = sunxi_mmc_remove,
> >>+};
> >>+module_platform_driver(sunxi_mmc_driver);
> >>+
> >>+MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver");
> >>+MODULE_LICENSE("GPL v2");
> >>+MODULE_AUTHOR("David Lanzend?rfer <david.lanzendoerfer-Z7Kmv9EsliU@public.gmane.org>");
> >>+MODULE_ALIAS("platform:sunxi-mmc");
> >>diff --git a/drivers/mmc/host/sunxi-mmc.h b/drivers/mmc/host/sunxi-mmc.h
> >>new file mode 100644
> >>index 0000000..75eaa02
> >>--- /dev/null
> >>+++ b/drivers/mmc/host/sunxi-mmc.h
> >>@@ -0,0 +1,239 @@
> >>+/*
> >>+ * Driver for sunxi SD/MMC host controllers
> >>+ * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd.
> >>+ * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh-jFKXxz0WcGyYHARAtoI1EgC/G2K4zDHf@public.gmane.org>
> >>+ * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch>
> >>+ * (C) Copyright 2013-2014 David Lanzend?rfer <david.lanzendoerfer@o2s.ch>
> >>+ * (C) Copyright 2013-2014 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> >>+ *
> >>+ * This program is free software; you can redistribute it and/or
> >>+ * modify it under the terms of the GNU General Public License as
> >>+ * published by the Free Software Foundation; either version 2 of
> >>+ * the License, or (at your option) any later version.
> >>+ */
> >>+
> >>+#ifndef __SUNXI_MMC_H__
> >>+#define __SUNXI_MMC_H__
> >>+
> >>+/* register offset definitions */
> >>+#define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */
> >>+#define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */
> >>+#define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */
> >>+#define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */
> >>+#define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */
> >>+#define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */
> >>+#define SDXC_REG_CMDR (0x18) /* SMC Command Register */
> >>+#define SDXC_REG_CARG (0x1C) /* SMC Argument Register */
> >>+#define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */
> >>+#define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */
> >>+#define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */
> >>+#define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */
> >>+#define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */
> >>+#define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */
> >>+#define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */
> >>+#define SDXC_REG_STAS (0x3C) /* SMC Status Register */
> >>+#define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */
> >>+#define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */
> >>+#define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */
> >>+#define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */
> >>+#define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */
> >>+#define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */
> >>+#define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */
> >>+#define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */
> >>+#define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */
> >>+#define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */
> >>+#define SDXC_REG_CHDA (0x90)
> >>+#define SDXC_REG_CBDA (0x94)
> >>+
> >>+#define mci_readl(host, reg) \
> >>+ readl((host)->reg_base + SDXC_##reg)
> >>+#define mci_writel(host, reg, value) \
> >>+ writel((value), (host)->reg_base + SDXC_##reg)
> >
> >Please use some inline functions here.
> >
> >>+/* global control register bits */
> >>+#define SDXC_SOFT_RESET BIT(0)
> >>+#define SDXC_FIFO_RESET BIT(1)
> >>+#define SDXC_DMA_RESET BIT(2)
> >>+#define SDXC_HARDWARE_RESET (SDXC_SOFT_RESET|SDXC_FIFO_RESET|SDXC_DMA_RESET)
> >>+#define SDXC_INTERRUPT_ENABLE_BIT BIT(4)
> >>+#define SDXC_DMA_ENABLE_BIT BIT(5)
> >>+#define SDXC_DEBOUNCE_ENABLE_BIT BIT(8)
> >>+#define SDXC_POSEDGE_LATCH_DATA BIT(9)
> >>+#define SDXC_DDR_MODE BIT(10)
> >>+#define SDXC_MEMORY_ACCESS_DONE BIT(29)
> >>+#define SDXC_ACCESS_DONE_DIRECT BIT(30)
> >>+#define SDXC_ACCESS_BY_AHB BIT(31)
> >>+#define SDXC_ACCESS_BY_DMA (0U << 31)
> >
> >Isn't it 0?
>
> Yes, but is is the inverse of ACCESS_BY_DMA, which
> this makes much clearer then just 0 does.
>
> >
> >>+/* clock control bits */
> >>+#define SDXC_CARD_CLOCK_ON BIT(16)
> >>+#define SDXC_LOW_POWER_ON BIT(17)
> >>+/* bus width */
> >>+#define SDXC_WIDTH1 (0)
> >>+#define SDXC_WIDTH4 (1)
> >>+#define SDXC_WIDTH8 (2)
> >>+/* smc command bits */
> >>+#define SDXC_RESP_EXPIRE BIT(6)
> >>+#define SDXC_LONG_RESPONSE BIT(7)
> >>+#define SDXC_CHECK_RESPONSE_CRC BIT(8)
> >>+#define SDXC_DATA_EXPIRE BIT(9)
> >>+#define SDXC_WRITE BIT(10)
> >>+#define SDXC_SEQUENCE_MODE BIT(11)
> >>+#define SDXC_SEND_AUTO_STOP BIT(12)
> >>+#define SDXC_WAIT_PRE_OVER BIT(13)
> >>+#define SDXC_STOP_ABORT_CMD BIT(14)
> >>+#define SDXC_SEND_INIT_SEQUENCE BIT(15)
> >>+#define SDXC_UPCLK_ONLY BIT(21)
> >>+#define SDXC_READ_CEATA_DEV BIT(22)
> >>+#define SDXC_CCS_EXPIRE BIT(23)
> >>+#define SDXC_ENABLE_BIT_BOOT BIT(24)
> >>+#define SDXC_ALT_BOOT_OPTIONS BIT(25)
> >>+#define SDXC_BOOT_ACK_EXPIRE BIT(26)
> >>+#define SDXC_BOOT_ABORT BIT(27)
> >>+#define SDXC_VOLTAGE_SWITCH BIT(28)
> >>+#define SDXC_USE_HOLD_REGISTER BIT(29)
> >>+#define SDXC_START BIT(31)
> >>+/* interrupt bits */
> >>+#define SDXC_RESP_ERROR BIT(1)
> >>+#define SDXC_COMMAND_DONE BIT(2)
> >>+#define SDXC_DATA_OVER BIT(3)
> >>+#define SDXC_TX_DATA_REQUEST BIT(4)
> >>+#define SDXC_RX_DATA_REQUEST BIT(5)
> >>+#define SDXC_RESP_CRC_ERROR BIT(6)
> >>+#define SDXC_DATA_CRC_ERROR BIT(7)
> >>+#define SDXC_RESP_TIMEOUT BIT(8)
> >>+#define SDXC_DATA_TIMEOUT BIT(9)
> >>+#define SDXC_VOLTAGE_CHANGE_DONE BIT(10)
> >>+#define SDXC_FIFO_RUN_ERROR BIT(11)
> >>+#define SDXC_HARD_WARE_LOCKED BIT(12)
> >>+#define SDXC_START_BIT_ERROR BIT(13)
> >>+#define SDXC_AUTO_COMMAND_DONE BIT(14)
> >>+#define SDXC_END_BIT_ERROR BIT(15)
> >>+#define SDXC_SDIO_INTERRUPT BIT(16)
> >>+#define SDXC_CARD_INSERT BIT(30)
> >>+#define SDXC_CARD_REMOVE BIT(31)
> >>+#define SDXC_INTERRUPT_ERROR_BIT (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | \
> >>+ SDXC_DATA_CRC_ERROR | SDXC_RESP_TIMEOUT | \
> >>+ SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \
> >>+ SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | \
> >>+ SDXC_END_BIT_ERROR) /* 0xbbc2 */
> >>+#define SDXC_INTERRUPT_DONE_BIT (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \
> >>+ SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE)
> >>+/* status */
> >>+#define SDXC_RXWL_FLAG BIT(0)
> >>+#define SDXC_TXWL_FLAG BIT(1)
> >>+#define SDXC_FIFO_EMPTY BIT(2)
> >>+#define SDXC_FIFO_FULL BIT(3)
> >>+#define SDXC_CARD_PRESENT BIT(8)
> >>+#define SDXC_CARD_DATA_BUSY BIT(9)
> >>+#define SDXC_DATA_FSM_BUSY BIT(10)
> >>+#define SDXC_DMA_REQUEST BIT(31)
> >>+#define SDXC_FIFO_SIZE (16)
> >>+/* Function select */
> >>+#define SDXC_CEATA_ON (0xceaaU << 16)
> >>+#define SDXC_SEND_IRQ_RESPONSE BIT(0)
> >>+#define SDXC_SDIO_READ_WAIT BIT(1)
> >>+#define SDXC_ABORT_READ_DATA BIT(2)
> >>+#define SDXC_SEND_CCSD BIT(8)
> >>+#define SDXC_SEND_AUTO_STOPCCSD BIT(9)
> >>+#define SDXC_CEATA_DEV_INTERRUPT_ENABLE_BIT BIT(10)
> >>+/* IDMA controller bus mod bit field */
> >>+#define SDXC_IDMAC_SOFT_RESET BIT(0)
> >>+#define SDXC_IDMAC_FIX_BURST BIT(1)
> >>+#define SDXC_IDMAC_IDMA_ON BIT(7)
> >>+#define SDXC_IDMAC_REFETCH_DES BIT(31)
> >>+/* IDMA status bit field */
> >>+#define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0)
> >>+#define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1)
> >>+#define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2)
> >>+#define SDXC_IDMAC_DESTINATION_INVALID BIT(4)
> >>+#define SDXC_IDMAC_CARD_ERROR_SUM BIT(5)
> >>+#define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8)
> >>+#define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9)
> >>+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_TX BIT(10)
> >>+#define SDXC_IDMAC_HOST_ABORT_INTERRUPT_RX BIT(10)
> >>+#define SDXC_IDMAC_IDLE (0U << 13)
> >
> >Ditto
> >
> >>+#define SDXC_IDMAC_SUSPEND (1U << 13)
> >>+#define SDXC_IDMAC_DESC_READ (2U << 13)
> >>+#define SDXC_IDMAC_DESC_CHECK (3U << 13)
> >>+#define SDXC_IDMAC_READ_REQUEST_WAIT (4U << 13)
> >>+#define SDXC_IDMAC_WRITE_REQUEST_WAIT (5U << 13)
> >>+#define SDXC_IDMAC_READ (6U << 13)
> >>+#define SDXC_IDMAC_WRITE (7U << 13)
> >>+#define SDXC_IDMAC_DESC_CLOSE (8U << 13)
> >
> >Please use BIT as much as possible here.
>
> Erm lets not do that, nor remove the 0 << 13, this are all
> values to store in a multi-bit field which lives in bits 13-xx,
> changing the values which happen to be power of 2 into BIT
> macros is not helpful.
Ok.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH v4 1/2] memory: ti-aemif: introduce AEMIF driver
From: Ivan Khoronzhuk @ 2014-02-19 10:32 UTC (permalink / raw)
To: Greg KH
Cc: santosh.shilimkar-l0cyMroinI0, rob-VoJi6FS/r0vR7s880joybQ,
linux-lFZ/pmaqli7XmaaqVzeoHQ,
galak-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, rob.herring-bsGFqQB8/DxBDgjK7y7TUQ,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
grygorii.strashko-l0cyMroinI0, dwmw2-wEGCiKHe2LqWVfeAwA7xHQ,
nsekhar-l0cyMroinI0, [initial author] Murali Karicheri
In-Reply-To: <20140218203049.GA18647-U8xfFu+wG4EAvxtiuMwx3w@public.gmane.org>
On 02/18/2014 10:30 PM, Greg KH wrote:
> On Wed, Feb 05, 2014 at 09:46:13PM +0200, Ivan Khoronzhuk wrote:
>> Add new AEMIF driver for EMIF16 Texas Instruments controller.
>> The EMIF16 module is intended to provide a glue-less interface to
>> a variety of asynchronous memory devices like ASRA M, NOR and NAND
>> memory. A total of 256M bytes of any of these memories can be
>> accessed at any given time via 4 chip selects with 64M byte access
>> per chip select.
>>
>> Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR
>> are not supported.
>>
>> This controller is used on SoCs like Davinci, Keysone2
>>
>> Acked-by: Santosh Shilimkar <santosh.shilimkar-l0cyMroinI0@public.gmane.org
>> Signed-off-by: [initial author] Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> What's this [] stuff?
>
> If Murali wrote this, that name needs to be in a "From:" line in the
> patch to properly attribute it, and drop the [] here.
Ok, I'll delete [] stuff.
>> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk-l0cyMroinI0@public.gmane.org>
>> ---
>> drivers/memory/Kconfig | 11 ++
>> drivers/memory/Makefile | 1 +
>> drivers/memory/ti-aemif.c | 429 ++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 441 insertions(+)
>> create mode 100644 drivers/memory/ti-aemif.c
>>
>> diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
>> index 29a11db..7bc3982 100644
>> --- a/drivers/memory/Kconfig
>> +++ b/drivers/memory/Kconfig
>> @@ -7,6 +7,17 @@ menuconfig MEMORY
>>
>> if MEMORY
>>
>> +config TI_AEMIF
>> + tristate "Texas Instruments AEMIF driver"
>> + depends on (ARCH_DAVINCI || ARCH_KEYSTONE) && OF
>> + help
>> + This driver is for the AEMIF module available in Texas Instruments
>> + SoCs. AEMIF stands for Asynchronous External Memory Interface and
>> + is intended to provide a glue-less interface to a variety of
>> + asynchronuous memory devices like ASRAM, NOR and NAND memory. A total
>> + of 256M bytes of any of these memories can be accessed at a given
>> + time via four chip selects with 64M byte access per chip select.
>> +
>> config TI_EMIF
>> tristate "Texas Instruments EMIF driver"
>> depends on ARCH_OMAP2PLUS
>> diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
>> index 969d923..d4e150c 100644
>> --- a/drivers/memory/Makefile
>> +++ b/drivers/memory/Makefile
>> @@ -5,6 +5,7 @@
>> ifeq ($(CONFIG_DDR),y)
>> obj-$(CONFIG_OF) += of_memory.o
>> endif
>> +obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
>> obj-$(CONFIG_TI_EMIF) += emif.o
>> obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
>> obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o
>> diff --git a/drivers/memory/ti-aemif.c b/drivers/memory/ti-aemif.c
>> new file mode 100644
>> index 0000000..8d15d87
>> --- /dev/null
>> +++ b/drivers/memory/ti-aemif.c
>> @@ -0,0 +1,429 @@
>> +/*
>> + * TI AEMIF driver
>> + *
>> + * Copyright (C) 2010 - 2013 Texas Instruments Incorporated. http://www.ti.com/
>> + *
>> + * Authors:
>> + * Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
>> + * Ivan Khoronzhuk <ivan.khoronzhuk-l0cyMroinI0@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License version 2 as
>> + * published by the Free Software Foundation.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/err.h>
>> +#include <linux/io.h>
>> +#include <linux/kernel.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/of_platform.h>
>> +#include <linux/platform_device.h>
>> +
>> +#define TA_SHIFT 2
>> +#define RHOLD_SHIFT 4
>> +#define RSTROBE_SHIFT 7
>> +#define RSETUP_SHIFT 13
>> +#define WHOLD_SHIFT 17
>> +#define WSTROBE_SHIFT 20
>> +#define WSETUP_SHIFT 26
>> +#define EW_SHIFT 30
>> +#define SS_SHIFT 31
>> +
>> +#define TA(x) ((x) << TA_SHIFT)
>> +#define RHOLD(x) ((x) << RHOLD_SHIFT)
>> +#define RSTROBE(x) ((x) << RSTROBE_SHIFT)
>> +#define RSETUP(x) ((x) << RSETUP_SHIFT)
>> +#define WHOLD(x) ((x) << WHOLD_SHIFT)
>> +#define WSTROBE(x) ((x) << WSTROBE_SHIFT)
>> +#define WSETUP(x) ((x) << WSETUP_SHIFT)
>> +#define EW(x) ((x) << EW_SHIFT)
>> +#define SS(x) ((x) << SS_SHIFT)
>> +
>> +#define ASIZE_MAX 0x1
>> +#define TA_MAX 0x3
>> +#define RHOLD_MAX 0x7
>> +#define RSTROBE_MAX 0x3f
>> +#define RSETUP_MAX 0xf
>> +#define WHOLD_MAX 0x7
>> +#define WSTROBE_MAX 0x3f
>> +#define WSETUP_MAX 0xf
>> +#define EW_MAX 0x1
>> +#define SS_MAX 0x1
>> +#define NUM_CS 4
>> +
>> +#define TA_VAL(x) (((x) & TA(TA_MAX)) >> TA_SHIFT)
>> +#define RHOLD_VAL(x) (((x) & RHOLD(RHOLD_MAX)) >> RHOLD_SHIFT)
>> +#define RSTROBE_VAL(x) (((x) & RSTROBE(RSTROBE_MAX)) >> RSTROBE_SHIFT)
>> +#define RSETUP_VAL(x) (((x) & RSETUP(RSETUP_MAX)) >> RSETUP_SHIFT)
>> +#define WHOLD_VAL(x) (((x) & WHOLD(WHOLD_MAX)) >> WHOLD_SHIFT)
>> +#define WSTROBE_VAL(x) (((x) & WSTROBE(WSTROBE_MAX)) >> WSTROBE_SHIFT)
>> +#define WSETUP_VAL(x) (((x) & WSETUP(WSETUP_MAX)) >> WSETUP_SHIFT)
>> +#define EW_VAL(x) (((x) & EW(EW_MAX)) >> EW_SHIFT)
>> +#define SS_VAL(x) (((x) & SS(SS_MAX)) >> SS_SHIFT)
>> +
>> +#define NRCSR_OFFSET 0x00
>> +#define AWCCR_OFFSET 0x04
>> +#define A1CR_OFFSET 0x10
>> +
>> +#define ACR_ASIZE_MASK 0x3
>> +#define ACR_EW_MASK BIT(30)
>> +#define ACR_SS_MASK BIT(31)
>> +#define ASIZE_16BIT 1
>> +
>> +#define CONFIG_MASK (TA(TA_MAX) | \
>> + RHOLD(RHOLD_MAX) | \
>> + RSTROBE(RSTROBE_MAX) | \
>> + RSETUP(RSETUP_MAX) | \
>> + WHOLD(WHOLD_MAX) | \
>> + WSTROBE(WSTROBE_MAX) | \
>> + WSETUP(WSETUP_MAX) | \
>> + EW(EW_MAX) | SS(SS_MAX) | \
>> + ASIZE_MAX)
>> +
>> +#define DRV_NAME "ti-aemif"
> What's wrong with KBUILD_MODNAME?
Yes, I'll drop DRV_NAME in favour of KBUILD_MODNAME
>> +static int aemif_probe(struct platform_device *pdev)
>> +{
>> + int ret = -ENODEV, i;
> Extra spaces?
>
> Split this into two lines?
Ok.
>> + struct resource *res;
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node;
>> + struct device_node *child_np;
>> + struct aemif_device *aemif;
>> +
>> + if (np == NULL)
>> + return 0;
>> +
>> + aemif = devm_kzalloc(dev, sizeof(*aemif), GFP_KERNEL);
>> + if (!aemif) {
>> + dev_err(dev, "cannot allocate memory for aemif\n");
> Not needed, you'll get a message from kzalloc about this.\
Ok.
>
>> + return -ENOMEM;
>> + }
>> +
>> + platform_set_drvdata(pdev, aemif);
>> +
>> + aemif->clk = devm_clk_get(dev, NULL);
>> + if (IS_ERR(aemif->clk)) {
>> + dev_err(dev, "cannot get clock 'aemif'\n");
>> + return PTR_ERR(aemif->clk);
> No freeing memory?
There is no need to free memory explicitly.
devm_kzalloc is used instead of kzalloc.
>> + }
>> +
>> + clk_prepare_enable(aemif->clk);
>> + aemif->clk_rate = clk_get_rate(aemif->clk) / MSEC_PER_SEC;
>> +
>> + if (of_device_is_compatible(np, "ti,da850-aemif"))
>> + aemif->cs_offset = 2;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + aemif->base = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(aemif->base)) {
>> + ret = PTR_ERR(aemif->base);
>> + goto error;
>> + }
>> +
>> + /*
>> + * For every controller device node, there is a cs device node that
>> + * describe the bus configuration parameters. This functions iterate
>> + * over these nodes and update the cs data array.
>> + */
>> + for_each_available_child_of_node(np, child_np) {
>> + ret = of_aemif_parse_abus_config(pdev, child_np);
>> + if (ret < 0)
>> + goto error;
>> + }
>> +
>> + for (i = 0; i < aemif->num_cs; i++) {
>> + ret = aemif_config_abus(pdev, i);
>> + if (ret < 0) {
>> + dev_err(dev, "Error configuring chip select %d\n",
>> + aemif->cs_data[i].cs);
>> + goto error;
>> + }
>> + }
>> +
>> + /*
>> + * Create a child devices explicitly from here to
>> + * guarantee that the child will be probed after the AEMIF timing
>> + * parameters are set.
>> + */
>> + for_each_available_child_of_node(np, child_np) {
>> + ret = of_platform_populate(child_np, NULL, NULL, dev);
>> + if (ret < 0)
>> + goto error;
>> + }
>> +
>> + return 0;
>> +error:
>> + clk_disable_unprepare(aemif->clk);
>> + return ret;
> No freeing memory?
devm_* allocations were used, so no need.
>
>> +}
>> +
>> +static int aemif_remove(struct platform_device *pdev)
>> +{
>> + struct aemif_device *aemif = platform_get_drvdata(pdev);
>> + clk_disable_unprepare(aemif->clk);
> Extra line needed.
Ok
Thanks!
--
Regards,
Ivan Khoronzhuk
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^ permalink raw reply
* Re: [PATCH v2 0/3] usb: chipidea: msm: Clean and fix glue layer driver
From: Ivan T. Ivanov @ 2014-02-19 10:32 UTC (permalink / raw)
To: Tim Bird
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Rob Landley, Peter Chen, Grant Likely, Greg Kroah-Hartman,
David Brown, devicetree@vger.kernel.org,
Linux Kernel Mailing List, linux-usb, linux-arm-msm
In-Reply-To: <CA+bK7J7D1bgehNMaMtWWggZ5KDBfZ8LK0bEYUARmc8OD3wa89Q@mail.gmail.com>
Hi,
I will need some time to recreate USB test
environment. I will come back when I am ready.
Regards,
Ivan
^ permalink raw reply
* Re: [PATCH v2] ARM/dts: hdmi-codec: panda/es dt entries
From: Paolo Pisati @ 2014-02-19 10:54 UTC (permalink / raw)
To: Peter Ujfalusi; +Cc: Paolo Pisati, bcousson, tony, devicetree, linux-omap
In-Reply-To: <5304681C.4010106@ti.com>
On Wed, Feb 19, 2014 at 10:15:24AM +0200, Peter Ujfalusi wrote:
> > diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > index 88c6a05..f4aeaa1 100644
> > --- a/arch/arm/boot/dts/omap4-panda-common.dtsi
> > +++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
> > @@ -36,9 +36,15 @@
> > };
> > };
> >
> > + hdmi_audio: hdmi_audio@0 {
> > + compatible = "linux,hdmi-audio";
> > + status = "okay";
> > + };
> > +
> > sound: sound {
> > compatible = "ti,abe-twl6040";
> > ti,model = "PandaBoard";
> > + ti,audio-codec = <&hdmi_audio>;
>
> I don't think this is going to work. The omap-abe-twl6040 machine driver only
> handles mcpdm and dmic right know.
> 'ti,audio-codec' is not even supported and it is kind of misleading naming in
> this context since twl6040 is also a codec, so why only the dummy-hdmi codec
> deserves to be called as codec.
i see what you mean: i thought that hdmi_audio to actually work had to be
referenced inside the sound node (hence my inclusion there) but i was wrong and
it had nothing to do with twl6040,
would this one be ok for you?
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 88c6a05..b6dd458 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -36,6 +36,11 @@
};
};
+ hdmi_audio: hdmi_audio@0 {
+ compatible = "linux,hdmi-audio";
+ status = "okay";
+ };
+
sound: sound {
compatible = "ti,abe-twl6040";
ti,model = "PandaBoard";
> Furthermore: we have the omap-hdmi-card machine driver to handle the HDMI
> audio. It lacks DT support AFAIK but should not be a big deal to add the bindings.
> To get the hdmi audio working you also need to have phandle for the omap-hdmi
> DAI, the codec alone is not enough.
>
you mean sound/soc/omap/omap-hdmi-card.c? that's exactly what i'm trying to fix.
With the above patch, plus:
-CONFIG_DISPLAY_CONNECTOR_HDMI=m
+CONFIG_DISPLAY_CONNECTOR_HDMI=y
CONFIG_DISPLAY_ENCODER_TFP410=m
-CONFIG_DISPLAY_ENCODER_TPD12S015=m
+CONFIG_DISPLAY_ENCODER_TPD12S015=y
to make the omap-hdmi-audio-dai attach (sound/soc/omap/omap-hdmi.c)
and something like this (that is not upstreamable as i understand
but is an unfortunate fallout from the board removal[*]):
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -335,6 +335,11 @@ static struct platform_device omap_hdmi_audio = {
.id = -1,
};
+static struct platform_device hdmi_audio_codec = {
+ .name = "hdmi-audio-codec",
+ .id = -1,
+};
+
static void __init omap_init_hdmi_audio(void)
{
struct omap_hwmod *oh;
@@ -349,6 +354,7 @@ static void __init omap_init_hdmi_audio(void)
"Can't build omap_device for omap-hdmi-audio-dai.\n");
platform_device_register(&omap_hdmi_audio);
+ platform_device_register(&hdmi_audio_codec);
}
#else
static inline void omap_init_hdmi_audio(void) {}
i finally get my OMAPHDMI device back:
flag@panda:~$ cat /proc/asound/cards
0 [OMAPHDMI ]: OMAPHDMI - OMAPHDMI
OMAPHDMI
1 [PandaBoardES ]: PandaBoardES - PandaBoardES
PandaBoardES
[*]: in arch/arm/mach-omap2/board-omap4panda.c we had:
-static struct platform_device panda_hdmi_audio_codec = {
- .name = "hdmi-audio-codec",
- .id = -1,
-};
-static struct platform_device *panda_devices[] __initdata = {
...
- &panda_hdmi_audio_codec,
...
-};
that was registered as part of omap4_panda_init():
- platform_add_devices(panda_devices, ARRAY_SIZE(panda_devices));
--
bye,
p.
^ permalink raw reply related
* [RFC PATCH v2 0/2] Syscon early initialization
From: Michal Simek @ 2014-02-19 11:04 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann
Cc: Mike Turquette, Kumar Gala, Peter Crosthwaite, Ian Campbell,
Rob Herring, James Hogan, Michal Simek, Felipe Pena, Pawel Moll,
Soren Brinkmann, Stephen Warren, devicetree, Stephen Boyd,
Russell King, Lee Jones, Rob Herring, Josh Cartwright,
Steffen Trumtrar, linux-kernel, Samuel Ortiz, Mark Rutland
[-- Attachment #1: Type: text/plain, Size: 1578 bytes --]
Hi,
this series come from my discussion with Arnd at KS and then
on some other threads/IRCs(Arnd and Mark) that SoC vendors
are more and more try to add misc functionality to
one memory region. For this purpose syscon driver is in the kernel.
But regular syscon driver is initialized too late
and platforms are trying to create specific code to handle it.
For this purpose the series have been created to provide
early syscon initialization and regmap creation first
and then attaching device.
The last patch is zynq specific patch to clear slcr driver
and clock driver can profit from it too when clk regmap is ready.
Also moving syscon driver from mfs should be consider.
Mark already applied the first part to his regmap repo
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git tags/nodev
Thanks for your comments,
Michal
Changes in v2:
- Fix bad logic in early_syscon_probe
- Fix compilation failure for x86_64 reported by zero day testing system
- Regmap change available here
git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git tags/nodev
Michal Simek (2):
mfd: syscon: Support early initialization
ARM: zynq: Use early syscon initialization
arch/arm/boot/dts/zynq-7000.dtsi | 1 +
arch/arm/mach-zynq/common.c | 6 +-
arch/arm/mach-zynq/slcr.c | 42 +------------
drivers/clk/zynq/clkc.c | 57 ++++++-----------
drivers/mfd/syscon.c | 128 +++++++++++++++++++++++++++++++++------
include/linux/mfd/syscon.h | 11 ++++
6 files changed, 145 insertions(+), 100 deletions(-)
--
1.8.2.3
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^ permalink raw reply
* [RFC PATCH v2 2/2] ARM: zynq: Use early syscon initialization
From: Michal Simek @ 2014-02-19 11:04 UTC (permalink / raw)
To: linux-arm-kernel, Arnd Bergmann
Cc: monstr, Josh Cartwright, Steffen Trumtrar, Rob Herring,
Peter Crosthwaite, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Russell King, Mike Turquette,
Soren Brinkmann, Stephen Boyd, Stephen Warren, James Hogan,
Felipe Pena, devicetree, linux-kernel
In-Reply-To: <cover.1392807832.git.michal.simek@xilinx.com>
[-- Attachment #1: Type: text/plain, Size: 6084 bytes --]
Use early syscon initialization to simplify slcr code.
- Remove two slcr inits (zynq_slcr_init, zynq_early_slcr_init)
- Directly use regmap accesses in zynq_slcr_read/write
- Remove zynq_clock_init() and use addresses from syscon
(This is the most problematic part now because clock
doesn't support regmap accesses that's why reading
slcr base is ugly. There are some attempts to get
clk regmap to work - for example:
https://lkml.org/lkml/2013/10/16/112)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
---
Changes in v2: None
Especially look at slcr.c which is much simpler than was before.
clkc.c will be simpler when regmap support is added because then
syscon_early_regmap_lookup_by_phandle() will be called
without zynq_slcr_base search.
---
arch/arm/boot/dts/zynq-7000.dtsi | 1 +
arch/arm/mach-zynq/common.c | 6 ++---
arch/arm/mach-zynq/slcr.c | 42 ++---------------------------
drivers/clk/zynq/clkc.c | 57 ++++++++++++----------------------------
4 files changed, 23 insertions(+), 83 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 7284499..e414489 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -135,6 +135,7 @@
compatible = "xlnx,zynq-slcr", "syscon";
reg = <0xF8000000 0x1000>;
ranges;
+ syscon = <&slcr>;
clkc: clkc@100 {
#clock-cells = <1>;
compatible = "xlnx,ps7-clkc";
diff --git a/arch/arm/mach-zynq/common.c b/arch/arm/mach-zynq/common.c
index 9d3c88e..78589e3 100644
--- a/arch/arm/mach-zynq/common.c
+++ b/arch/arm/mach-zynq/common.c
@@ -28,6 +28,7 @@
#include <linux/of.h>
#include <linux/irqchip.h>
#include <linux/irqchip/arm-gic.h>
+#include <linux/mfd/syscon.h>
#include <linux/slab.h>
#include <linux/sys_soc.h>
@@ -130,15 +131,14 @@ out:
of_platform_populate(NULL, of_default_bus_match_table, NULL, parent);
platform_device_register(&zynq_cpuidle_device);
-
- zynq_slcr_init();
}
static void __init zynq_timer_init(void)
{
+ early_syscon_init();
+
zynq_early_slcr_init();
- zynq_clock_init();
of_clk_init(NULL);
clocksource_of_init();
}
diff --git a/arch/arm/mach-zynq/slcr.c b/arch/arm/mach-zynq/slcr.c
index 594b280..a89b082 100644
--- a/arch/arm/mach-zynq/slcr.c
+++ b/arch/arm/mach-zynq/slcr.c
@@ -35,7 +35,6 @@
#define SLCR_PSS_IDCODE_DEVICE_SHIFT 12
#define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F
-static void __iomem *zynq_slcr_base;
static struct regmap *zynq_slcr_regmap;
/**
@@ -48,11 +47,6 @@ static struct regmap *zynq_slcr_regmap;
*/
static int zynq_slcr_write(u32 val, u32 offset)
{
- if (!zynq_slcr_regmap) {
- writel(val, zynq_slcr_base + offset);
- return 0;
- }
-
return regmap_write(zynq_slcr_regmap, offset, val);
}
@@ -66,12 +60,7 @@ static int zynq_slcr_write(u32 val, u32 offset)
*/
static int zynq_slcr_read(u32 *val, u32 offset)
{
- if (zynq_slcr_regmap)
- return regmap_read(zynq_slcr_regmap, offset, val);
-
- *val = readl(zynq_slcr_base + offset);
-
- return 0;
+ return regmap_read(zynq_slcr_regmap, offset, val);
}
/**
@@ -169,24 +158,6 @@ void zynq_slcr_cpu_stop(int cpu)
}
/**
- * zynq_slcr_init - Regular slcr driver init
- *
- * Return: 0 on success, negative errno otherwise.
- *
- * Called early during boot from platform code to remap SLCR area.
- */
-int __init zynq_slcr_init(void)
-{
- zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
- if (IS_ERR(zynq_slcr_regmap)) {
- pr_err("%s: failed to find zynq-slcr\n", __func__);
- return -ENODEV;
- }
-
- return 0;
-}
-
-/**
* zynq_early_slcr_init - Early slcr init function
*
* Return: 0 on success, negative errno otherwise.
@@ -202,20 +173,11 @@ int __init zynq_early_slcr_init(void)
pr_err("%s: no slcr node found\n", __func__);
BUG();
}
-
- zynq_slcr_base = of_iomap(np, 0);
- if (!zynq_slcr_base) {
- pr_err("%s: Unable to map I/O memory\n", __func__);
- BUG();
- }
-
- np->data = (__force void *)zynq_slcr_base;
+ zynq_slcr_regmap = syscon_early_regmap_lookup_by_phandle(np, "syscon");
/* unlock the SLCR so that registers can be changed */
zynq_slcr_unlock();
- pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
-
of_node_put(np);
return 0;
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index c812b93..b2fd160 100644
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -214,6 +214,10 @@ err:
clks[clk1] = ERR_PTR(-ENOMEM);
}
+struct syscon {
+ void __iomem *base;
+};
+
static void __init zynq_clk_setup(struct device_node *np)
{
int i;
@@ -227,6 +231,19 @@ static void __init zynq_clk_setup(struct device_node *np)
const char *periph_parents[4];
const char *swdt_ext_clk_mux_parents[2];
const char *can_mio_mux_parents[NUM_MIO_PINS];
+ struct resource res;
+ void __iomem *zynq_slcr_base;
+
+ struct device_node *slcr = of_get_parent(np);
+ struct syscon *syscon = slcr->data;
+ zynq_slcr_base = syscon->base;
+
+ if (of_address_to_resource(np, 0, &res)) {
+ pr_err("%s: failed to get resource\n", np->name);
+ return;
+ }
+
+ zynq_clkc_base = zynq_slcr_base + res.start;
pr_info("Zynq clock init\n");
@@ -569,43 +586,3 @@ static void __init zynq_clk_setup(struct device_node *np)
}
CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
-
-void __init zynq_clock_init(void)
-{
- struct device_node *np;
- struct device_node *slcr;
- struct resource res;
-
- np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
- if (!np) {
- pr_err("%s: clkc node not found\n", __func__);
- goto np_err;
- }
-
- if (of_address_to_resource(np, 0, &res)) {
- pr_err("%s: failed to get resource\n", np->name);
- goto np_err;
- }
-
- slcr = of_get_parent(np);
-
- if (slcr->data) {
- zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
- } else {
- pr_err("%s: Unable to get I/O memory\n", np->name);
- of_node_put(slcr);
- goto np_err;
- }
-
- pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
-
- of_node_put(slcr);
- of_node_put(np);
-
- return;
-
-np_err:
- of_node_put(np);
- BUG();
- return;
-}
--
1.8.2.3
[-- Attachment #2: Type: application/pgp-signature, Size: 198 bytes --]
^ permalink raw reply related
* [PATCH v6 00/18] ahci: library-ise ahci_platform, add sunxi driver and cleanup imx driver
From: Hans de Goede @ 2014-02-19 12:01 UTC (permalink / raw)
To: Tejun Heo, Maxime Ripard
Cc: Oliver Schinagl, Richard Zhu, Roger Quadros, Lee Jones,
linux-ide-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
Hi all,
Here is v6 of my patchset for adding ahci-sunxi support. This has been
tested with Allwinner A10, Allwinner A20 and Freeware imx6x SoCs, including
suspend / resume. Note that since my last revision the ahci_imx driver has
also grown imx53 sata support, it would be good if some-one could test that
with this series.
History:
v1, by Olliver Schinagl:
This was using the approach of having a platform device which probe method
creates a new child platform device which gets driven by ahci_platform.c,
as done by ahci_imx.c .
v2, by Hans de Goede:
Stand-alone platform driver based on Olliver's work
v3, by Hans de Goede:
patch-series, with 4 different parts
a) Make ahci_platform.c more generic, handle more then 1 clk, target pwr
regulator
b) New ahci-sunxi code only populating ahci_platform_data, passed to
ahci_platform.c to of_device_id matching.
c) Refactor ahci-imx code to work the same as the new ahci-sunxi code, this
is the reason why v3 is an RFC, I'm waiting for the wandboard I ordered to
arrive so that I can actually test this.
d) dts bindings for the sunxi ahci parts
v4, by Hans de Goede:
patch-series, with 5 different parts:
a) Make ahci_platform.c more generic, handle more then 1 clk, target pwr
regulator
b) Turn parts of ahci_platform.c into a library for use by other drivers
c) New ahci-sunxi driver using the ahci_platform.c library functionality
d) Refactor ahci-imx code to work the same as the new ahci-sunxi code
e) dts bindings for the sunxi ahci parts
v5:
v4 + the following changes:
1) fsl,imx6q driver is now tested
2) fixed suspend / resume on fsl,imx6q
3) Modifed devicetree node naming to match dt spec
4) Reworked the busy waiting code in the sunxi-phy handling as suggested by
Russell King
v6:
v5 rebased on top of 3.14-rc3 + the following changes
1) Added Roger Quadros' generic phy support series
2) Added a "ARM: sun4i: dt: Remove grouping + simple-bus for regulators" dts
patch
Tejun, can you please add patches 1-15 to your ata tree for 3.15 ?
Maxime, can you please add patch 16-18 to your dts tree for 3.15 ?
Thanks & Regards,
Hans
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