* Re: [PATCHv2 03/16] Documentation: dt: add OMAP iommu bindings
From: Suman Anna @ 2014-02-24 18:09 UTC (permalink / raw)
To: florian.vaussard, Tony Lindgren, iommu, devicetree, Mark Rutland,
Kumar Gala, Rob Herring
Cc: Joerg Roedel, Laurent Pinchart, linux-omap, linux-arm-kernel
In-Reply-To: <530B41AD.2030608@epfl.ch>
Mark, Kumar, Rob,
> On 02/13/2014 07:15 PM, Suman Anna wrote:
>> From: Florian Vaussard <florian.vaussard@epfl.ch>
>>
>> This patch adds the iommu bindings for all OMAP2+ SoCs. Apart from
>> the standard bindings used by OMAP peripherals, this patch uses a
>> 'dma-window' (already used by Tegra SMMU) and adds two OMAP custom
>> bindings - 'ti,#tlb-entries' and 'ti,iommu-bus-err-back'.
>>
>> Signed-off-by: Florian Vaussard <florian.vaussard@epfl.ch>
>> [s-anna@ti.com: split bindings document, add dra7 and bus error back]
>> Signed-off-by: Suman Anna <s-anna@ti.com>
>> ---
>> .../devicetree/bindings/iommu/ti,omap-iommu.txt | 28 ++++++++++++++++++++++
>> 1 file changed, 28 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt
>> new file mode 100644
>> index 0000000..116492d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iommu/ti,omap-iommu.txt
>> @@ -0,0 +1,28 @@
>> +OMAP2+ IOMMU
>> +
>> +Required properties:
>> +- compatible : Should be one of,
>> + "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
>> + "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
>> + "ti,dra7-iommu" for DRA7xx IOMMU instances
>> +- ti,hwmods : Name of the hwmod associated with the IOMMU instance
>> +- reg : Address space for the configuration registers
>> +- interrupts : Interrupt specifier for the IOMMU instance
>> +- dma-window : IOVA start address and length
>> +
>> +Optional properties:
>> +- ti,#tlb-entries : Number of entries in the translation look-aside buffer.
>> + Should be either 8 or 32 (default: 32)
>> +- ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
>> + back a bus error response on MMU faults.
>> +
>> +Example:
>> + /* OMAP3 ISP MMU */
>> + mmu_isp: mmu@480bd400 {
>> + compatible = "ti,omap2-iommu";
>> + reg = <0x480bd400 0x80>;
>> + interrupts = <24>;
>> + ti,hwmods = "mmu_isp";
>> + ti,#tlb-entries = <8>;
>> + dma-window = <0 0xfffff000>;
>> + };
>>
>
> Any comments on this binding?
Can one of you look through this binding and ack/suggest changes?
As I mentioned in the cover letter, the optional properties usually
apply only to specific subsystems, so do let me know if this should be
handled using compatible string per subsystem per SoC rather than per SoC.
regards
Suman
^ permalink raw reply
* Re: [PATCH 00/10] pinctrl: mvebu: remove hard-coded addresses from Dove pinctrl
From: Jason Cooper @ 2014-02-24 18:10 UTC (permalink / raw)
To: Sebastian Hesselbarth, Linus Walleij
Cc: Mark Rutland, Andrew Lunn, Russell King, Pawel Moll, Ian Campbell,
linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Rob Landley,
Kumar Gala, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1393231382-11078-1-git-send-email-sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Sebastian, Linus,
I've now created mvebu/pinctrl-dove for this series. It's based on
v3.14-rc1, and depends on mvebu/pinctrl (which depends on
mvebu/pinctrl-3xx).
I've kept this series in a separate branch in case we encounter an
unforeseen problem with something in here. Then this branch can be
dropped, and /pinctrl-3xx and /pinctrl will still make it in.
So, all patches except 3 and 4 are in mvebu/pinctrl-dove. 3 and 4 are
in mvebu/dt.
thx,
Jason.
On Mon, Feb 24, 2014 at 09:42:52AM +0100, Sebastian Hesselbarth wrote:
> This is a patches separated from one sent earlier [1] with just the
> removal of any hard-coded reg addresses from Dove pinctrl stub. This
> is a required step for Dove to leave mach-dove, hop into mach-mvebu,
> and become part of multi_v7.
>
> In the meantime, support for new Armada 375/38x was added that also
> contain patches for pinctrl [2]. The cleanup patches [3] split off from
> the original patch set take care of pinctrl-related changes for Armada
> 375/38x. Since this patch set now already depends on Armada 375/38x
> pinctrl through those cleanup patches, we take care of Armada 375/38x
> binding updates here, too.
>
> For Dove, this patch set removes all hardcoded addresses from
> pinctrl-dove by either requesting additional resources or a syscon
> provided regmap for global config registers. As this changes existing
> driver to DT binding relationship, all additional resources are probed
> in a backward compatible way. If the corresponding resource cannot be
> found, we derive it from the existing pinctrl resource and warn about
> the old DTB firmware.
>
> Patches 1-2 add or update binding documentation for dove, global config
> syscon, and pinctrl-dove. Patch 2 also documents missing reg property
> requirement for other mvebu pinctrl nodes, including new Armada 375/38x.
>
> Patch 3 and 4 add the new pinctrl reg property values and global config
> register syscon to exisiting dove.dtsi.
>
> Patches 5-6 request either additional reg ranges or the syscon regmap
> in a DT-backward compatible way. If any resource cannot be derived from
> DT node, we warn about an old DTB firmware.
>
> Patches 7-10 finally remove any hardcoded addresses from Dove SoC
> pinctrl driver and use the iomap/regmap resources instead.
>
> DT and binding related patches have also been sent to DT maintainers
> and corresponding lists, additional pinctrl related patches have been
> sent to pinctrl/mvebu maintainers and LAKML only.
>
> This patch set is based on v3.14-rc1 and depends on some cleanup patches
> that will go into v3.15. We have a lot of stuff for v3.15 already in
> mvebu, so I am okay with postponing this and/or the following dove-to-
> mvebu patches for v3.16. As Jason prepares mvebu pinctrl PRs for LinusW,
> it is up to him when to take it with LinusW's Acked-by.
>
> Nevertheless, there is an *unstable* branch based on v3.14-rc1, with
> mvebu/pinctrl-3xx and mvebu/pinctrl merged in at (still named -for-3.15)
>
> https://github.com/shesselba/linux-dove.git unstable/dove-pinctrl-for-3.15_v1
>
> [1] http://www.spinics.net/lists/arm-kernel/msg303496.html
> [2] http://www.spinics.net/lists/arm-kernel/msg306409.html
> [3] http://lkml.org/lkml/2014/2/23/43
>
> Sebastian Hesselbarth (10):
> devicetree: bindings: add missing Marvell Dove SoC documentation
> devicetree: bindings: update MVEBU pinctrl binding documentation
> ARM: dove: add additional pinctrl registers
> ARM: dove: add global-config register node
> pinctrl: mvebu: dove: request additional resources
> pinctrl: mvebu: dove: request syscon regmap for global registers
> pinctrl: mvebu: dove: use remapped mpp base registers
> pinctrl: mvebu: dove: use remapped mpp4 register
> pinctrl: mvebu: dove: use remapped pmu_mpp registers
> pinctrl: mvebu: dove: use global register regmap
>
> .../devicetree/bindings/arm/marvell,dove.txt | 22 ++
> .../pinctrl/marvell,armada-370-pinctrl.txt | 1 +
> .../pinctrl/marvell,armada-375-pinctrl.txt | 1 +
> .../pinctrl/marvell,armada-38x-pinctrl.txt | 1 +
> .../bindings/pinctrl/marvell,armada-xp-pinctrl.txt | 1 +
> .../bindings/pinctrl/marvell,dove-pinctrl.txt | 1 +
> .../bindings/pinctrl/marvell,kirkwood-pinctrl.txt | 1 +
> .../bindings/pinctrl/marvell,mvebu-pinctrl.txt | 2 +-
> arch/arm/boot/dts/dove.dtsi | 10 +-
> drivers/pinctrl/mvebu/Kconfig | 1 +
> drivers/pinctrl/mvebu/pinctrl-dove.c | 286 +++++++++++++--------
> 11 files changed, 213 insertions(+), 114 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell,dove.txt
>
> ---
> Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Cc: Pawel Moll <pawel.moll-5wv7dgnIgG8@public.gmane.org>
> Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> Cc: Ian Campbell <ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org>
> Cc: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Cc: Rob Landley <rob-VoJi6FS/r0vR7s880joybQ@public.gmane.org>
> Cc: Linus Walleij <linus.walleij-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Cc: Russell King <linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> Cc: Jason Cooper <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
> Cc: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> Cc: Gregory Clement <gregory.clement-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> --
> 1.8.5.3
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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^ permalink raw reply
* Re: [PATCH RFC v1 3/3] clk: Add handling of clk parent and rate assigned from DT
From: Sylwester Nawrocki @ 2014-02-24 18:11 UTC (permalink / raw)
To: Mike Turquette, Grant Likely
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-lFZ/pmaqli7XmaaqVzeoHQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
galak-sgV2jX0FEOL9JmXXK+q4OQ,
kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ,
t.figa-Sze3O3UU22JBDgjK7y7TUQ
In-Reply-To: <20140224004826.22529.87768@quantum>
On 24/02/14 01:48, Mike Turquette wrote:
> Quoting Sylwester Nawrocki (2014-02-21 02:38:21)
>> > On 20/02/14 15:09, Grant Likely wrote:
>> > [...]
>>>>> > >> > diff --git a/Documentation/devicetree/bindings/clock/clock-bindings.txt b/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>> > >> > index 7c52c29..d618498 100644
>>>>> > >> > --- a/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>> > >> > +++ b/Documentation/devicetree/bindings/clock/clock-bindings.txt
>>>>> > >> > @@ -115,3 +115,27 @@ clock signal, and a UART.
>>>>> > >> > ("pll" and "pll-switched").
>>>>> > >> > * The UART has its baud clock connected the external oscillator and its
>>>>> > >> > register clock connected to the PLL clock (the "pll-switched" signal)
>>>>> > >> > +
>>>>> > >> > +==Static initial configuration of clock parent and clock frequency==
>>>>> > >> > +
>>>>> > >> > +Some platforms require static configuration of (parts of) the clock controller
>>>>> > >> > +often determined by the board design. Such a configuration can be specified in
>>>>> > >> > +a clock consumer node through [clk-name]-clk-parent and [clk-name]-clk-rate DT
>>>>> > >> > +properties. The former should contain phandle and clock specifier of the parent
>>>>> > >> > +clock, the latter the required clock's frequency value (one cell). "clk-name"
>>>>> > >> > +should be listed in the clock-names property and a phandle and a clock specifier
>>>>> > >> > +pair corresponding to it should be present in the clocks property.
>>>>> > >> > +
>>>>> > >> > + uart@a000 {
>>>>> > >> > + compatible = "fsl,imx-uart";
>>>>> > >> > + reg = <0xa000 0x1000>;
>>>>> > >> > + ...
>>>>> > >> > + clocks = <&clkcon 0>, <&clkcon 3>;
>>>>> > >> > + clock-names = "baud", "mux";
>>>>> > >> > +
>>>>> > >> > + mux-clk-parent = <&pll 1>;
>>>>> > >> > + baud-clk-rate = <460800>;
>>> > >
>>> > > This mixes patterns for references to clocks. Plus it requires composing
>>> > > property names which is a little painful. I'd rather see a list of
>>> > > tuples to match the existing pattern already in use
>>> > >
>>> > > clocks = <&clkcon 0>, <&clkcon 3>;
>>> > > clock-names = "baud", "mux";
>>> > > clock-parents = <0> <&pll 1>;
>>> > > clock-rates = <0> <460800>;
>> >
>> > Thank you for the review. This looks much better to me. My bad, I wasn't
>> > aware 0 can be used to denote an empty phandle like this. ePAPR seems not
>> > to be specifying exact meaning of the 'phandle' property values, except
>> > they be unique. Anyway, it seems to be clearly documented within the
>> > __of_parse_phandle_with_args() function.
>> >
>> > I'll try this modified binding instead, presumably it would be useful to
>> > have a variant of __of_parse_phandle_with_args() function which would
>> > accept a context data containing result of previous call within an iteration,
>> > similarly as of_property_next_string() is written. So we don't iterate
>> > from beginning of the list with each __of_parse_phandle_with_args() call.
>> > But it's an optimization issue that could be considered separately I guess.
>
> I was always partial to the regulator style of blahblah-supply but
> Grant's suggestion is much cleaner with respect to the rest of the clock
> binding.
I don't have a strong opinion, I'm slightly inclined towards Grant's suggestion,
which doesn't have a problem of limiting effective clk name to 21 characters.
Also DT property names with underscores coming from the clock names are a bit
incorrect and it might be not immediately obvious which part of name is a
canonical property's name and which is clock's name. Let's consider property
names like:
mux-clk-parent, divider-clk-rate, sclk_mmc0-clk-parent, sclk_uart_baud0-clk-parent,
etc.
> I guess it will be a bit ugly if a very long array is needed with a
> sparse attribute. E.g. 20 clocks specified in the 'clocks' property and
> only a single clock needs to have its parent or rate specified.
It was also concerning me, but this inconvenience could be mitigated by
reordering content of clocks/clock-names properties so that the clocks for
which parents and/or rates are being assigned are first on the list.
Then number of padding zeros is minimized.
> Is there a reason not to support both methods?
--
Regards,
Sylwester
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^ permalink raw reply
* Re: [PATCHv4 0/7] omap hwspinlock dt support
From: Suman Anna @ 2014-02-24 18:14 UTC (permalink / raw)
To: Ohad Ben-Cohen, Mark Rutland
Cc: devicetree, Tony Lindgren, linux-kernel, Kumar Gala, linux-omap,
linux-arm-kernel
In-Reply-To: <52F9282B.5000702@ti.com>
Mark, Ohad,
On 02/10/2014 01:27 PM, Suman Anna wrote:
> Mark,
>
> On 01/13/2014 06:19 PM, Suman Anna wrote:
>> Hi,
>>
>> This is an updated series mainly addressing Mark Rutland's comments
>> about hwlock specifier being always one-cell. The series adds the
>> support for #hwlock-cells property and adds a simple default OF
>> translate function.
>>
>> The DTS patches from previous series have already been merged, and
>> needs this property to be added. This is handled in a separate series
>> that only deals with OMAP hwspinlock DTS patches.
>>
>> The series, along with the DTS patches, is tested on top of v3.13-rc8
>> plus Tero's v13 clock DT series and Tony's 3.14 staged branches. The
>> validation on OMAP5, DRA7, AM437 requires Tero's series with couple of
>> additional base patches for AM43xx. AM43xx functionality needs a hwmod
>> fix [1] for creating the associated omap_device as well.
>>
>
> Can you please take a look at this series and give your ack on the
> bindings if you do not have any further comments? The only comments so
> far are from Bjorn on the OF helpers.
>
Gentle reminder, can you provide your acks/comments?
regards
Suman
^ permalink raw reply
* Re: [PATCH v13 2/3] ata: Add APM X-Gene SoC AHCI SATA host controller driver
From: Tejun Heo @ 2014-02-24 18:31 UTC (permalink / raw)
To: Loc Ho
Cc: olof, arnd, linux-scsi, linux-ide, devicetree, linux-arm-kernel,
ddutile, jcm, patches, Tuan Phan, Suman Tripathi
In-Reply-To: <1393221265-13057-3-git-send-email-lho@apm.com>
Hello, Loc.
Almost there. Just one more thing.
On Sun, Feb 23, 2014 at 10:54:24PM -0700, Loc Ho wrote:
....
> +static int xgene_ahci_init_memram(struct xgene_ahci_context *ctx)
> +{
> + void __iomem *diagcsr = ctx->csr_base + SATA_DIAG_OFFSET;
> + int try;
> + u32 val;
> +
> + val = readl(diagcsr + CFG_MEM_RAM_SHUTDOWN);
> + if (val == 0) {
> + dev_dbg(ctx->dev, "memory already released from shutdown\n");
> + return 0;
> + }
> + dev_dbg(ctx->dev, "Release memory from shutdown\n");
> + /* SATA controller memory in shutdown. Remove from shutdown. */
> + writel(0x0, diagcsr + CFG_MEM_RAM_SHUTDOWN);
> + readl(diagcsr + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
> +
> + /* Check for at least ~1ms */
> + try = 1000;
> + do {
> + val = readl(diagcsr + BLOCK_MEM_RDY);
> + if (val != 0xFFFFFFFF)
> + usleep_range(1, 100);
> + } while (val != 0xFFFFFFFF && try-- > 0);
> + if (try <= 0) {
> + dev_err(ctx->dev, "failed to release memory from shutdown\n");
> + return -ENODEV;
> + }
> + return 0;
> +}
Hmm... ISTR raising this issue before but the above is way more
elaborate than necessary. This isn't in any sense a hot path and 1ms
is short enough to handle it simply. If the only thing being
addressed here is that the init may take upto 1ms, you might as well
just do
writel(0x0, diagcsr + CFG_MEM_RAM_SHUTDOWN);
readl(diagcsr + CFG_MEM_RAM_SHUTDOWN); /* Force a barrier */
msleep(1); /* reset may take upto 1ms */
if (readl(diagcsr + BLOCK_MEM_RDY) != 0xFFFFFFFF) {
dev_err(...);
return -ENODEV;
}
return 0;
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH v13 3/3] arm64: Add APM X-Gene SoC AHCI SATA host controller DTS entries
From: Tejun Heo @ 2014-02-24 18:32 UTC (permalink / raw)
To: Loc Ho
Cc: olof, arnd, linux-scsi, linux-ide, devicetree, linux-arm-kernel,
ddutile, jcm, patches, Tuan Phan, Suman Tripathi
In-Reply-To: <1393221265-13057-4-git-send-email-lho@apm.com>
On Sun, Feb 23, 2014 at 10:54:25PM -0700, Loc Ho wrote:
> Signed-off-by: Loc Ho <lho@apm.com>
> Signed-off-by: Tuan Phan <tphan@apm.com>
> Signed-off-by: Suman Tripathi <stripathi@apm.com>
This doesn't apply cleanly to libata/for-3.15. How should this be
routed?
Thanks.
--
tejun
^ permalink raw reply
* Re: [PATCH v11 09/15] usb: phy: Add set_wakeup API
From: Sergei Shtylyov @ 2014-02-24 18:41 UTC (permalink / raw)
To: Peter Chen, balbi-l0cyMroinI0, shawn.guo-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
grant.likely-QSEj5FYQhm4dnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8
Cc: linux-usb-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
festevam-Re5JQEeQqe8AvxtiuMwx3w, marex-ynQEQJNshbs,
kernel-bIcnvbaLZ9MEGnE8C9+IrQ, m.grzeschik-bIcnvbaLZ9MEGnE8C9+IrQ,
frank.li-KZfg59tc24xl57MIdRCFDg,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-doc-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1393208467-6355-10-git-send-email-peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
Hello.
On 02/24/2014 05:21 AM, Peter Chen wrote:
> This API is used to set wakeup enable at PHY registers, in that
> case, the PHY can be waken up from suspend due to external events,
> like vbus change, dp/dm change and id change.
> Signed-off-by: Peter Chen <peter.chen-KZfg59tc24xl57MIdRCFDg@public.gmane.org>
> ---
> include/linux/usb/phy.h | 16 ++++++++++++++++
> 1 files changed, 16 insertions(+), 0 deletions(-)
> diff --git a/include/linux/usb/phy.h b/include/linux/usb/phy.h
> index 6c0b1c5..c2c6f49 100644
> --- a/include/linux/usb/phy.h
> +++ b/include/linux/usb/phy.h
> @@ -111,6 +111,13 @@ struct usb_phy {
> int (*set_suspend)(struct usb_phy *x,
> int suspend);
>
> + /*
> + * Set wakeup enable for PHY, in that case, the PHY can be
> + * waken up from suspend status due to external events,
s/waken/woken/
WBR, Sergei
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^ permalink raw reply
* [PATCH] ARM: dts: keystone: add AEMIF/NAND device entry
From: Ivan Khoronzhuk @ 2014-02-24 18:52 UTC (permalink / raw)
To: santosh.shilimkar
Cc: mark.rutland, devicetree, grygorii.strashko, linux, pawel.moll,
ijc+devicetree, robh+dt, galak, Ivan Khoronzhuk, linux-arm-kernel
Add AEMIF/NAND device entry.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
---
Based on
git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone.git
keystone/master
arch/arm/boot/dts/k2hk-evm.dts | 52 +++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/keystone.dtsi | 13 +++++++++++
2 files changed, 65 insertions(+)
diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
index 1d8ea6e..a08581b 100644
--- a/arch/arm/boot/dts/k2hk-evm.dts
+++ b/arch/arm/boot/dts/k2hk-evm.dts
@@ -84,3 +84,55 @@
&usb {
status = "okay";
};
+
+&aemif {
+ cs0 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clock-ranges;
+ ranges;
+
+ ti,cs-chipselect = <0>;
+ /* all timings in nanoseconds */
+ ti,cs-min-turnaround-ns = <12>;
+ ti,cs-read-hold-ns = <6>;
+ ti,cs-read-strobe-ns = <23>;
+ ti,cs-read-setup-ns = <9>;
+ ti,cs-write-hold-ns = <8>;
+ ti,cs-write-strobe-ns = <23>;
+ ti,cs-write-setup-ns = <8>;
+
+ nand@0,0 {
+ compatible = "ti,keystone-nand","ti,davinci-nand";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0 0 0x4000000
+ 1 0 0x0000100>;
+
+ ti,davinci-chipselect = <0>;
+ ti,davinci-mask-ale = <0x2000>;
+ ti,davinci-mask-cle = <0x4000>;
+ ti,davinci-mask-chipsel = <0>;
+ nand-ecc-mode = "hw";
+ ti,davinci-ecc-bits = <4>;
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x100000>;
+ read-only;
+ };
+
+ partition@100000 {
+ label = "params";
+ reg = <0x100000 0x80000>;
+ read-only;
+ };
+
+ partition@180000 {
+ label = "ubifs";
+ reg = <0x180000 0x7E80000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
index 4eceb46..af80cb2 100644
--- a/arch/arm/boot/dts/keystone.dtsi
+++ b/arch/arm/boot/dts/keystone.dtsi
@@ -266,5 +266,18 @@
ti,ngpio = <32>;
ti,davinci-gpio-unbanked = <32>;
};
+
+ aemif: aemif@21000A00 {
+ compatible = "ti,keystone-aemif", "ti,davinci-aemif";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ clocks = <&clkaemif>;
+ clock-names = "aemif";
+ clock-ranges;
+
+ reg = <0x21000A00 0x00000100>;
+ ranges = <0 0 0x30000000 0x10000000
+ 1 0 0x21000A00 0x00000100>;
+ };
};
};
--
1.8.3.2
^ permalink raw reply related
* Re: [PATCH] ARM: tegra: add device tree for SHIELD
From: Stephen Warren @ 2014-02-24 18:53 UTC (permalink / raw)
To: Alexandre Courbot, Thierry Reding, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Russell King
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1393237593-28121-1-git-send-email-acourbot-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On 02/24/2014 03:26 AM, Alexandre Courbot wrote:
> Add a device tree for NVIDIA SHIELD. The set of enabled features is
> still minimal with no display option (although HDMI should be easy
> to get to work) and USB requiring external power.
You could add a simple-framebuffer node for now, I think?
> diff --git a/arch/arm/boot/dts/tegra114-roth.dts b/arch/arm/boot/dts/tegra114-roth.dts
> + memory {
> + reg = <0x80000000 0x79600000>;
It might be worth a comment here pointing out that the rest of RAM is
reserved for some carveouts/..., or at least that these values are set
this way in order to match what the bootloader usually passes to
downstream kernels in the command-line?
> + i2c@7000d000 {
> + palmas: pmic@58 {
> + compatible = "ti,palmas";
> + reg = <0x58>;
> + interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
> + ti,irq-externally-inverted;
Unfortunately, the patch I sent to document/implement that last property
hasn't yet been ack'd/applied, so I'll hold off applying this until it has.
> + /* Wifi */
> + sdhci@78000000 {
> + status = "okay";
> + bus-width = <4>;
> + broken-cd;
> + keep-power-in-suspend;
> + cap-sdio-irq;
Is non-removable better than broken-cd, or are they entirely unrelated?
Should we add broken-cd and/or cap-sdio-irq to the SDIO WiFi on other
boards (Springbank, Ventana, Cardhu)?
> + usb-phy@7d000000 {
> + status = "okay";
> + nvidia,xcvr-setup = <7>;
> + nvidia,xcvr-lsfslew = <2>;
> + nvidia,xcvr-lsrslew = <2>;
> + interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
> + dr_mode = "otg";
While opt is probably accurate, we don't actually support otg upstream,
but only host. While the DT is supposed to represent HW rather than
SW/OS details, I've tried to avoid putting otg into the DT, since I'm
not sure that the DT binding for otg is stable, since we can't test it,
whereas host probably is. Still, this is a pretty minor detail, and we
can ignore that if you want ("otg" evidently /works/ fine on Seaboard,
so it's OK if you keep this).
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^ permalink raw reply
* Re: [PATCH v5 04/10] V4L: Add driver for s5k6a3 image sensor
From: Baruch Siach @ 2014-02-24 19:38 UTC (permalink / raw)
To: Sylwester Nawrocki
Cc: linux-media, devicetree, mark.rutland, linux-samsung-soc, a.hajda,
kyungmin.park, robh+dt, galak, kgene.kim, linux-arm-kernel
In-Reply-To: <1393263322-28215-5-git-send-email-s.nawrocki@samsung.com>
Hi Sylwester,
On Mon, Feb 24, 2014 at 06:35:16PM +0100, Sylwester Nawrocki wrote:
> This patch adds subdev driver for Samsung S5K6A3 raw image sensor.
> As it is intended at the moment to be used only with the Exynos
> FIMC-IS (camera ISP) subsystem it is pretty minimal subdev driver.
> It doesn't do any I2C communication since the sensor is controlled
> by the ISP and its own firmware.
> This driver, if needed, can be updated in future into a regular
> subdev driver where the main CPU communicates with the sensor
> directly.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
[...]
> +static int s5k6a3_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
> +{
> + struct v4l2_mbus_framefmt *format = v4l2_subdev_get_try_format(fh, 0);
> +
> + *format = s5k6a3_formats[0];
> + format->width = S5K6A3_DEFAULT_WIDTH;
> + format->height = S5K6A3_DEFAULT_HEIGHT;
> +
> + return 0;
> +}
> +
> +static const struct v4l2_subdev_internal_ops s5k6a3_sd_internal_ops = {
> + .open = s5k6a3_open,
> +};
Where is this used?
baruch
--
http://baruch.siach.name/blog/ ~. .~ Tk Open Systems
=}------------------------------------------------ooO--U--Ooo------------{=
- baruch@tkos.co.il - tel: +972.2.679.5364, http://www.tkos.co.il -
^ permalink raw reply
* Re: [PATCHv1 5/6] HSI: Introduce OMAP SSI driver
From: Sebastian Reichel @ 2014-02-24 19:42 UTC (permalink / raw)
To: Nishanth Menon
Cc: Mark Rutland, Linus Walleij, Shubhrajyoti Datta, Carlos Chinea,
Tony Lindgren, grant.likely@linaro.org, rob.herring@calxeda.com,
Pawel Moll, Stephen Warren, Ian Campbell, Rob Landley,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-omap@vger.kernel.org, Pali Rohár,
Ивайло Димитров,
Joni Lapilainen, Aaro Koskinen
In-Reply-To: <530B6BC3.6070306@ti.com>
[-- Attachment #1: Type: text/plain, Size: 1771 bytes --]
On Mon, Feb 24, 2014 at 09:56:51AM -0600, Nishanth Menon wrote:
> On 02/24/2014 09:51 AM, Mark Rutland wrote:
> > On Sun, Feb 23, 2014 at 11:50:00PM +0000, Sebastian Reichel wrote:
>
> [...]
> >> +static int omap_ssi_port_runtime_suspend(struct device *dev)
> >> +{
> >> + struct hsi_port *port = dev_get_drvdata(dev);
> >> + struct omap_ssi_port *omap_port = hsi_port_drvdata(port);
> >> + struct hsi_controller *ssi = to_hsi_controller(port->device.parent);
> >> + struct omap_ssi_controller *omap_ssi = hsi_controller_drvdata(ssi);
> >> +
> >> + dev_dbg(dev, "port runtime suspend!\n");
> >> +
> >> + ssi_set_port_mode(omap_port, SSI_MODE_SLEEP);
> >> + if (omap_ssi->get_loss)
> >> + omap_port->loss_count =
> >> + (*omap_ssi->get_loss)(ssi->device.parent);
> >
> > You don't need to do (*struct->func)(args) when invoking a function
> > pointer. You can jsut have struct->func(args) as we do elsewhere. This
> > can be:
> >
> > omap_ssi->get_loss(ssi->device.parent)
> >
> > This should be fixed up in the other sites too.
>
> in fact, we should stop expecting that service and drivers should
> manage their own context_loss detection
> Examples:
> MMC:
> http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=0a82e06e6183a252608df48cc4793b83e2d73dfd
>
> DSS: http://marc.info/?l=linux-omap&m=139272358619064&w=2
I'm currently initializing get_loss as NULL, so context loss
detection is currently disabled. I will try to find a way to
detect context loss once the n900 modem is in a working state
in the mainline kernel.
For now I will keep the get_loss() with the changes requested
by Mark.
-- Sebastian
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
^ permalink raw reply
* Re: Movement of testcases.dtsi
From: Grant Likely @ 2014-02-24 19:48 UTC (permalink / raw)
To: Ian Campbell, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1393237542.16570.26.camel-ommiHX4a84BXesXXhkcM7miJhflN2719@public.gmane.org>
On Mon, 24 Feb 2014 10:25:42 +0000, Ian Campbell <ijc-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> wrote:
> My device-tree-rebasing.git repo no longer builds, it fails with:
> src/arm/versatile-pb.dts:50:26: fatal error: testcases.dtsi: No such file or directory
>
> I suspect this is due to b5190516b282 "of: Move testcase FDT data into
> drivers/of". I think I need to add drivers/of/testcase-data to the list
> of paths to convert, probably extracting it to /testcase-data in the dt
> repo and teach the build system about the new path in the obvious way.
>
> Does that make sense?
Yup, that's the right thing to do... although I would like it to be a
short term solution. Ultimately I want the testcase data to be loaded at
runtime by the selftest module.
g.
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^ permalink raw reply
* [PATCH V6] gpio: New driver for LSI ZEVIO SoCs
From: Fabian Vogt @ 2014-02-24 19:54 UTC (permalink / raw)
To: linux-gpio
Cc: linux-kernel, linux-doc, devicetree, linus.walleij, grant.likely,
pawel.moll, rob, Fabian Vogt
This driver supports the GPIO controller found in LSI ZEVIO SoCs.
It has been successfully tested on a TI nspire CX calculator.
Signed-off-by: Fabian Vogt <fabian@ritter-vogt.de>
---
It took a while for me to make this patch.
School, other projects and some bugs which prevented testing
were time consuming.
This patch should resolve all issues, hopefully.
Changes to V5:
-Rewrote documentation
-Doesn't kfree devm_kzalloc'd memory
-Fixed multiline comments
-Got rid of unnecessary braces
-Converted two too complex macros to static inline functions
.../devicetree/bindings/gpio/gpio-zevio.txt | 17 ++
drivers/gpio/Kconfig | 6 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-zevio.c | 221 +++++++++++++++++++++
4 files changed, 245 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/gpio-zevio.txt
create mode 100644 drivers/gpio/gpio-zevio.c
diff --git a/Documentation/devicetree/bindings/gpio/gpio-zevio.txt b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
new file mode 100644
index 0000000..17bd9c8
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-zevio.txt
@@ -0,0 +1,17 @@
+Zevio GPIO controller
+
+Required properties:
+- compatible: Should be "lsi,zevio-gpio"
+- reg: Address and length of the register set for the device
+- #gpio-cells: Should be two. The first cell is the pin number and the
+ second cell is used to specify optional parameters (currently unused).
+- gpio-controller: Marks the device node as a GPIO controller.
+
+Example:
+ gpio: gpio@90000000 {
+ compatible = "lsi,zevio-gpio";
+ reg = <0x90000000 0x1000>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 903f24d..c69b9e3 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -145,6 +145,12 @@ config GPIO_EP93XX
depends on ARCH_EP93XX
select GPIO_GENERIC
+config GPIO_ZEVIO
+ bool "LSI ZEVIO SoC memory mapped GPIOs"
+ depends on OF
+ help
+ Say yes here to support the GPIO controller in LSI ZEVIO SoCs.
+
config GPIO_MM_LANTIQ
bool "Lantiq Memory mapped GPIOs"
depends on LANTIQ && SOC_XWAY
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5d50179..b845375 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -99,3 +99,4 @@ obj-$(CONFIG_GPIO_WM8350) += gpio-wm8350.o
obj-$(CONFIG_GPIO_WM8994) += gpio-wm8994.o
obj-$(CONFIG_GPIO_XILINX) += gpio-xilinx.o
obj-$(CONFIG_GPIO_XTENSA) += gpio-xtensa.o
+obj-$(CONFIG_GPIO_ZEVIO) += gpio-zevio.o
diff --git a/drivers/gpio/gpio-zevio.c b/drivers/gpio/gpio-zevio.c
new file mode 100644
index 0000000..9354c8e
--- /dev/null
+++ b/drivers/gpio/gpio-zevio.c
@@ -0,0 +1,221 @@
+/*
+ * GPIO controller in LSI ZEVIO SoCs.
+ *
+ * Author: Fabian Vogt <fabian@ritter-vogt.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/spinlock.h>
+#include <linux/errno.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+#include <linux/of_gpio.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+
+/*
+ * Memory layout:
+ * This chip has four gpio sections, each controls 8 GPIOs.
+ * Bit 0 in section 0 is GPIO 0, bit 2 in section 1 is GPIO 10.
+ * Disclaimer: Reverse engineered!
+ * For more information refer to:
+ * http://hackspire.unsads.com/wiki/index.php/Memory-mapped_I/O_ports#90000000_-_General_Purpose_I.2FO_.28GPIO.29
+ *
+ * 0x00-0x3F: Section 0
+ * +0x00: Masked interrupt status (read-only)
+ * +0x04: R: Interrupt status W: Reset interrupt status
+ * +0x08: R: Interrupt mask W: Mask interrupt
+ * +0x0C: W: Unmask interrupt (write-only)
+ * +0x10: Direction: I/O=1/0
+ * +0x14: Output
+ * +0x18: Input (read-only)
+ * +0x20: R: Level interrupt W: Set as level interrupt
+ * 0x40-0x7F: Section 1
+ * 0x80-0xBF: Section 2
+ * 0xC0-0xFF: Section 3
+ */
+
+#define ZEVIO_GPIO_SECTION_SIZE 0x40
+
+/* Offsets to various registers */
+#define ZEVIO_GPIO_INT_MASKED_STATUS 0x00
+#define ZEVIO_GPIO_INT_STATUS 0x04
+#define ZEVIO_GPIO_INT_UNMASK 0x08
+#define ZEVIO_GPIO_INT_MASK 0x0C
+#define ZEVIO_GPIO_DIRECTION 0x10
+#define ZEVIO_GPIO_OUTPUT 0x14
+#define ZEVIO_GPIO_INPUT 0x18
+#define ZEVIO_GPIO_INT_STICKY 0x20
+
+#define to_zevio_gpio(chip) container_of(to_of_mm_gpio_chip(chip), \
+ struct zevio_gpio, chip)
+
+/* Bit number of GPIO in its section */
+#define ZEVIO_GPIO_BIT(gpio) (gpio&7)
+
+struct zevio_gpio {
+ spinlock_t lock;
+ struct of_mm_gpio_chip chip;
+};
+
+static inline u32 zevio_gpio_port_get(struct zevio_gpio *c, unsigned pin,
+ unsigned port_offset)
+{
+ unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
+ return readl(IOMEM(c->chip.regs + section_offset + port_offset));
+}
+
+static inline void zevio_gpio_port_set(struct zevio_gpio *c, unsigned pin,
+ unsigned port_offset, u32 val)
+{
+ unsigned section_offset = ((pin >> 3) & 3)*ZEVIO_GPIO_SECTION_SIZE;
+ writel(val, IOMEM(c->chip.regs + section_offset + port_offset));
+}
+
+/* Functions for struct gpio_chip */
+static int zevio_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+
+ /* Only reading allowed, so no spinlock needed */
+ u32 val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_INPUT);
+
+ return (val >> ZEVIO_GPIO_BIT(pin)) & 0x1;
+}
+
+static void zevio_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+ u32 val;
+
+ spin_lock(&controller->lock);
+ val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
+ if (value)
+ val |= BIT(ZEVIO_GPIO_BIT(pin));
+ else
+ val &= ~BIT(ZEVIO_GPIO_BIT(pin));
+
+ zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
+ spin_unlock(&controller->lock);
+}
+
+static int zevio_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+ u32 val;
+
+ spin_lock(&controller->lock);
+
+ val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
+ val |= BIT(ZEVIO_GPIO_BIT(pin));
+ zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
+
+ spin_unlock(&controller->lock);
+
+ return 0;
+}
+
+static int zevio_gpio_direction_output(struct gpio_chip *chip,
+ unsigned pin, int value)
+{
+ struct zevio_gpio *controller = to_zevio_gpio(chip);
+ u32 val;
+
+ spin_lock(&controller->lock);
+ val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_OUTPUT);
+ if (value)
+ val |= BIT(ZEVIO_GPIO_BIT(pin));
+ else
+ val &= ~BIT(ZEVIO_GPIO_BIT(pin));
+
+ zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_OUTPUT, val);
+ val = zevio_gpio_port_get(controller, pin, ZEVIO_GPIO_DIRECTION);
+ val &= ~BIT(ZEVIO_GPIO_BIT(pin));
+ zevio_gpio_port_set(controller, pin, ZEVIO_GPIO_DIRECTION, val);
+
+ spin_unlock(&controller->lock);
+
+ return 0;
+}
+
+static int zevio_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+ /*
+ * TODO: Implement IRQs.
+ * Not implemented yet due to weird lockups
+ */
+
+ return -ENXIO;
+}
+
+static struct gpio_chip zevio_gpio_chip = {
+ .direction_input = zevio_gpio_direction_input,
+ .direction_output = zevio_gpio_direction_output,
+ .set = zevio_gpio_set,
+ .get = zevio_gpio_get,
+ .to_irq = zevio_gpio_to_irq,
+ .base = 0,
+ .owner = THIS_MODULE,
+ .ngpio = 32,
+ .of_gpio_n_cells = 2,
+};
+
+/* Initialization */
+static int zevio_gpio_probe(struct platform_device *pdev)
+{
+ struct zevio_gpio *controller;
+ int status, i;
+
+ controller = devm_kzalloc(&pdev->dev, sizeof(*controller), GFP_KERNEL);
+ if (!controller) {
+ dev_err(&pdev->dev, "not enough free memory\n");
+ return -ENOMEM;
+ }
+
+ /* Copy our reference */
+ controller->chip.gc = zevio_gpio_chip;
+ controller->chip.gc.dev = &pdev->dev;
+
+ status = of_mm_gpiochip_add(pdev->dev.of_node, &(controller->chip));
+ if (status) {
+ dev_err(&pdev->dev, "failed to add gpiochip: %d\n", status);
+ return status;
+ }
+
+ spin_lock_init(&controller->lock);
+
+ /* Disable interrupts, they only cause errors */
+ for (i = 0; i < controller->chip.gc.ngpio; i += 8)
+ zevio_gpio_port_set(controller, i, ZEVIO_GPIO_INT_MASK, 0xFF);
+
+ dev_dbg(controller->chip.gc.dev, "ZEVIO GPIO controller set up!\n");
+
+ return 0;
+}
+
+static struct of_device_id zevio_gpio_of_match[] = {
+ { .compatible = "lsi,zevio-gpio", },
+ { },
+};
+
+MODULE_DEVICE_TABLE(of, zevio_gpio_of_match);
+
+static struct platform_driver zevio_gpio_driver = {
+ .driver = {
+ .name = "gpio-zevio",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(zevio_gpio_of_match),
+ },
+ .probe = zevio_gpio_probe,
+};
+
+module_platform_driver(zevio_gpio_driver);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Fabian Vogt <fabian@ritter-vogt.de>");
+MODULE_DESCRIPTION("LSI ZEVIO SoC GPIO driver");
--
1.8.1.4
^ permalink raw reply related
* Re: [PATCH v3 0/11] Xilinx watchdog changes
From: Wim Van Sebroeck @ 2014-02-24 20:01 UTC (permalink / raw)
To: Michal Simek
Cc: linux-kernel, monstr, Guenter Roeck, devicetree, linux-watchdog,
linux-doc, Kumar Gala, Rob Landley, Ian Campbell, Rob Herring,
Pawel Moll, Mark Rutland, Grant Likely, linux-arm-kernel,
Arnd Bergmann
In-Reply-To: <cover.1392212059.git.michal.simek@xilinx.com>
Hi Michal,
> Hi,
>
> This series contains changes for Xilinx watchdog.
> The whole code series have been reviewed by Guenter
> and device-tree binding was acked by Arnd.
>
> I have also pushed this v3 to git repo
> for easier pulling here:
> git://git.monstr.eu/linux-2.6-microblaze.git watchdog
>
> Thanks,
> Michal
>
> Changes in v3:
> - Remove one if checking and use variable directly
>
> Changes in v2:
> - Fix enable_once logic
> - Change patch subject
> - New patch in this series
>
> Michal Simek (11):
> watchdog: xilinx: Convert driver to the watchdog framework
> watchdog: xilinx: Move control_status_reg to functions
> watchdog: xilinx: Simplify probe and remove functions
> watchdog: xilinx: Move no_timeout to probe function
> watchdog: xilinx: Allocate private structure per device
> watchdog: xilinx: Fix all printk messages
> watchdog: xilinx: Use of_property_read_u32
> watchdog: xilinx: Use correct comment indentation
> watchdog: xilinx: Add missing binding
> watchdog: xilinx: Enable this driver for Zynq
> watchdog: xilinx: Remove no_timeout variable
>
> .../devicetree/bindings/watchdog/of-xilinx-wdt.txt | 23 ++
> drivers/watchdog/Kconfig | 21 +-
> drivers/watchdog/of_xilinx_wdt.c | 389 ++++++---------------
> 3 files changed, 148 insertions(+), 285 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/watchdog/of-xilinx-wdt.txt
>
> --
> 1.8.2.3
>
This patch series has been added to linux-watchdog-next.
Kind regards,
Wim.
^ permalink raw reply
* Re: Movement of testcases.dtsi
From: Ian Campbell @ 2014-02-24 20:05 UTC (permalink / raw)
To: Grant Likely; +Cc: devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20140224194821.3D196C409F3-WNowdnHR2B42iJbIjFUEsiwD8/FfD2ys@public.gmane.org>
On Mon, 2014-02-24 at 19:48 +0000, Grant Likely wrote:
> On Mon, 24 Feb 2014 10:25:42 +0000, Ian Campbell <ijc-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org> wrote:
> > My device-tree-rebasing.git repo no longer builds, it fails with:
> > src/arm/versatile-pb.dts:50:26: fatal error: testcases.dtsi: No such file or directory
> >
> > I suspect this is due to b5190516b282 "of: Move testcase FDT data into
> > drivers/of". I think I need to add drivers/of/testcase-data to the list
> > of paths to convert, probably extracting it to /testcase-data in the dt
> > repo and teach the build system about the new path in the obvious way.
> >
> > Does that make sense?
>
> Yup, that's the right thing to do...
Thanks, I'll look into it.
> although I would like it to be a
> short term solution. Ultimately I want the testcase data to be loaded at
> runtime by the selftest module.
I suppose at this point linux.git will have a git rm done and my
conversion script will just import that as expected?
Ian.
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^ permalink raw reply
* Re: [PATCH v2] ARM: dts: Leave sdio1 as disabled on bcm28155-ap
From: Matt Porter @ 2014-02-24 20:11 UTC (permalink / raw)
To: Tim Kryger
Cc: Christian Daudt, Rob Herring, Pawel Moll, Mark Rutland,
Ian Campbell, Kumar Gala, Broadcom Kernel Feedback List,
Device Tree List, ARM Linux List, Linux Kernel Mailing List
In-Reply-To: <1391556460-24218-1-git-send-email-tim.kryger@linaro.org>
On Tue, Feb 04, 2014 at 03:27:40PM -0800, Tim Kryger wrote:
> The sdio1 interface pins are routed to an unpopulated daughter card
> connector on the bcm28155-ap board. Thus there is no need to mark
> this interface as enabled.
>
> Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
> Reviewed-by: Matt Porter <matt.porter@linaro.org>
Applied to mach-bcm armsoc/for-3.15/dt
-Matt
^ permalink raw reply
* Re: [PATCH 2/2] ARM: dts: duovero-parlor: Add HDMI output
From: Javier Martinez Canillas @ 2014-02-24 20:22 UTC (permalink / raw)
To: Russell King - ARM Linux, Tomi Valkeinen
Cc: Florian Vaussard, Benoît Cousson, Tony Lindgren,
devicetree@vger.kernel.org, linux-omap@vger.kernel.org,
Ash Charles, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20140224180336.GU27282@n2100.arm.linux.org.uk>
Hi Russell,
On Mon, Feb 24, 2014 at 3:03 PM, Russell King - ARM Linux
<linux@arm.linux.org.uk> wrote:
> On Mon, Feb 24, 2014 at 06:07:49PM +0100, Florian Vaussard wrote:
>> + hdmi0: connector@0 {
>> + compatible = "hdmi-connector";
>
> This looks way to generic a compatible string. Are you sure it's
> correct?
>
That compatible string is correct according to the latest series
posted by Tomi Valkeinen to add DT bindings for the OMAP Display
SubSystem (DSS) [0].
The property is added on this patch [1] and as far as I understood the
idea is that it could be a generic DT binding that can be used by
platform specific HDMI connectors like the omap dss HDMI connector
[2].
I'm adding Tomi to the cc list so he can a correct me if I'm wrong.
Thanks a lot and best regards,
Javier
[0]: http://www.spinics.net/lists/linux-omap/msg102522.html
[1]: http://www.spinics.net/lists/linux-omap/msg102559.html
[2]: http://www.spinics.net/lists/arm-kernel/msg302197.html
^ permalink raw reply
* Re: [PATCH 2/2] arm/xen: Don't use xen DMA ops when the device is protected by an IOMMU
From: Stefano Stabellini @ 2014-02-24 20:49 UTC (permalink / raw)
To: gregkh@linuxfoundation.org
Cc: Stefano Stabellini, Ian Campbell, Julien Grall, linux-kernel,
linux-arm-kernel, xen-devel, Rob Herring, Pawel Moll,
Mark Rutland, Ian Campbell, Kumar Gala, Rob Landley, Russell King,
devicetree
In-Reply-To: <20140224151636.GA13489@kroah.com>
On Mon, 24 Feb 2014, gregkh@linuxfoundation.org wrote:
> On Mon, Feb 24, 2014 at 12:19:11PM +0000, Stefano Stabellini wrote:
> > CC'ing Greg.
> >
> > On Thu, 20 Feb 2014, Ian Campbell wrote:
> > > On Thu, 2014-02-20 at 16:21 +0000, Julien Grall wrote:
> > > > Only Xen is able to know if a device can safely avoid to use xen-swiotlb.
> > > > This patch introduce a new property "protected-devices" for the hypervisor
> > > > node which list device which the IOMMU are been correctly programmed by Xen.
> > > >
> > > > During Linux boot, Xen specific code will create an hash table which
> > > > contains all these devices. The hash table will be used in need_xen_dma_ops
> > > > to check if the Xen DMA ops needs to be used for the current device.
> > >
> > > Is it out of the question to find a field within struct device itself to
> > > store this e.g. in struct device_dma_parameters perhaps and avoid the
> > > need for a hashtable lookup.
> > >
> > > device->iommu_group might be another option, if we can create our own
> > > group?
> >
> > I agree that a field in struct device would be ideal.
> > Greg, get_maintainer.pl points at you as main maintainer of device.h, do
> > you have an opinion on this?
>
> I need a whole lot more context here please. With a patch would be even
> better so that I know exactly what you are referring to...
The Xen hypervisor tells Linux which devices are protected by an SMMU,
preprogrammed by Xen, so that Linux can avoid the swiotlb and bounce
buffers for DMA requests involving them.
The information is present on device tree and parsed at boot time by
Linux.
Julien is proposing to store the list of "safe" devices on an hash table
in the Xen specific code (in arch/arm/xen/enlighten.c, see
http://marc.info/?l=linux-kernel&m=139291370526082&w=2).
Whenever Linux is about to do DMA, we would check in the hashtable to
figure out whether we need to go through the swiotlb or we can simply
use the native dma_ops.
Ian and I were thinking that it would be much easier and faster to have
a "xen_safe_device" parameter in struct device and just check for that.
It doesn't actually need to be in struct device, it could simply be a
flag in struct device_dma_parameters as Ian was suggesting.
Julien, could you please come up with a simple patch to demonstrate the
concept?
^ permalink raw reply
* Re: [PATCH] ARM: dts: keystone: add AEMIF/NAND device entry
From: Santosh Shilimkar @ 2014-02-24 21:10 UTC (permalink / raw)
To: Ivan Khoronzhuk
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-lFZ/pmaqli7XmaaqVzeoHQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
grygorii.strashko-l0cyMroinI0
In-Reply-To: <1393267976-15709-1-git-send-email-ivan.khoronzhuk-l0cyMroinI0@public.gmane.org>
On Monday 24 February 2014 01:52 PM, Ivan Khoronzhuk wrote:
> Add AEMIF/NAND device entry.
>
> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk-l0cyMroinI0@public.gmane.org>
> ---
>
Once the driver is in Greg's queue, I will pick this up and defconfig
patch.
>
> arch/arm/boot/dts/k2hk-evm.dts | 52 +++++++++++++++++++++++++++++++++++++++++
> arch/arm/boot/dts/keystone.dtsi | 13 +++++++++++
> 2 files changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/k2hk-evm.dts b/arch/arm/boot/dts/k2hk-evm.dts
> index 1d8ea6e..a08581b 100644
> --- a/arch/arm/boot/dts/k2hk-evm.dts
> +++ b/arch/arm/boot/dts/k2hk-evm.dts
> @@ -84,3 +84,55 @@
> &usb {
> status = "okay";
> };
> +
> +&aemif {
> + cs0 {
> + #address-cells = <2>;
> + #size-cells = <1>;
> + clock-ranges;
> + ranges;
> +
> + ti,cs-chipselect = <0>;
> + /* all timings in nanoseconds */
> + ti,cs-min-turnaround-ns = <12>;
> + ti,cs-read-hold-ns = <6>;
> + ti,cs-read-strobe-ns = <23>;
> + ti,cs-read-setup-ns = <9>;
> + ti,cs-write-hold-ns = <8>;
> + ti,cs-write-strobe-ns = <23>;
> + ti,cs-write-setup-ns = <8>;
> +
> + nand@0,0 {
> + compatible = "ti,keystone-nand","ti,davinci-nand";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0 0 0x4000000
> + 1 0 0x0000100>;
> +
> + ti,davinci-chipselect = <0>;
> + ti,davinci-mask-ale = <0x2000>;
> + ti,davinci-mask-cle = <0x4000>;
> + ti,davinci-mask-chipsel = <0>;
> + nand-ecc-mode = "hw";
> + ti,davinci-ecc-bits = <4>;
> + nand-on-flash-bbt;
> +
> + partition@0 {
> + label = "u-boot";
> + reg = <0x0 0x100000>;
> + read-only;
> + };
> +
> + partition@100000 {
> + label = "params";
> + reg = <0x100000 0x80000>;
> + read-only;
> + };
> +
> + partition@180000 {
> + label = "ubifs";
> + reg = <0x180000 0x7E80000>;
> + };
> + };
> + };
> +};
> diff --git a/arch/arm/boot/dts/keystone.dtsi b/arch/arm/boot/dts/keystone.dtsi
> index 4eceb46..af80cb2 100644
> --- a/arch/arm/boot/dts/keystone.dtsi
> +++ b/arch/arm/boot/dts/keystone.dtsi
> @@ -266,5 +266,18 @@
> ti,ngpio = <32>;
> ti,davinci-gpio-unbanked = <32>;
> };
> +
> + aemif: aemif@21000A00 {
> + compatible = "ti,keystone-aemif", "ti,davinci-aemif";
> + #address-cells = <2>;
> + #size-cells = <1>;
> + clocks = <&clkaemif>;
> + clock-names = "aemif";
> + clock-ranges;
> +
> + reg = <0x21000A00 0x00000100>;
> + ranges = <0 0 0x30000000 0x10000000
> + 1 0 0x21000A00 0x00000100>;
> + };
> };
> };
>
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^ permalink raw reply
* [Patch v7 0/2] Add Qualcomm BAM dmaengine driver
From: Andy Gross @ 2014-02-24 23:11 UTC (permalink / raw)
To: Vinod Koul, Dan Williams, dmaengine
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, devicetree,
Andy Gross
This patch set introduces the dmaengine driver for the Qualcomm Bus Access
Manager (BAM) DMA controller present on MSM 8x74 devices. A number of the
on-chip devices have their own BAM DMA controller and use it to move data
between system memory and peripherals or between two peripherals.
The initial version of this driver will only support slave DMA operations
between system memory and peripherals.
Changes from v6:
- Changed KConfig dependency from ARCH_MSM_DT to ARCH_QCOM.
- Incorporated comments on DT binding.
- Changed driver source file to accomodate DT changes.
Changes from v5:
- Separated copyright from BAM description
- Removed usage of slave dma direction
- Reworked slave config interface
- Removed max segment size restriction in slave_sg
- Added acked-by on DT patch
- Fixed nit comments
Changes from v4:
- Add devm_free_irq() to .remove to avoid race condition
- Free FIFO memory in .remove
Changes from v3:
- Remove unused bam_channel_dir.
- Remove incorrect write to BAM_IRQ_SRCS_EE (read only).
- Remove dma direction from DT binding and revise driver to use
direction from prep_slave_sg.
- Remove unnecessary channel reset from channel_init. This could affect
channels controlled from other execution environments.
- Change terminate_all to also take care of the current active
descriptor.
- Rework .remove function to correctly mask interrupts and clean up
resources and tasklets.
Changes from v2:
- Corrected Kconfig dependencies
- Moved execution environment ID to controller DT binding. The EE is
a global setting across all of the channels on the controller.
- Combined header into source file.
- Corrected copyright date.
- Moved channel hardware initialization to occur when channel is used
for the first time.
- Converted dma_alloc_coherent to dma_alloc_writecombine
- Removed unecessary reset of channel from the dma terminate_all
- Corrected usage of EE in irq handler and channel configuration
functions.
- Changed resource functions inside probe to use correct APIs.
- Removed dma filter function and modified dma_xlate to use
dma_get_slave_channel API
- Fixed various nit comments
Changes from v1:
- Converted driver to use virt-dma
- Reworked probe function per review comments
- tx_status function now computes and returns residuals
- Removed proprietary slave config. Removed associated include file.
- Renamed files to reflect vendor name instead of specific device
- Converted to use (readl|writel)_relaxed w/ appropriate barriers
- Removed unions in favor of standard types.
Andy Gross (2):
dmaengine: qcom_bam_dma: Add device tree binding
dmaengine: add Qualcomm BAM dma driver
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41 +
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/qcom_bam_dma.c | 1106 ++++++++++++++++++++
4 files changed, 1157 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
create mode 100644 drivers/dma/qcom_bam_dma.c
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply
* [Patch v7 1/2] dmaengine: qcom_bam_dma: Add device tree binding
From: Andy Gross @ 2014-02-24 23:11 UTC (permalink / raw)
To: Vinod Koul, Dan Williams, dmaengine-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andy Gross
In-Reply-To: <1393283500-18599-1-git-send-email-agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Add device tree binding support for the QCOM BAM DMA driver.
Acked-by: Kumar Gala <galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
Signed-off-by: Andy Gross <agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
---
.../devicetree/bindings/dma/qcom_bam_dma.txt | 41 ++++++++++++++++++++
1 file changed, 41 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
diff --git a/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
new file mode 100644
index 0000000..d75a9d7
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/qcom_bam_dma.txt
@@ -0,0 +1,41 @@
+QCOM BAM DMA controller
+
+Required properties:
+- compatible: must contain "qcom,bam-v1.4.0" for MSM8974
+- reg: Address range for DMA registers
+- interrupts: Should contain the one interrupt shared by all channels
+- #dma-cells: must be <1>, the cell in the dmas property of the client device
+ represents the channel number
+- clocks: required clock
+- clock-names: must contain "bam_clk" entry
+- qcom,ee : indicates the active Execution Environment identifier (0-7) used in
+ the secure world.
+
+Example:
+
+ uart-bam: dma@f9984000 = {
+ compatible = "qcom,bam-v1.4.0";
+ reg = <0xf9984000 0x15000>;
+ interrupts = <0 94 0>;
+ clocks = <&gcc GCC_BAM_DMA_AHB_CLK>;
+ clock-names = "bam_clk";
+ #dma-cells = <1>;
+ qcom,ee = <0>;
+ };
+
+DMA clients must use the format described in the dma.txt file, using a two cell
+specifier for each channel.
+
+Example:
+ serial@f991e000 {
+ compatible = "qcom,msm-uart";
+ reg = <0xf991e000 0x1000>
+ <0xf9944000 0x19000>;
+ interrupts = <0 108 0>;
+ clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+
+ dmas = <&uart-bam 0>, <&uart-bam 1>;
+ dma-names = "rx", "tx";
+ };
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
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^ permalink raw reply related
* [Patch v7 2/2] dmaengine: add Qualcomm BAM dma driver
From: Andy Gross @ 2014-02-24 23:11 UTC (permalink / raw)
To: Vinod Koul, Dan Williams, dmaengine
Cc: linux-kernel, linux-arm-kernel, linux-arm-msm, devicetree,
Andy Gross
In-Reply-To: <1393283500-18599-1-git-send-email-agross@codeaurora.org>
Add the DMA engine driver for the QCOM Bus Access Manager (BAM) DMA controller
found in the MSM 8x74 platforms.
Each BAM DMA device is associated with a specific on-chip peripheral. Each
channel provides a uni-directional data transfer engine that is capable of
transferring data between the peripheral and system memory (System mode), or
between two peripherals (BAM2BAM).
The initial release of this driver only supports slave transfers between
peripherals and system memory.
Signed-off-by: Andy Gross <agross@codeaurora.org>
---
drivers/dma/Kconfig | 9 +
drivers/dma/Makefile | 1 +
drivers/dma/qcom_bam_dma.c | 1106 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 1116 insertions(+)
create mode 100644 drivers/dma/qcom_bam_dma.c
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 605b016..f87cef9 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -401,4 +401,13 @@ config DMATEST
config DMA_ENGINE_RAID
bool
+config QCOM_BAM_DMA
+ tristate "QCOM BAM DMA support"
+ depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM)
+ select DMA_ENGINE
+ select DMA_VIRTUAL_CHANNELS
+ ---help---
+ Enable support for the QCOM BAM DMA controller. This controller
+ provides DMA capabilities for a variety of on-chip devices.
+
endif
diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile
index a029d0f4..907b915 100644
--- a/drivers/dma/Makefile
+++ b/drivers/dma/Makefile
@@ -44,3 +44,4 @@ obj-$(CONFIG_DMA_JZ4740) += dma-jz4740.o
obj-$(CONFIG_TI_CPPI41) += cppi41.o
obj-$(CONFIG_K3_DMA) += k3dma.o
obj-$(CONFIG_MOXART_DMA) += moxart-dma.o
+obj-$(CONFIG_QCOM_BAM_DMA) += qcom_bam_dma.o
diff --git a/drivers/dma/qcom_bam_dma.c b/drivers/dma/qcom_bam_dma.c
new file mode 100644
index 0000000..32333b3
--- /dev/null
+++ b/drivers/dma/qcom_bam_dma.c
@@ -0,0 +1,1106 @@
+/*
+ * Copyright (c) 2013-2014, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+/*
+ * QCOM BAM DMA engine driver
+ *
+ * QCOM BAM DMA blocks are distributed amongst a number of the on-chip
+ * peripherals on the MSM 8x74. The configuration of the channels are dependent
+ * on the way they are hard wired to that specific peripheral. The peripheral
+ * device tree entries specify the configuration of each channel.
+ *
+ * The DMA controller requires the use of external memory for storage of the
+ * hardware descriptors for each channel. The descriptor FIFO is accessed as a
+ * circular buffer and operations are managed according to the offset within the
+ * FIFO. After pipe/channel reset, all of the pipe registers and internal state
+ * are back to defaults.
+ *
+ * During DMA operations, we write descriptors to the FIFO, being careful to
+ * handle wrapping and then write the last FIFO offset to that channel's
+ * P_EVNT_REG register to kick off the transaction. The P_SW_OFSTS register
+ * indicates the current FIFO offset that is being processed, so there is some
+ * indication of where the hardware is currently working.
+ */
+
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/dma-mapping.h>
+#include <linux/scatterlist.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_dma.h>
+#include <linux/clk.h>
+#include <linux/dmaengine.h>
+
+#include "dmaengine.h"
+#include "virt-dma.h"
+
+struct bam_desc_hw {
+ u32 addr; /* Buffer physical address */
+ u16 size; /* Buffer size in bytes */
+ u16 flags;
+};
+
+#define DESC_FLAG_INT BIT(15)
+#define DESC_FLAG_EOT BIT(14)
+#define DESC_FLAG_EOB BIT(13)
+
+struct bam_async_desc {
+ struct virt_dma_desc vd;
+
+ u32 num_desc;
+ u32 xfer_len;
+ struct bam_desc_hw *curr_desc;
+
+ enum dma_transfer_direction dir;
+ size_t length;
+ struct bam_desc_hw desc[0];
+};
+
+#define BAM_CTRL 0x0000
+#define BAM_REVISION 0x0004
+#define BAM_SW_REVISION 0x0080
+#define BAM_NUM_PIPES 0x003C
+#define BAM_TIMER 0x0040
+#define BAM_TIMER_CTRL 0x0044
+#define BAM_DESC_CNT_TRSHLD 0x0008
+#define BAM_IRQ_SRCS 0x000C
+#define BAM_IRQ_SRCS_MSK 0x0010
+#define BAM_IRQ_SRCS_UNMASKED 0x0030
+#define BAM_IRQ_STTS 0x0014
+#define BAM_IRQ_CLR 0x0018
+#define BAM_IRQ_EN 0x001C
+#define BAM_CNFG_BITS 0x007C
+#define BAM_IRQ_SRCS_EE(pipe) (0x0800 + ((pipe) * 0x80))
+#define BAM_IRQ_SRCS_MSK_EE(pipe) (0x0804 + ((pipe) * 0x80))
+#define BAM_P_CTRL(pipe) (0x1000 + ((pipe) * 0x1000))
+#define BAM_P_RST(pipe) (0x1004 + ((pipe) * 0x1000))
+#define BAM_P_HALT(pipe) (0x1008 + ((pipe) * 0x1000))
+#define BAM_P_IRQ_STTS(pipe) (0x1010 + ((pipe) * 0x1000))
+#define BAM_P_IRQ_CLR(pipe) (0x1014 + ((pipe) * 0x1000))
+#define BAM_P_IRQ_EN(pipe) (0x1018 + ((pipe) * 0x1000))
+#define BAM_P_EVNT_DEST_ADDR(pipe) (0x182C + ((pipe) * 0x1000))
+#define BAM_P_EVNT_REG(pipe) (0x1818 + ((pipe) * 0x1000))
+#define BAM_P_SW_OFSTS(pipe) (0x1800 + ((pipe) * 0x1000))
+#define BAM_P_DATA_FIFO_ADDR(pipe) (0x1824 + ((pipe) * 0x1000))
+#define BAM_P_DESC_FIFO_ADDR(pipe) (0x181C + ((pipe) * 0x1000))
+#define BAM_P_EVNT_TRSHLD(pipe) (0x1828 + ((pipe) * 0x1000))
+#define BAM_P_FIFO_SIZES(pipe) (0x1820 + ((pipe) * 0x1000))
+
+/* BAM CTRL */
+#define BAM_SW_RST BIT(0)
+#define BAM_EN BIT(1)
+#define BAM_EN_ACCUM BIT(4)
+#define BAM_TESTBUS_SEL_SHIFT 5
+#define BAM_TESTBUS_SEL_MASK 0x3F
+#define BAM_DESC_CACHE_SEL_SHIFT 13
+#define BAM_DESC_CACHE_SEL_MASK 0x3
+#define BAM_CACHED_DESC_STORE BIT(15)
+#define IBC_DISABLE BIT(16)
+
+/* BAM REVISION */
+#define REVISION_SHIFT 0
+#define REVISION_MASK 0xFF
+#define NUM_EES_SHIFT 8
+#define NUM_EES_MASK 0xF
+#define CE_BUFFER_SIZE BIT(13)
+#define AXI_ACTIVE BIT(14)
+#define USE_VMIDMT BIT(15)
+#define SECURED BIT(16)
+#define BAM_HAS_NO_BYPASS BIT(17)
+#define HIGH_FREQUENCY_BAM BIT(18)
+#define INACTIV_TMRS_EXST BIT(19)
+#define NUM_INACTIV_TMRS BIT(20)
+#define DESC_CACHE_DEPTH_SHIFT 21
+#define DESC_CACHE_DEPTH_1 (0 << DESC_CACHE_DEPTH_SHIFT)
+#define DESC_CACHE_DEPTH_2 (1 << DESC_CACHE_DEPTH_SHIFT)
+#define DESC_CACHE_DEPTH_3 (2 << DESC_CACHE_DEPTH_SHIFT)
+#define DESC_CACHE_DEPTH_4 (3 << DESC_CACHE_DEPTH_SHIFT)
+#define CMD_DESC_EN BIT(23)
+#define INACTIV_TMR_BASE_SHIFT 24
+#define INACTIV_TMR_BASE_MASK 0xFF
+
+/* BAM NUM PIPES */
+#define BAM_NUM_PIPES_SHIFT 0
+#define BAM_NUM_PIPES_MASK 0xFF
+#define PERIPH_NON_PIPE_GRP_SHIFT 16
+#define PERIPH_NON_PIP_GRP_MASK 0xFF
+#define BAM_NON_PIPE_GRP_SHIFT 24
+#define BAM_NON_PIPE_GRP_MASK 0xFF
+
+/* BAM CNFG BITS */
+#define BAM_PIPE_CNFG BIT(2)
+#define BAM_FULL_PIPE BIT(11)
+#define BAM_NO_EXT_P_RST BIT(12)
+#define BAM_IBC_DISABLE BIT(13)
+#define BAM_SB_CLK_REQ BIT(14)
+#define BAM_PSM_CSW_REQ BIT(15)
+#define BAM_PSM_P_RES BIT(16)
+#define BAM_AU_P_RES BIT(17)
+#define BAM_SI_P_RES BIT(18)
+#define BAM_WB_P_RES BIT(19)
+#define BAM_WB_BLK_CSW BIT(20)
+#define BAM_WB_CSW_ACK_IDL BIT(21)
+#define BAM_WB_RETR_SVPNT BIT(22)
+#define BAM_WB_DSC_AVL_P_RST BIT(23)
+#define BAM_REG_P_EN BIT(24)
+#define BAM_PSM_P_HD_DATA BIT(25)
+#define BAM_AU_ACCUMED BIT(26)
+#define BAM_CMD_ENABLE BIT(27)
+
+#define BAM_CNFG_BITS_DEFAULT (BAM_PIPE_CNFG | \
+ BAM_NO_EXT_P_RST | \
+ BAM_IBC_DISABLE | \
+ BAM_SB_CLK_REQ | \
+ BAM_PSM_CSW_REQ | \
+ BAM_PSM_P_RES | \
+ BAM_AU_P_RES | \
+ BAM_SI_P_RES | \
+ BAM_WB_P_RES | \
+ BAM_WB_BLK_CSW | \
+ BAM_WB_CSW_ACK_IDL | \
+ BAM_WB_RETR_SVPNT | \
+ BAM_WB_DSC_AVL_P_RST | \
+ BAM_REG_P_EN | \
+ BAM_PSM_P_HD_DATA | \
+ BAM_AU_ACCUMED | \
+ BAM_CMD_ENABLE)
+
+/* PIPE CTRL */
+#define P_EN BIT(1)
+#define P_DIRECTION BIT(3)
+#define P_SYS_STRM BIT(4)
+#define P_SYS_MODE BIT(5)
+#define P_AUTO_EOB BIT(6)
+#define P_AUTO_EOB_SEL_SHIFT 7
+#define P_AUTO_EOB_SEL_512 (0 << P_AUTO_EOB_SEL_SHIFT)
+#define P_AUTO_EOB_SEL_256 (1 << P_AUTO_EOB_SEL_SHIFT)
+#define P_AUTO_EOB_SEL_128 (2 << P_AUTO_EOB_SEL_SHIFT)
+#define P_AUTO_EOB_SEL_64 (3 << P_AUTO_EOB_SEL_SHIFT)
+#define P_PREFETCH_LIMIT_SHIFT 9
+#define P_PREFETCH_LIMIT_32 (0 << P_PREFETCH_LIMIT_SHIFT)
+#define P_PREFETCH_LIMIT_16 (1 << P_PREFETCH_LIMIT_SHIFT)
+#define P_PREFETCH_LIMIT_4 (2 << P_PREFETCH_LIMIT_SHIFT)
+#define P_WRITE_NWD BIT(11)
+#define P_LOCK_GROUP_SHIFT 16
+#define P_LOCK_GROUP_MASK 0x1F
+
+/* BAM_DESC_CNT_TRSHLD */
+#define CNT_TRSHLD 0xffff
+#define DEFAULT_CNT_THRSHLD 0x4
+
+/* BAM_IRQ_SRCS */
+#define BAM_IRQ BIT(31)
+#define P_IRQ 0x7fffffff
+
+/* BAM_IRQ_SRCS_MSK */
+#define BAM_IRQ_MSK BAM_IRQ
+#define P_IRQ_MSK P_IRQ
+
+/* BAM_IRQ_STTS */
+#define BAM_TIMER_IRQ BIT(4)
+#define BAM_EMPTY_IRQ BIT(3)
+#define BAM_ERROR_IRQ BIT(2)
+#define BAM_HRESP_ERR_IRQ BIT(1)
+
+/* BAM_IRQ_CLR */
+#define BAM_TIMER_CLR BIT(4)
+#define BAM_EMPTY_CLR BIT(3)
+#define BAM_ERROR_CLR BIT(2)
+#define BAM_HRESP_ERR_CLR BIT(1)
+
+/* BAM_IRQ_EN */
+#define BAM_TIMER_EN BIT(4)
+#define BAM_EMPTY_EN BIT(3)
+#define BAM_ERROR_EN BIT(2)
+#define BAM_HRESP_ERR_EN BIT(1)
+
+/* BAM_P_IRQ_EN */
+#define P_PRCSD_DESC_EN BIT(0)
+#define P_TIMER_EN BIT(1)
+#define P_WAKE_EN BIT(2)
+#define P_OUT_OF_DESC_EN BIT(3)
+#define P_ERR_EN BIT(4)
+#define P_TRNSFR_END_EN BIT(5)
+#define P_DEFAULT_IRQS_EN (P_PRCSD_DESC_EN | P_ERR_EN | P_TRNSFR_END_EN)
+
+/* BAM_P_SW_OFSTS */
+#define P_SW_OFSTS_MASK 0xffff
+
+#define BAM_DESC_FIFO_SIZE SZ_32K
+#define MAX_DESCRIPTORS (BAM_DESC_FIFO_SIZE / sizeof(struct bam_desc_hw) - 1)
+#define BAM_MAX_DATA_SIZE (SZ_32K - 8)
+
+struct bam_chan {
+ struct virt_dma_chan vc;
+
+ struct bam_device *bdev;
+
+ /* configuration from device tree */
+ u32 id;
+ u32 ee;
+
+ struct bam_async_desc *curr_txd; /* current running dma */
+
+ /* runtime configuration */
+ struct dma_slave_config slave;
+
+ /* fifo storage */
+ struct bam_desc_hw *fifo_virt;
+ dma_addr_t fifo_phys;
+
+ /* fifo markers */
+ unsigned short head; /* start of active descriptor entries */
+ unsigned short tail; /* end of active descriptor entries */
+
+ unsigned int initialized; /* is the channel hw initialized? */
+ unsigned int paused; /* is the channel paused? */
+ unsigned int reconfigure; /* new slave config? */
+
+ struct list_head node;
+};
+
+static inline struct bam_chan *to_bam_chan(struct dma_chan *common)
+{
+ return container_of(common, struct bam_chan, vc.chan);
+}
+
+struct bam_device {
+ void __iomem *regs;
+ struct device *dev;
+ struct dma_device common;
+ struct device_dma_parameters dma_parms;
+ struct bam_chan *channels;
+ u32 num_channels;
+
+ /* execution environment ID, from DT */
+ u32 ee;
+
+ struct clk *bamclk;
+ int irq;
+
+ /* dma start transaction tasklet */
+ struct tasklet_struct task;
+};
+
+/**
+ * bam_reset_channel - Reset individual BAM DMA channel
+ * @bchan: bam channel
+ *
+ * This function resets a specific BAM channel
+ */
+static void bam_reset_channel(struct bam_chan *bchan)
+{
+ struct bam_device *bdev = bchan->bdev;
+
+ lockdep_assert_held(&bchan->vc.lock);
+
+ /* reset channel */
+ writel_relaxed(1, bdev->regs + BAM_P_RST(bchan->id));
+ writel_relaxed(0, bdev->regs + BAM_P_RST(bchan->id));
+
+ /* don't allow cpu to reorder BAM register accesses done after this */
+ wmb();
+
+ /* make sure hw is initialized when channel is used the first time */
+ bchan->initialized = 0;
+}
+
+/**
+ * bam_chan_init_hw - Initialize channel hardware
+ * @bchan: bam channel
+ *
+ * This function resets and initializes the BAM channel
+ */
+static void bam_chan_init_hw(struct bam_chan *bchan,
+ enum dma_transfer_direction dir)
+{
+ struct bam_device *bdev = bchan->bdev;
+ u32 val;
+
+ /* Reset the channel to clear internal state of the FIFO */
+ bam_reset_channel(bchan);
+
+ /*
+ * write out 8 byte aligned address. We have enough space for this
+ * because we allocated 1 more descriptor (8 bytes) than we can use
+ */
+ writel_relaxed(ALIGN(bchan->fifo_phys, sizeof(struct bam_desc_hw)),
+ bdev->regs + BAM_P_DESC_FIFO_ADDR(bchan->id));
+ writel_relaxed(BAM_DESC_FIFO_SIZE, bdev->regs +
+ BAM_P_FIFO_SIZES(bchan->id));
+
+ /* enable the per pipe interrupts, enable EOT, ERR, and INT irqs */
+ writel_relaxed(P_DEFAULT_IRQS_EN, bdev->regs + BAM_P_IRQ_EN(bchan->id));
+
+ /* unmask the specific pipe and EE combo */
+ val = readl_relaxed(bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
+ val |= BIT(bchan->id);
+ writel_relaxed(val, bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
+
+ /* don't allow cpu to reorder the channel enable done below */
+ wmb();
+
+ /* set fixed direction and mode, then enable channel */
+ val = P_EN | P_SYS_MODE;
+ if (dir == DMA_DEV_TO_MEM)
+ val |= P_DIRECTION;
+
+ writel_relaxed(val, bdev->regs + BAM_P_CTRL(bchan->id));
+
+ bchan->initialized = 1;
+
+ /* init FIFO pointers */
+ bchan->head = 0;
+ bchan->tail = 0;
+}
+
+/**
+ * bam_alloc_chan - Allocate channel resources for DMA channel.
+ * @chan: specified channel
+ *
+ * This function allocates the FIFO descriptor memory
+ */
+static int bam_alloc_chan(struct dma_chan *chan)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ struct bam_device *bdev = bchan->bdev;
+
+ /* allocate FIFO descriptor space, but only if necessary */
+ if (!bchan->fifo_virt) {
+ bchan->fifo_virt = dma_alloc_writecombine(bdev->dev,
+ BAM_DESC_FIFO_SIZE, &bchan->fifo_phys,
+ GFP_KERNEL);
+
+ if (!bchan->fifo_virt) {
+ dev_err(bdev->dev, "Failed to allocate desc fifo\n");
+ return -ENOMEM;
+ }
+ }
+
+ return 0;
+}
+
+/**
+ * bam_free_chan - Frees dma resources associated with specific channel
+ * @chan: specified channel
+ *
+ * Free the allocated fifo descriptor memory and channel resources
+ *
+ */
+static void bam_free_chan(struct dma_chan *chan)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ struct bam_device *bdev = bchan->bdev;
+ u32 val;
+ unsigned long flags;
+
+ vchan_free_chan_resources(to_virt_chan(chan));
+
+ if (bchan->curr_txd) {
+ dev_err(bchan->bdev->dev, "Cannot free busy channel\n");
+ return;
+ }
+
+ spin_lock_irqsave(&bchan->vc.lock, flags);
+ bam_reset_channel(bchan);
+ spin_unlock_irqrestore(&bchan->vc.lock, flags);
+
+ dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt,
+ bchan->fifo_phys);
+ bchan->fifo_virt = NULL;
+
+ /* mask irq for pipe/channel */
+ val = readl_relaxed(bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
+ val &= ~BIT(bchan->id);
+ writel_relaxed(val, bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
+
+ /* disable irq */
+ writel_relaxed(0, bdev->regs + BAM_P_IRQ_EN(bchan->id));
+}
+
+/**
+ * bam_slave_config - set slave configuration for channel
+ * @chan: dma channel
+ * @cfg: slave configuration
+ *
+ * Sets slave configuration for channel
+ *
+ */
+static void bam_slave_config(struct bam_chan *bchan,
+ struct dma_slave_config *cfg)
+{
+ memcpy(&bchan->slave, cfg, sizeof(*cfg));
+ bchan->reconfigure = 1;
+}
+
+/**
+ * bam_prep_slave_sg - Prep slave sg transaction
+ *
+ * @chan: dma channel
+ * @sgl: scatter gather list
+ * @sg_len: length of sg
+ * @direction: DMA transfer direction
+ * @flags: DMA flags
+ * @context: transfer context (unused)
+ */
+static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan,
+ struct scatterlist *sgl, unsigned int sg_len,
+ enum dma_transfer_direction direction, unsigned long flags,
+ void *context)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ struct bam_device *bdev = bchan->bdev;
+ struct bam_async_desc *async_desc;
+ struct scatterlist *sg;
+ u32 i;
+ struct bam_desc_hw *desc;
+ unsigned int num_alloc = 0;
+
+
+ if (!is_slave_direction(direction)) {
+ dev_err(bdev->dev, "invalid dma direction\n");
+ return NULL;
+ }
+
+ /* calculate number of required entries */
+ for_each_sg(sgl, sg, sg_len, i)
+ num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_MAX_DATA_SIZE);
+
+ /* allocate enough room to accomodate the number of entries */
+ async_desc = kzalloc(sizeof(*async_desc) +
+ (num_alloc * sizeof(struct bam_desc_hw)), GFP_NOWAIT);
+
+ if (!async_desc)
+ goto err_out;
+
+ async_desc->num_desc = num_alloc;
+ async_desc->curr_desc = async_desc->desc;
+ async_desc->dir = direction;
+
+ /* fill in temporary descriptors */
+ desc = async_desc->desc;
+ for_each_sg(sgl, sg, sg_len, i) {
+ unsigned int remainder = sg_dma_len(sg);
+ unsigned int curr_offset = 0;
+
+ do {
+ desc->addr = sg_dma_address(sg) + curr_offset;
+
+ if (remainder > BAM_MAX_DATA_SIZE) {
+ desc->size = BAM_MAX_DATA_SIZE;
+ remainder -= BAM_MAX_DATA_SIZE;
+ curr_offset += BAM_MAX_DATA_SIZE;
+ } else {
+ desc->size = remainder;
+ remainder = 0;
+ }
+
+ async_desc->length += desc->size;
+ desc++;
+ } while (remainder > 0);
+ }
+
+ return vchan_tx_prep(&bchan->vc, &async_desc->vd, flags);
+
+err_out:
+ kfree(async_desc);
+ return NULL;
+}
+
+/**
+ * bam_dma_terminate_all - terminate all transactions on a channel
+ * @bchan: bam dma channel
+ *
+ * Dequeues and frees all transactions
+ * No callbacks are done
+ *
+ */
+static void bam_dma_terminate_all(struct bam_chan *bchan)
+{
+ unsigned long flag;
+ LIST_HEAD(head);
+
+ /* remove all transactions, including active transaction */
+ spin_lock_irqsave(&bchan->vc.lock, flag);
+ if (bchan->curr_txd) {
+ list_add(&bchan->curr_txd->vd.node, &bchan->vc.desc_issued);
+ bchan->curr_txd = NULL;
+ }
+
+ vchan_get_all_descriptors(&bchan->vc, &head);
+ spin_unlock_irqrestore(&bchan->vc.lock, flag);
+
+ vchan_dma_desc_free_list(&bchan->vc, &head);
+}
+
+/**
+ * bam_control - DMA device control
+ * @chan: dma channel
+ * @cmd: control cmd
+ * @arg: cmd argument
+ *
+ * Perform DMA control command
+ *
+ */
+static int bam_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
+ unsigned long arg)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ struct bam_device *bdev = bchan->bdev;
+ int ret = 0;
+ unsigned long flag;
+
+ switch (cmd) {
+ case DMA_PAUSE:
+ spin_lock_irqsave(&bchan->vc.lock, flag);
+ writel_relaxed(1, bdev->regs + BAM_P_HALT(bchan->id));
+ bchan->paused = 1;
+ spin_unlock_irqrestore(&bchan->vc.lock, flag);
+ break;
+
+ case DMA_RESUME:
+ spin_lock_irqsave(&bchan->vc.lock, flag);
+ writel_relaxed(0, bdev->regs + BAM_P_HALT(bchan->id));
+ bchan->paused = 0;
+ spin_unlock_irqrestore(&bchan->vc.lock, flag);
+ break;
+
+ case DMA_TERMINATE_ALL:
+ bam_dma_terminate_all(bchan);
+ break;
+
+ case DMA_SLAVE_CONFIG:
+ spin_lock_irqsave(&bchan->vc.lock, flag);
+ bam_slave_config(bchan, (struct dma_slave_config *)arg);
+ spin_unlock_irqrestore(&bchan->vc.lock, flag);
+ break;
+
+ default:
+ ret = -ENXIO;
+ break;
+ }
+
+ return ret;
+}
+
+/**
+ * process_channel_irqs - processes the channel interrupts
+ * @bdev: bam controller
+ *
+ * This function processes the channel interrupts
+ *
+ */
+static u32 process_channel_irqs(struct bam_device *bdev)
+{
+ u32 i, srcs, pipe_stts;
+ unsigned long flags;
+ struct bam_async_desc *async_desc;
+
+ srcs = readl_relaxed(bdev->regs + BAM_IRQ_SRCS_EE(bdev->ee));
+
+ /* return early if no pipe/channel interrupts are present */
+ if (!(srcs & P_IRQ))
+ return srcs;
+
+ for (i = 0; i < bdev->num_channels; i++) {
+ struct bam_chan *bchan = &bdev->channels[i];
+ if (srcs & BIT(i)) {
+ /* clear pipe irq */
+ pipe_stts = readl_relaxed(bdev->regs +
+ BAM_P_IRQ_STTS(i));
+
+ writel_relaxed(pipe_stts, bdev->regs +
+ BAM_P_IRQ_CLR(i));
+
+ spin_lock_irqsave(&bchan->vc.lock, flags);
+ async_desc = bchan->curr_txd;
+
+ if (async_desc) {
+ async_desc->num_desc -= async_desc->xfer_len;
+ async_desc->curr_desc += async_desc->xfer_len;
+ bchan->curr_txd = NULL;
+
+ /* manage FIFO */
+ bchan->head += async_desc->xfer_len;
+ bchan->head %= MAX_DESCRIPTORS;
+
+ /*
+ * if complete, process cookie. Otherwise
+ * push back to front of desc_issued so that
+ * it gets restarted by the tasklet
+ */
+ if (!async_desc->num_desc)
+ vchan_cookie_complete(&async_desc->vd);
+ else
+ list_add(&async_desc->vd.node,
+ &bchan->vc.desc_issued);
+ }
+
+ spin_unlock_irqrestore(&bchan->vc.lock, flags);
+ }
+ }
+
+ return srcs;
+}
+
+/**
+ * bam_dma_irq - irq handler for bam controller
+ * @irq: IRQ of interrupt
+ * @data: callback data
+ *
+ * IRQ handler for the bam controller
+ */
+static irqreturn_t bam_dma_irq(int irq, void *data)
+{
+ struct bam_device *bdev = data;
+ u32 clr_mask = 0, srcs = 0;
+
+ srcs |= process_channel_irqs(bdev);
+
+ /* kick off tasklet to start next dma transfer */
+ if (srcs & P_IRQ)
+ tasklet_schedule(&bdev->task);
+
+ if (srcs & BAM_IRQ)
+ clr_mask = readl_relaxed(bdev->regs + BAM_IRQ_STTS);
+
+ /* don't allow reorder of the various accesses to the BAM registers */
+ mb();
+
+ writel_relaxed(clr_mask, bdev->regs + BAM_IRQ_CLR);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * bam_tx_status - returns status of transaction
+ * @chan: dma channel
+ * @cookie: transaction cookie
+ * @txstate: DMA transaction state
+ *
+ * Return status of dma transaction
+ */
+static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
+ struct dma_tx_state *txstate)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ struct virt_dma_desc *vd;
+ int ret;
+ size_t residue = 0;
+ unsigned int i;
+ unsigned long flags;
+
+ ret = dma_cookie_status(chan, cookie, txstate);
+ if (ret == DMA_COMPLETE)
+ return ret;
+
+ if (!txstate)
+ return bchan->paused ? DMA_PAUSED : ret;
+
+ spin_lock_irqsave(&bchan->vc.lock, flags);
+ vd = vchan_find_desc(&bchan->vc, cookie);
+ if (vd)
+ residue = container_of(vd, struct bam_async_desc, vd)->length;
+ else if (bchan->curr_txd && bchan->curr_txd->vd.tx.cookie == cookie)
+ for (i = 0; i < bchan->curr_txd->num_desc; i++)
+ residue += bchan->curr_txd->curr_desc[i].size;
+
+ spin_unlock_irqrestore(&bchan->vc.lock, flags);
+
+ dma_set_residue(txstate, residue);
+
+ if (ret == DMA_IN_PROGRESS && bchan->paused)
+ ret = DMA_PAUSED;
+
+ return ret;
+}
+
+/**
+ * bam_apply_new_config
+ * @bchan: bam dma channel
+ * @dir: DMA direction
+ */
+static void bam_apply_new_config(struct bam_chan *bchan,
+ enum dma_transfer_direction dir)
+{
+ struct bam_device *bdev = bchan->bdev;
+ u32 maxburst;
+
+ if (dir == DMA_DEV_TO_MEM)
+ maxburst = bchan->slave.src_maxburst;
+ else
+ maxburst = bchan->slave.dst_maxburst;
+
+ writel_relaxed(maxburst, bdev->regs + BAM_DESC_CNT_TRSHLD);
+
+ bchan->reconfigure = 0;
+}
+
+/**
+ * bam_start_dma - start next transaction
+ * @bchan - bam dma channel
+ */
+static void bam_start_dma(struct bam_chan *bchan)
+{
+ struct virt_dma_desc *vd = vchan_next_desc(&bchan->vc);
+ struct bam_device *bdev = bchan->bdev;
+ struct bam_async_desc *async_desc;
+ struct bam_desc_hw *desc;
+ struct bam_desc_hw *fifo = PTR_ALIGN(bchan->fifo_virt,
+ sizeof(struct bam_desc_hw));
+
+ lockdep_assert_held(&bchan->vc.lock);
+
+ if (!vd)
+ return;
+
+ list_del(&vd->node);
+
+ async_desc = container_of(vd, struct bam_async_desc, vd);
+ bchan->curr_txd = async_desc;
+
+ /* on first use, initialize the channel hardware */
+ if (!bchan->initialized)
+ bam_chan_init_hw(bchan, async_desc->dir);
+
+ /* apply new slave config changes, if necessary */
+ if (bchan->reconfigure)
+ bam_apply_new_config(bchan, async_desc->dir);
+
+ desc = bchan->curr_txd->curr_desc;
+
+ if (async_desc->num_desc > MAX_DESCRIPTORS)
+ async_desc->xfer_len = MAX_DESCRIPTORS;
+ else
+ async_desc->xfer_len = async_desc->num_desc;
+
+ /* set INT on last descriptor */
+ desc[async_desc->xfer_len - 1].flags |= DESC_FLAG_INT;
+
+ if (bchan->tail + async_desc->xfer_len > MAX_DESCRIPTORS) {
+ u32 partial = MAX_DESCRIPTORS - bchan->tail;
+
+ memcpy(&fifo[bchan->tail], desc,
+ partial * sizeof(struct bam_desc_hw));
+ memcpy(fifo, &desc[partial], (async_desc->xfer_len - partial) *
+ sizeof(struct bam_desc_hw));
+ } else {
+ memcpy(&fifo[bchan->tail], desc,
+ async_desc->xfer_len * sizeof(struct bam_desc_hw));
+ }
+
+ bchan->tail += async_desc->xfer_len;
+ bchan->tail %= MAX_DESCRIPTORS;
+
+ /* ensure descriptor writes and dma start not reordered */
+ wmb();
+ writel_relaxed(bchan->tail * sizeof(struct bam_desc_hw),
+ bdev->regs + BAM_P_EVNT_REG(bchan->id));
+}
+
+/**
+ * dma_tasklet - DMA IRQ tasklet
+ * @data: tasklet argument (bam controller structure)
+ *
+ * Sets up next DMA operation and then processes all completed transactions
+ */
+static void dma_tasklet(unsigned long data)
+{
+ struct bam_device *bdev = (struct bam_device *)data;
+ struct bam_chan *bchan;
+ unsigned long flags;
+ unsigned int i;
+
+ /* go through the channels and kick off transactions */
+ for (i = 0; i < bdev->num_channels; i++) {
+ bchan = &bdev->channels[i];
+ spin_lock_irqsave(&bchan->vc.lock, flags);
+
+ if (!list_empty(&bchan->vc.desc_issued) && !bchan->curr_txd)
+ bam_start_dma(bchan);
+ spin_unlock_irqrestore(&bchan->vc.lock, flags);
+ }
+}
+
+/**
+ * bam_issue_pending - starts pending transactions
+ * @chan: dma channel
+ *
+ * Calls tasklet directly which in turn starts any pending transactions
+ */
+static void bam_issue_pending(struct dma_chan *chan)
+{
+ struct bam_chan *bchan = to_bam_chan(chan);
+ unsigned long flags;
+
+ spin_lock_irqsave(&bchan->vc.lock, flags);
+
+ /* if work pending and idle, start a transaction */
+ if (vchan_issue_pending(&bchan->vc) && !bchan->curr_txd)
+ bam_start_dma(bchan);
+
+ spin_unlock_irqrestore(&bchan->vc.lock, flags);
+}
+
+/**
+ * bam_dma_free_desc - free descriptor memory
+ * @vd: virtual descriptor
+ *
+ */
+static void bam_dma_free_desc(struct virt_dma_desc *vd)
+{
+ struct bam_async_desc *async_desc = container_of(vd,
+ struct bam_async_desc, vd);
+
+ kfree(async_desc);
+}
+
+static struct dma_chan *bam_dma_xlate(struct of_phandle_args *dma_spec,
+ struct of_dma *of)
+{
+ struct bam_device *bdev = container_of(of->of_dma_data,
+ struct bam_device, common);
+ unsigned int request;
+
+ if (dma_spec->args_count != 1)
+ return NULL;
+
+ request = dma_spec->args[0];
+ if (request >= bdev->num_channels)
+ return NULL;
+
+ return dma_get_slave_channel(&(bdev->channels[request].vc.chan));
+}
+
+/**
+ * bam_init
+ * @bdev: bam device
+ *
+ * Initialization helper for global bam registers
+ */
+static int bam_init(struct bam_device *bdev)
+{
+ u32 val;
+
+ /* read revision and configuration information */
+ val = readl_relaxed(bdev->regs + BAM_REVISION) & NUM_EES_MASK;
+
+ /* check that configured EE is within range */
+ if (bdev->ee >= val)
+ return -EINVAL;
+
+ val = readl_relaxed(bdev->regs + BAM_NUM_PIPES);
+ bdev->num_channels = val & BAM_NUM_PIPES_MASK;
+
+ /* s/w reset bam */
+ /* after reset all pipes are disabled and idle */
+ val = readl_relaxed(bdev->regs + BAM_CTRL);
+ val |= BAM_SW_RST;
+ writel_relaxed(val, bdev->regs + BAM_CTRL);
+ val &= ~BAM_SW_RST;
+ writel_relaxed(val, bdev->regs + BAM_CTRL);
+
+ /* make sure previous stores are visible before enabling BAM */
+ wmb();
+
+ /* enable bam */
+ val |= BAM_EN;
+ writel_relaxed(val, bdev->regs + BAM_CTRL);
+
+ /* set descriptor threshhold, start with 4 bytes */
+ writel_relaxed(DEFAULT_CNT_THRSHLD, bdev->regs + BAM_DESC_CNT_TRSHLD);
+
+ /* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
+ writel_relaxed(BAM_CNFG_BITS_DEFAULT, bdev->regs + BAM_CNFG_BITS);
+
+ /* enable irqs for errors */
+ writel_relaxed(BAM_ERROR_EN | BAM_HRESP_ERR_EN,
+ bdev->regs + BAM_IRQ_EN);
+
+ return 0;
+}
+
+static void bam_channel_init(struct bam_device *bdev, struct bam_chan *bchan,
+ u32 index)
+{
+ bchan->id = index;
+ bchan->bdev = bdev;
+
+ vchan_init(&bchan->vc, &bdev->common);
+ bchan->vc.desc_free = bam_dma_free_desc;
+}
+
+static int bam_dma_probe(struct platform_device *pdev)
+{
+ struct bam_device *bdev;
+ struct resource *iores;
+ int ret, i;
+
+ bdev = devm_kzalloc(&pdev->dev, sizeof(*bdev), GFP_KERNEL);
+ if (!bdev)
+ return -ENOMEM;
+
+ bdev->dev = &pdev->dev;
+
+ iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ bdev->regs = devm_ioremap_resource(&pdev->dev, iores);
+ if (IS_ERR(bdev->regs))
+ return PTR_ERR(bdev->regs);
+
+ bdev->irq = platform_get_irq(pdev, 0);
+ if (bdev->irq < 0)
+ return bdev->irq;
+
+ bdev->bamclk = devm_clk_get(bdev->dev, "bam_clk");
+ if (IS_ERR(bdev->bamclk))
+ return PTR_ERR(bdev->bamclk);
+
+ ret = clk_prepare_enable(bdev->bamclk);
+ if (ret) {
+ dev_err(bdev->dev, "failed to prepare/enable clock\n");
+ return ret;
+ }
+
+ ret = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &bdev->ee);
+ if (ret) {
+ dev_err(bdev->dev, "Execution environment unspecified\n");
+ return ret;
+ }
+
+ ret = bam_init(bdev);
+ if (ret)
+ return ret;
+
+ tasklet_init(&bdev->task, dma_tasklet, (unsigned long)bdev);
+
+ bdev->channels = devm_kcalloc(bdev->dev, bdev->num_channels,
+ sizeof(*bdev->channels), GFP_KERNEL);
+
+ if (!bdev->channels) {
+ ret = -ENOMEM;
+ goto err_disable_clk;
+ }
+
+ /* allocate and initialize channels */
+ INIT_LIST_HEAD(&bdev->common.channels);
+
+ for (i = 0; i < bdev->num_channels; i++)
+ bam_channel_init(bdev, &bdev->channels[i], i);
+
+ ret = devm_request_irq(bdev->dev, bdev->irq, bam_dma_irq,
+ IRQF_TRIGGER_HIGH, "bam_dma", bdev);
+ if (ret)
+ goto err_disable_clk;
+
+ /* set max dma segment size */
+ bdev->common.dev = bdev->dev;
+ bdev->common.dev->dma_parms = &bdev->dma_parms;
+ ret = dma_set_max_seg_size(bdev->common.dev, BAM_MAX_DATA_SIZE);
+ if (ret) {
+ dev_err(bdev->dev, "cannot set maximum segment size\n");
+ goto err_disable_clk;
+ }
+
+ platform_set_drvdata(pdev, bdev);
+
+ /* set capabilities */
+ dma_cap_zero(bdev->common.cap_mask);
+ dma_cap_set(DMA_SLAVE, bdev->common.cap_mask);
+
+ /* initialize dmaengine apis */
+ bdev->common.device_alloc_chan_resources = bam_alloc_chan;
+ bdev->common.device_free_chan_resources = bam_free_chan;
+ bdev->common.device_prep_slave_sg = bam_prep_slave_sg;
+ bdev->common.device_control = bam_control;
+ bdev->common.device_issue_pending = bam_issue_pending;
+ bdev->common.device_tx_status = bam_tx_status;
+ bdev->common.dev = bdev->dev;
+
+ ret = dma_async_device_register(&bdev->common);
+ if (ret) {
+ dev_err(bdev->dev, "failed to register dma async device\n");
+ goto err_disable_clk;
+ }
+
+ ret = of_dma_controller_register(pdev->dev.of_node, bam_dma_xlate,
+ &bdev->common);
+ if (ret)
+ goto err_unregister_dma;
+
+ return 0;
+
+err_unregister_dma:
+ dma_async_device_unregister(&bdev->common);
+err_disable_clk:
+ clk_disable_unprepare(bdev->bamclk);
+ return ret;
+}
+
+static int bam_dma_remove(struct platform_device *pdev)
+{
+ struct bam_device *bdev = platform_get_drvdata(pdev);
+ u32 i;
+
+ of_dma_controller_free(pdev->dev.of_node);
+ dma_async_device_unregister(&bdev->common);
+
+ /* mask all interrupts for this execution environment */
+ writel_relaxed(0, bdev->regs + BAM_IRQ_SRCS_MSK_EE(bdev->ee));
+
+ devm_free_irq(bdev->dev, bdev->irq, bdev);
+
+ for (i = 0; i < bdev->num_channels; i++) {
+ bam_dma_terminate_all(&bdev->channels[i]);
+ tasklet_kill(&bdev->channels[i].vc.task);
+
+ dma_free_writecombine(bdev->dev, BAM_DESC_FIFO_SIZE,
+ bdev->channels[i].fifo_virt,
+ bdev->channels[i].fifo_phys);
+ }
+
+ tasklet_kill(&bdev->task);
+
+ clk_disable_unprepare(bdev->bamclk);
+
+ return 0;
+}
+
+static const struct of_device_id bam_of_match[] = {
+ { .compatible = "qcom,bam-v1.4.0", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, bam_of_match);
+
+static struct platform_driver bam_dma_driver = {
+ .probe = bam_dma_probe,
+ .remove = bam_dma_remove,
+ .driver = {
+ .name = "bam-dma-engine",
+ .owner = THIS_MODULE,
+ .of_match_table = bam_of_match,
+ },
+};
+
+module_platform_driver(bam_dma_driver);
+
+MODULE_AUTHOR("Andy Gross <agross@codeaurora.org>");
+MODULE_DESCRIPTION("QCOM BAM DMA engine driver");
+MODULE_LICENSE("GPL v2");
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
hosted by The Linux Foundation
^ permalink raw reply related
* Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
From: Emilio López @ 2014-02-24 23:38 UTC (permalink / raw)
To: Russell King - ARM Linux, Maxime Ripard
Cc: Dan Williams, Vinod Koul, devicetree-u79uwXL29TY76Z2rM5mHXA,
Mike Turquette, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20140224163034.GN21483-l+eeeJia6m9vn6HldHNs0ANdhmdF6hFW@public.gmane.org>
Hello Russell,
El 24/02/14 13:30, Russell King - ARM Linux escribió:
> On Mon, Feb 24, 2014 at 05:22:43PM +0100, Maxime Ripard wrote:
>> Right now, AHB is an indirect child clock of the CPU clock. If that happens to
>> change, since the CPU clock has no other consumers declared in Linux, it would
>> be shut down, which is not really a good idea.
>>
>> Prevent this by forcing it enabled.
>>
>> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>> ---
>> drivers/clk/sunxi/clk-sunxi.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/clk/sunxi/clk-sunxi.c b/drivers/clk/sunxi/clk-sunxi.c
>> index 23baad9..cedaf4b 100644
>> --- a/drivers/clk/sunxi/clk-sunxi.c
>> +++ b/drivers/clk/sunxi/clk-sunxi.c
>> @@ -1301,6 +1301,14 @@ static void __init sunxi_clock_protect(void)
>> clk_prepare_enable(clk);
>> clk_put(clk);
>> }
>> +
>> + /* CPU clocks - sun6i */
>> + clk = clk_get(NULL, "cpu");
>> + if (!IS_ERR(clk)) {
>> + clk_prepare_enable(clk);
>> + clk_put(clk);
>> + }
>
> This is broken. I'm not sure what's difficult to grasp about the concept
> of "while a clock is in use, you should keep a reference to that clock".
>
> That implies that if you get a clock, and then enable it, you don't
> put the clock until you've disabled it.
Why is this so? Can't a clock be left enabled while nobody has a
reference to it? I have looked around in Documentation/ (rather quickly
I must say) and have not found any explicit mention that it is required
to keep a reference to the clock while it's enabled. I'd appreciate it
if you could explain this a bit more verbosely or point me to the
relevant documents.
For what it's worth, I've seen this same pattern on
enable/disable_clock() on drivers/base/power/clock_ops.c as well.
Cheers,
Emilio
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^ permalink raw reply
* Re: [PATCH] ASoC: cs42888: Add codec driver support
From: Mark Brown @ 2014-02-25 0:00 UTC (permalink / raw)
To: Nicolin Chen
Cc: Austin, Brian, Handrigan, Paul, robh+dt@kernel.org,
pawel.moll@arm.com, mark.rutland@arm.com,
ijc+devicetree@hellion.org.uk, galak@codeaurora.org,
rob@landley.net, Liam Girdwood, grant.likely@linaro.org,
devicetree@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, alsa-devel@alsa-project.org
In-Reply-To: <20140224160648.GC6132@MrMyself>
[-- Attachment #1: Type: text/plain, Size: 858 bytes --]
On Tue, Feb 25, 2014 at 12:06:49AM +0800, Nicolin Chen wrote:
> On Mon, Feb 24, 2014 at 03:52:24PM +0000, Austin, Brian wrote:
> Wait...Regarding this clock part, I just forgot the reason I put the code:
> 385 cs42888->clk = devm_clk_get(&i2c->dev, "mclk");
> 386 if (IS_ERR(cs42888->clk))
> 387 dev_warn(&i2c->dev, "failed to get the clock: %ld\n",
> 388 PTR_ERR(cs42888->clk));
> was because the MCLK might be provided from SoC (DAI master) so it could
> be totally controlled by CPU DAI driver, ESAI for example has its own
> dividers to derive the HCKT clock (MCLK for Tx) from ahb clock in SoC
> clock tree, in which case we might not easily pass a valid clock phandle
> via DT. (RFC to this thought.)
We should be getting those clocks visible in the clock API rather than
doing this.
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 836 bytes --]
^ permalink raw reply
* Re: [PATCH 1/5] clk: sun6i: Protect CPU clock
From: Russell King - ARM Linux @ 2014-02-25 0:01 UTC (permalink / raw)
To: Emilio López
Cc: Maxime Ripard, devicetree-u79uwXL29TY76Z2rM5mHXA, Mike Turquette,
Vinod Koul, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
dmaengine-u79uwXL29TY76Z2rM5mHXA, Dan Williams,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <530BD804.5090806-0Z03zUJReD5OxF6Tv1QG9Q@public.gmane.org>
Hi Emilio.
On Mon, Feb 24, 2014 at 08:38:44PM -0300, Emilio López wrote:
> Why is this so? Can't a clock be left enabled while nobody has a
> reference to it? I have looked around in Documentation/ (rather quickly
> I must say) and have not found any explicit mention that it is required
> to keep a reference to the clock while it's enabled. I'd appreciate it
> if you could explain this a bit more verbosely or point me to the
> relevant documents.
First up, if you have a requirement that a clock be enabled, then is it
not unreasonable to ensure that the clock is referenced?
Secondly, what if we have code which scans the clocks in the system,
shutting down those leaf clocks which appear to be unreferenced?
Thirdly, the API (as I designed it) says so:
/**
* clk_put - "free" the clock source
* @clk: clock source
*
* Note: drivers must ensure that all clk_enable calls made on this
* clock source are balanced by clk_disable calls prior to calling
* this function.
*
* clk_put should not be called from within interrupt context.
*/
void clk_put(struct clk *clk);
which has been there since the API was first created - it's part of the
contract between drivers using the API and implementers creating something
which conforms to the API - which today means CCF.
The intention here is that while there are any users holding a clk_get()
reference on a clock, the clock is assumed to be required for some
device, and the struct clk may not be kfree'd, nor may its state be
changed in an unpredictable way to those drivers holding a reference
to it.
--
FTTC broadband for 0.8mile line: now at 9.7Mbps down 460kbps up... slowly
improving, and getting towards what was expected from it.
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^ permalink raw reply
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