* [PATCH 1/5] thermal: st_thermal_syscfg: Remove obsolete STiH415/416 platform support.
From: patrice.chotard-qxv4g6HH51o @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
patrice.chotard-qxv4g6HH51o, rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
STiH415/6 SoC support is being removed from the kernel.
This patch removes support from the syscfg thermal driver.
This driver also supports STiD127 SoC which has never been
upstreamed.
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Cc: <rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: <edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/thermal/st/Kconfig | 4 -
drivers/thermal/st/Makefile | 1 -
drivers/thermal/st/st_thermal_syscfg.c | 178 ---------------------------------
3 files changed, 183 deletions(-)
delete mode 100644 drivers/thermal/st/st_thermal_syscfg.c
diff --git a/drivers/thermal/st/Kconfig b/drivers/thermal/st/Kconfig
index 490fdbe..ce84267 100644
--- a/drivers/thermal/st/Kconfig
+++ b/drivers/thermal/st/Kconfig
@@ -3,10 +3,6 @@ config ST_THERMAL
help
Support for thermal sensors on STMicroelectronics STi series of SoCs.
-config ST_THERMAL_SYSCFG
- select ST_THERMAL
- tristate "STi series syscfg register access based thermal sensors"
-
config ST_THERMAL_MEMMAP
select ST_THERMAL
tristate "STi series memory mapped access based thermal sensors"
diff --git a/drivers/thermal/st/Makefile b/drivers/thermal/st/Makefile
index b388789..27197e1 100644
--- a/drivers/thermal/st/Makefile
+++ b/drivers/thermal/st/Makefile
@@ -1,3 +1,2 @@
obj-$(CONFIG_ST_THERMAL) := st_thermal.o
-obj-$(CONFIG_ST_THERMAL_SYSCFG) += st_thermal_syscfg.o
obj-$(CONFIG_ST_THERMAL_MEMMAP) += st_thermal_memmap.o
diff --git a/drivers/thermal/st/st_thermal_syscfg.c b/drivers/thermal/st/st_thermal_syscfg.c
deleted file mode 100644
index 3df5b789..0000000
--- a/drivers/thermal/st/st_thermal_syscfg.c
+++ /dev/null
@@ -1,178 +0,0 @@
-/*
- * ST Thermal Sensor Driver for syscfg based sensors.
- * Author: Ajit Pal Singh <ajitpal.singh-qxv4g6HH51o@public.gmane.org>
- *
- * Copyright (C) 2003-2014 STMicroelectronics (R&D) Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/of.h>
-#include <linux/module.h>
-#include <linux/mfd/syscon.h>
-
-#include "st_thermal.h"
-
-/* STiH415 */
-#define STIH415_SYSCFG_FRONT(num) ((num - 100) * 4)
-#define STIH415_SAS_THSENS_CONF STIH415_SYSCFG_FRONT(178)
-#define STIH415_SAS_THSENS_STATUS STIH415_SYSCFG_FRONT(198)
-#define STIH415_SYSCFG_MPE(num) ((num - 600) * 4)
-#define STIH415_MPE_THSENS_CONF STIH415_SYSCFG_MPE(607)
-#define STIH415_MPE_THSENS_STATUS STIH415_SYSCFG_MPE(667)
-
-/* STiH416 */
-#define STIH416_SYSCFG_FRONT(num) ((num - 1000) * 4)
-#define STIH416_SAS_THSENS_CONF STIH416_SYSCFG_FRONT(1552)
-#define STIH416_SAS_THSENS_STATUS1 STIH416_SYSCFG_FRONT(1554)
-#define STIH416_SAS_THSENS_STATUS2 STIH416_SYSCFG_FRONT(1594)
-
-/* STiD127 */
-#define STID127_SYSCFG_CPU(num) ((num - 700) * 4)
-#define STID127_THSENS_CONF STID127_SYSCFG_CPU(743)
-#define STID127_THSENS_STATUS STID127_SYSCFG_CPU(767)
-
-static const struct reg_field st_415sas_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH415_SAS_THSENS_CONF, 9, 9),
- [DCORRECT] = REG_FIELD(STIH415_SAS_THSENS_CONF, 4, 8),
- [OVERFLOW] = REG_FIELD(STIH415_SAS_THSENS_STATUS, 8, 8),
- [DATA] = REG_FIELD(STIH415_SAS_THSENS_STATUS, 10, 16),
-};
-
-static const struct reg_field st_415mpe_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH415_MPE_THSENS_CONF, 8, 8),
- [DCORRECT] = REG_FIELD(STIH415_MPE_THSENS_CONF, 3, 7),
- [OVERFLOW] = REG_FIELD(STIH415_MPE_THSENS_STATUS, 9, 9),
- [DATA] = REG_FIELD(STIH415_MPE_THSENS_STATUS, 11, 18),
-};
-
-static const struct reg_field st_416sas_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STIH416_SAS_THSENS_CONF, 9, 9),
- [DCORRECT] = REG_FIELD(STIH416_SAS_THSENS_CONF, 4, 8),
- [OVERFLOW] = REG_FIELD(STIH416_SAS_THSENS_STATUS1, 8, 8),
- [DATA] = REG_FIELD(STIH416_SAS_THSENS_STATUS2, 10, 16),
-};
-
-static const struct reg_field st_127_regfields[MAX_REGFIELDS] = {
- [TEMP_PWR] = REG_FIELD(STID127_THSENS_CONF, 7, 7),
- [DCORRECT] = REG_FIELD(STID127_THSENS_CONF, 2, 6),
- [OVERFLOW] = REG_FIELD(STID127_THSENS_STATUS, 9, 9),
- [DATA] = REG_FIELD(STID127_THSENS_STATUS, 11, 18),
-};
-
-/* Private OPs for System Configuration Register based thermal sensors */
-static int st_syscfg_power_ctrl(struct st_thermal_sensor *sensor,
- enum st_thermal_power_state power_state)
-{
- return regmap_field_write(sensor->pwr, power_state);
-}
-
-static int st_syscfg_alloc_regfields(struct st_thermal_sensor *sensor)
-{
- struct device *dev = sensor->dev;
-
- sensor->pwr = devm_regmap_field_alloc(dev, sensor->regmap,
- sensor->cdata->reg_fields[TEMP_PWR]);
-
- if (IS_ERR(sensor->pwr)) {
- dev_err(dev, "failed to alloc syscfg regfields\n");
- return PTR_ERR(sensor->pwr);
- }
-
- return 0;
-}
-
-static int st_syscfg_regmap_init(struct st_thermal_sensor *sensor)
-{
- sensor->regmap =
- syscon_regmap_lookup_by_compatible(sensor->cdata->sys_compat);
- if (IS_ERR(sensor->regmap)) {
- dev_err(sensor->dev, "failed to find syscfg regmap\n");
- return PTR_ERR(sensor->regmap);
- }
-
- return 0;
-}
-
-static const struct st_thermal_sensor_ops st_syscfg_sensor_ops = {
- .power_ctrl = st_syscfg_power_ctrl,
- .alloc_regfields = st_syscfg_alloc_regfields,
- .regmap_init = st_syscfg_regmap_init,
-};
-
-/* Compatible device data for stih415 sas thermal sensor */
-static const struct st_thermal_compat_data st_415sas_cdata = {
- .sys_compat = "st,stih415-front-syscfg",
- .reg_fields = st_415sas_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = 20,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stih415 mpe thermal sensor */
-static const struct st_thermal_compat_data st_415mpe_cdata = {
- .sys_compat = "st,stih415-system-syscfg",
- .reg_fields = st_415mpe_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = -103,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stih416 sas thermal sensor */
-static const struct st_thermal_compat_data st_416sas_cdata = {
- .sys_compat = "st,stih416-front-syscfg",
- .reg_fields = st_416sas_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 16,
- .temp_adjust_val = 20,
- .crit_temp = 120,
-};
-
-/* Compatible device data for stid127 thermal sensor */
-static const struct st_thermal_compat_data st_127_cdata = {
- .sys_compat = "st,stid127-cpu-syscfg",
- .reg_fields = st_127_regfields,
- .ops = &st_syscfg_sensor_ops,
- .calibration_val = 8,
- .temp_adjust_val = -103,
- .crit_temp = 120,
-};
-
-static const struct of_device_id st_syscfg_thermal_of_match[] = {
- { .compatible = "st,stih415-sas-thermal", .data = &st_415sas_cdata },
- { .compatible = "st,stih415-mpe-thermal", .data = &st_415mpe_cdata },
- { .compatible = "st,stih416-sas-thermal", .data = &st_416sas_cdata },
- { .compatible = "st,stid127-thermal", .data = &st_127_cdata },
- { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, st_syscfg_thermal_of_match);
-
-static int st_syscfg_probe(struct platform_device *pdev)
-{
- return st_thermal_register(pdev, st_syscfg_thermal_of_match);
-}
-
-static int st_syscfg_remove(struct platform_device *pdev)
-{
- return st_thermal_unregister(pdev);
-}
-
-static struct platform_driver st_syscfg_thermal_driver = {
- .driver = {
- .name = "st_syscfg_thermal",
- .pm = &st_thermal_pm_ops,
- .of_match_table = st_syscfg_thermal_of_match,
- },
- .probe = st_syscfg_probe,
- .remove = st_syscfg_remove,
-};
-module_platform_driver(st_syscfg_thermal_driver);
-
-MODULE_AUTHOR("STMicroelectronics (R&D) Limited <ajitpal.singh-qxv4g6HH51o@public.gmane.org>");
-MODULE_DESCRIPTION("STMicroelectronics STi SoC Thermal Sensor Driver");
-MODULE_LICENSE("GPL v2");
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/5] ARM: multi_v7_defconfig: Remove ST_THERMAL_SYSCFG Kconfig symbol
From: patrice.chotard-qxv4g6HH51o @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
patrice.chotard-qxv4g6HH51o, rui.zhang-ral2JQCrhuEAvxtiuMwx3w,
edubezval-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
STiH415/6 SoC support is being removed from the kernel and
was the only platform using this Kconfig symbol
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Cc: <rui.zhang-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: <edubezval-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/configs/multi_v7_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 437d074..15b2f99 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -450,7 +450,6 @@ CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_EXYNOS_THERMAL=m
-CONFIG_ST_THERMAL_SYSCFG=y
CONFIG_ST_THERMAL_MEMMAP=y
CONFIG_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=m
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 3/5] ARM: multi_v7_defconfig: Remove CONFIG_ST_THERMAL_MEMMAP Kconfig symbol
From: patrice.chotard @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, devicetree
Cc: peter.griffin, lee.jones, kernel, patrice.chotard, rui.zhang,
edubezval
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Driver code has been already removed, see
http://www.spinics.net/lists/devicetree/msg143322.html
Remove the multi_v7_defconfig part
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: <rui.zhang@intel.com>
Cc: <edubezval@gmail.com>
---
arch/arm/configs/multi_v7_defconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 15b2f99..45e252b 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -450,7 +450,6 @@ CONFIG_RCAR_THERMAL=y
CONFIG_ARMADA_THERMAL=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_EXYNOS_THERMAL=m
-CONFIG_ST_THERMAL_MEMMAP=y
CONFIG_WATCHDOG=y
CONFIG_DA9063_WATCHDOG=m
CONFIG_XILINX_WATCHDOG=y
--
1.9.1
^ permalink raw reply related
* [PATCH 4/5] irqchip: st: remove STiH415/416 irqchip support
From: patrice.chotard @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel, linux-kernel, devicetree
Cc: peter.griffin, lee.jones, kernel, patrice.chotard, tglx, jason,
marc.zyngier
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard@st.com>
From: Patrice Chotard <patrice.chotard@st.com>
Support for STiH415/6 SoCs is being removed from the
kernel because the platforms are obsolete. This patch removes
the irqchip for these SoC's.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Cc: <tglx@linutronix.de>
Cc: <jason@lakedaemon.net>
Cc: <marc.zyngier@arm.com>
---
drivers/irqchip/irq-st.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/irqchip/irq-st.c b/drivers/irqchip/irq-st.c
index 9af48a8..3ac9226 100644
--- a/drivers/irqchip/irq-st.c
+++ b/drivers/irqchip/irq-st.c
@@ -18,8 +18,6 @@
#include <linux/regmap.h>
#include <linux/slab.h>
-#define STIH415_SYSCFG_642 0x0a8
-#define STIH416_SYSCFG_7543 0x87c
#define STIH407_SYSCFG_5102 0x198
#define STID127_SYSCFG_734 0x088
@@ -48,14 +46,6 @@ struct st_irq_syscfg {
static const struct of_device_id st_irq_syscfg_match[] = {
{
- .compatible = "st,stih415-irq-syscfg",
- .data = (void *)STIH415_SYSCFG_642,
- },
- {
- .compatible = "st,stih416-irq-syscfg",
- .data = (void *)STIH416_SYSCFG_7543,
- },
- {
.compatible = "st,stih407-irq-syscfg",
.data = (void *)STIH407_SYSCFG_5102,
},
--
1.9.1
^ permalink raw reply related
* [PATCH 5/5] irqchip: st: Remove obsolete platforms from dt binding doc
From: patrice.chotard-qxv4g6HH51o @ 2016-10-21 15:57 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, kernel-F5mvAk5X5gdBDgjK7y7TUQ,
patrice.chotard-qxv4g6HH51o, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8
In-Reply-To: <1477065443-10668-1-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
STiH415/6 SoC support is being removed from the kernel.
This patch updates the sti irchip and removes
references to these obsolete platforms.
Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
Cc: <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
Cc: <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
Cc: <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
---
.../devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
index ced6014..23d1e1c 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt
@@ -7,8 +7,6 @@ This driver is used to unmask them prior to use.
Required properties:
- compatible : Should be set to one of:
- "st,stih415-irq-syscfg"
- "st,stih416-irq-syscfg"
"st,stih407-irq-syscfg"
"st,stid127-irq-syscfg"
- st,syscfg : Phandle to Cortex-A9 IRQ system config registers
@@ -25,8 +23,8 @@ Optional properties:
Example:
irq-syscfg {
- compatible = "st,stih416-irq-syscfg";
- st,syscfg = <&syscfg_cpu>;
+ compatible = "st,stih407-irq-syscfg";
+ st,syscfg = <&syscfg_core>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [RFC PATCH 08/13] dwmac-meson8b: add support for phy selection
From: Neil Armstrong @ 2016-10-21 15:59 UTC (permalink / raw)
To: Andrew Lunn
Cc: khilman, carlo, linus.walleij, linux-gpio, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel, netdev
In-Reply-To: <20161021155408.GR16974@lunn.ch>
On 10/21/2016 05:54 PM, Andrew Lunn wrote:
> On Fri, Oct 21, 2016 at 04:40:33PM +0200, Neil Armstrong wrote:
>> The Meson GXL dwmac Glue Layer also provides switching between an external PHY
>> and an internal RMII 10/100 PHY.
>> Add a way to setup the correct PHY switching from a device tree attribute.
>
> Humm, actually. Maybe PHY_IS_INTERNAL in the phydrv->flags is the
> better solution. The MAC can then use phy_is_internal(ndev->phydev) to
> decide if this register needs programming.
>
> Andrew
>
Hi Andrew,
Yes this would be a good idea if we were able to scan the internal and external PHYs at the same time,
but with our limited knowledge the values we write in the register seems to switch a mux for the whole RMII
and MDIO signals to either interface.
Do you have knowledge if this case is already handled upstream ?
Thanks for your help,
Neil
^ permalink raw reply
* Re: [RFC PATCH 08/13] dwmac-meson8b: add support for phy selection
From: Andrew Lunn @ 2016-10-21 16:08 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman, carlo, linus.walleij, linux-gpio, devicetree,
linux-arm-kernel, linux-amlogic, linux-kernel, netdev
In-Reply-To: <dc810494-6ece-c4ae-d412-ed9af3fac9c2@baylibre.com>
Hi Neil
> Yes this would be a good idea if we were able to scan the internal
> and external PHYs at the same time, but with our limited knowledge
> the values we write in the register seems to switch a mux for the
> whole RMII and MDIO signals to either interface.
Ah, O.K. So you need something like:
drivers/net/phy/mdio-mux-mmioreg.c
This seems to be limited to a single byte for the mux register, so you
might need to make some extensions.
Andrew
^ permalink raw reply
* [PATCH V7 0/4] dmaengine: qcom_hidma: add MSI interrupt support
From: Sinan Kaya @ 2016-10-21 16:37 UTC (permalink / raw)
To: dmaengine-u79uwXL29TY76Z2rM5mHXA, timur-sgV2jX0FEOL9JmXXK+q4OQ,
devicetree-u79uwXL29TY76Z2rM5mHXA, cov-sgV2jX0FEOL9JmXXK+q4OQ,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w, jcm-H+wXaHxf7aLQT0dZR+AlfA
Cc: agross-sgV2jX0FEOL9JmXXK+q4OQ, arnd-r2nGTMty4D4,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Sinan Kaya
The new version of the HW supports MSI interrupts instead of wired
interrupts. The MSI interrupts are especially useful for the guest machine
execution. The wired interrupts usually trap to the hypervisor and then are
relayed to the actual interrupt.
The MSI interrupts can be directly fed into the interrupt controller.
Adding a new OF compat string (qcom,hidma-1.1) and ACPI string (QCOM8062)
to distinguish newer HW from the older ones.
v7:
* rebase on top of Vinod's topic/qcom
* drop first 6 patches as they are already applied
v6:
http://www.spinics.net/lists/devicetree/msg146700.html
* rebase 4.9 kernel
v5:
http://www.spinics.net/lists/arm-kernel/msg537014.html
* dmaengine: qcom_hidma: add MSI support for interrupts
** Return MSI interrupts before calling platform_msi_domain_free_irqs.
Also cleanup MSI interrupts on the error path.
** Free the legacy IRQ only if MSI is disabled
* add dmaengine: qcom_hidma: break completion processing on error
in order to break the completions if an error is observed while servicing
completed work.
* drop dmaengine: qcom_hidma: make error and success path common
as the success path assumes that we'll get the number of notifications for
the
jobs queued. This is not true under error conditions.
* simplify dmaengine: qcom_hidma: protect common data structures. We just
need to protect the TRE processed offset. It is the variable that keeps
track
of outstanding requests.
v4:
http://www.spinics.net/lists/devicetree/msg144563.html
* device tree binding update to refer to msi.txt
v3:
* day 0 fix for when ACPI is not compiled in
* https://www.spinics.net/lists/arm-kernel/msg532179.html
v2:
https://patchwork.kernel.org/patch/9326399/
* Documentation update for DT bindings
* Rebased to slave-next
* Dropped dmaengine: qcom_hidma: eliminate processed variables. Replaced it
with dmaengine: qcom_hidma: protect common data structures
v1:
http://lists.infradead.org/pipermail/linux-arm-kernel/2016-July/444167.html
* initial implementation
Sinan Kaya (4):
dmaengine: qcom_hidma: make pending_tre_count atomic
dmaengine: qcom_hidma: bring out interrupt cause
dmaengine: qcom_hidma: protect common data structures
dmaengine: qcom_hidma: add MSI support for interrupts
drivers/dma/qcom/hidma.c | 143 +++++++++++++++++++++++++++++++++++++++++--
drivers/dma/qcom/hidma.h | 4 +-
drivers/dma/qcom/hidma_dbg.c | 3 +-
drivers/dma/qcom/hidma_ll.c | 127 ++++++++++++++++++--------------------
4 files changed, 200 insertions(+), 77 deletions(-)
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH V7 1/4] dmaengine: qcom_hidma: make pending_tre_count atomic
From: Sinan Kaya @ 2016-10-21 16:37 UTC (permalink / raw)
To: dmaengine, timur, devicetree, cov, vinod.koul, jcm
Cc: agross, arnd, linux-arm-msm, linux-arm-kernel, Sinan Kaya,
Dan Williams, Andy Shevchenko, linux-kernel
In-Reply-To: <1477067879-23750-1-git-send-email-okaya@codeaurora.org>
Getting ready for the MSI interrupts. The pending_tre_count is used
in the interrupt handler to make sure all outstanding requests are
serviced.
The driver will allocate 11 MSI interrupts. Each MSI interrupt can be
assigned to a different CPU. Then, we have a race condition for common
variables as they share the same interrupt handler with a different
cause bit and they can potentially be executed in parallel. Making this
variable atomic so that it can be updated from multiple processor
contexts.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.h | 2 +-
drivers/dma/qcom/hidma_dbg.c | 3 ++-
drivers/dma/qcom/hidma_ll.c | 13 ++++++-------
3 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/qcom/hidma.h b/drivers/dma/qcom/hidma.h
index de61764..181f7e0 100644
--- a/drivers/dma/qcom/hidma.h
+++ b/drivers/dma/qcom/hidma.h
@@ -59,7 +59,7 @@ struct hidma_lldev {
void __iomem *evca; /* Event Channel address */
struct hidma_tre
**pending_tre_list; /* Pointers to pending TREs */
- s32 pending_tre_count; /* Number of TREs pending */
+ atomic_t pending_tre_count; /* Number of TREs pending */
void *tre_ring; /* TRE ring */
dma_addr_t tre_dma; /* TRE ring to be shared with HW */
diff --git a/drivers/dma/qcom/hidma_dbg.c b/drivers/dma/qcom/hidma_dbg.c
index 3d83b99..3bdcb80 100644
--- a/drivers/dma/qcom/hidma_dbg.c
+++ b/drivers/dma/qcom/hidma_dbg.c
@@ -74,7 +74,8 @@ static void hidma_ll_devstats(struct seq_file *s, void *llhndl)
seq_printf(s, "tre_ring_handle=%pap\n", &lldev->tre_dma);
seq_printf(s, "tre_ring_size = 0x%x\n", lldev->tre_ring_size);
seq_printf(s, "tre_processed_off = 0x%x\n", lldev->tre_processed_off);
- seq_printf(s, "pending_tre_count=%d\n", lldev->pending_tre_count);
+ seq_printf(s, "pending_tre_count=%d\n",
+ atomic_read(&lldev->pending_tre_count));
seq_printf(s, "evca=%p\n", lldev->evca);
seq_printf(s, "evre_ring=%p\n", lldev->evre_ring);
seq_printf(s, "evre_ring_handle=%pap\n", &lldev->evre_dma);
diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c
index e605c90..114409e 100644
--- a/drivers/dma/qcom/hidma_ll.c
+++ b/drivers/dma/qcom/hidma_ll.c
@@ -218,10 +218,9 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator,
* Keep track of pending TREs that SW is expecting to receive
* from HW. We got one now. Decrement our counter.
*/
- lldev->pending_tre_count--;
- if (lldev->pending_tre_count < 0) {
+ if (atomic_dec_return(&lldev->pending_tre_count) < 0) {
dev_warn(lldev->dev, "tre count mismatch on completion");
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
}
spin_unlock_irqrestore(&lldev->lock, flags);
@@ -328,7 +327,7 @@ void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info,
u32 tre_read_off;
tre_iterator = lldev->tre_processed_off;
- while (lldev->pending_tre_count) {
+ while (atomic_read(&lldev->pending_tre_count)) {
if (hidma_post_completed(lldev, tre_iterator, err_info,
err_code))
break;
@@ -555,7 +554,7 @@ void hidma_ll_queue_request(struct hidma_lldev *lldev, u32 tre_ch)
tre->err_code = 0;
tre->err_info = 0;
tre->queued = 1;
- lldev->pending_tre_count++;
+ atomic_inc(&lldev->pending_tre_count);
lldev->tre_write_offset = (lldev->tre_write_offset + HIDMA_TRE_SIZE)
% lldev->tre_ring_size;
spin_unlock_irqrestore(&lldev->lock, flags);
@@ -650,7 +649,7 @@ int hidma_ll_setup(struct hidma_lldev *lldev)
u32 val;
u32 nr_tres = lldev->nr_tres;
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
lldev->tre_processed_off = 0;
lldev->evre_processed_off = 0;
lldev->tre_write_offset = 0;
@@ -831,7 +830,7 @@ int hidma_ll_uninit(struct hidma_lldev *lldev)
tasklet_kill(&lldev->task);
memset(lldev->trepool, 0, required_bytes);
lldev->trepool = NULL;
- lldev->pending_tre_count = 0;
+ atomic_set(&lldev->pending_tre_count, 0);
lldev->tre_write_offset = 0;
rc = hidma_ll_reset(lldev);
--
1.9.1
^ permalink raw reply related
* [PATCH V7 2/4] dmaengine: qcom_hidma: bring out interrupt cause
From: Sinan Kaya @ 2016-10-21 16:37 UTC (permalink / raw)
To: dmaengine, timur, devicetree, cov, vinod.koul, jcm
Cc: agross, arnd, linux-arm-msm, linux-arm-kernel, Sinan Kaya,
Dan Williams, linux-kernel
In-Reply-To: <1477067879-23750-1-git-send-email-okaya@codeaurora.org>
Bring out the interrupt cause to the top level so that MSI interrupts
can be hooked at a later stage.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma_ll.c | 62 ++++++++++++++++++++++++---------------------
1 file changed, 33 insertions(+), 29 deletions(-)
diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c
index 114409e..9193f46 100644
--- a/drivers/dma/qcom/hidma_ll.c
+++ b/drivers/dma/qcom/hidma_ll.c
@@ -418,12 +418,24 @@ static int hidma_ll_reset(struct hidma_lldev *lldev)
* requests traditionally to the destination, this concept does not apply
* here for this HW.
*/
-irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
+static void hidma_ll_int_handler_internal(struct hidma_lldev *lldev, int cause)
{
- struct hidma_lldev *lldev = arg;
- u32 status;
- u32 enable;
- u32 cause;
+ if (cause & HIDMA_ERR_INT_MASK) {
+ dev_err(lldev->dev, "error 0x%x, disabling...\n",
+ cause);
+
+ /* Clear out pending interrupts */
+ writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
+
+ /* No further submissions. */
+ hidma_ll_disable(lldev);
+
+ /* Driver completes the txn and intimates the client.*/
+ hidma_cleanup_pending_tre(lldev, 0xFF,
+ HIDMA_EVRE_STATUS_ERROR);
+
+ return;
+ }
/*
* Fine tuned for this HW...
@@ -432,35 +444,28 @@ irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
* read and write accessors are used for performance reasons due to
* interrupt delivery guarantees. Do not copy this code blindly and
* expect that to work.
+ *
+ * Try to consume as many EVREs as possible.
*/
+ hidma_handle_tre_completion(lldev);
+
+ /* We consumed TREs or there are pending TREs or EVREs. */
+ writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
+}
+
+irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
+{
+ struct hidma_lldev *lldev = arg;
+ u32 status;
+ u32 enable;
+ u32 cause;
+
status = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_STAT_REG);
enable = readl_relaxed(lldev->evca + HIDMA_EVCA_IRQ_EN_REG);
cause = status & enable;
while (cause) {
- if (cause & HIDMA_ERR_INT_MASK) {
- dev_err(lldev->dev, "error 0x%x, disabling...\n",
- cause);
-
- /* Clear out pending interrupts */
- writel(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
-
- /* No further submissions. */
- hidma_ll_disable(lldev);
-
- /* Driver completes the txn and intimates the client.*/
- hidma_cleanup_pending_tre(lldev, 0xFF,
- HIDMA_EVRE_STATUS_ERROR);
- goto out;
- }
-
- /*
- * Try to consume as many EVREs as possible.
- */
- hidma_handle_tre_completion(lldev);
-
- /* We consumed TREs or there are pending TREs or EVREs. */
- writel_relaxed(cause, lldev->evca + HIDMA_EVCA_IRQ_CLR_REG);
+ hidma_ll_int_handler_internal(lldev, cause);
/*
* Another interrupt might have arrived while we are
@@ -471,7 +476,6 @@ irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
cause = status & enable;
}
-out:
return IRQ_HANDLED;
}
--
1.9.1
^ permalink raw reply related
* [PATCH V7 3/4] dmaengine: qcom_hidma: protect common data structures
From: Sinan Kaya @ 2016-10-21 16:37 UTC (permalink / raw)
To: dmaengine, timur, devicetree, cov, vinod.koul, jcm
Cc: agross, arnd, linux-arm-msm, linux-arm-kernel, Sinan Kaya,
Dan Williams, linux-kernel
In-Reply-To: <1477067879-23750-1-git-send-email-okaya@codeaurora.org>
When MSI interrupts are supported, error and the transfer interrupt can
come from multiple processor contexts.
Each error interrupt is an MSI interrupt. If the channel is disabled by
the first error interrupt, the remaining error interrupts will gracefully
return in the interrupt handler.
If an error is observed while servicing the completions in success case,
the posting of the completions will be aborted as soon as channel disabled
state is observed. The error interrupt handler will take it from there and
finish the remaining completions. We don't want to create multiple success
and error messages to be delivered to the client in mixed order.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma_ll.c | 44 +++++++++++---------------------------------
1 file changed, 11 insertions(+), 33 deletions(-)
diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c
index 9193f46..7fe43af 100644
--- a/drivers/dma/qcom/hidma_ll.c
+++ b/drivers/dma/qcom/hidma_ll.c
@@ -198,13 +198,16 @@ static void hidma_ll_tre_complete(unsigned long arg)
}
}
-static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator,
- u8 err_info, u8 err_code)
+static int hidma_post_completed(struct hidma_lldev *lldev, u8 err_info,
+ u8 err_code)
{
struct hidma_tre *tre;
unsigned long flags;
+ u32 tre_iterator;
spin_lock_irqsave(&lldev->lock, flags);
+
+ tre_iterator = lldev->tre_processed_off;
tre = lldev->pending_tre_list[tre_iterator / HIDMA_TRE_SIZE];
if (!tre) {
spin_unlock_irqrestore(&lldev->lock, flags);
@@ -223,6 +226,9 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator,
atomic_set(&lldev->pending_tre_count, 0);
}
+ HIDMA_INCREMENT_ITERATOR(tre_iterator, HIDMA_TRE_SIZE,
+ lldev->tre_ring_size);
+ lldev->tre_processed_off = tre_iterator;
spin_unlock_irqrestore(&lldev->lock, flags);
tre->err_info = err_info;
@@ -244,13 +250,11 @@ static int hidma_post_completed(struct hidma_lldev *lldev, int tre_iterator,
static int hidma_handle_tre_completion(struct hidma_lldev *lldev)
{
u32 evre_ring_size = lldev->evre_ring_size;
- u32 tre_ring_size = lldev->tre_ring_size;
u32 err_info, err_code, evre_write_off;
- u32 tre_iterator, evre_iterator;
+ u32 evre_iterator;
u32 num_completed = 0;
evre_write_off = readl_relaxed(lldev->evca + HIDMA_EVCA_WRITE_PTR_REG);
- tre_iterator = lldev->tre_processed_off;
evre_iterator = lldev->evre_processed_off;
if ((evre_write_off > evre_ring_size) ||
@@ -273,12 +277,9 @@ static int hidma_handle_tre_completion(struct hidma_lldev *lldev)
err_code =
(cfg >> HIDMA_EVRE_CODE_BIT_POS) & HIDMA_EVRE_CODE_MASK;
- if (hidma_post_completed(lldev, tre_iterator, err_info,
- err_code))
+ if (hidma_post_completed(lldev, err_info, err_code))
break;
- HIDMA_INCREMENT_ITERATOR(tre_iterator, HIDMA_TRE_SIZE,
- tre_ring_size);
HIDMA_INCREMENT_ITERATOR(evre_iterator, HIDMA_EVRE_SIZE,
evre_ring_size);
@@ -302,16 +303,10 @@ static int hidma_handle_tre_completion(struct hidma_lldev *lldev)
if (num_completed) {
u32 evre_read_off = (lldev->evre_processed_off +
HIDMA_EVRE_SIZE * num_completed);
- u32 tre_read_off = (lldev->tre_processed_off +
- HIDMA_TRE_SIZE * num_completed);
-
evre_read_off = evre_read_off % evre_ring_size;
- tre_read_off = tre_read_off % tre_ring_size;
-
writel(evre_read_off, lldev->evca + HIDMA_EVCA_DOORBELL_REG);
/* record the last processed tre offset */
- lldev->tre_processed_off = tre_read_off;
lldev->evre_processed_off = evre_read_off;
}
@@ -321,27 +316,10 @@ static int hidma_handle_tre_completion(struct hidma_lldev *lldev)
void hidma_cleanup_pending_tre(struct hidma_lldev *lldev, u8 err_info,
u8 err_code)
{
- u32 tre_iterator;
- u32 tre_ring_size = lldev->tre_ring_size;
- int num_completed = 0;
- u32 tre_read_off;
-
- tre_iterator = lldev->tre_processed_off;
while (atomic_read(&lldev->pending_tre_count)) {
- if (hidma_post_completed(lldev, tre_iterator, err_info,
- err_code))
+ if (hidma_post_completed(lldev, err_info, err_code))
break;
- HIDMA_INCREMENT_ITERATOR(tre_iterator, HIDMA_TRE_SIZE,
- tre_ring_size);
- num_completed++;
}
- tre_read_off = (lldev->tre_processed_off +
- HIDMA_TRE_SIZE * num_completed);
-
- tre_read_off = tre_read_off % tre_ring_size;
-
- /* record the last processed tre offset */
- lldev->tre_processed_off = tre_read_off;
}
static int hidma_ll_reset(struct hidma_lldev *lldev)
--
1.9.1
^ permalink raw reply related
* [PATCH V7 4/4] dmaengine: qcom_hidma: add MSI support for interrupts
From: Sinan Kaya @ 2016-10-21 16:37 UTC (permalink / raw)
To: dmaengine, timur, devicetree, cov, vinod.koul, jcm
Cc: agross, arnd, linux-arm-msm, linux-arm-kernel, Sinan Kaya,
Dan Williams, Andy Shevchenko, Dave Jiang, Lars-Peter Clausen,
linux-kernel
In-Reply-To: <1477067879-23750-1-git-send-email-okaya@codeaurora.org>
The interrupts can now be delivered as platform MSI interrupts on newer
platforms. The code looks for a new OF and ACPI strings in order to enable
the functionality.
Signed-off-by: Sinan Kaya <okaya@codeaurora.org>
---
drivers/dma/qcom/hidma.c | 143 ++++++++++++++++++++++++++++++++++++++++++--
drivers/dma/qcom/hidma.h | 2 +
drivers/dma/qcom/hidma_ll.c | 8 +++
3 files changed, 147 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/qcom/hidma.c b/drivers/dma/qcom/hidma.c
index e244e10..d5e7991 100644
--- a/drivers/dma/qcom/hidma.c
+++ b/drivers/dma/qcom/hidma.c
@@ -56,6 +56,7 @@
#include <linux/irq.h>
#include <linux/atomic.h>
#include <linux/pm_runtime.h>
+#include <linux/msi.h>
#include "../dmaengine.h"
#include "hidma.h"
@@ -70,6 +71,7 @@
#define HIDMA_ERR_INFO_SW 0xFF
#define HIDMA_ERR_CODE_UNEXPECTED_TERMINATE 0x0
#define HIDMA_NR_DEFAULT_DESC 10
+#define HIDMA_MSI_INTS 11
static inline struct hidma_dev *to_hidma_dev(struct dma_device *dmadev)
{
@@ -553,6 +555,15 @@ static irqreturn_t hidma_chirq_handler(int chirq, void *arg)
return hidma_ll_inthandler(chirq, lldev);
}
+static irqreturn_t hidma_chirq_handler_msi(int chirq, void *arg)
+{
+ struct hidma_lldev **lldevp = arg;
+ struct hidma_dev *dmadev = to_hidma_dev_from_lldev(lldevp);
+
+ return hidma_ll_inthandler_msi(chirq, *lldevp,
+ 1 << (chirq - dmadev->msi_virqbase));
+}
+
static ssize_t hidma_show_values(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -590,6 +601,104 @@ static int hidma_create_sysfs_entry(struct hidma_dev *dev, char *name,
return device_create_file(dev->ddev.dev, attrs);
}
+#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
+static void hidma_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+ struct device *dev = msi_desc_to_dev(desc);
+ struct hidma_dev *dmadev = dev_get_drvdata(dev);
+
+ if (!desc->platform.msi_index) {
+ writel(msg->address_lo, dmadev->dev_evca + 0x118);
+ writel(msg->address_hi, dmadev->dev_evca + 0x11C);
+ writel(msg->data, dmadev->dev_evca + 0x120);
+ }
+}
+#endif
+
+static void hidma_free_msis(struct hidma_dev *dmadev)
+{
+#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
+ struct device *dev = dmadev->ddev.dev;
+ struct msi_desc *desc;
+
+ /* free allocated MSI interrupts above */
+ for_each_msi_entry(desc, dev)
+ devm_free_irq(dev, desc->irq, &dmadev->lldev);
+
+ platform_msi_domain_free_irqs(dev);
+#endif
+}
+
+static int hidma_request_msi(struct hidma_dev *dmadev,
+ struct platform_device *pdev)
+{
+#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN
+ int rc;
+ struct msi_desc *desc;
+ struct msi_desc *failed_desc = NULL;
+
+ rc = platform_msi_domain_alloc_irqs(&pdev->dev, HIDMA_MSI_INTS,
+ hidma_write_msi_msg);
+ if (rc)
+ return rc;
+
+ for_each_msi_entry(desc, &pdev->dev) {
+ if (!desc->platform.msi_index)
+ dmadev->msi_virqbase = desc->irq;
+
+ rc = devm_request_irq(&pdev->dev, desc->irq,
+ hidma_chirq_handler_msi,
+ 0, "qcom-hidma-msi",
+ &dmadev->lldev);
+ if (rc) {
+ failed_desc = desc;
+ break;
+ }
+ }
+
+ if (rc) {
+ /* free allocated MSI interrupts above */
+ for_each_msi_entry(desc, &pdev->dev) {
+ if (desc == failed_desc)
+ break;
+ devm_free_irq(&pdev->dev, desc->irq,
+ &dmadev->lldev);
+ }
+ } else {
+ /* Add callback to free MSIs on teardown */
+ hidma_ll_setup_irq(dmadev->lldev, true);
+
+ }
+ if (rc)
+ dev_warn(&pdev->dev,
+ "failed to request MSI irq, falling back to wired IRQ\n");
+ return rc;
+#else
+ return -EINVAL;
+#endif
+}
+
+static bool hidma_msi_capable(struct device *dev)
+{
+ struct acpi_device *adev = ACPI_COMPANION(dev);
+ const char *of_compat;
+ int ret = -EINVAL;
+
+ if (!adev || acpi_disabled) {
+ ret = device_property_read_string(dev, "compatible",
+ &of_compat);
+ if (ret)
+ return false;
+
+ ret = strcmp(of_compat, "qcom,hidma-1.1");
+ } else {
+#ifdef CONFIG_ACPI
+ ret = strcmp(acpi_device_hid(adev), "QCOM8062");
+#endif
+ }
+ return ret == 0;
+}
+
static int hidma_probe(struct platform_device *pdev)
{
struct hidma_dev *dmadev;
@@ -599,6 +708,7 @@ static int hidma_probe(struct platform_device *pdev)
void __iomem *evca;
void __iomem *trca;
int rc;
+ bool msi;
pm_runtime_set_autosuspend_delay(&pdev->dev, HIDMA_AUTOSUSPEND_TIMEOUT);
pm_runtime_use_autosuspend(&pdev->dev);
@@ -660,6 +770,12 @@ static int hidma_probe(struct platform_device *pdev)
dmadev->ddev.device_terminate_all = hidma_terminate_all;
dmadev->ddev.copy_align = 8;
+ /*
+ * Determine the MSI capability of the platform. Old HW doesn't
+ * support MSI.
+ */
+ msi = hidma_msi_capable(&pdev->dev);
+
device_property_read_u32(&pdev->dev, "desc-count",
&dmadev->nr_descriptors);
@@ -688,10 +804,17 @@ static int hidma_probe(struct platform_device *pdev)
goto dmafree;
}
- rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler, 0,
- "qcom-hidma", dmadev->lldev);
- if (rc)
- goto uninit;
+ platform_set_drvdata(pdev, dmadev);
+ if (msi)
+ rc = hidma_request_msi(dmadev, pdev);
+
+ if (!msi || rc) {
+ hidma_ll_setup_irq(dmadev->lldev, false);
+ rc = devm_request_irq(&pdev->dev, chirq, hidma_chirq_handler,
+ 0, "qcom-hidma", dmadev->lldev);
+ if (rc)
+ goto uninit;
+ }
INIT_LIST_HEAD(&dmadev->ddev.channels);
rc = hidma_chan_init(dmadev, 0);
@@ -707,12 +830,14 @@ static int hidma_probe(struct platform_device *pdev)
hidma_debug_init(dmadev);
hidma_create_sysfs_entry(dmadev, "chid", S_IRUGO);
dev_info(&pdev->dev, "HI-DMA engine driver registration complete\n");
- platform_set_drvdata(pdev, dmadev);
pm_runtime_mark_last_busy(dmadev->ddev.dev);
pm_runtime_put_autosuspend(dmadev->ddev.dev);
return 0;
uninit:
+ if (msi)
+ hidma_free_msis(dmadev);
+
hidma_debug_uninit(dmadev);
hidma_ll_uninit(dmadev->lldev);
dmafree:
@@ -730,7 +855,11 @@ static int hidma_remove(struct platform_device *pdev)
pm_runtime_get_sync(dmadev->ddev.dev);
dma_async_device_unregister(&dmadev->ddev);
- devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
+ if (!dmadev->lldev->msi_support)
+ devm_free_irq(dmadev->ddev.dev, dmadev->irq, dmadev->lldev);
+ else
+ hidma_free_msis(dmadev);
+
tasklet_kill(&dmadev->task);
hidma_debug_uninit(dmadev);
hidma_ll_uninit(dmadev->lldev);
@@ -746,12 +875,14 @@ static int hidma_remove(struct platform_device *pdev)
#if IS_ENABLED(CONFIG_ACPI)
static const struct acpi_device_id hidma_acpi_ids[] = {
{"QCOM8061"},
+ {"QCOM8062"},
{},
};
#endif
static const struct of_device_id hidma_match[] = {
{.compatible = "qcom,hidma-1.0",},
+ {.compatible = "qcom,hidma-1.1",},
{},
};
MODULE_DEVICE_TABLE(of, hidma_match);
diff --git a/drivers/dma/qcom/hidma.h b/drivers/dma/qcom/hidma.h
index 181f7e0..05f8ba4 100644
--- a/drivers/dma/qcom/hidma.h
+++ b/drivers/dma/qcom/hidma.h
@@ -115,6 +115,7 @@ struct hidma_dev {
int irq;
int chidx;
u32 nr_descriptors;
+ int msi_virqbase;
struct hidma_lldev *lldev;
void __iomem *dev_trca;
@@ -153,6 +154,7 @@ struct hidma_lldev *hidma_ll_init(struct device *dev, u32 max_channels,
u8 chidx);
int hidma_ll_uninit(struct hidma_lldev *llhndl);
irqreturn_t hidma_ll_inthandler(int irq, void *arg);
+irqreturn_t hidma_ll_inthandler_msi(int irq, void *arg, int cause);
void hidma_cleanup_pending_tre(struct hidma_lldev *llhndl, u8 err_info,
u8 err_code);
int hidma_debug_init(struct hidma_dev *dmadev);
diff --git a/drivers/dma/qcom/hidma_ll.c b/drivers/dma/qcom/hidma_ll.c
index 7fe43af..6645bdf 100644
--- a/drivers/dma/qcom/hidma_ll.c
+++ b/drivers/dma/qcom/hidma_ll.c
@@ -457,6 +457,14 @@ irqreturn_t hidma_ll_inthandler(int chirq, void *arg)
return IRQ_HANDLED;
}
+irqreturn_t hidma_ll_inthandler_msi(int chirq, void *arg, int cause)
+{
+ struct hidma_lldev *lldev = arg;
+
+ hidma_ll_int_handler_internal(lldev, cause);
+ return IRQ_HANDLED;
+}
+
int hidma_ll_enable(struct hidma_lldev *lldev)
{
u32 val;
--
1.9.1
^ permalink raw reply related
* [PATCH v5] mwifiex: parse device tree node for PCIe
From: Rajat Jain @ 2016-10-21 17:15 UTC (permalink / raw)
To: linux-wireless-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, rajatja-hpIqsD4AKlfQT0dZR+AlfA,
Xinming Hu, Amitkumar Karwar, Brian Norris, Kalle Valo,
Rob Herring
Cc: rajatxjain-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20161021020609.GA18359@localhost>
From: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
This patch derives device tree node from pcie bus layer framework, and
fixes a minor memory leak in mwifiex_pcie_probe() (in failure path).
Device tree bindings file has been renamed(marvell-sd8xxx.txt ->
marvell-8xxx.txt) to accomodate PCIe changes.
Signed-off-by: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Amitkumar Karwar <akarwar-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
Signed-off-by: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Reviewed-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
v2: Included vendor and product IDs in compatible strings for PCIe
chipsets(Rob Herring)
v3: Patch is created using -M option so that it will only include diff of
original and renamed files(Rob Herring)
Resend v3: Resending the patch because I missed to include device tree mailing
while sending v3.
v4: Fix error handling, also move-on even if no device tree node is present.
v5: Update commit log to include memory leak, return -EINVAL instead of -1.
.../{marvell-sd8xxx.txt => marvell-8xxx.txt} | 8 +++--
drivers/net/wireless/marvell/mwifiex/pcie.c | 39 +++++++++++++++++++---
drivers/net/wireless/marvell/mwifiex/sta_cmd.c | 3 +-
3 files changed, 42 insertions(+), 8 deletions(-)
rename Documentation/devicetree/bindings/net/wireless/{marvell-sd8xxx.txt => marvell-8xxx.txt} (91%)
diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
similarity index 91%
rename from Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
rename to Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
index c421aba..dfe5f8e 100644
--- a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
+++ b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
@@ -1,8 +1,8 @@
-Marvell 8897/8997 (sd8897/sd8997) SDIO devices
+Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices
------
-This node provides properties for controlling the marvell sdio wireless device.
-The node is expected to be specified as a child node to the SDIO controller that
+This node provides properties for controlling the marvell sdio/pcie wireless device.
+The node is expected to be specified as a child node to the SDIO/PCIE controller that
connects the device to the system.
Required properties:
@@ -10,6 +10,8 @@ Required properties:
- compatible : should be one of the following:
* "marvell,sd8897"
* "marvell,sd8997"
+ * "pci11ab,2b42"
+ * "pci1b4b,2b42"
Optional properties:
diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c
index 3c3c4f1..7c44f88 100644
--- a/drivers/net/wireless/marvell/mwifiex/pcie.c
+++ b/drivers/net/wireless/marvell/mwifiex/pcie.c
@@ -37,6 +37,22 @@ static struct mwifiex_if_ops pcie_ops;
static struct semaphore add_remove_card_sem;
+static const struct of_device_id mwifiex_pcie_of_match_table[] = {
+ { .compatible = "pci11ab,2b42" },
+ { .compatible = "pci1b4b,2b42" },
+ { }
+};
+
+static int mwifiex_pcie_probe_of(struct device *dev)
+{
+ if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
+ pr_err("pcie device node not available");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
size_t size, int flags)
@@ -178,6 +194,7 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev,
const struct pci_device_id *ent)
{
struct pcie_service_card *card;
+ int ret;
pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
pdev->vendor, pdev->device, pdev->revision);
@@ -199,13 +216,27 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev,
card->pcie.can_ext_scan = data->can_ext_scan;
}
- if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
- MWIFIEX_PCIE)) {
- pr_err("%s failed\n", __func__);
- return -1;
+ /* device tree node parsing and platform specific configuration*/
+ if (pdev->dev.of_node) {
+ ret = mwifiex_pcie_probe_of(&pdev->dev);
+ if (ret) {
+ dev_err(&pdev->dev,
+ "required compatible string missing\n");
+ goto err_free;
+ }
}
+ ret = mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
+ MWIFIEX_PCIE);
+ if (ret) {
+ pr_err("%s failed\n", __func__);
+ goto err_free;
+ }
return 0;
+
+err_free:
+ kfree(card);
+ return ret;
}
/*
diff --git a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
index 2a162c3..c8dccf5 100644
--- a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
+++ b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
@@ -2218,7 +2218,8 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta, bool init)
* The cal-data can be read from device tree and/or
* a configuration file and downloaded to firmware.
*/
- if (priv->adapter->iface_type == MWIFIEX_SDIO &&
+ if ((priv->adapter->iface_type == MWIFIEX_SDIO ||
+ priv->adapter->iface_type == MWIFIEX_PCIE) &&
adapter->dev->of_node) {
adapter->dt_node = adapter->dev->of_node;
if (of_property_read_u32(adapter->dt_node,
--
2.8.0.rc3.226.g39d4020
^ permalink raw reply related
* Re: [PATCH] x86: bzImage: Allow the appending of a device tree binary
From: Mark Rutland @ 2016-10-21 17:38 UTC (permalink / raw)
To: Franck Jullien
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w,
jose.abreu-HKixBCOQz3hWk0Htik3J/w,
panto-wVdstyuyKrO8r51toPun2/C9HSW9iNxf,
lars-Qo5EllUWu/uELgA04lAiVw
In-Reply-To: <1476512960-22406-1-git-send-email-franck.jullien-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sat, Oct 15, 2016 at 08:29:20AM +0200, Franck Jullien wrote:
> This patch provides the ability to boot using a device tree that is appended
> to the raw binary bzImage (e.g. cat bzImage <filename>.dtb > bzImage_w_dtb).
>
> Based on Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org> work on x86
> builtin dtb support.
>
> Signed-off-by: Franck Jullien <franck.jullien-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
I understand that the rationale for this is to describe devices
instantiated dynamically on an FPGA (or to provide a base for overlays
to be applied when they are later instantiated).
I don't think that this, as it stands, is a good idea.
For one thing, this provides us with no notion of topology (i.e. where
the FPGA device falls in the interconnect hierarchy), as there's no
"nexus" defined where the DT bridges onto the existing ACPI topology.
Worse, even if that were present, we have no way of mapping things like
interrupts across the ACPI/DT boundary, and more complex things like
IOMMU mastering (where ACPI and DT differ quite substantially).
Generally, I do not think that mixing ACPI and DT is a good idea, as
there are a number of conceptual differences, and there is no trivial
mapping between them generally.
If you need to work atop of ACPI, I think that you need extensions to
ACPI, rather than attempting to graft DT atop.
> +config X86_APPENDED_DTB
> + bool "Use appended device tree blob to bzImage"
> + depends on OF
> + select OF_EARLY_FLATTREE
> + help
> + With this option, the boot code will look for a device tree binary
> + (DTB) appended to bzImage
> + (e.g. cat bzImage <filename>.dtb > bzImage_w_dtb).
> +
> + This is meant as a backward compatibility convenience for those
> + systems with a bootloader that can't be upgraded to accommodate
> + the documented boot protocol using a device tree.
> +
> + Beware that there is very little in terms of protection against
> + this option being confused by leftover garbage in memory that might
> + look like a DTB header after a reboot if no actual DTB is appended
> + to bzImage. Do not leave this option active in a production kernel
> + if you don't intend to always append a DTB.
I would advise that you reword this, as the existing wording is clearly
not applicable.
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [RFC V4 PATCH 1/6] arm64: dts: msm8992 SoC and LG Bullhead (Nexus 5X) support
From: Bjorn Andersson @ 2016-10-21 18:20 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm, linux-soc, devicetree, robh, andy.gross, sboyd,
arnd, mark.rutland, michael.scott
In-Reply-To: <1477048273-32451-2-git-send-email-jeremymc@redhat.com>
On Fri 21 Oct 04:11 PDT 2016, Jeremy McNicoll wrote:
> From: Jeremy McNicoll <jmcnicol@redhat.com>
>
> Initial device tree support for Qualcomm MSM8992 SoC and
> LG Bullhead / Google Nexus 5X support.
>
Looks reasonable, just two small nits below.
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 4 +-
> .../boot/dts/qcom/msm8992-bullhead-rev-101.dts | 42 ++++
> arch/arm64/boot/dts/qcom/msm8992-pins.dtsi | 38 ++++
> arch/arm64/boot/dts/qcom/msm8992.dtsi | 214 +++++++++++++++++++++
> 4 files changed, 296 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-bullhead-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8992.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index 5dd05de..abb366e 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -1,6 +1,6 @@
> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
> -dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
> -dtb-$(CONFIG_ARCH_QCOM) += apq8096-db820c.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb apq8096-db820c.dtb
Don't change these, just add yours.
[..]
> diff --git a/arch/arm64/boot/dts/qcom/msm8992.dtsi b/arch/arm64/boot/dts/qcom/msm8992.dtsi
[..]
> +
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
This device is not compatible with the msm8974 TLMM, so please drop the
second compatible.
> + reg = <0xfd510000 0x4000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
Regards,
Bjorn
^ permalink raw reply
* Re: [RFC V4 PATCH 5/6] arm64: dts: msm8994 SoC and Huawei Angler (Nexus 6P) support
From: Bjorn Andersson @ 2016-10-21 18:25 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm, linux-soc, devicetree, robh, andy.gross, sboyd,
arnd, mark.rutland, michael.scott
In-Reply-To: <1477048273-32451-6-git-send-email-jeremymc@redhat.com>
On Fri 21 Oct 04:11 PDT 2016, Jeremy McNicoll wrote:
> From: Bastian Köcher <mail@kchr.de>
>
> Initial device tree support for Qualcomm MSM8994 SoC and
> Huawei Angler / Google Nexus 6P support.
>
> The device tree is based on the Google 3.10 kernel tree.
>
> The device can be booted into the initrd with only one CPU running.
>
Looks reasonable as well, same two comments as the 8992 below.
> Signed-off-by: Bastian Köcher <mail@kchr.de>
> [jeremymc@redhat.com: removed Kconfig, defconfig, move from Huawei to qcom dir]
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
> arch/arm64/boot/dts/qcom/Makefile | 2 +-
> .../arm64/boot/dts/qcom/msm8994-angler-rev-101.dts | 42 ++++
> arch/arm64/boot/dts/qcom/msm8994-pins.dtsi | 38 ++++
> arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi | 32 +++
> arch/arm64/boot/dts/qcom/msm8994.dtsi | 236 +++++++++++++++++++++
> 5 files changed, 349 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-pins.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994-v2.0.dtsi
> create mode 100644 arch/arm64/boot/dts/qcom/msm8994.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile
> index abb366e..4040fc8 100644
> --- a/arch/arm64/boot/dts/qcom/Makefile
> +++ b/arch/arm64/boot/dts/qcom/Makefile
> @@ -1,6 +1,6 @@
> dtb-$(CONFIG_ARCH_QCOM) += apq8016-sbc.dtb msm8916-mtp.dtb
> dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb apq8096-db820c.dtb
> -dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
> +dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb msm8994-angler-rev-101.dtb
This won't scale, use multiple lines instead.
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
> new file mode 100644
> index 0000000..9684e6c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/msm8994-angler-rev-101.dts
> @@ -0,0 +1,42 @@
> +/* Copyright (c) 2015, Huawei Inc. All rights reserved.
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +/dts-v1/;
> +
> +#include "msm8994-v2.0.dtsi"
> +
> +/ {
> + model = "HUAWEI MSM8994 ANGLER rev-1.01";
> + compatible = "qcom,msm8994";
> + /* required for bootloader to select correct board */
> + qcom,board-id = <8026 0>;
> +};
> +
> +/ {
No need to close and reopen / {} here.
> + aliases {
> + serial0 = &blsp1_uart2;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + soc {
> + serial@f991e000 {
> + status = "okay";
> + pinctrl-names = "default", "sleep";
> + pinctrl-0 = <&blsp1_uart2_default>;
> + pinctrl-1 = <&blsp1_uart2_sleep>;
> + };
> + };
> +};
[..]
> diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
[..]
> + msmgpio: pinctrl@fd510000 {
> + compatible = "qcom,msm8994-pinctrl", "qcom,msm8974-pinctrl";
msm8974 TLMM won't work here either, so please drop that.
> + reg = <0xfd510000 0x4000>;
> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH v3 1/3] mtd: s3c2410: make ecc mode configurable via platform data
From: Krzysztof Kozlowski @ 2016-10-21 18:27 UTC (permalink / raw)
To: Sergio Prado
Cc: kgene, krzk, javier, linux, linux, boris.brezillon, richard,
dwmw2, computersforpeace, linux-arm-kernel, linux-samsung-soc,
linux-kernel, linux-mtd, robh+dt, mark.rutland, devicetree
In-Reply-To: <1476999766-32526-2-git-send-email-sergio.prado@e-labworks.com>
On Thu, Oct 20, 2016 at 07:42:44PM -0200, Sergio Prado wrote:
> Removing CONFIG_MTD_NAND_S3C2410_HWECC option and adding a ecc_mode
> field in the drivers's platform data structure so it can be selectable
> via platform data.
>
> Also setting this field to NAND_ECC_SOFT in all boards using this
> driver since none of them had CONFIG_MTD_NAND_S3C2410_HWECC enabled.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> ---
> arch/arm/mach-s3c24xx/common-smdk.c | 1 +
> arch/arm/mach-s3c24xx/mach-anubis.c | 1 +
> arch/arm/mach-s3c24xx/mach-at2440evb.c | 1 +
> arch/arm/mach-s3c24xx/mach-bast.c | 1 +
> arch/arm/mach-s3c24xx/mach-gta02.c | 1 +
> arch/arm/mach-s3c24xx/mach-jive.c | 1 +
> arch/arm/mach-s3c24xx/mach-mini2440.c | 1 +
> arch/arm/mach-s3c24xx/mach-osiris.c | 1 +
> arch/arm/mach-s3c24xx/mach-qt2410.c | 1 +
> arch/arm/mach-s3c24xx/mach-rx1950.c | 1 +
> arch/arm/mach-s3c24xx/mach-rx3715.c | 1 +
> arch/arm/mach-s3c24xx/mach-vstms.c | 1 +
> arch/arm/mach-s3c64xx/mach-hmt.c | 1 +
> arch/arm/mach-s3c64xx/mach-mini6410.c | 1 +
> arch/arm/mach-s3c64xx/mach-real6410.c | 1 +
> drivers/mtd/nand/Kconfig | 9 --
> drivers/mtd/nand/s3c2410.c | 119 +++++++++++++------------
> include/linux/platform_data/mtd-nand-s3c2410.h | 6 +-
> 18 files changed, 79 insertions(+), 70 deletions(-)
>
I acked this twice (v1 and v2)... and still you are ignoring them. I am
sorry, I am not gonna to ack this third time!
For v2 I acked also other patches but it it is not there as well...
BR,
Krzysztof
^ permalink raw reply
* Re: [RFC V4 PATCH 6/6] arm64: configs: enable configs for msm899(2/4) basic support
From: Bjorn Andersson @ 2016-10-21 18:27 UTC (permalink / raw)
To: Jeremy McNicoll
Cc: linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh-DgEjT+Ai2ygdnm+yROfE0A,
andy.gross-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
arnd-r2nGTMty4D4, mark.rutland-5wv7dgnIgG8,
michael.scott-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1477048273-32451-7-git-send-email-jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
On Fri 21 Oct 04:11 PDT 2016, Jeremy McNicoll wrote:
> From: Jeremy McNicoll <jmcnicol-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>
> Given the mimimal hardware support for msm899(2/4) currently.
> A few config options are needed to allow for continued
> development and booting.
>
> The following are needed for continued development and
> booting:
> -8x74 pinctrl for serial support
I don't have the datasheet for 899[24], but I don't think this is a good
idea. We need a 899[24] pinctrl driver for this.
> -Enable Global Glock Controller (gcc)
>
Regards,
Bjorn
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 0/5] Support for LEGO MINDSTORTMS EV3
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
This patch series adds support for LEGO MINDSTORTMS EV3[1]. This is a TI AM1808
based board.
This patch series has been tested working (along with some hacks to fix the
GPIOs) on an EV3.
There are still quite a few additional new drivers that need to be submitted
to get everything working. This patch series just adds support for the parts
that already have mainline kernel drivers.
I have a plan/driver in progress for many of the components[2], but I could use
some advice on a few particulars.
Bluetooth: This needs a driver to sequence a GPIO to take the Bluetooth chip
out of shutdown *after* the Bluetooth clock has been configured and started.
Is there a generic driver that can do this sort of thing? Or, if not, which
subsystem should the new driver go in?
Input and output ports: These ports are capable of hotplugging various devices,
such as sensors and motors. I have written a driver for these that can detect
most devices. I created a new subsystem for this called `lego-port`. However,
I am wondering if the existing phy or extcon subsystems might be a good fit for
this sort of thing.
[1]: http://mindstorms.lego.com
[2]: https://github.com/ev3dev/lego-linux-drivers/tree/master/evb
David Lechner (5):
ARM: davinci: Compile MMC in kernel
ARM: davinci: Don't append git rev to local version
ARM: davinci: enable gpio poweroff in default config
ARM: davinci: enable LEDs default-on trigger in default config
ARM: dts: Add LEGO MINDSTORTMS EV3 dts
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/lego-ev3.dts | 454 +++++++++++++++++++++++++++++++++
arch/arm/configs/davinci_all_defconfig | 8 +-
3 files changed, 462 insertions(+), 3 deletions(-)
create mode 100644 arch/arm/boot/dts/lego-ev3.dts
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/5] ARM: davinci: Compile MMC in kernel
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1477075018-20176-1-git-send-email-david@lechnology.com>
This changes the davinci default configuration to compile the davinci
MMC driver into the kernel. This allows booting from an SD card without
requiring an initrd containing the kernel module.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/configs/davinci_all_defconfig | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 58d04f1..a2f89a3 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -169,9 +169,9 @@ CONFIG_USB_MASS_STORAGE=m
CONFIG_USB_G_SERIAL=m
CONFIG_USB_G_PRINTER=m
CONFIG_USB_CDC_COMPOSITE=m
-CONFIG_MMC=m
+CONFIG_MMC=y
# CONFIG_MMC_BLOCK_BOUNCE is not set
-CONFIG_MMC_DAVINCI=m
+CONFIG_MMC_DAVINCI=y
CONFIG_NEW_LEDS=y
CONFIG_LEDS_CLASS=m
CONFIG_LEDS_GPIO=m
--
2.7.4
^ permalink raw reply related
* [PATCH 2/5] ARM: davinci: Don't append git rev to local version
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477075018-20176-1-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
In the davinci default configuration, don't append the git revision to
the local kernel version by. This seems like the more desirable default
value.
Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
---
arch/arm/configs/davinci_all_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index a2f89a3..9254609 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -1,3 +1,4 @@
+# CONFIG_LOCALVERSION_AUTO is not set
# CONFIG_SWAP is not set
CONFIG_SYSVIPC=y
CONFIG_POSIX_MQUEUE=y
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 3/5] ARM: davinci: enable gpio poweroff in default config
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477075018-20176-1-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
The gpio-poweroff driver is needed by LEGO MINDSTORMS EV3 (AM1808 based
board).
Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
---
arch/arm/configs/davinci_all_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 9254609..9d7f0bc 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -117,6 +117,8 @@ CONFIG_SPI_DAVINCI=m
CONFIG_PINCTRL_SINGLE=y
CONFIG_GPIO_SYSFS=y
CONFIG_GPIO_PCA953X=y
+CONFIG_POWER_RESET=y
+CONFIG_POWER_RESET_GPIO=y
CONFIG_WATCHDOG=y
CONFIG_DAVINCI_WATCHDOG=m
CONFIG_MFD_DM355EVM_MSP=y
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 4/5] ARM: davinci: enable LEDs default-on trigger in default config
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1477075018-20176-1-git-send-email-david@lechnology.com>
The LEDs default-on trigger is nice to have. For example, it can be used
to configure a LED as a power indicator.
Signed-off-by: David Lechner <david@lechnology.com>
---
arch/arm/configs/davinci_all_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
index 9d7f0bc..e380743 100644
--- a/arch/arm/configs/davinci_all_defconfig
+++ b/arch/arm/configs/davinci_all_defconfig
@@ -181,6 +181,7 @@ CONFIG_LEDS_GPIO=m
CONFIG_LEDS_TRIGGERS=y
CONFIG_LEDS_TRIGGER_TIMER=m
CONFIG_LEDS_TRIGGER_HEARTBEAT=m
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_OMAP=m
CONFIG_DMADEVICES=y
--
2.7.4
^ permalink raw reply related
* [PATCH 5/5] ARM: dts: Add LEGO MINDSTORTMS EV3 dts
From: David Lechner @ 2016-10-21 18:36 UTC (permalink / raw)
To: Kevin Hilman, Sekhar Nori
Cc: David Lechner, Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477075018-20176-1-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
This adds a device tree definition file for LEGO MINDSTORMS EV3.
What is working:
* Pin muxing
* MicroSD card reader
* UART on input port 1
What is partially working:
* Buttons - working after GPIO fix
* LEDs - working after GPIO fix
* Poweroff/reset - working after GPIO fix
* Flash memory - driver loads but can't read the block devices - this is
probably due to the fact that we are not able to configure the SPI to
use DMA via device tree
* EEPROM - there seems to be a hardware bug that causes the first byte
read to be corrupted - this can be worked around by adding an I2C stop
between writing the register and reading the data, but the at24 driver
does not have an option to do this
What is not working/to be added later:
* Display - waiting for "tiny DRM" to be mainlined
* Speaker - needs new PWM sound driver
* USB - waiting for OHCI and MUSB device tree support to be mainlined
* ADC - needs new iio driver
* GPIOs - broken because of recent changes to core gpio driver
* Bluetooth - needs new driver for sequencing power/enable/clock
* Input and output ports - need some sort of new phy or extcon driver
* Battery - needs new power supply driver (depends on ADC iio driver)
Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
---
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/lego-ev3.dts | 454 +++++++++++++++++++++++++++++++++++++++++
2 files changed, 456 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/lego-ev3.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index f80f5b7..5f91c1a 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -116,7 +116,8 @@ dtb-$(CONFIG_ARCH_CLPS711X) += \
dtb-$(CONFIG_ARCH_DAVINCI) += \
da850-lcdk.dtb \
da850-enbw-cmc.dtb \
- da850-evm.dtb
+ da850-evm.dtb \
+ lego-ev3.dtb
dtb-$(CONFIG_ARCH_DIGICOLOR) += \
cx92755_equinox.dtb
dtb-$(CONFIG_ARCH_EFM32) += \
diff --git a/arch/arm/boot/dts/lego-ev3.dts b/arch/arm/boot/dts/lego-ev3.dts
new file mode 100644
index 0000000..a6b4c7d
--- /dev/null
+++ b/arch/arm/boot/dts/lego-ev3.dts
@@ -0,0 +1,454 @@
+/*
+ * Device tree for LEGO MINDSTORMS EV3
+ *
+ * Copyright (C) 2016 David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation, version 2.
+ */
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/linux-event-codes.h>
+#include <dt-bindings/pwm/pwm.h>
+
+#include "da850.dtsi"
+
+/ {
+ compatible = "lego,ev3", "ti,da850";
+ model = "LEGO MINDSTORMS EV3";
+
+ soc@1c00000 {
+ /*
+ * (ab)using pinctrl-single to disable all internal pullups/
+ * pulldowns on I/O.
+ */
+ pinmux@22c00c {
+ compatible = "pinctrl-single";
+ reg = <0x22c00c 0x4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-single,bit-per-mux;
+ pinctrl-single,register-width = <32>;
+ pinctrl-single,function-mask = <0xf>;
+ /*
+ * There is a bug in pinctrl-single that prevents us
+ * from setting function-mask to 1, so doing things
+ * in groups of 4. Doesn't really matter since we are
+ * disabling all at once anyway.
+ */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pupu_disable>;
+
+ pupu_disable: pinmux_all_pins {
+ pinctrl-single,bits = <
+ 0x0 0x00000000 0xffffffff
+ >;
+ };
+ };
+ };
+
+ /*
+ * The buttons on the EV3 are mapped to keyboard keys.
+ */
+ gpio_keys {
+ compatible = "gpio-keys";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "EV3 buttons";
+ pinctrl-names = "default";
+ pinctrl-0 = <&button_pins>;
+
+ enter {
+ label = "EV3 Button ENTER";
+ linux,code = <KEY_ENTER>;
+ gpios = <&gpio 29 GPIO_ACTIVE_HIGH>;
+ };
+ left {
+ label = "EV3 Button LEFT";
+ linux,code = <KEY_LEFT>;
+ gpios = <&gpio 102 GPIO_ACTIVE_HIGH>;
+ };
+ back {
+ label = "EV3 Button BACK";
+ linux,code = <KEY_BACKSPACE>;
+ gpios = <&gpio 106 GPIO_ACTIVE_HIGH>;
+ };
+ right {
+ label = "EV3 Button RIGHT";
+ linux,code = <KEY_RIGHT>;
+ gpios = <&gpio 124 GPIO_ACTIVE_HIGH>;
+ };
+ down {
+ label = "EV3 Button DOWN";
+ linux,code = <KEY_DOWN>;
+ gpios = <&gpio 126 GPIO_ACTIVE_HIGH>;
+ };
+ up {
+ label = "EV3 Button UP";
+ linux,code = <KEY_UP>;
+ gpios = <&gpio 127 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ /*
+ * The EV3 has two built-in bi-color LEDs behind the buttons.
+ */
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&led_pins>;
+
+ left_red {
+ label = "led1:red:brick-status";
+ /* GP6[13] */
+ gpios = <&gpio 103 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ left_green {
+ label = "led1:green:brick-status";
+ /* GP6[7] */
+ gpios = <&gpio 108 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ right_red {
+ label = "led2:red:brick-status";
+ /* GP6[12] */
+ gpios = <&gpio 109 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ right_green {
+ label = "led2:green:brick-status";
+ /* GP6[14] */
+ gpios = <&gpio 110 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "default-on";
+ };
+ };
+
+ /*
+ * The EV3 is powered down by turning off the main 5V supply.
+ */
+ gpio-poweroff {
+ compatible = "gpio-poweroff";
+ /* low signal powers off the board */
+ gpios = <&gpio 107 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&system_power_pin>;
+ };
+
+ /*
+ * The Bluetooth chip requires a clock at 32768Hz. One of the PWMs
+ * is used to generate this signal.
+ */
+ bt-slow-clock {
+ status = "disabled";
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "slow_clk";
+ pwms = <&ecap2 0 30517>;
+ };
+};
+
+&pmx_core {
+ status = "okay";
+
+ spi0_cs3_pin: pinmux_spi0_cs3_pin {
+ pinctrl-single,bits = <
+ /* CS3 */
+ 0xc 0x01000000 0x0f000000
+ >;
+ };
+ mmc0_cd_pin: pinmux_mmc0_cd {
+ pinctrl-single,bits = <
+ /* GP5[14] */
+ 0x2C 0x00000080 0x000000f0
+ >;
+ };
+ button_pins: pinmux_button_pins {
+ pinctrl-single,bits = <
+ /* GP1[13] */
+ 0x8 0x00000800 0x00000f00
+ /* GP6[10] */
+ 0x34 0x00800000 0x00f00000
+ /* GP6[6] */
+ 0x38 0x00000080 0x000000f0
+ /* GP7[12], GP7[14], GP7[15] */
+ 0x40 0x00808800 0x00f0ff00
+ >;
+ };
+ led_pins: pinmux_led_pins {
+ pinctrl-single,bits = <
+ /* GP6[12], GP6[13], GP6[14] */
+ 0x34 0x00008880 0x0000fff0
+ /* GP6[7] */
+ 0x38 0x00000008 0x0000000f
+ >;
+ };
+ system_power_pin: pinmux_system_power {
+ pinctrl-single,bits = <
+ /* GP6[11] */
+ 0x34 0x00080000 0x000f0000
+ >;
+ };
+ in1_pins: pinmux_in1_pins {
+ pinctrl-single,bits = <
+ /* GP0[15] */
+ 0x0 0x00000008 0x0000000f
+ /* GP0[2] */
+ 0x4 0x00800000 0x00f00000
+ /* GP2[2] */
+ 0x18 0x00800000 0x00f00000
+ /* GP8[10], GP8[11] */
+ 0x48 0x88000000 0xff000000
+ >;
+ };
+ in2_pins: pinmux_in2_pins {
+ pinctrl-single,bits = <
+ /* GP0[13], GP0[14] */
+ 0x0 0x00000880 0x00000ff0
+ /* GP8[12], GP8[14], GP8[15] */
+ 0x48 0x00808800 0x00f0ff00
+ >;
+ };
+ in3_pins: pinmux_in3_pins {
+ pinctrl-single,bits = <
+ /* GP0[12] */
+ 0x0 0x00008000 0x0000f000
+ /* GP1[14] */
+ 0x8 0x00000080 0x000000f0
+ /* GP7[11] */
+ 0x40 0x08000000 0x0f000000
+ /* GP7[9] */
+ 0x44 0x00000008 0x0000000f
+ /* GP8[9] */
+ 0x4c 0x00000008 0x0000000f
+ >;
+ };
+ in4_pins: pinmux_in4_pins {
+ pinctrl-single,bits = <
+ /* GP0[1] */
+ 0x4 0x08000000 0x0f000000
+ /* GP1[15] */
+ 0x8 0x00000008 0x0000000f
+ /* GP7[10] */
+ 0x40 0x80000000 0xf0000000
+ /* GP7[8] */
+ 0x44 0x00000080 0x000000f0
+ /* GP6[4] */
+ 0x4c 0x00000800 0x00000f00
+ >;
+ };
+ outa_pins: pinmux_outa_pins {
+ pinctrl-single,bits = <
+ /* GP0[4] */
+ 0x4 0x00008000 0x0000f000
+ /* GP3[15] */
+ 0x1c 0x00000008 0x0000000f
+ /* GP3[6] */
+ 0x20 0x00000080 0x000000f0
+ /* GP5[11] */
+ 0x2c 0x00080000 0x000f0000
+ /* GP5[4] */
+ 0x30 0x00008000 0x0000f000
+ >;
+ };
+ outb_pins: pinmux_outb_pins {
+ pinctrl-single,bits = <
+ /* GP0[3] */
+ 0x4 0x00080000 0x000f0000
+ /* GP2[9] */
+ 0x14 0x08000000 0x0f000000
+ /* GP2[1], GP2[5] */
+ 0x18 0x08000800 0x0f000f00
+ /* GP5[11] */
+ 0x2c 0x80000000 0xf0000000
+ >;
+ };
+ outc_pins: pinmux_outc_pins {
+ pinctrl-single,bits = <
+ /* GP3[8], GP3[14] */
+ 0x1c 0x80000080 0xf00000f0
+ /* GP5[9], GP5[13] */
+ 0x2c 0x08000800 0x0f000f00
+ /* GP6[8] */
+ 0x34 0x80000000 0xf0000000
+ >;
+ };
+ outd_pins: pinmux_outd_pins {
+ pinctrl-single,bits = <
+ /* GP2[8] */
+ 0x14 0x80000000 0xf0000000
+ /* GP5[10], GP5[15] */
+ 0x2c 0x00800008 0x00f0000f
+ /* GP5[3] */
+ 0x30 0x00080000 0x000f0000
+ /* GP6[9] */
+ 0x34 0x08000000 0x0f000000
+ >;
+ };
+ sound_pins: pinmux_sound_pins {
+ pinctrl-single,bits = <
+ /* GP6[15] */
+ 0x34 0x00000008 0x0000000f
+ >;
+ };
+ usb11_pins: pinmux_usb11_pins {
+ pinctrl-single,bits = <
+ /* GP6[5] */
+ 0x40 0x00000080 0x000000f0
+ /* GP6[3] */
+ 0x4c 0x00008000 0x0000f000
+ >;
+ };
+};
+
+/* Input port 2 */
+&serial0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial0_rxtx_pins>;
+};
+
+/* Input port 1 */
+&serial1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial1_rxtx_pins>;
+};
+
+/* Bluetooth */
+&serial2 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&serial2_rxtx_pins>, <&serial2_rtscts_pins>;
+};
+
+&rtc0 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+
+ /*
+ * EEPROM contains the first stage bootloader, HW ID and Bluetooth MAC.
+ */
+ eeprom@50 {
+ compatible = "at24,24c128";
+ pagesize = <64>;
+ read-only;
+ reg = <0x50>;
+ };
+};
+
+&wdt {
+ status = "okay";
+};
+
+&mmc0 {
+ status = "okay";
+ max-frequency = <50000000>;
+ bus-width = <4>;
+ cd-gpios = <&gpio 94 GPIO_ACTIVE_LOW>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>, <&mmc0_cd_pin>;
+};
+
+&ehrpwm0 {
+ status = "okay";
+ pinctrl-names = "default";
+ /* SOUND_ARMA */
+ pinctrl-0 = <&ehrpwm0b_pins>;
+};
+
+&ehrpwm1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ /* MBPWM, MAPWM */
+ pinctrl-0 = <&ehrpwm1a_pins>, <&ehrpwm1b_pins>;
+};
+
+&ecap0 {
+ status = "okay";
+ pinctrl-names = "default";
+ /* MCPWM */
+ pinctrl-0 = <&ecap0_pins>;
+};
+
+&ecap1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ /* MDPWM */
+ pinctrl-0 = <&ecap1_pins>;
+};
+
+&ecap2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ /* BTSLOWCLK */
+ pinctrl-0 = <&ecap2_pins>;
+};
+
+&spi0 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>;
+ dmas = <&edma0 14 0>, <&edma0 15 0>;
+ dma-names = "rx", "tx";
+
+ spi-flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "n25q128a13", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ ti,spi-wdelay = <8>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x40000>;
+ };
+
+ partition@40000 {
+ label = "U-Boot Env";
+ reg = <0x40000 0x10000>;
+ };
+
+ partition@50000 {
+ label = "Kernel";
+ reg = <0x50000 0x200000>;
+ };
+
+ partition@250000 {
+ label = "Filesystem";
+ reg = <0x250000 0xa50000>;
+ };
+
+ partition@cb0000 {
+ label = "Storage";
+ reg = <0xcb0000 0x2f0000>;
+ };
+ };
+
+ /* TODO: ADC goes here */
+};
+
+&spi1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
+
+ /* TODO: LCD Display goes here */
+};
+
+&gpio {
+ status = "okay";
+};
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 0/5] Support for LEGO MINDSTORTMS EV3
From: Lennart Sorensen @ 2016-10-21 18:45 UTC (permalink / raw)
To: David Lechner
Cc: Kevin Hilman, Sekhar Nori, Rob Herring, Mark Rutland,
Russell King, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <1477075018-20176-1-git-send-email-david@lechnology.com>
On Fri, Oct 21, 2016 at 01:36:52PM -0500, David Lechner wrote:
> This patch series adds support for LEGO MINDSTORTMS EV3[1]. This is a TI AM1808
> based board.
>
> This patch series has been tested working (along with some hacks to fix the
> GPIOs) on an EV3.
>
> There are still quite a few additional new drivers that need to be submitted
> to get everything working. This patch series just adds support for the parts
> that already have mainline kernel drivers.
>
> I have a plan/driver in progress for many of the components[2], but I could use
> some advice on a few particulars.
>
> Bluetooth: This needs a driver to sequence a GPIO to take the Bluetooth chip
> out of shutdown *after* the Bluetooth clock has been configured and started.
> Is there a generic driver that can do this sort of thing? Or, if not, which
> subsystem should the new driver go in?
>
> Input and output ports: These ports are capable of hotplugging various devices,
> such as sensors and motors. I have written a driver for these that can detect
> most devices. I created a new subsystem for this called `lego-port`. However,
> I am wondering if the existing phy or extcon subsystems might be a good fit for
> this sort of thing.
Both this cover and patch 5/5 has MINDSTORTMS instead of MINDSTORMS in
a few places (including the subject line).
--
Len Sorensen
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox