* Re: [PATCH] ARM: dts: vf610: fix IRQ flag of global timer
From: Shawn Guo @ 2016-10-24 12:06 UTC (permalink / raw)
To: Stefan Agner; +Cc: kernel, devicetree, linux-arm-kernel, linux-kernel
In-Reply-To: <20161018015127.16981-1-stefan@agner.ch>
On Mon, Oct 17, 2016 at 06:51:27PM -0700, Stefan Agner wrote:
> The global timer IRQ (PPI[0], PPI 11 in device tree terms) is a
> rising edge interrupt. The ARM Cortex-A5 MPCore TRM in Chapter
> 10.1.2. Interrupt types and sources says:
> "Interrupt is rising-edge sensitive."
>
> The bits seem to be read-only, hence this missconfiguration had
> no negative effect. However, with commit 992345a58e0c
> ("irqchip/gic: WARN if setting the interrupt type for a PPI fails")
> warnings such as this get printed:
> GIC: PPI11 is secure or misconfigured
>
> With this change the new configuration matches the default
> configuration and no warning is printed anymore.
>
> Signed-off-by: Stefan Agner <stefan@agner.ch>
Applied, thanks.
^ permalink raw reply
* Re: [PATCH v4 1/2] ARM: dts: imx6ul: Add DTS for liteSOM module
From: Shawn Guo @ 2016-10-24 12:15 UTC (permalink / raw)
To: Marcin Niestroj
Cc: Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
Sascha Hauer, Fabio Estevam,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161021150717.27573-1-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
On Fri, Oct 21, 2016 at 05:07:16PM +0200, Marcin Niestroj wrote:
> This is a SOM (System on Module), so it will be part of another boards.
> Hence, this is a "dtsi" file that will be included from another device
> tree files.
>
> Hardware specification:
> * Freescale i.MX6UL SoC
> * up to 512 MB RAM
> * eMMC on uSDHC2
>
> Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
> Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
Applied both, thanks.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 02/23] of: device: Export of_device_{get_modalias, uvent_modalias} to modules
From: Chen-Yu Tsai @ 2016-10-24 12:19 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-usb, Felipe Balbi, Arnd Bergmann, Neil Armstrong,
linux-arm-msm, linux-kernel, Bjorn Andersson, devicetree,
Peter Chen, Andy Gross, linux-arm-kernel
In-Reply-To: <20161018015636.11701-3-stephen.boyd@linaro.org>
Hi,
On Tue, Oct 18, 2016 at 9:56 AM, Stephen Boyd <stephen.boyd@linaro.org> wrote:
> The ULPI bus can be built as a module, and it will soon be
> calling these functions when it supports probing devices from DT.
> Export them so they can be used by the ULPI module.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Cc: <devicetree@vger.kernel.org>
> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
> ---
> drivers/of/device.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/of/device.c b/drivers/of/device.c
> index 8a22a253a830..6719ab35b62e 100644
> --- a/drivers/of/device.c
> +++ b/drivers/of/device.c
> @@ -225,6 +225,7 @@ ssize_t of_device_get_modalias(struct device *dev, char *str, ssize_t len)
>
> return tsize;
> }
> +EXPORT_SYMBOL_GPL(of_device_get_modalias);
>
> int of_device_request_module(struct device *dev)
> {
> @@ -290,6 +291,7 @@ void of_device_uevent(struct device *dev, struct kobj_uevent_env *env)
> }
> mutex_unlock(&of_mutex);
> }
> +EXPORT_SYMBOL_GPL(of_device_uevent_modalias);
This is trailing the wrong function.
ChenYu
>
> int of_device_uevent_modalias(struct device *dev, struct kobj_uevent_env *env)
> {
> --
> 2.10.0.297.gf6727b0
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [v7, 1/3] nand: pl353: Add basic driver for arm pl353 smc nand interface
From: Boris Brezillon @ 2016-10-24 12:27 UTC (permalink / raw)
To: punnaiah choudary kalluri
Cc: Jason Gunthorpe, Punnaiah Choudary Kalluri, mark.rutland@arm.com,
jussi.kivilinna@iki.fi, linux-doc@vger.kernel.org,
artem.bityutskiy@linux.intel.com, linux-mtd@lists.infradead.org,
arnd@arndb.de, michal.simek@xilinx.com,
ezequiel.garcia@free-electrons.com, grant.likely@linaro.org,
devicetree@vger.kernel.org, jason@lakedaemon.net,
pawel.moll@arm.com
In-Reply-To: <CAGnW=Bb-pnJ9-xjcw-1dR-y+oKjNs53bgD+dh1LwsMTCmzdRmQ@mail.gmail.com>
Hi Punnaih,
On Sun, 23 Oct 2016 17:37:42 +0530
punnaiah choudary kalluri <punnaia@xilinx.com> wrote:
> Hi Boris and Jason,
>
> I am doing rework on these patches to accommodate recent changes with
> respect to ooblayout. Also some of the comments that i have received
> from Boris as part of the arasan nand controller upstream patches will
> apply to this driver. So, i will be releasing the next set of patches for this
> driver soon and request your time for reviewing those patches.
>
> for now, please ignore these patches.
OK. Thanks for the heads up. I'll wait for your new version.
Regards,
Boris
^ permalink raw reply
* Re: [PATCH v5 4/7] ASoC: sunxi: Add sun8i I2S driver
From: Maxime Ripard @ 2016-10-24 12:34 UTC (permalink / raw)
To: Jean-Francois Moine
Cc: Chen-Yu Tsai, Dave Airlie, Liam Girdwood, Mark Brown, Rob Herring,
Linux-ALSA, devicetree, dri-devel, linux-arm-kernel, linux-sunxi
In-Reply-To: <20161023094503.fbb22dd0701e3f2785828609-GANU6spQydw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1187 bytes --]
Hi,
On Sun, Oct 23, 2016 at 09:45:03AM +0200, Jean-Francois Moine wrote:
> On Sun, 23 Oct 2016 09:33:16 +0800
> Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org> wrote:
>
> > > Note: This driver is closed to the sun4i-i2s except that:
> > > - it handles the H3
> >
> > If it's close to sun4i-i2s, you should probably rework that one to support
> > the newer SoCs.
> >
> > > - it creates the sound card (with sun4i-i2s, the sound card is created
> > > by the CODECs)
> >
> > I think this is wrong. I2S is only the DAI. You typically have a separate
> > platform driver for the whole card, or just use simple-card.
>
> An other device is not needed. The layout is simple:
> I2S_controller (CPU DAI) <-> HDMI_CODEC (CODEC DAI)
> The HDMI CODEC is supported by the HDMI video driver (only one device),
> so, it cannot be the card device.
> ASoC does not use the CPU DAI device (I2S_controller), so, it is
> natural to use it to handle the card.
Still, duplicating the driver is not the solution. I agree with
Chen-Yu that we want to leverage the driver that is already there.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Ding Tianhong @ 2016-10-24 12:40 UTC (permalink / raw)
To: Mark Rutland
Cc: devicetree, Marc Zyngier, Catalin Marinas, Will Deacon,
stuart.yoder, Scott Wood, Shawn Guo, linux-arm-kernel
In-Reply-To: <20161024111608.GG15620@leverpostej>
On 2016/10/24 19:16, Mark Rutland wrote:
> On Sun, Oct 23, 2016 at 11:21:10AM +0800, Ding Tianhong wrote:
>> +- hisilicon,erratum-161x01 : A boolean property. Indicates the presence of
>> + QorIQ erratum 161201, which says that reading the counter is
>> + unreliable unless the small range of value is returned by back-to-back reads.
>> + This also affects writes to the tval register, due to the implicit
>> + counter read.
>
> Is "161x01" the *exact* erratum number, or is the 'x' a wildcard? Please
> use the *exact* erratum number, even if that means we have to list
> several.
>
Hi Mark:
The 'x' is a wildcard, it will cover 161001 to 161601 several numbers, I will discuss to
the chip develop and get a exact erratum number.
Thanks.
Ding
> Is "161x01" an *erratum* number, or the *part* number of affected
> devices?
>
> Thanks,
> Mark.
>
> .
>
^ permalink raw reply
* Re: [PATCH v3 3/3] mtd: s3c2410: parse the device configuration from OF node
From: Boris Brezillon @ 2016-10-24 13:02 UTC (permalink / raw)
To: Sergio Prado
Cc: kgene-DgEjT+Ai2ygdnm+yROfE0A, krzk-DgEjT+Ai2ygdnm+yROfE0A,
javier-JPH+aEBZ4P+UEJcrhfAQsw, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-Y5A6D6n0/KfQXOPxS62xeg, richard-/L3Ra7n9ekc,
dwmw2-wEGCiKHe2LqWVfeAwA7xHQ,
computersforpeace-Re5JQEeQqe8AvxtiuMwx3w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1476999766-32526-4-git-send-email-sergio.prado-1e4yhPs3/ABSwrhanM7KvQ@public.gmane.org>
On Thu, 20 Oct 2016 19:42:46 -0200
Sergio Prado <sergio.prado-1e4yhPs3/ABSwrhanM7KvQ@public.gmane.org> wrote:
> Allows configuring Samsung's s3c2410 memory controller using a
> devicetree.
>
> Signed-off-by: Sergio Prado <sergio.prado-1e4yhPs3/ABSwrhanM7KvQ@public.gmane.org>
> ---
> drivers/mtd/nand/s3c2410.c | 158 ++++++++++++++++++++++---
> include/linux/platform_data/mtd-nand-s3c2410.h | 1 +
> 2 files changed, 143 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/mtd/nand/s3c2410.c b/drivers/mtd/nand/s3c2410.c
> index 371db0d48135..ec170be881bc 100644
> --- a/drivers/mtd/nand/s3c2410.c
> +++ b/drivers/mtd/nand/s3c2410.c
> @@ -39,6 +39,8 @@
> #include <linux/slab.h>
> #include <linux/clk.h>
> #include <linux/cpufreq.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
>
> #include <linux/mtd/mtd.h>
> #include <linux/mtd/nand.h>
> @@ -185,6 +187,22 @@ struct s3c2410_nand_info {
> #endif
> };
>
> +struct s3c24XX_nand_devtype_data {
> + enum s3c_cpu_type type;
> +};
> +
> +static const struct s3c24XX_nand_devtype_data s3c2410_nand_devtype_data = {
> + .type = TYPE_S3C2410,
> +};
> +
> +static const struct s3c24XX_nand_devtype_data s3c2412_nand_devtype_data = {
> + .type = TYPE_S3C2412,
> +};
> +
> +static const struct s3c24XX_nand_devtype_data s3c2440_nand_devtype_data = {
> + .type = TYPE_S3C2440,
> +};
> +
> /* conversion functions */
>
> static struct s3c2410_nand_mtd *s3c2410_nand_mtd_toours(struct mtd_info *mtd)
> @@ -794,6 +812,30 @@ static int s3c2410_nand_add_partition(struct s3c2410_nand_info *info,
> return -ENODEV;
> }
>
> +static int s3c2410_nand_setup_data_interface(struct mtd_info *mtd,
> + const struct nand_data_interface *conf,
> + bool check_only)
> +{
> + struct s3c2410_nand_info *info = s3c2410_nand_mtd_toinfo(mtd);
> + struct s3c2410_platform_nand *pdata = info->platform;
> + const struct nand_sdr_timings *timings;
> + int tacls;
> +
> + timings = nand_get_sdr_timings(conf);
> + if (IS_ERR(timings))
> + return -ENOTSUPP;
> +
> + tacls = timings->tCLS_min - timings->tWP_min;
> + if (tacls < 0)
> + tacls = 0;
> +
> + pdata->tacls = DIV_ROUND_UP(tacls, 1000);
> + pdata->twrph0 = DIV_ROUND_UP(timings->tWP_min, 1000);
> + pdata->twrph1 = DIV_ROUND_UP(timings->tCLH_min, 1000);
You seem to only apply the timings in s3c2410_nand_setrate(), which is
only called at probe time or on a cpufreq even, but the core can change
timings at runtime (this is what happens each time you reset the chip).
To support that you have 2 options:
- apply the timings in ->select_chip()
- apply the timings here
> +
> + return 0;
> +}
> +
> /**
> * s3c2410_nand_init_chip - initialise a single instance of an chip
> * @info: The base NAND controller the chip is on.
> @@ -808,9 +850,12 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
> struct s3c2410_nand_mtd *nmtd,
> struct s3c2410_nand_set *set)
> {
> + struct device_node *np = info->device->of_node;
> struct nand_chip *chip = &nmtd->chip;
> void __iomem *regs = info->regs;
>
> + nand_set_flash_node(chip, set->of_node);
> +
> chip->write_buf = s3c2410_nand_write_buf;
> chip->read_buf = s3c2410_nand_read_buf;
> chip->select_chip = s3c2410_nand_select_chip;
> @@ -819,6 +864,13 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
> chip->options = set->options;
> chip->controller = &info->controller;
>
> + /*
> + * let's keep behavior unchanged for legacy boards booting via pdata and
> + * auto-detect timings only when booting with a device tree.
> + */
> + if (np)
> + chip->setup_data_interface = s3c2410_nand_setup_data_interface;
> +
> switch (info->cpu_type) {
> case TYPE_S3C2410:
> chip->IO_ADDR_W = regs + S3C2410_NFDATA;
> @@ -859,12 +911,9 @@ static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info,
> chip->ecc.mode = info->platform->ecc_mode;
>
> /* If you use u-boot BBT creation code, specifying this flag will
> - * let the kernel fish out the BBT from the NAND, and also skip the
> - * full NAND scan that can take 1/2s or so. Little things... */
> - if (set->flash_bbt) {
> + * let the kernel fish out the BBT from the NAND */
> + if (set->flash_bbt)
> chip->bbt_options |= NAND_BBT_USE_FLASH;
> - chip->options |= NAND_SKIP_BBTSCAN;
> - }
> }
>
> /**
> @@ -943,6 +992,77 @@ static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
> return -EINVAL;
> }
>
> + if (chip->bbt_options & NAND_BBT_USE_FLASH)
> + chip->options |= NAND_SKIP_BBTSCAN;
> +
> + return 0;
> +}
> +
> +static const struct of_device_id s3c24xx_nand_dt_ids[] = {
> + {
> + .compatible = "samsung,s3c2410-nand",
> + .data = &s3c2410_nand_devtype_data,
> + }, {
> + .compatible = "samsung,s3c2412-nand", /* also compatible with s3c6400 */
> + .data = &s3c2412_nand_devtype_data,
> + }, {
> + .compatible = "samsung,s3c2440-nand",
> + .data = &s3c2440_nand_devtype_data,
> + },
> + { /* sentinel */ }
> +};
> +MODULE_DEVICE_TABLE(of, s3c24xx_nand_dt_ids);
> +
> +static int s3c24xx_nand_probe_dt(struct platform_device *pdev)
> +{
> + const struct s3c24XX_nand_devtype_data *devtype_data;
> + struct s3c2410_platform_nand *pdata;
> + struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
> + struct device_node *np = pdev->dev.of_node, *child;
> + struct s3c2410_nand_set *sets;
> +
> + devtype_data = of_device_get_match_data(&pdev->dev);
> + if (!devtype_data)
> + return -ENODEV;
> +
> + info->cpu_type = devtype_data->type;
> +
> + pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
> + if (!pdata)
> + return -ENOMEM;
> +
> + pdev->dev.platform_data = pdata;
> +
> + pdata->nr_sets = of_get_child_count(np);
> + if (!pdata->nr_sets)
> + return 0;
> +
> + sets = devm_kzalloc(&pdev->dev, sizeof(*sets) * pdata->nr_sets, GFP_KERNEL);
> + if (!sets)
> + return -ENOMEM;
> +
> + pdata->sets = sets;
> +
> + for_each_available_child_of_node(np, child) {
> +
> + sets->name = (char *)child->name;
> + sets->of_node = child;
> + sets->nr_chips = 1;
> +
> + of_node_get(child);
> +
> + sets++;
> + }
> +
> + return 0;
> +}
> +
> +static int s3c24xx_nand_probe_pdata(struct platform_device *pdev)
> +{
> + struct s3c2410_nand_info *info = platform_get_drvdata(pdev);
> +
> + info->cpu_type = platform_get_device_id(pdev)->driver_data;
> +
> return 0;
> }
>
> @@ -955,8 +1075,7 @@ static int s3c2410_nand_update_chip(struct s3c2410_nand_info *info,
> */
> static int s3c24xx_nand_probe(struct platform_device *pdev)
> {
> - struct s3c2410_platform_nand *plat = to_nand_plat(pdev);
> - enum s3c_cpu_type cpu_type;
> + struct s3c2410_platform_nand *plat;
> struct s3c2410_nand_info *info;
> struct s3c2410_nand_mtd *nmtd;
> struct s3c2410_nand_set *sets;
> @@ -966,8 +1085,6 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
> int nr_sets;
> int setno;
>
> - cpu_type = platform_get_device_id(pdev)->driver_data;
> -
> info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
> if (info == NULL) {
> err = -ENOMEM;
> @@ -989,6 +1106,16 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
>
> s3c2410_nand_clk_set_state(info, CLOCK_ENABLE);
>
> + if (pdev->dev.of_node)
> + err = s3c24xx_nand_probe_dt(pdev);
> + else
> + err = s3c24xx_nand_probe_pdata(pdev);
> +
> + if (err)
> + goto exit_error;
> +
> + plat = to_nand_plat(pdev);
> +
> /* allocate and map the resource */
>
> /* currently we assume we have the one resource */
> @@ -997,7 +1124,6 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
>
> info->device = &pdev->dev;
> info->platform = plat;
> - info->cpu_type = cpu_type;
>
> info->regs = devm_ioremap_resource(&pdev->dev, res);
> if (IS_ERR(info->regs)) {
> @@ -1007,12 +1133,6 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
>
> dev_dbg(&pdev->dev, "mapped registers at %p\n", info->regs);
>
> - /* initialise the hardware */
> -
> - err = s3c2410_nand_inithw(info);
> - if (err != 0)
> - goto exit_error;
> -
> sets = (plat != NULL) ? plat->sets : NULL;
> nr_sets = (plat != NULL) ? plat->nr_sets : 1;
>
> @@ -1056,6 +1176,11 @@ static int s3c24xx_nand_probe(struct platform_device *pdev)
> sets++;
> }
>
> + /* initialise the hardware */
> + err = s3c2410_nand_inithw(info);
> + if (err != 0)
> + goto exit_error;
> +
> err = s3c2410_nand_cpufreq_register(info);
> if (err < 0) {
> dev_err(&pdev->dev, "failed to init cpufreq support\n");
> @@ -1156,6 +1281,7 @@ static int s3c24xx_nand_resume(struct platform_device *dev)
> .id_table = s3c24xx_driver_ids,
> .driver = {
> .name = "s3c24xx-nand",
> + .of_match_table = s3c24xx_nand_dt_ids,
> },
> };
>
> diff --git a/include/linux/platform_data/mtd-nand-s3c2410.h b/include/linux/platform_data/mtd-nand-s3c2410.h
> index 729af13d1773..f01659026b26 100644
> --- a/include/linux/platform_data/mtd-nand-s3c2410.h
> +++ b/include/linux/platform_data/mtd-nand-s3c2410.h
> @@ -40,6 +40,7 @@ struct s3c2410_nand_set {
> char *name;
> int *nr_map;
> struct mtd_partition *partitions;
> + struct device_node *of_node;
> };
>
> struct s3c2410_platform_nand {
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Mark Rutland @ 2016-10-24 13:16 UTC (permalink / raw)
To: Ding Tianhong
Cc: Catalin Marinas, Will Deacon, Marc Zyngier, Scott Wood,
devicetree-u79uwXL29TY76Z2rM5mHXA, Shawn Guo,
stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <7e839df8-f8f7-3b16-8321-4ff45b6c5884-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On Mon, Oct 24, 2016 at 08:40:01PM +0800, Ding Tianhong wrote:
> On 2016/10/24 19:16, Mark Rutland wrote:
> > Is "161x01" the *exact* erratum number, or is the 'x' a wildcard?
>
> The 'x' is a wildcard, it will cover 161001 to 161601 several numbers,
Given you're using a wildcard, I take it that this is a *part* number?
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 3/7] drm: sunxi: add DE2 HDMI support
From: Maxime Ripard @ 2016-10-24 13:17 UTC (permalink / raw)
To: Jean-Francois Moine
Cc: Dave Airlie, Liam Girdwood, Mark Brown, Rob Herring,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <36bd5454897c8ab77749e0294e4a4ecc2450dd12.1477142934.git.moinejf-GANU6spQydw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 676 bytes --]
Hi,
On Fri, Oct 21, 2016 at 10:08:06AM +0200, Jean-Francois Moine wrote:
> This patch adds a HDMI driver to the DE2 based Allwinner's SoCs
> as A83T and H3.
> Audio and video are supported.
>
> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
Output from checkpatch:
total: 26 errors, 31 warnings, 70 checks, 1458 lines checked
Please run checkpatch before sending your patches.
Apart from that, this looks an awful lot like the designware HDMI
controller, for which a driver already exists. Any reason to create a
new driver from scratch?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Ding Tianhong @ 2016-10-24 13:23 UTC (permalink / raw)
To: Mark Rutland
Cc: Catalin Marinas, Will Deacon, Marc Zyngier, Scott Wood,
devicetree-u79uwXL29TY76Z2rM5mHXA, Shawn Guo,
stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161024131617.GJ15620@leverpostej>
On 2016/10/24 21:16, Mark Rutland wrote:
> On Mon, Oct 24, 2016 at 08:40:01PM +0800, Ding Tianhong wrote:
>> On 2016/10/24 19:16, Mark Rutland wrote:
>>> Is "161x01" the *exact* erratum number, or is the 'x' a wildcard?
>>
>> The 'x' is a wildcard, it will cover 161001 to 161601 several numbers,
>
> Given you're using a wildcard, I take it that this is a *part* number?
>
Yes, I was doubt how to fix this, should I choose a better erratum number?
> Thanks,
> Mark.
>
> .
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] dmaengine: nbpfaxi: add optional max-burst property for memory reads/writes
From: Niklas Cassel @ 2016-10-24 13:29 UTC (permalink / raw)
To: vinod.koul, robh+dt, mark.rutland, dan.j.williams
Cc: dmaengine, devicetree, linux-kernel, Niklas Cassel
From: Niklas Cassel <niklas.cassel@axis.com>
Due to a hardware bug, reading memory (from the Accelerator Coherency Port)
with a burst size equal to the maximum burst size allowed by the DMA
hardware's buffer size will cause a hardware hang on the ARTPEC-6 SoC,
where the only solution is a manual power cycle.
On ARTPEC-6, this hardware bug does not trigger when writing memory (to the
Accelerator Coherency Port) with a burst size equal to the maximum burst
size allowed by the DMA hardware's buffer size.
To avoid this hardware hang, introduce a new optional max-burst property
for memory reads. For completeness, also introduce a max-burst property for
memory writes.
Signed-off-by: Niklas Cassel <niklas.cassel@axis.com>
---
Documentation/devicetree/bindings/dma/nbpfaxi.txt | 8 +++++
drivers/dma/nbpfaxi.c | 38 ++++++++++++++++++++---
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/nbpfaxi.txt b/Documentation/devicetree/bindings/dma/nbpfaxi.txt
index d5e2522b9ec1..d2e1e62e346a 100644
--- a/Documentation/devicetree/bindings/dma/nbpfaxi.txt
+++ b/Documentation/devicetree/bindings/dma/nbpfaxi.txt
@@ -23,6 +23,14 @@ Required properties
#define NBPF_SLAVE_RQ_LEVEL 4
Optional properties:
+- max-burst-mem-read: limit burst size for memory reads
+ (DMA_MEM_TO_MEM/DMA_MEM_TO_DEV) to this value, specified in bytes, rather
+ than using the maximum burst size allowed by the hardware's buffer size.
+- max-burst-mem-write: limit burst size for memory writes
+ (DMA_DEV_TO_MEM/DMA_MEM_TO_MEM) to this value, specified in bytes, rather
+ than using the maximum burst size allowed by the hardware's buffer size.
+ If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
+ will use the lower value.
You can use dma-channels and dma-requests as described in dma.txt, although they
won't be used, this information is derived from the compatibility string.
diff --git a/drivers/dma/nbpfaxi.c b/drivers/dma/nbpfaxi.c
index 09de71519d37..3f45b9bdf201 100644
--- a/drivers/dma/nbpfaxi.c
+++ b/drivers/dma/nbpfaxi.c
@@ -225,6 +225,8 @@ struct nbpf_channel {
struct nbpf_device {
struct dma_device dma_dev;
void __iomem *base;
+ u32 max_burst_mem_read;
+ u32 max_burst_mem_write;
struct clk *clk;
const struct nbpf_config *config;
unsigned int eirq;
@@ -425,10 +427,33 @@ static void nbpf_chan_configure(struct nbpf_channel *chan)
nbpf_chan_write(chan, NBPF_CHAN_CFG, NBPF_CHAN_CFG_DMS | chan->dmarq_cfg);
}
-static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size)
+static u32 nbpf_xfer_ds(struct nbpf_device *nbpf, size_t size,
+ enum dma_transfer_direction direction)
{
+ int max_burst = nbpf->config->buffer_size * 8;
+
+ if (nbpf->max_burst_mem_read || nbpf->max_burst_mem_write) {
+ switch (direction) {
+ case DMA_MEM_TO_MEM:
+ max_burst = min_not_zero(nbpf->max_burst_mem_read,
+ nbpf->max_burst_mem_write);
+ break;
+ case DMA_MEM_TO_DEV:
+ if (nbpf->max_burst_mem_read)
+ max_burst = nbpf->max_burst_mem_read;
+ break;
+ case DMA_DEV_TO_MEM:
+ if (nbpf->max_burst_mem_write)
+ max_burst = nbpf->max_burst_mem_write;
+ break;
+ case DMA_DEV_TO_DEV:
+ default:
+ break;
+ }
+ }
+
/* Maximum supported bursts depend on the buffer size */
- return min_t(int, __ffs(size), ilog2(nbpf->config->buffer_size * 8));
+ return min_t(int, __ffs(size), ilog2(max_burst));
}
static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
@@ -458,7 +483,7 @@ static size_t nbpf_xfer_size(struct nbpf_device *nbpf,
size = burst;
}
- return nbpf_xfer_ds(nbpf, size);
+ return nbpf_xfer_ds(nbpf, size, DMA_TRANS_NONE);
}
/*
@@ -507,7 +532,7 @@ static int nbpf_prep_one(struct nbpf_link_desc *ldesc,
* transfers we enable the SBE bit and terminate the transfer in our
* .device_pause handler.
*/
- mem_xfer = nbpf_xfer_ds(chan->nbpf, size);
+ mem_xfer = nbpf_xfer_ds(chan->nbpf, size, direction);
switch (direction) {
case DMA_DEV_TO_MEM:
@@ -1313,6 +1338,11 @@ static int nbpf_probe(struct platform_device *pdev)
if (IS_ERR(nbpf->clk))
return PTR_ERR(nbpf->clk);
+ of_property_read_u32(np, "max-burst-mem-read",
+ &nbpf->max_burst_mem_read);
+ of_property_read_u32(np, "max-burst-mem-write",
+ &nbpf->max_burst_mem_write);
+
nbpf->config = cfg;
for (i = 0; irqs < ARRAY_SIZE(irqbuf); i++) {
--
2.1.4
^ permalink raw reply related
* [PATCH] ARM: DT: STM32: add dma for usart3 on F429
From: Alexandre TORGUE @ 2016-10-24 13:31 UTC (permalink / raw)
To: Maxime Coquelin, gerald.baeza-qxv4g6HH51o, arnd-r2nGTMty4D4,
robh-DgEjT+Ai2ygdnm+yROfE0A, peter.griffin-QSEj5FYQhm4dnm+yROfE0A,
lee.jones-QSEj5FYQhm4dnm+yROfE0A
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Add DMA support for USART3 on STM32F429 MCU.
Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org>
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
index 11e8a69..0596d60 100644
--- a/arch/arm/boot/dts/stm32f429.dtsi
+++ b/arch/arm/boot/dts/stm32f429.dtsi
@@ -122,6 +122,9 @@
interrupts = <39>;
clocks = <&rcc 0 146>;
status = "disabled";
+ dmas = <&dma1 1 4 0x400 0x0>,
+ <&dma1 3 4 0x400 0x0>;
+ dma-names = "rx", "tx";
};
usart4: serial@40004c00 {
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH 1/3] arm64: arch_timer: Add device tree binding for hisilicon-161x01 erratum
From: Mark Rutland @ 2016-10-24 13:39 UTC (permalink / raw)
To: Ding Tianhong
Cc: Catalin Marinas, Will Deacon, Marc Zyngier, Scott Wood,
devicetree-u79uwXL29TY76Z2rM5mHXA, Shawn Guo,
stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1dcfb21a-7417-282e-f187-425d2c148672-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On Mon, Oct 24, 2016 at 09:23:10PM +0800, Ding Tianhong wrote:
> On 2016/10/24 21:16, Mark Rutland wrote:
> > On Mon, Oct 24, 2016 at 08:40:01PM +0800, Ding Tianhong wrote:
> >> On 2016/10/24 19:16, Mark Rutland wrote:
> >>> Is "161x01" the *exact* erratum number, or is the 'x' a wildcard?
> >>
> >> The 'x' is a wildcard, it will cover 161001 to 161601 several numbers,
> >
> > Given you're using a wildcard, I take it that this is a *part* number?
>
> Yes, I was doubt how to fix this, should I choose a better erratum number?
Typically, we expect that each vendor has some central database of their
errata, with each having a unique ID.
If Huawei do not have such a database, I do not think that we should
invent an erratum number here.
Thanks,
Mark.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v2 11/14] MIPS: Malta: Use syscon-reboot driver to reboot
From: Paul Burton @ 2016-10-24 13:42 UTC (permalink / raw)
To: Maciej W. Rozycki
Cc: linux-mips, Ralf Baechle, devicetree, Stephan Linz,
Jacek Anaszewski, Bartlomiej Zolnierkiewicz, linux-kernel,
Rob Herring, Mark Rutland
In-Reply-To: <alpine.DEB.2.00.1610220956020.31859@tp.orcam.me.uk>
[-- Attachment #1: Type: text/plain, Size: 957 bytes --]
Hi Maciej,
On Saturday, 22 October 2016 10:08:57 BST Maciej W. Rozycki wrote:
> On Mon, 19 Sep 2016, Paul Burton wrote:
> > Make use of the generic syscon-reboot driver to reboot the Malta board,
> > reducing the amount of platform code it requires.
> >
> > Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> > ---
>
> This has broken reboot support, all I get now is:
>
> reboot: Restarting system
> Unable to restart system
> Reboot failed -- System halted
>
> at which point I need to issue a serial BREAK to regain control of the
> board and get back to YAMON; fortunately the board is wired for that.
This was already reported over here:
https://www.linux-mips.org/archives/linux-mips/2016-10/msg00120.html
These 2 patches fix it:
https://patchwork.linux-mips.org/patch/14395/
https://patchwork.linux-mips.org/patch/14396/
I've asked Ralf if we can get those, along with a few others, in ASAP -
preferrably for -rc3.
Thanks,
Paul
[-- Attachment #2: This is a digitally signed message part. --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH] ARM: sti: stih410-clocks: Add PROC_STFE as a critical clock
From: Peter Griffin @ 2016-10-24 13:44 UTC (permalink / raw)
To: Lee Jones
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, patrice.chotard-qxv4g6HH51o,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161024085304.GE14477@dell>
Hi Lee,
On Mon, 24 Oct 2016, Lee Jones wrote:
> On Tue, 18 Oct 2016, Peter Griffin wrote:
>
> > Once the ST frontend demux HW IP has been enabled, the clock can't
> > be disabled otherwise the system will hang and the board will
> > be unserviceable.
> >
> > To allow balanced clock enable/disable calls in the driver we use
> > the critical clock infrastructure to take an extra reference on the
> > clock so the clock will never actually be disabled.
>
> This is an abuse of the critical-clocks framework, and is exactly the
> type of hack I promised the clk guys I'd try to prevent.
I expect the best way to do this would be to write some documentation on the
clock-critical DT binding and/or CRITICAL_CLK flag. The only documentation I can
find currently is with the initial patch series [1] and the comment in
clk-provider.h of
#define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
Or the patch decription
"Critical clocks are those which must not be gated, else undefined
or catastrophic failure would occur. Here we have chosen to
ensure the prepare/enable counts are correctly incremented, so as
not to confuse users with enabled clocks with no visible users."
Which is the functionality I want for this clock.
> If this, or
> any other IP has some quirks (i.e. once enabled, if this clock is
> subsequently disabled it will have a catastrophic effect on the
> platform), then they should be worked around in the driver.
>
> The correct thing to do here is craft a clk-keep-on flag and ensure it
> is set to true for the effected platform(s)' platform data.
I'm always wary of creating a driver specific flag, especially when its
purpose is to do the same thing as an existing mechanism provided by the
subsystem of not gating the clock.
I can see a couple of problems with what you propose:
1) You have to put the clk-keep-on flag in every driver which consumes the
clock. IMO it is much better to have this knowledge in the SoC's
clock driver so every consumer of the clock automatically benefits.
2) You don't benefit from the CLK_IS_CRITICAL reference counting logic in
clk.c. So then each driver has to also work around that to get sensible reference
counts. e.g.
if (!__clk_is_enabled(clk) && pdata->clk-keep-on)
clk_enable(clk)
Which seems to me to be fighting against the subsystem. Given that the only use of
_clk_is_enabled() outside drivers/clk is in an old arch/arm/mach-omap2/pm24xx.c
driver I suspect its use is frowned upon, and it shouldn't really be an EXPORTED_SYMBOL.
regards,
Peter.
[1] https://lkml.org/lkml/2016/1/18/272
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 1/7] drm: sunxi: Add a basic DRM driver for Allwinner DE2
From: Maxime Ripard @ 2016-10-24 14:04 UTC (permalink / raw)
To: Jean-Francois Moine
Cc: Dave Airlie, Liam Girdwood, Mark Brown, Rob Herring,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <8afc5e020c5767face34fe3a9ab300ce9e67ba00.1477142934.git.moinejf-GANU6spQydw@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 57399 bytes --]
Hi,
On Fri, Oct 21, 2016 at 09:26:18AM +0200, Jean-Francois Moine wrote:
> Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> engine, DE2.
> This patch adds a DRM video driver for this device.
>
> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
Output from checkpatch:
total: 0 errors, 20 warnings, 83 checks, 1799 lines checked
> ---
> .../bindings/display/sunxi/sunxi-de2.txt | 83 +++
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/sunxi/Kconfig | 21 +
> drivers/gpu/drm/sunxi/Makefile | 7 +
> drivers/gpu/drm/sunxi/de2_crtc.c | 475 +++++++++++++++++
> drivers/gpu/drm/sunxi/de2_crtc.h | 63 +++
> drivers/gpu/drm/sunxi/de2_de.c | 591 +++++++++++++++++++++
> drivers/gpu/drm/sunxi/de2_drm.h | 47 ++
> drivers/gpu/drm/sunxi/de2_drv.c | 378 +++++++++++++
> drivers/gpu/drm/sunxi/de2_plane.c | 119 +++++
> 11 files changed, 1787 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> create mode 100644 drivers/gpu/drm/sunxi/Kconfig
> create mode 100644 drivers/gpu/drm/sunxi/Makefile
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_crtc.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_de.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_drm.h
> create mode 100644 drivers/gpu/drm/sunxi/de2_drv.c
> create mode 100644 drivers/gpu/drm/sunxi/de2_plane.c
>
> diff --git a/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> new file mode 100644
> index 0000000..f9cd67a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/sunxi/sunxi-de2.txt
> @@ -0,0 +1,83 @@
> +Allwinner sunxi Display Engine 2 subsystem
> +==========================================
> +
> +The sunxi DE2 subsystem contains a display controller (DE2),
sunxi is a made up name, and doesn't really mean anything. You can
call it either sun8i (because it was introduced in that family).
> +one or two LCD controllers (TCON) and their external interfaces.
> +
> +Display controller
> +==================
> +
> +Required properties:
> +
> +- compatible: value should be one of the following
> + "allwinner,sun8i-a83t-display-engine"
> + "allwinner,sun8i-h3-display-engine"
> +
> +- clocks: must include clock specifiers corresponding to entries in the
> + clock-names property.
> +
> +- clock-names: must contain
> + "gate": for DE activation
> + "clock": DE clock
We've been calling them bus and mod.
> +
> +- resets: phandle to the reset of the device
> +
> +- ports: phandle's to the LCD ports
Please use the OF graph.
> +
> +LCD controller
> +==============
> +
> +Required properties:
> +
> +- compatible: value should be one of the following
> + "allwinner,sun8i-a83t-lcd"
> +
> +- clocks: must include clock specifiers corresponding to entries in the
> + clock-names property.
> +
> +- clock-names: must contain
> + "gate": for LCD activation
> + "clock": pixel clock
> +
> +- resets: phandle to the reset of the device
> +
> +- port: port node with endpoint definitions as defined in
> + Documentation/devicetree/bindings/media/video-interfaces.txt
> +
> +Example:
> +
> + de: de-controller@01000000 {
> + compatible = "allwinner,sun8i-h3-display-engine";
> + ...
> + clocks = <&&ccu CLK_BUS_DE>, <&ccu CLK_DE>;
> + clock-names = "gate", "clock";
> + resets = <&ccu RST_BUS_DE>;
> + ports = <&lcd0_p>;
> + };
> +
> + lcd0: lcd-controller@01c0c000 {
> + compatible = "allwinner,sun8i-a83t-lcd";
> + ...
> + clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
> + clock-names = "gate", "clock";
> + resets = <&ccu RST_BUS_TCON0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + lcd0_p: port {
> + lcd0_ep: endpoint {
> + remote-endpoint = <&hdmi_ep>;
> + };
> + };
> + };
> +
> + hdmi: hdmi@01ee0000 {
> + ...
> + #address-cells = <1>;
> + #size-cells = <0>;
> + port {
> + type = "video";
> + hdmi_ep: endpoint {
> + remote-endpoint = <&lcd0_ep>;
> + };
> + };
> + };
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 483059a..afd576f 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -187,6 +187,8 @@ source "drivers/gpu/drm/shmobile/Kconfig"
>
> source "drivers/gpu/drm/sun4i/Kconfig"
>
> +source "drivers/gpu/drm/sunxi/Kconfig"
> +
> source "drivers/gpu/drm/omapdrm/Kconfig"
>
> source "drivers/gpu/drm/tilcdc/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 25c7204..120d0bf 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -70,6 +70,7 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
> obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
> obj-y += omapdrm/
> obj-$(CONFIG_DRM_SUN4I) += sun4i/
> +obj-$(CONFIG_DRM_SUNXI) += sunxi/
> obj-y += tilcdc/
> obj-$(CONFIG_DRM_QXL) += qxl/
> obj-$(CONFIG_DRM_BOCHS) += bochs/
> diff --git a/drivers/gpu/drm/sunxi/Kconfig b/drivers/gpu/drm/sunxi/Kconfig
> new file mode 100644
> index 0000000..56bde2e
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/Kconfig
> @@ -0,0 +1,21 @@
> +#
> +# Allwinner Video configuration
> +#
> +
> +config DRM_SUNXI
> + tristate "DRM Support for Allwinner Video"
> + depends on DRM && OF
> + depends on ARCH_SUNXI || COMPILE_TEST
> + select DRM_KMS_HELPER
> + select DRM_KMS_CMA_HELPER
> + select DRM_GEM_CMA_HELPER
> + help
> + Choose this option if you have a Allwinner chipset.
> +
> +config DRM_SUNXI_DE2
> + tristate "Support for Allwinner Video with DE2 interface"
> + depends on DRM_SUNXI
> + help
> + Choose this option if your Allwinner chipset has the DE2 interface
> + as the A64, A83T and H3. If M is selected the module will be called
> + sunxi-de2-drm.
> diff --git a/drivers/gpu/drm/sunxi/Makefile b/drivers/gpu/drm/sunxi/Makefile
> new file mode 100644
> index 0000000..62220cb
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Makefile for Allwinner's sun8i DRM device driver
> +#
> +
> +sunxi-de2-drm-objs := de2_drv.o de2_de.o de2_crtc.o de2_plane.o
> +
> +obj-$(CONFIG_DRM_SUNXI_DE2) += sunxi-de2-drm.o
> diff --git a/drivers/gpu/drm/sunxi/de2_crtc.c b/drivers/gpu/drm/sunxi/de2_crtc.c
> new file mode 100644
> index 0000000..dae0fab
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_crtc.c
> @@ -0,0 +1,475 @@
> +/*
> + * Allwinner DRM driver - DE2 CRTC
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/component.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <asm/io.h>
> +#include <linux/of_irq.h>
> +
> +#include "de2_drm.h"
> +#include "de2_crtc.h"
> +
> +/* I/O map */
> +
> +struct tcon {
> + u32 gctl;
> +#define TCON_GCTL_TCON_En BIT(31)
> + u32 gint0;
> +#define TCON_GINT0_TCON1_Vb_Int_En BIT(30)
> +#define TCON_GINT0_TCON1_Vb_Int_Flag BIT(14)
> + u32 gint1;
> + u32 dum0[13];
> + u32 tcon0_ctl; /* 0x40 */
> +#define TCON0_CTL_TCON_En BIT(31)
> + u32 dum1[19];
> + u32 tcon1_ctl; /* 0x90 */
> +#define TCON1_CTL_TCON_En BIT(31)
> +#define TCON1_CTL_Interlace_En BIT(20)
> +#define TCON1_CTL_Start_Delay_SHIFT 4
> +#define TCON1_CTL_Start_Delay_MASK GENMASK(8, 4)
> + u32 basic0; /* XI/YI */
> + u32 basic1; /* LS_XO/LS_YO */
> + u32 basic2; /* XO/YO */
> + u32 basic3; /* HT/HBP */
> + u32 basic4; /* VT/VBP */
> + u32 basic5; /* HSPW/VSPW */
> + u32 dum2;
> + u32 ps_sync; /* 0xb0 */
> + u32 dum3[15];
> + u32 io_pol; /* 0xf0 */
> +#define TCON1_IO_POL_IO0_inv BIT(24)
> +#define TCON1_IO_POL_IO1_inv BIT(25)
> +#define TCON1_IO_POL_IO2_inv BIT(26)
> + u32 io_tri;
> + u32 dum4[2];
> +
> + u32 ceu_ctl; /* 0x100 */
> +#define TCON_CEU_CTL_ceu_en BIT(31)
> + u32 dum5[3];
> + u32 ceu_rr;
> + u32 ceu_rg;
> + u32 ceu_rb;
> + u32 ceu_rc;
> + u32 ceu_gr;
> + u32 ceu_gg;
> + u32 ceu_gb;
> + u32 ceu_gc;
> + u32 ceu_br;
> + u32 ceu_bg;
> + u32 ceu_bb;
> + u32 ceu_bc;
> + u32 ceu_rv;
> + u32 ceu_gv;
> + u32 ceu_bv;
> + u32 dum6[45];
> +
> + u32 mux_ctl; /* 0x200 */
> + u32 dum7[63];
> +
> + u32 fill_ctl; /* 0x300 */
> + u32 fill_start0;
> + u32 fill_end0;
> + u32 fill_data0;
> +};
Please use defines instead of the structures.
> +
> +#define XY(x, y) (((x) << 16) | (y))
> +
> +#define tcon_read(base, member) \
> + readl_relaxed(base + offsetof(struct tcon, member))
> +#define tcon_write(base, member, data) \
> + writel_relaxed(data, base + offsetof(struct tcon, member))
> +
> +/* vertical blank functions */
> +static void de2_atomic_flush(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_state)
> +{
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + if (event) {
> + crtc->state->event = NULL;
> + spin_lock_irq(&crtc->dev->event_lock);
> + if (drm_crtc_vblank_get(crtc) == 0)
> + drm_crtc_arm_vblank_event(crtc, event);
> + else
> + drm_crtc_send_vblank_event(crtc, event);
> + spin_unlock_irq(&crtc->dev->event_lock);
> + }
> +}
> +
> +static irqreturn_t de2_lcd_irq(int irq, void *dev_id)
> +{
> + struct lcd *lcd = (struct lcd *) dev_id;
> + u32 isr;
> +
> + isr = tcon_read(lcd->mmio, gint0);
> +
> + drm_crtc_handle_vblank(&lcd->crtc);
> +
> + tcon_write(lcd->mmio, gint0, isr & ~TCON_GINT0_TCON1_Vb_Int_Flag);
> +
> + return IRQ_HANDLED;
> +}
> +
> +int de2_enable_vblank(struct drm_device *drm, unsigned crtc)
> +{
> + struct priv *priv = drm->dev_private;
> + struct lcd *lcd = priv->lcds[crtc];
> +
> + tcon_write(lcd->mmio, gint0,
> + tcon_read(lcd->mmio, gint0) |
> + TCON_GINT0_TCON1_Vb_Int_En);
That's a weird indentation
> + return 0;
> +}
> +
> +void de2_disable_vblank(struct drm_device *drm, unsigned crtc)
> +{
> + struct priv *priv = drm->dev_private;
> + struct lcd *lcd = priv->lcds[crtc];
> +
> + tcon_write(lcd->mmio, gint0,
> + tcon_read(lcd->mmio, gint0) &
> + ~TCON_GINT0_TCON1_Vb_Int_En);
> +}
> +
> +/* panel functions */
Panel functions? In the CRTC driver?
> +static void de2_set_frame_timings(struct lcd *lcd)
> +{
> + struct drm_crtc *crtc = &lcd->crtc;
> + const struct drm_display_mode *mode = &crtc->mode;
> + int interlace = mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 1;
> + int start_delay;
> + u32 data;
> +
> + data = XY(mode->hdisplay - 1, mode->vdisplay / interlace - 1);
> + tcon_write(lcd->mmio, basic0, data);
> + tcon_write(lcd->mmio, basic1, data);
> + tcon_write(lcd->mmio, basic2, data);
> + tcon_write(lcd->mmio, basic3,
> + XY(mode->htotal - 1,
> + mode->htotal - mode->hsync_start - 1));
> + tcon_write(lcd->mmio, basic4,
> + XY(mode->vtotal * (3 - interlace),
> + mode->vtotal - mode->vsync_start - 1));
> + tcon_write(lcd->mmio, basic5,
> + XY(mode->hsync_end - mode->hsync_start - 1,
> + mode->vsync_end - mode->vsync_start - 1));
> +
> + tcon_write(lcd->mmio, ps_sync, XY(1, 1));
> +
> + data = TCON1_IO_POL_IO2_inv;
> + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> + data |= TCON1_IO_POL_IO0_inv;
> + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> + data |= TCON1_IO_POL_IO1_inv;
> + tcon_write(lcd->mmio, io_pol, data);
> +
> + tcon_write(lcd->mmio, ceu_ctl,
> + tcon_read(lcd->mmio, ceu_ctl) & ~TCON_CEU_CTL_ceu_en);
> +
> + data = tcon_read(lcd->mmio, tcon1_ctl);
> + if (interlace == 2)
> + data |= TCON1_CTL_Interlace_En;
> + else
> + data &= ~TCON1_CTL_Interlace_En;
> + tcon_write(lcd->mmio, tcon1_ctl, data);
> +
> + tcon_write(lcd->mmio, fill_ctl, 0);
> + tcon_write(lcd->mmio, fill_start0, mode->vtotal + 1);
> + tcon_write(lcd->mmio, fill_end0, mode->vtotal);
> + tcon_write(lcd->mmio, fill_data0, 0);
> +
> + start_delay = (mode->vtotal - mode->vdisplay) / interlace - 5;
> + if (start_delay > 31)
> + start_delay = 31;
> + data = tcon_read(lcd->mmio, tcon1_ctl);
> + data &= ~TCON1_CTL_Start_Delay_MASK;
> + data |= start_delay << TCON1_CTL_Start_Delay_SHIFT;
> + tcon_write(lcd->mmio, tcon1_ctl, data);
> +
> + tcon_write(lcd->mmio, io_tri, 0x0fffffff);
> +}
Some comments here would be nice, there's a lot of non trivial things.
> +
> +static void de2_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + struct drm_display_mode *mode = &crtc->mode;
> +
> + DRM_DEBUG_DRIVER("\n");
Log something useful, or don't.
> +
> + clk_set_rate(lcd->clk, mode->clock * 1000);
> +
> + de2_set_frame_timings(lcd);
> +
> + tcon_write(lcd->mmio, tcon1_ctl,
> + tcon_read(lcd->mmio, tcon1_ctl) | TCON1_CTL_TCON_En);
> +
> + de2_de_panel_init(lcd->priv, lcd->num, mode);
panel_init in the CRTC enable? Shouldn't that be in the panel driver?
or at least the encoder?
> +
> + drm_mode_debug_printmodeline(mode);
This is already printed by the core.
> +}
> +
> +static void de2_crtc_disable(struct drm_crtc *crtc)
> +{
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + unsigned long flags;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + tcon_write(lcd->mmio, tcon1_ctl,
> + tcon_read(lcd->mmio, tcon1_ctl) & ~TCON1_CTL_TCON_En);
> +
> + if (crtc->state->event && !crtc->state->active) {
> + spin_lock_irqsave(&crtc->dev->event_lock, flags);
> + drm_crtc_send_vblank_event(crtc, crtc->state->event);
> + spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
> + crtc->state->event = NULL;
> + }
> +}
> +
> +static const struct drm_crtc_funcs de2_crtc_funcs = {
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .reset = drm_atomic_helper_crtc_reset,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +static const struct drm_crtc_helper_funcs de2_crtc_helper_funcs = {
> + .atomic_flush = de2_atomic_flush,
> + .enable = de2_crtc_enable,
> + .disable = de2_crtc_disable,
> +};
> +
> +static void de2_tcon_init(struct lcd *lcd)
> +{
> + tcon_write(lcd->mmio, tcon0_ctl,
> + tcon_read(lcd->mmio, tcon0_ctl) & ~TCON0_CTL_TCON_En);
> + tcon_write(lcd->mmio, tcon1_ctl,
> + tcon_read(lcd->mmio, tcon1_ctl) & ~TCON1_CTL_TCON_En);
> + tcon_write(lcd->mmio, gctl,
> + tcon_read(lcd->mmio, gctl) & ~TCON_GCTL_TCON_En);
> +
> + /* disable/ack interrupts */
> + tcon_write(lcd->mmio, gint0, 0);
> +}
> +
> +static void de2_tcon_enable(struct lcd *lcd)
> +{
> + tcon_write(lcd->mmio, gctl,
> + tcon_read(lcd->mmio, gctl) | TCON_GCTL_TCON_En);
> +}
> +
> +static int de2_crtc_init(struct drm_device *drm, struct lcd *lcd)
> +{
> + struct drm_crtc *crtc = &lcd->crtc;
> + int ret;
> +
> + ret = de2_plane_init(drm, lcd);
> + if (ret < 0)
> + return ret;
> +
> + drm_crtc_helper_add(crtc, &de2_crtc_helper_funcs);
> +
> + ret = drm_crtc_init_with_planes(drm, crtc,
> + &lcd->planes[DE2_PRIMARY_PLANE],
> + &lcd->planes[DE2_CURSOR_PLANE],
> + &de2_crtc_funcs, NULL);
> + if (ret < 0)
> + return ret;
> +
> + de2_tcon_enable(lcd);
> +
> + de2_de_enable(lcd->priv, lcd->num);
> +
> + return 0;
> +}
> +
> +/*
> + * device init
> + */
> +static int de2_lcd_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct drm_device *drm = data;
> + struct priv *priv = drm->dev_private;
> + struct lcd *lcd = dev_get_drvdata(dev);
> + int ret;
> +
> + lcd->priv = priv;
> +
> + /* (only 2 LCDs) */
> + lcd->crtc_idx = priv->lcds[0] ? 1 : 0;
> + priv->lcds[lcd->crtc_idx] = lcd;
> +
> + ret = de2_crtc_init(drm, lcd);
> + if (ret < 0) {
> + dev_err(dev, "failed to init the crtc\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static void de2_lcd_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct lcd *lcd = platform_get_drvdata(pdev);
> +
> + if (lcd->mmio) {
> + if (lcd->priv)
> + de2_de_disable(lcd->priv, lcd->num);
> + tcon_write(lcd->mmio, gctl,
> + tcon_read(lcd->mmio, gctl) & ~TCON_GCTL_TCON_En);
> + }
> +}
> +
> +static const struct component_ops de2_lcd_ops = {
> + .bind = de2_lcd_bind,
> + .unbind = de2_lcd_unbind,
> +};
> +
> +static int de2_lcd_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node, *tmp, *parent, *port;
> + struct lcd *lcd;
> + struct resource *res;
> + int id, irq, ret;
> +
> + id = of_alias_get_id(np, "lcd");
> + if (id < 0) {
> + dev_err(dev, "no alias for lcd\n");
> + id = 0;
> + }
> + lcd = devm_kzalloc(dev, sizeof *lcd, GFP_KERNEL);
> + if (!lcd) {
> + dev_err(dev, "failed to allocate private data\n");
> + return -ENOMEM;
> + }
> + dev_set_drvdata(dev, lcd);
> + lcd->dev = dev;
> + lcd->num = id;
What do you need this number for?
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get memory resource\n");
> + return -EINVAL;
> + }
> +
> + lcd->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(lcd->mmio)) {
> + dev_err(dev, "failed to map registers\n");
> + return PTR_ERR(lcd->mmio);
> + }
> +
> + snprintf(lcd->name, sizeof(lcd->name), "sunxi-lcd%d", id);
> +
> + /* possible CRTCs */
> + parent = np;
> + tmp = of_get_child_by_name(np, "ports");
> + if (tmp)
> + parent = tmp;
> + port = of_get_child_by_name(parent, "port");
> + of_node_put(tmp);
> + if (!port) {
> + dev_err(dev, "no port node\n");
> + return -ENXIO;
> + }
> + lcd->crtc.port = port;
> +
> + lcd->gate = devm_clk_get(dev, "gate"); /* optional */
Having some kind of error checking would still be nice.
> +
> + lcd->clk = devm_clk_get(dev, "clock");
> + if (IS_ERR(lcd->clk)) {
> + dev_err(dev, "video clock err %d\n", (int) PTR_ERR(lcd->clk));
> + ret = PTR_ERR(lcd->clk);
> + goto err;
> + }
> +
> + lcd->rstc = devm_reset_control_get_optional(dev, NULL);
Ditto.
> +
> + irq = irq_of_parse_and_map(np, 0);
> + if (irq <= 0 || irq == NO_IRQ) {
> + dev_err(dev, "unable to get irq lcd %d\n", id);
> + ret = -EINVAL;
> + goto err;
> + }
You can use platform_get_irq for that.
> +
> + if (!IS_ERR(lcd->rstc)) {
> + ret = reset_control_deassert(lcd->rstc);
> + if (ret) {
> + dev_err(dev, "reset deassert err %d\n", ret);
> + goto err;
> + }
> + }
> +
> + if (!IS_ERR(lcd->gate)) {
> + ret = clk_prepare_enable(lcd->gate);
> + if (ret)
> + goto err2;
> + }
> +
> + ret = clk_prepare_enable(lcd->clk);
> + if (ret)
> + goto err2;
Is there any reason not to do that in the enable / disable? Leaving
clocks running while the device has no guarantee that it's going to be
used seems like a waste of resources.
> +
> + de2_tcon_init(lcd);
> +
> + ret = devm_request_irq(dev, irq, de2_lcd_irq, 0,
> + lcd->name, lcd);
> + if (ret < 0) {
> + dev_err(dev, "unable to request irq %d\n", irq);
> + goto err2;
> + }
> +
> + return component_add(dev, &de2_lcd_ops);
> +
> +err2:
> + if (!IS_ERR_OR_NULL(lcd->rstc))
> + reset_control_assert(lcd->rstc);
> + clk_disable_unprepare(lcd->gate);
> + clk_disable_unprepare(lcd->clk);
> +err:
> + of_node_put(lcd->crtc.port);
> + return ret;
> +}
> +
> +static int de2_lcd_remove(struct platform_device *pdev)
> +{
> + struct lcd *lcd = platform_get_drvdata(pdev);
> +
> + component_del(&pdev->dev, &de2_lcd_ops);
> +
> + if (!IS_ERR_OR_NULL(lcd->rstc))
> + reset_control_assert(lcd->rstc);
> + clk_disable_unprepare(lcd->gate);
> + clk_disable_unprepare(lcd->clk);
> + of_node_put(lcd->crtc.port);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id de2_lcd_ids[] = {
> + { .compatible = "allwinner,sun8i-a83t-lcd", },
> + { }
> +};
> +
> +struct platform_driver de2_lcd_platform_driver = {
> + .probe = de2_lcd_probe,
> + .remove = de2_lcd_remove,
> + .driver = {
> + .name = "sunxi-de2-lcd",
> + .of_match_table = of_match_ptr(de2_lcd_ids),
> + },
> +};
> diff --git a/drivers/gpu/drm/sunxi/de2_crtc.h b/drivers/gpu/drm/sunxi/de2_crtc.h
> new file mode 100644
> index 0000000..efbe45d
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_crtc.h
> @@ -0,0 +1,63 @@
> +#ifndef __DE2_CRTC_H__
> +#define __DE2_CRTC_H__
> +/*
> + * Copyright (C) 2016 Jean-François Moine
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <drm/drm_plane_helper.h>
> +
> +struct priv;
> +
> +enum de2_plane2 {
> + DE2_PRIMARY_PLANE,
> + DE2_CURSOR_PLANE,
> + DE2_VI_PLANE,
> + DE2_N_PLANES,
> +};
> +struct lcd {
> + void __iomem *mmio;
> +
> + struct device *dev;
> + struct drm_crtc crtc;
> + struct priv *priv; /* DRM/DE private data */
> +
> + short num; /* LCD number in hardware */
> + short crtc_idx; /* CRTC index in drm */
> +
> + struct clk *clk;
> + struct clk *gate;
> + struct reset_control *rstc;
> +
> + char name[16];
> +
> + struct drm_pending_vblank_event *event;
> +
> + struct drm_plane planes[DE2_N_PLANES];
> +};
> +
> +#define crtc_to_lcd(x) container_of(x, struct lcd, crtc)
> +
> +/* in de2_de.c */
> +void de2_de_enable(struct priv *priv, int lcd_num);
> +void de2_de_disable(struct priv *priv, int lcd_num);
> +void de2_de_hw_init(struct priv *priv, int lcd_num);
> +void de2_de_panel_init(struct priv *priv, int lcd_num,
> + struct drm_display_mode *mode);
> +void de2_de_plane_disable(struct priv *priv,
> + int lcd_num, int plane_ix);
> +void de2_de_plane_update(struct priv *priv,
> + int lcd_num, int plane_ix,
> + struct drm_plane_state *state,
> + struct drm_plane_state *old_state);
Does it need to be exported?
> +
> +/* in de2_plane.c */
> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd);
> +
> +#endif /* __DE2_CRTC_H__ */
> diff --git a/drivers/gpu/drm/sunxi/de2_de.c b/drivers/gpu/drm/sunxi/de2_de.c
> new file mode 100644
> index 0000000..0d8cb62
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_de.c
> @@ -0,0 +1,591 @@
> +/*
> + * ALLWINNER DRM driver - Display Engine 2
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + * Copyright (c) 2016 Allwinnertech Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <asm/io.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "de2_drm.h"
> +#include "de2_crtc.h"
> +
> +static DEFINE_SPINLOCK(de_lock);
> +
> +#define DE_CLK_RATE_A83T 504000000 /* pll-de */
> +#define DE_CLK_RATE_H3 432000000 /* de */
This can be set in the DT.
> +
> +/* I/O map */
> +
> +#define DE_MOD_REG 0x0000 /* 1 bit per LCD */
> +#define DE_GATE_REG 0x0004
> +#define DE_RESET_REG 0x0008
> +#define DE_DIV_REG 0x000c /* 4 bits per LCD */
> +#define DE_SEL_REG 0x0010
> +
> +#define DE_MUX0_BASE 0x00100000
> +#define DE_MUX1_BASE 0x00200000
> +
> +/* MUX registers (addr / MUX base) */
> +#define DE_MUX_GLB_REGS 0x00000 /* global control */
> +#define DE_MUX_BLD_REGS 0x01000 /* alpha blending */
> +#define DE_MUX_CHAN_REGS 0x02000 /* VI/UI overlay channels */
> +#define DE_MUX_CHAN_SZ 0x1000 /* size of a channel */
> +#define DE_MUX_VSU_REGS 0x20000 /* VSU */
> +#define DE_MUX_GSU1_REGS 0x30000 /* GSUs */
> +#define DE_MUX_GSU2_REGS 0x40000
> +#define DE_MUX_GSU3_REGS 0x50000
> +#define DE_MUX_FCE_REGS 0xa0000 /* FCE */
> +#define DE_MUX_BWS_REGS 0xa2000 /* BWS */
> +#define DE_MUX_LTI_REGS 0xa4000 /* LTI */
> +#define DE_MUX_PEAK_REGS 0xa6000 /* PEAK */
> +#define DE_MUX_ASE_REGS 0xa8000 /* ASE */
> +#define DE_MUX_FCC_REGS 0xaa000 /* FCC */
> +#define DE_MUX_DCSC_REGS 0xb0000 /* DCSC/SMBL */
> +
> +/* global control */
> +struct de_glb {
> + u32 ctl;
> +#define DE_MUX_GLB_CTL_rt_en BIT(0)
> +#define DE_MUX_GLB_CTL_finish_irq_en BIT(4)
> +#define DE_MUX_GLB_CTL_rtwb_port BIT(12)
> + u32 status;
> + u32 dbuff;
> + u32 size;
> +};
> +
> +/* alpha blending */
> +struct de_bld {
> + u32 fcolor_ctl; /* 00 */
> + struct {
> + u32 fcolor;
> + u32 insize;
> + u32 offset;
> + u32 dum;
> + } attr[4];
> + u32 dum0[15]; /* (end of clear offset) */
> + u32 route; /* 80 */
> + u32 premultiply;
> + u32 bkcolor;
> + u32 output_size;
> + u32 bld_mode[4];
> + u32 dum1[4];
> + u32 ck_ctl; /* b0 */
> + u32 ck_cfg;
> + u32 dum2[2];
> + u32 ck_max[4]; /* c0 */
> + u32 dum3[4];
> + u32 ck_min[4]; /* e0 */
> + u32 dum4[3];
> + u32 out_ctl; /* fc */
> +};
> +
> +/* VI channel */
> +struct de_vi {
> + struct {
> + u32 attr;
> +#define VI_CFG_ATTR_en BIT(0)
> +#define VI_CFG_ATTR_fcolor_en BIT(4)
> +#define VI_CFG_ATTR_fmt_SHIFT 8
> +#define VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
> +#define VI_CFG_ATTR_ui_sel BIT(15)
> +#define VI_CFG_ATTR_top_down BIT(23)
> + u32 size;
> + u32 coord;
> +#define VI_N_PLANES 3
> + u32 pitch[VI_N_PLANES];
> + u32 top_laddr[VI_N_PLANES];
> + u32 bot_laddr[VI_N_PLANES];
> + } cfg[4];
> + u32 fcolor[4]; /* c0 */
> + u32 top_haddr[VI_N_PLANES]; /* d0 */
> + u32 bot_haddr[VI_N_PLANES]; /* dc */
> + u32 ovl_size[2]; /* e8 */
> + u32 hori[2]; /* f0 */
> + u32 vert[2]; /* f8 */
> +};
> +
> +/* UI channel */
> +struct de_ui {
> + struct {
> + u32 attr;
> +#define UI_CFG_ATTR_en BIT(0)
> +#define UI_CFG_ATTR_alpmod_SHIFT 1
> +#define UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1)
> +#define UI_CFG_ATTR_fcolor_en BIT(4)
> +#define UI_CFG_ATTR_fmt_SHIFT 8
> +#define UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
> +#define UI_CFG_ATTR_top_down BIT(23)
> +#define UI_CFG_ATTR_alpha_SHIFT 24
> +#define UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
> + u32 size;
> + u32 coord;
> + u32 pitch;
> + u32 top_laddr;
> + u32 bot_laddr;
> + u32 fcolor;
> + u32 dum;
> + } cfg[4]; /* 00 */
> + u32 top_haddr; /* 80 */
> + u32 bot_haddr;
> + u32 ovl_size; /* 88 */
> +};
Please use defines instead of the structures.
> +
> +/* coordinates and sizes */
> +#define XY(x, y) (((y) << 16) | (x))
> +#define WH(w, h) (((h - 1) << 16) | (w - 1))
> +
> +/* UI video formats */
> +#define DE2_FORMAT_ARGB_8888 0
> +#define DE2_FORMAT_BGRA_8888 3
> +#define DE2_FORMAT_XRGB_8888 4
> +#define DE2_FORMAT_RGB_888 8
> +#define DE2_FORMAT_BGR_888 9
> +
> +/* VI video formats */
> +#define DE2_FORMAT_YUV422_I_YVYU 1 /* Y-V-Y-U */
> +#define DE2_FORMAT_YUV422_I_UYVY 2 /* U-Y-V-Y */
> +#define DE2_FORMAT_YUV422_I_YUYV 3 /* Y-U-Y-V */
> +#define DE2_FORMAT_YUV422_P 6 /* YYYY UU VV planar */
> +#define DE2_FORMAT_YUV420_P 10 /* YYYY U V planar */
> +
> +#define glb_read(base, member) \
> + readl_relaxed(base + offsetof(struct de_glb, member))
> +#define glb_write(base, member, data) \
> + writel_relaxed(data, base + offsetof(struct de_glb, member))
> +#define bld_read(base, member) \
> + readl_relaxed(base + offsetof(struct de_bld, member))
> +#define bld_write(base, member, data) \
> + writel_relaxed(data, base + offsetof(struct de_bld, member))
> +#define ui_read(base, member) \
> + readl_relaxed(base + offsetof(struct de_ui, member))
> +#define ui_write(base, member, data) \
> + writel_relaxed(data, base + offsetof(struct de_ui, member))
> +#define vi_read(base, member) \
> + readl_relaxed(base + offsetof(struct de_vi, member))
> +#define vi_write(base, member, data) \
> + writel_relaxed(data, base + offsetof(struct de_vi, member))
> +
> +static const struct {
> + char chan;
> + char layer;
> + char pipe;
> +} plane2layer[DE2_N_PLANES] = {
> + [DE2_PRIMARY_PLANE] = {0, 0, 0},
> + [DE2_CURSOR_PLANE] = {1, 0, 1},
> + [DE2_VI_PLANE] = {0, 1, 0},
> +};
Comments?
> +static inline void de_write(struct priv *priv, int reg, u32 data)
> +{
> + writel_relaxed(data, priv->mmio + reg);
> +}
> +
> +static inline u32 de_read(struct priv *priv, int reg)
> +{
> + return readl_relaxed(priv->mmio + reg);
> +}
> +
> +static void de_lcd_select(struct priv *priv,
> + int lcd_num,
> + void __iomem *mux_o)
> +{
> + u32 data;
> +
> + /* select the LCD */
> + data = de_read(priv, DE_SEL_REG);
> + data &= ~1;
> + de_write(priv, DE_SEL_REG, data);
> +
> + /* double register switch */
> + glb_write(mux_o + DE_MUX_GLB_REGS, dbuff, 1);
> +}
> +
> +void de2_de_plane_update(struct priv *priv,
> + int lcd_num, int plane_ix,
> + struct drm_plane_state *state,
> + struct drm_plane_state *old_state)
> +{
> + struct drm_framebuffer *fb = state->fb;
> + struct drm_gem_cma_object *gem;
> + void __iomem *mux_o = priv->mmio;
> + void __iomem *chan_o;
> + u32 size = WH(state->crtc_w, state->crtc_h);
> + u32 coord;
> + u32 screen_size;
> + u32 data, fcolor;
> + u32 ui_sel, alpha_glob;
> + int chan, layer, x, y;
> + unsigned fmt;
> + unsigned long flags;
> +
> + chan = plane2layer[plane_ix].chan;
> + layer = plane2layer[plane_ix].layer;
> +
> + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> + chan_o = mux_o;
> + chan_o += DE_MUX_CHAN_REGS + DE_MUX_CHAN_SZ * chan;
> +
> + x = state->crtc_x >= 0 ? state->crtc_x : 0;
> + y = state->crtc_y >= 0 ? state->crtc_y : 0;
> + coord = XY(x, y);
> +
> + /* handle the cursor move */
> + if (plane_ix == DE2_CURSOR_PLANE
> + && fb == old_state->fb) {
> + spin_lock_irqsave(&de_lock, flags);
> + de_lcd_select(priv, lcd_num, mux_o);
> + if (chan == 0)
> + vi_write(chan_o, cfg[layer].coord, coord);
> + else
> + ui_write(chan_o, cfg[layer].coord, coord);
> + spin_unlock_irqrestore(&de_lock, flags);
> + return;
> + }
> +
> + gem = drm_fb_cma_get_gem_obj(fb, 0);
> +
> + ui_sel = alpha_glob = 0;
> + switch (fb->pixel_format) {
> + case DRM_FORMAT_ARGB8888:
> + fmt = DE2_FORMAT_ARGB_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_BGRA8888:
> + fmt = DE2_FORMAT_BGRA_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_XRGB8888:
> + fmt = DE2_FORMAT_XRGB_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + alpha_glob = (1 << UI_CFG_ATTR_alpmod_SHIFT) |
> + (0xff << UI_CFG_ATTR_alpha_SHIFT);
> + break;
> + case DRM_FORMAT_RGB888:
> + fmt = DE2_FORMAT_RGB_888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_BGR888:
> + fmt = DE2_FORMAT_BGR_888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_YUYV:
> + fmt = DE2_FORMAT_YUV422_I_YUYV;
> + break;
> + case DRM_FORMAT_YVYU:
> + fmt = DE2_FORMAT_YUV422_I_YVYU;
> + break;
> + case DRM_FORMAT_YUV422:
> + fmt = DE2_FORMAT_YUV422_P;
> + break;
> + case DRM_FORMAT_YUV420:
> + fmt = DE2_FORMAT_YUV420_P;
> + break;
> + case DRM_FORMAT_UYVY:
> + fmt = DE2_FORMAT_YUV422_I_UYVY;
> + break;
> + default:
> + pr_err("format %.4s not yet treated\n",
> + (char *) &fb->pixel_format);
> + return;
> + }
> +
> + spin_lock_irqsave(&de_lock, flags);
> +
> + screen_size = plane_ix == DE2_PRIMARY_PLANE ?
> + size :
> + glb_read(mux_o + DE_MUX_GLB_REGS, size);
> +
> + /* prepare the activation of alpha blending (1 bit per plane) */
> + fcolor = bld_read(mux_o + DE_MUX_BLD_REGS, fcolor_ctl)
> + | (0x100 << plane2layer[plane_ix].pipe);
> +
> + de_lcd_select(priv, lcd_num, mux_o);
> +
> + if (chan == 0) { /* VI channel */
> + int i;
> +
> + data = VI_CFG_ATTR_en | (fmt << VI_CFG_ATTR_fmt_SHIFT) |
> + ui_sel;
> + vi_write(chan_o, cfg[layer].attr, data);
> + vi_write(chan_o, cfg[layer].size, size);
> + vi_write(chan_o, cfg[layer].coord, coord);
> + for (i = 0; i < VI_N_PLANES; i++) {
> + vi_write(chan_o, cfg[layer].pitch[i],
> + fb->pitches[i] ? fb->pitches[i] :
> + fb->pitches[0]);
> + vi_write(chan_o, cfg[layer].top_laddr[i],
> + gem->paddr + fb->offsets[i]);
> + vi_write(chan_o, fcolor[layer], 0xff000000);
> + }
> + if (layer == 0)
> + vi_write(chan_o, ovl_size[0], screen_size);
> +
> + } else { /* UI channel */
> + data = UI_CFG_ATTR_en | (fmt << UI_CFG_ATTR_fmt_SHIFT) |
> + alpha_glob;
> + ui_write(chan_o, cfg[layer].attr, data);
> + ui_write(chan_o, cfg[layer].size, size);
> + ui_write(chan_o, cfg[layer].coord, coord);
> + ui_write(chan_o, cfg[layer].pitch, fb->pitches[0]);
> + ui_write(chan_o, cfg[layer].top_laddr,
> + gem->paddr + fb->offsets[0]);
> + if (layer == 0)
> + ui_write(chan_o, ovl_size, screen_size);
> + }
> + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl, fcolor);
> +
> + spin_unlock_irqrestore(&de_lock, flags);
> +}
Splitting that into functions would make it a bit more trivial and
readable.
> +void de2_de_plane_disable(struct priv *priv,
> + int lcd_num, int plane_ix)
> +{
> + void __iomem *mux_o = priv->mmio;
> + void __iomem *chan_o;
> + u32 fcolor;
> + int chan, layer, chan_disable = 0;
> + unsigned long flags;
> +
> + chan = plane2layer[plane_ix].chan;
> + layer = plane2layer[plane_ix].layer;
> +
> + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> + chan_o = mux_o;
> + chan_o += DE_MUX_CHAN_REGS + DE_MUX_CHAN_SZ * chan;
> +
> + /* (only 2 layers) */
> + if (chan == 0) {
> + if (vi_read(chan_o, cfg[1 - layer].attr) == 0)
> + chan_disable = 1;
> + } else {
> + if (ui_read(chan_o, cfg[1 - layer].attr) == 0)
> + chan_disable = 1;
> + }
> +
> + spin_lock_irqsave(&de_lock, flags);
> +
> + fcolor = bld_read(mux_o + DE_MUX_BLD_REGS, fcolor_ctl);
> +
> + de_lcd_select(priv, lcd_num, mux_o);
> +
> + if (chan == 0)
> + vi_write(chan_o, cfg[layer].attr, 0);
> + else
> + ui_write(chan_o, cfg[layer].attr, 0);
> +
> + if (chan_disable)
> + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl,
> + fcolor & ~(0x100 << plane2layer[plane_ix].pipe));
> +
> + spin_unlock_irqrestore(&de_lock, flags);
> +}
Can't you just disable it?
> +void de2_de_panel_init(struct priv *priv, int lcd_num,
> + struct drm_display_mode *mode)
> +{
> + void __iomem *mux_o = priv->mmio;
> + u32 size = WH(mode->hdisplay, mode->vdisplay);
> + unsigned i;
> + unsigned long flags;
> +
> + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> +
> + DRM_DEBUG_DRIVER("%dx%d\n", mode->hdisplay, mode->vdisplay);
> +
> + spin_lock_irqsave(&de_lock, flags);
> +
> + de_lcd_select(priv, lcd_num, mux_o);
> +
> + glb_write(mux_o + DE_MUX_GLB_REGS, size, size);
> +
> + /* set alpha blending */
> + for (i = 0; i < 4; i++) {
> + bld_write(mux_o + DE_MUX_BLD_REGS, attr[i].fcolor, 0xff000000);
> + bld_write(mux_o + DE_MUX_BLD_REGS, attr[i].insize, size);
> + }
> + bld_write(mux_o + DE_MUX_BLD_REGS, output_size, size);
> + bld_write(mux_o + DE_MUX_BLD_REGS, out_ctl,
> + mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 0);
> +
> + spin_unlock_irqrestore(&de_lock, flags);
> +}
> +
> +void de2_de_enable(struct priv *priv, int lcd_num)
> +{
> + void __iomem *mux_o = priv->mmio;
> + unsigned chan, i;
> + u32 size = WH(1920, 1080);
> + u32 data;
> + unsigned long flags;
> +
> + DRM_DEBUG_DRIVER("lcd %d\n", lcd_num);
> +
> + de_write(priv, DE_RESET_REG,
> + de_read(priv, DE_RESET_REG) |
> + (lcd_num == 0 ? 1 : 4));
> + data = 1 << lcd_num; /* 1 bit / lcd */
> + de_write(priv, DE_GATE_REG,
> + de_read(priv, DE_GATE_REG) | data);
> + de_write(priv, DE_MOD_REG,
> + de_read(priv, DE_MOD_REG) | data);
> +
> + mux_o += (lcd_num == 0) ? DE_MUX0_BASE : DE_MUX1_BASE;
> +
> + spin_lock_irqsave(&de_lock, flags);
> +
> + /* select the LCD */
> + data = de_read(priv, DE_SEL_REG);
> + if (lcd_num == 0)
> + data &= ~1;
> + else
> + data |= 1;
> + de_write(priv, DE_SEL_REG, data);
> +
> + /* start init */
> + glb_write(mux_o + DE_MUX_GLB_REGS, ctl,
> + DE_MUX_GLB_CTL_rt_en | DE_MUX_GLB_CTL_rtwb_port);
> + glb_write(mux_o + DE_MUX_GLB_REGS, status, 0);
> + glb_write(mux_o + DE_MUX_GLB_REGS, dbuff, 1); /* dble reg switch */
> + glb_write(mux_o + DE_MUX_GLB_REGS, size, size);
> +
> + /* clear the VI/UI channels */
> + for (chan = 0; chan < 4; chan++) {
> + void __iomem *chan_o = mux_o + DE_MUX_CHAN_REGS +
> + DE_MUX_CHAN_SZ * chan;
> +
> + memset_io(chan_o, 0, chan == 0 ?
> + sizeof(struct de_vi) : sizeof(struct de_ui));
> +
> + /* only 1 VI and 1 UI in lcd1 */
> + if (chan == 2 && lcd_num == 1)
> + break;
> + }
> +
> + /* clear and set alpha blending */
> + memset_io(mux_o + DE_MUX_BLD_REGS, 0, offsetof(struct de_bld, dum0));
> + bld_write(mux_o + DE_MUX_BLD_REGS, fcolor_ctl, 0x00000101);
> + /* fcolor for primary */
> +
> + /* prepare route for planes */
> + data = 0;
> + for (i = 0; i < DE2_N_PLANES; i++)
> + data |= plane2layer[i].chan << (plane2layer[i].pipe * 4);
> + bld_write(mux_o + DE_MUX_BLD_REGS, route, data);
> +
> + bld_write(mux_o + DE_MUX_BLD_REGS, premultiply, 0);
> + bld_write(mux_o + DE_MUX_BLD_REGS, bkcolor, 0xff000000);
> + bld_write(mux_o + DE_MUX_BLD_REGS, bld_mode[0], 0x03010301);
> + /* SRCOVER */
> + bld_write(mux_o + DE_MUX_BLD_REGS, bld_mode[1], 0x03010301);
> + bld_write(mux_o + DE_MUX_BLD_REGS, out_ctl, 0);
> +
> + /* disable the enhancements */
> + writel_relaxed(0, mux_o + DE_MUX_VSU_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_GSU1_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_GSU2_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_GSU3_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_FCE_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_BWS_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_LTI_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_PEAK_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_ASE_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_FCC_REGS);
> + writel_relaxed(0, mux_o + DE_MUX_DCSC_REGS);
> +
> + spin_unlock_irqrestore(&de_lock, flags);
> +}
> +
> +void de2_de_disable(struct priv *priv, int lcd_num)
> +{
> + u32 data;
> +
> + data = ~(1 << lcd_num);
> + de_write(priv, DE_MOD_REG,
> + de_read(priv, DE_MOD_REG) & data);
> + de_write(priv, DE_GATE_REG,
> + de_read(priv, DE_GATE_REG) & data);
> + de_write(priv, DE_RESET_REG,
> + de_read(priv, DE_RESET_REG) & data);
> +}
> +
> +int de2_de_init(struct priv *priv, struct device *dev)
> +{
> + struct resource *res;
> + int ret;
> +
> + DRM_DEBUG_DRIVER("\n");
> +
> + res = platform_get_resource(to_platform_device(dev),
> + IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get memory resource\n");
> + return -EINVAL;
> + }
> +
> + priv->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->mmio)) {
> + dev_err(dev, "failed to map registers\n");
> + return PTR_ERR(priv->mmio);
> + }
> +
> + priv->gate = devm_clk_get(dev, "gate"); /* optional */
Error checking
> +
> + priv->clk = devm_clk_get(dev, "clock");
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "video clock err %d\n", (int) PTR_ERR(priv->clk));
> + return PTR_ERR(priv->clk);
> + }
> +
> + priv->rstc = devm_reset_control_get_optional(dev, NULL);
> +
> + if (!IS_ERR(priv->rstc)) {
> + ret = reset_control_deassert(priv->rstc);
> + if (ret) {
> + dev_err(dev, "reset deassert err %d\n", ret);
> + return ret;
> + }
> + }
> +
> + if (!IS_ERR(priv->gate)) {
> + ret = clk_prepare_enable(priv->gate);
> + if (ret)
> + goto err_gate;
> + }
> +
> + ret = clk_prepare_enable(priv->clk);
> + if (ret)
> + goto err_enable;
> + if (priv->soc_type == SOC_A83T)
> + clk_set_rate(priv->clk, DE_CLK_RATE_A83T);
> + else
> + clk_set_rate(priv->clk, DE_CLK_RATE_H3);
> +
> + /* set the A83T clock divider = 500 / 250 */
> + if (priv->soc_type == SOC_A83T)
> + de_write(priv, DE_DIV_REG,
> + 0x00000011); /* div = 2 for both LCDs */
> +
> + return 0;
> +
> +err_enable:
> + clk_disable_unprepare(priv->gate);
> +err_gate:
> + if (!IS_ERR(priv->rstc))
> + reset_control_assert(priv->rstc);
> + return ret;
> +}
> +
> +void de2_de_cleanup(struct priv *priv)
> +{
> + clk_disable_unprepare(priv->clk);
> + clk_disable_unprepare(priv->gate);
> + if (!IS_ERR(priv->rstc))
> + reset_control_assert(priv->rstc);
> +}
> diff --git a/drivers/gpu/drm/sunxi/de2_drm.h b/drivers/gpu/drm/sunxi/de2_drm.h
> new file mode 100644
> index 0000000..7bb966c
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_drm.h
> @@ -0,0 +1,47 @@
> +#ifndef __DE2_DRM_H__
> +#define __DE2_DRM_H__
> +/*
> + * Copyright (C) 2016 Jean-François Moine
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +#include <drm/drmP.h>
> +#include <drm/drm_fb_cma_helper.h>
> +
> +struct lcd;
> +
> +#define N_LCDS 2
> +
> +/* SoC types */
> +#define SOC_A83T 0
> +#define SOC_H3 1
> +
> +struct priv {
> + void __iomem *mmio;
> + struct clk *clk;
> + struct clk *gate;
> + struct reset_control *rstc;
> +
> + int soc_type;
> +
> + struct drm_fbdev_cma *fbdev;
> +
> + struct lcd *lcds[N_LCDS];
> +};
> +
> +/* in de2_crtc.c */
> +int de2_enable_vblank(struct drm_device *drm, unsigned crtc);
> +void de2_disable_vblank(struct drm_device *drm, unsigned crtc);
> +extern struct platform_driver de2_lcd_platform_driver;
> +
> +/* in de2_de.c */
> +int de2_de_init(struct priv *priv, struct device *dev);
> +void de2_de_cleanup(struct priv *priv);
> +
> +#endif /* __DE2_DRM_H__ */
> diff --git a/drivers/gpu/drm/sunxi/de2_drv.c b/drivers/gpu/drm/sunxi/de2_drv.c
> new file mode 100644
> index 0000000..5daa15c
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_drv.c
> @@ -0,0 +1,378 @@
> +/*
> + * Allwinner DRM driver - DE2 DRM driver
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/pm.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/of_device.h>
> +#include <linux/of_graph.h>
> +#include <linux/component.h>
> +#include <drm/drm_of.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "de2_drm.h"
> +
> +#define DRIVER_NAME "sunxi-de2"
> +#define DRIVER_DESC "Allwinner DRM DE2"
> +#define DRIVER_DATE "20161001"
> +#define DRIVER_MAJOR 1
> +#define DRIVER_MINOR 0
> +
> +static struct of_device_id de2_drm_of_match[] = {
> + { .compatible = "allwinner,sun8i-a83t-display-engine",
> + .data = (void *) SOC_A83T },
> + { .compatible = "allwinner,sun8i-h3-display-engine",
> + .data = (void *) SOC_H3 },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, de2_drm_of_match);
> +
> +static void de2_fb_output_poll_changed(struct drm_device *drm)
> +{
> + struct priv *priv = drm->dev_private;
> +
> + if (priv->fbdev)
> + drm_fbdev_cma_hotplug_event(priv->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs de2_mode_config_funcs = {
> + .fb_create = drm_fb_cma_create,
> + .output_poll_changed = de2_fb_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +/*
> + * DRM operations:
> + */
> +static void de2_lastclose(struct drm_device *drm)
> +{
> + struct priv *priv = drm->dev_private;
> +
> + if (priv->fbdev)
> + drm_fbdev_cma_restore_mode(priv->fbdev);
> +}
> +
> +static const struct file_operations de2_fops = {
> + .owner = THIS_MODULE,
> + .open = drm_open,
> + .release = drm_release,
> + .unlocked_ioctl = drm_ioctl,
> + .poll = drm_poll,
> + .read = drm_read,
> + .llseek = no_llseek,
> + .mmap = drm_gem_cma_mmap,
> +};
> +
> +static struct drm_driver de2_drm_driver = {
> + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
> + DRIVER_ATOMIC,
> + .lastclose = de2_lastclose,
> + .get_vblank_counter = drm_vblank_no_hw_counter,
> + .enable_vblank = de2_enable_vblank,
> + .disable_vblank = de2_disable_vblank,
> + .gem_free_object = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .fops = &de2_fops,
> + .name = DRIVER_NAME,
> + .desc = DRIVER_DESC,
> + .date = DRIVER_DATE,
> + .major = DRIVER_MAJOR,
> + .minor = DRIVER_MINOR,
> +};
> +
> +#ifdef CONFIG_PM_SLEEP
> +/*
> + * Power management
> + */
> +static int de2_pm_suspend(struct device *dev)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> +
> + drm_kms_helper_poll_disable(drm);
> + return 0;
> +}
> +
> +static int de2_pm_resume(struct device *dev)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> +
> + drm_kms_helper_poll_enable(drm);
> + return 0;
> +}
> +#endif
> +
> +static const struct dev_pm_ops de2_pm_ops = {
> + SET_SYSTEM_SLEEP_PM_OPS(de2_pm_suspend, de2_pm_resume)
> +};
Why do you need that? How did you test it? There's no runtime_pm calls
in your kernel.
> +/*
> + * Platform driver
> + */
> +
> +static int de2_drm_bind(struct device *dev)
> +{
> + struct drm_device *drm;
> + struct priv *priv;
> + int ret;
> +
> + drm = drm_dev_alloc(&de2_drm_driver, dev);
> + if (!drm)
> + return -ENOMEM;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv) {
> + dev_err(dev, "failed to allocate private area\n");
> + ret = -ENOMEM;
> + goto out1;
> + }
> +
> + dev_set_drvdata(dev, drm);
> + drm->dev_private = priv;
> +
> + drm_mode_config_init(drm);
> + drm->mode_config.min_width = 32; /* needed for cursor */
> + drm->mode_config.min_height = 32;
> + drm->mode_config.max_width = 1920;
> + drm->mode_config.max_height = 1080;
> + drm->mode_config.funcs = &de2_mode_config_funcs;
> +
> + drm->irq_enabled = true;
> +
> + /* initialize the display engine */
> + priv->soc_type = (int) of_match_device(de2_drm_of_match, dev)->data;
> + ret = de2_de_init(priv, dev);
> + if (ret)
> + goto out2;
> +
> + /* start the subdevices */
> + ret = component_bind_all(dev, drm);
> + if (ret < 0)
> + goto out2;
> +
> + ret = drm_dev_register(drm, 0);
> + if (ret < 0)
> + goto out3;
> +
> + DRM_DEBUG_DRIVER("%d crtcs %d connectors\n",
> + drm->mode_config.num_crtc,
> + drm->mode_config.num_connector);
> +
> + ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
> + if (ret < 0)
> + dev_warn(dev, "failed to initialize vblank\n");
> +
> + drm_mode_config_reset(drm);
> +
> + priv->fbdev = drm_fbdev_cma_init(drm,
> + 32, /* bpp */
> + drm->mode_config.num_crtc,
> + drm->mode_config.num_connector);
> + if (IS_ERR(priv->fbdev)) {
> + ret = PTR_ERR(priv->fbdev);
> + priv->fbdev = NULL;
> + goto out4;
> + }
> +
> + drm_kms_helper_poll_init(drm);
> +
> + return 0;
> +
> +out4:
> + drm_dev_unregister(drm);
> +out3:
> + component_unbind_all(dev, drm);
> +out2:
> + kfree(priv);
> +out1:
> + drm_dev_unref(drm);
> + return ret;
> +}
> +
> +static void de2_drm_unbind(struct device *dev)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> + struct priv *priv = drm->dev_private;
> +
> + if (priv)
> + drm_fbdev_cma_fini(priv->fbdev);
> + drm_kms_helper_poll_fini(drm);
> +
> + drm_dev_unregister(drm);
> + drm_vblank_cleanup(drm);
> +
> + drm_mode_config_cleanup(drm);
> +
> + component_unbind_all(dev, drm);
> +
> + if (priv) {
> + de2_de_cleanup(priv);
> + kfree(priv);
> + }
> +
> + drm_dev_unref(drm);
> +}
> +
> +static const struct component_master_ops de2_drm_comp_ops = {
> + .bind = de2_drm_bind,
> + .unbind = de2_drm_unbind,
> +};
> +
> +static int compare_of(struct device *dev, void *data)
> +{
> + return dev->of_node == data;
> +}
> +
> +static int de2_drm_add_components(struct device *dev,
> + int (*compare_of)(struct device *, void *),
> + const struct component_master_ops *m_ops)
> +{
> + struct device_node *ep, *port, *remote;
> + struct component_match *match = NULL;
> + int i;
> +
> + if (!dev->of_node)
> + return -EINVAL;
> +
> + /* bind the CRTCs */
> + for (i = 0; ; i++) {
> + port = of_parse_phandle(dev->of_node, "ports", i);
> + if (!port)
> + break;
> +
> + if (!of_device_is_available(port->parent)) {
> + of_node_put(port);
> + continue;
> + }
> +
> + component_match_add(dev, &match, compare_of, port->parent);
> + of_node_put(port);
> + }
> +
> + if (i == 0) {
> + dev_err(dev, "missing 'ports' property\n");
> + return -ENODEV;
> + }
> + if (!match) {
> + dev_err(dev, "no available port\n");
> + return -ENODEV;
> + }
> +
> + /* bind the encoders/connectors */
> + for (i = 0; ; i++) {
> + port = of_parse_phandle(dev->of_node, "ports", i);
> + if (!port)
> + break;
> +
> + if (!of_device_is_available(port->parent)) {
> + of_node_put(port);
> + continue;
> + }
> +
> + for_each_child_of_node(port, ep) {
> + remote = of_graph_get_remote_port_parent(ep);
> + if (!remote || !of_device_is_available(remote)) {
> + of_node_put(remote);
> + continue;
> + }
> + if (!of_device_is_available(remote->parent)) {
> + dev_warn(dev,
> + "parent device of %s is not available\n",
> + remote->full_name);
> + of_node_put(remote);
> + continue;
> + }
> +
> + component_match_add(dev, &match, compare_of, remote);
> + of_node_put(remote);
> + }
> + of_node_put(port);
> + }
> +
> + return component_master_add_with_match(dev, m_ops, match);
> +}
> +
> +static int de2_drm_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = de2_drm_add_components(&pdev->dev,
> + compare_of,
> + &de2_drm_comp_ops);
> + if (ret == -EINVAL)
> + ret = -ENXIO;
> + return ret;
> +}
> +
> +static int de2_drm_remove(struct platform_device *pdev)
> +{
> + component_master_del(&pdev->dev, &de2_drm_comp_ops);
> +
> + return 0;
> +}
> +
> +static struct platform_driver de2_drm_platform_driver = {
> + .probe = de2_drm_probe,
> + .remove = de2_drm_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .pm = &de2_pm_ops,
> + .of_match_table = de2_drm_of_match,
> + },
> +};
> +
> +static int __init de2_drm_init(void)
> +{
> + int ret;
> +
> +/* uncomment to activate the drm traces at startup time */
> +/* drm_debug = DRM_UT_CORE | DRM_UT_DRIVER | DRM_UT_KMS |
> + DRM_UT_PRIME | DRM_UT_ATOMIC; */
That's useless.
> + DRM_DEBUG_DRIVER("\n");
> +
> + ret = platform_driver_register(&de2_lcd_platform_driver);
> + if (ret < 0)
> + return ret;
> +
> + ret = platform_driver_register(&de2_drm_platform_driver);
> + if (ret < 0)
> + platform_driver_unregister(&de2_lcd_platform_driver);
> +
> + return ret;
> +}
And that really shouldn't be done that way.
> +static void __exit de2_drm_fini(void)
> +{
> + platform_driver_unregister(&de2_lcd_platform_driver);
> + platform_driver_unregister(&de2_drm_platform_driver);
> +}
> +
> +module_init(de2_drm_init);
> +module_exit(de2_drm_fini);
> +
> +MODULE_AUTHOR("Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>");
> +MODULE_DESCRIPTION("Allwinner DE2 DRM Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/sunxi/de2_plane.c b/drivers/gpu/drm/sunxi/de2_plane.c
> new file mode 100644
> index 0000000..b338684
> --- /dev/null
> +++ b/drivers/gpu/drm/sunxi/de2_plane.c
> @@ -0,0 +1,119 @@
> +/*
> + * Allwinner DRM driver - DE2 planes
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_plane_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +
> +#include "de2_drm.h"
> +#include "de2_crtc.h"
> +
> +/* plane formats */
> +static const uint32_t ui_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> +};
> +
> +static const uint32_t vi_formats[] = {
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_YUV422,
> + DRM_FORMAT_YUV420,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> +};
> +
> +static void de2_plane_disable(struct drm_plane *plane,
> + struct drm_plane_state *old_state)
> +{
> + struct drm_crtc *crtc = old_state->crtc;
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + int plane_num = plane - lcd->planes;
> +
> + de2_de_plane_disable(lcd->priv, lcd->num, plane_num);
> +}
> +
> +static void de2_plane_update(struct drm_plane *plane,
> + struct drm_plane_state *old_state)
> +{
> + struct drm_plane_state *state = plane->state;
> + struct drm_crtc *crtc = state->crtc;
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + struct drm_framebuffer *fb = state->fb;
> + int plane_num = plane - lcd->planes;
> +
> + if (!crtc || !fb) {
> + DRM_DEBUG_DRIVER("no crtc/fb\n");
> + return;
> + }
> +
> + de2_de_plane_update(lcd->priv, lcd->num, plane_num,
> + state, old_state);
> +}
> +
> +static const struct drm_plane_helper_funcs plane_helper_funcs = {
> + .atomic_disable = de2_plane_disable,
> + .atomic_update = de2_plane_update,
> +};
> +
> +static const struct drm_plane_funcs plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .destroy = drm_plane_cleanup,
> + .reset = drm_atomic_helper_plane_reset,
> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static int de2_one_plane_init(struct drm_device *drm,
> + struct drm_plane *plane,
> + int type, int possible_crtcs,
> + const uint32_t *formats,
> + int nformats)
> +{
> + int ret;
> +
> + ret = drm_universal_plane_init(drm, plane, possible_crtcs,
> + &plane_funcs,
> + formats, nformats, type, NULL);
> + if (ret >= 0)
> + drm_plane_helper_add(plane, &plane_helper_funcs);
> +
> + return ret;
> +}
> +
> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd)
> +{
> + int ret, possible_crtcs = 1 << lcd->crtc_idx;
> +
> + ret = de2_one_plane_init(drm, &lcd->planes[DE2_PRIMARY_PLANE],
> + DRM_PLANE_TYPE_PRIMARY, possible_crtcs,
> + ui_formats, ARRAY_SIZE(ui_formats));
> + if (ret >= 0)
> + ret = de2_one_plane_init(drm, &lcd->planes[DE2_CURSOR_PLANE],
> + DRM_PLANE_TYPE_CURSOR, possible_crtcs,
> + ui_formats, ARRAY_SIZE(ui_formats));
Nothing looks really special about that cursor plane. Any reasion not
to make it an overlay?
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
--
You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
For more options, visit https://groups.google.com/d/optout.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH] ARM: dt: sun8i-h3: Add sunxi-sid to dts for sun8i-h3
From: Maxime Ripard @ 2016-10-24 14:05 UTC (permalink / raw)
To: LABBE Corentin
Cc: Jean-Francois Moine, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, wens-jdAy2FN1RRM,
devicetree-u79uwXL29TY76Z2rM5mHXA, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161023082631.GA28485@Red>
[-- Attachment #1: Type: text/plain, Size: 2661 bytes --]
On Sun, Oct 23, 2016 at 10:26:31AM +0200, LABBE Corentin wrote:
> On Thu, Oct 20, 2016 at 10:36:54PM +0200, Maxime Ripard wrote:
> > On Wed, Oct 19, 2016 at 09:40:16AM +0200, LABBE Corentin wrote:
> > > On Wed, Oct 05, 2016 at 12:21:30PM +0200, Jean-Francois Moine wrote:
> > > > On Wed, 5 Oct 2016 11:48:24 +0200
> > > > Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > > >
> > > > > This patch add support for the sunxi-sid driver to the device tree for sun8i-h3.
> > > > >
> > > > > Signed-off-by: Corentin Labbe <clabbe.montjoie-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > > > > ---
> > > > > arch/arm/boot/dts/sun8i-h3.dtsi | 5 +++++
> > > > > 1 file changed, 5 insertions(+)
> > > > >
> > > > > diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > > > index 9f58bb4..abfd29c 100644
> > > > > --- a/arch/arm/boot/dts/sun8i-h3.dtsi
> > > > > +++ b/arch/arm/boot/dts/sun8i-h3.dtsi
> > > > > @@ -211,6 +211,11 @@
> > > > > #size-cells = <0>;
> > > > > };
> > > > >
> > > > > + sid: eeprom@01c14200 {
> > > > > + compatible = "allwinner,sun7i-a20-sid";
> > > > > + reg = <0x01c14200 0x200>;
> > > >
> > > > The datasheet says 1Kb starting at 0x01c14000.
> > > > Is there any reason to reduce the area and to shift the offset?
> > > >
> > >
> > > According to http://linux-sunxi.org/SID_Register_Guide "For
> > > Allwinner A83T and H3 the SID address space starts at 0x01c14000,
> > > and the e-fuses are at offset 0x200".
> > >
> > > So I use this offset, since the sunxi_sid driver need the base
> > > address of e-fuses.
> > >
> > > The easiest solution is to use 0x01c14200 since the other part of
> > > sid is not used and not known (A83T/H3 user manual doesnt give any
> > > information on all sid space, worse for A64 which reference SID only
> > > in memory map).
> > >
> > > So probably for H3/A64/A83T, there will never any usage of the rest
> > > of the SID address space.
> >
> > And since we can't know that, and we have to maintain the DT ABI,
> > using the whole address map and an offset, with a new compatible, is
> > definetely the safest thing to do.
> >
>
> I have two way of doing it, which one do you prefer ?
>
> - Adding two optionnal properties: efuses-offset and efuses-size defaulting to 0 and resourcesize.
> - Adding a subnode called efuses with its own reg=<>
>
> The first one is easy and didnt need any work on previous DT entries.
I'd prefer to have a compatible, and the size and/or offset of the
efuses associated to it.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v3] pinctrl: Add SX150X GPIO Extender Pinctrl Driver
From: Linus Walleij @ 2016-10-24 14:39 UTC (permalink / raw)
To: Andrey Smirnov, Neil Armstrong
Cc: Peter Rosin, linux-kernel@vger.kernel.org,
linux-gpio@vger.kernel.org, devicetree@vger.kernel.org,
Roland Stigge, Vladimir Zapolskiy
In-Reply-To: <CAHQ1cqGLQ=DdhXg1ebkgBbLN8P2P8BEDrGGTx9_r+6=Wy3uUWA@mail.gmail.com>
On Mon, Oct 24, 2016 at 6:51 AM, Andrey Smirnov
<andrew.smirnov@gmail.com> wrote:
> It seem strange to me that the driver uses "handle_edge_irq", given
> how none of the individual interrupts seem to require any ACKing,
> since it is all handled in sx150x_irq_thread_fn(), line 533. More so,
> I had trouble finding who/where sets .irq_ack() callback, which AFAIU
> is mandatory for handle_edge_irq().
Yes that looks strange.
Neil have you tested IRQs with this code?
If there is trouble, please follow up with a fix for the edge handler.
Maybe it should just be handle_simple_irq().
Yours,
Linus Walleij
^ permalink raw reply
* [PATCH] ARM64: dts: bcm2835: Fix bcm2837 compatible string
From: Andreas Färber @ 2016-10-24 15:09 UTC (permalink / raw)
To: linux-rpi-kernel
Cc: Andreas Färber, Eric Anholt, Stephen Warren, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Florian Fainelli,
Ray Jui, Scott Branden, bcm-kernel-feedback-list, devicetree,
linux-arm-kernel, linux-kernel
bcm2837-rpi-3-b.dts, its only in-tree user, was overriding it as
"brcm,bcm2837" already.
Fixes: 9d56c22a7861 ("ARM: bcm2835: Add devicetree for the Raspberry Pi 3.")
Cc: Eric Anholt <eric@anholt.net>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>
---
arch/arm64/boot/dts/broadcom/bcm2837.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
index 8216bbb29fe0..c1f719b7097a 100644
--- a/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcm2837.dtsi
@@ -1,7 +1,7 @@
#include "bcm283x.dtsi"
/ {
- compatible = "brcm,bcm2836";
+ compatible = "brcm,bcm2837";
soc {
ranges = <0x7e000000 0x3f000000 0x1000000>,
--
2.6.6
^ permalink raw reply related
* Re: [PATCH 2/5] ARM: davinci: Don't append git rev to local version
From: David Lechner @ 2016-10-24 15:15 UTC (permalink / raw)
To: Sekhar Nori, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20f3efba-4f79-3675-d2ce-09efe90fb692-l0cyMroinI0@public.gmane.org>
On 10/24/2016 06:35 AM, Sekhar Nori wrote:
> On Saturday 22 October 2016 12:06 AM, David Lechner wrote:
>> In the davinci default configuration, don't append the git revision to
>> the local kernel version by. This seems like the more desirable default
>> value.
>
> Why? To the contrary I actually quite like the fact that the git commit
> is appended to version string. Makes it easy for me to cross-check that
> I am booting the right image.
>
>>
>> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
>
> Thanks,
> Sekhar
>
Each time you make a commit, you get a new version, which installs
another copy of the kernel modules on the device. This will fill up the
SD card if you are making many commits.
Also, if someone wants to build the mainline kernel using the default
configuration, it seems odd to have a git revision tacked on to the end
even though you made no revisions.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [RFC v2 2/2] mmc: sdhci: Ignore capability register when it comes to speeds and use DT binding instead when sdhci-cap-speed-modes-broken is set.
From: Zach Brown @ 2016-10-24 15:48 UTC (permalink / raw)
To: Adrian Hunter
Cc: ulf.hansson, robh+dt, mark.rutland, linux-mmc, devicetree,
linux-kernel
In-Reply-To: <d4547457-036a-dbb7-ddb8-b839e04949b7@intel.com>
On Mon, Oct 24, 2016 at 10:34:46AM +0300, Adrian Hunter wrote:
> On 22/10/16 00:35, Zach Brown wrote:
> > When the sdhci-cap-speed-modes-broken DT property is set, the driver
> > will ignore the bits of the capability registers that correspond to
> > speed modes.
> >
> > Signed-off-by: Zach Brown <zach.brown@ni.com>
> > ---
> > drivers/mmc/host/sdhci.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
> > index 1e25b01..59c62d3 100644
> > --- a/drivers/mmc/host/sdhci.c
> > +++ b/drivers/mmc/host/sdhci.c
> > @@ -22,6 +22,7 @@
> > #include <linux/scatterlist.h>
> > #include <linux/regulator/consumer.h>
> > #include <linux/pm_runtime.h>
> > +#include <linux/of.h>
> >
> > #include <linux/leds.h>
> >
> > @@ -3013,10 +3014,19 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
> >
> > host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
> >
> > + if (of_property_read_bool(mmc_dev(host->mmc)->of_node,
> > + "sdhci-cap-speed-modes-broken"))
>
> It rather begs the question: if you are going to do something sdhci
> specific, why not just read the whole of the caps register from DT?
>
Throwing out the whole of the caps register seems like overkill. Also
there are some things set by the caps that are not available in the DT.
For example, SDHCI_CAN_64BIT is set by the cap register and is used in
sdhci_setup_host to set host->flags SDHCI_USE_64_BIT_DMA.
^ permalink raw reply
* Re: [PATCH 5/5] ARM: dts: Add LEGO MINDSTORTMS EV3 dts
From: David Lechner @ 2016-10-24 15:50 UTC (permalink / raw)
To: Sekhar Nori, Kevin Hilman
Cc: Rob Herring, Mark Rutland, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <b0022fad-a96e-86d4-71ba-2b803e5421fe-l0cyMroinI0@public.gmane.org>
On 10/24/2016 06:58 AM, Sekhar Nori wrote:
> On Saturday 22 October 2016 12:06 AM, David Lechner wrote:
>> This adds a device tree definition file for LEGO MINDSTORMS EV3.
>
> Thanks for the patch!
>
>>
>> What is working:
>>
>> * Pin muxing
>> * MicroSD card reader
>> * UART on input port 1
>>
>> What is partially working:
>>
>> * Buttons - working after GPIO fix
>> * LEDs - working after GPIO fix
>> * Poweroff/reset - working after GPIO fix
>
> Is the GPIO fix something that will go in v4.9-rc cycle ?
Not sure. This is still being discussed.
http://www.gossamer-threads.com/lists/linux/kernel/2550178
>
>> * Flash memory - driver loads but can't read the block devices - this is
>> probably due to the fact that we are not able to configure the SPI to
>> use DMA via device tree
>
> Hmm, I would not have expected PIO mode to be so inefficient that you
> are unable to even read the block device.
I am getting a -EIO error. I haven't been able to trace down exactly
what is causing it yet though.
>
...
>> +/ {
>> + compatible = "lego,ev3", "ti,da850";
>> + model = "LEGO MINDSTORMS EV3";
>> +
>> + soc@1c00000 {
>> + /*
>> + * (ab)using pinctrl-single to disable all internal pullups/
>> + * pulldowns on I/O.
>> + */
>> + pinmux@22c00c {
>> + compatible = "pinctrl-single";
>> + reg = <0x22c00c 0x4>;
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + pinctrl-single,bit-per-mux;
>> + pinctrl-single,register-width = <32>;
>> + pinctrl-single,function-mask = <0xf>;
>> + /*
>> + * There is a bug in pinctrl-single that prevents us
>> + * from setting function-mask to 1, so doing things
>> + * in groups of 4. Doesn't really matter since we are
>> + * disabling all at once anyway.
>> + */
>> +
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pupu_disable>;
>> +
>> + pupu_disable: pinmux_all_pins {
>> + pinctrl-single,bits = <
>> + 0x0 0x00000000 0xffffffff
>> + >;
>> + };
>
> Sigh. This is quite an abuse :)
>
> I know we don't have a good way to configure this in kernel today. And I
> am surprised we never had to care about disabling pullups so far. Can
> you clarify why you need it? I assume there is some contention you want
> to avoid, but on which interface?
The EV3 was designed with external pullup/pulldown everywhere. I know
for certain that it breaks one of the buttons if you do not disable the
internal ones. I imagine that it would have subtle effects elsewhere if
they are not disabled.
I have not gone through each pullup/pulldown bank individually, but it
would not surprise me at all if there was at least one thing on most of
them that would be adversely affected.
>
> I dont think this can be done this way using pinctrl-single. A small
> driver to handle pullup/down control for da850 may have to be added to
> drivers/pinctrl. It will be better to check with Linus Walleij on his
> thoughts using a new thread ccing the pinctrl subsystem list as well.
I will be glad to try to make a driver, but when I ran into this problem
I could not find much information on how to handle banks of
pullup/pulldown. Most of what I saw was for ones that can be
individually controlled. If anyone knows something like this already
that I could look at, it would be helpful to me.
> [...]
>
>> + in1_pins: pinmux_in1_pins {
>> + pinctrl-single,bits = <
>> + /* GP0[15] */
>> + 0x0 0x00000008 0x0000000f
>> + /* GP0[2] */
>> + 0x4 0x00800000 0x00f00000
>> + /* GP2[2] */
>> + 0x18 0x00800000 0x00f00000
>> + /* GP8[10], GP8[11] */
>> + 0x48 0x88000000 0xff000000
>> + >;
>> + };
>
> I see that this is not really used. Can you add these when you actually
> use them. Looks like that applies to some other definitions like this below.
It will be possible to uses these gpios via sysfs (until a proper driver
for input and output ports is merged). So how about I attach these to
the gpio node for now?
>
>> +&ehrpwm1 {
>> + status = "disabled";
>
> Hmm, disabled? Can you add this node when you actually use it?
Not sure why I have this disabled. Like the gpios, the pwms can be used
via sysfs, so I would like to leave them.
>
>> + pinctrl-names = "default";
>> + /* MBPWM, MAPWM */
>> + pinctrl-0 = <&ehrpwm1a_pins>, <&ehrpwm1b_pins>;
>> +};
>> +
>> +&ecap1 {
>> + status = "disabled";
>
> same here and other places below.
>
>> + pinctrl-names = "default";
>> + /* MDPWM */
>> + pinctrl-0 = <&ecap1_pins>;
>> +};
>> +
>> +&spi0 {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spi0_pins>, <&spi0_cs0_pin>, <&spi0_cs3_pin>;
>> + dmas = <&edma0 14 0>, <&edma0 15 0>;
>> + dma-names = "rx", "tx";
>> +
>> + spi-flash@0 {
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + compatible = "n25q128a13", "jedec,spi-nor";
>> + reg = <0>;
>> + spi-max-frequency = <50000000>;
>> + ti,spi-wdelay = <8>;
>> +
>> + partition@0 {
>> + label = "U-Boot";
>> + reg = <0 0x40000>;
>
> Thats 256KB for U-Boot and MLO (I assume in concatenated AIS image). Is
> that sufficient for future too? Moving partitions later is tough ask
> because that means users will lose data when they upgrade the kernel
> because of partitions moving around. Just a suggestion to keep future
> U-Boot bloat in mind and not use a "just fits" number.
The MLO is on an EEPROM in the EV3, so the U-Boot partition is just
U-boot. The SoC boots from I2C, which then runs whatever is as 0x0 on
the flash memory.
This partition table matches the partition scheme used on the official
LEGO firmware that ships with the devices. Most people running their own
kernel will probably be loading it from a microSD card, leaving the
official firmware intact and therefore will always have this partition
table.
My thinking is that if someone does want to use a different partitioning
scheme, they can build their own U-Boot and configure it to modify the
device tree with a new partition table.
The way the LEGO firmware flashing utility works, it wipes out the
entire flash memory each time you flash the firmware. So, data loss is
not a concern - you will loose your data anyway.
>
>> + };
>> +
>> + partition@40000 {
>> + label = "U-Boot Env";
>> + reg = <0x40000 0x10000>;
>> + };
>> +
>> + partition@50000 {
>> + label = "Kernel";
>> + reg = <0x50000 0x200000>;
>> + };
>> +
>> + partition@250000 {
>> + label = "Filesystem";
>> + reg = <0x250000 0xa50000>;
>> + };
>> +
>> + partition@cb0000 {
>> + label = "Storage";
>> + reg = <0xcb0000 0x2f0000>;
>> + };
>> + };
>> +
>> + /* TODO: ADC goes here */
>
> I would drop this comment.
ack
>
>> +};
>> +
>> +&spi1 {
>> + status = "okay";
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spi1_pins>, <&spi1_cs0_pin>;
>> +
>> + /* TODO: LCD Display goes here */
>
> Add this node when you actually have display working.
What if we set this up as a spidev node instead? This way the display
could be used from userspace without a driver.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH V7 2/6] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Stefan Wahren @ 2016-10-24 16:21 UTC (permalink / raw)
To: kernel
Cc: Mark Rutland, devicetree, Florian Fainelli, Russell King,
Pawel Moll, Stephen Warren, Catalin Marinas, linux-pm, Lee Jones,
Will Deacon, Eduardo Valentin, Eric Anholt, Rob Herring,
linux-rpi-kernel, Zhang Rui, linux-arm-kernel
In-Reply-To: <87twczg27x.fsf@eliezer.anholt.net>
Hi Martin,
Am 28.09.2016 um 23:10 schrieb Eric Anholt:
> kernel@martin.sperl.org writes:
>
>> From: Martin Sperl <kernel@martin.sperl.org>
>>
>> Add basic thermal driver for bcm2835 SOC.
>>
>> This driver currently relies on the firmware setting up the
>> tsense HW block and does not set it up itself.
>>
>> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
>> Acked-by: Eric Anholt <eric@anholt.net>
>> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
> What's the status of merging this one? I'd like to merge the other
> patches.
i think it's necessary to rebase the whole series. Maybe we could get it
into 4.10.
Stefan
^ permalink raw reply
* Re: [PATCH V7 2/6] thermal: bcm2835: add thermal driver for bcm2835 soc
From: Eric Anholt @ 2016-10-24 16:38 UTC (permalink / raw)
To: Stefan Wahren, kernel
Cc: Zhang Rui, Eduardo Valentin, Rob Herring, Pawel Moll,
Mark Rutland, Stephen Warren, Lee Jones, Russell King,
Florian Fainelli, Catalin Marinas, Will Deacon, linux-pm,
devicetree, linux-rpi-kernel, linux-arm-kernel
In-Reply-To: <eaff4043-5a62-da2d-cee1-9962b8c4783a@i2se.com>
[-- Attachment #1: Type: text/plain, Size: 831 bytes --]
Stefan Wahren <stefan.wahren@i2se.com> writes:
> Hi Martin,
>
> Am 28.09.2016 um 23:10 schrieb Eric Anholt:
>> kernel@martin.sperl.org writes:
>>
>>> From: Martin Sperl <kernel@martin.sperl.org>
>>>
>>> Add basic thermal driver for bcm2835 SOC.
>>>
>>> This driver currently relies on the firmware setting up the
>>> tsense HW block and does not set it up itself.
>>>
>>> Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
>>> Acked-by: Eric Anholt <eric@anholt.net>
>>> Acked-by: Stefan Wahren <stefan.wahren@i2se.com>
>> What's the status of merging this one? I'd like to merge the other
>> patches.
>
> i think it's necessary to rebase the whole series. Maybe we could get it
> into 4.10.
Why would it need to be rebased? The status, as far as I know, is that
we're still waiting for the subsystem maintainer to respond.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 800 bytes --]
^ permalink raw reply
* [PATCH/RFT v2 00/17] Add DT support for ohci-da8xx
From: ahaslam @ 2016-10-24 16:46 UTC (permalink / raw)
To: gregkh, johan, robh+dt, nsekhar, stern, khilman, sshtylyov, david,
manjunath.goudar, broonie, abailon
Cc: linux-usb, devicetree, linux-kernel, linux-arm-kernel,
Axel Haslam
From: Axel Haslam <ahaslam@baylibre.com>
The purpose of this patch series is to add DT support and modernize
the ohci-da8xx glue driver without breaking the non-DT boot,
which is still used in unconverted davinci devices.
The first couple of patches, are the recent and ongoing efforts from
David Lechner to clean up davinci-mach code and the ochi-da8xx driver,
Im including these patches on this series for completeness sake.
Then I re-based an old patch by Manjunath Goudar[4] to be able to build
the driver as a module. We can now add this patch because we removed
references to sysconf registers by using David's patches.
Then I prepare the stage for a DT boot which does not depend on any
mach-arch/* callbacks by using a regulator to handle the vbus and
over current gpios. For this, i extended the fixed regulator driver to
register for an irq and send a regulator notification if an over curent
pin is specified.
The only dependency left for this series is the recently re-posted patch
by David to remove references to mach-code[1], which is approved and
should be picked up soon.
Note 1: Testing was done on a omap138-lcdk board, using DT, and non-DT boot,
and checking that in both cases the hub, usb mass storage and an input
device are correctly enumerated and working. The omap138-lcdk does not
have gpios to control vbus and get over current interrupt notifications.
If anyone has a da830-evm based board and could confirm that ohci is
correctly working, i would appreciate it.
(the OHCI option needs to be enabled in menuconfig)
Note 2: It seems that the davinci-gpio driver is broken for DT based boot
and any gpio > 32. (luckly none of the DT based boards use gpios yet)
The issue is discussed here [2]
Note 3: A git branch based on tag: next-20161021 with the dependencies
is available in my github here [3].
[1] usb: ohci-da8xx: Remove code that references mach
http://marc.info/?l=linux-kernel&m=147632744323084&w=4
[2] thread about invalid gpio in davinci
http://www.gossamer-threads.com/lists/linux/kernel/2550178
[3] Git branch:
https://github.com/axelhaslamx/linux-axel/commits/ohci-da8xx-dt-v2.1
[4] Separate ohci-da8xx driver patch
https://patches.linaro.org/patch/18234/
Changes from v1->v2
* Rebased and added patch to make ohci a separate driver
* Use a regulator instead of handling Gpios (David Lechner)
* Add an overcurrent mode to regulator framework
* Fixed regulator is able to register for and overcurrent irq
* Added patch by Alexandre to remove build warnings
* Moved global variables into private hcd structure.
Alexandre Bailon (1):
ARM: davinci: da8xx: Fix some redefined symbol warnings
Axel Haslam (10):
ARM: davinci: da8xx: Enable the usb20 "per" clk on phy_clk_enable
ARM: davinci: hawk: add full constraints for ohci plat boot
regulator: fixed: Add over current event
USB: da8xx: use flag instead of bitmask for over current change
USB: ochi-da8xx: Use a regulator for vbus/overcurrent
USB: da8xx: use ohci priv data instead of globals
ARM: davinci: register the usb20_phy clock on the DT file
usb: host: ohci-da8xx: Add devicetree bindings documentation
USB: ohci-da8xx: Allow probing from DT
ARM: dts: da850: add usb device node
David Lechner (5):
ARM: davinci: da8xx: add usb phy clocks
ARM: davinci: da8xx: Add CFGCHIP syscon platform declaration.
ARM: davinci: da8xx: Add USB PHY platform declaration
ARM: DTS: da850: Add cfgchip syscon node
ARM: DTS: da850: Add usb phy node
Manjunath Goudar (1):
USB: OHCI: make ohci-da8xx a separate driver
.../bindings/regulator/fixed-regulator.txt | 4 +
.../devicetree/bindings/usb/ohci-da8xx.txt | 39 +++
arch/arm/boot/dts/da850-lcdk.dts | 8 +
arch/arm/boot/dts/da850.dtsi | 17 +
arch/arm/mach-davinci/board-da830-evm.c | 152 +++-----
arch/arm/mach-davinci/board-da850-evm.c | 4 +
arch/arm/mach-davinci/board-mityomapl138.c | 4 +
arch/arm/mach-davinci/board-omapl138-hawk.c | 122 ++-----
arch/arm/mach-davinci/da8xx-dt.c | 2 +
arch/arm/mach-davinci/devices-da8xx.c | 28 ++
arch/arm/mach-davinci/include/mach/da8xx.h | 8 +-
arch/arm/mach-davinci/usb-da8xx.c | 244 ++++++++++++-
drivers/regulator/fixed.c | 64 ++++
drivers/usb/host/Kconfig | 2 +-
drivers/usb/host/Makefile | 1 +
drivers/usb/host/ohci-da8xx.c | 382 +++++++++++----------
drivers/usb/host/ohci-hcd.c | 18 -
include/linux/platform_data/usb-davinci.h | 43 ---
include/linux/regulator/consumer.h | 5 +
include/linux/regulator/fixed.h | 3 +
20 files changed, 703 insertions(+), 447 deletions(-)
create mode 100644 Documentation/devicetree/bindings/usb/ohci-da8xx.txt
--
1.9.1
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox