* [PATCH 1/2] DT: binding: bcm2835-mbox: fix address typo in example
From: Stefan Wahren @ 2016-10-26 18:13 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Stephen Warren, Eric Anholt
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Stefan Wahren
The address of the mailbox node in the example has a typo.
So fix it accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren-eS4NqCHxEME@public.gmane.org>
Fixes: d4b5c782b9f4 ("dt/bindings: Add binding for the BCM2835 mailbox driver")
---
.../bindings/mailbox/brcm,bcm2835-mbox.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
index e893615..b48d7d3 100644
--- a/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
+++ b/Documentation/devicetree/bindings/mailbox/brcm,bcm2835-mbox.txt
@@ -12,7 +12,7 @@ Required properties:
Example:
-mailbox: mailbox@7e00b800 {
+mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/2] ARM: dts: bcm283x: fix typo in mailbox address
From: Stefan Wahren @ 2016-10-26 18:14 UTC (permalink / raw)
To: Mark Rutland, Rob Herring, Stephen Warren, Eric Anholt
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rpi-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Stefan Wahren
In-Reply-To: <1477505640-26658-1-git-send-email-stefan.wahren-eS4NqCHxEME@public.gmane.org>
The address of the mailbox node in the bcm283x.dts has also a typo.
So fix it accordingly.
Signed-off-by: Stefan Wahren <stefan.wahren-eS4NqCHxEME@public.gmane.org>
Fixes: 05b682b7a3b2 ("ARM: bcm2835: dt: Add the mailbox to the device tree")
---
arch/arm/boot/dts/bcm283x.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm283x.dtsi b/arch/arm/boot/dts/bcm283x.dtsi
index 46d46d8..74dd21b 100644
--- a/arch/arm/boot/dts/bcm283x.dtsi
+++ b/arch/arm/boot/dts/bcm283x.dtsi
@@ -104,7 +104,7 @@
reg = <0x7e104000 0x10>;
};
- mailbox: mailbox@7e00b800 {
+ mailbox: mailbox@7e00b880 {
compatible = "brcm,bcm2835-mbox";
reg = <0x7e00b880 0x40>;
interrupts = <0 1>;
--
1.7.9.5
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH V2 08/10] watchdog: da9062/61: watchdog driver
From: Guenter Roeck @ 2016-10-26 18:59 UTC (permalink / raw)
To: Steve Twiss
Cc: LINUX-KERNEL, LINUX-WATCHDOG, Wim Van Sebroeck, DEVICETREE,
Dmitry Torokhov, Eduardo Valentin, LINUX-INPUT, LINUX-PM,
Lee Jones, Liam Girdwood, Mark Brown, Mark Rutland, Rob Herring,
Support Opensource, Zhang Rui
In-Reply-To: <ecd0c36a9e1766e327b54afa6bf986e64890b881.1477501000.git.stwiss.opensource@diasemi.com>
On Wed, Oct 26, 2016 at 05:56:39PM +0100, Steve Twiss wrote:
> From: Steve Twiss <stwiss.opensource@diasemi.com>
>
> The of_device_id match array is added to support "dlg,da9062-watchdog"
> as a valid .compatible string.
>
> The watchdog_info structure is linked to this device tree compatible
> string in the .data section. Extra code is added into the probe function to
> search-for and assign this match data.
>
> This patch now assumes the use of a DA9062 fallback compatible string for
> the DTS to pick up the DA9062 device driver for use with the DA9061
> watchdog hardware.
>
> Copyright header is updated to add DA9061 in its description and the module
> description macro is extended to include DA9061.
>
> Kconfig is updated to reflect support for DA9061/62.
>
> Signed-off-by: Steve Twiss <stwiss.opensource@diasemi.com>
>
> ---
> This patch applies against linux-next and v4.8
>
> v1 -> v2
> - Patch renamed from [PATCH V1 04/10] to [PATCH V2 08/10] -- these
> changes were made to fix checkpatch warnings caused by the patch
> set dependency order
> - Removal of the DA9061 compatible entries for this device driver.
> - Additional explanation in the patch description for the use of a
> fall-back compatible DTS string
>
> Guenter,
>
> Alterations have been made in accordance with the previous e-mail thread
> on the use of compatible strings: https://lkml.org/lkml/2016/10/7/641
> This patch now assumes the use of a fallback compatible string in the DTS.
> Of the form: compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog";
>
> Regards,
> Steve Twiss, Dialog Semiconductor Ltd.
>
>
> drivers/watchdog/Kconfig | 4 ++--
> drivers/watchdog/da9062_wdt.c | 18 +++++++++++++++---
> 2 files changed, 17 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
> index 1bffe00..d6b4088 100644
> --- a/drivers/watchdog/Kconfig
> +++ b/drivers/watchdog/Kconfig
> @@ -104,11 +104,11 @@ config DA9063_WATCHDOG
> This driver can be built as a module. The module name is da9063_wdt.
>
> config DA9062_WATCHDOG
> - tristate "Dialog DA9062 Watchdog"
> + tristate "Dialog DA9062/61 Watchdog"
> depends on MFD_DA9062
> select WATCHDOG_CORE
> help
> - Support for the watchdog in the DA9062 PMIC.
> + Support for the watchdog in the DA9062 and DA9061 PMICs.
>
> This driver can be built as a module. The module name is da9062_wdt.
>
> diff --git a/drivers/watchdog/da9062_wdt.c b/drivers/watchdog/da9062_wdt.c
> index 7386111..4b20b7a 100644
> --- a/drivers/watchdog/da9062_wdt.c
> +++ b/drivers/watchdog/da9062_wdt.c
> @@ -1,5 +1,5 @@
> /*
> - * da9062_wdt.c - WDT device driver for DA9062
> + * Watchdog device driver for DA9062 and DA9061 PMICs
> * Copyright (C) 2015 Dialog Semiconductor Ltd.
> *
> * This program is free software; you can redistribute it and/or
> @@ -188,23 +188,34 @@ static const struct watchdog_ops da9062_watchdog_ops = {
> .set_timeout = da9062_wdt_set_timeout,
> };
>
> +static const struct of_device_id da9062_compatible_id_table[] = {
> + { .compatible = "dlg,da9062-watchdog", .data = &da9062_watchdog_info },
> + { },
> +};
> +
> static int da9062_wdt_probe(struct platform_device *pdev)
> {
> int ret;
> struct da9062 *chip;
> struct da9062_watchdog *wdt;
> + const struct of_device_id *match;
>
> chip = dev_get_drvdata(pdev->dev.parent);
> if (!chip)
> return -EINVAL;
>
> + match = of_match_node(da9062_compatible_id_table,
> + pdev->dev.of_node);
> + if (!match)
> + return -ENXIO;
> +
> wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
> if (!wdt)
> return -ENOMEM;
>
> wdt->hw = chip;
>
> - wdt->wdtdev.info = &da9062_watchdog_info;
> + wdt->wdtdev.info = (const struct watchdog_info *)match->data;
I don't see why you would need match->data or of_match_node above.
Guenter
> wdt->wdtdev.ops = &da9062_watchdog_ops;
> wdt->wdtdev.min_timeout = DA9062_WDT_MIN_TIMEOUT;
> wdt->wdtdev.max_timeout = DA9062_WDT_MAX_TIMEOUT;
> @@ -244,11 +255,12 @@ static struct platform_driver da9062_wdt_driver = {
> .remove = da9062_wdt_remove,
> .driver = {
> .name = "da9062-watchdog",
> + .of_match_table = da9062_compatible_id_table,
> },
> };
> module_platform_driver(da9062_wdt_driver);
>
> MODULE_AUTHOR("S Twiss <stwiss.opensource@diasemi.com>");
> -MODULE_DESCRIPTION("WDT device driver for Dialog DA9062");
> +MODULE_DESCRIPTION("WDT device driver for Dialog DA9062 and DA9061");
> MODULE_LICENSE("GPL");
> MODULE_ALIAS("platform:da9062-watchdog");
> --
> end-of-patch for PATCH V2
>
^ permalink raw reply
* [RFC 3/3] regulator: fixed: dt: Allow an optional over current pin
From: ahaslam @ 2016-10-26 19:00 UTC (permalink / raw)
To: broonie, lgirdwood, khilman, nsekhar, david
Cc: linux-kernel, Axel Haslam, devicetree
In-Reply-To: <20161026190054.11968-1-ahaslam@baylibre.com>
From: Axel Haslam <ahaslam@baylibre.com>
Add support for an optional over current input pin which
can be used to send an over current event to the regulator
consumer.
Cc: devicetree@vger.kernel.org
Signed-off-by: Axel Haslam <ahaslam@baylibre.com>
---
Documentation/devicetree/bindings/regulator/fixed-regulator.txt | 4 ++++
drivers/regulator/fixed.c | 8 ++++++++
2 files changed, 12 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
index 4fae41d..0c140cb 100644
--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -11,6 +11,8 @@ If this property is missing, the default assumed is Active low.
- gpio-open-drain: GPIO is open drain type.
If this property is missing then default assumption is false.
-vin-supply: Input supply name.
+- oc-gpio: Input gpio that signals an over current condition.
+- oc-active-high: The polarity of the over current pin is high.
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
@@ -26,9 +28,11 @@ Example:
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 16 0>;
+ oc-gpio = <&gpio1 18 0>;
startup-delay-us = <70000>;
enable-active-high;
regulator-boot-on;
gpio-open-drain;
+ oc-active-high;
vin-supply = <&parent_reg>;
};
diff --git a/drivers/regulator/fixed.c b/drivers/regulator/fixed.c
index 9937139..f02d24c 100644
--- a/drivers/regulator/fixed.c
+++ b/drivers/regulator/fixed.c
@@ -86,6 +86,14 @@ struct fixed_voltage_data {
if ((config->gpio < 0) && (config->gpio != -ENOENT))
return ERR_PTR(config->gpio);
+ config->oc_gpio = of_get_named_gpio(np, "oc-gpio", 0);
+ if (gpio_is_valid(config->oc_gpio))
+ config->has_oc_gpio = true;
+ else if (config->oc_gpio != -ENOENT)
+ return ERR_PTR(config->oc_gpio);
+
+ config->oc_high = of_property_read_bool(np, "oc-active-high");
+
of_property_read_u32(np, "startup-delay-us", &config->startup_delay);
config->enable_high = of_property_read_bool(np, "enable-active-high");
--
1.9.1
^ permalink raw reply related
* Re: [RFC PATCH 1/5] of: introduce the overlay manager
From: Thomas Petazzoni @ 2016-10-26 19:02 UTC (permalink / raw)
To: Mathieu Poirier
Cc: Antoine Tenart, Maxime Ripard, pantelis.antoniou, Mark Rutland,
sboyd, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <CANLsYkyszsn2TLYhUjHMt2ZnEUmE9eSc71W2KWBL0fWhh3PPBw@mail.gmail.com>
Hello,
On Wed, 26 Oct 2016 10:29:59 -0600, Mathieu Poirier wrote:
> > + overlay = devm_kzalloc(dev, sizeof(*overlay), GFP_KERNEL);
>
> Function devm_kzalloc() can sleep but you're holding a spinlock - I'm
> surprised the kernel didn't complain here. Allocate the memory before
> holding the lock. If the overly is already loaded simply free it on
> the error path.
Actually, I'm not sure using a spinlock here is appropriate. Using a
mutex would probably be better.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* [PATCH 0/5] add NS2 support to bgmac
From: Jon Mason @ 2016-10-26 19:35 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
Add support for the amac found in the Broadcom Northstar2 SoC to the
bgmac driver. This necessitates adding support to connect to an
externally defined phy (as described in the device tree) in the driver.
These phy changes are in addition to the changes necessary to get NS2
working.
This series (based on the net-next git tree) has been tested on NSP and
NS2 HW.
Jon Mason (4):
Documentation: devicetree: net: add NS2 bindings to amac
net: ethernet: bgmac: device tree phy enablement
net: ethernet: bgmac: add NS2 support
arm64: dts: NS2: add AMAC ethernet support
Vikas Soni (1):
net: phy: broadcom: Add BCM54810 phy entry
.../devicetree/bindings/net/brcm,amac.txt | 7 +-
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 +
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 +++
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 +++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 108 ++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 56 +----------
drivers/net/ethernet/broadcom/bgmac.h | 9 ++
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 65 +++++++++++++
include/linux/brcmphy.h | 7 ++
10 files changed, 264 insertions(+), 55 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCH 1/5] net: phy: broadcom: Add BCM54810 phy entry
From: Jon Mason @ 2016-10-26 19:35 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel, Vikas Soni
In-Reply-To: <1477510561-17035-1-git-send-email-jon.mason@broadcom.com>
From: Vikas Soni <vsoni@broadcom.com>
Add BCM54810 phy entry
Signed-off-by: Vikas Soni <vsoni@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/phy/Kconfig | 2 +-
drivers/net/phy/broadcom.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++
include/linux/brcmphy.h | 7 +++++
3 files changed, 73 insertions(+), 1 deletion(-)
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 45f68ea..31967ca 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -217,7 +217,7 @@ config BROADCOM_PHY
select BCM_NET_PHYLIB
---help---
Currently supports the BCM5411, BCM5421, BCM5461, BCM54616S, BCM5464,
- BCM5481 and BCM5482 PHYs.
+ BCM5481, BCM54810 and BCM5482 PHYs.
config CICADA_PHY
tristate "Cicada PHYs"
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 870327e..cdce761 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -35,6 +35,35 @@ static int bcm54xx_auxctl_write(struct phy_device *phydev, u16 regnum, u16 val)
return phy_write(phydev, MII_BCM54XX_AUX_CTL, regnum | val);
}
+static int bcm54810_config(struct phy_device *phydev)
+{
+ int rc;
+
+ /* Disable BroadR-Reach */
+ rc = bcm_phy_write_exp(phydev, BCM54810_EXP_BROADREACH_LRE_MISC_CTL, 0);
+ if (rc < 0)
+ return rc;
+
+ /* SKEW DISABLE */
+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+ 0xF0E0);
+ if (rc < 0)
+ return rc;
+
+ /* DELAY DISABLE */
+ rc = bcm54xx_auxctl_write(phydev, MII_BCM54XX_AUXCTL_SHDWSEL_MISC,
+ 0x7000);
+ if (rc < 0)
+ return rc;
+
+ /* DELAY DISABLE */
+ rc = bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, 0);
+ if (rc < 0)
+ return rc;
+
+ return 0;
+}
+
/* Needs SMDSP clock enabled via bcm54xx_phydsp_config() */
static int bcm50610_a0_workaround(struct phy_device *phydev)
{
@@ -207,6 +236,20 @@ static int bcm54xx_config_init(struct phy_device *phydev)
(phydev->dev_flags & PHY_BRCM_AUTO_PWRDWN_ENABLE))
bcm54xx_adjust_rxrefclk(phydev);
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810) {
+ err = bcm54810_config(phydev);
+ if (err)
+ return err;
+
+ reg = phy_read(phydev, MII_BMCR);
+ if (reg < 0)
+ return reg;
+
+ err = phy_write(phydev, MII_BMCR, reg & ~BMCR_PDOWN);
+ if (err)
+ return err;
+ }
+
bcm54xx_phydsp_config(phydev);
return 0;
@@ -334,6 +377,15 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
phy_write(phydev, 0x18, reg);
}
+ if (BRCM_PHY_MODEL(phydev) == PHY_ID_BCM54810 &&
+ phydev->dev_flags & PHY_BRCM_EXP_LANE_SWAP) {
+ /* LANE SWAP */
+ ret = bcm_phy_write_exp(phydev, MII_BCM54XX_EXP_SEL_ER + 0x9,
+ 0x11B);
+ if (ret < 0)
+ return ret;
+ }
+
return ret;
}
@@ -521,6 +573,18 @@ static struct phy_driver broadcom_drivers[] = {
.ack_interrupt = bcm_phy_ack_intr,
.config_intr = bcm_phy_config_intr,
}, {
+ .phy_id = PHY_ID_BCM54810,
+ .phy_id_mask = 0xfffffff0,
+ .name = "Broadcom BCM54810",
+ .features = PHY_GBIT_FEATURES |
+ SUPPORTED_Pause | SUPPORTED_Asym_Pause,
+ .flags = PHY_HAS_MAGICANEG | PHY_HAS_INTERRUPT,
+ .config_init = bcm54xx_config_init,
+ .config_aneg = bcm5481_config_aneg,
+ .read_status = genphy_read_status,
+ .ack_interrupt = bcm_phy_ack_intr,
+ .config_intr = bcm_phy_config_intr,
+}, {
.phy_id = PHY_ID_BCM5482,
.phy_id_mask = 0xfffffff0,
.name = "Broadcom BCM5482",
@@ -603,6 +667,7 @@ static struct mdio_device_id __maybe_unused broadcom_tbl[] = {
{ PHY_ID_BCM54616S, 0xfffffff0 },
{ PHY_ID_BCM5464, 0xfffffff0 },
{ PHY_ID_BCM5481, 0xfffffff0 },
+ { PHY_ID_BCM54810, 0xfffffff0 },
{ PHY_ID_BCM5482, 0xfffffff0 },
{ PHY_ID_BCM50610, 0xfffffff0 },
{ PHY_ID_BCM50610M, 0xfffffff0 },
diff --git a/include/linux/brcmphy.h b/include/linux/brcmphy.h
index e7a3d9d..40e6ead 100644
--- a/include/linux/brcmphy.h
+++ b/include/linux/brcmphy.h
@@ -13,6 +13,7 @@
#define PHY_ID_BCM5241 0x0143bc30
#define PHY_ID_BCMAC131 0x0143bc70
#define PHY_ID_BCM5481 0x0143bca0
+#define PHY_ID_BCM54810 0x03625d00
#define PHY_ID_BCM5482 0x0143bcb0
#define PHY_ID_BCM5411 0x00206070
#define PHY_ID_BCM5421 0x002060e0
@@ -55,6 +56,8 @@
#define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
#define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
#define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
+#define PHY_BRCM_EXP_LANE_SWAP 0x00010000
+
/* Broadcom BCM7xxx specific workarounds */
#define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)
#define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff)
@@ -187,6 +190,10 @@
#define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */
#define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */
+/* BCM54810 Registers */
+#define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90)
+#define BCM54810_SHD_CLK_CTL 0x3
+
/*****************************************************************************/
/* Fast Ethernet Transceiver definitions. */
--
2.7.4
^ permalink raw reply related
* [PATCH 2/5] Documentation: devicetree: net: add NS2 bindings to amac
From: Jon Mason @ 2016-10-26 19:35 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1477510561-17035-1-git-send-email-jon.mason@broadcom.com>
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
Documentation/devicetree/bindings/net/brcm,amac.txt | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/brcm,amac.txt b/Documentation/devicetree/bindings/net/brcm,amac.txt
index ba5ecc1..f92caee 100644
--- a/Documentation/devicetree/bindings/net/brcm,amac.txt
+++ b/Documentation/devicetree/bindings/net/brcm,amac.txt
@@ -2,15 +2,18 @@ Broadcom AMAC Ethernet Controller Device Tree Bindings
-------------------------------------------------------------
Required properties:
- - compatible: "brcm,amac" or "brcm,nsp-amac"
+ - compatible: "brcm,amac", "brcm,nsp-amac", or "brcm,ns2-amac"
- reg: Address and length of the GMAC registers,
Address and length of the GMAC IDM registers
+ Address and length of the NIC Port Manager registers (optional)
- reg-names: Names of the registers. Must have both "amac_base" and
- "idm_base"
+ "idm_base". "nicpm_base" is optional (required for NS2)
- interrupts: Interrupt number
Optional properties:
- mac-address: See ethernet.txt file in the same directory
+- brcm,enet-phy-lane-swap:
+ boolean; Swap the PHY lanes (needed on some SKUs of NS2)
Examples:
--
2.7.4
^ permalink raw reply related
* [PATCH 3/5] net: ethernet: bgmac: device tree phy enablement
From: Jon Mason @ 2016-10-26 19:35 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1477510561-17035-1-git-send-email-jon.mason@broadcom.com>
Change the bgmac driver to allow for phy's defined by the device tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
drivers/net/ethernet/broadcom/bgmac-bcma.c | 48 ++++++++++++++++++++++++
drivers/net/ethernet/broadcom/bgmac-platform.c | 48 +++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 51 +-------------------------
drivers/net/ethernet/broadcom/bgmac.h | 7 ++++
4 files changed, 104 insertions(+), 50 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-bcma.c b/drivers/net/ethernet/broadcom/bgmac-bcma.c
index c16ec3a..3e3efde 100644
--- a/drivers/net/ethernet/broadcom/bgmac-bcma.c
+++ b/drivers/net/ethernet/broadcom/bgmac-bcma.c
@@ -80,6 +80,50 @@ static void bcma_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset, u32 mask,
bcma_maskset32(bgmac->bcma.cmn, offset, mask, set);
}
+static int bcma_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+ char bus_id[MII_BUS_ID_SIZE + 3];
+
+ /* Connect to the PHY */
+ snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
+ bgmac->phyaddr);
+ phy_dev = phy_connect(bgmac->net_dev, bus_id, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "PHY connecton failed\n");
+ return PTR_ERR(phy_dev);
+ }
+
+ return 0;
+}
+
+static int bcma_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static const struct bcma_device_id bgmac_bcma_tbl[] = {
BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_4706_MAC_GBIT,
BCMA_ANY_REV, BCMA_ANY_CLASS),
@@ -275,6 +319,10 @@ static int bgmac_probe(struct bcma_device *core)
bgmac->cco_ctl_maskset = bcma_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = bcma_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = bcma_bgmac_cmn_maskset32;
+ if (bgmac->mii_bus)
+ bgmac->phy_connect = bcma_phy_connect;
+ else
+ bgmac->phy_connect = bcma_phy_direct_connect;
err = bgmac_enet_probe(bgmac);
if (err)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index be52f27..aed5dc5 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -16,6 +16,7 @@
#include <linux/bcma/bcma.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
+#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
@@ -86,6 +87,46 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static int platform_phy_connect(struct bgmac *bgmac)
+{
+ struct phy_device *phy_dev;
+
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
+ bgmac_adjust_link);
+ if (!phy_dev) {
+ dev_err(bgmac->dev, "Phy connect failed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int platform_phy_direct_connect(struct bgmac *bgmac)
+{
+ struct fixed_phy_status fphy_status = {
+ .link = 1,
+ .speed = SPEED_1000,
+ .duplex = DUPLEX_FULL,
+ };
+ struct phy_device *phy_dev;
+ int err;
+
+ phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
+ if (!phy_dev || IS_ERR(phy_dev)) {
+ dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
+ return -ENODEV;
+ }
+
+ err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
+ PHY_INTERFACE_MODE_MII);
+ if (err) {
+ dev_err(bgmac->dev, "Connecting PHY failed\n");
+ return err;
+ }
+
+ return err;
+}
+
static int bgmac_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
@@ -102,7 +143,6 @@ static int bgmac_probe(struct platform_device *pdev)
/* Set the features of the 4707 family */
bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
- bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
bgmac->feature_flags |= BGMAC_FEAT_CMDCFG_SR_REV4;
bgmac->feature_flags |= BGMAC_FEAT_TX_MASK_SETUP;
bgmac->feature_flags |= BGMAC_FEAT_RX_MASK_SETUP;
@@ -151,6 +191,12 @@ static int bgmac_probe(struct platform_device *pdev)
bgmac->cco_ctl_maskset = platform_bgmac_cco_ctl_maskset;
bgmac->get_bus_clock = platform_bgmac_get_bus_clock;
bgmac->cmn_maskset32 = platform_bgmac_cmn_maskset32;
+ if (of_parse_phandle(np, "phy-handle", 0)) {
+ bgmac->phy_connect = platform_phy_connect;
+ } else {
+ bgmac->phy_connect = platform_phy_direct_connect;
+ bgmac->feature_flags |= BGMAC_FEAT_FORCE_SPEED_2500;
+ }
return bgmac_enet_probe(bgmac);
}
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 856379c..38876ec 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1388,7 +1388,7 @@ static const struct ethtool_ops bgmac_ethtool_ops = {
* MII
**************************************************/
-static void bgmac_adjust_link(struct net_device *net_dev)
+void bgmac_adjust_link(struct net_device *net_dev)
{
struct bgmac *bgmac = netdev_priv(net_dev);
struct phy_device *phy_dev = net_dev->phydev;
@@ -1412,50 +1412,6 @@ static void bgmac_adjust_link(struct net_device *net_dev)
}
}
-static int bgmac_phy_connect_direct(struct bgmac *bgmac)
-{
- struct fixed_phy_status fphy_status = {
- .link = 1,
- .speed = SPEED_1000,
- .duplex = DUPLEX_FULL,
- };
- struct phy_device *phy_dev;
- int err;
-
- phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, -1, NULL);
- if (!phy_dev || IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
- return -ENODEV;
- }
-
- err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (err) {
- dev_err(bgmac->dev, "Connecting PHY failed\n");
- return err;
- }
-
- return err;
-}
-
-static int bgmac_phy_connect(struct bgmac *bgmac)
-{
- struct phy_device *phy_dev;
- char bus_id[MII_BUS_ID_SIZE + 3];
-
- /* Connect to the PHY */
- snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, bgmac->mii_bus->id,
- bgmac->phyaddr);
- phy_dev = phy_connect(bgmac->net_dev, bus_id, &bgmac_adjust_link,
- PHY_INTERFACE_MODE_MII);
- if (IS_ERR(phy_dev)) {
- dev_err(bgmac->dev, "PHY connecton failed\n");
- return PTR_ERR(phy_dev);
- }
-
- return 0;
-}
-
int bgmac_enet_probe(struct bgmac *info)
{
struct net_device *net_dev;
@@ -1507,10 +1463,7 @@ int bgmac_enet_probe(struct bgmac *info)
netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
- if (!bgmac->mii_bus)
- err = bgmac_phy_connect_direct(bgmac);
- else
- err = bgmac_phy_connect(bgmac);
+ err = bgmac_phy_connect(bgmac);
if (err) {
dev_err(bgmac->dev, "Cannot connect to phy\n");
goto err_dma_free;
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index 80836b4..ea52ac3 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -513,10 +513,12 @@ struct bgmac {
u32 (*get_bus_clock)(struct bgmac *bgmac);
void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
u32 set);
+ int (*phy_connect)(struct bgmac *bgmac);
};
int bgmac_enet_probe(struct bgmac *info);
void bgmac_enet_remove(struct bgmac *bgmac);
+void bgmac_adjust_link(struct net_device *net_dev);
struct mii_bus *bcma_mdio_mii_register(struct bcma_device *core, u8 phyaddr);
void bcma_mdio_mii_unregister(struct mii_bus *mii_bus);
@@ -583,4 +585,9 @@ static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
{
bgmac_maskset(bgmac, offset, ~0, set);
}
+
+static inline int bgmac_phy_connect(struct bgmac *bgmac)
+{
+ return bgmac->phy_connect(bgmac);
+}
#endif /* _BGMAC_H */
--
2.7.4
^ permalink raw reply related
* [PATCH 4/5] net: ethernet: bgmac: add NS2 support
From: Jon Mason @ 2016-10-26 19:36 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal-g1n6cQUeyibVItvQsEIGlw,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477510561-17035-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Add support for the variant of amac hardware present in the Broadcom
Northstar2 based SoCs. Northstar2 requires an additional register to be
configured with the port speed/duplexity (NICPM). This can be added to
the link callback to hide it from the instances that do not use this.
Also, the bgmac_chip_reset() was intentionally removed to prevent the
resetting of the chip to the default values on open. Finally, clearing
of the pending interrupts on init is required due to observed issues on
some platforms.
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
drivers/net/ethernet/broadcom/bgmac-platform.c | 64 +++++++++++++++++++++++++-
drivers/net/ethernet/broadcom/bgmac.c | 5 +-
drivers/net/ethernet/broadcom/bgmac.h | 2 +
3 files changed, 67 insertions(+), 4 deletions(-)
diff --git a/drivers/net/ethernet/broadcom/bgmac-platform.c b/drivers/net/ethernet/broadcom/bgmac-platform.c
index aed5dc5..49fcff4 100644
--- a/drivers/net/ethernet/broadcom/bgmac-platform.c
+++ b/drivers/net/ethernet/broadcom/bgmac-platform.c
@@ -14,12 +14,21 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/bcma/bcma.h>
+#include <linux/brcmphy.h>
#include <linux/etherdevice.h>
#include <linux/of_address.h>
#include <linux/of_mdio.h>
#include <linux/of_net.h>
#include "bgmac.h"
+#define NICPM_IOMUX_CTRL 0x00000008
+
+#define NICPM_IOMUX_CTRL_INIT_VAL 0x3196e000
+#define NICPM_IOMUX_CTRL_SPD_SHIFT 10
+#define NICPM_IOMUX_CTRL_SPD_10M 0
+#define NICPM_IOMUX_CTRL_SPD_100M 1
+#define NICPM_IOMUX_CTRL_SPD_1000M 2
+
static u32 platform_bgmac_read(struct bgmac *bgmac, u16 offset)
{
return readl(bgmac->plat.base + offset);
@@ -87,17 +96,56 @@ static void platform_bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
WARN_ON(1);
}
+static void bgmac_nicpm_speed_set(struct net_device *net_dev)
+{
+ struct bgmac *bgmac = netdev_priv(net_dev);
+ u32 val;
+
+ if (!bgmac->plat.nicpm_base)
+ return;
+
+ val = NICPM_IOMUX_CTRL_INIT_VAL;
+ switch (bgmac->net_dev->phydev->speed) {
+ default:
+ pr_err("Unsupported speed. Defaulting to 1000Mb\n");
+ case SPEED_1000:
+ val |= NICPM_IOMUX_CTRL_SPD_1000M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_100:
+ val |= NICPM_IOMUX_CTRL_SPD_100M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ case SPEED_10:
+ val |= NICPM_IOMUX_CTRL_SPD_10M << NICPM_IOMUX_CTRL_SPD_SHIFT;
+ break;
+ }
+
+ writel(val, bgmac->plat.nicpm_base + NICPM_IOMUX_CTRL);
+
+ usleep_range(10, 100);
+
+ bgmac_adjust_link(bgmac->net_dev);
+}
+
static int platform_phy_connect(struct bgmac *bgmac)
{
struct phy_device *phy_dev;
- phy_dev = of_phy_get_and_connect(bgmac->net_dev, bgmac->dev->of_node,
- bgmac_adjust_link);
+ if (bgmac->plat.nicpm_base)
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_nicpm_speed_set);
+ else
+ phy_dev = of_phy_get_and_connect(bgmac->net_dev,
+ bgmac->dev->of_node,
+ bgmac_adjust_link);
if (!phy_dev) {
dev_err(bgmac->dev, "Phy connect failed\n");
return -ENODEV;
}
+ if (bgmac->feature_flags & BGMAC_FEAT_LANE_SWAP)
+ phy_dev->dev_flags |= PHY_BRCM_EXP_LANE_SWAP;
+
return 0;
}
@@ -140,6 +188,9 @@ static int bgmac_probe(struct platform_device *pdev)
platform_set_drvdata(pdev, bgmac);
+ if (of_property_read_bool(np, "brcm,enet-phy-lane-swap"))
+ bgmac->feature_flags |= BGMAC_FEAT_LANE_SWAP;
+
/* Set the features of the 4707 family */
bgmac->feature_flags |= BGMAC_FEAT_CLKCTLST;
bgmac->feature_flags |= BGMAC_FEAT_NO_RESET;
@@ -182,6 +233,14 @@ static int bgmac_probe(struct platform_device *pdev)
if (IS_ERR(bgmac->plat.idm_base))
return PTR_ERR(bgmac->plat.idm_base);
+ regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nicpm_base");
+ if (regs) {
+ bgmac->plat.nicpm_base = devm_ioremap_resource(&pdev->dev,
+ regs);
+ if (IS_ERR(bgmac->plat.nicpm_base))
+ return PTR_ERR(bgmac->plat.nicpm_base);
+ }
+
bgmac->read = platform_bgmac_read;
bgmac->write = platform_bgmac_write;
bgmac->idm_read = platform_bgmac_idm_read;
@@ -213,6 +272,7 @@ static int bgmac_remove(struct platform_device *pdev)
static const struct of_device_id bgmac_of_enet_match[] = {
{.compatible = "brcm,amac",},
{.compatible = "brcm,nsp-amac",},
+ {.compatible = "brcm,ns2-amac",},
{},
};
diff --git a/drivers/net/ethernet/broadcom/bgmac.c b/drivers/net/ethernet/broadcom/bgmac.c
index 38876ec..1796208 100644
--- a/drivers/net/ethernet/broadcom/bgmac.c
+++ b/drivers/net/ethernet/broadcom/bgmac.c
@@ -1082,6 +1082,9 @@ static void bgmac_enable(struct bgmac *bgmac)
/* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
static void bgmac_chip_init(struct bgmac *bgmac)
{
+ /* Clear any erroneously pending interrupts */
+ bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
+
/* 1 interrupt per received frame */
bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
@@ -1158,8 +1161,6 @@ static int bgmac_open(struct net_device *net_dev)
struct bgmac *bgmac = netdev_priv(net_dev);
int err = 0;
- bgmac_chip_reset(bgmac);
-
err = bgmac_dma_init(bgmac);
if (err)
return err;
diff --git a/drivers/net/ethernet/broadcom/bgmac.h b/drivers/net/ethernet/broadcom/bgmac.h
index ea52ac3..677e685 100644
--- a/drivers/net/ethernet/broadcom/bgmac.h
+++ b/drivers/net/ethernet/broadcom/bgmac.h
@@ -409,6 +409,7 @@
#define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17)
#define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18)
#define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19)
+#define BGMAC_FEAT_LANE_SWAP BIT(20)
struct bgmac_slot_info {
union {
@@ -463,6 +464,7 @@ struct bgmac {
struct {
void *base;
void *idm_base;
+ void *nicpm_base;
} plat;
struct {
struct bcma_device *core;
--
2.7.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 5/5] arm64: dts: NS2: add AMAC ethernet support
From: Jon Mason @ 2016-10-26 19:36 UTC (permalink / raw)
To: David Miller, Rob Herring, Mark Rutland, Florian Fainelli
Cc: rafal, bcm-kernel-feedback-list, netdev, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <1477510561-17035-1-git-send-email-jon.mason@broadcom.com>
Add support for the AMAC ethernet to the Broadcom Northstar2 SoC device
tree
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 5 +++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 12 ++++++++++++
2 files changed, 17 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 2d7872a..362db7e 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -56,6 +56,11 @@
};
};
+&enet {
+ brcm,enet-phy-lane-swap;
+ status = "ok";
+};
+
&pci_phy0 {
status = "ok";
};
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index d95dc40..773ed59 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -191,6 +191,18 @@
#include "ns2-clock.dtsi"
+ enet: ethernet@61000000 {
+ compatible = "brcm,ns2-amac";
+ reg = <0x61000000 0x1000>,
+ <0x61090000 0x1000>,
+ <0x61030000 0x100>;
+ reg-names = "amac_base", "idm_base", "nicpm_base";
+ interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
+ phy-handle = <&gphy0>;
+ phy-mode = "rgmii";
+ status = "disabled";
+ };
+
dma0: dma@61360000 {
compatible = "arm,pl330", "arm,primecell";
reg = <0x61360000 0x1000>;
--
2.7.4
^ permalink raw reply related
* [PATCH 0/3] Add TI SCI Reset Driver
From: Andrew F. Davis @ 2016-10-26 19:39 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Philipp Zabel,
Rob Herring, Mark Rutland, Suman Anna
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andrew F . Davis
Hello all,
This series adds a reset controller driver that uses the TI SCI
protocol to manage resets.
The TI SCI protocol is used to communicate with power management
controllers used by some SoCs. These controllers manage the various
power domains, clocks, and resets available on a SoC.
This series is based on drivers for TI SCI and the first two controlled
elements above, these series can be found here:
TI-SCI: http://www.spinics.net/lists/arm-kernel/msg536851.html
PM Domains: http://www.spinics.net/lists/devicetree/msg146621.html
Clocks: https://www.spinics.net/lists/linux-clk/msg12785.html
Thanks,
Andrew
Andrew F. Davis (3):
Documentation: dt: reset: Add TI SCI reset binding
dt-bindings: reset: Add K2G reset definitions
reset: Add the TI SCI reset driver
.../devicetree/bindings/reset/ti,sci-reset.txt | 68 ++++++
MAINTAINERS | 3 +
drivers/reset/Kconfig | 9 +
drivers/reset/Makefile | 1 +
drivers/reset/reset-ti-sci.c | 262 +++++++++++++++++++++
include/dt-bindings/reset/k2g.h | 22 ++
6 files changed, 365 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/ti,sci-reset.txt
create mode 100644 drivers/reset/reset-ti-sci.c
create mode 100644 include/dt-bindings/reset/k2g.h
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 1/3] Documentation: dt: reset: Add TI SCI reset binding
From: Andrew F. Davis @ 2016-10-26 19:39 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Philipp Zabel,
Rob Herring, Mark Rutland, Suman Anna
Cc: devicetree, linux-kernel, Andrew F . Davis
In-Reply-To: <20161026193938.25093-1-afd@ti.com>
Add TI SCI reset controller binding. This describes the DT binding
details for a reset controller node providing reset management services
to hardware blocks (reset consumers) using the Texas Instrument's System
Control Interface (TI SCI) protocol to communicate to a system controller
block present on the SoC.
Signed-off-by: Andrew F. Davis <afd@ti.com>
[s-anna@ti.com: revise the binding format]
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---
.../devicetree/bindings/reset/ti,sci-reset.txt | 68 ++++++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 69 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/ti,sci-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/ti,sci-reset.txt b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt
new file mode 100644
index 0000000..189e284
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/ti,sci-reset.txt
@@ -0,0 +1,68 @@
+Texas Instruments System Control Interface (TI-SCI) Reset Controller
+=====================================================================
+
+Some TI SoCs contain a system controller (like the Power Management Micro
+Controller (PMMC) on Keystone K2G SoC) that are responsible for controlling
+the state of the various hardware modules present on the SoC. Communication
+between the host processor running an OS and the system controller happens
+through a protocol called TI System Control Interface (TI-SCI protocol).
+For TI SCI details, please refer to the document,
+Documentation/devicetree/bindings/arm/keystone/ti,sci.txt
+
+TI-SCI Reset Controller Node
+============================
+This reset controller node uses the TI SCI protocol to perform the reset
+management of various hardware modules present on the SoC.
+
+Required properties:
+--------------------
+ - compatible : Should be "ti,sci-reset"
+ - ti,sci : phandle to the TI SCI device to use for managing resets
+ - #reset-cells : Should be 2. Please see the reset consumer node below for
+ usage details.
+
+TI-SCI Reset Consumer Nodes
+===========================
+Each of the reset consumer nodes should have the following properties,
+in addition to their own properties.
+
+Required properties:
+--------------------
+ - resets : A phandle and reset specifier pair, one pair for each reset
+ signal that affects the device, or that the device manages.
+ The phandle should point to the TI-SCI reset controller node,
+ and the reset specifier should have 2 cell-values. The first
+ cell should contain the device ID, the values of which are
+ specified in the <dt-bindings/genpd/<soc>.h> include file.
+ The second cell should contain the reset mask value used by
+ system controller, the values of which are specified in the
+ include file <dt-bindings/reset/<soc>.h>, where <soc> is the
+ name of the SoC involved, for example 'k2g'.
+
+Please also refer to Documentation/devicetree/bindings/reset/reset.txt for
+common reset controller usage by consumers.
+
+
+Example:
+--------
+The following example demonstrates both a TI-SCI reset controller node and a
+consumer (a DSP device) on the K2G SoC.
+
+#include <dt-bindings/genpd/k2g.h>
+#include <dt-bindings/reset/k2g.h>
+
+/ {
+ soc {
+ k2g_reset: k2g_reset {
+ compatible = "ti,sci-reset";
+ ti,sci = <&pmmc>;
+ #reset-cells = <2>;
+ };
+
+ dsp0: dsp0 {
+ ...
+ resets = <&k2g_reset K2G_DEV_CGEM0 K2G_DEV_CGEM0_DSP0_RESET>;
+ ...
+ };
+ };
+};
diff --git a/MAINTAINERS b/MAINTAINERS
index 6e93976..d8068df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11899,6 +11899,7 @@ F: drivers/soc/ti/ti_sci_pm_domains.c
F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: include/dt-bindings/clock/k2g.h
F: drivers/clk/keystone/sci-clk.c
+F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
M: Hans Verkuil <hverkuil@xs4all.nl>
--
2.10.1
^ permalink raw reply related
* [PATCH 2/3] dt-bindings: reset: Add K2G reset definitions
From: Andrew F. Davis @ 2016-10-26 19:39 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Philipp Zabel,
Rob Herring, Mark Rutland, Suman Anna
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andrew F . Davis
In-Reply-To: <20161026193938.25093-1-afd-l0cyMroinI0@public.gmane.org>
Add identifiers for the K2G resets managed by the PMMC.
Signed-off-by: Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>
---
MAINTAINERS | 1 +
include/dt-bindings/reset/k2g.h | 22 ++++++++++++++++++++++
2 files changed, 23 insertions(+)
create mode 100644 include/dt-bindings/reset/k2g.h
diff --git a/MAINTAINERS b/MAINTAINERS
index d8068df..accf991 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11900,6 +11900,7 @@ F: Documentation/devicetree/bindings/clock/ti,sci-clk.txt
F: include/dt-bindings/clock/k2g.h
F: drivers/clk/keystone/sci-clk.c
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
+F: include/dt-bindings/reset/k2g.h
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
M: Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
diff --git a/include/dt-bindings/reset/k2g.h b/include/dt-bindings/reset/k2g.h
new file mode 100644
index 0000000..00e2a9b
--- /dev/null
+++ b/include/dt-bindings/reset/k2g.h
@@ -0,0 +1,22 @@
+/*
+ * TI K2G SoC reset definitions
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DT_BINDINGS_RESET_K2G_H__
+#define __DT_BINDINGS_RESET_K2G_H__
+
+#define K2G_DEV_CGEM0_DSP0_RESET 0x1
+
+#endif
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 3/3] reset: Add the TI SCI reset driver
From: Andrew F. Davis @ 2016-10-26 19:39 UTC (permalink / raw)
To: Nishanth Menon, Tero Kristo, Santosh Shilimkar, Philipp Zabel,
Rob Herring, Mark Rutland, Suman Anna
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andrew F . Davis
In-Reply-To: <20161026193938.25093-1-afd-l0cyMroinI0@public.gmane.org>
Some TI Keystone family of SoCs contain a system controller (like the
Power Management Micro Controller (PMMC) on K2G SoCs) that manage the
low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations
are provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.
This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management
of various devices present on the SoC. Various reset functionalities
are achieved by the means of different TI SCI device operations
provided by the TI SCI framework.
Signed-off-by: Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>
[s-anna-l0cyMroinI0@public.gmane.org: documentation changes, revised commit message]
Signed-off-by: Suman Anna <s-anna-l0cyMroinI0@public.gmane.org>
Signed-off-by: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
---
MAINTAINERS | 1 +
drivers/reset/Kconfig | 9 ++
drivers/reset/Makefile | 1 +
drivers/reset/reset-ti-sci.c | 262 +++++++++++++++++++++++++++++++++++++++++++
4 files changed, 273 insertions(+)
create mode 100644 drivers/reset/reset-ti-sci.c
diff --git a/MAINTAINERS b/MAINTAINERS
index accf991..b93d91a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11901,6 +11901,7 @@ F: include/dt-bindings/clock/k2g.h
F: drivers/clk/keystone/sci-clk.c
F: Documentation/devicetree/bindings/reset/ti,sci-reset.txt
F: include/dt-bindings/reset/k2g.h
+F: drivers/reset/reset-ti-sci.c
THANKO'S RAREMONO AM/FM/SW RADIO RECEIVER USB DRIVER
M: Hans Verkuil <hverkuil-qWit8jRvyhVmR6Xm/wNWPw@public.gmane.org>
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 06d9fa2..4c21c9d 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -66,6 +66,15 @@ config RESET_SUNXI
help
This enables the reset driver for Allwinner SoCs.
+config RESET_TI_SCI
+ tristate "TI System Control Interface (TI-SCI) reset driver"
+ depends on RESET_CONTROLLER
+ depends on TI_SCI_PROTOCOL
+ help
+ This enables the reset driver support over TI System Control Interface
+ available on some new TI's SoCs. If you wish to use reset resources
+ managed by the TI System Controller, say Y here. Otherwise, say N.
+
config TI_SYSCON_RESET
tristate "TI SYSCON Reset Driver"
depends on HAS_IOMEM
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index bbe7026..36321f2 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_RESET_STM32) += reset-stm32.o
obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
+obj-$(CONFIG_RESET_TI_SCI) += reset-ti-sci.o
obj-$(CONFIG_TI_SYSCON_RESET) += reset-ti-syscon.o
obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
obj-$(CONFIG_RESET_ZYNQ) += reset-zynq.o
diff --git a/drivers/reset/reset-ti-sci.c b/drivers/reset/reset-ti-sci.c
new file mode 100644
index 0000000..42ccf12
--- /dev/null
+++ b/drivers/reset/reset-ti-sci.c
@@ -0,0 +1,262 @@
+/*
+ * Texas Instrument's System Control Interface (TI-SCI) reset driver
+ *
+ * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
+ * Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/idr.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset-controller.h>
+#include <linux/soc/ti/ti_sci_protocol.h>
+
+/**
+ * struct ti_sci_reset_control - reset control structure
+ * @dev_id: SoC-specific device identifier
+ * @reset_mask: reset mask to use for toggling reset
+ */
+struct ti_sci_reset_control {
+ u32 dev_id;
+ u32 reset_mask;
+};
+
+/**
+ * struct ti_sci_reset_data - reset controller information structure
+ * @rcdev: reset controller entity
+ * @dev: reset controller device pointer
+ * @sci: TI SCI handle used for communication with system controller
+ * @idr: idr structure for mapping ids to reset control structures
+ */
+struct ti_sci_reset_data {
+ struct reset_controller_dev rcdev;
+ struct device *dev;
+ const struct ti_sci_handle *sci;
+ struct idr idr;
+};
+
+#define to_ti_sci_reset_data(p) \
+ container_of((p), struct ti_sci_reset_data, rcdev)
+
+/**
+ * ti_sci_reset_set() - program a device's reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to toggle
+ * @assert: boolean flag to indicate assert or deassert
+ *
+ * This is a common internal function used to assert or deassert a device's
+ * reset using the TI SCI protocol. The device's reset is asserted if the
+ * @assert argument is true, or deasserted if @assert argument is false.
+ * The mechanism itself is a read-modify-write procedure, the current device
+ * reset register is read using a TI SCI device operation, the new value is
+ * set or un-set using the reset's mask, and the new reset value written by
+ * using another TI SCI device operation.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_set(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
+ const struct ti_sci_handle *sci = data->sci;
+ const struct ti_sci_dev_ops *dev_ops = &sci->ops.dev_ops;
+ struct ti_sci_reset_control *control;
+ u32 reset_state;
+ int ret;
+
+ control = idr_find(&data->idr, id);
+ if (!control)
+ return -EINVAL;
+
+ ret = dev_ops->get_device_resets(sci, control->dev_id,
+ &reset_state);
+ if (ret)
+ return ret;
+
+ if (assert)
+ reset_state |= control->reset_mask;
+ else
+ reset_state &= ~control->reset_mask;
+
+ return dev_ops->set_device_resets(sci, control->dev_id,
+ reset_state);
+}
+
+/**
+ * ti_sci_reset_assert() - assert device reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to be asserted
+ *
+ * This function implements the reset driver op to assert a device's reset
+ * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
+ * with the corresponding parameters as passed in, but with the @assert
+ * argument set to true for asserting the reset.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return ti_sci_reset_set(rcdev, id, true);
+}
+
+/**
+ * ti_sci_reset_deassert() - deassert device reset
+ * @rcdev: reset controller entity
+ * @id: ID of the reset to be deasserted
+ *
+ * This function implements the reset driver op to deassert a device's reset
+ * using the TI SCI protocol. This invokes the function ti_sci_reset_set()
+ * with the corresponding parameters as passed in, but with the @assert
+ * argument set to false for deasserting the reset.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return ti_sci_reset_set(rcdev, id, false);
+}
+
+/**
+ * ti_sci_reset_status() - check device reset status
+ * @rcdev: reset controller entity
+ * @id: ID of reset to be checked
+ *
+ * This function implements the reset driver op to return the status of a
+ * device's reset using the TI SCI protocol. The reset register value is read
+ * by invoking the TI SCI device opertation .get_device_resets(), and the
+ * status of the specific reset is extracted and returned using this reset's
+ * reset mask.
+ *
+ * Return: 0 if reset is deasserted, or a non-zero value if reset is asserted
+ */
+static int ti_sci_reset_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
+ const struct ti_sci_handle *sci = data->sci;
+ const struct ti_sci_dev_ops *dev_ops = &sci->ops.dev_ops;
+ struct ti_sci_reset_control *control;
+ u32 reset_state;
+ int ret;
+
+ control = idr_find(&data->idr, id);
+ if (!control)
+ return -EINVAL;
+
+ ret = dev_ops->get_device_resets(sci, control->dev_id,
+ &reset_state);
+ if (ret)
+ return ret;
+
+ return reset_state & control->reset_mask;
+}
+
+static struct reset_control_ops ti_sci_reset_ops = {
+ .assert = ti_sci_reset_assert,
+ .deassert = ti_sci_reset_deassert,
+ .status = ti_sci_reset_status,
+};
+
+/**
+ * ti_sci_reset_of_xlate() - translate a set of OF arguments to a reset ID
+ * @rcdev: reset controller entity
+ * @reset_spec: OF reset argument specifier
+ *
+ * This function performs the translation of the reset argument specifier
+ * values defined in a reset consumer device node. The function allocates a
+ * reset control structure for that device reset, and will be used by the
+ * driver for performing any reset functions on that reset. An idr structure
+ * is allocated and used to map to the reset control structure. This idr
+ * is used by the driver to do reset lookups.
+ *
+ * Return: 0 for successful request, else a corresponding error value
+ */
+static int ti_sci_reset_of_xlate(struct reset_controller_dev *rcdev,
+ const struct of_phandle_args *reset_spec)
+{
+ struct ti_sci_reset_data *data = to_ti_sci_reset_data(rcdev);
+ struct ti_sci_reset_control *control;
+
+ if (WARN_ON(reset_spec->args_count != rcdev->of_reset_n_cells))
+ return -EINVAL;
+
+ control = devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL);
+ if (!control)
+ return -ENOMEM;
+
+ control->dev_id = reset_spec->args[0];
+ control->reset_mask = reset_spec->args[1];
+
+ return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL);
+}
+
+static const struct of_device_id ti_sci_reset_of_match[] = {
+ { .compatible = "ti,sci-reset", },
+ { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, ti_sci_reset_of_match);
+
+static int ti_sci_reset_probe(struct platform_device *pdev)
+{
+ struct ti_sci_reset_data *data;
+
+ if (!pdev->dev.of_node)
+ return -ENODEV;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ data->sci = devm_ti_sci_get_handle(&pdev->dev);
+ if (IS_ERR(data->sci))
+ return PTR_ERR(data->sci);
+
+ data->rcdev.ops = &ti_sci_reset_ops;
+ data->rcdev.owner = THIS_MODULE;
+ data->rcdev.of_node = pdev->dev.of_node;
+ data->rcdev.of_reset_n_cells = 2;
+ data->rcdev.of_xlate = ti_sci_reset_of_xlate;
+ data->dev = &pdev->dev;
+ idr_init(&data->idr);
+
+ platform_set_drvdata(pdev, data);
+
+ return reset_controller_register(&data->rcdev);
+}
+
+static int ti_sci_reset_remove(struct platform_device *pdev)
+{
+ struct ti_sci_reset_data *data = platform_get_drvdata(pdev);
+
+ reset_controller_unregister(&data->rcdev);
+
+ idr_destroy(&data->idr);
+
+ return 0;
+}
+
+static struct platform_driver ti_sci_reset_driver = {
+ .probe = ti_sci_reset_probe,
+ .remove = ti_sci_reset_remove,
+ .driver = {
+ .name = "ti-sci-reset",
+ .of_match_table = ti_sci_reset_of_match,
+ },
+};
+module_platform_driver(ti_sci_reset_driver);
+
+MODULE_AUTHOR("Andrew F. Davis <afd-l0cyMroinI0@public.gmane.org>");
+MODULE_DESCRIPTION("TI System Control Interface (TI SCI) Reset driver");
+MODULE_LICENSE("GPL v2");
--
2.10.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH V4 0/5] firmware: Add support for TI System Control Interface (TI-SCI) protocol driver
From: Santosh Shilimkar @ 2016-10-26 19:56 UTC (permalink / raw)
To: Tero Kristo, Nishanth Menon, Santosh Shilimkar
Cc: Dave Gerlach, Lokesh Vutla, Andrew Davis, Russell King, Russ Dill,
Sudeep Holla, linux-arm-kernel, devicetree, linux-pm,
linux-kernel, Rob Herring, Kevin Hilman
In-Reply-To: <2694e4b5-20d5-f590-c6a6-55ff4cb8c16b@ti.com>
On 10/25/2016 10:34 AM, Tero Kristo wrote:
> On 19/10/16 02:08, Nishanth Menon wrote:
>> Version 4 of the series is basically a rebase to v4.9-rc1, no functional
>> changes.
>
> Hi,
>
> Any final comments on this series, or shall I send a pull-req forward?
> Very minimal changes compared to v3 so should be good to go imo.
>
The patchset looks fine to me from brief scan so please Go from
my side at least for the pull request.
Regards,
Santosh
^ permalink raw reply
* Re: [PATCH 1/2] phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips
From: Kishon Vijay Abraham I @ 2016-10-26 19:56 UTC (permalink / raw)
To: Vivek Gautam, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <1476873827-7191-2-git-send-email-vivek.gautam@codeaurora.org>
Hi,
On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
> PHY transceiver driver for QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller present on
> Qualcomm chipsets.
>
> This driver is based on phy-msm-qusb driver available in
> msm-4.4 kernel @codeaurora[1]
>
> [1] https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
I'd prefer only LKML links in commit msg. This can be part of the comment
section below ---.
>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 37 ++
> drivers/phy/Kconfig | 10 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-qusb2.c | 577 +++++++++++++++++++++
> 4 files changed, 625 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> create mode 100644 drivers/phy/phy-qcom-qusb2.c
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> new file mode 100644
> index 0000000..97c9ce7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> @@ -0,0 +1,37 @@
> +Qualcomm QUSB2 phy controller
> +=============================
> +
> +QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> +
> +Required properties:
> + - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 0.
> +
> + - clocks: a list of phandles and clock-specifier pairs,
> + one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "ref_clk" for 19.2 MHz ref clk,
> + "ref_clk_src" reference clock source.
> + "iface" for phy interface clock (Optional).
> +
> + - vdd-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> + - vdda-phy-dpdm: Phandle to 3.1V regulator supply to Dp/Dm port signals.
> +
> + - resets: a list of phandles and reset controller specifier pairs,
> + one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block.
> +
> +Optional properties:
> + - nvmem-cells: a list of phandles to nvmem cells that contain fused
> + tuning parameters for qusb2 phy, one for each entry
> + in nvmem-cell-names.
> + - nvmem-cell-names: must be "tune2_hstx_trim_efuse" for cell containing
> + HS Tx trim value.
> + - qcom,hstx-trim-bit-offset: bit offset within nvmem cell for
> + HS Tx trim value.
> + - qcom,hstx-trim-bit-len: bit length of HS Tx trim value within nvmem cell.
> +
> + - qcom,tcsr-syscon: Phandle to TCSR syscon register region.
> + - qcom,phy-clk-scheme: Offset to TCSR_PHY_CLK_SCHEME_SEL register.
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index fe00f91..5547984 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -446,6 +446,16 @@ config PHY_STIH41X_USB
> Enable this to support the USB transceiver that is part of
> STMicroelectronics STiH41x SoC series.
>
> +config PHY_QCOM_QUSB2
> + tristate "Qualcomm QUSB2 PHY Driver"
> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the HighSpeed QUSB2 PHY transceiver for USB
> + controllers on Qualcomm chips. This driver supports the high-speed
> + PHY which is usually paired with either the ChipIdea or Synopsys DWC3
> + USB IPs on MSM SOCs.
> +
> config PHY_QCOM_UFS
> tristate "Qualcomm UFS PHY driver"
> depends on OF && ARCH_QCOM
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index a534cf5..848489d 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
> obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
> +obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-14nm.o
> diff --git a/drivers/phy/phy-qcom-qusb2.c b/drivers/phy/phy-qcom-qusb2.c
> new file mode 100644
> index 0000000..058f661
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-qusb2.c
> @@ -0,0 +1,577 @@
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/nvmem-consumer.h>
> +#include <linux/of.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/regmap.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#define QUSB2PHY_PLL_TEST 0x04
> +#define CLK_REF_SEL BIT(7)
> +
> +#define QUSB2PHY_PLL_TUNE 0x08
> +#define QUSB2PHY_PLL_USER_CTL1 0x0c
> +#define QUSB2PHY_PLL_USER_CTL2 0x10
> +#define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c
> +#define QUSB2PHY_PLL_PWR_CTRL 0x18
> +
> +#define QUSB2PHY_PLL_STATUS 0x38
> +#define PLL_LOCKED BIT(5)
> +
> +#define QUSB2PHY_PORT_TUNE1 0x80
> +
> +#define QUSB2PHY_PORT_TUNE2 0x84
> +/* TUNE2's high nibble value read from efuse */
> +#define TUNE2_HIGH_NIBBLE_VAL(val, pos, mask) ((val >> pos) & mask)
> +
> +#define QUSB2PHY_PORT_TUNE3 0x88
> +#define QUSB2PHY_PORT_TUNE4 0x8C
> +#define QUSB2PHY_PORT_TUNE5 0x90tx
> +#define QUSB2PHY_PORT_TEST2 0x9c
> +
> +#define QUSB2PHY_PORT_POWERDOWN 0xB4
> +#define CLAMP_N_EN BIT(5)
> +#define FREEZIO_N BIT(1)
> +#define POWER_DOWN BIT(0)
> +
> +#define QUSB2PHY_REFCLK_ENABLE BIT(0)
> +
> +#define PHY_CLK_SCHEME_SEL BIT(0)
> +
> +struct qusb2_phy_init_tbl {
> + unsigned int reg_offset;
> + unsigned int cfg_val;
> +};
> +#define QCOM_QUSB2_PHY_INIT_CFG(reg, val) \
> + { \
> + .reg_offset = reg, \
> + .cfg_val = val, \
> + }
> +
> +static struct qusb2_phy_init_tbl msm8996_phy_init_tbl[] = {
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE1, 0xF8),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE2, 0xB3),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE3, 0x83),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TUNE4, 0xC0),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PORT_TEST2, 0x14),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F),
> + QCOM_QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
> +};
we should generalize this so that it could be used for any phys. All these
tuning parameters can come from dt.
phy,tx-swing = <reg_offset> <swing value>;
phy,rx-swing = <reg_offset> <swing value>;
phy,tx-compensation = <reg_offset> <swing value>;
phy,rx-compensation = <reg_offset> <swing value>;
..
We have to identify all the calibration parameters and add a dt property for
each parameter. The phy-core can just use these properties to calibrate or tune
the PHY.
> +
> +struct qusb2_phy_init_cfg {
> + struct qusb2_phy_init_tbl *phy_init_tbl;
> + int phy_init_tbl_sz;
> +};
> +
> +const struct qusb2_phy_init_cfg msm8996_phy_init_cfg = {
> + .phy_init_tbl = msm8996_phy_init_tbl,
> + .phy_init_tbl_sz = ARRAY_SIZE(msm8996_phy_init_tbl),
> +};
> +
> +/**
> + * struct qusb2_phy: Structure holding qusb2 phy attributes.
> + *
> + * @phy: pointer to generic phy.
> + * @base: pointer to iomapped memory space for qubs2 phy.
> + *
> + * @cfg_ahb_clk: pointer to AHB2PHY interface clock.
> + * @ref_clk: pointer to reference clock.
> + * @ref_clk_src: pointer to source to reference clock.
> + * @iface_src: pointer to phy interface clock.
> + * @clk_enabled: check if clocks are enabled.
Why is this needed? IMO this should not be used. clk framework can handle this
better since it maintains a reference count for clk_enable/clk_disable.
> + *
> + * @phy_reset: Pointer to phy reset control
> + *
> + * @vdda_phy: vdd supply to the phy core block.
> + * @vdda_pll: 1.8V vdd supply to ref_clk block.
> + * @vdda_phy_dpdm: 3.1V vdd supply to Dp/Dm port signals.
> + * @pwr_enabled: check if the regulators are enabled.
same here.
> + * @tcsr: pointer to TCSR syscon register map.
> + * @clk_scheme_offset: offset to PHY_CLK_SCHEME register in TCSR map.
> + * @cfg: phy initialization config data
> + */
> +struct qusb2_phy {
> + struct phy *phy;
> + void __iomem *base;
> +
> + struct clk *cfg_ahb_clk;
> + struct clk *ref_clk;
> + struct clk *ref_clk_src;
> + struct clk *iface_clk;
> + bool clk_enabled;
> +
> + struct reset_control *phy_reset;
> +
> + struct regulator *vdd_phy;
> + struct regulator *vdda_pll;
> + struct regulator *vdda_phy_dpdm;
> + bool pwr_enabled;
> +
> + struct regmap *tcsr;
> + unsigned int clk_scheme_offset;
> +
> + const struct qusb2_phy_init_cfg *cfg;
> +};
> +
> +static inline void qusb2_set_bits(void __iomem *reg, u32 mask)
mask is misleading. just use val.
> +{
> + u32 val;
> +
> + val = readl_relaxed(reg);
> + val |= mask;
> + writel_relaxed(val, reg);
> +
> + /* Ensure above write is completed */
> + mb();
> +}
> +
> +static inline void qusb2_clr_bits(void __iomem *reg, u32 mask)
> +{
> + u32 val;
> +
> + val = readl_relaxed(reg);
> + val &= ~mask;
> + writel_relaxed(val, reg);
> +
> + /* Ensure above write is completed */
> + mb();
> +}
> +
> +static void qcom_qusb2_phy_configure(void __iomem *base,
> + struct qusb2_phy_init_tbl init_tbl[],
> + int init_tbl_sz)
> +{
> + int i;
> +
> + for (i = 0; i < init_tbl_sz; i++) {
> + writel_relaxed(init_tbl[i].cfg_val,
> + base + init_tbl[i].reg_offset);
> + }
> +
> + /* flush buffered writes */
> + mb();
> +}
> +
> +static void qusb2_phy_enable_clocks(struct qusb2_phy *qphy, bool on)
> +{
> + dev_dbg(&qphy->phy->dev, "%s(): clocks_enabled:%d on:%d\n",
> + __func__, qphy->clk_enabled, on);
unnecessary debug print IMO, given that there is another debug print before the
function returns.
> +
> + if (!qphy->clk_enabled && on) {
> + clk_prepare_enable(qphy->cfg_ahb_clk);
> + if (qphy->iface_clk)
> + clk_prepare_enable(qphy->iface_clk);
> + clk_prepare_enable(qphy->ref_clk_src);
> + qphy->clk_enabled = true;
> + }
> +
> + if (qphy->clk_enabled && !on) {
> + clk_disable_unprepare(qphy->ref_clk_src);
> + if (qphy->iface_clk)
> + clk_disable_unprepare(qphy->iface_clk);
> + clk_disable_unprepare(qphy->cfg_ahb_clk);
> + qphy->clk_enabled = false;
> + }
> +
> + dev_dbg(&qphy->phy->dev, "%s(): clocks_enabled:%d\n", __func__,
> + qphy->clk_enabled);
even this should be dev_vdbg.
> +}
> +
> +static int qusb2_phy_enable_power(struct qusb2_phy *qphy, bool on)
> +{
> + int ret = 0;
> + struct device *dev = &qphy->phy->dev;
> +
> + dev_dbg(dev, "%s(): turn %s regulators. power_enabled:%d\n",
> + __func__, on ? "on" : "off", qphy->pwr_enabled);
> +
> + if (qphy->pwr_enabled == on)
> + return 0;
> +
> + if (!on)
> + goto disable_vdda_phy_dpdm;
> +
> + ret = regulator_enable(qphy->vdd_phy);
> + if (ret) {
> + dev_err(dev, "Unable to enable vdd-phy:%d\n", ret);
> + goto err_vdd_phy;
> + }
> +
> + ret = regulator_enable(qphy->vdda_pll);
> + if (ret) {
> + dev_err(dev, "Unable to enable vdda-pll:%d\n", ret);
> + goto disable_vdd_phy;
> + }
> +
> + ret = regulator_enable(qphy->vdda_phy_dpdm);
> + if (ret) {
> + dev_err(dev, "Unable to enable vdda-phy-dpdm:%d\n", ret);
> + goto disable_vdda_pll;
> + }
> +
> + qphy->pwr_enabled = true;
> + dev_dbg(dev, "%s() regulators are turned on.\n", __func__);
> +
> + return ret;
> +
> +disable_vdda_phy_dpdm:
> + regulator_disable(qphy->vdda_phy_dpdm);
> +disable_vdda_pll:
> + regulator_disable(qphy->vdda_pll);
> +disable_vdd_phy:
> + regulator_disable(qphy->vdd_phy);
> +err_vdd_phy:
> + qphy->pwr_enabled = false;
> + dev_dbg(dev, "%s() regulators are turned off.\n", __func__);
> + return ret;
> +}
> +
> +/*
> + * Fetches HS Tx tuning value from e-fuse and sets QUSB2PHY_PORT_TUNE2
> + * register.
> + * For any error case, skip setting the value and use the default value.
> + */
> +static int qusb2_phy_set_tune2_param(struct qusb2_phy *qphy)
> +{
> + struct device *dev = &qphy->phy->dev;
> + struct nvmem_cell *cell;
> + unsigned int bit_mask;
> + u32 tune2_val;
> + int bit_offset = 0;
> + int bit_len = 0;
> + ssize_t len;
> + u32 *val;
> + int ret;
> +
> + /*
> + * Read EFUSE register having TUNE2 parameter's high nibble.
> + * If efuse register shows value as 0x0, or if we fail to find
> + * a valid efuse register settings, then use default value
> + * as 0xB for high nibble that we have already set while
> + * configuring phy.
> + */
> + cell = devm_nvmem_cell_get(dev, "tune2_hstx_trim_efuse");
> + if (IS_ERR(cell)) {
> + if (PTR_ERR(cell) == -EPROBE_DEFER)
> + return PTR_ERR(cell);
> + goto skip;
> + }
> +
> + val = (u32 *)nvmem_cell_read(cell, &len);
> + if (!IS_ERR(val)) {
> + ret = of_property_read_u32(dev->of_node,
> + "qcom,hstx-trim-bit-offset",
> + &bit_offset);
> + if (ret) {
> + dev_dbg(dev, "hstx-trim bit offset is invalid.\n");
> + goto skip;
> + }
> +
> + ret = of_property_read_u32(dev->of_node,
> + "qcom,hstx-trim-bit-len",
> + &bit_len);
> + if (ret) {
> + dev_dbg(dev, "hstx-trim bit length is invalid.\n");
> + goto skip;
> + }
> +
> + bit_mask = (1 << bit_len) - 1;
> + dev_dbg(dev,
> + "%s(): efuse value:%x, bit_mask:%x, bit_offset: %d\n",
> + __func__, val[0], bit_mask, bit_offset);
> + tune2_val = TUNE2_HIGH_NIBBLE_VAL(val[0], bit_offset, bit_mask);
> + if (!tune2_val) {
> + dev_dbg(dev, "hstx-trim bit length is invalid.\n");
> + goto skip;
> + }
> +
> + /* Fused TUNE2 value is the higher nibble only */
> + tune2_val = tune2_val << 0x4;
> + qusb2_set_bits(qphy->base + QUSB2PHY_PORT_TUNE2, tune2_val);
> + } else {
> + dev_dbg(dev, "failed reading hs-tx trim value: %d\n", ret);
> + }
> +
> +skip:
> + return 0;
> +}
> +
> +static int qusb2_phy_init(struct phy *phy)
> +{
> + struct qusb2_phy *qphy = phy_get_drvdata(phy);
> + unsigned int reset_val;
> + unsigned int clk_scheme;
> + bool is_se_clk = false;
> + int ret;
> +
> + dev_info(&phy->dev, "Initializing QUSB2 phy\n");
dev_vdbg here..
> +
> + ret = qusb2_phy_enable_power(qphy, true);
> + if (ret)
> + return ret;
shouldn't this be done in power_on?
> +
> + qusb2_phy_enable_clocks(qphy, true);
> +
> + /* Perform phy reset */
> + ret = reset_control_assert(qphy->phy_reset);
> + if (ret) {
> + dev_err(&phy->dev, "Failed to assert phy_reset\n");
> + return ret;
> + }
> + usleep_range(100, 150);
add a comment for the above delay.
> + ret = reset_control_deassert(qphy->phy_reset);
> + if (ret) {
> + dev_err(&phy->dev, "Failed to de-assert phy_reset\n");
> + return ret;
> + }
> +
> + /* Disable the PHY */
> + qusb2_set_bits(qphy->base + QUSB2PHY_PORT_POWERDOWN,
> + CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
> +
> + /* save reset value to override based on clk scheme */
> + reset_val = readl_relaxed(qphy->base + QUSB2PHY_PLL_TEST);
> +
> + qcom_qusb2_phy_configure(qphy->base, qphy->cfg->phy_init_tbl,
> + qphy->cfg->phy_init_tbl_sz);
> +
> + /* Check for efuse value for tuning the PHY */
> + ret = qusb2_phy_set_tune2_param(qphy);
> + if (ret)
> + return ret;
> +
> + /* Enable the PHY */
> + qusb2_clr_bits(qphy->base + QUSB2PHY_PORT_POWERDOWN, POWER_DOWN);
> +
> + /* Require to get phy pll lock successfully */
> + usleep_range(150, 160);
> +
> + /*
> + * Use differential clk by default; later we read TCSR_PHY_CLK_SCHEME
> + * register to check if Single-ended clock scheme is selected. If yes,
> + * then disable differential ref_clk and use single-ended clock.
> + */
> +
> + if (qphy->tcsr) {
> + ret = regmap_read(qphy->tcsr, qphy->clk_scheme_offset,
> + &clk_scheme);
> + /* is SE-clk available ? */
> + if (clk_scheme & PHY_CLK_SCHEME_SEL) {
> + dev_dbg(&phy->dev, "%s: select single-ended clk src\n",
> + __func__);
> + is_se_clk = true;
> + }
> + }
> +
> + if (is_se_clk) {
> + reset_val |= CLK_REF_SEL;
> + clk_disable_unprepare(qphy->ref_clk);
> + } else {
> + reset_val &= ~CLK_REF_SEL;
> + clk_prepare_enable(qphy->ref_clk);
> + }
> +
> + writel_relaxed(reset_val, qphy->base + QUSB2PHY_PLL_TEST);
> +
> + /* Make sure that above write is completed to get PLL source clock */
> + wmb();
> +
> + /* Required to get PHY PLL lock successfully */
> + usleep_range(100, 110);
> +
> + if (!(readb_relaxed(qphy->base + QUSB2PHY_PLL_STATUS) &
> + PLL_LOCKED)) {
> + dev_err(&phy->dev, "QUSB PHY PLL LOCK fails:%x\n",
> + readb_relaxed(qphy->base + QUSB2PHY_PLL_STATUS));
> + return -EBUSY;
> + }
> +
> + return 0;
> +}
> +
> +static int qusb2_phy_exit(struct phy *phy)
> +{
> + struct qusb2_phy *qphy = phy_get_drvdata(phy);
> +
> + /* Disable the PHY */
> + qusb2_set_bits(qphy->base + QUSB2PHY_PORT_POWERDOWN,
> + CLAMP_N_EN | FREEZIO_N | POWER_DOWN);
> +
> + qusb2_phy_enable_clocks(qphy, false);
> + qusb2_phy_enable_power(qphy, false);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops qusb2_phy_gen_ops = {
> + .init = qusb2_phy_init,
> + .exit = qusb2_phy_exit,
you can add callbacks for power_on and power_off and add then enable clocks and
power here?
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct of_device_id qusb2_phy_of_match_table[] = {
> + {
> + .compatible = "qcom,msm8996-qusb2-phy",
> + .data = &msm8996_phy_init_cfg,
> + },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table);
> +
> +static int qusb2_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct qusb2_phy *qphy;
> + struct phy_provider *phy_provider;
> + struct phy *generic_phy;
> + const struct of_device_id *match;
> + struct resource *res;
> + int ret = 0;
> +
> + qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
> + if (!qphy)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENODEV;
the above check is not required. ioremap will take care.
> + qphy->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(qphy->base))
> + return PTR_ERR(qphy->base);
> +
> + qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb_clk");
> + if (IS_ERR(qphy->cfg_ahb_clk)) {
> + ret = PTR_ERR(qphy->cfg_ahb_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get cfg_ahb_clk\n");
> + return ret;
> + }
> +
> + qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
> + if (IS_ERR(qphy->ref_clk_src)) {
> + qphy->ref_clk_src = NULL;
> + ret = PTR_ERR(qphy->ref_clk_src);
> + if (ret != -EPROBE_DEFER)
> + dev_dbg(dev, "clk get failed for ref_clk_src\n");
don't we have to return on PROBE_DEFER?
> + }
> +
> + qphy->ref_clk = devm_clk_get(dev, "ref_clk");
> + if (IS_ERR(qphy->ref_clk)) {
> + qphy->ref_clk = NULL;
> + ret = PTR_ERR(qphy->ref_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_dbg(dev, "clk get failed for ref_clk\n");
same here.
> + } else {
> + clk_set_rate(qphy->ref_clk, 19200000);
> + }
> +
> + qphy->iface_clk = devm_clk_get(dev, "iface_clk");
> + if (IS_ERR(qphy->iface_clk)) {
> + qphy->iface_clk = NULL;
> + ret = PTR_ERR(qphy->iface_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_dbg(dev, "clk get failed for iface_clk\n");
here..
> + }
> +
> + qphy->phy_reset = devm_reset_control_get(&pdev->dev, "phy");
> + if (IS_ERR(qphy->phy_reset)) {
> + dev_err(dev, "failed to get phy core reset\n");
> + return PTR_ERR(qphy->phy_reset);
> + }
> +
> + qphy->vdd_phy = devm_regulator_get(dev, "vdd-phy");
> + if (IS_ERR(qphy->vdd_phy)) {
> + dev_err(dev, "unable to get vdd-phy supply\n");
> + return PTR_ERR(qphy->vdd_phy);
> + }
> +
> + qphy->vdda_pll = devm_regulator_get(dev, "vdda-pll");
> + if (IS_ERR(qphy->vdda_pll)) {
> + dev_err(dev, "unable to get vdda-pll supply\n");
> + return PTR_ERR(qphy->vdda_pll);
> + }
> +
> + qphy->vdda_phy_dpdm = devm_regulator_get(dev, "vdda-phy-dpdm");
> + if (IS_ERR(qphy->vdda_phy_dpdm)) {
> + dev_err(dev, "unable to get vdda-phy-dpdm supply\n");
> + return PTR_ERR(qphy->vdda_phy_dpdm);
> + }
> +
> + /* Get the specific init parameters of QMP phy */
> + match = of_match_node(qusb2_phy_of_match_table, dev->of_node);
> + qphy->cfg = match->data;
> +
> + qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node,
> + "qcom,tcsr-syscon");
> + if (!IS_ERR(qphy->tcsr)) {
> + ret = of_property_read_u32(dev->of_node, "qcom,phy-clk-scheme",
> + &qphy->clk_scheme_offset);
> + if (ret) {
> + dev_err(dev, "phy-clk-scheme reg offset is invalid\n");
> + qphy->tcsr = NULL;
> + return ret;
> + }
> + } else {
> + dev_dbg(dev, "Failed to lookup TCSR regmap\n");
> + qphy->tcsr = NULL;
> + }
> +
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> + if (IS_ERR(phy_provider)) {
> + ret = PTR_ERR(phy_provider);
> + dev_err(dev, "%s: failed to register phy %d\n", __func__, ret);
> + return ret;
> + }
> +
> + generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops);
> + if (IS_ERR(generic_phy)) {
> + ret = PTR_ERR(generic_phy);
> + dev_err(dev, "%s: failed to create phy %d\n", __func__, ret);
> + generic_phy = NULL;
> + return ret;
> + }
phy should be created before registering the PHY.
> + qphy->phy = generic_phy;
> +
> + dev_set_drvdata(dev, qphy);
> + phy_set_drvdata(generic_phy, qphy);
this should be done before phy_provider_register.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets
From: Kishon Vijay Abraham I @ 2016-10-26 20:11 UTC (permalink / raw)
To: Vivek Gautam, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-arm-msm
In-Reply-To: <1476873827-7191-3-git-send-email-vivek.gautam@codeaurora.org>
Hi,
On Wednesday 19 October 2016 04:13 PM, Vivek Gautam wrote:
> Qualcomm SOCs have QMP phy controller that provides support
> to a number of controller, viz. PCIe, UFS, and USB.
> Add a new driver, based on generic phy framework, for this
> phy controller.
>
> USB3-phy changes: Based on phy-msm-ssusb-qmp driver available on
> msm-4.4 kernel @codeaurora[1].
> PCIe-phy changes: Based on msm8996-pcie-phy driver posted by
> Srinivas [2].
>
> [1] https://source.codeaurora.org/quic/la/kernel/msm-4.4/log/?h=caf/3.18/msm-3.18
> [2] https://patchwork.kernel.org/patch/9318947/
use only lkml links here.
>
> Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
> Cc: Kishon Vijay Abraham I <kishon@ti.com>
> ---
> .../devicetree/bindings/phy/qcom-qmp-phy.txt | 61 ++
> drivers/phy/Kconfig | 8 +
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-qcom-qmp.c | 1154 ++++++++++++++++++++
> 4 files changed, 1224 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> create mode 100644 drivers/phy/phy-qcom-qmp.c
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> new file mode 100644
> index 0000000..90214aa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
> @@ -0,0 +1,61 @@
> +Qualcomm QMP PHY
> +----------------
> +
> +QMP phy controller supports physical layer functionality for a number of
> +controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
> +
> +Required properties:
> + - compatible: compatible list, contains:
> + "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
> + "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996.
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 1
> + - Cell after phy phandle should be the port (lane) number.
> + - clocks: a list of phandles and clock-specifier pairs,
> + one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "aux" for phy aux clock,
> + "ref_clk" for 19.2 MHz ref clk,
> + "ref_clk_src" for reference clock source,
> + "pipe<port-number>" for pipe clock specific to
> + each port/lane (Optional).
> + - resets: a list of phandles and reset controller specifier pairs,
> + one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block,
> + "common" for phy common block reset,
> + "cfg" for phy's ahb cfg block reset (Optional).
> + "port<port-number>" for reset specific to
> + each port/lane. (Optional)
> + - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> +Optional properties:
> + - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
> + pll block.
> +
> +Example:
> + pcie_phy: pciephy@34000 {
> + compatible = "qcom,qmp-14nm-pcie-phy";
> + reg = <0x034000 0x3fff>;
> + #phy-cells = <1>;
> +
> + clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
> + <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
> + <&gcc GCC_PCIE_0_PIPE_CLK>,
> + <&gcc GCC_PCIE_1_PIPE_CLK>,
> + <&gcc GCC_PCIE_2_PIPE_CLK>;
> + clock-names = "aux", "cfg_ahb",
> + "pipe0", "pipe1", "pipe2";
> +
> + vdda-phy-supply = <&pm8994_l28>;
> + vdda-pll-supply = <&pm8994_l12>;
> +
> + resets = <&gcc GCC_PCIE_PHY_BCR>,
> + <&gcc GCC_PCIE_PHY_COM_BCR>,
> + <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>,
> + <&gcc GCC_PCIE_0_PHY_BCR>,
> + <&gcc GCC_PCIE_1_PHY_BCR>,
> + <&gcc GCC_PCIE_2_PHY_BCR>;
> + reset-names = "phy", "common", "cfg",
> + "lane0", "lane1", "lane2";
> + };
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index 5547984..d5e2b50f 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -446,6 +446,14 @@ config PHY_STIH41X_USB
> Enable this to support the USB transceiver that is part of
> STMicroelectronics STiH41x SoC series.
>
> +config PHY_QCOM_QMP
> + tristate "Qualcomm QMP PHY Driver"
> + depends on OF && (ARCH_QCOM || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable this to support the QMP PHY transceiver that is used
> + with controllers such as PCIe, UFS, and USB on Qualcomm chips.
> +
> config PHY_QCOM_QUSB2
> tristate "Qualcomm QUSB2 PHY Driver"
> depends on OF && (ARCH_QCOM || COMPILE_TEST)
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 848489d..fde9fba 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -51,6 +51,7 @@ obj-$(CONFIG_PHY_ST_SPEAR1340_MIPHY) += phy-spear1340-miphy.o
> obj-$(CONFIG_PHY_XGENE) += phy-xgene.o
> obj-$(CONFIG_PHY_STIH407_USB) += phy-stih407-usb.o
> obj-$(CONFIG_PHY_STIH41X_USB) += phy-stih41x-usb.o
> +obj-$(CONFIG_PHY_QCOM_QMP) += phy-qcom-qmp.o
> obj-$(CONFIG_PHY_QCOM_QUSB2) += phy-qcom-qusb2.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs.o
> obj-$(CONFIG_PHY_QCOM_UFS) += phy-qcom-ufs-qmp-20nm.o
> diff --git a/drivers/phy/phy-qcom-qmp.c b/drivers/phy/phy-qcom-qmp.c
> new file mode 100644
> index 0000000..7e89179
> --- /dev/null
> +++ b/drivers/phy/phy-qcom-qmp.c
> @@ -0,0 +1,1154 @@
> +/*
> + * Copyright (c) 2016, The Linux Foundation. All rights reserved.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 and
> + * only version 2 as published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/io.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/platform_device.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/reset.h>
> +#include <linux/slab.h>
> +
> +#include <dt-bindings/phy/phy.h>
> +
> +/* QMP PHY QSERDES COM registers */
> +#define QSERDES_COM_BG_TIMER 0x00c
> +#define QSERDES_COM_SSC_EN_CENTER 0x010
> +#define QSERDES_COM_SSC_ADJ_PER1 0x014
> +#define QSERDES_COM_SSC_ADJ_PER2 0x018
> +#define QSERDES_COM_SSC_PER1 0x01c
> +#define QSERDES_COM_SSC_PER2 0x020
> +#define QSERDES_COM_SSC_STEP_SIZE1 0x024
> +#define QSERDES_COM_SSC_STEP_SIZE2 0x028
> +#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034
> +#define QSERDES_COM_CLK_ENABLE1 0x038
> +#define QSERDES_COM_SYS_CLK_CTRL 0x03c
> +#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040
> +#define QSERDES_COM_PLL_IVCO 0x048
> +#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c
> +#define QSERDES_COM_LOCK_CMP2_MODE0 0x050
> +#define QSERDES_COM_LOCK_CMP3_MODE0 0x054
> +#define QSERDES_COM_LOCK_CMP1_MODE1 0x058
> +#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c
> +#define QSERDES_COM_LOCK_CMP3_MODE1 0x060
> +#define QSERDES_COM_BG_TRIM 0x070
> +#define QSERDES_COM_CLK_EP_DIV 0x074
> +#define QSERDES_COM_CP_CTRL_MODE0 0x078
> +#define QSERDES_COM_CP_CTRL_MODE1 0x07c
> +#define QSERDES_COM_PLL_RCTRL_MODE0 0x084
> +#define QSERDES_COM_PLL_RCTRL_MODE1 0x088
> +#define QSERDES_COM_PLL_CCTRL_MODE0 0x090
> +#define QSERDES_COM_PLL_CCTRL_MODE1 0x094
> +#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac
> +#define QSERDES_COM_RESETSM_CNTRL 0x0b4
> +#define QSERDES_COM_RESTRIM_CTRL 0x0bc
> +#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4
> +#define QSERDES_COM_LOCK_CMP_EN 0x0c8
> +#define QSERDES_COM_LOCK_CMP_CFG 0x0cc
> +#define QSERDES_COM_DEC_START_MODE0 0x0d0
> +#define QSERDES_COM_DEC_START_MODE1 0x0d4
> +#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc
> +#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0
> +#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4
> +#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8
> +#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec
> +#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0
> +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108
> +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c
> +#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110
> +#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114
> +#define QSERDES_COM_VCO_TUNE_CTRL 0x124
> +#define QSERDES_COM_VCO_TUNE_MAP 0x128
> +#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c
> +#define QSERDES_COM_VCO_TUNE2_MODE0 0x130
> +#define QSERDES_COM_VCO_TUNE1_MODE1 0x134
> +#define QSERDES_COM_VCO_TUNE2_MODE1 0x138
> +#define QSERDES_COM_VCO_TUNE_TIMER1 0x144
> +#define QSERDES_COM_VCO_TUNE_TIMER2 0x148
> +#define QSERDES_COM_BG_CTRL 0x170
> +#define QSERDES_COM_CLK_SELECT 0x174
> +#define QSERDES_COM_HSCLK_SEL 0x178
> +#define QSERDES_COM_CORECLK_DIV 0x184
> +#define QSERDES_COM_CORE_CLK_EN 0x18c
> +#define QSERDES_COM_C_READY_STATUS 0x190
> +#define QSERDES_COM_CMN_CONFIG 0x194
> +#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c
> +#define QSERDES_COM_DEBUG_BUS0 0x1a0
> +#define QSERDES_COM_DEBUG_BUS1 0x1a4
> +#define QSERDES_COM_DEBUG_BUS2 0x1a8
> +#define QSERDES_COM_DEBUG_BUS3 0x1ac
> +#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0
> +#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc
> +
> +/* QMP PHY TX registers */
> +#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054
> +#define QSERDES_TX_DEBUG_BUS_SEL 0x064
> +#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068
> +#define QSERDES_TX_LANE_MODE 0x094
> +#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac
> +
> +/* QMP PHY RX registers */
> +#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010
> +#define QSERDES_RX_UCDR_SO_GAIN 0x01c
> +#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040
> +#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048
> +#define QSERDES_RX_RX_TERM_BW 0x090
> +#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4
> +#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8
> +#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc
> +#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc
> +#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0
> +#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108
> +#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c
> +#define QSERDES_RX_SIGDET_ENABLES 0x110
> +#define QSERDES_RX_SIGDET_CNTRL 0x114
> +#define QSERDES_RX_SIGDET_LVL 0x118
> +#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c
> +#define QSERDES_RX_RX_BAND 0x120
> +#define QSERDES_RX_RX_INTERFACE_MODE 0x12c
> +
> +/* QMP PHY PCS registers */
> +#define QPHY_SW_RESET 0x00
> +#define QPHY_POWER_DOWN_CONTROL 0x04
> +#define QPHY_START_CTRL 0x08
> +#define QPHY_TXDEEMPH_M6DB_V0 0x24
> +#define QPHY_TXDEEMPH_M3P5DB_V0 0x28
> +#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54
> +#define QPHY_RX_IDLE_DTCT_CNTRL 0x58
> +#define QPHY_POWER_STATE_CONFIG1 0x60
> +#define QPHY_POWER_STATE_CONFIG2 0x64
> +#define QPHY_POWER_STATE_CONFIG4 0x6c
> +#define QPHY_LOCK_DETECT_CONFIG1 0x80
> +#define QPHY_LOCK_DETECT_CONFIG2 0x84
> +#define QPHY_LOCK_DETECT_CONFIG3 0x88
> +#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0
> +#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4
> +
> +/* PHY_SW_RESET bit */
> +#define PHY_SW_RESET BIT(0)
> +/* PHY_POWER_DOWN_CONTROL */
> +#define PHY_SW_PWRDN BIT(0)
> +#define PHY_REFCLK_DRV_DSBL BIT(1)
> +/* PHY_START_CONTROL bits */
> +#define PHY_SERDES_START BIT(0)
> +#define PHY_PCS_START BIT(1)
> +#define PHY_PLL_READY_GATE_EN BIT(3)
> +/* PHY_PCS_STATUS bit */
> +#define MASK_PHYSTATUS BIT(6)
> +/* PCS_READY_STATUS bit */
> +#define MASK_COM_PCS_READY BIT(0)
> +
> +#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
> +#define REFCLK_STABILIZATION_DELAY_US_MAX 1005
> +#define PHY_READY_TIMEOUT_COUNT 10
> +#define POWER_DOWN_DELAY_US_MIN 10
> +#define POWER_DOWN_DELAY_US_MAX 11
> +
> +#define MAX_PROP_NAME 32
> +
> +struct qmp_phy_init_tbl {
> + unsigned int reg_offset;
> + unsigned int cfg_val;
> + /*
> + * register part of layout ?
> + * if yes, then reg_offset gives index in the reg-layout
> + */
> + int in_layout;
> +};
> +#define QCOM_QMP_PHY_INIT_CFG(reg, val) \
> + { \
> + .reg_offset = reg, \
> + .cfg_val = val, \
> + }
> +#define QCOM_QMP_PHY_INIT_CFG_L(reg, val) \
> + { \
> + .reg_offset = reg, \
> + .cfg_val = val, \
> + .in_layout = 1, \
> + }
> +
> +/* set of registers with offsets different per-PHY */
> +enum qphy_reg_layout {
> + /* Common block control registers */
> + QPHY_COM_SW_RESET,
> + QPHY_COM_POWER_DOWN_CONTROL,
> + QPHY_COM_START_CONTROL,
> + QPHY_COM_PCS_READY_STATUS,
> + /* PCS registers */
> + QPHY_PLL_LOCK_CHK_DLY_TIME,
> + QPHY_FLL_CNTRL1,
> + QPHY_FLL_CNTRL2,
> + QPHY_FLL_CNT_VAL_L,
> + QPHY_FLL_CNT_VAL_H_TOL,
> + QPHY_FLL_MAN_CODE,
> + QPHY_PCS_READY_STATUS,
> +};
> +
> +unsigned int pciephy_regs_layout[] = {
> + [QPHY_COM_SW_RESET] = 0x400,
> + [QPHY_COM_POWER_DOWN_CONTROL] = 0x404,
> + [QPHY_COM_START_CONTROL] = 0x408,
> + [QPHY_COM_PCS_READY_STATUS] = 0x448,
> + [QPHY_PLL_LOCK_CHK_DLY_TIME] = 0xa8,
> + [QPHY_FLL_CNTRL1] = 0xc4,
> + [QPHY_FLL_CNTRL2] = 0xc8,
> + [QPHY_FLL_CNT_VAL_L] = 0xcc,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xd0,
> + [QPHY_FLL_MAN_CODE] = 0xd4,
> + [QPHY_PCS_READY_STATUS] = 0x174,
> +};
> +
> +unsigned int usb3phy_regs_layout[] = {
> + [QPHY_FLL_CNTRL1] = 0xc0,
> + [QPHY_FLL_CNTRL2] = 0xc4,
> + [QPHY_FLL_CNT_VAL_L] = 0xc8,
> + [QPHY_FLL_CNT_VAL_H_TOL] = 0xcc,
> + [QPHY_FLL_MAN_CODE] = 0xd0,
> + [QPHY_PCS_READY_STATUS] = 0x17c,
> +};
> +
> +static struct qmp_phy_init_tbl pciephy_serdes_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1c),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x42),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER1, 0xff),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_TIMER2, 0x1f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x09),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x1a),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x0a),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x33),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x02),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_BUF_ENABLE, 0x1f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x04),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x02),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x2f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x19),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x15),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_EP_DIV, 0x19),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_ENABLE1, 0x10),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_RESCODE_DIV_NUM, 0x40),
> +};
> +
> +static struct qmp_phy_init_tbl pciephy_tx_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static struct qmp_phy_init_tbl pciephy_rx_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x1c),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xdb),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_BAND, 0x18),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN_HALF, 0x04),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x4b),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x14),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x19),
> +};
> +
> +static struct qmp_phy_init_tbl pciephy_pcs_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QPHY_RX_IDLE_DTCT_CNTRL, 0x4c),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_PWRUP_RESET_DLY_TIME_AUXCLK, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_LP_WAKEUP_DLY_TIME_AUXCLK, 0x01),
> +
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_PLL_LOCK_CHK_DLY_TIME, 0x05),
> +
> + QCOM_QMP_PHY_INIT_CFG(QPHY_ENDPOINT_REFCLK_DRIVE, 0x05),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_POWER_DOWN_CONTROL, 0x02),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG4, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG1, 0xa3),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_TXDEEMPH_M3P5DB_V0, 0x0e),
> +};
> +
> +static struct qmp_phy_init_tbl usb3phy_serdes_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
> + /* PLL and Loop filter settings */
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
> + /* SSC settings */
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
> +};
> +
> +static struct qmp_phy_init_tbl usb3phy_tx_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
> +};
> +
> +static struct qmp_phy_init_tbl usb3phy_rx_init_tbl[] = {
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
> + QCOM_QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
> +};
> +
> +static struct qmp_phy_init_tbl usb3phy_pcs_init_tbl[] = {
> + /* FLL settings */
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL2, 0x03),
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_FLL_CNTRL1, 0x02),
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_L, 0x09),
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_FLL_CNT_VAL_H_TOL, 0x42),
> + QCOM_QMP_PHY_INIT_CFG_L(QPHY_FLL_MAN_CODE, 0x85),
> +
> + /* Lock Det settings */
> + QCOM_QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG1, 0xd1),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG2, 0x1f),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_LOCK_DETECT_CONFIG3, 0x47),
> + QCOM_QMP_PHY_INIT_CFG(QPHY_POWER_STATE_CONFIG2, 0x08),
> +};
if you can implement the dt mechanism I mentioned in your other patch, all
these tables can be got rid of and the code to initialize these can also be
removed.
> +
> +/**
> + * struct qmp_phy_init_cfg:- per-PHY init config.
> + */
> +struct qmp_phy_init_cfg {
> + /*
> + * @type: phy-type - PCIE/UFS/USB
> + * @nlanes: number of lanes provided by phy
> + * @tx_offsets: array of offsets of Tx block from PHY base
> + * @rx_offsets: array of offsets of Rx block from PHY base
> + * @pcs_offsets: array of offsets of PCS block from PHY base
> + */
> + unsigned int type;
> + int nlanes;
> + unsigned int *tx_offsets;
> + unsigned int *rx_offsets;
> + unsigned int *pcs_offsets;
> +
> + /* Initialization sequence for PHY blocks - Serdes, tx, rx, pcs */
> + struct qmp_phy_init_tbl *phy_init_serdes_tbl;
> + int phy_init_serdes_tbl_sz;
> + struct qmp_phy_init_tbl *phy_init_tx_tbl;
> + int phy_init_tx_tbl_sz;
> + struct qmp_phy_init_tbl *phy_init_rx_tbl;
> + int phy_init_rx_tbl_sz;
> + struct qmp_phy_init_tbl *phy_init_pcs_tbl;
> + int phy_init_pcs_tbl_sz;
> +
> + /* array of registers with different offsets */
> + unsigned int *regs;
> +
> + unsigned int mask_start_ctrl;
> + unsigned int mask_pwr_dn_ctrl;
> + /* true, if PHY has a separate PHY_COM_CNTRL block */
> + bool has_phy_com_ctrl;
> +};
> +
> +/**
> + * struct qmp_phy_desc:- per-lane phy-descriptor.
> + *
> + * @phy: pointer to generic phy
> + * @tx: pointer to iomapped memory space for PHY's tx
> + * @rx: pointer to iomapped memory space for PHY's rx
> + * @pcs: pointer to iomapped memory space for PHY's pcs
> + * @pipe_clk: pointer to pipe lock
> + * @index: lane index
> + * @qphy: pointer to QMP phy to which this lane belongs
> + * @lane_rst: pointer to lane's reset controller
> + */
> +struct qmp_phy_desc {
> + struct phy *phy;
> + void __iomem *tx;
> + void __iomem *rx;
> + void __iomem *pcs;
> + struct clk *pipe_clk;
> + unsigned int index;
> + struct qcom_qmp_phy *qphy;
> + struct reset_control *lane_rst;
> +};
> +
> +/**
> + * struct qcom_qmp_phy:- structure holding QMP PHY attributes.
> + *
> + * @dev: pointer to device
> + * @serdes: pointer to iomapped memory space for phy's serdes
> + *
> + * @aux_clk: pointer to phy core clock
> + * @cfg_ahb_clk: pointer to AHB2PHY interface clock
> + * @ref_clk: pointer to reference clock
> + * @ref_clk_src: pointer to source to reference clock
> + * @clk_enabled: check if clocks are enabled or not
> + *
> + * @vdda_phy: vdd supply to the phy core block
> + * @vdda_pll: 1.8V vdd supply to ref_clk block
> + * @vddp_ref_clk: vdd supply to specific ref_clk block
> + *
> + * @phy_rst: Pointer to phy reset control
> + * @phycom_rst: Pointer to phy common reset control
> + * @phycfg_rst: Pointer to phy ahb cfg reset control (Optional)
> + *
> + * @cfg: pointer to init config for each phys
> + * @phys: array of pointer to per-lane phy descriptors
> + * @phy_mutex: mutex lock for PHY common block initialization
> + * @init_count: Phy common block initialization count
> + */
> +struct qcom_qmp_phy {
> + struct device *dev;
> + void __iomem *serdes;
> +
> + struct clk *aux_clk;
> + struct clk *cfg_ahb_clk;
> + struct clk *ref_clk;
> + struct clk *ref_clk_src;
> + bool clk_enabled;
> +
> + struct regulator *vdda_phy;
> + struct regulator *vdda_pll;
> + struct regulator *vddp_ref_clk;
> +
> + struct reset_control *phy_rst;
> + struct reset_control *phycom_rst;
> + struct reset_control *phycfg_rst;
> +
> + const struct qmp_phy_init_cfg *cfg;
> + struct qmp_phy_desc **phys;
> +
> + struct mutex phy_mutex;
> + int init_count;
> +};
> +
> +static inline void qphy_setbits(u32 bitmask, void __iomem *reg)
> +{
> + u32 val;
> +
> + val = readl_relaxed(reg);
> + val |= bitmask;
> + writel_relaxed(val, reg);
> +}
> +
> +static inline void qphy_clrbits(u32 bitmask, void __iomem *reg)
> +{
> + u32 val;
> +
> + val = readl_relaxed(reg);
> + val &= ~bitmask;
> + writel_relaxed(val, reg);
> +}
> +
> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
you can have a separate reg map for each lane and all these can come from dt.
> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };
> +
> +unsigned int msm8996_usb3phy_tx_offsets[] = { 0x200 };
> +unsigned int msm8996_usb3phy_rx_offsets[] = { 0x400 };
> +unsigned int msm8996_usb3phy_pcs_offsets[] = { 0x600 };
> +
> +const struct qmp_phy_init_cfg pciephy_init_cfg = {
> + .type = PHY_TYPE_PCIE,
> + .nlanes = 3,
> + .tx_offsets = msm8996_pciephy_tx_offsets,
> + .rx_offsets = msm8996_pciephy_rx_offsets,
> + .pcs_offsets = msm8996_pciephy_pcs_offsets,
> +
> + .phy_init_serdes_tbl = pciephy_serdes_init_tbl,
> + .phy_init_serdes_tbl_sz = ARRAY_SIZE(pciephy_serdes_init_tbl),
> + .phy_init_tx_tbl = pciephy_tx_init_tbl,
> + .phy_init_tx_tbl_sz = ARRAY_SIZE(pciephy_tx_init_tbl),
> + .phy_init_rx_tbl = pciephy_rx_init_tbl,
> + .phy_init_rx_tbl_sz = ARRAY_SIZE(pciephy_rx_init_tbl),
> + .phy_init_pcs_tbl = pciephy_pcs_init_tbl,
> + .phy_init_pcs_tbl_sz = ARRAY_SIZE(pciephy_pcs_init_tbl),
> + .has_phy_com_ctrl = true,
> + .regs = pciephy_regs_layout,
> + .mask_start_ctrl = (PHY_PCS_START | PHY_PLL_READY_GATE_EN),
> + .mask_pwr_dn_ctrl = (PHY_SW_PWRDN | PHY_REFCLK_DRV_DSBL),
> +};
> +
> +const struct qmp_phy_init_cfg usb3phy_init_cfg = {
> + .type = PHY_TYPE_USB3,
> + .nlanes = 1,
> + .tx_offsets = msm8996_usb3phy_tx_offsets,
> + .rx_offsets = msm8996_usb3phy_rx_offsets,
> + .pcs_offsets = msm8996_usb3phy_pcs_offsets,
> +
> + .phy_init_serdes_tbl = usb3phy_serdes_init_tbl,
> + .phy_init_serdes_tbl_sz = ARRAY_SIZE(usb3phy_serdes_init_tbl),
> + .phy_init_tx_tbl = usb3phy_tx_init_tbl,
> + .phy_init_tx_tbl_sz = ARRAY_SIZE(usb3phy_tx_init_tbl),
> + .phy_init_rx_tbl = usb3phy_rx_init_tbl,
> + .phy_init_rx_tbl_sz = ARRAY_SIZE(usb3phy_rx_init_tbl),
> + .phy_init_pcs_tbl = usb3phy_pcs_init_tbl,
> + .phy_init_pcs_tbl_sz = ARRAY_SIZE(usb3phy_pcs_init_tbl),
> + .regs = usb3phy_regs_layout,
> + .mask_start_ctrl = (PHY_SERDES_START | PHY_PCS_START),
> + .mask_pwr_dn_ctrl = PHY_SW_PWRDN,
> +};
> +
> +static void qcom_qmp_phy_configure(void __iomem *base,
> + unsigned int *regs_layout,
> + struct qmp_phy_init_tbl init_tbl[],
> + int init_tbl_sz)
> +{
> + int i;
> +
> + for (i = 0; i < init_tbl_sz; i++) {
> + if (init_tbl[i].in_layout)
> + writel_relaxed(init_tbl[i].cfg_val,
> + base + regs_layout[init_tbl[i].reg_offset]);
> + else
> + writel_relaxed(init_tbl[i].cfg_val,
> + base + init_tbl[i].reg_offset);
> + }
> +
> + /* flush buffered writes */
> + mb();
> +}
> +
> +static int qcom_qmp_phy_poweron(struct phy *phy)
> +{
> + struct qmp_phy_desc *phydesc = phy_get_drvdata(phy);
> + struct qcom_qmp_phy *qphy = phydesc->qphy;
> + int ret;
> +
> + dev_info(&phy->dev, "Powering on QMP phy\n");
> +
> + ret = regulator_enable(qphy->vdda_phy);
> + if (ret) {
> + dev_err(qphy->dev, "%s: vdda-phy enable failed, err=%d\n",
> + __func__, ret);
> + return ret;
> + }
> +
> + ret = regulator_enable(qphy->vdda_pll);
> + if (ret) {
> + dev_err(qphy->dev, "%s: vdda-pll enable failed, err=%d\n",
> + __func__, ret);
> + goto err_vdda_pll;
> + }
> +
> + if (qphy->vddp_ref_clk) {
> + ret = regulator_enable(qphy->vddp_ref_clk);
> + if (ret) {
> + dev_err(qphy->dev, "%s: vdda-ref-clk enable failed, err=%d\n",
> + __func__, ret);
> + goto err_vddp_refclk;
> + }
> + }
> +
> + if (!qphy->clk_enabled) {
lot of my comments on the previous PHY driver is applicable here. For example
the clk_enabled is not required.
> + clk_prepare_enable(qphy->ref_clk_src);
> + clk_prepare_enable(qphy->ref_clk);
> + clk_prepare_enable(phydesc->pipe_clk);
> + qphy->clk_enabled = true;
> + }
> +
> + return 0;
> +
> +err_vddp_refclk:
> + regulator_disable(qphy->vdda_pll);
> +err_vdda_pll:
> + regulator_disable(qphy->vdda_phy);
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_poweroff(struct phy *phy)
> +{
> + struct qmp_phy_desc *phydesc = phy_get_drvdata(phy);
> + struct qcom_qmp_phy *qphy = phydesc->qphy;
> +
> + if (qphy->clk_enabled) {
> + clk_disable_unprepare(qphy->ref_clk_src);
> + clk_disable_unprepare(qphy->ref_clk);
> + clk_disable_unprepare(phydesc->pipe_clk);
> + qphy->clk_enabled = false;
> + }
> +
> + if (qphy->vddp_ref_clk)
> + regulator_disable(qphy->vddp_ref_clk);
> +
> + regulator_disable(qphy->vdda_pll);
> + regulator_disable(qphy->vdda_phy);
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_is_ready(struct qcom_qmp_phy *qphy,
> + void __iomem *pcs_status, u32 mask)
> +{
> + unsigned int init_timeout;
> +
> + init_timeout = PHY_READY_TIMEOUT_COUNT;
> + do {
> + if (readl_relaxed(pcs_status) & mask)
> + break;
> +
> + usleep_range(REFCLK_STABILIZATION_DELAY_US_MIN,
> + REFCLK_STABILIZATION_DELAY_US_MAX);
> + } while (--init_timeout);
> +
> + if (!init_timeout)
> + return -EBUSY;
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_com_init(struct qcom_qmp_phy *qphy)
> +{
> + const struct qmp_phy_init_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> + int ret;
> +
> + mutex_lock(&qphy->phy_mutex);
> + if (qphy->init_count++) {
> + mutex_unlock(&qphy->phy_mutex);
> + return 0;
> + }
> +
> + ret = reset_control_deassert(qphy->phy_rst);
> + if (ret) {
> + dev_err(qphy->dev, "phy reset deassert failed\n");
> + return ret;
> + }
> +
> + ret = reset_control_deassert(qphy->phycom_rst);
> + if (ret) {
> + dev_err(qphy->dev, "common reset deassert failed\n");
> + goto err_phycom_rst;
> + }
> +
> + if (qphy->phycfg_rst) {
> + ret = reset_control_deassert(qphy->phycfg_rst);
> + if (ret) {
> + dev_err(qphy->dev, "common reset deassert failed\n");
> + goto err_phycfg_rst;
> + }
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(PHY_SW_PWRDN,
> + serdes + cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]);
> + /* Make sure that above write is completed */
> + mb();
> + }
> +
> + /* Serdes configuration */
> + qcom_qmp_phy_configure(serdes, cfg->regs, cfg->phy_init_serdes_tbl,
> + cfg->phy_init_serdes_tbl_sz);
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_clrbits(PHY_SW_RESET, serdes +
> + cfg->regs[QPHY_COM_SW_RESET]);
> + qphy_setbits(PHY_SERDES_START | PHY_PCS_START,
> + serdes + cfg->regs[QPHY_COM_START_CONTROL]);
> + /* Make sure that above write is completed */
> + mb();
> +
> + ret = qcom_qmp_phy_is_ready(qphy, serdes +
> + cfg->regs[QPHY_COM_PCS_READY_STATUS],
> + MASK_COM_PCS_READY);
> + if (ret) {
> + dev_err(qphy->dev,
> + "common control block init timed-out\n");
> + goto err_phy_comctrl;
> + }
> + }
> +
> + mutex_unlock(&qphy->phy_mutex);
> +
> + return 0;
> +
> +err_phy_comctrl:
> + if (qphy->phycfg_rst)
> + reset_control_assert(qphy->phycfg_rst);
> +err_phycfg_rst:
> + reset_control_assert(qphy->phycom_rst);
> +err_phycom_rst:
> + reset_control_assert(qphy->phy_rst);
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_com_exit(struct qcom_qmp_phy *qphy)
> +{
> + const struct qmp_phy_init_cfg *cfg = qphy->cfg;
> + void __iomem *serdes = qphy->serdes;
> +
> + mutex_lock(&qphy->phy_mutex);
> + if (--qphy->init_count) {
> + mutex_unlock(&qphy->phy_mutex);
> + return 0;
> + }
> +
> + if (cfg->has_phy_com_ctrl) {
> + qphy_setbits(PHY_SERDES_START | PHY_PCS_START,
> + serdes + cfg->regs[QPHY_COM_START_CONTROL]);
> + qphy_clrbits(PHY_SW_RESET, serdes +
> + cfg->regs[QPHY_COM_SW_RESET]);
> + qphy_setbits(PHY_SW_PWRDN,
> + serdes + cfg->regs[QPHY_COM_POWER_DOWN_CONTROL]);
> +
> + /* Make sure that above writes are completed */
> + mb();
> + }
> +
> + reset_control_assert(qphy->phy_rst);
> + reset_control_assert(qphy->phycom_rst);
> + if (qphy->phycfg_rst)
> + reset_control_assert(qphy->phycfg_rst);
> +
> + mutex_unlock(&qphy->phy_mutex);
> +
> + return 0;
> +}
> +
> +/* PHY Initialization */
> +static int qcom_qmp_phy_init(struct phy *phy)
> +{
> + struct qmp_phy_desc *phydesc = phy_get_drvdata(phy);
> + struct qcom_qmp_phy *qphy = phydesc->qphy;
> + const struct qmp_phy_init_cfg *cfg = qphy->cfg;
> + void __iomem *tx = phydesc->tx;
> + void __iomem *rx = phydesc->rx;
> + void __iomem *pcs = phydesc->pcs;
> + int ret;
> +
> + dev_info(qphy->dev, "Initializing QMP phy\n");
> +
> + /* enable interface clocks to program phy */
> + clk_prepare_enable(qphy->aux_clk);
> + clk_prepare_enable(qphy->cfg_ahb_clk);
> +
> + ret = qcom_qmp_phy_com_init(qphy);
> + if (ret)
> + goto err;
> +
> + if (phydesc->lane_rst) {
> + ret = reset_control_deassert(phydesc->lane_rst);
> + if (ret) {
> + dev_err(qphy->dev, "lane<%d> reset deassert failed\n",
> + phydesc->index);
> + goto err_lane_rst;
> + }
> + }
> +
> + /* Tx, Rx, and PCS configurations */
> + qcom_qmp_phy_configure(tx, cfg->regs, cfg->phy_init_tx_tbl,
> + cfg->phy_init_tx_tbl_sz);
> + qcom_qmp_phy_configure(rx, cfg->regs, cfg->phy_init_rx_tbl,
> + cfg->phy_init_rx_tbl_sz);
> + qcom_qmp_phy_configure(pcs, cfg->regs, cfg->phy_init_pcs_tbl,
> + cfg->phy_init_pcs_tbl_sz);
> +
> + /*
> + * Pull out PHY from POWER DOWN state:
> + * This is active low enable signal to power-down PHY.
> + */
> + qphy_setbits(cfg->mask_pwr_dn_ctrl,
> + pcs + QPHY_POWER_DOWN_CONTROL);
> + /* XXX: 10 us delay; given in PCIE HPG only */
> + usleep_range(POWER_DOWN_DELAY_US_MIN, POWER_DOWN_DELAY_US_MAX);
> +
> + /* start SerDes and Phy-Coding-Sublayer */
> + qphy_setbits(cfg->mask_start_ctrl, pcs + QPHY_START_CTRL);
> +
> + /* Pull PHY out of reset state */
> + qphy_clrbits(PHY_SW_RESET, pcs + QPHY_SW_RESET);
> + /* Make sure that above writes are completed */
> + mb();
> +
> + ret = qcom_qmp_phy_is_ready(qphy, pcs +
> + cfg->regs[QPHY_PCS_READY_STATUS],
> + MASK_PHYSTATUS);
> + if (ret) {
> + dev_err(qphy->dev, "phy initialization timed-out\n");
> + goto err_pcs_ready;
> + }
> +
> + return 0;
> +
> +err_pcs_ready:
> + if (phydesc->lane_rst)
> + reset_control_assert(phydesc->lane_rst);
> +err_lane_rst:
> + qcom_qmp_phy_com_exit(qphy);
> +err:
> + clk_disable_unprepare(qphy->cfg_ahb_clk);
> + clk_disable_unprepare(qphy->aux_clk);
> + return ret;
> +}
> +
> +static int qcom_qmp_phy_exit(struct phy *phy)
> +{
> + struct qmp_phy_desc *phydesc = phy_get_drvdata(phy);
> + struct qcom_qmp_phy *qphy = phydesc->qphy;
> + const struct qmp_phy_init_cfg *cfg = qphy->cfg;
> +
> + /* PHY reset */
> + qphy_setbits(PHY_SW_RESET, phydesc->pcs + QPHY_SW_RESET);
> +
> + /* stop SerDes and Phy-Coding-Sublayer */
> + qphy_clrbits(cfg->mask_start_ctrl, phydesc->pcs + QPHY_START_CTRL);
> +
> + /* Put PHY into POWER DOWN state: active low */
> + qphy_clrbits(cfg->mask_pwr_dn_ctrl,
> + phydesc->pcs + QPHY_POWER_DOWN_CONTROL);
> +
> + /* Make sure that above writes are completed */
> + mb();
> +
> + if (phydesc->lane_rst)
> + reset_control_assert(phydesc->lane_rst);
> +
> + qcom_qmp_phy_com_exit(qphy);
> +
> + clk_disable_unprepare(qphy->aux_clk);
> + clk_disable_unprepare(qphy->cfg_ahb_clk);
> +
> + return 0;
> +}
> +
> +
> +static int qcom_qmp_phy_regulator_init(struct device *dev)
> +{
> + struct qcom_qmp_phy *qphy = dev_get_drvdata(dev);
> + int ret = 0;
> +
> + qphy->vdda_phy = devm_regulator_get(dev, "vdda-phy");
> + if (IS_ERR(qphy->vdda_phy)) {
> + ret = PTR_ERR(qphy->vdda_phy);
> + dev_err(dev, "failed to get vdda-phy, %d\n", ret);
> + return ret;
> + }
> +
> + qphy->vdda_pll = devm_regulator_get(dev, "vdda-pll");
> + if (IS_ERR(qphy->vdda_pll)) {
> + ret = PTR_ERR(qphy->vdda_pll);
> + dev_err(dev, "failed to get vdda-pll, %d\n", ret);
> + return ret;
> + }
> +
> + /* optional regulator */
> + qphy->vddp_ref_clk = devm_regulator_get(dev, "vddp-ref-clk");
> + if (IS_ERR(qphy->vddp_ref_clk)) {
> + ret = PTR_ERR(qphy->vddp_ref_clk);
> + dev_info(dev, "failed to get vddp-ref-clk, %d\n", ret);
> + qphy->vddp_ref_clk = NULL;
> + }
> +
> + return 0;
> +}
> +
> +static int qcom_qmp_phy_clk_init(struct device *dev)
> +{
> + struct qcom_qmp_phy *qphy = dev_get_drvdata(dev);
> + int ret;
> +
> + qphy->aux_clk = devm_clk_get(dev, "aux");
> + if (IS_ERR(qphy->aux_clk)) {
> + ret = PTR_ERR(qphy->aux_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get aux_clk\n");
> + return ret;
> + }
> +
> + qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb");
> + if (IS_ERR(qphy->cfg_ahb_clk)) {
> + ret = PTR_ERR(qphy->cfg_ahb_clk);
> + if (ret != -EPROBE_DEFER)
> + dev_err(dev, "failed to get cfg_ahb_clk\n");
> + return ret;
> + }
> +
> + /*
> + * ref_clk and ref_clk_src handles may not be available in
> + * all hardwares. So we don't return error in these cases.
> + */
> + qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
> + if (IS_ERR(qphy->ref_clk_src)) {
> + ret = PTR_ERR(qphy->ref_clk_src);
> + if (ret != -EPROBE_DEFER) {
> + qphy->ref_clk_src = NULL;
> + dev_dbg(dev, "failed to get ref_clk_src\n");
> + } else {
> + return ret;
> + }
> + }
> +
> + qphy->ref_clk = devm_clk_get(dev, "ref_clk");
> + if (IS_ERR(qphy->ref_clk)) {
> + ret = PTR_ERR(qphy->ref_clk);
> + if (ret != -EPROBE_DEFER) {
> + qphy->ref_clk = NULL;
> + dev_dbg(dev, "failed to get ref_clk\n");
> + } else {
> + return ret;
> + }
> + }
> +
> + return 0;
> +}
> +
> +static struct phy *qcom_qmp_phy_xlate(struct device *dev,
> + struct of_phandle_args *args)
> +{
> + struct qcom_qmp_phy *qphy = dev_get_drvdata(dev);
> + int i;
> +
> + if (WARN_ON(args->args[0] >= qphy->cfg->nlanes))
> + return ERR_PTR(-ENODEV);
> +
> + for (i = 0; i < qphy->cfg->nlanes; i++) {
> + if (qphy->phys[i]->index == args->args[0])
> + break;
finding a PHY based on index is not required. Just have a different label for
each sub-node and using this label in the controller node should be enough.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH v6] mwifiex: parse device tree node for PCIe
From: Brian Norris @ 2016-10-26 20:17 UTC (permalink / raw)
To: Rajat Jain
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Xinming Hu, Amitkumar Karwar,
Brian Norris, Kalle Valo, Rob Herring,
rajatxjain-Re5JQEeQqe8AvxtiuMwx3w, Dmitry Torokhov
In-Reply-To: <1477084869-15612-1-git-send-email-rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
Hi Rajat,
On Fri, Oct 21, 2016 at 02:21:09PM -0700, Rajat Jain wrote:
> From: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
>
> This patch derives device tree node from pcie bus layer framework, and
> fixes a minor memory leak in mwifiex_pcie_probe() (in failure path).
> Device tree bindings file has been renamed(marvell-sd8xxx.txt ->
> marvell-8xxx.txt) to accommodate PCIe changes.
>
> Signed-off-by: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Amitkumar Karwar <akarwar-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> Reviewed-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> ---
> v2: Included vendor and product IDs in compatible strings for PCIe
> chipsets(Rob Herring)
> v3: Patch is created using -M option so that it will only include diff of
> original and renamed files(Rob Herring)
> Resend v3: Resending the patch because I missed to include device tree mailing
> while sending v3.
> v4: Fix error handling, also move-on even if no device tree node is present.
> v5: Update commit log to include memory leak, return -EINVAL instead of -1.
I've been working on reworking some bugfixes for this driver, and I
noticed we have some problems w.r.t. memory leaks, and the "memory leak"
fix is not actually a fix. See below.
> v6: Remove an unnecessary error print, fix typo in commit log
>
> .../{marvell-sd8xxx.txt => marvell-8xxx.txt} | 8 +++--
> drivers/net/wireless/marvell/mwifiex/pcie.c | 36 +++++++++++++++++++---
> drivers/net/wireless/marvell/mwifiex/sta_cmd.c | 3 +-
> 3 files changed, 39 insertions(+), 8 deletions(-)
> rename Documentation/devicetree/bindings/net/wireless/{marvell-sd8xxx.txt => marvell-8xxx.txt} (91%)
>
> diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
> similarity index 91%
> rename from Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
> rename to Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
> index c421aba..dfe5f8e 100644
> --- a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
> +++ b/Documentation/devicetree/bindings/net/wireless/marvell-8xxx.txt
> @@ -1,8 +1,8 @@
> -Marvell 8897/8997 (sd8897/sd8997) SDIO devices
> +Marvell 8897/8997 (sd8897/sd8997/pcie8997) SDIO/PCIE devices
> ------
>
> -This node provides properties for controlling the marvell sdio wireless device.
> -The node is expected to be specified as a child node to the SDIO controller that
> +This node provides properties for controlling the marvell sdio/pcie wireless device.
> +The node is expected to be specified as a child node to the SDIO/PCIE controller that
> connects the device to the system.
>
> Required properties:
> @@ -10,6 +10,8 @@ Required properties:
> - compatible : should be one of the following:
> * "marvell,sd8897"
> * "marvell,sd8997"
> + * "pci11ab,2b42"
> + * "pci1b4b,2b42"
>
> Optional properties:
>
> diff --git a/drivers/net/wireless/marvell/mwifiex/pcie.c b/drivers/net/wireless/marvell/mwifiex/pcie.c
> index 3c3c4f1..f7c84d3 100644
> --- a/drivers/net/wireless/marvell/mwifiex/pcie.c
> +++ b/drivers/net/wireless/marvell/mwifiex/pcie.c
> @@ -37,6 +37,22 @@ static struct mwifiex_if_ops pcie_ops;
>
> static struct semaphore add_remove_card_sem;
>
> +static const struct of_device_id mwifiex_pcie_of_match_table[] = {
> + { .compatible = "pci11ab,2b42" },
> + { .compatible = "pci1b4b,2b42" },
> + { }
> +};
> +
> +static int mwifiex_pcie_probe_of(struct device *dev)
> +{
> + if (!of_match_node(mwifiex_pcie_of_match_table, dev->of_node)) {
> + dev_err(dev, "required compatible string missing\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int
> mwifiex_map_pci_memory(struct mwifiex_adapter *adapter, struct sk_buff *skb,
> size_t size, int flags)
> @@ -178,6 +194,7 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev,
> const struct pci_device_id *ent)
> {
> struct pcie_service_card *card;
> + int ret;
>
> pr_debug("info: vendor=0x%4.04X device=0x%4.04X rev=%d\n",
> pdev->vendor, pdev->device, pdev->revision);
> @@ -199,13 +216,24 @@ static int mwifiex_pcie_probe(struct pci_dev *pdev,
> card->pcie.can_ext_scan = data->can_ext_scan;
> }
>
> - if (mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
> - MWIFIEX_PCIE)) {
> - pr_err("%s failed\n", __func__);
> - return -1;
> + /* device tree node parsing and platform specific configuration*/
> + if (pdev->dev.of_node) {
> + ret = mwifiex_pcie_probe_of(&pdev->dev);
> + if (ret)
> + goto err_free;
> }
>
> + ret = mwifiex_add_card(card, &add_remove_card_sem, &pcie_ops,
> + MWIFIEX_PCIE);
> + if (ret) {
> + pr_err("%s failed\n", __func__);
> + goto err_free;
For most error cases in mwifiex_add_card(), we call cleanup_if(), which
currently calls kfree(card). It's currently unbalanced, so there are
*some* cases that leak. But...
> + }
> return 0;
> +
> +err_free:
> + kfree(card);
That means that most of the time, this is actually a double-free. I'd
rather have the leak than the double-free :)
Anyway, I have a patch in the works (as part of some device
init/teardown bugfixes) that will convert the allocation to
devm_kzalloc() and drop the kfree()'ing. So that'll fix the
aforementioned bug.
In your next revision (sorry), please just drop this "leak" fix.
Regards,
Brian
> + return ret;
> }
>
> /*
> diff --git a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
> index 2a162c3..c8dccf5 100644
> --- a/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
> +++ b/drivers/net/wireless/marvell/mwifiex/sta_cmd.c
> @@ -2218,7 +2218,8 @@ int mwifiex_sta_init_cmd(struct mwifiex_private *priv, u8 first_sta, bool init)
> * The cal-data can be read from device tree and/or
> * a configuration file and downloaded to firmware.
> */
> - if (priv->adapter->iface_type == MWIFIEX_SDIO &&
> + if ((priv->adapter->iface_type == MWIFIEX_SDIO ||
> + priv->adapter->iface_type == MWIFIEX_PCIE) &&
> adapter->dev->of_node) {
> adapter->dt_node = adapter->dev->of_node;
> if (of_property_read_u32(adapter->dt_node,
> --
> 2.8.0.rc3.226.g39d4020
>
^ permalink raw reply
* [PATCH 1/2] backlight: arcxcnn: add support for ArticSand devices
From: Olimpiu Dejeu @ 2016-10-26 20:29 UTC (permalink / raw)
To: robh
Cc: lee.jones, linux-kernel, linux-fbdev, devicetree, jg1.han,
Olimpiu Dejeu
Resubmition of arcxcnn backliught driver adding devicetree entries
for all registers
Signed-off-by: Olimpiu Dejeu <olimpiu@arcticsand.com>
---
drivers/video/backlight/Kconfig | 7 +
drivers/video/backlight/Makefile | 1 +
drivers/video/backlight/arcxcnn_bl.c | 541 +++++++++++++++++++++++++++++++++++
include/linux/i2c/arcxcnn.h | 67 +++++
4 files changed, 616 insertions(+)
create mode 100644 drivers/video/backlight/arcxcnn_bl.c
create mode 100644 include/linux/i2c/arcxcnn.h
diff --git a/drivers/video/backlight/Kconfig b/drivers/video/backlight/Kconfig
index 5ffa4b4..4e1d2ad 100644
--- a/drivers/video/backlight/Kconfig
+++ b/drivers/video/backlight/Kconfig
@@ -460,6 +460,13 @@ config BACKLIGHT_BD6107
help
If you have a Rohm BD6107 say Y to enable the backlight driver.
+config BACKLIGHT_ARCXCNN
+ tristate "Backlight driver for the Arctic Sands ARCxCnnnn family"
+ depends on I2C
+ help
+ If you have an ARCxCnnnn family backlight say Y to enable
+ the backlight driver.
+
endif # BACKLIGHT_CLASS_DEVICE
endif # BACKLIGHT_LCD_SUPPORT
diff --git a/drivers/video/backlight/Makefile b/drivers/video/backlight/Makefile
index 16ec534..8905129 100644
--- a/drivers/video/backlight/Makefile
+++ b/drivers/video/backlight/Makefile
@@ -55,3 +55,4 @@ obj-$(CONFIG_BACKLIGHT_SKY81452) += sky81452-backlight.o
obj-$(CONFIG_BACKLIGHT_TOSA) += tosa_bl.o
obj-$(CONFIG_BACKLIGHT_TPS65217) += tps65217_bl.o
obj-$(CONFIG_BACKLIGHT_WM831X) += wm831x_bl.o
+obj-$(CONFIG_BACKLIGHT_ARCXCNN) += arcxcnn_bl.o
diff --git a/drivers/video/backlight/arcxcnn_bl.c b/drivers/video/backlight/arcxcnn_bl.c
new file mode 100644
index 0000000..1dad680
--- /dev/null
+++ b/drivers/video/backlight/arcxcnn_bl.c
@@ -0,0 +1,541 @@
+/*
+ * Backlight driver for ArcticSand ARC_X_C_0N_0N Devices
+ *
+ * Copyright 2016 ArcticSand, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/i2c.h>
+#include <linux/backlight.h>
+#include <linux/err.h>
+#include <linux/of.h>
+#include <linux/pwm.h>
+#include <linux/regulator/consumer.h>
+
+#include "linux/i2c/arcxcnn.h"
+
+#define ARCXCNN_CMD (0x00) /* Command Register */
+#define ARCXCNN_CMD_STDBY (0x80) /* I2C Standby */
+#define ARCXCNN_CMD_RESET (0x40) /* Reset */
+#define ARCXCNN_CMD_BOOST (0x10) /* Boost */
+#define ARCXCNN_CMD_OVP_MASK (0x0C) /* --- Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_XXV (0x0C) /* <rsvrd> Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_20V (0x08) /* 20v Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_24V (0x04) /* 24v Over Voltage Threshold */
+#define ARCXCNN_CMD_OVP_31V (0x00) /* 31.4v Over Voltage Threshold */
+#define ARCXCNN_CMD_EXT_COMP (0x01) /* part (0) or full (1) external comp */
+
+#define ARCXCNN_CONFIG (0x01) /* Configuration */
+#define ARCXCNN_STATUS1 (0x02) /* Status 1 */
+#define ARCXCNN_STATUS2 (0x03) /* Status 2 */
+#define ARCXCNN_FADECTRL (0x04) /* Fading Control */
+#define ARCXCNN_ILED_CONFIG (0x05) /* ILED Configuration */
+
+#define ARCXCNN_LEDEN (0x06) /* LED Enable Register */
+#define ARCXCNN_LEDEN_ISETEXT (0x80) /* Full-scale current set externally */
+#define ARCXCNN_LEDEN_MASK (0x3F) /* LED string enables */
+#define ARCXCNN_LEDEN_LED1 (0x01)
+#define ARCXCNN_LEDEN_LED2 (0x02)
+#define ARCXCNN_LEDEN_LED3 (0x04)
+#define ARCXCNN_LEDEN_LED4 (0x08)
+#define ARCXCNN_LEDEN_LED5 (0x10)
+#define ARCXCNN_LEDEN_LED6 (0x20)
+
+#define ARCXCNN_WLED_ISET_LSB (0x07) /* LED ISET LSB (in upper nibble) */
+#define ARCXCNN_WLED_ISET_MSB (0x08) /* LED ISET MSB (8 bits) */
+
+#define ARCXCNN_DIMFREQ (0x09)
+#define ARCXCNN_COMP_CONFIG (0x0A)
+#define ARCXCNN_FILT_CONFIG (0x0B)
+#define ARCXCNN_IMAXTUNE (0x0C)
+
+#define DEFAULT_BL_NAME "arctic_bl"
+#define MAX_BRIGHTNESS 4095
+
+static int s_no_reset_on_remove;
+module_param_named(noreset, s_no_reset_on_remove, int, 0644);
+MODULE_PARM_DESC(noreset, "No reset on module removal");
+
+static int s_ibright = 60;
+module_param_named(ibright, s_ibright, int, 0644);
+MODULE_PARM_DESC(ibright, "Initial brightness (when no plat data)");
+
+static int s_iledstr = 0x3F;
+module_param_named(iledstr, s_iledstr, int, 0644);
+MODULE_PARM_DESC(iledstr, "Initial LED String (when no plat data)");
+
+static int s_retries = 2; /* 1 == only one try */
+module_param_named(retries, s_retries, int, 0644);
+MODULE_PARM_DESC(retries, "I2C retries attempted");
+
+enum arcxcnn_brightness_ctrl_mode {
+ PWM_BASED = 1,
+ REGISTER_BASED,
+};
+
+struct arcxcnn;
+
+struct arcxcnn {
+ char chipname[64];
+ enum arcxcnn_chip_id chip_id;
+ enum arcxcnn_brightness_ctrl_mode mode;
+ struct i2c_client *client;
+ struct backlight_device *bl;
+ struct device *dev;
+ struct arcxcnn_platform_data *pdata;
+ struct pwm_device *pwm;
+ struct regulator *supply; /* regulator for VDD input */
+};
+
+static int arcxcnn_write_byte(struct arcxcnn *lp, u8 reg, u8 data)
+{
+ s32 ret = -1;
+ int att;
+
+ for (att = 0; att < s_retries; att++) {
+ ret = i2c_smbus_write_byte_data(lp->client, reg, data);
+ if (ret >= 0)
+ return 0;
+ }
+ return ret;
+}
+
+static u8 arcxcnn_read_byte(struct arcxcnn *lp, u8 reg)
+{
+ int val;
+ int att;
+
+ for (att = 0; att < s_retries; att++) {
+ val = i2c_smbus_read_byte_data(lp->client, reg);
+ if (val >= 0)
+ return (u8)val;
+ }
+ return 0;
+}
+
+static int arcxcnn_update_bit(struct arcxcnn *lp, u8 reg, u8 mask, u8 data)
+{
+ int ret, att;
+ u8 tmp;
+
+ for (att = 0, ret = -1; att < s_retries; att++) {
+ ret = i2c_smbus_read_byte_data(lp->client, reg);
+ if (ret >= 0)
+ break;
+ }
+ if (ret < 0) {
+ dev_err(lp->dev, "failed to read 0x%.2x\n", reg);
+ return ret;
+ }
+
+ tmp = (u8)ret;
+ tmp &= ~mask;
+ tmp |= data & mask;
+
+ return arcxcnn_write_byte(lp, reg, tmp);
+}
+
+static int arcxcnn_set_brightness(struct arcxcnn *lp, u32 brightness)
+{
+ int ret;
+ u8 val;
+
+ val = (brightness & 0xF) << 4;
+ ret = arcxcnn_write_byte(lp, ARCXCNN_WLED_ISET_LSB, val);
+ if (ret < 0)
+ return ret;
+ val = (brightness >> 4);
+ ret = arcxcnn_write_byte(lp, ARCXCNN_WLED_ISET_MSB, val);
+ return ret;
+}
+
+static int arcxcnn_bl_update_status(struct backlight_device *bl)
+{
+ struct arcxcnn *lp = bl_get_data(bl);
+ u32 brightness = bl->props.brightness;
+
+ if (bl->props.state & (BL_CORE_SUSPENDED | BL_CORE_FBBLANK))
+ brightness = 0;
+
+ /* set brightness */
+ if (lp->mode == PWM_BASED)
+ ; /* via pwm */
+ else if (lp->mode == REGISTER_BASED)
+ arcxcnn_set_brightness(lp, brightness);
+
+ /* set power-on/off/save modes */
+ if (bl->props.power == 0)
+ /* take out of standby */
+ arcxcnn_update_bit(lp, ARCXCNN_CMD, ARCXCNN_CMD_STDBY, 0);
+ else
+ /* 1-3 == power save, 4 = off
+ * place in low-power standby mode
+ */
+ arcxcnn_update_bit(lp, ARCXCNN_CMD,
+ ARCXCNN_CMD_STDBY, ARCXCNN_CMD_STDBY);
+ return 0;
+}
+
+static const struct backlight_ops arcxcnn_bl_ops = {
+ .options = BL_CORE_SUSPENDRESUME,
+ .update_status = arcxcnn_bl_update_status,
+};
+
+static int arcxcnn_backlight_register(struct arcxcnn *lp)
+{
+ struct backlight_device *bl;
+ struct backlight_properties props;
+ struct arcxcnn_platform_data *pdata = lp->pdata;
+ const char *name = pdata->name ? : DEFAULT_BL_NAME;
+
+ memset(&props, 0, sizeof(props));
+ props.type = BACKLIGHT_PLATFORM;
+ props.max_brightness = MAX_BRIGHTNESS;
+
+ if (pdata->initial_brightness > props.max_brightness)
+ pdata->initial_brightness = props.max_brightness;
+
+ props.brightness = pdata->initial_brightness;
+
+ bl = devm_backlight_device_register(lp->dev, name, lp->dev, lp,
+ &arcxcnn_bl_ops, &props);
+ if (IS_ERR(bl))
+ return PTR_ERR(bl);
+
+ lp->bl = bl;
+
+ return 0;
+}
+
+static ssize_t arcxcnn_get_chip_id(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct arcxcnn *lp = dev_get_drvdata(dev);
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n", lp->chipname);
+}
+
+static ssize_t arcxcnn_get_led_str(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct arcxcnn *lp = dev_get_drvdata(dev);
+
+ return scnprintf(buf, PAGE_SIZE, "%02X\n", lp->pdata->led_str);
+}
+
+static ssize_t arcxcnn_set_led_str(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct arcxcnn *lp = dev_get_drvdata(dev);
+ unsigned long ledstr;
+
+ if (kstrtoul(buf, 0, &ledstr))
+ return 0;
+
+ if (ledstr != lp->pdata->led_str) {
+ /* don't allow 0 for ledstr, use power to turn all off */
+ if (ledstr == 0)
+ return 0;
+ lp->pdata->led_str = ledstr & 0x3F;
+ arcxcnn_update_bit(lp, ARCXCNN_LEDEN,
+ ARCXCNN_LEDEN_MASK, lp->pdata->led_str);
+ }
+ return len;
+}
+
+static ssize_t arcxcnn_get_bl_ctl_mode(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct arcxcnn *lp = dev_get_drvdata(dev);
+ char *strmode = NULL;
+
+ if (lp->mode == PWM_BASED)
+ strmode = "pwm based";
+ else if (lp->mode == REGISTER_BASED)
+ strmode = "register based";
+
+ return scnprintf(buf, PAGE_SIZE, "%s\n", strmode);
+}
+
+static DEVICE_ATTR(chip_id, 0444, arcxcnn_get_chip_id, NULL);
+static DEVICE_ATTR(led_str, 0664, arcxcnn_get_led_str, arcxcnn_set_led_str);
+static DEVICE_ATTR(bl_ctl_mode, 0444, arcxcnn_get_bl_ctl_mode, NULL);
+
+static struct attribute *arcxcnn_attributes[] = {
+ &dev_attr_chip_id.attr,
+ &dev_attr_led_str.attr,
+ &dev_attr_bl_ctl_mode.attr,
+ NULL,
+};
+
+static const struct attribute_group arcxcnn_attr_group = {
+ .attrs = arcxcnn_attributes,
+};
+
+#ifdef CONFIG_OF
+static int arcxcnn_parse_dt(struct arcxcnn *lp)
+{
+ struct device *dev = lp->dev;
+ struct device_node *node = dev->of_node;
+ u32 prog_val, num_entry, sources[6];
+ int ret;
+
+ if (!node) {
+ dev_err(dev, "no platform data.\n");
+ return -EINVAL;
+ }
+ lp->pdata->led_config_0_set = false;
+ lp->pdata->led_config_1_set = false;
+ lp->pdata->dim_freq_set = false;
+ lp->pdata->comp_config_set = false;
+ lp->pdata->filter_config_set = false;
+ lp->pdata->trim_config_set = false;
+
+ ret = of_property_read_string(node, "label", &lp->pdata->name);
+ if (ret < 0)
+ lp->pdata->name = NULL;
+
+ ret = of_property_read_u32(node, "default-brightness", &prog_val);
+ if (ret < 0)
+ prog_val = s_ibright;
+ lp->pdata->initial_brightness = prog_val;
+ if (lp->pdata->initial_brightness > MAX_BRIGHTNESS)
+ lp->pdata->initial_brightness = MAX_BRIGHTNESS;
+
+ ret = of_property_read_u32(node, "arcticsand,led-config-0", &prog_val);
+ if (ret == 0) {
+ lp->pdata->led_config_0 = (u8)prog_val;
+ lp->pdata->led_config_0_set = true;
+ }
+ ret = of_property_read_u32(node, "arcticsand,led-config-1", &prog_val);
+ if (ret == 0) {
+ lp->pdata->led_config_1 = (u8)prog_val;
+ lp->pdata->led_config_1_set = true;
+ }
+ ret = of_property_read_u32(node, "arcticsand,dim-freq", &prog_val);
+ if (ret == 0) {
+ lp->pdata->dim_freq = (u8)prog_val;
+ lp->pdata->dim_freq_set = true;
+ }
+ ret = of_property_read_u32(node, "arcticsand,comp-config", &prog_val);
+ if (ret == 0) {
+ lp->pdata->comp_config = (u8)prog_val;
+ lp->pdata->comp_config_set = true;
+ }
+ ret = of_property_read_u32(node, "arcticsand,filter-config", &prog_val);
+ if (ret == 0) {
+ lp->pdata->filter_config = (u8)prog_val;
+ lp->pdata->filter_config_set = true;
+ }
+ ret = of_property_read_u32(node, "arcticsand,trim-config", &prog_val);
+ if (ret == 0) {
+ lp->pdata->trim_config = (u8)prog_val;
+ lp->pdata->trim_config_set = true;
+ }
+ ret = of_property_count_u32_elems(node, "led-sources");
+ if (ret < 0)
+ lp->pdata->led_str = 0x3F;
+ else {
+ num_entry = ret;
+ if (num_entry > 6)
+ num_entry = 6;
+
+ ret = of_property_read_u32_array(node, "led-sources", sources,
+ num_entry);
+ if (ret < 0) {
+ dev_err(dev, "led-sources node is invalid.\n");
+ return -EINVAL;
+ }
+
+ lp->pdata->led_str = 0;
+ while (num_entry > 0)
+ lp->pdata->led_str |= (1 << sources[--num_entry]);
+ }
+ return 0;
+}
+#else
+static int arcxcnn_parse_dt(struct arcxcnn *lp)
+{
+ return -EINVAL;
+}
+#endif
+
+static int arcxcnn_probe(struct i2c_client *cl, const struct i2c_device_id *id)
+{
+ struct arcxcnn *lp;
+ int ret;
+ u8 regval;
+ u16 chipid;
+
+ if (!i2c_check_functionality(cl->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -EIO;
+
+ lp = devm_kzalloc(&cl->dev, sizeof(*lp), GFP_KERNEL);
+ if (!lp)
+ return -ENOMEM;
+
+ lp->client = cl;
+ lp->dev = &cl->dev;
+ lp->chip_id = id->driver_data;
+ lp->pdata = dev_get_platdata(&cl->dev);
+
+ if (!lp->pdata) {
+ lp->pdata = devm_kzalloc(lp->dev,
+ sizeof(*lp->pdata), GFP_KERNEL);
+ if (!lp->pdata)
+ return -ENOMEM;
+
+ /* no platform data, parse the device-tree for info. if there
+ * is no device tree entry, we are being told we exist because
+ * user-land said so, so make up the info we need
+ */
+ ret = arcxcnn_parse_dt(lp);
+ if (ret < 0) {
+ /* no device tree, use defaults based on module params
+ */
+ lp->pdata->led_config_0_set = false;
+ lp->pdata->led_config_1_set = false;
+ lp->pdata->dim_freq_set = false;
+ lp->pdata->comp_config_set = false;
+ lp->pdata->filter_config_set = false;
+ lp->pdata->trim_config_set = false;
+
+ lp->pdata->name = NULL;
+ lp->pdata->initial_brightness = s_ibright;
+ lp->pdata->led_str = s_iledstr;
+ }
+ }
+
+ if (lp->pdata->dim_freq_set)
+ lp->mode = PWM_BASED;
+ else
+ lp->mode = REGISTER_BASED;
+
+ i2c_set_clientdata(cl, lp);
+
+ /* read device ID */
+ regval = arcxcnn_read_byte(lp, 0x1E);
+ chipid = regval;
+ chipid <<= 8;
+ regval = arcxcnn_read_byte(lp, 0x1F);
+ chipid |= regval;
+
+ /* make sure it belongs to this driver
+ * TODO - handle specific ids
+ */
+ if (chipid != 0x02A5) {
+ #if 1
+ dev_info(&cl->dev, "Chip Id is %04X\n", chipid);
+ #else
+ dev_err(&cl->dev, "%04X is not ARC2C\n", chipid);
+ return -ENODEV;
+ #endif
+ }
+ /* reset the device */
+ arcxcnn_write_byte(lp, ARCXCNN_CMD, ARCXCNN_CMD_RESET);
+
+ /* set initial brightness */
+ arcxcnn_set_brightness(lp, lp->pdata->initial_brightness);
+
+ /* if fadectrl set in DT, set the value directly, else leave default */
+ if (lp->pdata->led_config_0_set)
+ arcxcnn_write_byte(lp, ARCXCNN_FADECTRL,
+ lp->pdata->led_config_0);
+
+ /* if iled config set in DT, set the value, else internal mode */
+ if (lp->pdata->led_config_1_set)
+ arcxcnn_write_byte(lp, ARCXCNN_ILED_CONFIG,
+ lp->pdata->led_config_1);
+ else
+ arcxcnn_write_byte(lp, ARCXCNN_ILED_CONFIG, 0x57);
+
+ /* other misc DT settings */
+ if (lp->pdata->dim_freq_set)
+ arcxcnn_write_byte(lp, ARCXCNN_FADECTRL, lp->pdata->dim_freq);
+ if (lp->pdata->comp_config_set)
+ arcxcnn_write_byte(lp, ARCXCNN_COMP_CONFIG,
+ lp->pdata->comp_config);
+ if (lp->pdata->filter_config_set)
+ arcxcnn_write_byte(lp, ARCXCNN_FILT_CONFIG,
+ lp->pdata->filter_config);
+ if (lp->pdata->trim_config_set)
+ arcxcnn_write_byte(lp, ARCXCNN_IMAXTUNE,
+ lp->pdata->trim_config);
+
+ /* set initial LED Strings */
+ arcxcnn_update_bit(lp, ARCXCNN_LEDEN,
+ ARCXCNN_LEDEN_MASK, lp->pdata->led_str);
+
+ snprintf(lp->chipname, sizeof(lp->chipname),
+ "%s-%04X", id->name, chipid);
+
+ ret = arcxcnn_backlight_register(lp);
+ if (ret) {
+ dev_err(lp->dev,
+ "failed to register backlight. err: %d\n", ret);
+ return ret;
+ }
+
+ ret = sysfs_create_group(&lp->dev->kobj, &arcxcnn_attr_group);
+ if (ret) {
+ dev_err(lp->dev, "failed to register sysfs. err: %d\n", ret);
+ return ret;
+ }
+
+ backlight_update_status(lp->bl);
+ return 0;
+}
+
+static int arcxcnn_remove(struct i2c_client *cl)
+{
+ struct arcxcnn *lp = i2c_get_clientdata(cl);
+
+ if (!s_no_reset_on_remove) {
+ /* disable all strings */
+ arcxcnn_write_byte(lp, ARCXCNN_LEDEN, 0x00);
+ /* reset the device */
+ arcxcnn_write_byte(lp, ARCXCNN_CMD, ARCXCNN_CMD_RESET);
+ }
+ lp->bl->props.brightness = 0;
+ backlight_update_status(lp->bl);
+ if (lp->supply)
+ regulator_disable(lp->supply);
+ sysfs_remove_group(&lp->dev->kobj, &arcxcnn_attr_group);
+
+ return 0;
+}
+
+static const struct of_device_id arcxcnn_dt_ids[] = {
+ { .compatible = "arc,arc2c0608" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, arcxcnn_dt_ids);
+
+/* Note that the device/chip ID is not fixed in silicon so
+ * auto-probing of these devices on the bus is most likely
+ * not possible, use device tree to set i2c bus address
+ */
+static const struct i2c_device_id arcxcnn_ids[] = {
+ {"arc2c0608", ARC2C0608},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, arcxcnn_ids);
+
+static struct i2c_driver arcxcnn_driver = {
+ .driver = {
+ .name = "arcxcnn_bl",
+ .of_match_table = of_match_ptr(arcxcnn_dt_ids),
+ },
+ .probe = arcxcnn_probe,
+ .remove = arcxcnn_remove,
+ .id_table = arcxcnn_ids,
+};
+
+module_i2c_driver(arcxcnn_driver);
+
+MODULE_LICENSE("GPL v2");
+MODULE_AUTHOR("Brian Dodge <bdodge09@outlook.com>");
+MODULE_DESCRIPTION("ARCXCNN Backlight driver");
diff --git a/include/linux/i2c/arcxcnn.h b/include/linux/i2c/arcxcnn.h
new file mode 100644
index 0000000..1c681dd
--- /dev/null
+++ b/include/linux/i2c/arcxcnn.h
@@ -0,0 +1,67 @@
+/*
+ * Backlight driver for ArcticSand ARC2C0608 Backlight Devices
+ *
+ * Copyright 2016 ArcticSand, Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#ifndef _ARCXCNN_H
+#define _ARCXCNN_H
+
+enum arcxcnn_chip_id {
+ ARC2C0608
+};
+
+enum arcxcnn_brightness_source {
+ ARCXCNN_PWM_ONLY,
+ ARCXCNN_I2C_ONLY = 2,
+};
+
+#define ARCXCNN_MAX_PROGENTRIES 48 /* max a/v pairs for custom */
+
+/**
+ * struct arcxcnn_platform_data
+ * @name : Backlight driver name. If it is not defined, default name is set.
+ * @initial_brightness : initial value of backlight brightness
+ * @led_str : initial LED string enables, upper bit is global on/off
+ * @led_config_0 : fading speed (period between intensity steps)
+ * @led_config_1 : misc settings, see datasheet
+ * @dim_freq : pwm dimming frequency if in pwm mode
+ * @comp_config : misc config, see datasheet
+ * @filter_config: RC/PWM filter config, see datasheet
+ * @trim_config : full scale current trim, see datasheet
+ * @led_config_0_set : the value in led_config_0 is valid
+ * @led_config_1_set : the value in led_config_1 is valid
+ * @dim_freq_set : the value in dim_freq is valid
+ * @comp_config_set : the value in comp_config is valid
+ * @filter_config_set : the value in filter_config is valid
+ * @trim_config_set : the value in trim_config is valid
+ *
+ * the _set flags are used to indicate that the value was explicitly set
+ * in the device tree or platform data. settings not set are left as default
+ * power-on default values of the chip except for led_str and led_config_1
+ * which are set by the driver (led_str is specified indirectly in the
+ * device tree via "led-sources")
+ */
+struct arcxcnn_platform_data {
+ const char *name;
+ u16 initial_brightness;
+ u8 led_str;
+
+ u8 led_config_0;
+ u8 led_config_1;
+ u8 dim_freq;
+ u8 comp_config;
+ u8 filter_config;
+ u8 trim_config;
+
+ bool led_config_0_set;
+ bool led_config_1_set;
+ bool dim_freq_set;
+ bool comp_config_set;
+ bool filter_config_set;
+ bool trim_config_set;
+};
+
+#endif
--
2.7.4
^ permalink raw reply related
* [PATCH 2/2] backlight: arcxcnn: devicetree bindings for ArticSand devices
From: Olimpiu Dejeu @ 2016-10-26 20:30 UTC (permalink / raw)
To: robh
Cc: lee.jones, linux-kernel, linux-fbdev, devicetree, jg1.han,
Olimpiu Dejeu
Resubmition of arcxcnn backliught driver bindings with added register
documentation
Signed-off-by: Olimpiu Dejeu <olimpiu@arcticsand.com>
---
.../bindings/leds/backlight/arcxcnn_bl.txt | 31 ++++++++++++++++++++++
1 file changed, 31 insertions(+)
create mode 100644 Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt
diff --git a/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt b/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt
new file mode 100644
index 0000000..a7b6ff2
--- /dev/null
+++ b/Documentation/devicetree/bindings/leds/backlight/arcxcnn_bl.txt
@@ -0,0 +1,31 @@
+Binding for ArcticSand arc2c0608 LED driver
+
+Required properties:
+- compatible: should be "arc,arc2c0608"
+- reg: slave address
+
+Optional properties:
+- default-brightness: brightness value on boot, value from: 0-4095
+- label: The name of the backlight device
+ See Documentation/devicetree/bindings/leds/common.txt
+- led-sources: List of enabled channels from 0 to 5.
+ See Documentation/devicetree/bindings/leds/common.txt
+
+- arcticsand,led-config-0: setting for register ILED_CONFIG_0
+- arcticsand,led-config-1: setting for register ILED_CONFIG_1
+- arcticsand,dim-freq: PWM mode frequence setting (bits [3:0] used)
+- arcticsand,comp-config: setting for register CONFIG_COMP
+- arcticsand,filter-config: setting for register FILTER_CONFIG
+- arcticsand,trim-config: setting for register IMAXTUNE
+
+Example:
+
+arc2c0608@30 {
+ compatible = "arc,arc2c0608";
+ reg = <0x30>;
+ default-brightness = <500>;
+ label = "lcd-backlight";
+ linux,default-trigger = "backlight";
+ led-sources = <0 1 2 5>;
+};
+
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 1/6] dt: bindings: Add Allwinner Q8 tablets hardware manager bindings
From: Rob Herring @ 2016-10-26 20:39 UTC (permalink / raw)
To: Hans de Goede
Cc: Mark Rutland, Arnd Bergmann, Greg Kroah-Hartman, Maxime Ripard,
Chen-Yu Tsai, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree
In-Reply-To: <20161014075337.10452-2-hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
On Fri, Oct 14, 2016 at 09:53:32AM +0200, Hans de Goede wrote:
> Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets
> of which a new batch is produced every few weeks. Each batch uses a
> different mix of touchscreen, accelerometer and wifi peripherals.
>
> Given that each batch is different creating a devicetree for each variant
> is not desirable, work is being done on a Q8 tablet hardware manager which
> auto-detects the touchscreen and accelerometer and will update the dt with
> what it has found, so that a single generic dt can be used for these tablets.
>
> This commit adds dt-bindings for this hardware manager.
>
> Note the wifi is connected to a discoverable bus (sdio or usb) and will be
> autodetected by the mmc resp. usb subsystems.
>
> Signed-off-by: Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> ---
> .../misc/allwinner,sunxi-q8-hardwaremgr.txt | 71 ++++++++++++++++++++++
> 1 file changed, 71 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
>
> diff --git a/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> new file mode 100644
> index 0000000..a81b258
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/misc/allwinner,sunxi-q8-hardwaremgr.txt
> @@ -0,0 +1,71 @@
> +Q8 tablet hardware manager
> +--------------------------
> +
> +Allwinnner A13 / A23 / A33 based Q8 tablets are popular cheap 7" tablets of
> +which a new batch is produced every few weeks. Each batch uses a different
> +mix of touchscreen, accelerometer and wifi peripherals.
> +
> +Given that each batch is different creating a devicetree for each variant is
> +not desirable. The Q8 tablet hardware manager bindings are bindings for an os
> +module which auto-detects the touchscreen and accelerometer so that a single
> +generic dts can be used for these tablets.
> +
> +The wifi is connected to a discoverable bus and will be autodetected by the os.
> +
> +Required properties:
> + - toplevel / machine compatible, one of:
> + "allwinner,q8-a13"
> + "allwinner,q8-a23"
> + "allwinner,q8-a33"
> + - touchscreen node : There must be a template touchscreen node named
> + "touchscreen", this must be a child node of the
> + touchscreen i2c bus
> + - accelerometer node : There must be a template accelerometer node named
> + "accelerometer", this must be a child node of the
> + accelerometer i2c bus
> +
> +touchscreen node required properties:
> + - interrupt-parent : phandle pointing to the interrupt controller
> + serving the touchscreen interrupt
> + - interrupts : interrupt specification for the touchscreen interrupt
> + - power-gpios : Specification for the pin connected to the touchscreen's
> + enable / wake pin. This needs to be driven high to
> + enable the touchscreen controller
enable-gpios is the common name.
I was going to say you need to list possible compatible strings here
also. However, I now wonder if this binding doc is even needed. The
binding docs should just be the bindings for each touchscreen or
accelerometer. The fact that the node is completed at run-time whether
the bootloader or kernel doesn't matter for the binding definition. When
and it is completed is orthogonal to the binding definition.
Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v6] mwifiex: parse device tree node for PCIe
From: Dmitry Torokhov @ 2016-10-26 20:46 UTC (permalink / raw)
To: Brian Norris
Cc: Rajat Jain, linux-wireless-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Xinming Hu, Amitkumar Karwar,
Brian Norris, Kalle Valo, Rob Herring,
rajatxjain-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20161026201735.GA10192@localhost>
On Wed, Oct 26, 2016 at 01:17:36PM -0700, Brian Norris wrote:
> Hi Rajat,
>
> On Fri, Oct 21, 2016 at 02:21:09PM -0700, Rajat Jain wrote:
> > From: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> >
> > This patch derives device tree node from pcie bus layer framework, and
> > fixes a minor memory leak in mwifiex_pcie_probe() (in failure path).
> > Device tree bindings file has been renamed(marvell-sd8xxx.txt ->
> > marvell-8xxx.txt) to accommodate PCIe changes.
> >
> > Signed-off-by: Xinming Hu <huxm-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> > Signed-off-by: Amitkumar Karwar <akarwar-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
> > Signed-off-by: Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
> > Reviewed-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> > ---
> > v2: Included vendor and product IDs in compatible strings for PCIe
> > chipsets(Rob Herring)
> > v3: Patch is created using -M option so that it will only include diff of
> > original and renamed files(Rob Herring)
> > Resend v3: Resending the patch because I missed to include device tree mailing
> > while sending v3.
> > v4: Fix error handling, also move-on even if no device tree node is present.
> > v5: Update commit log to include memory leak, return -EINVAL instead of -1.
>
> I've been working on reworking some bugfixes for this driver, and I
> noticed we have some problems w.r.t. memory leaks, and the "memory leak"
> fix is not actually a fix. See below.
Sorry, I just saw this... Why do we need devicetree data for
discoverable bus (PCI)? How does the driver work on systems that do not
use DT? Why do we need them to behave differently?
Thanks.
--
Dmitry
^ permalink raw reply
* Re: [PATCH v6] mwifiex: parse device tree node for PCIe
From: Rajat Jain @ 2016-10-26 20:51 UTC (permalink / raw)
To: Dmitry Torokhov
Cc: Brian Norris, linux-wireless, devicetree, Xinming Hu,
Amitkumar Karwar, Brian Norris, Kalle Valo, Rob Herring,
Rajat Jain
In-Reply-To: <20161026204648.GD3989@dtor-ws>
[-- Attachment #1: Type: text/plain, Size: 2113 bytes --]
On Wed, Oct 26, 2016 at 1:46 PM, Dmitry Torokhov <dmitry.torokhov@gmail.com>
wrote:
> On Wed, Oct 26, 2016 at 01:17:36PM -0700, Brian Norris wrote:
> > Hi Rajat,
> >
> > On Fri, Oct 21, 2016 at 02:21:09PM -0700, Rajat Jain wrote:
> > > From: Xinming Hu <huxm@marvell.com>
> > >
> > > This patch derives device tree node from pcie bus layer framework, and
> > > fixes a minor memory leak in mwifiex_pcie_probe() (in failure path).
> > > Device tree bindings file has been renamed(marvell-sd8xxx.txt ->
> > > marvell-8xxx.txt) to accommodate PCIe changes.
> > >
> > > Signed-off-by: Xinming Hu <huxm@marvell.com>
> > > Signed-off-by: Amitkumar Karwar <akarwar@marvell.com>
> > > Signed-off-by: Rajat Jain <rajatja@google.com>
> > > Reviewed-by: Brian Norris <briannorris@chromium.org>
> > > ---
> > > v2: Included vendor and product IDs in compatible strings for PCIe
> > > chipsets(Rob Herring)
> > > v3: Patch is created using -M option so that it will only include diff
> of
> > > original and renamed files(Rob Herring)
> > > Resend v3: Resending the patch because I missed to include device tree
> mailing
> > > while sending v3.
> > > v4: Fix error handling, also move-on even if no device tree node is
> present.
> > > v5: Update commit log to include memory leak, return -EINVAL instead
> of -1.
> >
> > I've been working on reworking some bugfixes for this driver, and I
> > noticed we have some problems w.r.t. memory leaks, and the "memory leak"
> > fix is not actually a fix. See below.
>
> Sorry, I just saw this... Why do we need devicetree data for
> discoverable bus (PCI)? How does the driver work on systems that do not
> use DT? Why do we need them to behave differently?
>
There are a couple of out-of-band GPIO pins from Marvell chip that can
serve as wake-up pins (wake up the CPU when asserted). The Marvell chip has
to be told which GPIO pin is to be used as the wake-up pin. The pin to be
used is system / platform dependent. (On some systems it could be GPIO13,
on others it could be GPIO14 etc depending on how the marvell chip is wired
up to the CPU).
>
> Thanks.
>
> --
> Dmitry
>
[-- Attachment #2: Type: text/html, Size: 3155 bytes --]
^ permalink raw reply
* Re: Add Allwinner Q8 tablets hardware manager
From: Rob Herring @ 2016-10-26 20:54 UTC (permalink / raw)
To: Mark Rutland, Hans de Goede
Cc: Arnd Bergmann, Greg Kroah-Hartman, Maxime Ripard, Chen-Yu Tsai,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, devicetree
In-Reply-To: <20161024173900.GP15620@leverpostej>
On Mon, Oct 24, 2016 at 06:39:01PM +0100, Mark Rutland wrote:
> On Fri, Oct 14, 2016 at 09:53:31AM +0200, Hans de Goede wrote:
> > Hi Rob, Mark, et al.,
>
> Hi Hans,
>
> Apologies for the delay in replying to this.
>
> I'd like to be clear that I do understand that there is a problem that
> needs to be addressed here. However, I do not believe that the *current*
> in-kernel approach is correct. More on that below.
>
> > Mark, I know that we discussed this at ELCE and you clearly indicated
> > that according to you this does not belong in the kernel. I was a bit
> > surprised by this part of the discussion.
> >
> > I had posted a RFC earlier and Rob had indicated that given that the q8
> > tablets are a special case, as my code uses actual probing rather then some
> > pre-arranged id mechanism with say an eeprom, that doing this in a
> > non-generic manner would be ok for my special case.
>
> To some extent, Rob and I may have differing views here; I'm not
> entirely sure what Rob's view is, and I cannot talk on his behalf. I
> certainly must apologise for having not commented on said RFC, however.
I've focused mainly on the bindings which I certainly had issues with
how the RFC was done. As to where this should be done, keeping all the
dirty bits in firmware/bootloader is certainly appealing. However, there
are cases where data alone can't abstract out board differences and we
need board code. Whether this is one of them, well, that is Hans' job to
convince Mark.
Rob
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox