* [PATCH 2/4] drivers: base: cacheinfo: fix boot error message when acpi is enabled
From: Sudeep Holla @ 2016-10-28 8:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Greg Kroah-Hartman
Cc: Sudeep Holla, x86-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477644331-25559-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
ARM64 enables both CONFIG_OF and CONFIG_ACPI and the firmware can pass
both ACPI tables and the device tree. Based on the kernel parameter, one
of the two will be chosen. If acpi is enabled, then device tree is not
unflattened.
Currently ARM64 platforms report:
"
Failed to find cpu0 device node
Unable to detect cache hierarchy from DT for CPU 0
"
which is incorrect when booting with ACPI. Also latest ACPI v6.1 has no
support for cache properties/hierarchy.
This patch adds check for unflattened device tree and also returns as
"not supported" if ACPI is runtime enabled.
It also removes the reference to DT from the error message as the cache
hierarchy can be detected from the firmware(OF/DT/ACPI)
Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
drivers/base/cacheinfo.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index ecde8957835a..70e13cf06ed0 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -16,6 +16,7 @@
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#include <linux/acpi.h>
#include <linux/bitops.h>
#include <linux/cacheinfo.h>
#include <linux/compiler.h>
@@ -104,12 +105,16 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
struct cacheinfo *this_leaf, *sib_leaf;
unsigned int index;
- int ret;
+ int ret = 0;
if (this_cpu_ci->cpu_map_populated)
return 0;
- ret = cache_setup_of_node(cpu);
+ if (of_have_populated_dt())
+ ret = cache_setup_of_node(cpu);
+ else if (!acpi_disabled)
+ /* No cache property/hierarchy support yet in ACPI */
+ ret = -ENOTSUPP;
if (ret)
return ret;
@@ -206,8 +211,7 @@ static int detect_cache_attributes(unsigned int cpu)
*/
ret = cache_shared_cpu_map_setup(cpu);
if (ret) {
- pr_warn("Unable to detect cache hierarchy from DT for CPU %d\n",
- cpu);
+ pr_warn("Unable to detect cache hierarchy for CPU %d\n", cpu);
goto free_ci;
}
return 0;
--
2.7.4
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* [PATCH 1/4] drivers: base: cacheinfo: fix x86 with CONFIG_OF enabled
From: Sudeep Holla @ 2016-10-28 8:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Greg Kroah-Hartman
Cc: Sudeep Holla, x86-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477644331-25559-1-git-send-email-sudeep.holla-5wv7dgnIgG8@public.gmane.org>
With CONFIG_OF enabled on x86, we get the following error on boot:
"
Failed to find cpu0 device node
Unable to detect cache hierarchy from DT for CPU 0
"
and the cacheinfo fails to get populated in the corresponding sysfs
entries. This is because cache_setup_of_node looks for of_node for
setting up the shared cpu_map without checking that it's already
populated in the architecture specific callback.
In order to indicate that the shared cpu_map is already populated, this
patch introduces a boolean `cpu_map_populated` in struct cpu_cacheinfo
that can be used by the generic code to skip cache_shared_cpu_map_setup.
This patch also sets that boolean for x86.
Cc: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
Signed-off-by: Sudeep Holla <sudeep.holla-5wv7dgnIgG8@public.gmane.org>
---
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 ++
drivers/base/cacheinfo.c | 3 +++
include/linux/cacheinfo.h | 1 +
3 files changed, 6 insertions(+)
diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index de6626c18e42..be6337156502 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -934,6 +934,8 @@ static int __populate_cache_leaves(unsigned int cpu)
ci_leaf_init(this_leaf++, &id4_regs);
__cache_cpumap_setup(cpu, idx, &id4_regs);
}
+ this_cpu_ci->cpu_map_populated = true;
+
return 0;
}
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index e9fd32e91668..ecde8957835a 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -106,6 +106,9 @@ static int cache_shared_cpu_map_setup(unsigned int cpu)
unsigned int index;
int ret;
+ if (this_cpu_ci->cpu_map_populated)
+ return 0;
+
ret = cache_setup_of_node(cpu);
if (ret)
return ret;
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 2189935075b4..a951fd10aaaa 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -71,6 +71,7 @@ struct cpu_cacheinfo {
struct cacheinfo *info_list;
unsigned int num_levels;
unsigned int num_leaves;
+ bool cpu_map_populated;
};
/*
--
2.7.4
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^ permalink raw reply related
* [PATCH 0/4] drivers: base: cacheinfo: fixes/updates
From: Sudeep Holla @ 2016-10-28 8:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Greg Kroah-Hartman
Cc: Sudeep Holla, x86-DgEjT+Ai2ygdnm+yROfE0A,
devicetree-u79uwXL29TY76Z2rM5mHXA
Hi Greg,
Since the couple of fixes here are not too severe, I am considering as
updates only.
Now the x86 allow CONFIG_OF to be enabled and ACPI on arm64, we have
couple of minor bugs in those configurations. The first 2 patches fixes
them. The 3rd patch is cosmetic update to help identify the logs easily.
The last patch adds the basic support for overriding cache properties
using the device tree.
Regards,
Sudeep
Sudeep Holla (4):
drivers: base: cacheinfo: fix x86 with CONFIG_OF enabled
drivers: base: cacheinfo: fix boot error message when acpi is enabled
drivers: base: cacheinfo: add pr_fmt logging
drivers: base: cacheinfo: support DT overrides for cache properties
arch/x86/kernel/cpu/intel_cacheinfo.c | 2 +
drivers/base/cacheinfo.c | 138 +++++++++++++++++++++++++++++++++-
include/linux/cacheinfo.h | 1 +
3 files changed, 137 insertions(+), 4 deletions(-)
--
2.7.4
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^ permalink raw reply
* Re: [PATCH v8 4/8] usb: core: add power sequence handling for USB devices
From: hvaibhav.linux @ 2016-10-28 8:41 UTC (permalink / raw)
To: Peter Chen, gregkh, stern, ulf.hansson, broonie, sre, robh+dt,
shawnguo, dbaryshkov
Cc: heiko, linux-arm-kernel, p.zabel, devicetree, pawel.moll,
mark.rutland, linux-usb, arnd, s.hauer, mail, troy.kisky,
festevam, oscar, stephen.boyd, linux-pm, stillcompiling,
linux-kernel, mka
In-Reply-To: <1476413995-20361-5-git-send-email-peter.chen@nxp.com>
[-- Attachment #1: Type: text/plain, Size: 3792 bytes --]
On Friday 14 October 2016 08:29 AM, Peter Chen wrote:
> Some hard-wired USB devices need to do power sequence to let the
> device work normally, the typical power sequence like: enable USB
> PHY clock, toggle reset pin, etc. But current Linux USB driver
> lacks of such code to do it, it may cause some hard-wired USB devices
> works abnormal or can't be recognized by controller at all.
>
> In this patch, it calls power sequence library APIs to finish
> the power sequence events. It will do power on sequence at hub's
> probe for all devices under this hub (includes root hub).
> At hub_disconnect, it will do power off sequence which is at powered
> on list.
>
> Signed-off-by: Peter Chen <peter.chen@nxp.com>
> Tested-by Joshua Clayton <stillcompiling@gmail.com>
> ---
> drivers/usb/core/hub.c | 41 ++++++++++++++++++++++++++++++++++++++---
> drivers/usb/core/hub.h | 1 +
> 2 files changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
> index cbb1467..acbbf0a 100644
> --- a/drivers/usb/core/hub.c
> +++ b/drivers/usb/core/hub.c
> @@ -26,6 +26,7 @@
> #include <linux/mutex.h>
> #include <linux/random.h>
> #include <linux/pm_qos.h>
> +#include <linux/power/pwrseq.h>
>
> #include <asm/uaccess.h>
> #include <asm/byteorder.h>
> @@ -1695,6 +1696,7 @@ static void hub_disconnect(struct usb_interface *intf)
> hub->error = 0;
> hub_quiesce(hub, HUB_DISCONNECT);
>
> + of_pwrseq_off_list(&hub->pwrseq_on_list);
> mutex_lock(&usb_port_peer_mutex);
>
> /* Avoid races with recursively_mark_NOTATTACHED() */
> @@ -1722,12 +1724,41 @@ static void hub_disconnect(struct usb_interface *intf)
> kref_put(&hub->kref, hub_release);
> }
>
> +#ifdef CONFIG_OF
> +static int hub_of_pwrseq_on(struct usb_hub *hub)
> +{
> + struct device *parent;
> + struct usb_device *hdev = hub->hdev;
> + struct device_node *np;
> + int ret;
> +
> + if (hdev->parent)
> + parent = &hdev->dev;
> + else
> + parent = bus_to_hcd(hdev->bus)->self.controller;
> +
> + for_each_child_of_node(parent->of_node, np) {
> + ret = of_pwrseq_on_list(np, &hub->pwrseq_on_list);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +#else
> +static int hub_of_pwrseq_on(struct usb_hub *hub)
> +{
> + return 0;
> +}
> +#endif
> +
> static int hub_probe(struct usb_interface *intf, const struct usb_device_id *id)
> {
> struct usb_host_interface *desc;
> struct usb_endpoint_descriptor *endpoint;
> struct usb_device *hdev;
> struct usb_hub *hub;
> + int ret = -ENODEV;
>
> desc = intf->cur_altsetting;
> hdev = interface_to_usbdev(intf);
> @@ -1832,6 +1863,7 @@ descriptor_error:
> INIT_DELAYED_WORK(&hub->leds, led_work);
> INIT_DELAYED_WORK(&hub->init_work, NULL);
> INIT_WORK(&hub->events, hub_event);
> + INIT_LIST_HEAD(&hub->pwrseq_on_list);
> usb_get_intf(intf);
> usb_get_dev(hdev);
>
> @@ -1845,11 +1877,14 @@ descriptor_error:
> if (id->driver_info & HUB_QUIRK_CHECK_PORT_AUTOSUSPEND)
> hub->quirk_check_port_auto_suspend = 1;
>
> - if (hub_configure(hub, endpoint) >= 0)
> - return 0;
> + if (hub_configure(hub, endpoint) >= 0) {
> + ret = hub_of_pwrseq_on(hub);
> + if (!ret)
> + return 0;
> + }
>
> hub_disconnect(intf);
> - return -ENODEV;
> + return ret;
> }
>
> static int
> diff --git a/drivers/usb/core/hub.h b/drivers/usb/core/hub.h
> index 34c1a7e..cd86f91 100644
> --- a/drivers/usb/core/hub.h
> +++ b/drivers/usb/core/hub.h
> @@ -78,6 +78,7 @@ struct usb_hub {
> struct delayed_work init_work;
> struct work_struct events;
> struct usb_port **ports;
> + struct list_head pwrseq_on_list; /* powered pwrseq node list */
> };
>
> /**
Reviewed-by: Vaibhav Hiremath <hvaibhav.linux@gmail.com>
Thanks,
Vaibhav
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^ permalink raw reply
* Re: [PATCH v6 4/5] ARM: DTS: da850: Add cfgchip syscon node
From: Sekhar Nori @ 2016-10-28 8:21 UTC (permalink / raw)
To: David Lechner, Kevin Hilman, Rob Herring, Mark Rutland
Cc: Axel Haslam, Sergei Shtylyov, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <b9bfc4aa-ef52-53c4-dc7e-c0bc1c5969fb@lechnology.com>
On Wednesday 26 October 2016 09:38 PM, David Lechner wrote:
> On 10/25/2016 10:06 PM, David Lechner wrote:
>> Add a syscon node for the SoC CFGCHIPn registers. This is needed for
>> the new usb phy driver.
>>
>> Signed-off-by: David Lechner <david@lechnology.com>
>> ---
>> arch/arm/boot/dts/da850.dtsi | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>> index f79e1b9..6bbf20d 100644
>> --- a/arch/arm/boot/dts/da850.dtsi
>> +++ b/arch/arm/boot/dts/da850.dtsi
>> @@ -188,6 +188,10 @@
>> };
>>
>> };
>> + cfgchip: cfgchip@1417c {
>
> I wonder if there is a more generic name instead of cfgchip@. Is there a
> preferred generic name for syscon nodes?
I did not find anything in ePAPR, but chip-controller might be more
appropriate.
>
>> + compatible = "ti,da830-cfgchip", "syscon";
Looks like we need "simple-mfd" too in the compatible list?
I think we can also fold patch 5/5 into this patch and add the cfgchip
along with USB phy child node included.
If you respin the patch, I can drop 4/5 and 5/5 that I have queued and
included the updated patch instead.
Thanks,
Sekhar
^ permalink raw reply
* Re: [RFC 1/2] mmc: sdhci: dt: Add device tree properties sdhci-caps and sdhci-caps-mask
From: Ulf Hansson @ 2016-10-28 8:12 UTC (permalink / raw)
To: Zach Brown
Cc: Adrian Hunter, Rob Herring, Mark Rutland, linux-mmc,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1477425538-3315-2-git-send-email-zach.brown-acOepvfBmUk@public.gmane.org>
On 25 October 2016 at 21:58, Zach Brown <zach.brown-acOepvfBmUk@public.gmane.org> wrote:
> On some systems the sdhci capabilty registers are incorrect for one
> reason or another.
>
> The sdhci-caps-mask property specifies which bits in the registers
> are incorrect and should be turned off before using sdhci-caps to turn
> on bits.
>
> The sdhci-caps property specifies which bits should be turned on.
>
> Signed-off-by: Zach Brown <zach.brown-acOepvfBmUk@public.gmane.org>
> ---
> Documentation/devicetree/bindings/mmc/mmc.txt | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mmc.txt b/Documentation/devicetree/bindings/mmc/mmc.txt
> index 8a37782..1415aa0 100644
> --- a/Documentation/devicetree/bindings/mmc/mmc.txt
> +++ b/Documentation/devicetree/bindings/mmc/mmc.txt
The bindings in this document are common mmc DT bindings, not bindings
specific to a mmc controller.
So unless these bindings are applicable for another controller than
sdhci, I suggest we create a new file to document these.
How about Documentation/devicetree/bindings/mmc/sdhci.txt?
> @@ -52,6 +52,13 @@ Optional properties:
> - no-sdio: controller is limited to send sdio cmd during initialization
> - no-sd: controller is limited to send sd cmd during initialization
> - no-mmc: controller is limited to send mmc cmd during initialization
> +- sdhci-caps-mask: The sdhci capabilities registers are incorrect. This 64bit
/s/registers/register
This applies to some more places below as well.
> + property corresponds to the bits in the sdhci capabilty registers. If the bit
> + is on in the mask then the bit is incorrect in the registers and should be
> + turned off.
> +- sdhci-caps: The sdhci capabilities registers are incorrect. This 64bit
> + property corresponds to the bits in the sdhci capability registers. If the
> + bit is on in the property then the bit should be on in the reigsters.
/s/reigsters/register
>
> *NOTE* on CD and WP polarity. To use common for all SD/MMC host controllers line
> polarity properties, we have to fix the meaning of the "normal" and "inverted"
> --
> 2.7.4
>
Overall, I like this idea as it gives us good flexibility. Thus it
should avoid us to having to add any further new similar "sdhci broken
cap" DT binding. We could also decide to start deprecate some of the
existing sdhci bindings, if we think that makes sense.
The downside is that we get a "magic" hex value in the dts. Although,
people could address this issue by providing some comments about what
the bits it means in the dts files themselves.
Let's see what Rob thinks about this.
Kind regards
Uffe
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^ permalink raw reply
* Re: [PATCHv4 11/15] clk: ti: clockdomain: add clock provider support to clockdomains
From: Tero Kristo @ 2016-10-28 7:41 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-omap, linux-clk, tony, mturquette, linux-arm-kernel,
devicetree, Rob Herring
In-Reply-To: <20161028005047.GQ26139@codeaurora.org>
On 28/10/16 03:50, Stephen Boyd wrote:
> On 10/18, Tero Kristo wrote:
>> Clockdomains can now be used as clock providers in the system. This
>> patch initializes the provider data during init, and parses the clocks
>> while they are being registered. An xlate function for the provider
>> is also given.
>>
>> Signed-off-by: Tero Kristo <t-kristo@ti.com>
>
> Please Cc dt reviewers on binding updates.
Sorry about missing that...
> I suppose a PRCM is
> like an MFD that has clocks and resets under it? On other
> platforms we've combined that all into one node and just had
> #clock-cells and #reset-cells in that node. Is there any reason
> we can't do that here?
For OMAPs, there are typically multiple instances of the PRCM around;
OMAP4 for example has:
cm1 @ 0x4a004000 (clocks + clockdomains)
cm2 @ 0x4a008000 (clocks + clockdomains)
prm @ 0x4a306000 (few clocks + resets + power state handling)
scrm @ 0x4a30a000 (few external clocks + plenty of misc stuff)
These instances are also under different power/voltage domains which
means their PM behavior is different.
The idea behind having a clockdomain as a provider was mostly to have
the topology visible : prcm-instance -> clockdomain -> clocks
... but basically I think it would be possible to drop the clockdomain
representation and just mark the prcm-instance as a clock provider.
Tony, any thoughts on that?
>
>> ---
>> .../devicetree/bindings/arm/omap/prcm.txt | 13 ++
>> .../devicetree/bindings/clock/ti/clockdomain.txt | 12 +-
>> arch/arm/mach-omap2/io.c | 2 +
>> drivers/clk/ti/clock.h | 1 +
>> drivers/clk/ti/clockdomain.c | 147 +++++++++++++++++++++
>> include/linux/clk/ti.h | 3 +
>> 6 files changed, 177 insertions(+), 1 deletion(-)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/omap/prcm.txt b/Documentation/devicetree/bindings/arm/omap/prcm.txt
>> index 3eb6d7a..301f576 100644
>> --- a/Documentation/devicetree/bindings/arm/omap/prcm.txt
>> +++ b/Documentation/devicetree/bindings/arm/omap/prcm.txt
>> @@ -47,6 +47,19 @@ cm: cm@48004000 {
>> };
>> }
>>
>> +cm2: cm2@8000 {
>> + compatible = "ti,omap4-cm2";
>> + reg = <0x8000 0x3000>;
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + ranges = <0 0x8000 0x3000>;
>> +
>> + l4_per_clkdm: l4_per_clkdm {
>> + compatible = "ti,clockdomain";
>> + reg = <0x1400 0x200>;
>
> Should there be #clock-cells = <1> here? Also node name should
> have an @1400 after it?
Yeah both should be there. I had the #clock-cells in my test data in
place already but the address portion I seem to have completely forgot.
>
>> + };
>> +};
>> +
>> &cm_clocks {
>> omap2_32k_fck: omap_32k_fck {
>> #clock-cells = <0>;
>> diff --git a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
>> index cb76b3f..5d8ca61 100644
>> --- a/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
>> +++ b/Documentation/devicetree/bindings/clock/ti/clockdomain.txt
>> @@ -14,11 +14,21 @@ hardware hierarchy.
>>
>> Required properties:
>> - compatible : shall be "ti,clockdomain"
>> -- #clock-cells : from common clock binding; shall be set to 0.
>> +- #clock-cells : from common clock binding; shall be set to 1 if this
>> + clockdomain acts as a clock provider.
>> +
>> +Optional properties:
>> - clocks : link phandles of clocks within this domain
>> +- reg : address for the clockdomain
>>
>> Examples:
>> dss_clkdm: dss_clkdm {
>> compatible = "ti,clockdomain";
>> clocks = <&dss1_alwon_fck_3430es2>, <&dss_ick_3430es2>;
>> };
>> +
>> + l4_per_clkdm: l4_per_clkdm {
>
> add an @1400?
Yea will do, unless we decide to go for prcm-instance provider approach.
>
>> + compatible = "ti,clockdomain";
>> + #clock-cells = <1>;
>> + reg = <0x1400 0x200>;
>> + };
>> diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
>> index 0e9acdd..c1a5cfb 100644
>> --- a/arch/arm/mach-omap2/io.c
>> +++ b/arch/arm/mach-omap2/io.c
>> @@ -794,6 +794,8 @@ int __init omap_clk_init(void)
>> if (ret)
>> return ret;
>>
>> + ti_dt_clockdomains_early_setup();
>> +
>> of_clk_init(NULL);
>>
>> ti_dt_clk_init_retry_clks();
>> diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h
>> index 9b8a5f2..f6383ab 100644
>> --- a/drivers/clk/ti/clock.h
>> +++ b/drivers/clk/ti/clock.h
>> @@ -205,6 +205,7 @@ struct clk *ti_clk_register(struct device *dev, struct clk_hw *hw,
>>
>> int ti_clk_get_memmap_index(struct device_node *node);
>> void __iomem *ti_clk_get_reg_addr(struct device_node *node, int index);
>> +void __iomem *ti_clk_get_reg_addr_clkdm(const char *clkdm_name, u16 offset);
>> void ti_dt_clocks_register(struct ti_dt_clk *oclks);
>> int ti_clk_retry_init(struct device_node *node, struct clk_hw *hw,
>> ti_of_clk_init_cb_t func);
>> diff --git a/drivers/clk/ti/clockdomain.c b/drivers/clk/ti/clockdomain.c
>> index 704157d..7b0a6c3 100644
>> --- a/drivers/clk/ti/clockdomain.c
>> +++ b/drivers/clk/ti/clockdomain.c
>> @@ -28,6 +28,23 @@
>> #define pr_fmt(fmt) "%s: " fmt, __func__
>>
>> /**
>> + * struct ti_clkdm - TI clockdomain data structure
>> + * @name: name of the clockdomain
>> + * @index: index of the clk_iomap struct for this clkdm
>> + * @offset: clockdomain offset from the beginning of the iomap
>> + * @link: link to the list
>> + */
>> +struct ti_clkdm {
>> + const char *name;
>> + int index;
>> + u32 offset;
>> + struct list_head link;
>> + struct list_head clocks;
>> +};
>> +
>> +static LIST_HEAD(clkdms);
>> +
>> +/**
>> * omap2_clkops_enable_clkdm - increment usecount on clkdm of @hw
>> * @hw: struct clk_hw * of the clock being enabled
>> *
>> @@ -116,6 +133,8 @@ void omap2_init_clk_clkdm(struct clk_hw *hw)
>> struct clk_hw_omap *clk = to_clk_hw_omap(hw);
>> struct clockdomain *clkdm;
>> const char *clk_name;
>> + struct ti_clkdm *ti_clkdm;
>> + bool match = false;
>>
>> if (!clk->clkdm_name)
>> return;
>> @@ -130,7 +149,21 @@ void omap2_init_clk_clkdm(struct clk_hw *hw)
>> } else {
>> pr_debug("clock: could not associate clk %s to clkdm %s\n",
>> clk_name, clk->clkdm_name);
>> + return;
>> }
>> +
>> + list_for_each_entry(ti_clkdm, &clkdms, link) {
>> + if (!strcmp(ti_clkdm->name, clk->clkdm_name)) {
>> + match = true;
>> + break;
>
> Or just goto found and then drop the match bool thing.
That will be cleaner yes. Will change.
>
>> + }
>> + }
>> +
>> + if (!match)
>> + return;
>> +
>> + /* Add clock to the list of provided clocks */
>> + list_add(&clk->clkdm_link, &ti_clkdm->clocks);
>> }
>>
>> static void __init of_ti_clockdomain_setup(struct device_node *node)
>> @@ -161,11 +194,125 @@ static void __init of_ti_clockdomain_setup(struct device_node *node)
>> }
>> }
>>
>> +static struct clk_hw *clkdm_clk_xlate(struct of_phandle_args *clkspec,
>> + void *data)
>> +{
>> + struct ti_clkdm *clkdm = data;
>> + struct clk_hw_omap *clk;
>> + u16 offset = clkspec->args[0];
>> +
>> + list_for_each_entry(clk, &clkdm->clocks, clkdm_link)
>> + if (((u32)clk->enable_reg & 0xffff) - clkdm->offset == offset)
>
> This looks scary.
I think I need to add a separate cleanup patch for the address handling
before this series... There are a few nasty looking address casts around
at the moment under the TI clock driver.
>
>> + return &clk->hw;
>> +
>> + return ERR_PTR(-EINVAL);
>> +}
>> +
>> +static int ti_clk_register_clkdm(struct device_node *node)
>> +{
>> + u64 clkdm_addr;
>> + u64 inst_addr;
>> + const __be32 *reg;
>> + u32 offset;
>> + int idx;
>> + struct ti_clkdm *clkdm;
>> + int ret;
>> +
>> + reg = of_get_address(node, 0, NULL, NULL);
>> + if (!reg)
>> + return -ENOENT;
>> +
>> + clkdm_addr = of_translate_address(node, reg);
>> +
>> + reg = of_get_address(node->parent, 0, NULL, NULL);
>> + if (!reg)
>> + return -EINVAL;
>> +
>> + inst_addr = of_translate_address(node->parent, reg);
>> +
>> + offset = clkdm_addr - inst_addr;
>> +
>
> I guess the usual offset tricks are still going on in the TI clk
> driver? Is there a plan to stop doing that at some point?
I can have a look at that with the addressing cleanup I mentioned above.
I'll see if I can reduce the amount of trickery involved.
>
>> + idx = ti_clk_get_memmap_index(node->parent);
>> +
>> + if (idx < 0) {
>> + pr_err("bad memmap index for %s\n", node->name);
>> + return idx;
>> + }
>> +
>> + clkdm = kzalloc(sizeof(*clkdm), GFP_KERNEL);
>> + if (!clkdm)
>> + return -ENOMEM;
>> +
>> + clkdm->name = node->name;
>> + clkdm->index = idx;
>> + clkdm->offset = offset;
>> +
>> + INIT_LIST_HEAD(&clkdm->clocks);
>> +
>> + list_add(&clkdm->link, &clkdms);
>> +
>> + ret = of_clk_add_hw_provider(node, clkdm_clk_xlate, clkdm);
>> + if (ret) {
>> + list_del(&clkdm->link);
>> + kfree(clkdm);
>> + return ret;
>> + }
>> +
>> + return 0;
>> +}
>> +
>> +/**
>> + * ti_clk_get_reg_addr_clkdm - get register address relative to clockdomain
>> + * @clkdm_name: parent clockdomain
>> + * @offset: offset from the clockdomain
>> + *
>> + * Gets a register address relative to parent clockdomain. Searches the
>> + * list of available clockdomain, and if match is found, calculates the
>> + * register address from the iomap relative to the clockdomain.
>> + * Returns the register address, or NULL if not found.
>> + */
>> +void __iomem *ti_clk_get_reg_addr_clkdm(const char *clkdm_name, u16 offset)
>> +{
>> + u32 reg;
>> + struct clk_omap_reg *reg_setup;
>> + struct ti_clkdm *clkdm;
>> + bool match = false;
>> +
>> + reg_setup = (struct clk_omap_reg *)®
>> +
>> + /* XXX: get offset from clkdm, get base for instance */
>> + list_for_each_entry(clkdm, &clkdms, link) {
>> + if (!strcmp(clkdm->name, clkdm_name)) {
>> + match = true;
>> + break;
>> + }
>> + }
>> +
>> + if (!match) {
>> + pr_err("%s: no entry for %s\n", __func__, clkdm_name);
>> + return NULL;
>> + }
>> +
>> + reg_setup->offset = clkdm->offset + offset;
>> + reg_setup->index = clkdm->index;
>> +
>> + return (void __iomem *)reg;
>> +}
>> +
>> static const struct of_device_id ti_clkdm_match_table[] __initconst = {
>> { .compatible = "ti,clockdomain" },
>> { }
>> };
>>
>> +void __init ti_dt_clockdomains_early_setup(void)
>> +{
>> + struct device_node *np;
>> +
>> + for_each_matching_node(np, ti_clkdm_match_table) {
>> + ti_clk_register_clkdm(np);
>> + }
>
> Nitpick: drop braces please.
True, will do that.
-Tero
>
>> +}
>> +
>> /**
>> * ti_dt_clockdomains_setup - setup device tree clockdomains
>> *
>> diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
>> index 626ae94..afccb48 100644
>> --- a/include/linux/clk/ti.h
>> +++ b/include/linux/clk/ti.h
>> @@ -125,6 +125,7 @@ struct clk_hw_omap_ops {
>> /**
>> * struct clk_hw_omap - OMAP struct clk
>> * @node: list_head connecting this clock into the full clock list
>> + * @clkdm_link: list_head connecting this clock into the clockdomain
>> * @enable_reg: register to write to enable the clock (see @enable_bit)
>> * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
>> * @flags: see "struct clk.flags possibilities" above
>> @@ -137,6 +138,7 @@ struct clk_hw_omap_ops {
>> struct clk_hw_omap {
>> struct clk_hw hw;
>> struct list_head node;
>> + struct list_head clkdm_link;
>> unsigned long fixed_rate;
>> u8 fixed_div;
>> void __iomem *enable_reg;
>> @@ -251,6 +253,7 @@ int omap2_reprogram_dpllcore(struct clk_hw *clk, unsigned long rate,
>> unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk);
>>
>> void ti_dt_clk_init_retry_clks(void);
>> +void ti_dt_clockdomains_early_setup(void);
>> void ti_dt_clockdomains_setup(void);
>> int ti_clk_setup_ll_ops(struct ti_clk_ll_ops *ops);
>>
>> --
>> 1.9.1
>>
>
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: hi6220: add resets property into dwmmc nodes
From: Leo Yan @ 2016-10-28 7:38 UTC (permalink / raw)
To: Jaehoon Chung
Cc: Vincent Guittot, John Stultz, Guodong Xu, Wei Xu, Rob Herring,
Rob Herring, Mark Rutland, Catalin Marinas, Will Deacon,
devicetree@vger.kernel.org, Xinliang Liu, linux-kernel,
Fathi Boudra, LAK
In-Reply-To: <d7993c1a-5e50-9a33-0900-5c1a79884d3c@samsung.com>
On Fri, Oct 28, 2016 at 04:33:41PM +0900, Jaehoon Chung wrote:
[...]
> >>> Guodong: Is there any bootloader dependency on that change?
> >>
> >> FYI, I use firmwares available in AOSP
> >
> > I tried latest firmware [1], still cannot boot up until revert the
> > patch "arm64: dts: hi6220: add resets property into dwmmc nodes".
>
> Could you share the log? Is there any log about failure?
Sure, please see below log:
EFI stub: Booting Linux Kernel...
EFI stub: Using DTB from configuration table
EFI stub: Exiting boot services and installing virtual address map...
[ 0.000000] Booting Linux on physical CPU 0x0
[ 0.000000] Linux version 4.9.0-rc1-00251-g323792f (leoy@leoy-linaro) (gcc version 4.9.2 20140904 (prerelease) (crosstool-NG linaro-1.13.1-4.9-2014.09 - Linaro GCC 4.9-2014.09) ) #589 SMP PREEMPT Fri Oct 28 15:35:15 CST 2016
[ 0.000000] Boot CPU: AArch64 Processor [410fd033]
[ 0.000000] efi: Getting EFI parameters from FDT:
[ 0.000000] efi: EFI v2.50 by hikey EFI Oct 26 2016 15:14:29
[ 0.000000] efi: PROP=0x3d8297d8
[ 0.000000] Reserved memory: created CMA memory pool at 0x000000002d000000, size 128 MiB
[ 0.000000] OF: reserved mem: initialized node linux,cma, compatible id shared-dma-pool
[ 0.000000] psci: probing for conduit method from DT.
[ 0.000000] psci: PSCIv1.0 detected in firmware.
[ 0.000000] psci: Using standard PSCI v0.2 function IDs
[ 0.000000] psci: MIGRATE_INFO_TYPE not supported.
[ 0.000000] percpu: Embedded 21 pages/cpu @ffff80003df10000 s48000 r8192 d29824 u86016
[ 0.000000] Detected VIPT I-cache on CPU0
[ 0.000000] CPU features: enabling workaround for ARM erratum 845719
[ 0.000000] Built 1 zonelists in Zone order, mobility grouping on. Total pages: 249229
[ 0.000000] Kernel command line: BOOT_IMAGE=(hd0,gpt6)/Image console=tty0 console=ttyAMA3,115200 root=/dev/disk/by-partlabel/system rootwait rw efi=noruntime
[ 0.000000] log_buf_len individual max cpu contribution: 4096 bytes
[ 0.000000] log_buf_len total cpu_extra contributions: 28672 bytes
[ 0.000000] log_buf_len min size: 16384 bytes
[ 0.000000] log_buf_len: 65536 bytes
[ 0.000000] early log buf free: 14468(88%)
[ 0.000000] PID hash table entries: 4096 (order: 3, 32768 bytes)
[ 0.000000] Dentry cache hash table entries: 131072 (order: 8, 1048576 bytes)
[ 0.000000] Inode-cache hash table entries: 65536 (order: 7, 524288 bytes)
[ 0.000000] Memory: 841572K/1012788K available (8316K kernel code, 860K rwdata, 3668K rodata, 1024K init, 283K bss, 40144K reserved, 131072K cma-reserved)
[ 0.000000] Virtual kernel memory layout:
[ 0.000000] modules : 0xffff000000000000 - 0xffff000008000000 ( 128 MB)
[ 0.000000] vmalloc : 0xffff000008000000 - 0xffff7dffbfff0000 (129022 GB)
[ 0.000000] .text : 0xffff000008080000 - 0xffff0000088a0000 ( 8320 KB)
[ 0.000000] .rodata : 0xffff0000088a0000 - 0xffff000008c40000 ( 3712 KB)
[ 0.000000] .init : 0xffff000008c40000 - 0xffff000008d40000 ( 1024 KB)
[ 0.000000] .data : 0xffff000008d40000 - 0xffff000008e17200 ( 861 KB)
[ 0.000000] .bss : 0xffff000008e17200 - 0xffff000008e5e0c0 ( 284 KB)
[ 0.000000] fixed : 0xffff7dfffe7fd000 - 0xffff7dfffec00000 ( 4108 KB)
[ 0.000000] PCI I/O : 0xffff7dfffee00000 - 0xffff7dffffe00000 ( 16 MB)
[ 0.000000] vmemmap : 0xffff7e0000000000 - 0xffff800000000000 ( 2048 GB maximum)
[ 0.000000] 0xffff7e0000000000 - 0xffff7e0000f80000 ( 15 MB actual)
[ 0.000000] memory : 0xffff800000000000 - 0xffff80003e000000 ( 992 MB)
[ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=8, Nodes=1
[ 0.000000] Preemptible hierarchical RCU implementation.
[ 0.000000] Build-time adjustment of leaf fanout to 64.
[ 0.000000] RCU restricting CPUs from NR_CPUS=64 to nr_cpu_ids=8.
[ 0.000000] RCU: Adjusting geometry for rcu_fanout_leaf=64, nr_cpu_ids=8
[ 0.000000] NR_IRQS:64 nr_irqs:64 0
[ 0.000000] GIC: Using split EOI/Deactivate mode
[ 0.000000] arm_arch_timer: Architected cp15 timer(s) running at 1.20MHz (phys).
[ 0.000000] clocksource: arch_sys_counter: mask: 0xffffffffffffff max_cycles: 0x11b661f8e, max_idle_ns: 1763180809113 ns
[ 0.000004] sched_clock: 56 bits at 1200kHz, resolution 833ns, wraps every 4398046510838ns
[ 0.000101] clocksource: arm,sp804: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 99544814920 ns
[ 0.000108] sched_clock: 32 bits at 19MHz, resolution 52ns, wraps every 111848106981ns
[ 0.000495] Console: colour dummy device 80x25
[ 0.001193] console [tty0] enabled
[ 0.001224] Calibrating delay loop (skipped), value calculated using timer frequency.. 2.40 BogoMIPS (lpj=4800)
[ 0.001253] pid_max: default: 32768 minimum: 301
[ 0.001331] Security Framework initialized
[ 0.001373] Mount-cache hash table entries: 2048 (order: 2, 16384 bytes)
[ 0.001392] Mountpoint-cache hash table entries: 2048 (order: 2, 16384 bytes)
[ 0.002258] ASID allocator initialised with 65536 entries
[ 0.032726] EFI runtime services will be disabled.
[ 0.080274] Detected VIPT I-cache on CPU1
[ 0.080323] CPU1: Booted secondary processor [410fd033]
[ 0.112299] Detected VIPT I-cache on CPU2
[ 0.112321] CPU2: Booted secondary processor [410fd033]
[ 0.144348] Detected VIPT I-cache on CPU3
[ 0.144369] CPU3: Booted secondary processor [410fd033]
[ 0.176488] Detected VIPT I-cache on CPU4
[ 0.176529] CPU4: Booted secondary processor [410fd033]
[ 0.208479] Detected VIPT I-cache on CPU5
[ 0.208501] CPU5: Booted secondary processor [410fd033]
[ 0.240546] Detected VIPT I-cache on CPU6
[ 0.240568] CPU6: Booted secondary processor [410fd033]
[ 0.272610] Detected VIPT I-cache on CPU7
[ 0.272632] CPU7: Booted secondary processor [410fd033]
[ 0.272708] Brought up 8 CPUs
[ 0.272887] SMP: Total of 8 processors activated.
[ 0.272904] CPU features: detected feature: 32-bit EL0 Support
[ 0.272975] CPU: All CPU(s) started at EL2
[ 0.273028] alternatives: patching kernel code
[ 0.273645] devtmpfs: initialized
[ 0.278919] DMI not present or invalid.
[ 0.279161] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
[ 0.282522] pinctrl core: initialized pinctrl subsystem
[ 0.283636] NET: Registered protocol family 16
[ 0.300541] cpuidle: using governor menu
[ 0.301073] vdso: 2 pages (1 code @ ffff0000088a7000, 1 data @ ffff000008d44000)
[ 0.301106] hw-breakpoint: found 6 breakpoint and 4 watchpoint registers.
[ 0.301863] DMA: preallocated 256 KiB pool for atomic allocations
[ 0.302088] Serial: AMBA PL011 UART driver
[ 0.303683] f8015000.uart: ttyAMA0 at MMIO 0xf8015000 (irq = 7, base_baud = 0) is a PL011 rev2
[ 0.304121] uart-pl011 f7111000.uart: could not find pctldev for node /soc/pinmux@f7010000/uart1_pmx_func, deferring probe
[ 0.304340] uart-pl011 f7112000.uart: could not find pctldev for node /soc/pinmux@f7010000/uart2_pmx_func, deferring probe
[ 0.304580] uart-pl011 f7113000.uart: could not find pctldev for node /soc/pinmux@f7010000/uart3_pmx_func, deferring probe
[ 0.310373] hi6220-mbox f7510000.mailbox: Mailbox enabled
[ 0.341400] HugeTLB registered 2 MB page size, pre-allocated 0 pages
[ 0.342257] ACPI: Interpreter disabled.
[ 0.342953] vgaarb: loaded
[ 0.343177] SCSI subsystem initialized
[ 0.343450] ssp-pl022 f7106000.spi: could not find pctldev for node /soc/pinmux@f7010000/spi0_pmx_func, deferring probe
[ 0.343955] usbcore: registered new interface driver usbfs
[ 0.344042] usbcore: registered new interface driver hub
[ 0.344177] usbcore: registered new device driver usb
[ 0.344452] i2c_designware f7100000.i2c: could not find pctldev for node /soc/pinmux@f7010000/i2c0_pmx_func, deferring probe
[ 0.344494] i2c_designware f7101000.i2c: could not find pctldev for node /soc/pinmux@f7010000/i2c1_pmx_func, deferring probe
[ 0.344535] i2c_designware f7102000.i2c: could not find pctldev for node /soc/pinmux@f7010000/i2c2_pmx_func, deferring probe
[ 0.344915] pps_core: LinuxPPS API ver. 1 registered
[ 0.344931] pps_core: Software ver. 5.3.6 - Copyright 2005-2007 Rodolfo Giometti <giometti@linux.it>
[ 0.345003] PTP clock support registered
[ 0.345325] dmi: Firmware registration failed.
[ 0.345408] Registered efivars operations
[ 0.345580] Advanced Linux Sound Architecture Driver Initialized.
[ 0.346449] clocksource: Switched to clocksource arch_sys_counter
[ 0.346617] VFS: Disk quotas dquot_6.6.0
[ 0.346670] VFS: Dquot-cache hash table entries: 512 (order 0, 4096 bytes)
[ 0.346935] pnp: PnP ACPI: disabled
[ 0.355325] NET: Registered protocol family 2
[ 0.355797] TCP established hash table entries: 8192 (order: 4, 65536 bytes)
[ 0.355885] TCP bind hash table entries: 8192 (order: 5, 131072 bytes)
[ 0.356026] TCP: Hash tables configured (established 8192 bind 8192)
[ 0.356085] UDP hash table entries: 512 (order: 2, 16384 bytes)
[ 0.356120] UDP-Lite hash table entries: 512 (order: 2, 16384 bytes)
[ 0.356255] NET: Registered protocol family 1
[ 0.356569] RPC: Registered named UNIX socket transport module.
[ 0.356585] RPC: Registered udp transport module.
[ 0.356599] RPC: Registered tcp transport module.
[ 0.356613] RPC: Registered tcp NFSv4.1 backchannel transport module.
[ 0.356791] Unpacking initramfs...
[ 0.497134] Freeing initrd memory: 3576K (ffff8000372d5000 - ffff800037653000)
[ 0.497725] kvm [1]: 8-bit VMID
[ 0.497744] kvm [1]: IDMAP page: 890000
[ 0.497758] kvm [1]: HYP VA range: 800000000000:ffffffffffff
[ 0.498691] kvm [1]: Hyp mode initialized successfully
[ 0.498741] kvm [1]: vgic-v2@f6804000
[ 0.498936] kvm [1]: vgic interrupt IRQ1
[ 0.498978] kvm [1]: virtual timer IRQ4
[ 0.501267] futex hash table entries: 2048 (order: 6, 262144 bytes)
[ 0.501394] audit: initializing netlink subsys (disabled)
[ 0.501462] audit: type=2000 audit(0.495:1): initialized
[ 0.501845] workingset: timestamp_bits=46 max_order=18 bucket_order=0
[ 0.508960] squashfs: version 4.0 (2009/01/31) Phillip Lougher
[ 0.509596] NFS: Registering the id_resolver key type
[ 0.509632] Key type id_resolver registered
[ 0.509645] Key type id_legacy registered
[ 0.509665] nfs4filelayout_init: NFSv4 File Layout Driver Registering...
[ 0.509833] 9p: Installing v9fs 9p2000 file system support
[ 0.512208] Block layer SCSI generic (bsg) driver version 0.4 loaded (major 247)
[ 0.512235] io scheduler noop registered
[ 0.512349] io scheduler cfq registered (default)
[ 0.513271] libphy: mdio_driver_register: phy-bcm-ns2-pci
[ 0.514198] pinctrl-single f7010000.pinmux: 159 pins at pa ffff000008e81000 size 636
[ 0.514612] pinctrl-single f7010800.pinmux: 163 pins at pa ffff000008e83800 size 652
[ 0.514770] pinctrl-single f8001800.pinmux: 30 pins at pa ffff000008e85800 size 120
[ 0.515809] pl061_gpio f8011000.gpio: PL061 GPIO chip @0x00000000f8011000 registered
[ 0.516214] pl061_gpio f8012000.gpio: PL061 GPIO chip @0x00000000f8012000 registered
[ 0.516610] pl061_gpio f8013000.gpio: PL061 GPIO chip @0x00000000f8013000 registered
[ 0.516687] gpio gpiochip3: gpio-line-names specifies 9 line names but there are 8 lines on the chip
[ 0.517038] pl061_gpio f8014000.gpio: PL061 GPIO chip @0x00000000f8014000 registered
[ 0.517416] pl061_gpio f7020000.gpio: PL061 GPIO chip @0x00000000f7020000 registered
[ 0.517796] pl061_gpio f7021000.gpio: PL061 GPIO chip @0x00000000f7021000 registered
[ 0.518172] pl061_gpio f7022000.gpio: PL061 GPIO chip @0x00000000f7022000 registered
[ 0.518577] pl061_gpio f7023000.gpio: PL061 GPIO chip @0x00000000f7023000 registered
[ 0.518658] gpio gpiochip8: gpio-line-names specifies 9 line names but there are 8 lines on the chip
[ 0.518999] pl061_gpio f7024000.gpio: PL061 GPIO chip @0x00000000f7024000 registered
[ 0.519385] pl061_gpio f7025000.gpio: PL061 GPIO chip @0x00000000f7025000 registered
[ 0.519774] pl061_gpio f7026000.gpio: PL061 GPIO chip @0x00000000f7026000 registered
[ 0.520162] pl061_gpio f7027000.gpio: PL061 GPIO chip @0x00000000f7027000 registered
[ 0.520550] pl061_gpio f7028000.gpio: PL061 GPIO chip @0x00000000f7028000 registered
[ 0.520939] pl061_gpio f7029000.gpio: PL061 GPIO chip @0x00000000f7029000 registered
[ 0.521324] pl061_gpio f702a000.gpio: PL061 GPIO chip @0x00000000f702a000 registered
[ 0.521719] pl061_gpio f702b000.gpio: PL061 GPIO chip @0x00000000f702b000 registered
[ 0.522107] pl061_gpio f702c000.gpio: PL061 GPIO chip @0x00000000f702c000 registered
[ 0.522505] pl061_gpio f702d000.gpio: PL061 GPIO chip @0x00000000f702d000 registered
[ 0.522884] pl061_gpio f702e000.gpio: PL061 GPIO chip @0x00000000f702e000 registered
[ 0.523275] pl061_gpio f702f000.gpio: PL061 GPIO chip @0x00000000f702f000 registered
[ 0.526086] xenfs: not registering filesystem on non-xen platform
[ 0.528934] Serial: 8250/16550 driver, 4 ports, IRQ sharing disabled
[ 0.530124] SuperH (H)SCI(F) driver initialized
[ 0.530364] msm_serial: driver initialized
[ 0.536344] loop: module loaded
[ 0.539526] hisi_sas: driver version v1.6
[ 0.541976] libphy: Fixed MDIO Bus: probed
[ 0.542702] tun: Universal TUN/TAP device driver, 1.6
[ 0.542719] tun: (C) 1999-2004 Max Krasnyansky <maxk@qualcomm.com>
[ 0.543688] e1000e: Intel(R) PRO/1000 Network Driver - 3.2.6-k
[ 0.543707] e1000e: Copyright(c) 1999 - 2015 Intel Corporation.
[ 0.543804] igb: Intel(R) Gigabit Ethernet Network Driver - version 5.4.0-k
[ 0.543821] igb: Copyright (c) 2007-2014 Intel Corporation.
[ 0.543906] igbvf: Intel(R) Gigabit Virtual Function Network Driver - version 2.4.0-k
[ 0.543930] igbvf: Copyright (c) 2009 - 2012 Intel Corporation.
[ 0.544018] sky2: driver version 1.30
[ 0.544551] VFIO - User Level meta-driver version: 0.3
[ 0.546560] ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver
[ 0.546590] ehci-pci: EHCI PCI platform driver
[ 0.546638] ehci-platform: EHCI generic platform driver
[ 0.546730] ehci-exynos: EHCI EXYNOS driver
[ 0.546802] ehci-msm: Qualcomm On-Chip EHCI Host Controller
[ 0.546866] ohci_hcd: USB 1.1 'Open' Host Controller (OHCI) Driver
[ 0.546900] ohci-pci: OHCI PCI platform driver
[ 0.546952] ohci-platform: OHCI generic platform driver
[ 0.547024] ohci-exynos: OHCI EXYNOS driver
[ 0.547324] usbcore: registered new interface driver usb-storage
[ 0.547863] file system registered
[ 0.548183] mousedev: PS/2 mouse device common for all mice
[ 0.548621] input: HISI 65xx PowerOn Key as /devices/platform/f8000000.pmic/hi65xx-powerkey.0.auto/input/input0
[ 0.549253] rtc-pl031 f8003000.rtc: rtc core: registered pl031 as rtc0
[ 0.549459] rtc-pl031 f8004000.rtc: rtc core: registered pl031 as rtc1
[ 0.549796] i2c /dev entries driver
[ 0.552183] sdhci: Secure Digital Host Controller Interface driver
[ 0.552207] sdhci: Copyright(c) Pierre Ossman
[ 0.552403] Synopsys Designware Multimedia Card Interface Driver
[ 0.553405] sdhci-pltfm: SDHCI platform and OF driver helper
[ 0.554851] ledtrig-cpu: registered to indicate activity on CPUs
[ 0.555695] usbcore: registered new interface driver usbhid
[ 0.555717] usbhid: USB HID core driver
[ 0.557233] NET: Registered protocol family 17
[ 0.557320] 9pnet: Installing 9P2000 support
[ 0.557383] Key type dns_resolver registered
[ 0.557996] registered taskstats version 1
[ 0.561690] f7111000.uart: ttyAMA1 at MMIO 0xf7111000 (irq = 8, base_baud = 0) is a PL011 rev2
[ 0.562226] f7112000.uart: ttyAMA2 at MMIO 0xf7112000 (irq = 9, base_baud = 0) is a PL011 rev2
[ 0.562553] f7113000.uart: ttyAMA3 at MMIO 0xf7113000 (irq = 10, base_baud = 0) is a PL011 rev2
[ 1.916968] console [ttyAMA3] enabled
[ 1.922080] ssp-pl022 f7106000.spi: ARM PL022 driver, device ID: 0x00041022
[ 1.929144] ssp-pl022 f7106000.spi: mapped registers from 0x00000000f7106000 to ffff000008f03000
[ 1.938007] ssp-pl022 f7106000.spi: Failed to work in dma mode, work without dma!
[ 1.949535] f72c0000.usb supply vusb_d not found, using dummy regulator
[ 1.956256] f72c0000.usb supply vusb_a not found, using dummy regulator
[ 2.344873] dwc2 f72c0000.usb: EPs: 16, dedicated fifos, 1920 entries in SPRAM
[ 2.353154] dwc2 f72c0000.usb: DWC OTG Controller
[ 2.357891] dwc2 f72c0000.usb: new USB bus registered, assigned bus number 1
[ 2.364979] dwc2 f72c0000.usb: irq 38, io mem 0x00000000
[ 2.371082] hub 1-0:1.0: USB hub found
[ 2.374866] hub 1-0:1.0: 1 port detected
[ 2.382071] rtc-pl031 f8003000.rtc: setting system clock to 1970-01-01 00:00:19 UTC (19)
[ 2.390486] LDO2_2V8: disabling
[ 2.393639] LDO7_SDIO: disabling
[ 2.396900] LDO10_2V85: disabling
[ 2.400234] LDO13_1V8: disabling
[ 2.403476] LDO14_2V8: disabling
[ 2.406721] LDO17_2V5: disabling
[ 2.409956] LDO19_3V0: disabling
[ 2.413199] wlan-en-regulator: disabling
[ 2.417135] ALSA device list:
[ 2.420109] No soundcards found.
[ 2.423712] uart-pl011 f7113000.uart: no DMA platform data
[ 2.429585] Freeing unused kernel memory: 1024K (ffff800000c40000 - ffff800000d40000)
Loading, please wait...
starting version 228
[ 2.479981] random: systemd-udevd: uninitialized urandom read (16 bytes read)
[ 2.483570] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.483680] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.485404] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.485631] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.485859] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.486098] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.486305] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.486729] random: udevadm: uninitialized urandom read (16 bytes read)
[ 2.486951] random: udevadm: uninitialized urandom read (16 bytes read)
Begin: Loading essential drivers ... done.
Begin: Running /scripts/init-premount ... done.
Begin: Mounting root file system ... Begin: Running /scripts/local-top ... done.
Begin: Running /scripts/local-premount ... modprobe: can't change directory to '4.9.0-rc1-00251-g323792f': No such file or directory
done.
Begin: Waiting for root file system ... Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Begin: Running /scripts/local-block ... done.
Thanks,
Leo Yan
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: hi6220: add resets property into dwmmc nodes
From: Jaehoon Chung @ 2016-10-28 7:33 UTC (permalink / raw)
To: Leo Yan, Vincent Guittot
Cc: Mark Rutland, Rob Herring, Guodong Xu, devicetree@vger.kernel.org,
Xinliang Liu, Catalin Marinas, Will Deacon, linux-kernel, Wei Xu,
Rob Herring, John Stultz, Fathi Boudra, LAK
In-Reply-To: <20161028072640.GB17266@leoy-linaro>
Hi,
On 10/28/2016 04:26 PM, Leo Yan wrote:
> On Fri, Oct 28, 2016 at 08:43:51AM +0200, Vincent Guittot wrote:
>
> [...]
>
>>> running with? Also do you have any details about the card in case its
>>> card specific?
>>
>> The sdcard is quite common: sandisk ultra 16GB
>> and my rootfs is on the sdcard
>
> I'm using rootfs in emmc also have same failure.
>
>>> Guodong: Is there any bootloader dependency on that change?
>>
>> FYI, I use firmwares available in AOSP
>
> I tried latest firmware [1], still cannot boot up until revert the
> patch "arm64: dts: hi6220: add resets property into dwmmc nodes".
Could you share the log? Is there any log about failure?
Best Regards,
Jaehoon Chung
>
> [1] http://builds.96boards.org/snapshots/hikey/linaro/uefi-openplatformpkg/latest/
>
> Thanks,
> Leo Yan
>
>
>
^ permalink raw reply
* Re: [PATCH v2 2/2] arm64: dts: hi6220: add resets property into dwmmc nodes
From: Leo Yan @ 2016-10-28 7:26 UTC (permalink / raw)
To: Vincent Guittot
Cc: John Stultz, Guodong Xu, Wei Xu, Rob Herring, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon,
devicetree@vger.kernel.org, Xinliang Liu, linux-kernel,
Jaehoon Chung, Fathi Boudra, LAK
In-Reply-To: <CAKfTPtAXdkKcfpHmUmQNwuJxO0PORcCf49noST_CCkZPigPwgw@mail.gmail.com>
On Fri, Oct 28, 2016 at 08:43:51AM +0200, Vincent Guittot wrote:
[...]
> > running with? Also do you have any details about the card in case its
> > card specific?
>
> The sdcard is quite common: sandisk ultra 16GB
> and my rootfs is on the sdcard
I'm using rootfs in emmc also have same failure.
> > Guodong: Is there any bootloader dependency on that change?
>
> FYI, I use firmwares available in AOSP
I tried latest firmware [1], still cannot boot up until revert the
patch "arm64: dts: hi6220: add resets property into dwmmc nodes".
[1] http://builds.96boards.org/snapshots/hikey/linaro/uefi-openplatformpkg/latest/
Thanks,
Leo Yan
^ permalink raw reply
* Re: [PATCH] ARM: DT: stm32: move dma translation to board files
From: Radosław Pietrzyk @ 2016-10-28 7:09 UTC (permalink / raw)
To: Bruno Herrera
Cc: Alexandre Torgue, mark.rutland, devicetree, Arnd Bergmann, linux,
>, >, Maxime Coquelin, Lee Jones, linux-arm-kernel
In-Reply-To: <CAF3+TqcxVj9f7kcSQTKDercVfvDdLzAXGpUU1oAxeNBFZx73nQ@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 8308 bytes --]
Have you defined your sdio node within soc node ?
2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera@gmail.com>:
> Hi Alex,
>
> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
> <alexandre.torgue@st.com> wrote:
> > Hi Bruno,
> >
> >
> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
> >>
> >> Hi Alex,
> >>
> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
> >> <alexandre.torgue@st.com> wrote:
> >>>
> >>> Hi Bruno,
> >>>
> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
> >>>>
> >>>>
> >>>> Hi Alexandre,
> >>>>
> >>>>>
> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM start address
> >>>>> remapping
> >>>>> (to @0) to boost performances. A DMA translation through "dma-ranges"
> >>>>> property was needed for other masters than the M4 CPU.
> >>>>> stm32f429-disco doesn't use remapping so doesn't need this DMA
> >>>>> translation.
> >>>>> This patches moves this DMA translation definition from stm32f429 soc
> >>>>> file
> >>>>> to board files.
> >>>>>
> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com>
> >>>>>
> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
> >>>>> index 13c7cd2..a763c15 100644
> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
> >>>>> @@ -82,6 +82,10 @@
> >>>>> };
> >>>>> };
> >>>>>
> >>>>> + soc {
> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
> >>>>> + };
> >>>>> +
> >>>>> usbotg_hs_phy: usbphy {
> >>>>> #phy-cells = <0>;
> >>>>> compatible = "usb-nop-xceiv";
> >>>>
> >>>>
> >>>>
> >>>> Shouldn't also the peripheral dma-ranges property move to board
> specific
> >>>> too?
> >>>> I had this patch for while but I didn't had the time to submit:
> >>>
> >>>
> >>>
> >>> Well spot I forgot it. Actually, discussing with Arnd ysterday on IIRC,
> >>> empty dma-ranges is not needed. Can you test on your side by removing
> >>> dma-ranges in usb node please ?
> >>
> >> Unfortunately will take a time for me to set up this environment on
> >> the STM32F4-EVAL board.
> >> And on the discovery boards we dont have this scenario. That was the
> >> main reason I did not submit the patch right away.
> >> My conclusion and I might be wrong but is based on the my tests with
> >> SDIO device at STM32F469I-DISCO board.
> >>
> >> I started this issue as discussion at ST Forum but Maxime gave me the
> >> hint.
> >>
> >>
> >> https://my.st.com/public/STe2ecommunities/mcu/Lists/
> cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%
> 2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%
> 2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=
> 0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46
> A77F0FFD06506F5B¤tviews=44
> >>
> >>> I will push a v2 by removing empty dma-ranges if tests are ok in your
> >>> side.
> >>
> >>
> >> From my understating/conclusion is: when empty property(dma-ranges) is
> >> the device node, the mapping will be taken in consideration when using
> >> DMA otherwise the mapping is ignored.
> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
> >> MEM(SDRAM)->DEV. If it is not the case for the devices in question so
> >> I suppose it can work without the property.
> >
> >
> > For sure translation has to be done but I'm not sure that an empty
> > "dma-ranges" is needed in device node to activate it. For Ethernet empty
> > "dma-ranges" is not needed. I will try with usb.
>
> In the case of SDIO it is needed. As example this is my working SDIO node:
>
> sdio: sdio@40012c00 {
> compatible = "arm,pl18x", "arm,primecell";
> arm,primecell-periphid = <0x00480181>;
> reg = <0x40012c00 0x400>;
> dmas = <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
> dma-names = "rx", "tx";
> clocks = <&rcc 0 171>;
> clock-names = "apb_pclk";
> interrupts = <49>;
> status = "disabled";
> };
>
> &sdio {
> status = "okay";
> vmmc-supply = <&wlan_en>;
> bus-width = <4>;
> max-frequency = <24000000>;
> pinctrl-names = "default";
> pinctrl-0 = <&sdio_pins>;
> ti,non-removable;
> ti,needs-special-hs-handling;
> dma-ranges;
> cap-power-off-card;
> keep-power-in-suspend;
>
> #address-cells = <1>;
> #size-cells = <0>;
> wlcore: wlcore@0 {
> compatible = "ti,wl1835";
> reg = <2>;
> interrupt-parent = <&gpioa>;
> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
> };
> };
>
> >
> > alex
> >
> >
> >>
> >>>
> >>> Thanks in advance
> >>> Alex
> >>>
> >>>
> >>>>
> >>>> Author: Bruno Herrera <bruherrera@gmail.com>
> >>>> Date: Sun Oct 16 14:50:00 2016 -0200
> >>>>
> >>>> ARM: DT: STM32: Use dma-ranges property per board not at dtsi file
> >>>>
> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
> >>>> index 6bfc595..2a22a82 100644
> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
> >>>> @@ -52,6 +52,10 @@
> >>>> model = "STMicroelectronics STM32429i-EVAL board";
> >>>> compatible = "st,stm32429i-eval", "st,stm32f429";
> >>>>
> >>>> + soc {
> >>>> + dma-ranges = <0xC0000000 0x0 0x10000000>;
> >>>> + };
> >>>> +
> >>>> chosen {
> >>>> bootargs = "root=/dev/ram rdinit=/linuxrc";
> >>>> stdout-path = "serial0:115200n8";
> >>>> @@ -96,6 +100,7 @@
> >>>>
> >>>> ðernet0 {
> >>>> status = "okay";
> >>>> + dma-ranges;
> >>>> pinctrl-0 = <ðernet0_mii>;
> >>>> pinctrl-names = "default";
> >>>> phy-mode = "mii-id";
> >>>> @@ -116,6 +121,7 @@
> >>>> };
> >>>>
> >>>> &usbotg_hs {
> >>>> + dma-ranges;
> >>>> dr_mode = "host";
> >>>> phys = <&usbotg_hs_phy>;
> >>>> phy-names = "usb2-phy";
> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
> >>>> index 7d624a2..697a133 100644
> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> >>>> @@ -59,7 +59,6 @@
> >>>> };
> >>>>
> >>>> soc {
> >>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
> >>>>
> >>>> timer2: timer@40000000 {
> >>>> compatible = "st,stm32-timer";
> >>>> @@ -472,13 +471,11 @@
> >>>> st,syscon = <&syscfg 0x4>;
> >>>> snps,pbl = <8>;
> >>>> snps,mixed-burst;
> >>>> - dma-ranges;
> >>>> status = "disabled";
> >>>> };
> >>>>
> >>>> usbotg_hs: usb@40040000 {
> >>>> compatible = "snps,dwc2";
> >>>> - dma-ranges;
> >>>> reg = <0x40040000 0x40000>;
> >>>> interrupts = <77>;
> >>>> clocks = <&rcc 0 29>;
> >>>>
> >>>>
> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
> >>>>> index 0596d60..3a1cfdd 100644
> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> >>>>> @@ -59,8 +59,6 @@
> >>>>> };
> >>>>>
> >>>>> soc {
> >>>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
> >>>>> -
> >>>>> timer2: timer@40000000 {
> >>>>> compatible = "st,stm32-timer";
> >>>>> reg = <0x40000000 0x400>;
> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
> >>>>> index 9e73656..c2213c0 100644
> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
> >>>>> @@ -64,6 +64,10 @@
> >>>>> aliases {
> >>>>> serial0 = &usart3;
> >>>>> };
> >>>>> +
> >>>>> + soc {
> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
> >>>>> + };
> >>>>> };
> >>>>>
> >>>>> &clk_hse {
> >>>>> --
> >>>>
> >>>>
> >>>>
> >>>>
> >>>> Br.,
> >>>> Bruno
> >>>>
> >>>
> >
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
[-- Attachment #2: Type: text/html, Size: 13616 bytes --]
^ permalink raw reply
* RE: [v13, 5/8] soc: fsl: add GUTS driver for QorIQ platforms
From: Y.B. Lu @ 2016-10-28 7:08 UTC (permalink / raw)
To: Scott Wood, linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, X.B. Xie, M.H. Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Qiang Zhao,
Russell King, Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
In-Reply-To: <1477629956.6812.15.camel@buserror.net>
> -----Original Message-----
> From: Y.B. Lu
> Sent: Friday, October 28, 2016 2:06 PM
> To: Y.B. Lu; 'Scott Wood'; 'linux-mmc@vger.kernel.org';
> 'ulf.hansson@linaro.org'; 'Arnd Bergmann'
> Cc: 'linuxppc-dev@lists.ozlabs.org'; 'devicetree@vger.kernel.org';
> 'linux-arm-kernel@lists.infradead.org'; 'linux-kernel@vger.kernel.org';
> 'linux-clk@vger.kernel.org'; 'linux-i2c@vger.kernel.org';
> 'iommu@lists.linux-foundation.org'; 'netdev@vger.kernel.org'; 'Greg
> Kroah-Hartman'; 'Mark Rutland'; 'Rob Herring'; 'Russell King'; 'Jochen
> Friedrich'; 'Joerg Roedel'; 'Claudiu Manoil'; 'Bhupesh Sharma'; Qiang
> Zhao; 'Kumar Gala'; 'Santosh Shilimkar'; Leo Li; X.B. Xie; M.H. Lian
> Subject: RE: [v13, 5/8] soc: fsl: add GUTS driver for QorIQ platforms
>
> > -----Original Message-----
> > From: Y.B. Lu
> > Sent: Friday, October 28, 2016 2:00 PM
> > To: 'Scott Wood'; linux-mmc@vger.kernel.org; ulf.hansson@linaro.org;
> > Arnd Bergmann
> > Cc: linuxppc-dev@lists.ozlabs.org; devicetree@vger.kernel.org;
> > linux-arm- kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> > linux- clk@vger.kernel.org; linux-i2c@vger.kernel.org;
> > iommu@lists.linux- foundation.org; netdev@vger.kernel.org; Greg
> > Kroah-Hartman; Mark Rutland; Rob Herring; Russell King; Jochen
> > Friedrich; Joerg Roedel; Claudiu Manoil; Bhupesh Sharma; Qiang Zhao;
> Kumar Gala; Santosh Shilimkar; Leo Li; X.B.
> > Xie; M.H. Lian
> > Subject: RE: [v13, 5/8] soc: fsl: add GUTS driver for QorIQ platforms
> >
> >
> >
> > > -----Original Message-----
> > > From: linux-mmc-owner@vger.kernel.org [mailto:linux-mmc-
> > > owner@vger.kernel.org] On Behalf Of Scott Wood
> > > Sent: Friday, October 28, 2016 12:46 PM
> > > To: Y.B. Lu; linux-mmc@vger.kernel.org; ulf.hansson@linaro.org; Arnd
> > > Bergmann
> > > Cc: linuxppc-dev@lists.ozlabs.org; devicetree@vger.kernel.org;
> > > linux-arm- kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> > > linux- clk@vger.kernel.org; linux-i2c@vger.kernel.org;
> > > iommu@lists.linux- foundation.org; netdev@vger.kernel.org; Greg
> > > Kroah-Hartman; Mark Rutland; Rob Herring; Russell King; Jochen
> > > Friedrich; Joerg Roedel; Claudiu Manoil; Bhupesh Sharma; Qiang Zhao;
> > Kumar Gala; Santosh Shilimkar; Leo Li; X.B.
> > > Xie; M.H. Lian
> > > Subject: Re: [v13, 5/8] soc: fsl: add GUTS driver for QorIQ
> > > platforms
> > >
> > > On Fri, 2016-10-28 at 11:32 +0800, Yangbo Lu wrote:
> > > > + guts->regs = of_iomap(np, 0);
> > > > + if (!guts->regs)
> > > > + return -ENOMEM;
> > > > +
> > > > + /* Register soc device */
> > > > + machine = of_flat_dt_get_machine_name();
> > > > + if (machine)
> > > > + soc_dev_attr.machine = devm_kstrdup(dev, machine,
> > > > GFP_KERNEL);
> > > > +
> > > > + svr = fsl_guts_get_svr();
> > > > + soc_die = fsl_soc_die_match(svr, fsl_soc_die);
> > > > + if (soc_die) {
> > > > + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
> > > > + "QorIQ %s", soc_die-
> > > > >die);
> > > > + } else {
> > > > + soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
> > > > "QorIQ");
> > > > + }
> > > > + soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
> > > > + "svr:0x%08x", svr);
> > > > + soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL,
> "%d.%d",
> > > > + SVR_MAJ(svr), SVR_MIN(svr));
> > > > +
> > > > + soc_dev = soc_device_register(&soc_dev_attr);
> > > > + if (IS_ERR(soc_dev))
> > > > + return PTR_ERR(soc_dev);
> > >
> > > ioremap leaks on this error path. Use devm_ioremap_resource().
> > >
> >
> > [Lu Yangbo-B47093] Ok. I have fixed it in v14. Thanks :)
>
> [Lu Yangbo-B47093] Sorry, used the wrong error code... Will resent it
[Lu Yangbo-B47093] The v15 had been sent. And dropped patch 'dt: bindings: update Freescale DCFG compatible',
since that work has been done by below patch on ShawnGuo's linux tree.
'dt-bindings: fsl: add LS1043A/LS1046A/LS2080A compatible for SCFG and DCFG'
https://git.kernel.org/cgit/linux/kernel/git/shawnguo/linux.git/commit/?h=imx/dt64&id=981034a2bfcaff5c95dafde24d7abfe7f9025c19
Thanks.
>
> >
> > > -Scott
> > >
> > > --
> > > To unsubscribe from this list: send the line "unsubscribe linux-mmc"
> > > in the body of a message to majordomo@vger.kernel.org More majordomo
> > > info at http://vger.kernel.org/majordomo-info.html
_______________________________________________
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https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* [PATCH v2 3/3] ARM: dts: sun8i: Add dts file for NanoPi M1 SBC
From: Milo Kim @ 2016-10-28 6:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, James Pettigrew,
Milo Kim
In-Reply-To: <20161028065903.23298-1-woogyom.kim@gmail.com>
NanoPi M1 is the Allwinner H3 based board.
This patch enables UART for debug console, LEDs, GPIO key switch, 3 USB
host ports, a micro SD slot and related power and pin controls by using
NanoPi common dtsi file.
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 64 ++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
new file mode 100644
index 0000000..ec63d10
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "sun8i-h3-nanopi.dtsi"
+
+/ {
+ model = "FriendlyArm NanoPi M1";
+ compatible = "friendlyarm,nanopi-m1", "allwinner,sun8i-h3";
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&ehci2 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&ohci2 {
+ status = "okay";
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 2/3] ARM: dts: sun8i: Use the common file in NanoPi NEO SBC
From: Milo Kim @ 2016-10-28 6:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, James Pettigrew,
Milo Kim
In-Reply-To: <20161028065903.23298-1-woogyom.kim@gmail.com>
NanoPi common dtsi supports all components of NEO SBC, so just include it.
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 79 +------------------------------
1 file changed, 1 insertion(+), 78 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
index 3d64caf..8d2cc6e 100644
--- a/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts
@@ -40,86 +40,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-/dts-v1/;
-#include "sun8i-h3.dtsi"
-#include "sunxi-common-regulators.dtsi"
-
-#include <dt-bindings/gpio/gpio.h>
-#include <dt-bindings/pinctrl/sun4i-a10.h>
+#include "sun8i-h3-nanopi.dtsi"
/ {
model = "FriendlyARM NanoPi NEO";
compatible = "friendlyarm,nanopi-neo", "allwinner,sun8i-h3";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- leds {
- compatible = "gpio-leds";
- pinctrl-names = "default";
- pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
-
- pwr {
- label = "nanopi:green:pwr";
- gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>; /* PL10 */
- default-state = "on";
- };
-
- status {
- label = "nanopi:blue:status";
- gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>; /* PA10 */
- };
- };
-};
-
-&ehci3 {
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default";
- pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
- vmmc-supply = <®_vcc3v3>;
- bus-width = <4>;
- cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
- cd-inverted;
- status = "okay";
-};
-
-&ohci3 {
- status = "okay";
-};
-
-&pio {
- leds_opc: led-pins {
- allwinner,pins = "PA10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&r_pio {
- leds_r_opc: led-pins {
- allwinner,pins = "PL10";
- allwinner,function = "gpio_out";
- allwinner,drive = <SUN4I_PINCTRL_10_MA>;
- allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
- };
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins_a>;
- status = "okay";
-};
-
-&usbphy {
- /* USB VBUS is always on */
- status = "okay";
};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 1/3] ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs
From: Milo Kim @ 2016-10-28 6:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree, linux-arm-kernel, linux-kernel, James Pettigrew,
Milo Kim
In-Reply-To: <20161028065903.23298-1-woogyom.kim@gmail.com>
This patch provides a common file for NanoPi M1 and Neo SBC.
Those have common features below.
* UART0
* 2 LEDs
* USB host (EHCI3, OHCI3) and PHY
* MicroSD
* GPIO key switch
Cc: James Pettigrew <james@innovum.com.au>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 144 +++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
new file mode 100644
index 0000000..8038aa2
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
@@ -0,0 +1,144 @@
+/*
+ * Copyright (C) 2016 James Pettigrew <james@innovum.com.au>
+ * Copyright (C) 2016 Milo Kim <woogyom.kim@gmail.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <&leds_npi>, <&leds_r_npi>;
+
+ status {
+ label = "nanopi:blue:status";
+ gpios = <&pio 0 10 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+
+ pwr {
+ label = "nanopi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+ };
+
+ r_gpio_keys {
+ compatible = "gpio-keys";
+ input-name = "k1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&sw_r_npi>;
+
+ k1@0 {
+ label = "k1";
+ linux,code = <KEY_POWER>;
+ gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
+ };
+ };
+};
+
+&ehci3 {
+ status = "okay";
+};
+
+&mmc0 {
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
+ status = "okay";
+ vmmc-supply = <®_vcc3v3>;
+};
+
+&ohci3 {
+ status = "okay";
+};
+
+&pio {
+ leds_npi: led_pins@0 {
+ allwinner,pins = "PA10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&r_pio {
+ leds_r_npi: led_pins@0 {
+ allwinner,pins = "PL10";
+ allwinner,function = "gpio_out";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ sw_r_npi: key_pins@0 {
+ allwinner,pins = "PL3";
+ allwinner,function = "gpio_in";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&usbphy {
+ status = "okay";
+};
--
2.9.3
^ permalink raw reply related
* [PATCH v2 0/3] ARM: dts: sun8i: Support NanoPi SBCs
From: Milo Kim @ 2016-10-28 6:59 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, James Pettigrew, Milo Kim
NanoPi M1 and NEO have common features, so duplicate properties can be
moved into new dtsi file.
v2:
Add James's copyrights in NanoPi common dtsi file
Milo Kim (3):
ARM: dts: sun8i: Add common dtsi file for NanoPi SBCs
ARM: dts: sun8i: Use the common file in NanoPi NEO SBC
ARM: dts: sun8i: Add dts file for NanoPi M1 SBC
arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts | 64 +++++++++++++
arch/arm/boot/dts/sun8i-h3-nanopi-neo.dts | 79 +---------------
arch/arm/boot/dts/sun8i-h3-nanopi.dtsi | 144 ++++++++++++++++++++++++++++++
3 files changed, 209 insertions(+), 78 deletions(-)
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi-m1.dts
create mode 100644 arch/arm/boot/dts/sun8i-h3-nanopi.dtsi
--
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply
* [PATCH v2 4/4] spi: sun6i: Support Allwinner H3 SPI controller
From: Milo Kim @ 2016-10-28 6:54 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Mark Brown
Cc: devicetree, linux-arm-kernel, linux-spi, linux-kernel, Milo Kim
In-Reply-To: <20161028065412.23008-1-woogyom.kim@gmail.com>
H3 has two SPI controllers. The size of the buffer is 64 * 8.
(8 bit transfer by 64 entry FIFO)
A31 has four controllers. The size of the buffer is 128 * 8.
(8 bit transfer by 128 entry FIFO)
Register maps are sharable, so sun6i SPI driver is reusable with
device configuration.
Use the variable, 'fifo_depth' instead of fixed value to support both SPI
controllers.
Cc: Mark Brown <broonie@kernel.org>
Cc: Maxime Ripard <maxime.ripard@free-electrons.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Milo Kim <woogyom.kim@gmail.com>
---
drivers/spi/spi-sun6i.c | 18 +++++++++++++-----
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c
index 9918a57..e311483 100644
--- a/drivers/spi/spi-sun6i.c
+++ b/drivers/spi/spi-sun6i.c
@@ -17,6 +17,7 @@
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/module.h>
+#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/reset.h>
@@ -24,6 +25,7 @@
#include <linux/spi/spi.h>
#define SUN6I_FIFO_DEPTH 128
+#define SUN8I_FIFO_DEPTH 64
#define SUN6I_GBL_CTL_REG 0x04
#define SUN6I_GBL_CTL_BUS_ENABLE BIT(0)
@@ -90,6 +92,7 @@ struct sun6i_spi {
const u8 *tx_buf;
u8 *rx_buf;
int len;
+ unsigned long fifo_depth;
};
static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg)
@@ -155,7 +158,9 @@ static void sun6i_spi_set_cs(struct spi_device *spi, bool enable)
static size_t sun6i_spi_max_transfer_size(struct spi_device *spi)
{
- return SUN6I_FIFO_DEPTH - 1;
+ struct sun6i_spi *sspi = spi_master_get_devdata(spi->master);
+
+ return sspi->fifo_depth - 1;
}
static int sun6i_spi_transfer_one(struct spi_master *master,
@@ -170,7 +175,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
u32 reg;
/* We don't support transfer larger than the FIFO */
- if (tfr->len > SUN6I_FIFO_DEPTH)
+ if (tfr->len > sspi->fifo_depth)
return -EINVAL;
reinit_completion(&sspi->done);
@@ -265,7 +270,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
SUN6I_BURST_CTL_CNT_STC(tx_len));
/* Fill the TX FIFO */
- sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH);
+ sun6i_spi_fill_fifo(sspi, sspi->fifo_depth);
/* Enable the interrupts */
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC);
@@ -288,7 +293,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master,
goto out;
}
- sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH);
+ sun6i_spi_drain_fifo(sspi, sspi->fifo_depth);
out:
sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0);
@@ -398,6 +403,8 @@ static int sun6i_spi_probe(struct platform_device *pdev)
}
sspi->master = master;
+ sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev);
+
master->max_speed_hz = 100 * 1000 * 1000;
master->min_speed_hz = 3 * 1000;
master->set_cs = sun6i_spi_set_cs;
@@ -470,7 +477,8 @@ static int sun6i_spi_remove(struct platform_device *pdev)
}
static const struct of_device_id sun6i_spi_match[] = {
- { .compatible = "allwinner,sun6i-a31-spi", },
+ { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH },
+ { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH },
{}
};
MODULE_DEVICE_TABLE(of, sun6i_spi_match);
--
2.9.3
^ permalink raw reply related
* [PATCH v2 3/4] spi: sun6i: Add binding for Allwinner H3 SPI controller
From: Milo Kim @ 2016-10-28 6:54 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Milo Kim, Rob Herring
In-Reply-To: <20161028065412.23008-1-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
H3 SPI has same architecture as A31 except FIFO capacity.
To configure the buffer size separately, compatible property should be
different. Optional DMA specifiers and example are added.
Acked-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
.../devicetree/bindings/spi/spi-sun6i.txt | 25 ++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/spi-sun6i.txt b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
index 21de73d..2ec99b8 100644
--- a/Documentation/devicetree/bindings/spi/spi-sun6i.txt
+++ b/Documentation/devicetree/bindings/spi/spi-sun6i.txt
@@ -1,7 +1,7 @@
-Allwinner A31 SPI controller
+Allwinner A31/H3 SPI controller
Required properties:
-- compatible: Should be "allwinner,sun6i-a31-spi".
+- compatible: Should be "allwinner,sun6i-a31-spi" or "allwinner,sun8i-h3-spi".
- reg: Should contain register location and length.
- interrupts: Should contain interrupt.
- clocks: phandle to the clocks feeding the SPI controller. Two are
@@ -12,6 +12,11 @@ Required properties:
- resets: phandle to the reset controller asserting this device in
reset
+Optional properties:
+- dmas: DMA specifiers for rx and tx dma. See the DMA client binding,
+ Documentation/devicetree/bindings/dma/dma.txt
+- dma-names: DMA request names should include "rx" and "tx" if present.
+
Example:
spi1: spi@01c69000 {
@@ -22,3 +27,19 @@ spi1: spi@01c69000 {
clock-names = "ahb", "mod";
resets = <&ahb1_rst 21>;
};
+
+spi0: spi@01c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+};
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 2/4] ARM: dts: sun8i: Add SPI controller node in H3
From: Milo Kim @ 2016-10-28 6:54 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Milo Kim
In-Reply-To: <20161028065412.23008-1-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
H3 SPI subsystem is almost same as A31 SPI except buffer size, so those
DT properties are reusable.
Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 8a59d8d..c38b028 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -439,6 +439,38 @@
clocks = <&osc24M>;
};
+ spi0: spi@01c68000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c68000 0x1000>;
+ interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 23>, <&dma 23>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi0_pins>;
+ resets = <&ccu RST_BUS_SPI0>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ spi1: spi@01c69000 {
+ compatible = "allwinner,sun8i-h3-spi";
+ reg = <0x01c69000 0x1000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
+ clock-names = "ahb", "mod";
+ dmas = <&dma 24>, <&dma 24>;
+ dma-names = "rx", "tx";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spi1_pins>;
+ resets = <&ccu RST_BUS_SPI1>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
wdt0: watchdog@01c20ca0 {
compatible = "allwinner,sun6i-a31-wdt";
reg = <0x01c20ca0 0x20>;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 1/4] ARM: dts: sun8i: Add SPI pinctrl node in H3
From: Milo Kim @ 2016-10-28 6:54 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Milo Kim
In-Reply-To: <20161028065412.23008-1-woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
H3 supports two SPI controllers. Four pins (MOSI, MISO, SCLK, SS) are
configured through the pinctrl subsystem.
Cc: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Cc: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
Signed-off-by: Milo Kim <woogyom.kim-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/sun8i-h3.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index 75a8654..8a59d8d 100644
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -381,6 +381,20 @@
allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
};
+ spi0_pins: spi0 {
+ allwinner,pins = "PC0", "PC1", "PC2", "PC3";
+ allwinner,function = "spi0";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
+ spi1_pins: spi1 {
+ allwinner,pins = "PA15", "PA16", "PA14", "PA13";
+ allwinner,function = "spi1";
+ allwinner,drive = <SUN4I_PINCTRL_10_MA>;
+ allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
+ };
+
uart0_pins_a: uart0@0 {
allwinner,pins = "PA4", "PA5";
allwinner,function = "uart0";
--
2.9.3
--
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^ permalink raw reply related
* [PATCH v2 0/4] Support H3 SPI controller
From: Milo Kim @ 2016-10-28 6:54 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Mark Brown
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-spi-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Milo Kim
Allwinner H3 SPI controller has same architecture as A31.
So most configuration is identical except one thing - FIFO capacity.
A31 H3
------------------------------------
Number of controllers 4 2
Number of FIFO depth 128 64
Transfer bits 8 8
Register maps are sharable, so sun6i SPI driver is reusable with
device configuration.
Tested on Nano Pi M1 and SPI slave device is TI LP8860.
v2:
Include DTS patches
Use of_device_get_match_data() helper to get device specific data
Fix build warning of 64bit CPU architecture
(warning: cast from pointer to integer of different size
[-Wpointer-to-int-cast])
Milo Kim (4):
ARM: dts: sun8i: Add SPI pinctrl node in H3
ARM: dts: sun8i: Add SPI controller node in H3
spi: sun6i: Add binding for Allwinner H3 SPI controller
spi: sun6i: Support Allwinner H3 SPI controller
.../devicetree/bindings/spi/spi-sun6i.txt | 25 +++++++++++-
arch/arm/boot/dts/sun8i-h3.dtsi | 46 ++++++++++++++++++++++
drivers/spi/spi-sun6i.c | 18 ++++++---
3 files changed, 82 insertions(+), 7 deletions(-)
--
2.9.3
--
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^ permalink raw reply
* [v15, 7/7] mmc: sdhci-of-esdhc: fix host version for T4240-R1.0-R2.0
From: Yangbo Lu @ 2016-10-28 6:50 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Scott Wood, Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, Xiaobo Xie, Minghuan Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Qiang Zhao, Russell King,
Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA, Yangbo Lu, Rob Herring,
Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Kumar Gala,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1477637418-38938-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
The eSDHC of T4240-R1.0-R2.0 has incorrect vender version and spec version.
Acturally the right version numbers should be VVN=0x13 and SVN = 0x1.
This patch adds the GUTS driver support for eSDHC driver to match SoC.
And fix host version to avoid that incorrect version numbers break down
the ADMA data transfer.
Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Acked-by: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
---
Changes for v2:
- Got SVR through iomap instead of dts
Changes for v3:
- Managed GUTS through syscon instead of iomap in eSDHC driver
Changes for v4:
- Got SVR by GUTS driver instead of SYSCON
Changes for v5:
- Changed to get SVR through API fsl_guts_get_svr()
- Combined patch 4, patch 5 and patch 6 into one
Changes for v6:
- Added 'Acked-by: Ulf Hansson'
Changes for v7:
- None
Changes for v8:
- Added 'Acked-by: Scott Wood'
Changes for v9:
- None
Changes for v10:
- None
Changes for v11:
- Changed to use soc_device_match
Changes for v12:
- Matched soc through .family field instead of .soc_id
Changes for v13:
- None
Changes for v14:
- None
Changes for v15:
- None
---
drivers/mmc/host/Kconfig | 1 +
drivers/mmc/host/sdhci-of-esdhc.c | 20 ++++++++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 5274f50..a1135a9 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -144,6 +144,7 @@ config MMC_SDHCI_OF_ESDHC
depends on MMC_SDHCI_PLTFM
depends on PPC || ARCH_MXC || ARCH_LAYERSCAPE
select MMC_SDHCI_IO_ACCESSORS
+ select FSL_GUTS
help
This selects the Freescale eSDHC controller support.
diff --git a/drivers/mmc/host/sdhci-of-esdhc.c b/drivers/mmc/host/sdhci-of-esdhc.c
index fb71c86..57bdb9e 100644
--- a/drivers/mmc/host/sdhci-of-esdhc.c
+++ b/drivers/mmc/host/sdhci-of-esdhc.c
@@ -18,6 +18,7 @@
#include <linux/of.h>
#include <linux/delay.h>
#include <linux/module.h>
+#include <linux/sys_soc.h>
#include <linux/mmc/host.h>
#include "sdhci-pltfm.h"
#include "sdhci-esdhc.h"
@@ -28,6 +29,7 @@
struct sdhci_esdhc {
u8 vendor_ver;
u8 spec_ver;
+ bool quirk_incorrect_hostver;
};
/**
@@ -73,6 +75,8 @@ static u32 esdhc_readl_fixup(struct sdhci_host *host,
static u16 esdhc_readw_fixup(struct sdhci_host *host,
int spec_reg, u32 value)
{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host);
u16 ret;
int shift = (spec_reg & 0x2) * 8;
@@ -80,6 +84,12 @@ static u16 esdhc_readw_fixup(struct sdhci_host *host,
ret = value & 0xffff;
else
ret = (value >> shift) & 0xffff;
+ /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect
+ * vendor version and spec version information.
+ */
+ if ((spec_reg == SDHCI_HOST_VERSION) &&
+ (esdhc->quirk_incorrect_hostver))
+ ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200;
return ret;
}
@@ -558,6 +568,12 @@ static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = {
.ops = &sdhci_esdhc_le_ops,
};
+static struct soc_device_attribute soc_incorrect_hostver[] = {
+ { .family = "QorIQ T4240", .revision = "1.0", },
+ { .family = "QorIQ T4240", .revision = "2.0", },
+ { },
+};
+
static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
{
struct sdhci_pltfm_host *pltfm_host;
@@ -571,6 +587,10 @@ static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host)
esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >>
SDHCI_VENDOR_VER_SHIFT;
esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK;
+ if (soc_device_match(soc_incorrect_hostver))
+ esdhc->quirk_incorrect_hostver = true;
+ else
+ esdhc->quirk_incorrect_hostver = false;
}
static int sdhci_esdhc_probe(struct platform_device *pdev)
--
2.1.0.27.g96db324
^ permalink raw reply related
* [v15, 6/7] base: soc: introduce soc_device_match() interface
From: Yangbo Lu @ 2016-10-28 6:50 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Scott Wood, Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, Xiaobo Xie, Minghuan Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Qiang Zhao, Russell King,
Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA, Yangbo Lu, Rob Herring,
Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Kumar Gala,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1477637418-38938-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
From: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
We keep running into cases where device drivers want to know the exact
version of the a SoC they are currently running on. In the past, this has
usually been done through a vendor specific API that can be called by a
driver, or by directly accessing some kind of version register that is
not part of the device itself but that belongs to a global register area
of the chip.
Common reasons for doing this include:
- A machine is not using devicetree or similar for passing data about
on-chip devices, but just announces their presence using boot-time
platform devices, and the machine code itself does not care about the
revision.
- There is existing firmware or boot loaders with existing DT binaries
with generic compatible strings that do not identify the particular
revision of each device, but the driver knows which SoC revisions
include which part.
- A prerelease version of a chip has some quirks and we are using the same
version of the bootloader and the DT blob on both the prerelease and the
final version. An update of the DT binding seems inappropriate because
that would involve maintaining multiple copies of the dts and/or
bootloader.
This patch introduces the soc_device_match() interface that is meant to
work like of_match_node() but instead of identifying the version of a
device, it identifies the SoC itself using a vendor-agnostic interface.
Unlike of_match_node(), we do not do an exact string compare but instead
use glob_match() to allow wildcards in strings.
Signed-off-by: Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org>
Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Acked-by: Greg Kroah-Hartman <gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r@public.gmane.org>
---
Changes for v11:
- Added this patch for soc match
Changes for v12:
- Corrected the author
- Rewrited soc_device_match with while loop
Changes for v13:
- Added ack from Greg
Changes for v14:
- None
Changes for v15:
- None
---
drivers/base/Kconfig | 1 +
drivers/base/soc.c | 66 +++++++++++++++++++++++++++++++++++++++++++++++++
include/linux/sys_soc.h | 3 +++
3 files changed, 70 insertions(+)
diff --git a/drivers/base/Kconfig b/drivers/base/Kconfig
index fdf44ca..991b21e 100644
--- a/drivers/base/Kconfig
+++ b/drivers/base/Kconfig
@@ -235,6 +235,7 @@ config GENERIC_CPU_AUTOPROBE
config SOC_BUS
bool
+ select GLOB
source "drivers/base/regmap/Kconfig"
diff --git a/drivers/base/soc.c b/drivers/base/soc.c
index b63f23e..0c5cf87 100644
--- a/drivers/base/soc.c
+++ b/drivers/base/soc.c
@@ -13,6 +13,7 @@
#include <linux/spinlock.h>
#include <linux/sys_soc.h>
#include <linux/err.h>
+#include <linux/glob.h>
static DEFINE_IDA(soc_ida);
@@ -159,3 +160,68 @@ static int __init soc_bus_register(void)
return bus_register(&soc_bus_type);
}
core_initcall(soc_bus_register);
+
+static int soc_device_match_one(struct device *dev, void *arg)
+{
+ struct soc_device *soc_dev = container_of(dev, struct soc_device, dev);
+ const struct soc_device_attribute *match = arg;
+
+ if (match->machine &&
+ !glob_match(match->machine, soc_dev->attr->machine))
+ return 0;
+
+ if (match->family &&
+ !glob_match(match->family, soc_dev->attr->family))
+ return 0;
+
+ if (match->revision &&
+ !glob_match(match->revision, soc_dev->attr->revision))
+ return 0;
+
+ if (match->soc_id &&
+ !glob_match(match->soc_id, soc_dev->attr->soc_id))
+ return 0;
+
+ return 1;
+}
+
+/*
+ * soc_device_match - identify the SoC in the machine
+ * @matches: zero-terminated array of possible matches
+ *
+ * returns the first matching entry of the argument array, or NULL
+ * if none of them match.
+ *
+ * This function is meant as a helper in place of of_match_node()
+ * in cases where either no device tree is available or the information
+ * in a device node is insufficient to identify a particular variant
+ * by its compatible strings or other properties. For new devices,
+ * the DT binding should always provide unique compatible strings
+ * that allow the use of of_match_node() instead.
+ *
+ * The calling function can use the .data entry of the
+ * soc_device_attribute to pass a structure or function pointer for
+ * each entry.
+ */
+const struct soc_device_attribute *soc_device_match(
+ const struct soc_device_attribute *matches)
+{
+ int ret = 0;
+
+ if (!matches)
+ return NULL;
+
+ while (!ret) {
+ if (!(matches->machine || matches->family ||
+ matches->revision || matches->soc_id))
+ break;
+ ret = bus_for_each_dev(&soc_bus_type, NULL, (void *)matches,
+ soc_device_match_one);
+ if (!ret)
+ matches++;
+ else
+ return matches;
+ }
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(soc_device_match);
diff --git a/include/linux/sys_soc.h b/include/linux/sys_soc.h
index 2739ccb..9f5eb06 100644
--- a/include/linux/sys_soc.h
+++ b/include/linux/sys_soc.h
@@ -13,6 +13,7 @@ struct soc_device_attribute {
const char *family;
const char *revision;
const char *soc_id;
+ const void *data;
};
/**
@@ -34,4 +35,6 @@ void soc_device_unregister(struct soc_device *soc_dev);
*/
struct device *soc_device_to_device(struct soc_device *soc);
+const struct soc_device_attribute *soc_device_match(
+ const struct soc_device_attribute *matches);
#endif /* __SOC_BUS_H */
--
2.1.0.27.g96db324
^ permalink raw reply related
* [v15, 5/7] MAINTAINERS: add entry for Freescale SoC drivers
From: Yangbo Lu @ 2016-10-28 6:50 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Scott Wood, Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, Xiaobo Xie, Minghuan Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Qiang Zhao, Russell King,
Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA, Yangbo Lu, Rob Herring,
Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Kumar Gala,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1477637418-38938-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Add maintainer entry for Freescale SoC drivers including
the QE library and the GUTS driver now. Also add maintainer
for QE library.
Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
Acked-by: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
Acked-by: Qiang Zhao <qiang.zhao-3arQi8VN3Tc@public.gmane.org>
---
Changes for v8:
- Added this patch
Changes for v9:
- Added linux-arm mail list
- Removed GUTS driver entry
Changes for v10:
- Changed 'DRIVER' to 'DRIVERS'
- Added 'Acked-by' of Scott and Qiang
Changes for v11:
- None
Changes for v12:
- None
Changes for v13:
- None
Changes for v14:
- None
Changes for v15:
- None
---
MAINTAINERS | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index c72fa18..cf3aaee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5037,9 +5037,18 @@ S: Maintained
F: drivers/net/ethernet/freescale/fman
F: Documentation/devicetree/bindings/powerpc/fsl/fman.txt
+FREESCALE SOC DRIVERS
+M: Scott Wood <oss-fOR+EgIDQEHk1uMJSBkQmQ@public.gmane.org>
+L: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
+L: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
+S: Maintained
+F: drivers/soc/fsl/
+F: include/linux/fsl/
+
FREESCALE QUICC ENGINE LIBRARY
+M: Qiang Zhao <qiang.zhao-3arQi8VN3Tc@public.gmane.org>
L: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
-S: Orphan
+S: Maintained
F: drivers/soc/fsl/qe/
F: include/soc/fsl/*qe*.h
F: include/soc/fsl/*ucc*.h
--
2.1.0.27.g96db324
^ permalink raw reply related
* [v15, 4/7] soc: fsl: add GUTS driver for QorIQ platforms
From: Yangbo Lu @ 2016-10-28 6:50 UTC (permalink / raw)
To: linux-mmc-u79uwXL29TY76Z2rM5mHXA,
ulf.hansson-QSEj5FYQhm4dnm+yROfE0A, Scott Wood, Arnd Bergmann
Cc: Mark Rutland, Greg Kroah-Hartman, Xiaobo Xie, Minghuan Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Qiang Zhao, Russell King,
Bhupesh Sharma, Jochen Friedrich, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA, Yangbo Lu, Rob Herring,
Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
netdev-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Leo Li,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA, Kumar Gala,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ
In-Reply-To: <1477637418-38938-1-git-send-email-yangbo.lu-3arQi8VN3Tc@public.gmane.org>
The global utilities block controls power management, I/O device
enabling, power-onreset(POR) configuration monitoring, alternate
function selection for multiplexed signals,and clock control.
This patch adds a driver to manage and access global utilities block.
Initially only reading SVR and registering soc device are supported.
Other guts accesses, such as reading RCW, should eventually be moved
into this driver as well.
Signed-off-by: Yangbo Lu <yangbo.lu-3arQi8VN3Tc@public.gmane.org>
---
Changes for v4:
- Added this patch
Changes for v5:
- Modified copyright info
- Changed MODULE_LICENSE to GPL
- Changed EXPORT_SYMBOL_GPL to EXPORT_SYMBOL
- Made FSL_GUTS user-invisible
- Added a complete compatible list for GUTS
- Stored guts info in file-scope variable
- Added mfspr() getting SVR
- Redefined GUTS APIs
- Called fsl_guts_init rather than using platform driver
- Removed useless parentheses
- Removed useless 'extern' key words
Changes for v6:
- Made guts thread safe in fsl_guts_init
Changes for v7:
- Removed 'ifdef' for function declaration in guts.h
Changes for v8:
- Fixes lines longer than 80 characters checkpatch issue
- Added 'Acked-by: Scott Wood'
Changes for v9:
- None
Changes for v10:
- None
Changes for v11:
- Changed to platform driver
Changes for v12:
- Removed "signed-off-by: Scott"
- Defined fsl_soc_die_attr struct array instead of
soc_device_attribute
- Re-designed soc_device_attribute for QorIQ SoC
- Other minor fixes
Changes for v13:
- Rebased
- Removed text after 'bool' in Kconfig
- Removed ARCH ifdefs
- Added more bits for ls1021a mask
- Used devm
Changes for v14:
- Used devm_ioremap_resource
Changes for v15:
- Fixed error code for devm_ioremap_resource
---
drivers/soc/Kconfig | 3 +-
drivers/soc/fsl/Kconfig | 18 ++++
drivers/soc/fsl/Makefile | 1 +
drivers/soc/fsl/guts.c | 237 +++++++++++++++++++++++++++++++++++++++++++++++
include/linux/fsl/guts.h | 125 +++++++++++++++----------
5 files changed, 334 insertions(+), 50 deletions(-)
create mode 100644 drivers/soc/fsl/Kconfig
create mode 100644 drivers/soc/fsl/guts.c
diff --git a/drivers/soc/Kconfig b/drivers/soc/Kconfig
index e6e90e8..f31bceb 100644
--- a/drivers/soc/Kconfig
+++ b/drivers/soc/Kconfig
@@ -1,8 +1,7 @@
menu "SOC (System On Chip) specific Drivers"
source "drivers/soc/bcm/Kconfig"
-source "drivers/soc/fsl/qbman/Kconfig"
-source "drivers/soc/fsl/qe/Kconfig"
+source "drivers/soc/fsl/Kconfig"
source "drivers/soc/mediatek/Kconfig"
source "drivers/soc/qcom/Kconfig"
source "drivers/soc/rockchip/Kconfig"
diff --git a/drivers/soc/fsl/Kconfig b/drivers/soc/fsl/Kconfig
new file mode 100644
index 0000000..7a9fb9b
--- /dev/null
+++ b/drivers/soc/fsl/Kconfig
@@ -0,0 +1,18 @@
+#
+# Freescale SOC drivers
+#
+
+source "drivers/soc/fsl/qbman/Kconfig"
+source "drivers/soc/fsl/qe/Kconfig"
+
+config FSL_GUTS
+ bool
+ select SOC_BUS
+ help
+ The global utilities block controls power management, I/O device
+ enabling, power-onreset(POR) configuration monitoring, alternate
+ function selection for multiplexed signals,and clock control.
+ This driver is to manage and access global utilities block.
+ Initially only reading SVR and registering soc device are supported.
+ Other guts accesses, such as reading RCW, should eventually be moved
+ into this driver as well.
diff --git a/drivers/soc/fsl/Makefile b/drivers/soc/fsl/Makefile
index 75e1f53..44b3beb 100644
--- a/drivers/soc/fsl/Makefile
+++ b/drivers/soc/fsl/Makefile
@@ -5,3 +5,4 @@
obj-$(CONFIG_FSL_DPAA) += qbman/
obj-$(CONFIG_QUICC_ENGINE) += qe/
obj-$(CONFIG_CPM) += qe/
+obj-$(CONFIG_FSL_GUTS) += guts.o
diff --git a/drivers/soc/fsl/guts.c b/drivers/soc/fsl/guts.c
new file mode 100644
index 0000000..e564d1a
--- /dev/null
+++ b/drivers/soc/fsl/guts.c
@@ -0,0 +1,237 @@
+/*
+ * Freescale QorIQ Platforms GUTS Driver
+ *
+ * Copyright (C) 2016 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/of_fdt.h>
+#include <linux/sys_soc.h>
+#include <linux/of_address.h>
+#include <linux/platform_device.h>
+#include <linux/fsl/guts.h>
+#include <linux/fsl/svr.h>
+
+struct guts {
+ struct ccsr_guts __iomem *regs;
+ bool little_endian;
+};
+
+struct fsl_soc_die_attr {
+ char *die;
+ u32 svr;
+ u32 mask;
+};
+
+static struct guts *guts;
+static struct soc_device_attribute soc_dev_attr;
+static struct soc_device *soc_dev;
+
+
+/* SoC die attribute definition for QorIQ platform */
+static const struct fsl_soc_die_attr fsl_soc_die[] = {
+ /*
+ * Power Architecture-based SoCs T Series
+ */
+
+ /* Die: T4240, SoC: T4240/T4160/T4080 */
+ { .die = "T4240",
+ .svr = 0x82400000,
+ .mask = 0xfff00000,
+ },
+ /* Die: T1040, SoC: T1040/T1020/T1042/T1022 */
+ { .die = "T1040",
+ .svr = 0x85200000,
+ .mask = 0xfff00000,
+ },
+ /* Die: T2080, SoC: T2080/T2081 */
+ { .die = "T2080",
+ .svr = 0x85300000,
+ .mask = 0xfff00000,
+ },
+ /* Die: T1024, SoC: T1024/T1014/T1023/T1013 */
+ { .die = "T1024",
+ .svr = 0x85400000,
+ .mask = 0xfff00000,
+ },
+
+ /*
+ * ARM-based SoCs LS Series
+ */
+
+ /* Die: LS1043A, SoC: LS1043A/LS1023A */
+ { .die = "LS1043A",
+ .svr = 0x87920000,
+ .mask = 0xffff0000,
+ },
+ /* Die: LS2080A, SoC: LS2080A/LS2040A/LS2085A */
+ { .die = "LS2080A",
+ .svr = 0x87010000,
+ .mask = 0xff3f0000,
+ },
+ /* Die: LS1088A, SoC: LS1088A/LS1048A/LS1084A/LS1044A */
+ { .die = "LS1088A",
+ .svr = 0x87030000,
+ .mask = 0xff3f0000,
+ },
+ /* Die: LS1012A, SoC: LS1012A */
+ { .die = "LS1012A",
+ .svr = 0x87040000,
+ .mask = 0xffff0000,
+ },
+ /* Die: LS1046A, SoC: LS1046A/LS1026A */
+ { .die = "LS1046A",
+ .svr = 0x87070000,
+ .mask = 0xffff0000,
+ },
+ /* Die: LS2088A, SoC: LS2088A/LS2048A/LS2084A/LS2044A */
+ { .die = "LS2088A",
+ .svr = 0x87090000,
+ .mask = 0xff3f0000,
+ },
+ /* Die: LS1021A, SoC: LS1021A/LS1020A/LS1022A */
+ { .die = "LS1021A",
+ .svr = 0x87000000,
+ .mask = 0xfff70000,
+ },
+ { },
+};
+
+static const struct fsl_soc_die_attr *fsl_soc_die_match(
+ u32 svr, const struct fsl_soc_die_attr *matches)
+{
+ while (matches->svr) {
+ if (matches->svr == (svr & matches->mask))
+ return matches;
+ matches++;
+ };
+ return NULL;
+}
+
+u32 fsl_guts_get_svr(void)
+{
+ u32 svr = 0;
+
+ if (!guts || !guts->regs)
+ return svr;
+
+ if (guts->little_endian)
+ svr = ioread32(&guts->regs->svr);
+ else
+ svr = ioread32be(&guts->regs->svr);
+
+ return svr;
+}
+EXPORT_SYMBOL(fsl_guts_get_svr);
+
+static int fsl_guts_probe(struct platform_device *pdev)
+{
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ const struct fsl_soc_die_attr *soc_die;
+ const char *machine;
+ u32 svr;
+
+ /* Initialize guts */
+ guts = devm_kzalloc(dev, sizeof(*guts), GFP_KERNEL);
+ if (!guts)
+ return -ENOMEM;
+
+ guts->little_endian = of_property_read_bool(np, "little-endian");
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ guts->regs = devm_ioremap_resource(dev, res);
+ if (IS_ERR(guts->regs))
+ return PTR_ERR(guts->regs);
+
+ /* Register soc device */
+ machine = of_flat_dt_get_machine_name();
+ if (machine)
+ soc_dev_attr.machine = devm_kstrdup(dev, machine, GFP_KERNEL);
+
+ svr = fsl_guts_get_svr();
+ soc_die = fsl_soc_die_match(svr, fsl_soc_die);
+ if (soc_die) {
+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL,
+ "QorIQ %s", soc_die->die);
+ } else {
+ soc_dev_attr.family = devm_kasprintf(dev, GFP_KERNEL, "QorIQ");
+ }
+ soc_dev_attr.soc_id = devm_kasprintf(dev, GFP_KERNEL,
+ "svr:0x%08x", svr);
+ soc_dev_attr.revision = devm_kasprintf(dev, GFP_KERNEL, "%d.%d",
+ SVR_MAJ(svr), SVR_MIN(svr));
+
+ soc_dev = soc_device_register(&soc_dev_attr);
+ if (IS_ERR(soc_dev))
+ return PTR_ERR(soc_dev);
+
+ pr_info("Machine: %s\n", soc_dev_attr.machine);
+ pr_info("SoC family: %s\n", soc_dev_attr.family);
+ pr_info("SoC ID: %s, Revision: %s\n",
+ soc_dev_attr.soc_id, soc_dev_attr.revision);
+ return 0;
+}
+
+static int fsl_guts_remove(struct platform_device *dev)
+{
+ soc_device_unregister(soc_dev);
+ return 0;
+}
+
+/*
+ * Table for matching compatible strings, for device tree
+ * guts node, for Freescale QorIQ SOCs.
+ */
+static const struct of_device_id fsl_guts_of_match[] = {
+ { .compatible = "fsl,qoriq-device-config-1.0", },
+ { .compatible = "fsl,qoriq-device-config-2.0", },
+ { .compatible = "fsl,p1010-guts", },
+ { .compatible = "fsl,p1020-guts", },
+ { .compatible = "fsl,p1021-guts", },
+ { .compatible = "fsl,p1022-guts", },
+ { .compatible = "fsl,p1023-guts", },
+ { .compatible = "fsl,p2020-guts", },
+ { .compatible = "fsl,bsc9131-guts", },
+ { .compatible = "fsl,bsc9132-guts", },
+ { .compatible = "fsl,mpc8536-guts", },
+ { .compatible = "fsl,mpc8544-guts", },
+ { .compatible = "fsl,mpc8548-guts", },
+ { .compatible = "fsl,mpc8568-guts", },
+ { .compatible = "fsl,mpc8569-guts", },
+ { .compatible = "fsl,mpc8572-guts", },
+ { .compatible = "fsl,ls1021a-dcfg", },
+ { .compatible = "fsl,ls1043a-dcfg", },
+ { .compatible = "fsl,ls2080a-dcfg", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, fsl_guts_of_match);
+
+static struct platform_driver fsl_guts_driver = {
+ .driver = {
+ .name = "fsl-guts",
+ .of_match_table = fsl_guts_of_match,
+ },
+ .probe = fsl_guts_probe,
+ .remove = fsl_guts_remove,
+};
+
+static int __init fsl_guts_init(void)
+{
+ return platform_driver_register(&fsl_guts_driver);
+}
+core_initcall(fsl_guts_init);
+
+static void __exit fsl_guts_exit(void)
+{
+ platform_driver_unregister(&fsl_guts_driver);
+}
+module_exit(fsl_guts_exit);
diff --git a/include/linux/fsl/guts.h b/include/linux/fsl/guts.h
index 649e917..3efa3b8 100644
--- a/include/linux/fsl/guts.h
+++ b/include/linux/fsl/guts.h
@@ -29,83 +29,112 @@
* #ifdefs.
*/
struct ccsr_guts {
- __be32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
- __be32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
- __be32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and Control Register */
- __be32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
- __be32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
- __be32 pordevsr2; /* 0x.0014 - POR device status register 2 */
+ u32 porpllsr; /* 0x.0000 - POR PLL Ratio Status Register */
+ u32 porbmsr; /* 0x.0004 - POR Boot Mode Status Register */
+ u32 porimpscr; /* 0x.0008 - POR I/O Impedance Status and
+ * Control Register
+ */
+ u32 pordevsr; /* 0x.000c - POR I/O Device Status Register */
+ u32 pordbgmsr; /* 0x.0010 - POR Debug Mode Status Register */
+ u32 pordevsr2; /* 0x.0014 - POR device status register 2 */
u8 res018[0x20 - 0x18];
- __be32 porcir; /* 0x.0020 - POR Configuration Information Register */
+ u32 porcir; /* 0x.0020 - POR Configuration Information
+ * Register
+ */
u8 res024[0x30 - 0x24];
- __be32 gpiocr; /* 0x.0030 - GPIO Control Register */
+ u32 gpiocr; /* 0x.0030 - GPIO Control Register */
u8 res034[0x40 - 0x34];
- __be32 gpoutdr; /* 0x.0040 - General-Purpose Output Data Register */
+ u32 gpoutdr; /* 0x.0040 - General-Purpose Output Data
+ * Register
+ */
u8 res044[0x50 - 0x44];
- __be32 gpindr; /* 0x.0050 - General-Purpose Input Data Register */
+ u32 gpindr; /* 0x.0050 - General-Purpose Input Data
+ * Register
+ */
u8 res054[0x60 - 0x54];
- __be32 pmuxcr; /* 0x.0060 - Alternate Function Signal Multiplex Control */
- __be32 pmuxcr2; /* 0x.0064 - Alternate function signal multiplex control 2 */
- __be32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
+ u32 pmuxcr; /* 0x.0060 - Alternate Function Signal
+ * Multiplex Control
+ */
+ u32 pmuxcr2; /* 0x.0064 - Alternate function signal
+ * multiplex control 2
+ */
+ u32 dmuxcr; /* 0x.0068 - DMA Mux Control Register */
u8 res06c[0x70 - 0x6c];
- __be32 devdisr; /* 0x.0070 - Device Disable Control */
+ u32 devdisr; /* 0x.0070 - Device Disable Control */
#define CCSR_GUTS_DEVDISR_TB1 0x00001000
#define CCSR_GUTS_DEVDISR_TB0 0x00004000
- __be32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
+ u32 devdisr2; /* 0x.0074 - Device Disable Control 2 */
u8 res078[0x7c - 0x78];
- __be32 pmjcr; /* 0x.007c - 4 Power Management Jog Control Register */
- __be32 powmgtcsr; /* 0x.0080 - Power Management Status and Control Register */
- __be32 pmrccr; /* 0x.0084 - Power Management Reset Counter Configuration Register */
- __be32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter Configuration Register */
- __be32 pmcdr; /* 0x.008c - 4Power management clock disable register */
- __be32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
- __be32 rstrscr; /* 0x.0094 - Reset Request Status and Control Register */
- __be32 ectrstcr; /* 0x.0098 - Exception reset control register */
- __be32 autorstsr; /* 0x.009c - Automatic reset status register */
- __be32 pvr; /* 0x.00a0 - Processor Version Register */
- __be32 svr; /* 0x.00a4 - System Version Register */
+ u32 pmjcr; /* 0x.007c - 4 Power Management Jog Control
+ * Register
+ */
+ u32 powmgtcsr; /* 0x.0080 - Power Management Status and
+ * Control Register
+ */
+ u32 pmrccr; /* 0x.0084 - Power Management Reset Counter
+ * Configuration Register
+ */
+ u32 pmpdccr; /* 0x.0088 - Power Management Power Down Counter
+ * Configuration Register
+ */
+ u32 pmcdr; /* 0x.008c - 4Power management clock disable
+ * register
+ */
+ u32 mcpsumr; /* 0x.0090 - Machine Check Summary Register */
+ u32 rstrscr; /* 0x.0094 - Reset Request Status and
+ * Control Register
+ */
+ u32 ectrstcr; /* 0x.0098 - Exception reset control register */
+ u32 autorstsr; /* 0x.009c - Automatic reset status register */
+ u32 pvr; /* 0x.00a0 - Processor Version Register */
+ u32 svr; /* 0x.00a4 - System Version Register */
u8 res0a8[0xb0 - 0xa8];
- __be32 rstcr; /* 0x.00b0 - Reset Control Register */
+ u32 rstcr; /* 0x.00b0 - Reset Control Register */
u8 res0b4[0xc0 - 0xb4];
- __be32 iovselsr; /* 0x.00c0 - I/O voltage select status register
+ u32 iovselsr; /* 0x.00c0 - I/O voltage select status register
Called 'elbcvselcr' on 86xx SOCs */
u8 res0c4[0x100 - 0xc4];
- __be32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
+ u32 rcwsr[16]; /* 0x.0100 - Reset Control Word Status registers
There are 16 registers */
u8 res140[0x224 - 0x140];
- __be32 iodelay1; /* 0x.0224 - IO delay control register 1 */
- __be32 iodelay2; /* 0x.0228 - IO delay control register 2 */
+ u32 iodelay1; /* 0x.0224 - IO delay control register 1 */
+ u32 iodelay2; /* 0x.0228 - IO delay control register 2 */
u8 res22c[0x604 - 0x22c];
- __be32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
+ u32 pamubypenr; /* 0x.604 - PAMU bypass enable register */
u8 res608[0x800 - 0x608];
- __be32 clkdvdr; /* 0x.0800 - Clock Divide Register */
+ u32 clkdvdr; /* 0x.0800 - Clock Divide Register */
u8 res804[0x900 - 0x804];
- __be32 ircr; /* 0x.0900 - Infrared Control Register */
+ u32 ircr; /* 0x.0900 - Infrared Control Register */
u8 res904[0x908 - 0x904];
- __be32 dmacr; /* 0x.0908 - DMA Control Register */
+ u32 dmacr; /* 0x.0908 - DMA Control Register */
u8 res90c[0x914 - 0x90c];
- __be32 elbccr; /* 0x.0914 - eLBC Control Register */
+ u32 elbccr; /* 0x.0914 - eLBC Control Register */
u8 res918[0xb20 - 0x918];
- __be32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
- __be32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
- __be32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
+ u32 ddr1clkdr; /* 0x.0b20 - DDR1 Clock Disable Register */
+ u32 ddr2clkdr; /* 0x.0b24 - DDR2 Clock Disable Register */
+ u32 ddrclkdr; /* 0x.0b28 - DDR Clock Disable Register */
u8 resb2c[0xe00 - 0xb2c];
- __be32 clkocr; /* 0x.0e00 - Clock Out Select Register */
+ u32 clkocr; /* 0x.0e00 - Clock Out Select Register */
u8 rese04[0xe10 - 0xe04];
- __be32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
+ u32 ddrdllcr; /* 0x.0e10 - DDR DLL Control Register */
u8 rese14[0xe20 - 0xe14];
- __be32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
- __be32 cpfor; /* 0x.0e24 - L2 charge pump fuse override register */
+ u32 lbcdllcr; /* 0x.0e20 - LBC DLL Control Register */
+ u32 cpfor; /* 0x.0e24 - L2 charge pump fuse override
+ * register
+ */
u8 rese28[0xf04 - 0xe28];
- __be32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
- __be32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
+ u32 srds1cr0; /* 0x.0f04 - SerDes1 Control Register 0 */
+ u32 srds1cr1; /* 0x.0f08 - SerDes1 Control Register 0 */
u8 resf0c[0xf2c - 0xf0c];
- __be32 itcr; /* 0x.0f2c - Internal transaction control register */
+ u32 itcr; /* 0x.0f2c - Internal transaction control
+ * register
+ */
u8 resf30[0xf40 - 0xf30];
- __be32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
- __be32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
+ u32 srds2cr0; /* 0x.0f40 - SerDes2 Control Register 0 */
+ u32 srds2cr1; /* 0x.0f44 - SerDes2 Control Register 0 */
} __attribute__ ((packed));
+u32 fsl_guts_get_svr(void);
/* Alternate function signal multiplex control */
#define MPC85xx_PMUXCR_QE(x) (0x8000 >> (x))
--
2.1.0.27.g96db324
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