* Re: [PATCH 1/3] dt-bindings: firmware: scm: Add MSM8996 DT bindings
From: Rob Herring @ 2016-10-31 6:23 UTC (permalink / raw)
To: Sarangdhar Joshi
Cc: Andy Gross, David Brown, Mark Rutland, Catalin Marinas,
Will Deacon, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Bjorn Andersson,
Jordan Crouse, Stephen Boyd, Trilok Soni
In-Reply-To: <1477699729-18451-2-git-send-email-spjoshi-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Fri, Oct 28, 2016 at 05:08:47PM -0700, Sarangdhar Joshi wrote:
> Add SCM DT bindings for Qualcomm's MSM8996 platform.
>
> Signed-off-by: Sarangdhar Joshi <spjoshi-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
> Documentation/devicetree/bindings/firmware/qcom,scm.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v3 1/2] drm/bridge: dumb-vga-dac: Support a VDD regulator supply
From: Rob Herring @ 2016-10-31 6:28 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: Maxime Ripard, David Airlie, Mark Rutland,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
In-Reply-To: <20161029110611.28951-2-wens-jdAy2FN1RRM@public.gmane.org>
On Sat, Oct 29, 2016 at 07:06:10PM +0800, Chen-Yu Tsai wrote:
> Some dumb VGA DACs are active components which require external power.
> Add support for specifying a regulator as its power supply.
>
> Signed-off-by: Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> ---
> .../bindings/display/bridge/dumb-vga-dac.txt | 2 ++
For the binding,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
One code comment below...
> drivers/gpu/drm/bridge/dumb-vga-dac.c | 35 ++++++++++++++++++++++
> 2 files changed, 37 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> index 003bc246a270..164cbb15f04c 100644
> --- a/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> +++ b/Documentation/devicetree/bindings/display/bridge/dumb-vga-dac.txt
> @@ -16,6 +16,8 @@ graph bindings specified in Documentation/devicetree/bindings/graph.txt.
> - Video port 0 for RGB input
> - Video port 1 for VGA output
>
> +Optional properties:
> +- vdd-supply: Power supply for DAC
>
> Example
> -------
> diff --git a/drivers/gpu/drm/bridge/dumb-vga-dac.c b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> index afec232185a7..59781e031220 100644
> --- a/drivers/gpu/drm/bridge/dumb-vga-dac.c
> +++ b/drivers/gpu/drm/bridge/dumb-vga-dac.c
> @@ -12,6 +12,7 @@
>
> #include <linux/module.h>
> #include <linux/of_graph.h>
> +#include <linux/regulator/consumer.h>
>
> #include <drm/drmP.h>
> #include <drm/drm_atomic_helper.h>
> @@ -23,6 +24,7 @@ struct dumb_vga {
> struct drm_connector connector;
>
> struct i2c_adapter *ddc;
> + struct regulator *vdd;
> };
>
> static inline struct dumb_vga *
> @@ -124,8 +126,33 @@ static int dumb_vga_attach(struct drm_bridge *bridge)
> return 0;
> }
>
> +static void dumb_vga_enable(struct drm_bridge *bridge)
> +{
> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
> + int ret;
> +
> + if (!IS_ERR(vga->vdd)) {
if (IS_ERR())
return;
...will save some intentation.
> + ret = regulator_enable(vga->vdd);
> +
> + if (ret) {
> + DRM_ERROR("Failed to enable vdd regulator: %d\n", ret);
> + return;
> + }
> + }
> +}
> +
> +static void dumb_vga_disable(struct drm_bridge *bridge)
> +{
> + struct dumb_vga *vga = drm_bridge_to_dumb_vga(bridge);
> +
> + if (!IS_ERR(vga->vdd))
> + regulator_disable(vga->vdd);
> +}
> +
> static const struct drm_bridge_funcs dumb_vga_bridge_funcs = {
> .attach = dumb_vga_attach,
> + .enable = dumb_vga_enable,
> + .disable = dumb_vga_disable,
> };
>
> static struct i2c_adapter *dumb_vga_retrieve_ddc(struct device *dev)
> @@ -169,6 +196,14 @@ static int dumb_vga_probe(struct platform_device *pdev)
> return -ENOMEM;
> platform_set_drvdata(pdev, vga);
>
> + vga->vdd = devm_regulator_get_optional(&pdev->dev, "vdd");
> + if (IS_ERR(vga->vdd)) {
> + ret = PTR_ERR(vga->vdd);
> + if (ret == -EPROBE_DEFER)
> + return -EPROBE_DEFER;
> + dev_dbg(&pdev->dev, "No vdd regulator found: %d\n", ret);
> + }
> +
> vga->ddc = dumb_vga_retrieve_ddc(&pdev->dev);
> if (IS_ERR(vga->ddc)) {
> if (PTR_ERR(vga->ddc) == -ENODEV) {
> --
> 2.9.3
>
^ permalink raw reply
* Re: [PATCH v4 1/2] of: Add vendor prefix for Lattice Semiconductor
From: Rob Herring @ 2016-10-31 6:29 UTC (permalink / raw)
To: Joel Holdsworth
Cc: atull, moritz.fischer, devicetree, linux-kernel, linux-spi
In-Reply-To: <1477776746-3678-1-git-send-email-joel@airwebreathe.org.uk>
On Sat, Oct 29, 2016 at 03:32:25PM -0600, Joel Holdsworth wrote:
> ---
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 2/2] fpga: Add support for Lattice iCE40 FPGAs
From: Rob Herring @ 2016-10-31 6:33 UTC (permalink / raw)
To: Joel Holdsworth
Cc: atull-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-spi-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477776746-3678-2-git-send-email-joel-IJEoVVyKhCJXvIrf17iDB/XRex20P6io@public.gmane.org>
On Sat, Oct 29, 2016 at 03:32:26PM -0600, Joel Holdsworth wrote:
> The Lattice iCE40 is a family of FPGAs with a minimalistic architecture
> and very regular structure, designed for low-cost, high-volume consumer
> and system applications.
>
> This patch adds support to the FPGA manager for configuring the SRAM of
> iCE40LM, iCE40LP, iCE40HX, iCE40 Ultra, iCE40 UltraLite and iCE40
> UltraPlus devices, through slave SPI.
>
> The iCE40 family is notable because it is the first FPGA family to have
> complete reverse engineered bit-stream documentation for the iCE40LP and
> iCE40HX devices. Furthermore, there is now a Free Software Verilog
> synthesis tool-chain: the "IceStorm" tool-chain.
>
> This project is the work of Clifford Wolf, who is the maintainer of
> Yosys Verilog RTL synthesis framework, and Mathias Lasser, with notable
> contributions from "Cotton Seed", the main author of "arachne-pnr"; a
> place-and-route tool for iCE40 FPGAs.
>
> Having a Free Software synthesis tool-chain offers interesting
> opportunities for embedded devices that are able reconfigure themselves
> with open firmware that is generated on the device itself. For example
> a mobile device might have an application processor with an iCE40 FPGA
> attached, which implements slave devices, or through which the processor
> communicates with other devices through the FPGA fabric.
>
> A kernel driver for the iCE40 is useful, because in some cases, the FPGA
> may need to be configured before other devices can be accessed.
>
> An example of such a device is the icoBoard; a RaspberryPI HAT which
> features an iCE40HX8K with a 1 or 8 MBit SRAM and ports for
> Digilent-compatible PMOD modules. A PMOD module may contain a device
> with which the kernel communicates, via the FPGA.
> ---
> .../bindings/fpga/lattice-ice40-fpga-mgr.txt | 23 +++
It's preferred that bindings are a separate patch.
> drivers/fpga/Kconfig | 6 +
> drivers/fpga/Makefile | 1 +
> drivers/fpga/ice40-spi.c | 219 +++++++++++++++++++++
> 4 files changed, 249 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> create mode 100644 drivers/fpga/ice40-spi.c
>
> diff --git a/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> new file mode 100644
> index 0000000..3d2917c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/fpga/lattice-ice40-fpga-mgr.txt
> @@ -0,0 +1,23 @@
> +Lattice iCE40 FPGA Manager
> +
> +Required properties:
> +- compatible: should contain "lattice,ice40-fpga-mgr"
> +- reg: SPI chip select
> +- spi-max-frequency: Maximum SPI frequency (>=1000000, <=25000000)
> +- cdone-gpio: GPIO connected to CDONE pin
-gpios is preferred.
Please state direction and polarity.
> +- creset_b-gpio: GPIO connected to CRESET_B pin. Note that CRESET_B is
Don't use '_'. In this case, I'd just do cresetb-gpios.
> + treated as an active-low output because the signal is
> + treated as an enable signal, rather than a reset. This
Though for enable signals, enable-gpios is fairly standard even if that
deviates from the pin name.
> + is necessary because the FPGA will enter Master SPI
> + mode and drive SCK with a clock signal, potentially
> + jamming other devices on the bus, unless CRESET_B is
> + held high until the firmware is loaded.
> +
> +Example:
> + ice40: ice40@0 {
> + compatible = "lattice,ice40-fpga-mgr";
> + reg = <0>;
> + spi-max-frequency = <1000000>;
> + cdone-gpio = <&gpio 24 GPIO_ACTIVE_HIGH>;
> + creset_b-gpio = <&gpio 22 GPIO_ACTIVE_LOW>;
> + };
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^ permalink raw reply
* Re: [PATCH] clk: cdce925: add support for CDCE913, CDCE937, and CDCE949
From: Rob Herring @ 2016-10-31 6:34 UTC (permalink / raw)
To: Akinobu Mita
Cc: linux-clk, devicetree, Mike Looijmans, Michael Turquette,
Stephen Boyd
In-Reply-To: <1477848637-5151-1-git-send-email-akinobu.mita@gmail.com>
On Mon, Oct 31, 2016 at 02:30:37AM +0900, Akinobu Mita wrote:
> The CDCE925 is a member of the CDCE(L)9xx programmable clock generator
> family. There are also CDCE913, CDCE937, CDCE949 which have different
> number of PLLs and outputs.
>
> The clk-cdce925 driver supports only CDCE925 in the family. This adds
> support for the CDCE913, CDCE937, CDCE949, too.
>
> Signed-off-by: Akinobu Mita <akinobu.mita@gmail.com>
> Cc: Mike Looijmans <mike.looijmans@topic.nl>
> Cc: Michael Turquette <mturquette@linaro.org>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> ---
> .../devicetree/bindings/clock/ti,cdce925.txt | 15 ++-
Acked-by: Rob Herring <robh@kernel.org>
> drivers/clk/Kconfig | 11 ++-
> drivers/clk/clk-cdce925.c | 106 ++++++++++++++++-----
> 3 files changed, 99 insertions(+), 33 deletions(-)
^ permalink raw reply
* Re: [PATCH v2 2/7] Documentation: dt: Add binding info for jz4740-rtc driver
From: Rob Herring @ 2016-10-31 6:39 UTC (permalink / raw)
To: Paul Cercueil
Cc: rtc-linux-/JYPxA39Uh5TLH3MbocFFw, Alessandro Zummo,
Alexandre Belloni, Mark Rutland, Ralf Baechle, Maarten ter Huurne,
Lars-Peter Clausen, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mips-6z/3iImG2C8G8FEW9MqTrA
In-Reply-To: <20161030230247.20538-3-paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
On Mon, Oct 31, 2016 at 12:02:42AM +0100, Paul Cercueil wrote:
> This commit adds documentation for the device-tree bindings of the
> jz4740-rtc driver, which supports the RTC unit present in the JZ4740 and
> JZ4780 SoCs from Ingenic.
>
> Signed-off-by: Paul Cercueil <paul-icTtO2rgO2OTuSrc4Mpeew@public.gmane.org>
> Acked-by: Maarten ter Huurne <maarten-Ph2Y2OKCxY1M656bX5wj8A@public.gmane.org>
> ---
> .../devicetree/bindings/rtc/ingenic,jz4740-rtc.txt | 37 ++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/rtc/ingenic,jz4740-rtc.txt
>
> v2:
> - Remove 'interrupt-parent' of the list of required properties
> - Add the -msec suffix for the DT entries that represent time
Sorry, I told you the wrong suffix. It should be '-ms' as documented in
.../bindings/property-units.txt. I never can remember which is why I
wrote the doc to begin with. With that fix,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v14 1/4] clk: mediatek: Add MT2701 clock support
From: James Liao @ 2016-10-31 6:49 UTC (permalink / raw)
To: Stephen Boyd
Cc: Erin Lo, Matthias Brugger, Mike Turquette, Rob Herring,
Arnd Bergmann, Sascha Hauer, Daniel Kurtz, Philipp Zabel,
devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
linux-clk, srv_heupstream, ms.chen, robert.chou, Shunli Wang
In-Reply-To: <20161028011753.GS26139@codeaurora.org>
Hi Stephen,
On Thu, 2016-10-27 at 18:17 -0700, Stephen Boyd wrote:
> On 10/21, Erin Lo wrote:
> > diff --git a/drivers/clk/mediatek/clk-mt2701-bdp.c b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > new file mode 100644
> > index 0000000..dbf6ab2
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-bdp.c
> > @@ -0,0 +1,148 @@
> > +
> > +static int mtk_bdpsys_init(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_BDP_NR);
> > +
> > + mtk_clk_register_gates(node, bdp_clks, ARRAY_SIZE(bdp_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > + return r;
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_bdp[] = {
> > + { .compatible = "mediatek,mt2701-bdpsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt2701_bdp_probe(struct platform_device *pdev)
> > +{
> > + int r;
> > +
> > + r = mtk_bdpsys_init(pdev);
>
> Why not just put the contents of that function here? I don't see
> the point of this.
Because of some historical reasons, we keep mtk_bdpsys_init() for
changing init points between CLK_OF_DECLARE() and probe() more easily. I
can move all contents from mtk_bdpsys_init() here in next patch.
> > + if (r) {
> > + dev_err(&pdev->dev,
> > + "could not register clock provider: %s: %d\n",
> > + pdev->name, r);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_bdp_drv = {
> > + .probe = clk_mt2701_bdp_probe,
> > + .driver = {
> > + .name = "clk-mt2701-bdp",
> > + .of_match_table = of_match_clk_mt2701_bdp,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt2701_bdp_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt2701-eth.c b/drivers/clk/mediatek/clk-mt2701-eth.c
> > new file mode 100644
> > index 0000000..b2a71a4
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-eth.c
> > @@ -0,0 +1,90 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang <shunli.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt2701-clk.h>
> > +
> > +static const struct mtk_gate_regs eth_cg_regs = {
> > + .sta_ofs = 0x0030,
> > +};
> > +
> > +#define GATE_ETH(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = ð_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> > + }
> > +
> > +static const struct mtk_gate eth_clks[] = {
> > + GATE_ETH(CLK_ETHSYS_HSDMA, "hsdma_clk", "ethif_sel", 5),
> > + GATE_ETH(CLK_ETHSYS_ESW, "esw_clk", "ethpll_500m_ck", 6),
> > + GATE_ETH(CLK_ETHSYS_GP2, "gp2_clk", "trgpll", 7),
> > + GATE_ETH(CLK_ETHSYS_GP1, "gp1_clk", "ethpll_500m_ck", 8),
> > + GATE_ETH(CLK_ETHSYS_PCM, "pcm_clk", "ethif_sel", 11),
> > + GATE_ETH(CLK_ETHSYS_GDMA, "gdma_clk", "ethif_sel", 14),
> > + GATE_ETH(CLK_ETHSYS_I2S, "i2s_clk", "ethif_sel", 17),
> > + GATE_ETH(CLK_ETHSYS_CRYPTO, "crypto_clk", "ethif_sel", 29),
> > +};
> > +
> > +static int mtk_ethsys_init(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_ETHSYS_NR);
> > +
> > + mtk_clk_register_gates(node, eth_clks, ARRAY_SIZE(eth_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > + return r;
>
> Just return of_clk_add_provider() please.
I'll change it in next patch.
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_eth[] = {
> > + { .compatible = "mediatek,mt2701-ethsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt2701_eth_probe(struct platform_device *pdev)
> > +{
> > + int r;
> > +
> > + r = mtk_ethsys_init(pdev);
>
> Same comment.
Okay.
> > + if (r) {
> > + dev_err(&pdev->dev,
> > + "could not register clock provider: %s: %d\n",
> > + pdev->name, r);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_eth_drv = {
> > + .probe = clk_mt2701_eth_probe,
> > + .driver = {
> > + .name = "clk-mt2701-eth",
> > + .of_match_table = of_match_clk_mt2701_eth,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt2701_eth_drv);
> > diff --git a/drivers/clk/mediatek/clk-mt2701-hif.c b/drivers/clk/mediatek/clk-mt2701-hif.c
> > new file mode 100644
> > index 0000000..e2b0039
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701-hif.c
> > @@ -0,0 +1,87 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang <shunli.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt2701-clk.h>
> > +
> > +static const struct mtk_gate_regs hif_cg_regs = {
> > + .sta_ofs = 0x0030,
> > +};
> > +
> > +#define GATE_HIF(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &hif_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_no_setclr_inv, \
> > + }
> > +
> > +static const struct mtk_gate hif_clks[] = {
> > + GATE_HIF(CLK_HIFSYS_USB0PHY, "usb0_phy_clk", "ethpll_500m_ck", 21),
> > + GATE_HIF(CLK_HIFSYS_USB1PHY, "usb1_phy_clk", "ethpll_500m_ck", 22),
> > + GATE_HIF(CLK_HIFSYS_PCIE0, "pcie0_clk", "ethpll_500m_ck", 24),
> > + GATE_HIF(CLK_HIFSYS_PCIE1, "pcie1_clk", "ethpll_500m_ck", 25),
> > + GATE_HIF(CLK_HIFSYS_PCIE2, "pcie2_clk", "ethpll_500m_ck", 26),
> > +};
> > +
> > +static int mtk_hifsys_init(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_HIFSYS_NR);
> > +
> > + mtk_clk_register_gates(node, hif_clks, ARRAY_SIZE(hif_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > + return r;
>
> Just return of_clk_add_provider() please.
Okay.
> > +}
> > +
> > +static const struct of_device_id of_match_clk_mt2701_hif[] = {
> > + { .compatible = "mediatek,mt2701-hifsys", },
> > + {}
> > +};
> > +
> > +static int clk_mt2701_hif_probe(struct platform_device *pdev)
> > +{
> > + int r;
> > +
> > + r = mtk_hifsys_init(pdev);
>
> There's a pattern. Same comments apply for everything that uses
> this style.
I'll change them in next patch.
> > + if (r) {
> > + dev_err(&pdev->dev,
> > + "could not register clock provider: %s: %d\n",
> > + pdev->name, r);
> > + }
> > +
> > + return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_hif_drv = {
> > + .probe = clk_mt2701_hif_probe,
> > + .driver = {
> > + .name = "clk-mt2701-hif",
> > + .of_match_table = of_match_clk_mt2701_hif,
> > + },
> > +};
> > +
> > +builtin_platform_driver(clk_mt2701_hif_drv);
> [cut a bunch of same drivers]
> > diff --git a/drivers/clk/mediatek/clk-mt2701.c b/drivers/clk/mediatek/clk-mt2701.c
> > new file mode 100644
> > index 0000000..c225256
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt2701.c
> > @@ -0,0 +1,1046 @@
> > +/*
> > + * Copyright (c) 2014 MediaTek Inc.
> > + * Author: Shunli Wang <shunli.wang@mediatek.com>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2 as
> > + * published by the Free Software Foundation.
> > + *
> > + * This program is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + */
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/of.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +
> > +#include "clk-mtk.h"
> > +#include "clk-gate.h"
> > +
> > +#include <dt-bindings/clock/mt2701-clk.h>
> > +
> > +/*
> > + * For some clocks, we don't care what their actual rates are. And these
> > + * clocks may change their rate on different products or different scenarios.
> > + * So we model these clocks' rate as 0, to denote it's not an actual rate.
> > + */
> > +#define DUMMY_RATE 0
> > +
> > +static DEFINE_SPINLOCK(lock);
>
> Please name this something more mtk specific. mt2701_clk_lock?
Okay.
> > +
> > +static const struct mtk_fixed_clk top_fixed_clks[] = {
> > + FIXED_CLK(CLK_TOP_DPI, "dpi_ck", "clk26m",
> > + 108 * MHZ),
> > + FIXED_CLK(CLK_TOP_DMPLL, "dmpll_ck", "clk26m",
> > + 400 * MHZ),
> > + FIXED_CLK(CLK_TOP_VENCPLL, "vencpll_ck", "clk26m",
> > + 295750000),
> > + FIXED_CLK(CLK_TOP_HDMI_0_PIX340M, "hdmi_0_pix340m", "clk26m",
> > + 340 * MHZ),
> > + FIXED_CLK(CLK_TOP_HDMI_0_DEEP340M, "hdmi_0_deep340m", "clk26m",
> > + 340 * MHZ),
> > + FIXED_CLK(CLK_TOP_HDMI_0_PLL340M, "hdmi_0_pll340m", "clk26m",
> > + 340 * MHZ),
> > + FIXED_CLK(CLK_TOP_HDMITX_CLKDIG_CTS, "hdmitx_dig_cts", "clk26m",
> > + 300 * MHZ),
> > + FIXED_CLK(CLK_TOP_HADDS2_FB, "hadds2_fbclk", "clk26m",
> > + 27 * MHZ),
> > + FIXED_CLK(CLK_TOP_WBG_DIG_416M, "wbg_dig_ck_416m", "clk26m",
> > + 416 * MHZ),
> > + FIXED_CLK(CLK_TOP_DSI0_LNTC_DSI, "dsi0_lntc_dsi", "clk26m",
> > + 143 * MHZ),
> > + FIXED_CLK(CLK_TOP_HDMI_SCL_RX, "hdmi_scl_rx", "clk26m",
> > + 27 * MHZ),
> > + FIXED_CLK(CLK_TOP_AUD_EXT1, "aud_ext1", "clk26m",
> > + DUMMY_RATE),
> > + FIXED_CLK(CLK_TOP_AUD_EXT2, "aud_ext2", "clk26m",
> > + DUMMY_RATE),
> > + FIXED_CLK(CLK_TOP_NFI1X_PAD, "nfi1x_pad", "clk26m",
> > + DUMMY_RATE),
> > +};
> > +
> > +static const struct mtk_fixed_factor top_fixed_divs[] = {
> > + FACTOR(CLK_TOP_SYSPLL, "syspll_ck", "mainpll", 1, 1),
> > + FACTOR(CLK_TOP_SYSPLL_D2, "syspll_d2", "mainpll", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL_D3, "syspll_d3", "mainpll", 1, 3),
> > + FACTOR(CLK_TOP_SYSPLL_D5, "syspll_d5", "mainpll", 1, 5),
> > + FACTOR(CLK_TOP_SYSPLL_D7, "syspll_d7", "mainpll", 1, 7),
> > + FACTOR(CLK_TOP_SYSPLL1_D2, "syspll1_d2", "syspll_d2", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL1_D4, "syspll1_d4", "syspll_d2", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL1_D8, "syspll1_d8", "syspll_d2", 1, 8),
> > + FACTOR(CLK_TOP_SYSPLL1_D16, "syspll1_d16", "syspll_d2", 1, 16),
> > + FACTOR(CLK_TOP_SYSPLL2_D2, "syspll2_d2", "syspll_d3", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL2_D4, "syspll2_d4", "syspll_d3", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL2_D8, "syspll2_d8", "syspll_d3", 1, 8),
> > + FACTOR(CLK_TOP_SYSPLL3_D2, "syspll3_d2", "syspll_d5", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL3_D4, "syspll3_d4", "syspll_d5", 1, 4),
> > + FACTOR(CLK_TOP_SYSPLL4_D2, "syspll4_d2", "syspll_d7", 1, 2),
> > + FACTOR(CLK_TOP_SYSPLL4_D4, "syspll4_d4", "syspll_d7", 1, 4),
> > +
> > + FACTOR(CLK_TOP_UNIVPLL, "univpll_ck", "univpll", 1, 1),
> > + FACTOR(CLK_TOP_UNIVPLL_D2, "univpll_d2", "univpll", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL_D3, "univpll_d3", "univpll", 1, 3),
> > + FACTOR(CLK_TOP_UNIVPLL_D5, "univpll_d5", "univpll", 1, 5),
> > + FACTOR(CLK_TOP_UNIVPLL_D7, "univpll_d7", "univpll", 1, 7),
> > + FACTOR(CLK_TOP_UNIVPLL_D26, "univpll_d26", "univpll", 1, 26),
> > + FACTOR(CLK_TOP_UNIVPLL_D52, "univpll_d52", "univpll", 1, 52),
> > + FACTOR(CLK_TOP_UNIVPLL_D108, "univpll_d108", "univpll", 1, 108),
> > + FACTOR(CLK_TOP_USB_PHY48M, "usb_phy48m_ck", "univpll", 1, 26),
> > + FACTOR(CLK_TOP_UNIVPLL1_D2, "univpll1_d2", "univpll_d2", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL1_D4, "univpll1_d4", "univpll_d2", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL1_D8, "univpll1_d8", "univpll_d2", 1, 8),
> > + FACTOR(CLK_TOP_8BDAC, "8bdac_ck", "univpll_d2", 1, 1),
> > + FACTOR(CLK_TOP_UNIVPLL2_D2, "univpll2_d2", "univpll_d3", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL2_D4, "univpll2_d4", "univpll_d3", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL2_D8, "univpll2_d8", "univpll_d3", 1, 8),
> > + FACTOR(CLK_TOP_UNIVPLL2_D16, "univpll2_d16", "univpll_d3", 1, 16),
> > + FACTOR(CLK_TOP_UNIVPLL2_D32, "univpll2_d32", "univpll_d3", 1, 32),
> > + FACTOR(CLK_TOP_UNIVPLL3_D2, "univpll3_d2", "univpll_d5", 1, 2),
> > + FACTOR(CLK_TOP_UNIVPLL3_D4, "univpll3_d4", "univpll_d5", 1, 4),
> > + FACTOR(CLK_TOP_UNIVPLL3_D8, "univpll3_d8", "univpll_d5", 1, 8),
> > +
> > + FACTOR(CLK_TOP_MSDCPLL, "msdcpll_ck", "msdcpll", 1, 1),
> > + FACTOR(CLK_TOP_MSDCPLL_D2, "msdcpll_d2", "msdcpll", 1, 2),
> > + FACTOR(CLK_TOP_MSDCPLL_D4, "msdcpll_d4", "msdcpll", 1, 4),
> > + FACTOR(CLK_TOP_MSDCPLL_D8, "msdcpll_d8", "msdcpll", 1, 8),
> > +
> > + FACTOR(CLK_TOP_MMPLL, "mmpll_ck", "mmpll", 1, 1),
> > + FACTOR(CLK_TOP_MMPLL_D2, "mmpll_d2", "mmpll", 1, 2),
> > +
> > + FACTOR(CLK_TOP_DMPLL_D2, "dmpll_d2", "dmpll_ck", 1, 2),
> > + FACTOR(CLK_TOP_DMPLL_D4, "dmpll_d4", "dmpll_ck", 1, 4),
> > + FACTOR(CLK_TOP_DMPLL_X2, "dmpll_x2", "dmpll_ck", 1, 1),
> > +
> > + FACTOR(CLK_TOP_TVDPLL, "tvdpll_ck", "tvdpll", 1, 1),
> > + FACTOR(CLK_TOP_TVDPLL_D2, "tvdpll_d2", "tvdpll", 1, 2),
> > + FACTOR(CLK_TOP_TVDPLL_D4, "tvdpll_d4", "tvdpll", 1, 4),
> > +
> > + FACTOR(CLK_TOP_VDECPLL, "vdecpll_ck", "vdecpll", 1, 1),
> > + FACTOR(CLK_TOP_TVD2PLL, "tvd2pll_ck", "tvd2pll", 1, 1),
> > + FACTOR(CLK_TOP_TVD2PLL_D2, "tvd2pll_d2", "tvd2pll", 1, 2),
> > +
> > + FACTOR(CLK_TOP_MIPIPLL, "mipipll", "dpi_ck", 1, 1),
> > + FACTOR(CLK_TOP_MIPIPLL_D2, "mipipll_d2", "dpi_ck", 1, 2),
> > + FACTOR(CLK_TOP_MIPIPLL_D4, "mipipll_d4", "dpi_ck", 1, 4),
> > +
> > + FACTOR(CLK_TOP_HDMIPLL, "hdmipll_ck", "hdmitx_dig_cts", 1, 1),
> > + FACTOR(CLK_TOP_HDMIPLL_D2, "hdmipll_d2", "hdmitx_dig_cts", 1, 2),
> > + FACTOR(CLK_TOP_HDMIPLL_D3, "hdmipll_d3", "hdmitx_dig_cts", 1, 3),
> > +
> > + FACTOR(CLK_TOP_ARMPLL_1P3G, "armpll_1p3g_ck", "armpll", 1, 1),
> > +
> > + FACTOR(CLK_TOP_AUDPLL, "audpll", "audpll_sel", 1, 1),
> > + FACTOR(CLK_TOP_AUDPLL_D4, "audpll_d4", "audpll_sel", 1, 4),
> > + FACTOR(CLK_TOP_AUDPLL_D8, "audpll_d8", "audpll_sel", 1, 8),
> > + FACTOR(CLK_TOP_AUDPLL_D16, "audpll_d16", "audpll_sel", 1, 16),
> > + FACTOR(CLK_TOP_AUDPLL_D24, "audpll_d24", "audpll_sel", 1, 24),
> > +
> > + FACTOR(CLK_TOP_AUD1PLL_98M, "aud1pll_98m_ck", "aud1pll", 1, 3),
> > + FACTOR(CLK_TOP_AUD2PLL_90M, "aud2pll_90m_ck", "aud2pll", 1, 3),
> > + FACTOR(CLK_TOP_HADDS2PLL_98M, "hadds2pll_98m", "hadds2pll", 1, 3),
> > + FACTOR(CLK_TOP_HADDS2PLL_294M, "hadds2pll_294m", "hadds2pll", 1, 1),
> > + FACTOR(CLK_TOP_ETHPLL_500M, "ethpll_500m_ck", "ethpll", 1, 1),
> > + FACTOR(CLK_TOP_CLK26M_D8, "clk26m_d8", "clk26m", 1, 8),
> > + FACTOR(CLK_TOP_32K_INTERNAL, "32k_internal", "clk26m", 1, 793),
> > + FACTOR(CLK_TOP_32K_EXTERNAL, "32k_external", "rtc32k", 1, 1),
> > +};
> > +
> > +static const char * const axi_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "syspll_d5",
> > + "syspll1_d4",
> > + "univpll_d5",
> > + "univpll2_d2",
> > + "mmpll_d2",
> > + "dmpll_d2"
> > +};
> > +
> > +static const char * const mem_parents[] = {
> > + "clk26m",
> > + "dmpll_ck"
> > +};
> > +
> > +static const char * const ddrphycfg_parents[] = {
> > + "clk26m",
> > + "syspll1_d8"
> > +};
> > +
> > +static const char * const mm_parents[] = {
> > + "clk26m",
> > + "vencpll_ck",
> > + "syspll1_d2",
> > + "syspll1_d4",
> > + "univpll_d5",
> > + "univpll1_d2",
> > + "univpll2_d2",
> > + "dmpll_ck"
> > +};
> > +
> > +static const char * const pwm_parents[] = {
> > + "clk26m",
> > + "univpll2_d4",
> > + "univpll3_d2",
> > + "univpll1_d4",
> > +};
> > +
> > +static const char * const vdec_parents[] = {
> > + "clk26m",
> > + "vdecpll_ck",
> > + "syspll_d5",
> > + "syspll1_d4",
> > + "univpll_d5",
> > + "univpll2_d2",
> > + "vencpll_ck",
> > + "msdcpll_d2",
> > + "mmpll_d2"
> > +};
> > +
> > +static const char * const mfg_parents[] = {
> > + "clk26m",
> > + "mmpll_ck",
> > + "dmpll_x2_ck",
> > + "msdcpll_ck",
> > + "clk26m",
> > + "syspll_d3",
> > + "univpll_d3",
> > + "univpll1_d2"
> > +};
> > +
> > +static const char * const camtg_parents[] = {
> > + "clk26m",
> > + "univpll_d26",
> > + "univpll2_d2",
> > + "syspll3_d2",
> > + "syspll3_d4",
> > + "msdcpll_d2",
> > + "mmpll_d2"
> > +};
> > +
> > +static const char * const uart_parents[] = {
> > + "clk26m",
> > + "univpll2_d8"
> > +};
> > +
> > +static const char * const spi_parents[] = {
> > + "clk26m",
> > + "syspll3_d2",
> > + "syspll4_d2",
> > + "univpll2_d4",
> > + "univpll1_d8"
> > +};
> > +
> > +static const char * const usb20_parents[] = {
> > + "clk26m",
> > + "univpll1_d8",
> > + "univpll3_d4"
> > +};
> > +
> > +static const char * const msdc30_parents[] = {
> > + "clk26m",
> > + "msdcpll_d2",
> > + "syspll2_d2",
> > + "syspll1_d4",
> > + "univpll1_d4",
> > + "univpll2_d4"
> > +};
> > +
> > +static const char * const audio_parents[] = {
> > + "clk26m",
> > + "syspll1_d16"
> > +};
> > +
> > +static const char * const aud_intbus_parents[] = {
> > + "clk26m",
> > + "syspll1_d4",
> > + "syspll3_d2",
> > + "syspll4_d2",
> > + "univpll3_d2",
> > + "univpll2_d4"
> > +};
> > +
> > +static const char * const pmicspi_parents[] = {
> > + "clk26m",
> > + "syspll1_d8",
> > + "syspll2_d4",
> > + "syspll4_d2",
> > + "syspll3_d4",
> > + "syspll2_d8",
> > + "syspll1_d16",
> > + "univpll3_d4",
> > + "univpll_d26",
> > + "dmpll_d2",
> > + "dmpll_d4"
> > +};
> > +
> > +static const char * const scp_parents[] = {
> > + "clk26m",
> > + "syspll1_d8",
> > + "dmpll_d2",
> > + "dmpll_d4"
> > +};
> > +
> > +static const char * const dpi0_parents[] = {
> > + "clk26m",
> > + "mipipll",
> > + "mipipll_d2",
> > + "mipipll_d4",
> > + "clk26m",
> > + "tvdpll_ck",
> > + "tvdpll_d2",
> > + "tvdpll_d4"
> > +};
> > +
> > +static const char * const dpi1_parents[] = {
> > + "clk26m",
> > + "tvdpll_ck",
> > + "tvdpll_d2",
> > + "tvdpll_d4"
> > +};
> > +
> > +static const char * const tve_parents[] = {
> > + "clk26m",
> > + "mipipll",
> > + "mipipll_d2",
> > + "mipipll_d4",
> > + "clk26m",
> > + "tvdpll_ck",
> > + "tvdpll_d2",
> > + "tvdpll_d4"
> > +};
> > +
> > +static const char * const hdmi_parents[] = {
> > + "clk26m",
> > + "hdmipll_ck",
> > + "hdmipll_d2",
> > + "hdmipll_d3"
> > +};
> > +
> > +static const char * const apll_parents[] = {
> > + "clk26m",
> > + "audpll",
> > + "audpll_d4",
> > + "audpll_d8",
> > + "audpll_d16",
> > + "audpll_d24",
> > + "clk26m",
> > + "clk26m"
> > +};
> > +
> > +static const char * const rtc_parents[] = {
> > + "32k_internal",
> > + "32k_external",
> > + "clk26m",
> > + "univpll3_d8"
> > +};
> > +
> > +static const char * const nfi2x_parents[] = {
> > + "clk26m",
> > + "syspll2_d2",
> > + "syspll_d7",
> > + "univpll3_d2",
> > + "syspll2_d4",
> > + "univpll3_d4",
> > + "syspll4_d4",
> > + "clk26m"
> > +};
> > +
> > +static const char * const emmc_hclk_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "syspll1_d4",
> > + "syspll2_d2"
> > +};
> > +
> > +static const char * const flash_parents[] = {
> > + "clk26m_d8",
> > + "clk26m",
> > + "syspll2_d8",
> > + "syspll3_d4",
> > + "univpll3_d4",
> > + "syspll4_d2",
> > + "syspll2_d4",
> > + "univpll2_d4"
> > +};
> > +
> > +static const char * const di_parents[] = {
> > + "clk26m",
> > + "tvd2pll_ck",
> > + "tvd2pll_d2",
> > + "clk26m"
> > +};
> > +
> > +static const char * const nr_osd_parents[] = {
> > + "clk26m",
> > + "vencpll_ck",
> > + "syspll1_d2",
> > + "syspll1_d4",
> > + "univpll_d5",
> > + "univpll1_d2",
> > + "univpll2_d2",
> > + "dmpll_ck"
> > +};
> > +
> > +static const char * const hdmirx_bist_parents[] = {
> > + "clk26m",
> > + "syspll_d3",
> > + "clk26m",
> > + "syspll1_d16",
> > + "syspll4_d2",
> > + "syspll1_d4",
> > + "vencpll_ck",
> > + "clk26m"
> > +};
> > +
> > +static const char * const intdir_parents[] = {
> > + "clk26m",
> > + "mmpll_ck",
> > + "syspll_d2",
> > + "univpll_d2"
> > +};
> > +
> > +static const char * const asm_parents[] = {
> > + "clk26m",
> > + "univpll2_d4",
> > + "univpll2_d2",
> > + "syspll_d5"
> > +};
> > +
> > +static const char * const ms_card_parents[] = {
> > + "clk26m",
> > + "univpll3_d8",
> > + "syspll4_d4"
> > +};
> > +
> > +static const char * const ethif_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "syspll_d5",
> > + "syspll1_d4",
> > + "univpll_d5",
> > + "univpll1_d2",
> > + "dmpll_ck",
> > + "dmpll_d2"
> > +};
> > +
> > +static const char * const hdmirx_parents[] = {
> > + "clk26m",
> > + "univpll_d52"
> > +};
> > +
> > +static const char * const cmsys_parents[] = {
> > + "clk26m",
> > + "syspll1_d2",
> > + "univpll1_d2",
> > + "univpll_d5",
> > + "syspll_d5",
> > + "syspll2_d2",
> > + "syspll1_d4",
> > + "syspll3_d2",
> > + "syspll2_d4",
> > + "syspll1_d8",
> > + "clk26m",
> > + "clk26m",
> > + "clk26m",
> > + "clk26m",
> > + "clk26m"
> > +};
> > +
> > +static const char * const clk_8bdac_parents[] = {
> > + "32k_internal",
> > + "8bdac_ck",
> > + "clk26m",
> > + "clk26m"
> > +};
> > +
> > +static const char * const aud2dvd_parents[] = {
> > + "a1sys_hp_ck",
> > + "a2sys_hp_ck"
> > +};
> > +
> > +static const char * const padmclk_parents[] = {
> > + "clk26m",
> > + "univpll_d26",
> > + "univpll_d52",
> > + "univpll_d108",
> > + "univpll2_d8",
> > + "univpll2_d16",
> > + "univpll2_d32"
> > +};
> > +
> > +static const char * const aud_mux_parents[] = {
> > + "clk26m",
> > + "aud1pll_98m_ck",
> > + "aud2pll_90m_ck",
> > + "hadds2pll_98m",
> > + "audio_ext1_ck",
> > + "audio_ext2_ck"
> > +};
> > +
> > +static const char * const aud_src_parents[] = {
> > + "aud_mux1_sel",
> > + "aud_mux2_sel"
> > +};
> > +
> > +static const char * const cpu_parents[] = {
> > + "clk26m",
> > + "armpll",
> > + "mainpll",
> > + "mmpll"
> > +};
> > +
> > +static const struct mtk_composite top_muxes[] = {
> > + MUX_GATE_FLAGS(CLK_TOP_AXI_SEL, "axi_sel", axi_parents,
> > + 0x0040, 0, 3, 7, CLK_IS_CRITICAL),
> > + MUX_GATE_FLAGS(CLK_TOP_MEM_SEL, "mem_sel", mem_parents,
> > + 0x0040, 8, 1, 15, CLK_IS_CRITICAL),
> > + MUX_GATE_FLAGS(CLK_TOP_DDRPHYCFG_SEL, "ddrphycfg_sel",
> > + ddrphycfg_parents, 0x0040, 16, 1, 23, CLK_IS_CRITICAL),
> > + MUX_GATE(CLK_TOP_MM_SEL, "mm_sel", mm_parents,
> > + 0x0040, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_PWM_SEL, "pwm_sel", pwm_parents,
> > + 0x0050, 0, 2, 7),
> > + MUX_GATE(CLK_TOP_VDEC_SEL, "vdec_sel", vdec_parents,
> > + 0x0050, 8, 4, 15),
> > + MUX_GATE(CLK_TOP_MFG_SEL, "mfg_sel", mfg_parents,
> > + 0x0050, 16, 3, 23),
> > + MUX_GATE(CLK_TOP_CAMTG_SEL, "camtg_sel", camtg_parents,
> > + 0x0050, 24, 3, 31),
> > + MUX_GATE(CLK_TOP_UART_SEL, "uart_sel", uart_parents,
> > + 0x0060, 0, 1, 7),
> > +
> > + MUX_GATE(CLK_TOP_SPI0_SEL, "spi0_sel", spi_parents,
> > + 0x0060, 8, 3, 15),
> > + MUX_GATE(CLK_TOP_USB20_SEL, "usb20_sel", usb20_parents,
> > + 0x0060, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_MSDC30_0_SEL, "msdc30_0_sel", msdc30_parents,
> > + 0x0060, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_MSDC30_1_SEL, "msdc30_1_sel", msdc30_parents,
> > + 0x0070, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_MSDC30_2_SEL, "msdc30_2_sel", msdc30_parents,
> > + 0x0070, 8, 3, 15),
> > + MUX_GATE(CLK_TOP_AUDIO_SEL, "audio_sel", msdc30_parents,
> > + 0x0070, 16, 1, 23),
> > + MUX_GATE(CLK_TOP_AUDINTBUS_SEL, "aud_intbus_sel", aud_intbus_parents,
> > + 0x0070, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_parents,
> > + 0x0080, 0, 4, 7),
> > + MUX_GATE(CLK_TOP_SCP_SEL, "scp_sel", scp_parents,
> > + 0x0080, 8, 2, 15),
> > + MUX_GATE(CLK_TOP_DPI0_SEL, "dpi0_sel", dpi0_parents,
> > + 0x0080, 16, 3, 23),
> > + MUX_GATE(CLK_TOP_DPI1_SEL, "dpi1_sel", dpi1_parents,
> > + 0x0080, 24, 2, 31),
> > +
> > + MUX_GATE(CLK_TOP_TVE_SEL, "tve_sel", tve_parents,
> > + 0x0090, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_HDMI_SEL, "hdmi_sel", hdmi_parents,
> > + 0x0090, 8, 2, 15),
> > + MUX_GATE(CLK_TOP_APLL_SEL, "apll_sel", apll_parents,
> > + 0x0090, 16, 3, 23),
> > +
> > + MUX_GATE_FLAGS(CLK_TOP_RTC_SEL, "rtc_sel", rtc_parents,
> > + 0x00A0, 0, 2, 7, CLK_IS_CRITICAL),
> > + MUX_GATE(CLK_TOP_NFI2X_SEL, "nfi2x_sel", nfi2x_parents,
> > + 0x00A0, 8, 3, 15),
> > + MUX_GATE(CLK_TOP_EMMC_HCLK_SEL, "emmc_hclk_sel", emmc_hclk_parents,
> > + 0x00A0, 24, 2, 31),
> > +
> > + MUX_GATE(CLK_TOP_FLASH_SEL, "flash_sel", flash_parents,
> > + 0x00B0, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_DI_SEL, "di_sel", di_parents,
> > + 0x00B0, 8, 2, 15),
> > + MUX_GATE(CLK_TOP_NR_SEL, "nr_sel", nr_osd_parents,
> > + 0x00B0, 16, 3, 23),
> > + MUX_GATE(CLK_TOP_OSD_SEL, "osd_sel", nr_osd_parents,
> > + 0x00B0, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_HDMIRX_BIST_SEL, "hdmirx_bist_sel",
> > + hdmirx_bist_parents, 0x00C0, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_INTDIR_SEL, "intdir_sel", intdir_parents,
> > + 0x00C0, 8, 2, 15),
> > + MUX_GATE(CLK_TOP_ASM_I_SEL, "asm_i_sel", asm_parents,
> > + 0x00C0, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_ASM_M_SEL, "asm_m_sel", asm_parents,
> > + 0x00C0, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_ASM_H_SEL, "asm_h_sel", asm_parents,
> > + 0x00D0, 0, 2, 7),
> > + MUX_GATE(CLK_TOP_MS_CARD_SEL, "ms_card_sel", ms_card_parents,
> > + 0x00D0, 16, 2, 23),
> > + MUX_GATE(CLK_TOP_ETHIF_SEL, "ethif_sel", ethif_parents,
> > + 0x00D0, 24, 3, 31),
> > +
> > + MUX_GATE(CLK_TOP_HDMIRX26_24_SEL, "hdmirx26_24_sel", hdmirx_parents,
> > + 0x00E0, 0, 1, 7),
> > + MUX_GATE(CLK_TOP_MSDC30_3_SEL, "msdc30_3_sel", msdc30_parents,
> > + 0x00E0, 8, 3, 15),
> > + MUX_GATE(CLK_TOP_CMSYS_SEL, "cmsys_sel", cmsys_parents,
> > + 0x00E0, 16, 4, 23),
> > +
> > + MUX_GATE(CLK_TOP_SPI1_SEL, "spi2_sel", spi_parents,
> > + 0x00E0, 24, 3, 31),
> > + MUX_GATE(CLK_TOP_SPI2_SEL, "spi1_sel", spi_parents,
> > + 0x00F0, 0, 3, 7),
> > + MUX_GATE(CLK_TOP_8BDAC_SEL, "8bdac_sel", clk_8bdac_parents,
> > + 0x00F0, 8, 2, 15),
> > + MUX_GATE(CLK_TOP_AUD2DVD_SEL, "aud2dvd_sel", aud2dvd_parents,
> > + 0x00F0, 16, 1, 23),
> > +
> > + MUX(CLK_TOP_PADMCLK_SEL, "padmclk_sel", padmclk_parents,
> > + 0x0100, 0, 3),
> > +
> > + MUX(CLK_TOP_AUD_MUX1_SEL, "aud_mux1_sel", aud_mux_parents,
> > + 0x012c, 0, 3),
> > + MUX(CLK_TOP_AUD_MUX2_SEL, "aud_mux2_sel", aud_mux_parents,
> > + 0x012c, 3, 3),
> > + MUX(CLK_TOP_AUDPLL_MUX_SEL, "audpll_sel", aud_mux_parents,
> > + 0x012c, 6, 3),
> > + MUX_GATE(CLK_TOP_AUD_K1_SRC_SEL, "aud_k1_src_sel", aud_src_parents,
> > + 0x012c, 15, 1, 23),
> > + MUX_GATE(CLK_TOP_AUD_K2_SRC_SEL, "aud_k2_src_sel", aud_src_parents,
> > + 0x012c, 16, 1, 24),
> > + MUX_GATE(CLK_TOP_AUD_K3_SRC_SEL, "aud_k3_src_sel", aud_src_parents,
> > + 0x012c, 17, 1, 25),
> > + MUX_GATE(CLK_TOP_AUD_K4_SRC_SEL, "aud_k4_src_sel", aud_src_parents,
> > + 0x012c, 18, 1, 26),
> > + MUX_GATE(CLK_TOP_AUD_K5_SRC_SEL, "aud_k5_src_sel", aud_src_parents,
> > + 0x012c, 19, 1, 27),
> > + MUX_GATE(CLK_TOP_AUD_K6_SRC_SEL, "aud_k6_src_sel", aud_src_parents,
> > + 0x012c, 20, 1, 28),
> > +};
> > +
> > +static const struct mtk_clk_divider top_adj_divs[] = {
> > + DIV_ADJ(CLK_TOP_AUD_EXTCK1_DIV, "audio_ext1_ck", "aud_ext1",
> > + 0x0120, 0, 8),
> > + DIV_ADJ(CLK_TOP_AUD_EXTCK2_DIV, "audio_ext2_ck", "aud_ext2",
> > + 0x0120, 8, 8),
> > + DIV_ADJ(CLK_TOP_AUD_MUX1_DIV, "aud_mux1_div", "aud_mux1_sel",
> > + 0x0120, 16, 8),
> > + DIV_ADJ(CLK_TOP_AUD_MUX2_DIV, "aud_mux2_div", "aud_mux2_sel",
> > + 0x0120, 24, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K1_SRC_DIV, "aud_k1_src_div", "aud_k1_src_sel",
> > + 0x0124, 0, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K2_SRC_DIV, "aud_k2_src_div", "aud_k2_src_sel",
> > + 0x0124, 8, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K3_SRC_DIV, "aud_k3_src_div", "aud_k3_src_sel",
> > + 0x0124, 16, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K4_SRC_DIV, "aud_k4_src_div", "aud_k4_src_sel",
> > + 0x0124, 24, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K5_SRC_DIV, "aud_k5_src_div", "aud_k5_src_sel",
> > + 0x0128, 0, 8),
> > + DIV_ADJ(CLK_TOP_AUD_K6_SRC_DIV, "aud_k6_src_div", "aud_k6_src_sel",
> > + 0x0128, 8, 8),
> > +};
> > +
> > +static const struct mtk_gate_regs top_aud_cg_regs = {
> > + .sta_ofs = 0x012C,
> > +};
> > +
> > +#define GATE_TOP_AUD(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &top_aud_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_no_setclr, \
> > + }
> > +
> > +static const struct mtk_gate top_clks[] = {
> > + GATE_TOP_AUD(CLK_TOP_AUD_48K_TIMING, "a1sys_hp_ck", "aud_mux1_div",
> > + 21),
> > + GATE_TOP_AUD(CLK_TOP_AUD_44K_TIMING, "a2sys_hp_ck", "aud_mux2_div",
> > + 22),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S1_MCLK, "aud_i2s1_mclk", "aud_k1_src_div",
> > + 23),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S2_MCLK, "aud_i2s2_mclk", "aud_k2_src_div",
> > + 24),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S3_MCLK, "aud_i2s3_mclk", "aud_k3_src_div",
> > + 25),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S4_MCLK, "aud_i2s4_mclk", "aud_k4_src_div",
> > + 26),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S5_MCLK, "aud_i2s5_mclk", "aud_k5_src_div",
> > + 27),
> > + GATE_TOP_AUD(CLK_TOP_AUD_I2S6_MCLK, "aud_i2s6_mclk", "aud_k6_src_div",
> > + 28),
> > +};
> > +
> > +void __iomem *devm_of_iomap(struct device *dev, int index)
>
> Sorry what is this?
To reduce duplicated code of looking up base address.
> > +{
> > + struct resource res;
> > +
> > + if (!dev)
> > + return NULL;
> > +
> > + if (of_address_to_resource(dev->of_node, index, &res))
> > + return NULL;
> > +
> > + return devm_ioremap(dev, res.start, resource_size(&res));
>
> Can't we just use platform_get_resouce() and
> devm_ioremap_resource() here? It looks like we always have a
> platform device.
I'll change it with these 2 functions.
> > +}
> > +
> > +static int mtk_topckgen_init(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + void __iomem *base;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + base = devm_of_iomap(&pdev->dev, 0);
> > + if (!base)
> > + return -ENOMEM;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_TOP_NR);
> > +
> > + mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> > + clk_data);
> > +
> > + mtk_clk_register_factors(top_fixed_divs, ARRAY_SIZE(top_fixed_divs),
> > + clk_data);
> > +
> > + mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes),
> > + base, &lock, clk_data);
> > +
> > + mtk_clk_register_dividers(top_adj_divs, ARRAY_SIZE(top_adj_divs),
> > + base, &lock, clk_data);
> > +
> > + mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks),
> > + clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > + return r;
> > +}
> > +
> > +static const struct mtk_gate_regs infra_cg_regs = {
> > + .set_ofs = 0x0040,
> > + .clr_ofs = 0x0044,
> > + .sta_ofs = 0x0048,
> > +};
> > +
> > +#define GATE_ICG(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &infra_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > + }
> > +
> > +static const struct mtk_gate infra_clks[] = {
> > + GATE_ICG(CLK_INFRA_DBG, "dbgclk", "axi_sel", 0),
> > + GATE_ICG(CLK_INFRA_SMI, "smi_ck", "mm_sel", 1),
> > + GATE_ICG(CLK_INFRA_QAXI_CM4, "cm4_ck", "axi_sel", 2),
> > + GATE_ICG(CLK_INFRA_AUD_SPLIN_B, "audio_splin_bck", "hadds2pll_294m", 4),
> > + GATE_ICG(CLK_INFRA_AUDIO, "audio_ck", "clk26m", 5),
> > + GATE_ICG(CLK_INFRA_EFUSE, "efuse_ck", "clk26m", 6),
> > + GATE_ICG(CLK_INFRA_L2C_SRAM, "l2c_sram_ck", "mm_sel", 7),
> > + GATE_ICG(CLK_INFRA_M4U, "m4u_ck", "mem_sel", 8),
> > + GATE_ICG(CLK_INFRA_CONNMCU, "connsys_bus", "wbg_dig_ck_416m", 12),
> > + GATE_ICG(CLK_INFRA_TRNG, "trng_ck", "axi_sel", 13),
> > + GATE_ICG(CLK_INFRA_RAMBUFIF, "rambufif_ck", "mem_sel", 14),
> > + GATE_ICG(CLK_INFRA_CPUM, "cpum_ck", "mem_sel", 15),
> > + GATE_ICG(CLK_INFRA_KP, "kp_ck", "axi_sel", 16),
> > + GATE_ICG(CLK_INFRA_CEC, "cec_ck", "rtc_sel", 18),
> > + GATE_ICG(CLK_INFRA_IRRX, "irrx_ck", "axi_sel", 19),
> > + GATE_ICG(CLK_INFRA_PMICSPI, "pmicspi_ck", "pmicspi_sel", 22),
> > + GATE_ICG(CLK_INFRA_PMICWRAP, "pmicwrap_ck", "axi_sel", 23),
> > + GATE_ICG(CLK_INFRA_DDCCI, "ddcci_ck", "axi_sel", 24),
> > +};
> > +
> > +static const struct mtk_fixed_factor infra_fixed_divs[] = {
> > + FACTOR(CLK_INFRA_CLK_13M, "clk13m", "clk26m", 1, 2),
> > +};
> > +
> > +static struct clk_onecell_data *infra_clk_data;
> > +
> > +static void mtk_infrasys_init_early(struct device_node *node)
> > +{
> > + int r, i;
> > +
> > + if (!infra_clk_data) {
> > + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > +
> > + for (i = 0; i < CLK_INFRA_NR; i++)
> > + infra_clk_data->clks[i] = ERR_PTR(-EPROBE_DEFER);
> > + }
> > +
> > + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > + infra_clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > + if (r)
> > + pr_err("%s(): could not register clock provider: %d\n",
> > + __func__, r);
> > +}
> > +CLK_OF_DECLARE_DRIVER(mtk_infra, "mediatek,mt2701-infracfg",
> > + mtk_infrasys_init_early);
> > +
> > +static int mtk_infrasys_init(struct platform_device *pdev)
> > +{
> > + int r, i;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + if (!infra_clk_data) {
> > + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR);
> > + } else {
> > + for (i = 0; i < CLK_INFRA_NR; i++) {
> > + if (infra_clk_data->clks[i] == ERR_PTR(-EPROBE_DEFER))
> > + infra_clk_data->clks[i] = ERR_PTR(-ENOENT);
> > + }
> > + }
> > +
> > + mtk_clk_register_gates(node, infra_clks, ARRAY_SIZE(infra_clks),
> > + infra_clk_data);
> > + mtk_clk_register_factors(infra_fixed_divs, ARRAY_SIZE(infra_fixed_divs),
> > + infra_clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, infra_clk_data);
> > +
> > + return r;
> > +}
> > +
> > +static const struct mtk_gate_regs peri0_cg_regs = {
> > + .set_ofs = 0x0008,
> > + .clr_ofs = 0x0010,
> > + .sta_ofs = 0x0018,
> > +};
> > +
> > +static const struct mtk_gate_regs peri1_cg_regs = {
> > + .set_ofs = 0x000c,
> > + .clr_ofs = 0x0014,
> > + .sta_ofs = 0x001c,
> > +};
> > +
> > +#define GATE_PERI0(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &peri0_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > + }
> > +
> > +#define GATE_PERI1(_id, _name, _parent, _shift) { \
> > + .id = _id, \
> > + .name = _name, \
> > + .parent_name = _parent, \
> > + .regs = &peri1_cg_regs, \
> > + .shift = _shift, \
> > + .ops = &mtk_clk_gate_ops_setclr, \
> > + }
> > +
> > +static const struct mtk_gate peri_clks[] = {
> > + GATE_PERI0(CLK_PERI_USB0_MCU, "usb0_mcu_ck", "axi_sel", 31),
> > + GATE_PERI0(CLK_PERI_ETH, "eth_ck", "clk26m", 30),
> > + GATE_PERI0(CLK_PERI_SPI0, "spi0_ck", "spi0_sel", 29),
> > + GATE_PERI0(CLK_PERI_AUXADC, "auxadc_ck", "clk26m", 28),
> > + GATE_PERI0(CLK_PERI_I2C3, "i2c3_ck", "clk26m", 27),
> > + GATE_PERI0(CLK_PERI_I2C2, "i2c2_ck", "axi_sel", 26),
> > + GATE_PERI0(CLK_PERI_I2C1, "i2c1_ck", "axi_sel", 25),
> > + GATE_PERI0(CLK_PERI_I2C0, "i2c0_ck", "axi_sel", 24),
> > + GATE_PERI0(CLK_PERI_BTIF, "bitif_ck", "axi_sel", 23),
> > + GATE_PERI0(CLK_PERI_UART3, "uart3_ck", "axi_sel", 22),
> > + GATE_PERI0(CLK_PERI_UART2, "uart2_ck", "axi_sel", 21),
> > + GATE_PERI0(CLK_PERI_UART1, "uart1_ck", "axi_sel", 20),
> > + GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
> > + GATE_PERI0(CLK_PERI_NLI, "nli_ck", "axi_sel", 18),
> > + GATE_PERI0(CLK_PERI_MSDC50_3, "msdc50_3_ck", "emmc_hclk_sel", 17),
> > + GATE_PERI0(CLK_PERI_MSDC30_3, "msdc30_3_ck", "msdc30_3_sel", 16),
> > + GATE_PERI0(CLK_PERI_MSDC30_2, "msdc30_2_ck", "msdc30_2_sel", 15),
> > + GATE_PERI0(CLK_PERI_MSDC30_1, "msdc30_1_ck", "msdc30_1_sel", 14),
> > + GATE_PERI0(CLK_PERI_MSDC30_0, "msdc30_0_ck", "msdc30_0_sel", 13),
> > + GATE_PERI0(CLK_PERI_AP_DMA, "ap_dma_ck", "axi_sel", 12),
> > + GATE_PERI0(CLK_PERI_USB1, "usb1_ck", "usb20_sel", 11),
> > + GATE_PERI0(CLK_PERI_USB0, "usb0_ck", "usb20_sel", 10),
> > + GATE_PERI0(CLK_PERI_PWM, "pwm_ck", "axi_sel", 9),
> > + GATE_PERI0(CLK_PERI_PWM7, "pwm7_ck", "axi_sel", 8),
> > + GATE_PERI0(CLK_PERI_PWM6, "pwm6_ck", "axi_sel", 7),
> > + GATE_PERI0(CLK_PERI_PWM5, "pwm5_ck", "axi_sel", 6),
> > + GATE_PERI0(CLK_PERI_PWM4, "pwm4_ck", "axi_sel", 5),
> > + GATE_PERI0(CLK_PERI_PWM3, "pwm3_ck", "axi_sel", 4),
> > + GATE_PERI0(CLK_PERI_PWM2, "pwm2_ck", "axi_sel", 3),
> > + GATE_PERI0(CLK_PERI_PWM1, "pwm1_ck", "axi_sel", 2),
> > + GATE_PERI0(CLK_PERI_THERM, "therm_ck", "axi_sel", 1),
> > + GATE_PERI0(CLK_PERI_NFI, "nfi_ck", "nfi2x_sel", 0),
> > +
> > + GATE_PERI1(CLK_PERI_FCI, "fci_ck", "ms_card_sel", 11),
> > + GATE_PERI1(CLK_PERI_SPI2, "spi2_ck", "spi2_sel", 10),
> > + GATE_PERI1(CLK_PERI_SPI1, "spi1_ck", "spi1_sel", 9),
> > + GATE_PERI1(CLK_PERI_HOST89_DVD, "host89_dvd_ck", "aud2dvd_sel", 8),
> > + GATE_PERI1(CLK_PERI_HOST89_SPI, "host89_spi_ck", "spi0_sel", 7),
> > + GATE_PERI1(CLK_PERI_HOST89_INT, "host89_int_ck", "axi_sel", 6),
> > + GATE_PERI1(CLK_PERI_FLASH, "flash_ck", "nfi2x_sel", 5),
> > + GATE_PERI1(CLK_PERI_NFI_PAD, "nfi_pad_ck", "nfi1x_pad", 4),
> > + GATE_PERI1(CLK_PERI_NFI_ECC, "nfi_ecc_ck", "nfi1x_pad", 3),
> > + GATE_PERI1(CLK_PERI_GCPU, "gcpu_ck", "axi_sel", 2),
> > + GATE_PERI1(CLK_PERI_USB_SLV, "usbslv_ck", "axi_sel", 1),
> > + GATE_PERI1(CLK_PERI_USB1_MCU, "usb1_mcu_ck", "axi_sel", 0),
> > +};
> > +
> > +static const char * const uart_ck_sel_parents[] = {
> > + "clk26m",
> > + "uart_sel",
> > +};
> > +
> > +static const struct mtk_composite peri_muxs[] = {
> > + MUX(CLK_PERI_UART0_SEL, "uart0_ck_sel", uart_ck_sel_parents,
> > + 0x40c, 0, 1),
> > + MUX(CLK_PERI_UART1_SEL, "uart1_ck_sel", uart_ck_sel_parents,
> > + 0x40c, 1, 1),
> > + MUX(CLK_PERI_UART2_SEL, "uart2_ck_sel", uart_ck_sel_parents,
> > + 0x40c, 2, 1),
> > + MUX(CLK_PERI_UART3_SEL, "uart3_ck_sel", uart_ck_sel_parents,
> > + 0x40c, 3, 1),
> > +};
> > +
> > +static int mtk_pericfg_init(struct platform_device *pdev)
> > +{
> > + struct clk_onecell_data *clk_data;
> > + void __iomem *base;
> > + int r;
> > + struct device_node *node = pdev->dev.of_node;
> > +
> > + base = devm_of_iomap(&pdev->dev, 0);
> > + if (!base)
> > + return -ENOMEM;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_PERI_NR);
> > +
> > + mtk_clk_register_gates(node, peri_clks, ARRAY_SIZE(peri_clks),
> > + clk_data);
> > +
> > + mtk_clk_register_composites(peri_muxs, ARRAY_SIZE(peri_muxs), base,
> > + &lock, clk_data);
> > +
> > + r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
> > +
> > + return r;
>
> Just return of_clk_add_provider()?
Okay.
> > +}
> [...]
> > +
> > +static int clk_mt2701_probe(struct platform_device *pdev)
> > +{
> > + int (*clk_init)(struct platform_device *);
> > + int r;
> > +
> > + clk_init = of_device_get_match_data(&pdev->dev);
> > + if (!clk_init)
> > + return -EINVAL;
> > +
> > + r = clk_init(pdev);
> > + if (r) {
> > + dev_err(&pdev->dev,
> > + "could not register clock provider: %s: %d\n",
> > + pdev->name, r);
> > + }
>
> Braces are unnecessary.
I'll remove it.
> > +
> > + return r;
> > +}
> > +
> > +static struct platform_driver clk_mt2701_drv = {
> > + .probe = clk_mt2701_probe,
> > + .driver = {
> > + .name = "clk-mt2701",
> > + .owner = THIS_MODULE,
>
> This is unnecessary because platform_driver_register() already
> does it.
Okay, I'll remove it.
> > + .of_match_table = of_match_clk_mt2701,
> > + },
> > +};
> > +
> > +static int __init clk_mt2701_init(void)
> > +{
> > + return platform_driver_register(&clk_mt2701_drv);
> > +}
> > +
> > +arch_initcall(clk_mt2701_init);
> > diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
> > index bb30f70..0541df7 100644
> > --- a/drivers/clk/mediatek/clk-mtk.c
> > +++ b/drivers/clk/mediatek/clk-mtk.c
> > @@ -58,6 +58,9 @@ void mtk_clk_register_fixed_clks(const struct mtk_fixed_clk *clks,
> > for (i = 0; i < num; i++) {
> > const struct mtk_fixed_clk *rc = &clks[i];
> >
> > + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[rc->id]))
> > + continue;
> > +
> > clk = clk_register_fixed_rate(NULL, rc->name, rc->parent, 0,
> > rc->rate);
> >
> > @@ -81,6 +84,9 @@ void mtk_clk_register_factors(const struct mtk_fixed_factor *clks,
> > for (i = 0; i < num; i++) {
> > const struct mtk_fixed_factor *ff = &clks[i];
> >
> > + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[ff->id]))
> > + continue;
> > +
> > clk = clk_register_fixed_factor(NULL, ff->name, ff->parent_name,
> > CLK_SET_RATE_PARENT, ff->mult, ff->div);
> >
> > @@ -116,6 +122,9 @@ int mtk_clk_register_gates(struct device_node *node,
> > for (i = 0; i < num; i++) {
> > const struct mtk_gate *gate = &clks[i];
> >
> > + if (!IS_ERR_OR_NULL(clk_data->clks[gate->id]))
> > + continue;
> > +
> > clk = mtk_clk_register_gate(gate->name, gate->parent_name,
> > regmap,
> > gate->regs->set_ofs,
> > @@ -232,6 +241,9 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
> > for (i = 0; i < num; i++) {
> > const struct mtk_composite *mc = &mcs[i];
> >
> > + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mc->id]))
> > + continue;
> > +
> > clk = mtk_clk_register_composite(mc, base, lock);
> >
> > if (IS_ERR(clk)) {
> > @@ -244,3 +256,31 @@ void mtk_clk_register_composites(const struct mtk_composite *mcs,
> > clk_data->clks[mc->id] = clk;
> > }
> > }
> > +
> > +void mtk_clk_register_dividers(const struct mtk_clk_divider *mcds,
> > + int num, void __iomem *base, spinlock_t *lock,
> > + struct clk_onecell_data *clk_data)
> > +{
> > + struct clk *clk;
> > + int i;
> > +
> > + for (i = 0; i < num; i++) {
> > + const struct mtk_clk_divider *mcd = &mcds[i];
> > +
> > + if (clk_data && !IS_ERR_OR_NULL(clk_data->clks[mcd->id]))
>
> NULL is a valid clk. IS_ERR_OR_NULL is usually wrong.
Why NULL is a valid clk?
clk_data is designed for multiple initialization from different clock
types, such as infra_clk_data in clk-mt2701.c. So it will ignore valid
clocks to avoid duplicated clock registration. Here I assume a clock
pointer with error code or NULL to be an invalid (not initialized)
clock.
> > + continue;
> > +
> > + clk = clk_register_divider(NULL, mcd->name, mcd->parent_name,
> > + mcd->flags, base + mcd->div_reg, mcd->div_shift,
> > + mcd->div_width, mcd->clk_divider_flags, lock);
> > +
> > + if (IS_ERR(clk)) {
> > + pr_err("Failed to register clk %s: %ld\n",
> > + mcd->name, PTR_ERR(clk));
> > + continue;
> > + }
> > +
> > + if (clk_data)
> > + clk_data->clks[mcd->id] = clk;
> > + }
> > +}
> > diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
> > index 9f24fcf..f5d6b70 100644
> > --- a/drivers/clk/mediatek/clk-mtk.h
> > +++ b/drivers/clk/mediatek/clk-mtk.h
> > @@ -87,7 +87,8 @@ struct mtk_composite {
> > * In case the rate change propagation to parent clocks is undesirable,
> > * this macro allows to specify the clock flags manually.
> > */
> > -#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, _flags) { \
> > +#define MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> > + _gate, _flags) { \
> > .id = _id, \
> > .name = _name, \
> > .mux_reg = _reg, \
> > @@ -106,7 +107,8 @@ struct mtk_composite {
> > * parent clock by default.
> > */
> > #define MUX_GATE(_id, _name, _parents, _reg, _shift, _width, _gate) \
> > - MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, _gate, CLK_SET_RATE_PARENT)
> > + MUX_GATE_FLAGS(_id, _name, _parents, _reg, _shift, _width, \
> > + _gate, CLK_SET_RATE_PARENT)
> >
> > #define MUX(_id, _name, _parents, _reg, _shift, _width) { \
> > .id = _id, \
> > @@ -121,7 +123,8 @@ struct mtk_composite {
> > .flags = CLK_SET_RATE_PARENT, \
> > }
> >
> > -#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, _div_width, _div_shift) { \
> > +#define DIV_GATE(_id, _name, _parent, _gate_reg, _gate_shift, _div_reg, \
> > + _div_width, _div_shift) { \
>
> Did anything actually change? Checkpatch fix?
Right. Just limit max line length to 80 chars.
> > .id = _id, \
> > .parent = _parent, \
> > .name = _name, \
^ permalink raw reply
* Re: [PATCH V3 2/2] iio: adc: spmi-vadc: Changes to support different scaling
From: Rama Krishna Phani A @ 2016-10-31 7:12 UTC (permalink / raw)
To: Jonathan Cameron, Stanimir Varbanov,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh-DgEjT+Ai2ygdnm+yROfE0A, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
smohanad-sgV2jX0FEOL9JmXXK+q4OQ, mgautam-sgV2jX0FEOL9JmXXK+q4OQ,
sivaa-sgV2jX0FEOL9JmXXK+q4OQ, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
Julia.Lawall-L2FTfq7BK8M
In-Reply-To: <a96141dc-6ee5-2d7c-868c-7cb282002b89-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Hi Jonathan,
On 30-Oct-16 10:43 PM, Jonathan Cameron wrote:
> On 27/10/16 18:37, Phani A, Rama Krishna wrote:
>> Hi Stan,
>>
>> On 27-Oct-16 4:48 PM, Stanimir Varbanov wrote:
>>> Hi Rama,
>>>
>>> On 10/26/2016 05:41 PM, Rama Krishna Phani A wrote:
>>>> Polling can also be used for End of conversion completion. Implement logic
>>>> to choose either polling or interrupt for End of conversion completion.
>>>> Scaling can be done on the voltage to report adc code in physical units.
>>>> Add changes to support different scale functions to convert adc code to
>>>> physical units.
>>>>
>>>> Signed-off-by: Rama Krishna Phani A <rphani-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>>> ---
>>>> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 14 ++
>>>> drivers/iio/adc/qcom-spmi-vadc.c | 263 +++++++++++++++++----
>>>> 2 files changed, 236 insertions(+), 41 deletions(-)
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>> index 0fb4613..39e31c0e 100644
>>>> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>> @@ -37,6 +37,12 @@ VADC node:
>>>> Value type: <prop-encoded-array>
>>>> Definition: End of conversion interrupt.
>>>>
>>>> +- qcom,vadc-poll-eoc:
>>>> + Usage: optional
>>>> + Value type: <bool>
>>>> + Definition: Use polling instead of interrupts for End of Conversion
>>>> + completion.
>>>
>>> Why you need to add such a flag in DT?
>>>
>>> The DT should describe hardware details not how the driver will choose
>>> pooling vs interrupt.
>>>
>>> On which use-case you would prefer pooling?
>>>
>>
>> Few PMIC's support interrupt functionality for ADC where as few
>> PMIC's dont support. Based on the functionality that is supported in
>> hardware we choose whether to go for polling or for interrupt.
> Can't use the usual trick of an optional interrupt in DT?
> If it's there we try to use it, if not then fall back to polling?
>
Ok., Will check this logic for implementation and will post next patch.
>
>>>> +
>>>> Channel node properties:
>>>>
>>>> - reg:
>>>> @@ -92,6 +98,14 @@ Channel node properties:
>>>> Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
>>>> If property is not found, 1 sample will be used.
>>>>
>>>> +- qcom,scale-function:
>>>> + Usage: optional
>>>> + Value type: <u32>
>>>> + Definition: Scaling function used to convert raw ADC code to
>>>> + units specific to a given channel. Scaled units can be
>>>> + microvolts, millidegC.Valid values are: 0, 1, 2, 3, 4.
>>>> + If property is not found, 0 scaling will be used.
>>>
>>> This shouldn't be in DT binding. Just select the scale function for each
>>> channel in the driver based on compatible property.
>>>
>>>
>> Ok ., Will remove this binding from DT, implement logic in driver and will post next patch.
>>
>> Thanks,
>> Ramakrishna
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>> the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
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^ permalink raw reply
* [PATCH v3 0/3] Add clockevet for timer-nps driver to NPS400 SoC
From: Noam Camus @ 2016-10-31 7:37 UTC (permalink / raw)
To: robh+dt, mark.rutland, daniel.lezcano
Cc: tglx, devicetree, linux-kernel, Noam Camus
From: Noam Camus <noamca@mellanox.com>
Change log
---
V2 --> V3
Apply Rob Herring comment about backword compatibility
V1 --> V2
Apply Daniel Lezcano comments:
CLOCKSOURCE_OF_DECLARE return value
update hotplug callbacks usage
squash of 2 first commits.
In this version I created new commit to serve as preperation for adding clockevents.
This way the last patch is more readable with clockevent content.
---
In first version of this driver we supported clocksource for the NPS400.
The support for clockevent was taken from Synopsys ARC timer driver.
This was good for working with our simulator of NPS400.
However in NPS400 ASIC the timers behave differently than simulation.
The timers in ASIC are shared between all threads whithin a core
and hence need different driver to support this behaviour.
The idea of this design is that we got 16 HW threads per core
each represented at bimask in a shared register in this core.
So when thread wants that next clockevent expiration will produce
timer interrupt to itself the correspondance bit in this register
should be set.
So theoretically if all 16 bits are set then all HW threads will get
timer interrupt on next expiration of timer 0.
Note that we use Synopsys ARC design naming convention for the timers
where:
timer0 is used for clockevents
timer1 is used for clocksource.
Noam Camus (3):
soc: Support for NPS HW scheduling
clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer
clocksource: Add clockevent support to NPS400 driver
.../bindings/timer/ezchip,nps400-timer.txt | 15 --
.../bindings/timer/ezchip,nps400-timer0.txt | 17 ++
.../bindings/timer/ezchip,nps400-timer1.txt | 15 ++
arch/arc/plat-eznps/include/plat/ctop.h | 2 -
drivers/clocksource/timer-nps.c | 255 ++++++++++++++++++--
include/linux/cpuhotplug.h | 1 +
include/soc/nps/mtm.h | 59 +++++
7 files changed, 327 insertions(+), 37 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
create mode 100644 include/soc/nps/mtm.h
^ permalink raw reply
* [PATCH v3 1/3] soc: Support for NPS HW scheduling
From: Noam Camus @ 2016-10-31 7:37 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Noam Camus
In-Reply-To: <1477899468-5494-1-git-send-email-noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
This new header file is for NPS400 SoC (part of ARC architecture).
The header file includes macros for save/restore of HW scheduling.
The control of HW scheduling is acheived by writing core registers.
This code was moved from arc/plat-eznps so it can be used
from drivers/clocksource/, available only for CONFIG_EZNPS_MTM_EXT.
Signed-off-by: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
---
arch/arc/plat-eznps/include/plat/ctop.h | 2 -
include/soc/nps/mtm.h | 59 +++++++++++++++++++++++++++++++
2 files changed, 59 insertions(+), 2 deletions(-)
create mode 100644 include/soc/nps/mtm.h
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index 9d6718c..ee2e32d 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -46,9 +46,7 @@
#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
/* EZchip core instructions */
-#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
-#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
#define CTOP_INST_SCHD_RW 0x3E6F7004
#define CTOP_INST_SCHD_RD 0x3E6F7084
diff --git a/include/soc/nps/mtm.h b/include/soc/nps/mtm.h
new file mode 100644
index 0000000..d2f5e7e
--- /dev/null
+++ b/include/soc/nps/mtm.h
@@ -0,0 +1,59 @@
+/*
+ * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
+ *
+ * This software is available to you under a choice of one of two
+ * licenses. You may choose to be licensed under the terms of the GNU
+ * General Public License (GPL) Version 2, available from the file
+ * COPYING in the main directory of this source tree, or the
+ * OpenIB.org BSD license below:
+ *
+ * Redistribution and use in source and binary forms, with or
+ * without modification, are permitted provided that the following
+ * conditions are met:
+ *
+ * - Redistributions of source code must retain the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer.
+ *
+ * - Redistributions in binary form must reproduce the above
+ * copyright notice, this list of conditions and the following
+ * disclaimer in the documentation and/or other materials
+ * provided with the distribution.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef SOC_NPS_MTM_H
+#define SOC_NPS_MTM_H
+
+#define CTOP_INST_HWSCHD_OFF_R3 0x3B6F00BF
+#define CTOP_INST_HWSCHD_RESTORE_R3 0x3E6F70C3
+
+static inline void hw_schd_save(unsigned int *flags)
+{
+ __asm__ __volatile__(
+ " .word %1\n"
+ " st r3,[%0]\n"
+ :
+ : "r"(flags), "i"(CTOP_INST_HWSCHD_OFF_R3)
+ : "r3", "memory");
+}
+
+static inline void hw_schd_restore(unsigned int flags)
+{
+ __asm__ __volatile__(
+ " mov r3, %0\n"
+ " .word %1\n"
+ :
+ : "r"(flags), "i"(CTOP_INST_HWSCHD_RESTORE_R3)
+ : "r3");
+}
+
+#endif /* SOC_NPS_MTM_H */
--
1.7.1
--
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^ permalink raw reply related
* [PATCH v3 2/3] clocksource: update "fn" at CLOCKSOURCE_OF_DECLARE() of nps400 timer
From: Noam Camus @ 2016-10-31 7:37 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Noam Camus
In-Reply-To: <1477899468-5494-1-git-send-email-noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
nps_setup_clocksource() should take node as only argument i.e.:
replace
int __init nps_setup_clocksource(struct device_node *node, struct clk *clk)
with
int __init nps_setup_clocksource(struct device_node *node)
This is also serve as preperation for next patch which adds support
for clockevents to nps400.
Specifically we add new function nps_get_timer_clk() to serve clocksource
and later clockevent registration.
Signed-off-by: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
---
drivers/clocksource/timer-nps.c | 49 ++++++++++++++++++++------------------
1 files changed, 26 insertions(+), 23 deletions(-)
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 70c149a..6156e54 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -47,6 +47,28 @@
static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
static unsigned long nps_timer_rate;
+static int nps_get_timer_clk(struct device_node *node,
+ unsigned long *timer_freq,
+ struct clk *clk)
+{
+ int ret;
+
+ clk = of_clk_get(node, 0);
+ if (IS_ERR(clk)) {
+ pr_err("timer missing clk");
+ return PTR_ERR(clk);
+ }
+
+ ret = clk_prepare_enable(clk);
+ if (ret) {
+ pr_err("Couldn't enable parent clk\n");
+ return ret;
+ }
+
+ *timer_freq = clk_get_rate(clk);
+
+ return 0;
+}
static cycle_t nps_clksrc_read(struct clocksource *clksrc)
{
@@ -55,23 +77,17 @@ static cycle_t nps_clksrc_read(struct clocksource *clksrc)
return (cycle_t)ioread32be(nps_msu_reg_low_addr[cluster]);
}
-static int __init nps_setup_clocksource(struct device_node *node,
- struct clk *clk)
+static int __init nps_setup_clocksource(struct device_node *node)
{
int ret, cluster;
+ struct clk *clk;
for (cluster = 0; cluster < NPS_CLUSTER_NUM; cluster++)
nps_msu_reg_low_addr[cluster] =
nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
- ret = clk_prepare_enable(clk);
- if (ret) {
- pr_err("Couldn't enable parent clock\n");
- return ret;
- }
-
- nps_timer_rate = clk_get_rate(clk);
+ nps_get_timer_clk(node, &nps_timer_rate, clk);
ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
nps_timer_rate, 301, 32, nps_clksrc_read);
@@ -83,18 +99,5 @@ static int __init nps_setup_clocksource(struct device_node *node,
return ret;
}
-static int __init nps_timer_init(struct device_node *node)
-{
- struct clk *clk;
-
- clk = of_clk_get(node, 0);
- if (IS_ERR(clk)) {
- pr_err("Can't get timer clock.\n");
- return PTR_ERR(clk);
- }
-
- return nps_setup_clocksource(node, clk);
-}
-
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
- nps_timer_init);
+ nps_setup_clocksource);
--
1.7.1
--
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^ permalink raw reply related
* [PATCH v3 3/3] clocksource: Add clockevent support to NPS400 driver
From: Noam Camus @ 2016-10-31 7:37 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A
Cc: tglx-hfZtesqFncYOwBW4kG4KsQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Noam Camus
In-Reply-To: <1477899468-5494-1-git-send-email-noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
From: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.
The design idea is that for each core there is dedicated regirtser
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.
Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent
Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
Signed-off-by: Noam Camus <noamca-VPRAkNaXOzVWk0Htik3J/w@public.gmane.org>
Change-Id: Ib351e6fc7a6b691293040ae655f202f3cc2c1298
---
.../bindings/timer/ezchip,nps400-timer.txt | 15 --
.../bindings/timer/ezchip,nps400-timer0.txt | 17 ++
.../bindings/timer/ezchip,nps400-timer1.txt | 15 ++
drivers/clocksource/timer-nps.c | 220 +++++++++++++++++++-
include/linux/cpuhotplug.h | 1 +
5 files changed, 249 insertions(+), 19 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
create mode 100644 Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
deleted file mode 100644
index c8c03d7..0000000
--- a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer.txt
+++ /dev/null
@@ -1,15 +0,0 @@
-NPS Network Processor
-
-Required properties:
-
-- compatible : should be "ezchip,nps400-timer"
-
-Clocks required for compatible = "ezchip,nps400-timer":
-- clocks : Must contain a single entry describing the clock input
-
-Example:
-
-timer {
- compatible = "ezchip,nps400-timer";
- clocks = <&sysclk>;
-};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
new file mode 100644
index 0000000..e3cfce8
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer0.txt
@@ -0,0 +1,17 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer0"
+
+Clocks required for compatible = "ezchip,nps400-timer0":
+- interrupts : The interrupt of the first timer
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer0";
+ interrupts = <3>;
+ clocks = <&sysclk>;
+};
diff --git a/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
new file mode 100644
index 0000000..c0ab419
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/ezchip,nps400-timer1.txt
@@ -0,0 +1,15 @@
+NPS Network Processor
+
+Required properties:
+
+- compatible : should be "ezchip,nps400-timer1"
+
+Clocks required for compatible = "ezchip,nps400-timer1":
+- clocks : Must contain a single entry describing the clock input
+
+Example:
+
+timer {
+ compatible = "ezchip,nps400-timer1";
+ clocks = <&sysclk>;
+};
diff --git a/drivers/clocksource/timer-nps.c b/drivers/clocksource/timer-nps.c
index 6156e54..67aafcc 100644
--- a/drivers/clocksource/timer-nps.c
+++ b/drivers/clocksource/timer-nps.c
@@ -46,7 +46,7 @@
/* This array is per cluster of CPUs (Each NPS400 cluster got 256 CPUs) */
static void *nps_msu_reg_low_addr[NPS_CLUSTER_NUM] __read_mostly;
-static unsigned long nps_timer_rate;
+static unsigned long nps_timer1_freq;
static int nps_get_timer_clk(struct device_node *node,
unsigned long *timer_freq,
struct clk *clk)
@@ -87,10 +87,10 @@ static int __init nps_setup_clocksource(struct device_node *node)
nps_host_reg((cluster << NPS_CLUSTER_OFFSET),
NPS_MSU_BLKID, NPS_MSU_TICK_LOW);
- nps_get_timer_clk(node, &nps_timer_rate, clk);
+ nps_get_timer_clk(node, &nps_timer1_freq, clk);
- ret = clocksource_mmio_init(nps_msu_reg_low_addr, "EZnps-tick",
- nps_timer_rate, 301, 32, nps_clksrc_read);
+ ret = clocksource_mmio_init(nps_msu_reg_low_addr, "nps-tick",
+ nps_timer1_freq, 301, 32, nps_clksrc_read);
if (ret) {
pr_err("Couldn't register clock source.\n");
clk_disable_unprepare(clk);
@@ -101,3 +101,215 @@ static int __init nps_setup_clocksource(struct device_node *node)
CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clksrc, "ezchip,nps400-timer",
nps_setup_clocksource);
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_src, "ezchip,nps400-timer1",
+ nps_setup_clocksource);
+
+#ifdef CONFIG_EZNPS_MTM_EXT
+#include <soc/nps/mtm.h>
+
+/* Timer related Aux registers */
+#define AUX_REG_TIMER0_TSI 0xFFFFF850 /* timer 0 HW threads mask */
+#define NPS_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
+#define NPS_REG_TIMER0_CTRL 0x22 /* timer 0 control */
+#define NPS_REG_TIMER0_CNT 0x21 /* timer 0 count */
+
+#define TIMER0_CTRL_IE (1 << 0) /* Interrupt when Count reaches limit */
+#define TIMER0_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
+
+static unsigned long nps_timer0_freq;
+static unsigned long nps_timer0_irq;
+
+/*
+ * Arm the timer to interrupt after @cycles
+ */
+static void nps_clkevent_timer_event_setup(unsigned int cycles)
+{
+ write_aux_reg(NPS_REG_TIMER0_LIMIT, cycles);
+ write_aux_reg(NPS_REG_TIMER0_CNT, 0); /* start from 0 */
+
+ write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+}
+
+static void nps_clkevent_rm_thread(bool remove_thread)
+{
+ unsigned int cflags;
+ unsigned int enabled_threads;
+ unsigned long flags;
+ int thread;
+
+ local_irq_save(flags);
+ hw_schd_save(&cflags);
+
+ enabled_threads = read_aux_reg(AUX_REG_TIMER0_TSI);
+
+ /* remove thread from TSI1 */
+ if (remove_thread) {
+ thread = read_aux_reg(CTOP_AUX_THREAD_ID);
+ enabled_threads &= ~(1 << thread);
+ write_aux_reg(AUX_REG_TIMER0_TSI, enabled_threads);
+ }
+
+ /* Re-arm the timer if needed */
+ if (!enabled_threads)
+ write_aux_reg(NPS_REG_TIMER0_CTRL, TIMER0_CTRL_NH);
+ else
+ write_aux_reg(NPS_REG_TIMER0_CTRL,
+ TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+
+ hw_schd_restore(cflags);
+ local_irq_restore(flags);
+}
+
+static void nps_clkevent_add_thread(bool set_event)
+{
+ int thread;
+ unsigned int cflags, enabled_threads;
+ unsigned long flags;
+
+ local_irq_save(flags);
+ hw_schd_save(&cflags);
+
+ /* add thread to TSI1 */
+ thread = read_aux_reg(CTOP_AUX_THREAD_ID);
+ enabled_threads = read_aux_reg(AUX_REG_TIMER0_TSI);
+ enabled_threads |= (1 << thread);
+ write_aux_reg(AUX_REG_TIMER0_TSI, enabled_threads);
+
+ /* set next timer event */
+ if (set_event)
+ write_aux_reg(NPS_REG_TIMER0_CTRL,
+ TIMER0_CTRL_IE | TIMER0_CTRL_NH);
+
+ hw_schd_restore(cflags);
+ local_irq_restore(flags);
+}
+
+static int nps_clkevent_set_next_event(unsigned long delta,
+ struct clock_event_device *dev)
+{
+ struct irq_desc *desc = irq_to_desc(nps_timer0_irq);
+ struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data);
+
+ nps_clkevent_add_thread(true);
+ chip->irq_unmask(&desc->irq_data);
+
+ return 0;
+}
+
+/*
+ * Whenever anyone tries to change modes, we just mask interrupts
+ * and wait for the next event to get set.
+ */
+static int nps_clkevent_timer_shutdown(struct clock_event_device *dev)
+{
+ struct irq_desc *desc = irq_to_desc(nps_timer0_irq);
+ struct irq_chip *chip = irq_data_get_irq_chip(&desc->irq_data);
+
+ chip->irq_mask(&desc->irq_data);
+
+ return 0;
+}
+
+static int nps_clkevent_set_periodic(struct clock_event_device *dev)
+{
+ nps_clkevent_add_thread(false);
+ if (read_aux_reg(CTOP_AUX_THREAD_ID) == 0)
+ nps_clkevent_timer_event_setup(nps_timer0_freq / HZ);
+
+ return 0;
+}
+
+static int nps_clkevent_set_oneshot(struct clock_event_device *dev)
+{
+ nps_clkevent_rm_thread(true);
+ nps_clkevent_timer_shutdown(dev);
+
+ return 0;
+}
+
+static DEFINE_PER_CPU(struct clock_event_device, nps_clockevent_device) = {
+ .name = "NPS Timer0",
+ .features = CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_PERIODIC,
+ .rating = 300,
+ .set_next_event = nps_clkevent_set_next_event,
+ .set_state_periodic = nps_clkevent_set_periodic,
+ .set_state_oneshot = nps_clkevent_set_oneshot,
+ .set_state_oneshot_stopped = nps_clkevent_timer_shutdown,
+ .set_state_shutdown = nps_clkevent_timer_shutdown,
+ .tick_resume = nps_clkevent_timer_shutdown,
+};
+
+static irqreturn_t timer_irq_handler(int irq, void *dev_id)
+{
+ /*
+ * Note that generic IRQ core could have passed @evt for @dev_id if
+ * irq_set_chip_and_handler() asked for handle_percpu_devid_irq()
+ */
+ struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+ int irq_reenable = clockevent_state_periodic(evt);
+
+ nps_clkevent_rm_thread(!irq_reenable);
+
+ evt->event_handler(evt);
+
+ return IRQ_HANDLED;
+}
+
+static int nps_timer_starting_cpu(unsigned int cpu)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+
+ evt->cpumask = cpumask_of(smp_processor_id());
+
+ clockevents_config_and_register(evt, nps_timer0_freq, 0, ULONG_MAX);
+ enable_percpu_irq(nps_timer0_irq, 0);
+
+ return 0;
+}
+
+static int nps_timer_dying_cpu(unsigned int cpu)
+{
+ disable_percpu_irq(nps_timer0_irq);
+ return 0;
+}
+
+static int __init nps_setup_clockevent(struct device_node *node)
+{
+ struct clock_event_device *evt = this_cpu_ptr(&nps_clockevent_device);
+ struct clk *clk;
+ int ret;
+
+ nps_timer0_irq = irq_of_parse_and_map(node, 0);
+ if (nps_timer0_irq <= 0) {
+ pr_err("clockevent: missing irq");
+ return -EINVAL;
+ }
+
+ nps_get_timer_clk(node, &nps_timer0_freq, clk);
+
+ /* Needs apriori irq_set_percpu_devid() done in intc map function */
+ ret = request_percpu_irq(nps_timer0_irq, timer_irq_handler,
+ "Timer0 (per-cpu-tick)", evt);
+ if (ret) {
+ pr_err("Couldn't request irq\n");
+ clk_disable_unprepare(clk);
+ return ret;
+ }
+
+ ret = cpuhp_setup_state(CPUHP_AP_NPS_TIMER_STARTING,
+ "AP_NPS_TIMER_STARTING",
+ nps_timer_starting_cpu,
+ nps_timer_dying_cpu);
+ if (ret) {
+ pr_err("Failed to setup hotplug state");
+ clk_disable_unprepare(clk);
+ return ret;
+ }
+
+ return 0;
+}
+
+CLOCKSOURCE_OF_DECLARE(ezchip_nps400_clk_evt, "ezchip,nps400-timer0",
+ nps_setup_clockevent);
+#endif /* CONFIG_EZNPS_MTM_EXT */
diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h
index 34bd805..9efc1a3 100644
--- a/include/linux/cpuhotplug.h
+++ b/include/linux/cpuhotplug.h
@@ -60,6 +60,7 @@ enum cpuhp_state {
CPUHP_AP_MARCO_TIMER_STARTING,
CPUHP_AP_MIPS_GIC_TIMER_STARTING,
CPUHP_AP_ARC_TIMER_STARTING,
+ CPUHP_AP_NPS_TIMER_STARTING,
CPUHP_AP_KVM_STARTING,
CPUHP_AP_KVM_ARM_VGIC_INIT_STARTING,
CPUHP_AP_KVM_ARM_VGIC_STARTING,
--
1.7.1
--
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^ permalink raw reply related
* Re: [PATCH V3 2/2] iio: adc: spmi-vadc: Changes to support different scaling
From: Rama Krishna Phani A @ 2016-10-31 7:45 UTC (permalink / raw)
To: Jonathan Cameron, linux-iio, devicetree
Cc: robh, linux-arm-msm, smohanad, mgautam, sivaa, knaack.h, lars,
pmeerw, Julia.Lawall
In-Reply-To: <555edcae-23e1-ea96-551b-86cda4c489b3@kernel.org>
Hi Jonathan,
On 30-Oct-16 11:09 PM, Jonathan Cameron wrote:
> On 26/10/16 15:41, Rama Krishna Phani A wrote:
>> Polling can also be used for End of conversion completion. Implement logic
>> to choose either polling or interrupt for End of conversion completion.
> Why is this change in a patch with the title above? Should be a separate patch.
>
Ok., Will split the patch.
>> Scaling can be done on the voltage to report adc code in physical units.
>> Add changes to support different scale functions to convert adc code to
>> physical units.
>>
>> Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
>> ---
>> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 14 ++
>> drivers/iio/adc/qcom-spmi-vadc.c | 263 +++++++++++++++++----
>> 2 files changed, 236 insertions(+), 41 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>> index 0fb4613..39e31c0e 100644
>> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>> @@ -37,6 +37,12 @@ VADC node:
>> Value type: <prop-encoded-array>
>> Definition: End of conversion interrupt.
>>
>> +- qcom,vadc-poll-eoc:
>> + Usage: optional
>> + Value type: <bool>
>> + Definition: Use polling instead of interrupts for End of Conversion
>> + completion.
>> +
>> Channel node properties:
>>
>> - reg:
>> @@ -92,6 +98,14 @@ Channel node properties:
>> Valid values are: 1, 2, 4, 8, 16, 32, 64, 128, 256, 512
>> If property is not found, 1 sample will be used.
>>
>> +- qcom,scale-function:
>> + Usage: optional
>> + Value type: <u32>
>> + Definition: Scaling function used to convert raw ADC code to
>> + units specific to a given channel. Scaled units can be
>> + microvolts, millidegC.Valid values are: 0, 1, 2, 3, 4.
>> + If property is not found, 0 scaling will be used.
>> +
>> NOTE:
>>
>> Following channels, also known as reference point channels, are used for
>> diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
>> index ff4d549..6e521a9 100644
>> --- a/drivers/iio/adc/qcom-spmi-vadc.c
>> +++ b/drivers/iio/adc/qcom-spmi-vadc.c
>> @@ -92,6 +92,8 @@
>> #define VADC_DEF_AVG_SAMPLES 0 /* 1 sample */
>> #define VADC_DEF_CALIB_TYPE VADC_CALIB_ABSOLUTE
>>
>> +#define VADC_DEF_SCALE_FN SCALE_DEFAULT
>> +
>> #define VADC_DECIMATION_MIN 512
>> #define VADC_DECIMATION_MAX 4096
>>
>> @@ -100,9 +102,43 @@
>>
>> #define KELVINMIL_CELSIUSMIL 273150
>>
>> +#define PMI_CHG_SCALE_1 -138890
>> +#define PMI_CHG_SCALE_2 391750000000
>> +
>> #define VADC_CHAN_MIN VADC_USBIN
>> #define VADC_CHAN_MAX VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM
>>
>> +/**
>> + * enum vadc_scale_fn_type - Scaling function to convert ADC code to
>> + * physical scaled units for the channel.
>> + * %SCALE_DEFAULT: Default scaling to convert raw adc code to voltage (uV).
>> + * %SCALE_THERM_100K_PULLUP: Returns temperature in millidegC.
>> + * Uses a mapping table with 100K pullup.
>> + * %SCALE_PMIC_THERM: Returns result in milli degree's Centigrade.
>> + * %SCALE_XOTHERM: Returns XO thermistor voltage in millidegC.
>> + * %SCALE_PMI_CHG_TEMP: Conversion for PMI CHG temp
>> + * %SCALE_NONE: Do not use this scaling type.
>> + */
>> +enum vadc_scale_fn_type {
>> + SCALE_DEFAULT = 0,
>> + SCALE_THERM_100K_PULLUP,
>> + SCALE_PMIC_THERM,
>> + SCALE_XOTHERM,
>> + SCALE_PMI_CHG_TEMP,
>> + SCALE_NONE,
>> +};
>> +
>> +/**
>> + * struct vadc_map_pt - Map the graph representation for ADC channel
>> + * @x: Represent the ADC digitized code.
>> + * @y: Represent the physical data which can be temperature, voltage,
>> + * resistance.
>> + */
>> +struct vadc_map_pt {
>> + s32 x;
>> + s32 y;
>> +};
>> +
>> /*
>> * VADC_CALIB_ABSOLUTE: uses the 625mV and 1.25V as reference channels.
>> * VADC_CALIB_RATIOMETRIC: uses the reference voltage (1.8V) and GND for
>> @@ -148,6 +184,9 @@ struct vadc_prescale_ratio {
>> * start of conversion.
>> * @avg_samples: ability to provide single result from the ADC
>> * that is an average of multiple measurements.
> Make sure your indentation matches the rest of the comment..
Sure ., Will check for indentation.
>> + *@scale_function: Represents the scaling function to convert voltage
>> + * physical units desired by the client for the channel.
>> + * Referenced from enum vadc_scale_fn_type.
>> */
>> struct vadc_channel_prop {
>> unsigned int channel;
>> @@ -156,6 +195,7 @@ struct vadc_channel_prop {
>> unsigned int prescale;
>> unsigned int hw_settle_time;
>> unsigned int avg_samples;
>> + unsigned int scale_function;
>> };
>>
>> /**
>> @@ -197,6 +237,44 @@ struct vadc_priv {
>> {.num = 1, .den = 10}
>> };
>>
>> +/* Voltage to temperature */
>> +static const struct vadc_map_pt adcmap_100k_104ef_104fb[] = {
>> + {1758, -40},
>> + {1742, -35},
>> + {1719, -30},
>> + {1691, -25},
>> + {1654, -20},
>> + {1608, -15},
>> + {1551, -10},
>> + {1483, -5},
>> + {1404, 0},
>> + {1315, 5},
>> + {1218, 10},
>> + {1114, 15},
>> + {1007, 20},
>> + {900, 25},
>> + {795, 30},
>> + {696, 35},
>> + {605, 40},
>> + {522, 45},
>> + {448, 50},
>> + {383, 55},
>> + {327, 60},
>> + {278, 65},
>> + {237, 70},
>> + {202, 75},
>> + {172, 80},
>> + {146, 85},
>> + {125, 90},
>> + {107, 95},
>> + {92, 100},
>> + {79, 105},
>> + {68, 110},
>> + {59, 115},
>> + {51, 120},
>> + {44, 125}
>> +};
>> +
>> static int vadc_read(struct vadc_priv *vadc, u16 offset, u8 *data)
>> {
>> return regmap_bulk_read(vadc->regmap, vadc->base + offset, data, 1);
>> @@ -468,6 +546,51 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
>> return ret;
>> }
>>
>> +static int vadc_map_voltage_temp(const struct vadc_map_pt *pts,
>> + u32 tablesize, s32 input, s64 *output)
>> +{
>> + bool descending = 1;
>> + u32 i = 0;
>> +
>> + if (!pts)
>> + return -EINVAL;
>> +
>> + /* Check if table is descending or ascending */
>> + if (tablesize > 1) {
>> + if (pts[0].x < pts[1].x)
>> + descending = 0;
>> + }
>> +
>> + while (i < tablesize) {
>> + if ((descending) && (pts[i].x < input)) {
>> + /* table entry is less than measured*/
>> + /* value and table is descending, stop */
>> + break;
>> + } else if ((!descending) &&
>> + (pts[i].x > input)) {
>> + /* table entry is greater than measured*/
>> + /*value and table is ascending, stop */
>> + break;
>> + }
>> + i++;
>> + }
>> +
>> + if (i == 0) {
>> + *output = pts[0].y;
>> + } else if (i == tablesize) {
>> + *output = pts[tablesize - 1].y;
>> + } else {
>> + /* result is between search_index and search_index-1 */
>> + /* interpolate linearly */
>> + *output = (((s32)((pts[i].y - pts[i - 1].y) *
>> + (input - pts[i - 1].x)) /
>> + (pts[i].x - pts[i - 1].x)) +
>> + pts[i - 1].y);
>> + }
>> +
>> + return 0;
>> +}
>> +
>> static void vadc_scale_calib(struct vadc_priv *vadc, u16 adc_code,
>> const struct vadc_channel_prop *prop,
>> s64 *scale_voltage)
>> @@ -489,15 +612,61 @@ static s64 vadc_scale_fn(struct vadc_priv *vadc,
>> const struct vadc_channel_prop *prop, u16 adc_code)
>> {
>> const struct vadc_prescale_ratio *prescale;
>> - s64 voltage = 0;
>> + s64 voltage = 0, result = 0;
>> + int ret;
>> +
>> + switch (prop->scale_function) {
>> + case SCALE_DEFAULT:
>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>> +
>> + prescale = &vadc_prescale_ratios[prop->prescale];
>> + voltage = voltage * prescale->den;
>> + return div64_s64(voltage, prescale->num);
>> +
>> + case SCALE_THERM_100K_PULLUP:
>> + case SCALE_XOTHERM:
>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>> +
>> + if (prop->calibration == VADC_CALIB_ABSOLUTE)
>> + voltage /= 1000;
>> +
>> + vadc_map_voltage_temp(adcmap_100k_104ef_104fb,
>> + ARRAY_SIZE(adcmap_100k_104ef_104fb),
>> + voltage, &result);
>> + result *= 1000;
>> + return result;
>> +
>> + case SCALE_PMIC_THERM:
>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>> +
>> + if (voltage > 0) {
>> + prescale = &vadc_prescale_ratios[prop->prescale];
>> + voltage = voltage * prescale->den;
>> + voltage /= (prescale->num * 2);
>> + } else {
>> + voltage = 0;
>> + }
>> +
>> + voltage -= KELVINMIL_CELSIUSMIL;
>>
>> - vadc_scale_calib(vadc, adc_code, prop, &voltage);
>> + return voltage;
>>
>> - prescale = &vadc_prescale_ratios[prop->prescale];
>> + case SCALE_PMI_CHG_TEMP:
>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>> + prescale = &vadc_prescale_ratios[prop->prescale];
>> + voltage = voltage * prescale->den;
>>
>> - voltage = voltage * prescale->den;
>> + voltage = div64_s64(voltage, prescale->num);
>> + voltage = ((PMI_CHG_SCALE_1) * (voltage * 2));
>> + voltage = (voltage + PMI_CHG_SCALE_2);
>> + return div64_s64(voltage, 1000000);
>>
>> - return div64_s64(voltage, prescale->num);
>> + default:
>> + ret = -EINVAL;
>> + break;
>> + }
>> +
>> + return ret;
>> }
>>
>> static int vadc_decimation_from_dt(u32 value)
>> @@ -615,7 +784,9 @@ struct vadc_channels {
>> }, \
>>
>> #define VADC_CHAN_TEMP(_dname, _pre) \
>> - VADC_CHAN(_dname, IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre) \
>> + VADC_CHAN(_dname, IIO_TEMP, \
>> + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED), \
>> + _pre) \
>>
>> #define VADC_CHAN_VOLT(_dname, _pre) \
>> VADC_CHAN(_dname, IIO_VOLTAGE, \
>> @@ -639,7 +810,7 @@ struct vadc_channels {
>> VADC_CHAN_TEMP(DIE_TEMP, 0)
>> VADC_CHAN_VOLT(REF_625MV, 0)
>> VADC_CHAN_VOLT(REF_1250MV, 0)
>> - VADC_CHAN_VOLT(CHG_TEMP, 0)
>> + VADC_CHAN_TEMP(CHG_TEMP, 0)
>> VADC_CHAN_VOLT(SPARE1, 0)
>> VADC_CHAN_VOLT(SPARE2, 0)
>> VADC_CHAN_VOLT(GND_REF, 0)
>> @@ -693,41 +864,41 @@ struct vadc_channels {
>> VADC_CHAN_VOLT(AMUX_PU2, 0)
>> VADC_CHAN_VOLT(LR_MUX3_BUF_XO_THERM, 0)
>>
>> - VADC_CHAN_VOLT(LR_MUX1_PU1_BAT_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX1_PU1_BAT_THERM, 0)
>> VADC_CHAN_VOLT(LR_MUX2_PU1_BAT_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_PU1_XO_THERM, 0)
>> - VADC_CHAN_VOLT(LR_MUX4_PU1_AMUX_THM1, 0)
>> - VADC_CHAN_VOLT(LR_MUX5_PU1_AMUX_THM2, 0)
>> - VADC_CHAN_VOLT(LR_MUX6_PU1_AMUX_THM3, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_PU1_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX4_PU1_AMUX_THM1, 0)
>> + VADC_CHAN_TEMP(LR_MUX5_PU1_AMUX_THM2, 0)
>> + VADC_CHAN_TEMP(LR_MUX6_PU1_AMUX_THM3, 0)
>> VADC_CHAN_VOLT(LR_MUX7_PU1_AMUX_HW_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX8_PU1_AMUX_THM4, 0)
>> - VADC_CHAN_VOLT(LR_MUX9_PU1_AMUX_THM5, 0)
>> + VADC_CHAN_TEMP(LR_MUX8_PU1_AMUX_THM4, 0)
>> + VADC_CHAN_TEMP(LR_MUX9_PU1_AMUX_THM5, 0)
>> VADC_CHAN_VOLT(LR_MUX10_PU1_AMUX_USB_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_BUF_PU1_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_BUF_PU1_XO_THERM, 0)
>>
>> - VADC_CHAN_VOLT(LR_MUX1_PU2_BAT_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX1_PU2_BAT_THERM, 0)
>> VADC_CHAN_VOLT(LR_MUX2_PU2_BAT_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_PU2_XO_THERM, 0)
>> - VADC_CHAN_VOLT(LR_MUX4_PU2_AMUX_THM1, 0)
>> - VADC_CHAN_VOLT(LR_MUX5_PU2_AMUX_THM2, 0)
>> - VADC_CHAN_VOLT(LR_MUX6_PU2_AMUX_THM3, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_PU2_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX4_PU2_AMUX_THM1, 0)
>> + VADC_CHAN_TEMP(LR_MUX5_PU2_AMUX_THM2, 0)
>> + VADC_CHAN_TEMP(LR_MUX6_PU2_AMUX_THM3, 0)
>> VADC_CHAN_VOLT(LR_MUX7_PU2_AMUX_HW_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX8_PU2_AMUX_THM4, 0)
>> - VADC_CHAN_VOLT(LR_MUX9_PU2_AMUX_THM5, 0)
>> + VADC_CHAN_TEMP(LR_MUX8_PU2_AMUX_THM4, 0)
>> + VADC_CHAN_TEMP(LR_MUX9_PU2_AMUX_THM5, 0)
>> VADC_CHAN_VOLT(LR_MUX10_PU2_AMUX_USB_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_BUF_PU2_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_BUF_PU2_XO_THERM, 0)
>>
>> - VADC_CHAN_VOLT(LR_MUX1_PU1_PU2_BAT_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX1_PU1_PU2_BAT_THERM, 0)
>> VADC_CHAN_VOLT(LR_MUX2_PU1_PU2_BAT_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_PU1_PU2_XO_THERM, 0)
>> - VADC_CHAN_VOLT(LR_MUX4_PU1_PU2_AMUX_THM1, 0)
>> - VADC_CHAN_VOLT(LR_MUX5_PU1_PU2_AMUX_THM2, 0)
>> - VADC_CHAN_VOLT(LR_MUX6_PU1_PU2_AMUX_THM3, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_PU1_PU2_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX4_PU1_PU2_AMUX_THM1, 0)
>> + VADC_CHAN_TEMP(LR_MUX5_PU1_PU2_AMUX_THM2, 0)
>> + VADC_CHAN_TEMP(LR_MUX6_PU1_PU2_AMUX_THM3, 0)
>> VADC_CHAN_VOLT(LR_MUX7_PU1_PU2_AMUX_HW_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX8_PU1_PU2_AMUX_THM4, 0)
>> - VADC_CHAN_VOLT(LR_MUX9_PU1_PU2_AMUX_THM5, 0)
>> + VADC_CHAN_TEMP(LR_MUX8_PU1_PU2_AMUX_THM4, 0)
>> + VADC_CHAN_TEMP(LR_MUX9_PU1_PU2_AMUX_THM5, 0)
>> VADC_CHAN_VOLT(LR_MUX10_PU1_PU2_AMUX_USB_ID, 0)
>> - VADC_CHAN_VOLT(LR_MUX3_BUF_PU1_PU2_XO_THERM, 0)
>> + VADC_CHAN_TEMP(LR_MUX3_BUF_PU1_PU2_XO_THERM, 0)
>> };
>>
>> static int vadc_get_dt_channel_data(struct device *dev,
>> @@ -804,6 +975,11 @@ static int vadc_get_dt_channel_data(struct device *dev,
>> prop->avg_samples = VADC_DEF_AVG_SAMPLES;
>> }
>>
>> + ret = of_property_read_u32(node, "qcom,scale-function",
>> + &prop->scale_function);
>> + if (ret)
>> + prop->scale_function = SCALE_DEFAULT;
>> +
>> if (of_property_read_bool(node, "qcom,ratiometric"))
>> prop->calibration = VADC_CALIB_RATIOMETRIC;
>> else
>> @@ -966,16 +1142,21 @@ static int vadc_probe(struct platform_device *pdev)
>> if (ret)
>> return ret;
>>
>> - irq_eoc = platform_get_irq(pdev, 0);
>> - if (irq_eoc < 0) {
>> - if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
>> - return irq_eoc;
>> - vadc->poll_eoc = true;
>> - } else {
>> - ret = devm_request_irq(dev, irq_eoc, vadc_isr, 0,
>> - "spmi-vadc", vadc);
>> - if (ret)
>> - return ret;
>> + vadc->poll_eoc = of_property_read_bool(node,
>> + "qcom,vadc-poll-eoc");
> Should definitely be done on availability of the IRQ rather than a separate
> device tree element.
Will check the logic for implementation and will post next patch.
>> +
>> + if (!vadc->poll_eoc) {
>> + irq_eoc = platform_get_irq(pdev, 0);
>> + if (irq_eoc < 0) {
>> + if (irq_eoc == -EPROBE_DEFER || irq_eoc == -EINVAL)
>> + return irq_eoc;
>> + vadc->poll_eoc = true;
>> + } else {
>> + ret = devm_request_irq(dev, irq_eoc, vadc_isr, 0,
>> + "spmi-vadc", vadc);
>> + if (ret)
>> + return ret;
>> + }
>> }
>>
>> ret = vadc_reset(vadc);
>>
>
Thanks,
Ramakrishna
---
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^ permalink raw reply
* Re: [PATCHv2 3/4] mfd: altr-a10sr: Add Arria10 SR Monitor
From: Lee Jones @ 2016-10-31 8:02 UTC (permalink / raw)
To: tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, arnd-r2nGTMty4D4,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, geert-Td1EMuHUCqxL1ZNQvxDV9g,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1477598426-28125-4-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
On Thu, 27 Oct 2016, tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org wrote:
> From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
>
> Add the Altera Arria10 DevKit System Resource Monitor functionality
> to the MFD device.
>
> Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
> ---
> v2 Change from -mon to -monitor for clarity
> ---
> drivers/mfd/altera-a10sr.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
> index 06e1f7f..30de652 100644
> --- a/drivers/mfd/altera-a10sr.c
> +++ b/drivers/mfd/altera-a10sr.c
> @@ -33,6 +33,10 @@
> .name = "altr_a10sr_gpio",
> .of_compatible = "altr,a10sr-gpio",
> },
> + {
> + .name = "altr_a10sr_monitor",
> + .of_compatible = "altr,a10sr-monitor",
So long as you use whichever compatible you agree on with Rob:
For my own reference:
Acked-for-MFD-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> + },
> };
>
> static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH 1/4] mfd: ti_am335x_tscadc: store physical address
From: Lee Jones @ 2016-10-31 8:16 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Mugunthan V N, linux-iio-u79uwXL29TY76Z2rM5mHXA, Tony Lindgren,
Rob Herring, Mark Rutland, Russell King, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Vignesh R,
Andrew F . Davis, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Sekhar Nori, Peter Ujfalusi
In-Reply-To: <954adfa7-94d9-f785-aeab-6f20c8f4c3b9-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
On Sun, 30 Oct 2016, Jonathan Cameron wrote:
> On 26/10/16 13:17, Lee Jones wrote:
> > On Fri, 30 Sep 2016, Mugunthan V N wrote:
> >
> >> On Wednesday 28 September 2016 01:10 AM, Lee Jones wrote:
> >>> On Wed, 21 Sep 2016, Mugunthan V N wrote:
> >>>
> >>>> store the physical address of the device in its priv to use it
> >>>> for DMA addressing in the client drivers.
> >>>>
> >>>> Signed-off-by: Mugunthan V N <mugunthanvnm-l0cyMroinI0@public.gmane.org>
> >>>> ---
> >>>> drivers/mfd/ti_am335x_tscadc.c | 1 +
> >>>> include/linux/mfd/ti_am335x_tscadc.h | 1 +
> >>>> 2 files changed, 2 insertions(+)
> >>>>
> >>>> diff --git a/drivers/mfd/ti_am335x_tscadc.c b/drivers/mfd/ti_am335x_tscadc.c
> >>>> index c8f027b..0f3fab4 100644
> >>>> --- a/drivers/mfd/ti_am335x_tscadc.c
> >>>> +++ b/drivers/mfd/ti_am335x_tscadc.c
> >>>> @@ -183,6 +183,7 @@ static int ti_tscadc_probe(struct platform_device *pdev)
> >>>> tscadc->irq = err;
> >>>>
> >>>> res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> >>>> + tscadc->tscadc_phys_base = res->start;
> >>>
> >>> This is unusual. Can't you use a virt_to_phys() variant instead?
> >>>
> >>
> >> I tried using virt_to_phys(), but its not working for me.
> >> Also saw many drivers uses like this to get physical address
> >> ("git grep -n " res->start;" drivers/*").
> >
> > Very well:
> >
> > For my own reference:
> > Acked-for-MFD-by: Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >
> > Let me know how you wish this set to be handled.
> I'm happy to pick up the whole series. There are some more mfd
> header changes in patch 2 but as they only add defines, I
> don't mind that much if I don't an Ack from you on those
> (btw this got to V3 but as patch 1 didn't change I'll carry
> your ack forwards).
>
> Do you want an immutable branch? Seems unlikely to cause
> much trouble even if there is a merge issue on all 10ish
> lines of mfd code in the next merge window.
Not at the moment, but if you could set things up so it's possible to
create one at a later date if things go Pete Tong, that would be
great.
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Simon Horman @ 2016-10-31 8:19 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Philipp Zabel, Magnus Damm,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAMuHMdVbpuv94x-ocTSDoEj+SbnESDbkuMXsXExQvoyZepp+Zg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Wed, Oct 26, 2016 at 02:00:24PM +0200, Geert Uytterhoeven wrote:
> Hi Mike, Stephen,
>
> On Fri, Oct 21, 2016 at 3:17 PM, Geert Uytterhoeven
> <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> wrote:
> > Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
> > state of the mode pins either by a call from the platform code, or
> > directly by using a hardcoded register access. This is a bit messy, and
> > creates a dependency between driver and platform code.
> >
> > This patch series converts the various Renesas R-Car clock drivers
> > and support code from reading the mode pin states using a hardcoded
> > register access to using a new minimalistic R-Car RST driver.
> >
> > All R-Car clock drivers will rely on the presence in DT of a device node
> > for the RST module. Backwards compatibility with old DTBs is retained
> > only for R-Car Gen2, which has fallback code using its own private copy
> > of rcar_gen2_read_mode_pins().
> >
> > After this, there is still one remaining user of
> > rcar_gen2_read_mode_pins() left in platform code. A patch series to
> > remove that user has already been posted, though ("[PATCH/RFT 0/4] ARM:
> > shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode").
> > Since v3, the other user has been removed in commit 9f5ce39ddb8f68b3
> > ("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT").
> >
> > This series consists of 5 parts:
> > A. Patches 1 and 2 add DT bindings and driver code for the R-Car RST
> > driver,
> > B. Patches 3-11 add device nodes for the RST modules to the R-Car DTS
> > files,
> > C. Patches 12-17 convert the clock drivers to call into the new R-Car
> > RST driver,
> > D. Patches 18-20 remove passing mode pin state to the clock drivers
> > from the platform code,
> > E. Patches 21-23 remove dead code from the clock drivers.
> >
> > As is usually the case with moving functionality from platform code to
> > DT, there are lots of hard dependencies:
> > - The DT updates in Part B can be merged as soon as the DT bindings in
> > Part A have been approved,
> > - The clock driver updates in Part C depend functionally on the driver
> > code in Part A, and on the DT updates in Part B,
> > - The board code cleanups in Part D depend on the clock driver updates
> > in Part C,
> > - The block driver cleanups in part E depend on the board code
> > cleanups in part D.
> >
> > Hence to maintain the required lockstep between SoC driver, clock
> > drivers, shmobile platform code, and shmobile DT, I propose to queue up
> > all patches in a single branch against v4.9-rc1, and send pull requests
> > to both Mike/Stephen (clock) and Simon (rest).
> >
> > ***
>
> > - Mike/Stephen/Simon/Magnus: Are you OK with the suggested merge
> > approach above?
>
> Is this OK for you?
>
> I'd like to move forward with this, as this is a prerequisite for adding
> support for new SoCs (RZ/G) without adding more copies of
> rcar_gen2_read_mode_pins(), and removing that function from platform code
> for good.
This seems reasonable to me but likely the ARM SoC maintainers will want to
know about this plan before it is executed.
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^ permalink raw reply
* Re: [RESEND][PATCH] crypto: caam: add support for iMX6UL
From: Russell King - ARM Linux @ 2016-10-31 8:20 UTC (permalink / raw)
To: Marcus Folkesson
Cc: Herbert Xu, David S . Miller, Rob Herring, Mark Rutland,
Horia Geanta, Arnd Bergmann, Alex Porosanu, Srinivas Kandagatla,
Baoyou Xie, linux-crypto-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1476703680-22676-1-git-send-email-marcus.folkesson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, Oct 17, 2016 at 01:28:00PM +0200, Marcus Folkesson wrote:
> i.MX6UL does only require three clocks to enable CAAM module.
>
> Signed-off-by: Marcus Folkesson <marcus.folkesson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Horia Geantă <horia.geanta-3arQi8VN3Tc@public.gmane.org>
> ---
> .../devicetree/bindings/crypto/fsl-sec4.txt | 20 +++++++++++++
> drivers/crypto/caam/ctrl.c | 35 ++++++++++++----------
> 2 files changed, 40 insertions(+), 15 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> index adeca34..10a425f 100644
> --- a/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> +++ b/Documentation/devicetree/bindings/crypto/fsl-sec4.txt
> @@ -123,6 +123,9 @@ PROPERTIES
>
>
> EXAMPLE
> +
> +iMX6QDL/SX requires four clocks
> +
> crypto@300000 {
> compatible = "fsl,sec-v4.0";
> fsl,sec-era = <2>;
> @@ -139,6 +142,23 @@ EXAMPLE
> clock-names = "mem", "aclk", "ipg", "emi_slow";
> };
>
> +
> +iMX6UL does only require three clocks
> +
> + crypto: caam@2140000 {
> + compatible = "fsl,sec-v4.0";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0x2140000 0x3c000>;
> + ranges = <0 0x2140000 0x3c000>;
> + interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
> +
> + clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
> + <&clks IMX6UL_CLK_CAAM_ACLK>,
> + <&clks IMX6UL_CLK_CAAM_IPG>;
> + clock-names = "mem", "aclk", "ipg";
> + };
> +
> =====================================================================
> Job Ring (JR) Node
>
> diff --git a/drivers/crypto/caam/ctrl.c b/drivers/crypto/caam/ctrl.c
> index 0ec112e..5abaf37 100644
> --- a/drivers/crypto/caam/ctrl.c
> +++ b/drivers/crypto/caam/ctrl.c
> @@ -329,8 +329,8 @@ static int caam_remove(struct platform_device *pdev)
> clk_disable_unprepare(ctrlpriv->caam_ipg);
> clk_disable_unprepare(ctrlpriv->caam_mem);
> clk_disable_unprepare(ctrlpriv->caam_aclk);
> - clk_disable_unprepare(ctrlpriv->caam_emi_slow);
> -
> + if (!of_machine_is_compatible("fsl,imx6ul"))
> + clk_disable_unprepare(ctrlpriv->caam_emi_slow);
There is no need to re-lookup the platform here. Can't you check the
validity of ctrlpriv->caam_emi_slow ?
> return 0;
> }
>
> @@ -481,14 +481,16 @@ static int caam_probe(struct platform_device *pdev)
> }
> ctrlpriv->caam_aclk = clk;
>
> - clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
> - if (IS_ERR(clk)) {
> - ret = PTR_ERR(clk);
> - dev_err(&pdev->dev,
> - "can't identify CAAM emi_slow clk: %d\n", ret);
> - return ret;
> + if (!of_machine_is_compatible("fsl,imx6ul")) {
> + clk = caam_drv_identify_clk(&pdev->dev, "emi_slow");
> + if (IS_ERR(clk)) {
> + ret = PTR_ERR(clk);
> + dev_err(&pdev->dev,
> + "can't identify CAAM emi_slow clk: %d\n", ret);
> + return ret;
> + }
> + ctrlpriv->caam_emi_slow = clk;
> }
> - ctrlpriv->caam_emi_slow = clk;
>
> ret = clk_prepare_enable(ctrlpriv->caam_ipg);
> if (ret < 0) {
> @@ -509,11 +511,13 @@ static int caam_probe(struct platform_device *pdev)
> goto disable_caam_mem;
> }
>
> - ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
> - if (ret < 0) {
> - dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
> - ret);
> - goto disable_caam_aclk;
> + if (!of_machine_is_compatible("fsl,imx6ul")) {
Same here.
> + ret = clk_prepare_enable(ctrlpriv->caam_emi_slow);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "can't enable CAAM emi slow clock: %d\n",
> + ret);
> + goto disable_caam_aclk;
> + }
> }
>
> /* Get configuration properties from device tree */
> @@ -829,7 +833,8 @@ caam_remove:
> iounmap_ctrl:
> iounmap(ctrl);
> disable_caam_emi_slow:
> - clk_disable_unprepare(ctrlpriv->caam_emi_slow);
> + if (!of_machine_is_compatible("fsl,imx6ul"))
> + clk_disable_unprepare(ctrlpriv->caam_emi_slow);
and here.
> disable_caam_aclk:
> clk_disable_unprepare(ctrlpriv->caam_aclk);
> disable_caam_mem:
> --
> 2.8.0
>
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
according to speedtest.net.
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^ permalink raw reply
* Re: [PATCH] arm64: dts: r8a7795: salvator-x: add bias setting for usb1_pins
From: Simon Horman @ 2016-10-31 8:23 UTC (permalink / raw)
To: Yoshihiro Shimoda
Cc: magnus.damm, robh+dt, mark.rutland, devicetree, linux-renesas-soc
In-Reply-To: <1477564167-22422-1-git-send-email-yoshihiro.shimoda.uh@renesas.com>
On Thu, Oct 27, 2016 at 07:29:27PM +0900, Yoshihiro Shimoda wrote:
> Since this board doesn't mount pull-up/down registers for
> USB1_{OVC,PWEN} pins, we should enable bias setting to pull these
> pins up/down.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Thanks, I have queued this up.
^ permalink raw reply
* Re: [PATCH v2] iommu/ipmmu-vmsa: Add r8a7796 DT binding
From: Simon Horman @ 2016-10-31 8:28 UTC (permalink / raw)
To: Rob Herring
Cc: Magnus Damm, devicetree, mark.rutland, laurent.pinchart+renesas,
geert+renesas, joro, linux-kernel, linux-renesas-soc, iommu
In-Reply-To: <20161031051516.zpmoynwudyxlvppg@rob-hp-laptop>
On Mon, Oct 31, 2016 at 12:15:16AM -0500, Rob Herring wrote:
> On Thu, Oct 27, 2016 at 07:45:10PM +0900, Magnus Damm wrote:
> > From: Magnus Damm <damm+renesas@opensource.se>
> >
> > Update the IPMMU DT binding documentation to include the r8a7796 compat
> > string for R-Car M3-W.
> >
> > Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
> > Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> >
> > Changes since V1:
> > - Added Acked-by from Laurent - thanks!
> >
> > Now broken out, however earlier V1 posted as part of:
> > [PATCH 0/3] iommu/ipmmu-vmsa: Initial r8a7796 support
> >
> > Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.txt | 1 +
> > 1 file changed, 1 insertion(+)
>
> Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* Re: [PATCH v4 00/23] soc: renesas: Add R-Car RST driver for obtaining mode pin state
From: Geert Uytterhoeven @ 2016-10-31 8:32 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Arnd Bergmann, Olof Johansson,
Kevin Hilman
Cc: Philipp Zabel, Magnus Damm,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-Renesas,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Simon Horman
In-Reply-To: <20161031081923.GF18195-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Hi Mike, Stephen, Arnd, Olof, Kevin,
Is the merge strategy [see ##### below] OK for you?
Thanks a lot!
On Mon, Oct 31, 2016 at 9:19 AM, Simon Horman <horms-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> On Wed, Oct 26, 2016 at 02:00:24PM +0200, Geert Uytterhoeven wrote:
>> On Fri, Oct 21, 2016 at 3:17 PM, Geert Uytterhoeven
>> <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org> wrote:
>> > Currently the R-Car Clock Pulse Generator (CPG) drivers obtains the
>> > state of the mode pins either by a call from the platform code, or
>> > directly by using a hardcoded register access. This is a bit messy, and
>> > creates a dependency between driver and platform code.
>> >
>> > This patch series converts the various Renesas R-Car clock drivers
>> > and support code from reading the mode pin states using a hardcoded
>> > register access to using a new minimalistic R-Car RST driver.
>> >
>> > All R-Car clock drivers will rely on the presence in DT of a device node
>> > for the RST module. Backwards compatibility with old DTBs is retained
>> > only for R-Car Gen2, which has fallback code using its own private copy
>> > of rcar_gen2_read_mode_pins().
>> >
>> > After this, there is still one remaining user of
>> > rcar_gen2_read_mode_pins() left in platform code. A patch series to
>> > remove that user has already been posted, though ("[PATCH/RFT 0/4] ARM:
>> > shmobile: R-Car Gen2: Allow booting secondary CPU cores in debug mode").
>> > Since v3, the other user has been removed in commit 9f5ce39ddb8f68b3
>> > ("ARM: shmobile: rcar-gen2: Obtain extal frequency from DT").
>> >
>> > This series consists of 5 parts:
>> > A. Patches 1 and 2 add DT bindings and driver code for the R-Car RST
>> > driver,
>> > B. Patches 3-11 add device nodes for the RST modules to the R-Car DTS
>> > files,
>> > C. Patches 12-17 convert the clock drivers to call into the new R-Car
>> > RST driver,
>> > D. Patches 18-20 remove passing mode pin state to the clock drivers
>> > from the platform code,
>> > E. Patches 21-23 remove dead code from the clock drivers.
>> >
>> > As is usually the case with moving functionality from platform code to
>> > DT, there are lots of hard dependencies:
>> > - The DT updates in Part B can be merged as soon as the DT bindings in
>> > Part A have been approved,
>> > - The clock driver updates in Part C depend functionally on the driver
>> > code in Part A, and on the DT updates in Part B,
>> > - The board code cleanups in Part D depend on the clock driver updates
>> > in Part C,
>> > - The block driver cleanups in part E depend on the board code
>> > cleanups in part D.
>> >
>> > Hence to maintain the required lockstep between SoC driver, clock
>> > drivers, shmobile platform code, and shmobile DT, I propose to queue up
>> > all patches in a single branch against v4.9-rc1, and send pull requests
>> > to both Mike/Stephen (clock) and Simon (rest).
>> >
>> > ***
>>
>> > - Mike/Stephen/Simon/Magnus: Are you OK with the suggested merge
>> > approach above?
>>
>> Is this OK for you?
#####
(link to the full series at
https://groups.google.com/forum/#!topic/linux.kernel/fLSFsjOgPT8)
>>
>> I'd like to move forward with this, as this is a prerequisite for adding
>> support for new SoCs (RZ/G) without adding more copies of
>> rcar_gen2_read_mode_pins(), and removing that function from platform code
>> for good.
>
> This seems reasonable to me but likely the ARM SoC maintainers will want to
> know about this plan before it is executed.
OK, adding more people in the loop...
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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^ permalink raw reply
* Re: [PATCH V2] pinctrl: qcom: Add msm8994 pinctrl driver
From: Linus Walleij @ 2016-10-31 8:33 UTC (permalink / raw)
To: Bjorn Andersson
Cc: Michael Scott, linux-gpio@vger.kernel.org,
linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Rob Herring, Mark Rutland,
Andy Gross, David Brown, Joonwoo Park, Jeremy McNicoll
In-Reply-To: <20161029180658.GD25787@tuxbot>
On Sat, Oct 29, 2016 at 8:06 PM, Bjorn Andersson
<bjorn.andersson@linaro.org> wrote:
> Please add the compatible and you have my
>
> Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Michael, please add this compatible, add the ACKs and resend and I'll
queue the patch.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH V3 1/2] iio: adc: spmi-vadc: Update changes to support reporting of Raw adc code.
From: Rama Krishna Phani A @ 2016-10-31 8:48 UTC (permalink / raw)
To: Jonathan Cameron, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh-DgEjT+Ai2ygdnm+yROfE0A, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
smohanad-sgV2jX0FEOL9JmXXK+q4OQ, mgautam-sgV2jX0FEOL9JmXXK+q4OQ,
sivaa-sgV2jX0FEOL9JmXXK+q4OQ, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
Julia.Lawall-L2FTfq7BK8M
In-Reply-To: <ee44e76a-b7e1-63b2-2251-6247d9e6bb9d-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Hi Jonathan,
On 30-Oct-16 11:05 PM, Jonathan Cameron wrote:
> On 26/10/16 15:41, Rama Krishna Phani A wrote:
>> Logic to convert adc code to voltage is generic across all channels.
>> Different scaling can be done on the obtained voltage to report in physical
>> units. Implement separate function for generic conversion logic.
>> Scaling functionality can be changed per channel. Update changes to support
>> reporting of Raw adc code.
> Pleas rewrite this description. Perhaps give examples of the changes
> it makes to what is read from the various attributes?
There are several channels in the ADC of PMIC which can be used to
measure voltage, temperature, current etc., Hardware provides readings
for all channels in adc code. That adc code needs to be converted to
voltage. The logic for conversion of adc code to voltage is common for
all ADC channels(voltage, temperature and current .,etc). Once voltage
is obtained ., scaling is done on that voltage.
For Ex., Thermal SW wants to know the temperature of thermistor on PMIC
and it expects the temperature to be reported in millidegC. ADC channel
is used to read the adc code and convert it to voltage. Once the voltage
is available based on the thermistor spec that voltage is mapped to a
temperature and then that value is reported to Thermal SW.
Mapping of voltage to temperature is called scaling for that channel and
scaling function can be different per channel based on how the voltage
is reported.
>
> I haven't immediately followed what this change is actually doing.
>
> I 'think' the point here is to not apply the calibration to
> the raw adc counts when a true raw read is requested?
>
When a true raw read is requested .,Scaling is not applied.
> There are several unconnected looking changes in here...
>>
>> Signed-off-by: Rama Krishna Phani A <rphani-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>> drivers/iio/adc/qcom-spmi-vadc.c | 54 +++++++++++++++++++++-------------------
>> 1 file changed, 28 insertions(+), 26 deletions(-)
>>
>> diff --git a/drivers/iio/adc/qcom-spmi-vadc.c b/drivers/iio/adc/qcom-spmi-vadc.c
>> index c2babe5..ff4d549 100644
>> --- a/drivers/iio/adc/qcom-spmi-vadc.c
>> +++ b/drivers/iio/adc/qcom-spmi-vadc.c
>> @@ -1,5 +1,5 @@
>> /*
>> - * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
>> + * Copyright (c) 2012-2016, The Linux Foundation. All rights reserved.
>> *
>> * This program is free software; you can redistribute it and/or modify
>> * it under the terms of the GNU General Public License version 2 and
>> @@ -84,7 +84,7 @@
>> #define VADC_MAX_ADC_CODE 0xa800
>>
>> #define VADC_ABSOLUTE_RANGE_UV 625000
>> -#define VADC_RATIOMETRIC_RANGE_UV 1800000
>> +#define VADC_RATIOMETRIC_RANGE 1800
>>
>> #define VADC_DEF_PRESCALING 0 /* 1:1 */
>> #define VADC_DEF_DECIMATION 0 /* 512 */
>> @@ -418,7 +418,7 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
>> u16 read_1, read_2;
>> int ret;
>>
>> - vadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE_UV;
>> + vadc->graph[VADC_CALIB_RATIOMETRIC].dx = VADC_RATIOMETRIC_RANGE;
>> vadc->graph[VADC_CALIB_ABSOLUTE].dx = VADC_ABSOLUTE_RANGE_UV;
>>
>> prop = vadc_get_channel(vadc, VADC_REF_1250MV);
>> @@ -468,21 +468,30 @@ static int vadc_measure_ref_points(struct vadc_priv *vadc)
>> return ret;
>> }
>>
>> -static s32 vadc_calibrate(struct vadc_priv *vadc,
>> - const struct vadc_channel_prop *prop, u16 adc_code)
>> +static void vadc_scale_calib(struct vadc_priv *vadc, u16 adc_code,
>> + const struct vadc_channel_prop *prop,
>> + s64 *scale_voltage)
>> {
>> - const struct vadc_prescale_ratio *prescale;
>> - s64 voltage;
>> + *scale_voltage = (adc_code -
>> + vadc->graph[prop->calibration].gnd);
>> + *scale_voltage *= vadc->graph[prop->calibration].dx;
>> + *scale_voltage = div64_s64(*scale_voltage,
>> + vadc->graph[prop->calibration].dy);
>> + if (prop->calibration == VADC_CALIB_ABSOLUTE)
>> + *scale_voltage +=
>> + vadc->graph[prop->calibration].dx;
>>
>> - voltage = adc_code - vadc->graph[prop->calibration].gnd;
>> - voltage *= vadc->graph[prop->calibration].dx;
>> - voltage = div64_s64(voltage, vadc->graph[prop->calibration].dy);
>> + if (*scale_voltage < 0)
>> + *scale_voltage = 0;
>> +}
>>
>> - if (prop->calibration == VADC_CALIB_ABSOLUTE)
>> - voltage += vadc->graph[prop->calibration].dx;
>> +static s64 vadc_scale_fn(struct vadc_priv *vadc,
>> + const struct vadc_channel_prop *prop, u16 adc_code)
>> +{
>> + const struct vadc_prescale_ratio *prescale;
>> + s64 voltage = 0;
>>
>> - if (voltage < 0)
>> - voltage = 0;
>> + vadc_scale_calib(vadc, adc_code, prop, &voltage);
>>
>> prescale = &vadc_prescale_ratios[prop->prescale];
>>
>> @@ -552,11 +561,8 @@ static int vadc_read_raw(struct iio_dev *indio_dev,
>> if (ret)
>> break;
>>
>> - *val = vadc_calibrate(vadc, prop, adc_code);
>> + *val = vadc_scale_fn(vadc, prop, adc_code);
>>
>> - /* 2mV/K, return milli Celsius */
>> - *val /= 2;
>> - *val -= KELVINMIL_CELSIUSMIL;
>> return IIO_VAL_INT;
>> case IIO_CHAN_INFO_RAW:
>> prop = &vadc->chan_props[chan->address];
>> @@ -564,12 +570,8 @@ static int vadc_read_raw(struct iio_dev *indio_dev,
>> if (ret)
>> break;
>>
>> - *val = vadc_calibrate(vadc, prop, adc_code);
>> + *val = (int)adc_code;
>> return IIO_VAL_INT;
> So this is 'more raw'.
Yes., its raw value.
>> - case IIO_CHAN_INFO_SCALE:
>> - *val = 0;
>> - *val2 = 1000;
>> - return IIO_VAL_INT_PLUS_MICRO;
>> default:
>> ret = -EINVAL;
>> break;
>> @@ -616,8 +618,8 @@ struct vadc_channels {
>> VADC_CHAN(_dname, IIO_TEMP, BIT(IIO_CHAN_INFO_PROCESSED), _pre) \
>>
>> #define VADC_CHAN_VOLT(_dname, _pre) \
>> - VADC_CHAN(_dname, IIO_VOLTAGE, \
>> - BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_SCALE), \
>> + VADC_CHAN(_dname, IIO_VOLTAGE, \
>> + BIT(IIO_CHAN_INFO_RAW) | BIT(IIO_CHAN_INFO_PROCESSED),\
>> _pre) \
> It very unusual to report both raw and processed values. Please explain
> why that is needed here? It may be valid to maintain backwards compatibility
> of ABI. Which would be fine. However if I read the above correctly you are
> changing what comes out of reading the raw value so the ABI just changed...
>
With the help of IIO sysfs ., we can read the ADC channel readings
either in RAW format or in processed format. There are two separate
individual entries to read the ADC channel either in Raw format or in
processed format. Most of the clients for ADC expect the readings in
processed format.
>
>>
>> /*
>> @@ -850,9 +852,9 @@ static int vadc_get_dt_data(struct vadc_priv *vadc, struct device_node *node)
>>
>> iio_chan->channel = prop.channel;
>> iio_chan->datasheet_name = vadc_chan->datasheet_name;
>> + iio_chan->extend_name = child->name;
> What's this change?
We can choose how we want to display our adc channel entries in sysfs.
Am using the child node name to be displayed as the sysfs entry rather
than channel number for easy interpretation.
For ex: for vcoin(coin battery voltage channel.,) with this change it
appears like below in iio adc sysfs
"in_voltage_vcoin_input"
>> iio_chan->info_mask_separate = vadc_chan->info_mask;
>> iio_chan->type = vadc_chan->type;
>> - iio_chan->indexed = 1;
> Or for that matter this one...
reason explained above.
>> iio_chan->address = index++;
>>
>> iio_chan++;
>>
>
Thanks,
Ramakrishna
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^ permalink raw reply
* Re: [PATCH 5/5] irqchip: st: Remove obsolete platforms from dt binding doc
From: Peter Griffin @ 2016-10-31 9:06 UTC (permalink / raw)
To: patrice.chotard-qxv4g6HH51o
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kernel-F5mvAk5X5gdBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
lee.jones-QSEj5FYQhm4dnm+yROfE0A, tglx-hfZtesqFncYOwBW4kG4KsQ,
jason-NLaQJdtUoK4Be96aLqz0jA, marc.zyngier-5wv7dgnIgG8
In-Reply-To: <1477065443-10668-6-git-send-email-patrice.chotard-qxv4g6HH51o@public.gmane.org>
On Fri, 21 Oct 2016, patrice.chotard-qxv4g6HH51o@public.gmane.org wrote:
> From: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
>
> STiH415/6 SoC support is being removed from the kernel.
> This patch updates the sti irchip and removes
> references to these obsolete platforms.
>
> Signed-off-by: Patrice Chotard <patrice.chotard-qxv4g6HH51o@public.gmane.org>
> Cc: <tglx-hfZtesqFncYOwBW4kG4KsQ@public.gmane.org>
> Cc: <jason-NLaQJdtUoK4Be96aLqz0jA@public.gmane.org>
> Cc: <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
> ---
> .../devicetree/bindings/interrupt-controller/st,sti-irq-syscfg.txt | 6 ++----
> 1 file changed, 2 insertions(+), 4 deletions(-)
Acked-by: Peter Griffin <peter.griffin-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH V3 2/2] iio: adc: spmi-vadc: Changes to support different scaling
From: Stanimir Varbanov @ 2016-10-31 9:26 UTC (permalink / raw)
To: Rama Krishna Phani A, Jonathan Cameron, linux-iio, devicetree
Cc: robh, linux-arm-msm, smohanad, mgautam, sivaa, knaack.h, lars,
pmeerw, Julia.Lawall
In-Reply-To: <812bb533-0f19-7abc-1fa1-9e83f1db10f4@codeaurora.org>
Hi Rama,
On 10/31/2016 09:12 AM, Rama Krishna Phani A wrote:
> Hi Jonathan,
>
> On 30-Oct-16 10:43 PM, Jonathan Cameron wrote:
>> On 27/10/16 18:37, Phani A, Rama Krishna wrote:
>>> Hi Stan,
>>>
>>> On 27-Oct-16 4:48 PM, Stanimir Varbanov wrote:
>>>> Hi Rama,
>>>>
>>>> On 10/26/2016 05:41 PM, Rama Krishna Phani A wrote:
>>>>> Polling can also be used for End of conversion completion.
>>>>> Implement logic
>>>>> to choose either polling or interrupt for End of conversion
>>>>> completion.
>>>>> Scaling can be done on the voltage to report adc code in physical
>>>>> units.
>>>>> Add changes to support different scale functions to convert adc
>>>>> code to
>>>>> physical units.
>>>>>
>>>>> Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
>>>>> ---
>>>>> .../devicetree/bindings/iio/adc/qcom,spmi-vadc.txt | 14 ++
>>>>> drivers/iio/adc/qcom-spmi-vadc.c | 263
>>>>> +++++++++++++++++----
>>>>> 2 files changed, 236 insertions(+), 41 deletions(-)
>>>>>
>>>>> diff --git
>>>>> a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>>> b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>>> index 0fb4613..39e31c0e 100644
>>>>> --- a/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>>> +++ b/Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc.txt
>>>>> @@ -37,6 +37,12 @@ VADC node:
>>>>> Value type: <prop-encoded-array>
>>>>> Definition: End of conversion interrupt.
>>>>>
>>>>> +- qcom,vadc-poll-eoc:
>>>>> + Usage: optional
>>>>> + Value type: <bool>
>>>>> + Definition: Use polling instead of interrupts for End of
>>>>> Conversion
>>>>> + completion.
>>>>
>>>> Why you need to add such a flag in DT?
>>>>
>>>> The DT should describe hardware details not how the driver will choose
>>>> pooling vs interrupt.
>>>>
>>>> On which use-case you would prefer pooling?
>>>>
>>>
>>> Few PMIC's support interrupt functionality for ADC where as few
>>> PMIC's dont support. Based on the functionality that is supported in
>>> hardware we choose whether to go for polling or for interrupt.
>> Can't use the usual trick of an optional interrupt in DT?
>> If it's there we try to use it, if not then fall back to polling?
>>
> Ok., Will check this logic for implementation and will post next patch.
The interrupts DT property in binding doc is marked as optional already,
so I can't really understand what you are trying to achieve with this
new qcom,vadc-poll-eoc boolean property?
--
regards,
Stan
^ permalink raw reply
* RE: [v15, 6/7] base: soc: introduce soc_device_match() interface
From: Y.B. Lu @ 2016-10-31 9:28 UTC (permalink / raw)
To: Arnd Bergmann,
linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
Cc: Mark Rutland, ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org,
Geert Uytterhoeven,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, M.H. Lian,
linux-i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Qiang Zhao,
Russell King, Bhupesh Sharma, Claudiu Manoil,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Kumar Gala,
Scott Wood, Rob Herring, Santosh Shilimkar,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Greg Kroah-Hartman,
"linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <linux-mmc>
In-Reply-To: <2572890.e6aV4hmMEL@wuerfel>
> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd-r2nGTMty4D4@public.gmane.org]
> Sent: Friday, October 28, 2016 6:48 PM
> To: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ@public.gmane.org
> Cc: Y.B. Lu; linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org; Scott
> Wood; Mark Rutland; Greg Kroah-Hartman; X.B. Xie; M.H. Lian; linux-
> i2c-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-clk-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Qiang Zhao; Russell King;
> Bhupesh Sharma; Joerg Roedel; Claudiu Manoil; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> Rob Herring; Santosh Shilimkar; linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org;
> netdev-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Leo Li;
> iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org; Kumar Gala; Geert Uytterhoeven
> Subject: Re: [v15, 6/7] base: soc: introduce soc_device_match() interface
>
> On Friday, October 28, 2016 2:50:17 PM CEST Yangbo Lu wrote:
> > +
> > +static int soc_device_match_one(struct device *dev, void *arg) {
> > + struct soc_device *soc_dev = container_of(dev, struct
> soc_device, dev);
> > + const struct soc_device_attribute *match = arg;
> > +
> > + if (match->machine &&
> > + !glob_match(match->machine, soc_dev->attr->machine))
> > + return 0;
> > +
> > + if (match->family &&
> > + !glob_match(match->family, soc_dev->attr->family))
> > + return 0;
> > +
> >
>
> Geert found a bug in my code, and submitted a fix at
> https://patchwork.kernel.org/patch/9361395/
>
> I think you should include that one in your series.
>
[Lu Yangbo-B47093] Ok, no problem. Thanks :)
> Arnd
^ permalink raw reply
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