* [PATCH 2/3] drm/bridge: Add ti-ftp410 HDMI transmitter driver
From: Jyri Sarha @ 2016-11-02 16:32 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: bcousson, khilman, Jyri Sarha, bgolaszewski, tomi.valkeinen,
laurent.pinchart
In-Reply-To: <cover.1478103726.git.jsarha@ti.com>
Add very basic ti-ftp410 HDMI transmitter driver. The only feature
separating this from a completely dummy bridge is the DDC i2c
support. However, other HW specific features may be added later when
needed. For instance there is a set of registers behind i2c if it is
connected. The implementations is tested against my new tilcdc bridge
support and works with BeagleBone DVI-D Cape Rev A3. A DT binding
document is also added.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
.../bindings/display/bridge/ti,tfp410.txt | 30 ++++
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ti-tfp410.c | 199 +++++++++++++++++++++
4 files changed, 237 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
create mode 100644 drivers/gpu/drm/bridge/ti-tfp410.c
diff --git a/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt b/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
new file mode 100644
index 0000000..dc93713
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
@@ -0,0 +1,30 @@
+TFP410 HDMI/DVI bridge bindings
+
+Required properties:
+ - compatible: "ti,tfp410"
+
+Optional properties:
+ - ddc-i2c: phandle of an I2C controller used for DDC EDID probing
+
+Optional subnodes:
+ - video input: this subnode can contain a video input port node
+ to connect the bridge to a display controller output (See this
+ documentation [1]).
+
+[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+
+Example:
+ hdmi-bridge {
+ compatible = "ti,tfp410";
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ bridge_in: endpoint {
+ remote-endpoint = <&dc_out>;
+ };
+ };
+ };
+ };
diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
index bd6acc8..a424e03 100644
--- a/drivers/gpu/drm/bridge/Kconfig
+++ b/drivers/gpu/drm/bridge/Kconfig
@@ -81,6 +81,13 @@ config DRM_TOSHIBA_TC358767
---help---
Toshiba TC358767 eDP bridge chip driver.
+config DRM_TI_TFP410
+ tristate "TI TFP410 DVI/HDMI bridge"
+ depends on OF
+ select DRM_KMS_HELPER
+ ---help---
+ Texas Instruments TFP410 DVI/HDMI Transmitter driver
+
source "drivers/gpu/drm/bridge/analogix/Kconfig"
source "drivers/gpu/drm/bridge/adv7511/Kconfig"
diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
index 97ed1a5..8b065d9 100644
--- a/drivers/gpu/drm/bridge/Makefile
+++ b/drivers/gpu/drm/bridge/Makefile
@@ -11,3 +11,4 @@ obj-$(CONFIG_DRM_SII902X) += sii902x.o
obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
obj-$(CONFIG_DRM_I2C_ADV7511) += adv7511/
+obj-$(CONFIG_DRM_TI_TFP410) += ti-tfp410.o
diff --git a/drivers/gpu/drm/bridge/ti-tfp410.c b/drivers/gpu/drm/bridge/ti-tfp410.c
new file mode 100644
index 0000000..b0753d2
--- /dev/null
+++ b/drivers/gpu/drm/bridge/ti-tfp410.c
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2016 Texas Instruments
+ * Author: Jyri Sarha <jsarha@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of_graph.h>
+
+#include <drm/drmP.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_crtc_helper.h>
+
+struct tfp410 {
+ struct drm_bridge bridge;
+ struct drm_connector connector;
+
+ struct i2c_adapter *ddc;
+
+ struct device *dev;
+};
+
+static inline struct tfp410 *
+drm_bridge_to_tfp410(struct drm_bridge *bridge)
+{
+ return container_of(bridge, struct tfp410, bridge);
+}
+
+static inline struct tfp410 *
+drm_connector_to_tfp410(struct drm_connector *connector)
+{
+ return container_of(connector, struct tfp410, connector);
+}
+
+static int tfp410_get_modes(struct drm_connector *connector)
+{
+ struct tfp410 *hdmi = drm_connector_to_tfp410(connector);
+ struct edid *edid;
+ int ret;
+
+ if (!hdmi->ddc)
+ goto fallback;
+
+ edid = drm_get_edid(connector, hdmi->ddc);
+ if (!edid) {
+ DRM_INFO("EDID read failed. Fallback to standard modes\n");
+ goto fallback;
+ }
+
+ drm_mode_connector_update_edid_property(connector, edid);
+
+ return drm_add_edid_modes(connector, edid);
+fallback:
+ /* No EDID, fallback on the XGA standard modes */
+ ret = drm_add_modes_noedid(connector, 1920, 1200);
+
+ /* And prefer a mode pretty much anything can handle */
+ drm_set_preferred_mode(connector, 1024, 768);
+
+ return ret;
+}
+
+static const struct drm_connector_helper_funcs tfp410_con_helper_funcs = {
+ .get_modes = tfp410_get_modes,
+};
+
+static enum drm_connector_status
+tfp410_connector_detect(struct drm_connector *connector, bool force)
+{
+ struct tfp410 *hdmi = drm_connector_to_tfp410(connector);
+
+ if (hdmi->ddc) {
+ if (drm_probe_ddc(hdmi->ddc))
+ return connector_status_connected;
+ else
+ return connector_status_disconnected;
+ }
+
+ return connector_status_unknown;
+}
+
+static const struct drm_connector_funcs tfp410_con_funcs = {
+ .dpms = drm_atomic_helper_connector_dpms,
+ .detect = tfp410_connector_detect,
+ .fill_modes = drm_helper_probe_single_connector_modes,
+ .destroy = drm_connector_cleanup,
+ .reset = drm_atomic_helper_connector_reset,
+ .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
+ .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
+};
+
+static int tfp410_attach(struct drm_bridge *bridge)
+{
+ struct tfp410 *hdmi = drm_bridge_to_tfp410(bridge);
+ int ret;
+
+ if (!bridge->encoder) {
+ dev_err(hdmi->dev, "Missing encoder\n");
+ return -ENODEV;
+ }
+
+ drm_connector_helper_add(&hdmi->connector,
+ &tfp410_con_helper_funcs);
+ ret = drm_connector_init(bridge->dev, &hdmi->connector,
+ &tfp410_con_funcs, DRM_MODE_CONNECTOR_HDMIA);
+ if (ret) {
+ dev_err(hdmi->dev, "drm_connector_init() failed: %d\n", ret);
+ return ret;
+ }
+
+ drm_mode_connector_attach_encoder(&hdmi->connector,
+ bridge->encoder);
+
+ return 0;
+}
+
+static const struct drm_bridge_funcs tfp410_bridge_funcs = {
+ .attach = tfp410_attach,
+};
+
+static int tfp410_probe(struct platform_device *pdev)
+{
+ struct device_node *ddc_phandle;
+ struct tfp410 *hdmi;
+ int ret;
+
+ if (!pdev->dev.of_node) {
+ dev_err(&pdev->dev, "device-tree data is missing\n");
+ return -ENXIO;
+ }
+
+ hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
+ if (!hdmi)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, hdmi);
+
+ ddc_phandle = of_parse_phandle(pdev->dev.of_node, "ddc-i2c", 0);
+ if (ddc_phandle) {
+ hdmi->ddc = of_get_i2c_adapter_by_node(ddc_phandle);
+ of_node_put(ddc_phandle);
+ if (!hdmi->ddc)
+ return -EPROBE_DEFER;
+ } else {
+ dev_info(&pdev->dev,
+ "No ddc i2c bus, disabling EDID readout\n");
+ }
+
+ hdmi->bridge.funcs = &tfp410_bridge_funcs;
+ hdmi->bridge.of_node = pdev->dev.of_node;
+ hdmi->dev = &pdev->dev;
+
+ ret = drm_bridge_add(&hdmi->bridge);
+ if (ret) {
+ dev_err(&pdev->dev, "drm_bridge_add() failed: %d\n", ret);
+ goto fail;
+ }
+
+ return 0;
+fail:
+ i2c_put_adapter(hdmi->ddc);
+ return ret;
+}
+
+static int tfp410_remove(struct platform_device *pdev)
+{
+ struct tfp410 *hdmi = platform_get_drvdata(pdev);
+
+ drm_bridge_remove(&hdmi->bridge);
+
+ if (hdmi->ddc)
+ i2c_put_adapter(hdmi->ddc);
+
+ return 0;
+}
+
+static const struct of_device_id tfp410_match[] = {
+ { .compatible = "ti,tfp410" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, tfp410_match);
+
+struct platform_driver tfp410_driver = {
+ .probe = tfp410_probe,
+ .remove = tfp410_remove,
+ .driver = {
+ .name = "tfp410-bridge",
+ .of_match_table = tfp410_match,
+ },
+};
+module_platform_driver(tfp410_driver);
+
+MODULE_AUTHOR("Jyri Sarha <jsarha@ti.com>");
+MODULE_DESCRIPTION("TI TFP410 HDMI bridge driver");
+MODULE_LICENSE("GPL");
--
1.9.1
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^ permalink raw reply related
* [PATCH 1/3] drm/tilcdc: Recover from sync lost error flood by resetting the LCDC
From: Jyri Sarha @ 2016-11-02 16:32 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: bcousson, khilman, Jyri Sarha, bgolaszewski, tomi.valkeinen,
laurent.pinchart
In-Reply-To: <cover.1478103726.git.jsarha@ti.com>
Recover from sync lost error flood by resetting the LCDC instead of
turning off the SYNC_LOST error IRQ. When LCDC starves on limited
memory bandwidth it may sometimes result an error situation when the
picture may have shifted couple of pixels to right and SYNC_LOST
interrupt is generated on every frame. LCDC main reset recovers from
this situation and causes a brief blanking on the screen.
Signed-off-by: Jyri Sarha <jsarha@ti.com>
---
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 26 +++++++++++++++++++++++++-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
index 0d09acc..c787349 100644
--- a/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
+++ b/drivers/gpu/drm/tilcdc/tilcdc_crtc.c
@@ -55,6 +55,7 @@ struct tilcdc_crtc {
int sync_lost_count;
bool frame_intact;
+ struct work_struct recover_work;
};
#define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
@@ -252,6 +253,25 @@ static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
return crtc->state && crtc->state->enable && crtc->state->active;
}
+static void tilcdc_crtc_recover_work(struct work_struct *work)
+{
+ struct tilcdc_crtc *tilcdc_crtc =
+ container_of(work, struct tilcdc_crtc, recover_work);
+ struct drm_crtc *crtc = &tilcdc_crtc->base;
+
+ dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
+
+ drm_modeset_lock_crtc(crtc, NULL);
+
+ if (!tilcdc_crtc_is_on(crtc))
+ goto out;
+
+ tilcdc_crtc_disable(crtc);
+ tilcdc_crtc_enable(crtc);
+out:
+ drm_modeset_unlock_crtc(crtc);
+}
+
static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
{
struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
@@ -838,9 +858,12 @@ irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
tilcdc_crtc->frame_intact = false;
if (tilcdc_crtc->sync_lost_count++ >
SYNC_LOST_COUNT_LIMIT) {
- dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, disabling the interrupt", __func__, stat);
+ dev_err(dev->dev, "%s(0x%08x): Sync lost flood detected, recovering", __func__, stat);
+ queue_work(system_wq,
+ &tilcdc_crtc->recover_work);
tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
LCDC_SYNC_LOST);
+ tilcdc_crtc->sync_lost_count = 0;
}
}
@@ -880,6 +903,7 @@ struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
"unref", unref_worker);
spin_lock_init(&tilcdc_crtc->irq_lock);
+ INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
ret = drm_crtc_init_with_planes(dev, crtc,
&tilcdc_crtc->primary,
--
1.9.1
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^ permalink raw reply related
* [PATCH 0/3] drm/tilcdc: Add bridge support and sync-lost flood recovery
From: Jyri Sarha @ 2016-11-02 16:32 UTC (permalink / raw)
To: dri-devel, devicetree
Cc: bcousson, khilman, Jyri Sarha, bgolaszewski, tomi.valkeinen,
laurent.pinchart
The first patch is an independent on and I've been testing it for
quite a while now.
The tfp410 bridge driver and the tilcdc bridge support are tested with
BeagleBone DVI-D Cape Rev A3. The tfp410 bridge driver is missing a
lot of features, because the DVI-D cape does not have too many wires
connected. They missing features can be added later when they are
needed.
Jyri Sarha (3):
drm/tilcdc: Recover from sync lost error flood by resetting the LCDC
drm/bridge: Add ti-ftp410 HDMI transmitter driver
drm/tilcdc: Add drm bridge support for attaching drm bridge drivers
.../bindings/display/bridge/ti,tfp410.txt | 30 ++++
.../devicetree/bindings/display/tilcdc/tilcdc.txt | 7 +-
drivers/gpu/drm/bridge/Kconfig | 7 +
drivers/gpu/drm/bridge/Makefile | 1 +
drivers/gpu/drm/bridge/ti-tfp410.c | 199 +++++++++++++++++++++
drivers/gpu/drm/tilcdc/tilcdc_crtc.c | 26 ++-
drivers/gpu/drm/tilcdc/tilcdc_drv.c | 7 +-
drivers/gpu/drm/tilcdc/tilcdc_drv.h | 2 +
drivers/gpu/drm/tilcdc/tilcdc_external.c | 140 +++++++++++++--
drivers/gpu/drm/tilcdc/tilcdc_external.h | 1 +
10 files changed, 397 insertions(+), 23 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/bridge/ti,tfp410.txt
create mode 100644 drivers/gpu/drm/bridge/ti-tfp410.c
--
1.9.1
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^ permalink raw reply
* Re: [PATCH] soc: qcom: Add SoC info driver
From: Bjorn Andersson @ 2016-11-02 16:28 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Imran Khan, andy.gross, David Brown, Rob Herring, Mark Rutland,
open list:ARM/QUALCOMM SUPPORT, open list:ARM/QUALCOMM SUPPORT,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, Geert Uytterhoeven
In-Reply-To: <3809309.oOnjdjqnN9@wuerfel>
On Wed 26 Oct 07:05 PDT 2016, Arnd Bergmann wrote:
> On Wednesday, October 26, 2016 7:20:42 PM CEST Imran Khan wrote:
> > On 10/26/2016 2:19 AM, Arnd Bergmann wrote:
> > > On Tuesday, October 25, 2016 3:23:34 PM CEST Imran Khan wrote:
> > >> On 10/21/2016 4:03 PM, Arnd Bergmann wrote:
> > >>>> +/* socinfo: sysfs functions */
> > >>>
> > >>> This seems overly verbose, having both raw and human-readable
> > >>> IDs is generally not necessary, pick one of the two. If you
> > >>> need any fields that we don't already support in soc_device,
> > >>> let's talk about adding them to the generic structure.
> > >>>
> > >>>
> > >>
> > >> Okay. I will go for human readable IDs. Can we add 2 more fields
> > >> in the generic structure.
> > >> These 2 fields would be:
> > >>
> > >> vendor: A string for vendor name
> > >> serial_number: A string containing serial number for the platform
> > >
> > >
> > > serial_number seems straightforward, adding this seems like a good
> > > idea. I don't understand yet what would go into the vendor field
> > > though. For this particular driver, is it always "Qualcomm", or
> > > would it be a third-party that makes a device based on that chip?
> > >
> >
> > As we are talking about generic soc_device_attribute fields, I was hoping that
> > having a vendor field would be helpful as along with family it would provide
> > a more thorough information. Also as more than one foundries may be used for
> > a soc, can we have a field say foundry_id to provide this information.
>
> My first feeling is that this 'vendor' information can should be
> derived from the family.
In [1] Geert just put the vendor directly into "family", while Imran
uses "Snapdragon" (which I find reasonable in the Qualcomm case). But it
seems like Geert would like a "vendor" as well, rather than a "family".
And if "family" really is supposed to contain the "SoC family name" and
we're trying to provide user space with some useful information (for
some reason), should we just rely on the unlikeliness of two vendors
using the same family name?
[1] http://www.mail-archive.com/linux-kernel@vger.kernel.org/msg1261742.html
Regards,
Bjorn
^ permalink raw reply
* Re: [PATCH] ARM: DT: stm32: move dma translation to board files
From: Alexandre Torgue @ 2016-11-02 16:14 UTC (permalink / raw)
To: Bruno Herrera
Cc: Radosław Pietrzyk, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, >, >, Maxime Coquelin,
Lee Jones, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
andrea.merello-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <CAF3+TqeiPjtG7Fs1-cpbcHGxxtSS1UOGD=S=sggpaZahFLJhEQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 11/02/2016 05:07 PM, Bruno Herrera wrote:
> Hi
>
> On Wed, Nov 2, 2016 at 12:32 PM, Alexandre Torgue
> <alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote:
>> Hi
>>
>> On 10/31/2016 07:58 PM, Radosław Pietrzyk wrote:
>>>
>>> I think wlcore driver searches dma-ranges in its parent that's why sdio
>>> node needs it.
>>
>>
>> Yes I agree. In this case it is needed as you have subnode in sdio node.
>> So IMO empty dma-ranges could be removed from ethernet and usb node, but
>> kept in future sdio subnode.
>
> Now it is clear.
Nice. Can I add your tested-by ?
>
>>
>> Bruno,
>> Do you plan to push sdio support ?
>
> Yes I do, but I'm not sure how long it will take. The I had to
> change(and hack) the mmci code because I could not get the ID from
> STM32 SDIO IP.
> My current WIP is at @
> https://github.com/mcoquelin-stm32/afboot-stm32/pull/4#issuecomment-247571615
> I know Andrea Merello is also working on that (and he probably has a
> more complete patch).
>
>>
>>
>>
>>>
>>> 2016-10-31 17:41 GMT+01:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>>>
>>> On Mon, Oct 31, 2016 at 12:14 PM, Radosław Pietrzyk
>>> <radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <mailto:radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
>>> wrote:
>>> > This is weird because dma ddresses are recalculated using parent's
>>> > dma-ranges property and soc already has it so there should be
>>> absolutely no
>>> > problem.
>>>
>>> These are my DTS and DTSI file.
>>> >
>>> > 2016-10-31 11:27 GMT+01:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>>> >>
>>> >> On Fri, Oct 28, 2016 at 5:09 AM, Radosław Pietrzyk
>>> >> <radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>>> >> > Have you defined your sdio node within soc node ?
>>> >>
>>> >> It is in the SOC node of the DSTI file.
>>> >>
>>> >> >
>>> >> > 2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>>> >> >>
>>> >> >> Hi Alex,
>>> >> >>
>>> >> >> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
>>> >> >> <alexandre.torgue-qxv4g6HH51o@public.gmane.org <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>>> wrote:
>>> >> >> > Hi Bruno,
>>> >> >> >
>>> >> >> >
>>> >> >> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
>>> >> >> >>
>>> >> >> >> Hi Alex,
>>> >> >> >>
>>> >> >> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
>>> >> >> >> <alexandre.torgue-qxv4g6HH51o@public.gmane.org <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>>> wrote:
>>> >> >> >>>
>>> >> >> >>> Hi Bruno,
>>> >> >> >>>
>>> >> >> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Hi Alexandre,
>>> >> >> >>>>
>>> >> >> >>>>>
>>> >> >> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM
>>> start address
>>> >> >> >>>>> remapping
>>> >> >> >>>>> (to @0) to boost performances. A DMA translation through
>>> >> >> >>>>> "dma-ranges"
>>> >> >> >>>>> property was needed for other masters than the M4 CPU.
>>> >> >> >>>>> stm32f429-disco doesn't use remapping so doesn't need
>>> this DMA
>>> >> >> >>>>> translation.
>>> >> >> >>>>> This patches moves this DMA translation definition from
>>> stm32f429
>>> >> >> >>>>> soc
>>> >> >> >>>>> file
>>> >> >> >>>>> to board files.
>>> >> >> >>>>>
>>> >> >> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org
>>> <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>>>
>>> >> >> >>>>>
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> index 13c7cd2..a763c15 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>>> @@ -82,6 +82,10 @@
>>> >> >> >>>>> };
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> + soc {
>>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> + };
>>> >> >> >>>>> +
>>> >> >> >>>>> usbotg_hs_phy: usbphy {
>>> >> >> >>>>> #phy-cells = <0>;
>>> >> >> >>>>> compatible = "usb-nop-xceiv";
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Shouldn't also the peripheral dma-ranges property move to
>>> board
>>> >> >> >>>> specific
>>> >> >> >>>> too?
>>> >> >> >>>> I had this patch for while but I didn't had the time to
>>> submit:
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>> Well spot I forgot it. Actually, discussing with Arnd
>>> ysterday on
>>> >> >> >>> IIRC,
>>> >> >> >>> empty dma-ranges is not needed. Can you test on your side by
>>> >> >> >>> removing
>>> >> >> >>> dma-ranges in usb node please ?
>>> >> >> >>
>>> >> >> >> Unfortunately will take a time for me to set up this
>>> environment on
>>> >> >> >> the STM32F4-EVAL board.
>>> >> >> >> And on the discovery boards we dont have this scenario.
>>> That was the
>>> >> >> >> main reason I did not submit the patch right away.
>>> >> >> >> My conclusion and I might be wrong but is based on the my
>>> tests with
>>> >> >> >> SDIO device at STM32F469I-DISCO board.
>>> >> >> >>
>>> >> >> >> I started this issue as discussion at ST Forum but Maxime
>>> gave me
>>> >> >> >> the
>>> >> >> >> hint.
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>> >> >> >>
>>>
>>> https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44
>>>
>>> <https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44>
>>> >> >> >>
>>> >> >> >>> I will push a v2 by removing empty dma-ranges if tests are
>>> ok in
>>> >> >> >>> your
>>> >> >> >>> side.
>>> >> >> >>
>>> >> >> >>
>>> >> >> >> From my understating/conclusion is: when empty
>>> property(dma-ranges)
>>> >> >> >> is
>>> >> >> >> the device node, the mapping will be taken in consideration
>>> when
>>> >> >> >> using
>>> >> >> >> DMA otherwise the mapping is ignored.
>>> >> >> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
>>> >> >> >> MEM(SDRAM)->DEV. If it is not the case for the devices in
>>> question
>>> >> >> >> so
>>> >> >> >> I suppose it can work without the property.
>>> >> >> >
>>> >> >> >
>>> >> >> > For sure translation has to be done but I'm not sure that an
>>> empty
>>> >> >> > "dma-ranges" is needed in device node to activate it. For
>>> Ethernet
>>> >> >> > empty
>>> >> >> > "dma-ranges" is not needed. I will try with usb.
>>> >> >>
>>> >> >> In the case of SDIO it is needed. As example this is my
>>> working SDIO
>>> >> >> node:
>>> >> >>
>>> >> >> sdio: sdio@40012c00 {
>>> >> >> compatible = "arm,pl18x", "arm,primecell";
>>> >> >> arm,primecell-periphid = <0x00480181>;
>>> >> >> reg = <0x40012c00 0x400>;
>>> >> >> dmas = <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
>>> >> >> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
>>> >> >> dma-names = "rx", "tx";
>>> >> >> clocks = <&rcc 0 171>;
>>> >> >> clock-names = "apb_pclk";
>>> >> >> interrupts = <49>;
>>> >> >> status = "disabled";
>>> >> >> };
>>> >> >>
>>> >> >> &sdio {
>>> >> >> status = "okay";
>>> >> >> vmmc-supply = <&wlan_en>;
>>> >> >> bus-width = <4>;
>>> >> >> max-frequency = <24000000>;
>>> >> >> pinctrl-names = "default";
>>> >> >> pinctrl-0 = <&sdio_pins>;
>>> >> >> ti,non-removable;
>>> >> >> ti,needs-special-hs-handling;
>>> >> >> dma-ranges;
>>> >> >> cap-power-off-card;
>>> >> >> keep-power-in-suspend;
>>> >> >>
>>> >> >> #address-cells = <1>;
>>> >> >> #size-cells = <0>;
>>> >> >> wlcore: wlcore@0 {
>>> >> >> compatible = "ti,wl1835";
>>> >> >> reg = <2>;
>>> >> >> interrupt-parent = <&gpioa>;
>>> >> >> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
>>> >> >> };
>>> >> >> };
>>> >> >>
>>> >> >> >
>>> >> >> > alex
>>> >> >> >
>>> >> >> >
>>> >> >> >>
>>> >> >> >>>
>>> >> >> >>> Thanks in advance
>>> >> >> >>> Alex
>>> >> >> >>>
>>> >> >> >>>
>>> >> >> >>>>
>>> >> >> >>>> Author: Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
>>>
>>> >> >> >>>> Date: Sun Oct 16 14:50:00 2016 -0200
>>> >> >> >>>>
>>> >> >> >>>> ARM: DT: STM32: Use dma-ranges property per board not
>>> at dtsi
>>> >> >> >>>> file
>>> >> >> >>>>
>>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> index 6bfc595..2a22a82 100644
>>> >> >> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>>> >> >> >>>> @@ -52,6 +52,10 @@
>>> >> >> >>>> model = "STMicroelectronics STM32429i-EVAL board";
>>> >> >> >>>> compatible = "st,stm32429i-eval", "st,stm32f429";
>>> >> >> >>>>
>>> >> >> >>>> + soc {
>>> >> >> >>>> + dma-ranges = <0xC0000000 0x0 0x10000000>;
>>> >> >> >>>> + };
>>> >> >> >>>> +
>>> >> >> >>>> chosen {
>>> >> >> >>>> bootargs = "root=/dev/ram rdinit=/linuxrc";
>>> >> >> >>>> stdout-path = "serial0:115200n8";
>>> >> >> >>>> @@ -96,6 +100,7 @@
>>> >> >> >>>>
>>> >> >> >>>> ðernet0 {
>>> >> >> >>>> status = "okay";
>>> >> >> >>>> + dma-ranges;
>>> >> >> >>>> pinctrl-0 = <ðernet0_mii>;
>>> >> >> >>>> pinctrl-names = "default";
>>> >> >> >>>> phy-mode = "mii-id";
>>> >> >> >>>> @@ -116,6 +121,7 @@
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> &usbotg_hs {
>>> >> >> >>>> + dma-ranges;
>>> >> >> >>>> dr_mode = "host";
>>> >> >> >>>> phys = <&usbotg_hs_phy>;
>>> >> >> >>>> phy-names = "usb2-phy";
>>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> index 7d624a2..697a133 100644
>>> >> >> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>> @@ -59,7 +59,6 @@
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> soc {
>>> >> >> >>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>
>>> >> >> >>>> timer2: timer@40000000 {
>>> >> >> >>>> compatible = "st,stm32-timer";
>>> >> >> >>>> @@ -472,13 +471,11 @@
>>> >> >> >>>> st,syscon = <&syscfg 0x4>;
>>> >> >> >>>> snps,pbl = <8>;
>>> >> >> >>>> snps,mixed-burst;
>>> >> >> >>>> - dma-ranges;
>>> >> >> >>>> status = "disabled";
>>> >> >> >>>> };
>>> >> >> >>>>
>>> >> >> >>>> usbotg_hs: usb@40040000 {
>>> >> >> >>>> compatible = "snps,dwc2";
>>> >> >> >>>> - dma-ranges;
>>> >> >> >>>> reg = <0x40040000 0x40000>;
>>> >> >> >>>> interrupts = <77>;
>>> >> >> >>>> clocks = <&rcc 0 29>;
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> index 0596d60..3a1cfdd 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>>> >> >> >>>>> @@ -59,8 +59,6 @@
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> soc {
>>> >> >> >>>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> -
>>> >> >> >>>>> timer2: timer@40000000 {
>>> >> >> >>>>> compatible = "st,stm32-timer";
>>> >> >> >>>>> reg = <0x40000000 0x400>;
>>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> index 9e73656..c2213c0 100644
>>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>>> >> >> >>>>> @@ -64,6 +64,10 @@
>>> >> >> >>>>> aliases {
>>> >> >> >>>>> serial0 = &usart3;
>>> >> >> >>>>> };
>>> >> >> >>>>> +
>>> >> >> >>>>> + soc {
>>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>>> >> >> >>>>> + };
>>> >> >> >>>>> };
>>> >> >> >>>>>
>>> >> >> >>>>> &clk_hse {
>>> >> >> >>>>> --
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>>
>>> >> >> >>>> Br.,
>>> >> >> >>>> Bruno
>>> >> >> >>>>
>>> >> >> >>>
>>> >> >> >
>>> >> >>
>>> >> >> _______________________________________________
>>> >> >> linux-arm-kernel mailing list
>>> >> >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>>> <mailto:linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
>>> >> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>>> <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>
>>> >> >
>>> >> >
>>> >
>>> >
>>>
>>>
>>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] ARM: DT: stm32: move dma translation to board files
From: Bruno Herrera @ 2016-11-02 16:07 UTC (permalink / raw)
To: Alexandre Torgue
Cc: Radosław Pietrzyk, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA, Arnd Bergmann,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, >, >, Maxime Coquelin,
Lee Jones, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
andrea.merello-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <3e854414-f51d-3e59-6cee-142106cef40f-qxv4g6HH51o@public.gmane.org>
Hi
On Wed, Nov 2, 2016 at 12:32 PM, Alexandre Torgue
<alexandre.torgue-qxv4g6HH51o@public.gmane.org> wrote:
> Hi
>
> On 10/31/2016 07:58 PM, Radosław Pietrzyk wrote:
>>
>> I think wlcore driver searches dma-ranges in its parent that's why sdio
>> node needs it.
>
>
> Yes I agree. In this case it is needed as you have subnode in sdio node.
> So IMO empty dma-ranges could be removed from ethernet and usb node, but
> kept in future sdio subnode.
Now it is clear.
>
> Bruno,
> Do you plan to push sdio support ?
Yes I do, but I'm not sure how long it will take. The I had to
change(and hack) the mmci code because I could not get the ID from
STM32 SDIO IP.
My current WIP is at @
https://github.com/mcoquelin-stm32/afboot-stm32/pull/4#issuecomment-247571615
I know Andrea Merello is also working on that (and he probably has a
more complete patch).
>
>
>
>>
>> 2016-10-31 17:41 GMT+01:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>>
>> On Mon, Oct 31, 2016 at 12:14 PM, Radosław Pietrzyk
>> <radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org <mailto:radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
>> wrote:
>> > This is weird because dma ddresses are recalculated using parent's
>> > dma-ranges property and soc already has it so there should be
>> absolutely no
>> > problem.
>>
>> These are my DTS and DTSI file.
>> >
>> > 2016-10-31 11:27 GMT+01:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>> >>
>> >> On Fri, Oct 28, 2016 at 5:09 AM, Radosław Pietrzyk
>> >> <radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> <mailto:radoslaw.pietrzyk-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>> wrote:
>> >> > Have you defined your sdio node within soc node ?
>> >>
>> >> It is in the SOC node of the DSTI file.
>> >>
>> >> >
>> >> > 2016-10-27 14:57 GMT+02:00 Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>:
>> >> >>
>> >> >> Hi Alex,
>> >> >>
>> >> >> On Thu, Oct 27, 2016 at 10:21 AM, Alexandre Torgue
>> >> >> <alexandre.torgue-qxv4g6HH51o@public.gmane.org <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>> wrote:
>> >> >> > Hi Bruno,
>> >> >> >
>> >> >> >
>> >> >> > On 10/27/2016 12:43 PM, Bruno Herrera wrote:
>> >> >> >>
>> >> >> >> Hi Alex,
>> >> >> >>
>> >> >> >> On Wed, Oct 26, 2016 at 7:09 AM, Alexandre Torgue
>> >> >> >> <alexandre.torgue-qxv4g6HH51o@public.gmane.org <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>> wrote:
>> >> >> >>>
>> >> >> >>> Hi Bruno,
>> >> >> >>>
>> >> >> >>> On 10/25/2016 11:06 PM, Bruno Herrera wrote:
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Hi Alexandre,
>> >> >> >>>>
>> >> >> >>>>>
>> >> >> >>>>> stm32f469-disco and stm32f429-eval boards use SDRAM
>> start address
>> >> >> >>>>> remapping
>> >> >> >>>>> (to @0) to boost performances. A DMA translation through
>> >> >> >>>>> "dma-ranges"
>> >> >> >>>>> property was needed for other masters than the M4 CPU.
>> >> >> >>>>> stm32f429-disco doesn't use remapping so doesn't need
>> this DMA
>> >> >> >>>>> translation.
>> >> >> >>>>> This patches moves this DMA translation definition from
>> stm32f429
>> >> >> >>>>> soc
>> >> >> >>>>> file
>> >> >> >>>>> to board files.
>> >> >> >>>>>
>> >> >> >>>>> Signed-off-by: Alexandre TORGUE <alexandre.torgue-qxv4g6HH51o@public.gmane.org
>> <mailto:alexandre.torgue-qxv4g6HH51o@public.gmane.org>>
>>
>> >> >> >>>>>
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> index 13c7cd2..a763c15 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>>> @@ -82,6 +82,10 @@
>> >> >> >>>>> };
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> + soc {
>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> + };
>> >> >> >>>>> +
>> >> >> >>>>> usbotg_hs_phy: usbphy {
>> >> >> >>>>> #phy-cells = <0>;
>> >> >> >>>>> compatible = "usb-nop-xceiv";
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Shouldn't also the peripheral dma-ranges property move to
>> board
>> >> >> >>>> specific
>> >> >> >>>> too?
>> >> >> >>>> I had this patch for while but I didn't had the time to
>> submit:
>> >> >> >>>
>> >> >> >>>
>> >> >> >>>
>> >> >> >>> Well spot I forgot it. Actually, discussing with Arnd
>> ysterday on
>> >> >> >>> IIRC,
>> >> >> >>> empty dma-ranges is not needed. Can you test on your side by
>> >> >> >>> removing
>> >> >> >>> dma-ranges in usb node please ?
>> >> >> >>
>> >> >> >> Unfortunately will take a time for me to set up this
>> environment on
>> >> >> >> the STM32F4-EVAL board.
>> >> >> >> And on the discovery boards we dont have this scenario.
>> That was the
>> >> >> >> main reason I did not submit the patch right away.
>> >> >> >> My conclusion and I might be wrong but is based on the my
>> tests with
>> >> >> >> SDIO device at STM32F469I-DISCO board.
>> >> >> >>
>> >> >> >> I started this issue as discussion at ST Forum but Maxime
>> gave me
>> >> >> >> the
>> >> >> >> hint.
>> >> >> >>
>> >> >> >>
>> >> >> >>
>> >> >> >>
>> >> >> >>
>>
>> https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44
>>
>> <https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=https%3a%2f%2fmy%2est%2ecom%2fpublic%2fSTe2ecommunities%2fmcu%2fLists%2fcortex_mx_stm32%2fDMA2%20and%20SYSCFG_MEMRMP%20relationship&FolderCTID=0x01200200770978C69A1141439FE559EB459D7580009C4E14902C3CDE46A77F0FFD06506F5B¤tviews=44>
>> >> >> >>
>> >> >> >>> I will push a v2 by removing empty dma-ranges if tests are
>> ok in
>> >> >> >>> your
>> >> >> >>> side.
>> >> >> >>
>> >> >> >>
>> >> >> >> From my understating/conclusion is: when empty
>> property(dma-ranges)
>> >> >> >> is
>> >> >> >> the device node, the mapping will be taken in consideration
>> when
>> >> >> >> using
>> >> >> >> DMA otherwise the mapping is ignored.
>> >> >> >> And in the SDIO case it is needed for DEV->MEM(SDRAM) and
>> >> >> >> MEM(SDRAM)->DEV. If it is not the case for the devices in
>> question
>> >> >> >> so
>> >> >> >> I suppose it can work without the property.
>> >> >> >
>> >> >> >
>> >> >> > For sure translation has to be done but I'm not sure that an
>> empty
>> >> >> > "dma-ranges" is needed in device node to activate it. For
>> Ethernet
>> >> >> > empty
>> >> >> > "dma-ranges" is not needed. I will try with usb.
>> >> >>
>> >> >> In the case of SDIO it is needed. As example this is my
>> working SDIO
>> >> >> node:
>> >> >>
>> >> >> sdio: sdio@40012c00 {
>> >> >> compatible = "arm,pl18x", "arm,primecell";
>> >> >> arm,primecell-periphid = <0x00480181>;
>> >> >> reg = <0x40012c00 0x400>;
>> >> >> dmas = <&dma2 6 4 0x10400 0x3>, /* Logical - DevToMem */
>> >> >> <&dma2 3 4 0x10400 0x3>; /* Logical - MemToDev */
>> >> >> dma-names = "rx", "tx";
>> >> >> clocks = <&rcc 0 171>;
>> >> >> clock-names = "apb_pclk";
>> >> >> interrupts = <49>;
>> >> >> status = "disabled";
>> >> >> };
>> >> >>
>> >> >> &sdio {
>> >> >> status = "okay";
>> >> >> vmmc-supply = <&wlan_en>;
>> >> >> bus-width = <4>;
>> >> >> max-frequency = <24000000>;
>> >> >> pinctrl-names = "default";
>> >> >> pinctrl-0 = <&sdio_pins>;
>> >> >> ti,non-removable;
>> >> >> ti,needs-special-hs-handling;
>> >> >> dma-ranges;
>> >> >> cap-power-off-card;
>> >> >> keep-power-in-suspend;
>> >> >>
>> >> >> #address-cells = <1>;
>> >> >> #size-cells = <0>;
>> >> >> wlcore: wlcore@0 {
>> >> >> compatible = "ti,wl1835";
>> >> >> reg = <2>;
>> >> >> interrupt-parent = <&gpioa>;
>> >> >> interrupts = <8 IRQ_TYPE_EDGE_RISING>;
>> >> >> };
>> >> >> };
>> >> >>
>> >> >> >
>> >> >> > alex
>> >> >> >
>> >> >> >
>> >> >> >>
>> >> >> >>>
>> >> >> >>> Thanks in advance
>> >> >> >>> Alex
>> >> >> >>>
>> >> >> >>>
>> >> >> >>>>
>> >> >> >>>> Author: Bruno Herrera <bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org
>> <mailto:bruherrera-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>>
>>
>> >> >> >>>> Date: Sun Oct 16 14:50:00 2016 -0200
>> >> >> >>>>
>> >> >> >>>> ARM: DT: STM32: Use dma-ranges property per board not
>> at dtsi
>> >> >> >>>> file
>> >> >> >>>>
>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> index 6bfc595..2a22a82 100644
>> >> >> >>>> --- a/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
>> >> >> >>>> @@ -52,6 +52,10 @@
>> >> >> >>>> model = "STMicroelectronics STM32429i-EVAL board";
>> >> >> >>>> compatible = "st,stm32429i-eval", "st,stm32f429";
>> >> >> >>>>
>> >> >> >>>> + soc {
>> >> >> >>>> + dma-ranges = <0xC0000000 0x0 0x10000000>;
>> >> >> >>>> + };
>> >> >> >>>> +
>> >> >> >>>> chosen {
>> >> >> >>>> bootargs = "root=/dev/ram rdinit=/linuxrc";
>> >> >> >>>> stdout-path = "serial0:115200n8";
>> >> >> >>>> @@ -96,6 +100,7 @@
>> >> >> >>>>
>> >> >> >>>> ðernet0 {
>> >> >> >>>> status = "okay";
>> >> >> >>>> + dma-ranges;
>> >> >> >>>> pinctrl-0 = <ðernet0_mii>;
>> >> >> >>>> pinctrl-names = "default";
>> >> >> >>>> phy-mode = "mii-id";
>> >> >> >>>> @@ -116,6 +121,7 @@
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> &usbotg_hs {
>> >> >> >>>> + dma-ranges;
>> >> >> >>>> dr_mode = "host";
>> >> >> >>>> phys = <&usbotg_hs_phy>;
>> >> >> >>>> phy-names = "usb2-phy";
>> >> >> >>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> index 7d624a2..697a133 100644
>> >> >> >>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>> @@ -59,7 +59,6 @@
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> soc {
>> >> >> >>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>
>> >> >> >>>> timer2: timer@40000000 {
>> >> >> >>>> compatible = "st,stm32-timer";
>> >> >> >>>> @@ -472,13 +471,11 @@
>> >> >> >>>> st,syscon = <&syscfg 0x4>;
>> >> >> >>>> snps,pbl = <8>;
>> >> >> >>>> snps,mixed-burst;
>> >> >> >>>> - dma-ranges;
>> >> >> >>>> status = "disabled";
>> >> >> >>>> };
>> >> >> >>>>
>> >> >> >>>> usbotg_hs: usb@40040000 {
>> >> >> >>>> compatible = "snps,dwc2";
>> >> >> >>>> - dma-ranges;
>> >> >> >>>> reg = <0x40040000 0x40000>;
>> >> >> >>>> interrupts = <77>;
>> >> >> >>>> clocks = <&rcc 0 29>;
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> index 0596d60..3a1cfdd 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f429.dtsi
>> >> >> >>>>> @@ -59,8 +59,6 @@
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> soc {
>> >> >> >>>>> - dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> -
>> >> >> >>>>> timer2: timer@40000000 {
>> >> >> >>>>> compatible = "st,stm32-timer";
>> >> >> >>>>> reg = <0x40000000 0x400>;
>> >> >> >>>>> diff --git a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> index 9e73656..c2213c0 100644
>> >> >> >>>>> --- a/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> +++ b/arch/arm/boot/dts/stm32f469-disco.dts
>> >> >> >>>>> @@ -64,6 +64,10 @@
>> >> >> >>>>> aliases {
>> >> >> >>>>> serial0 = &usart3;
>> >> >> >>>>> };
>> >> >> >>>>> +
>> >> >> >>>>> + soc {
>> >> >> >>>>> + dma-ranges = <0xc0000000 0x0 0x10000000>;
>> >> >> >>>>> + };
>> >> >> >>>>> };
>> >> >> >>>>>
>> >> >> >>>>> &clk_hse {
>> >> >> >>>>> --
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>>
>> >> >> >>>> Br.,
>> >> >> >>>> Bruno
>> >> >> >>>>
>> >> >> >>>
>> >> >> >
>> >> >>
>> >> >> _______________________________________________
>> >> >> linux-arm-kernel mailing list
>> >> >> linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
>> <mailto:linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>
>> >> >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>> <http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>
>> >> >
>> >> >
>> >
>> >
>>
>>
>
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^ permalink raw reply
* Re: [PATCH v3 2/3] Documentation: dt: add bindings for ti-cpufreq
From: Dave Gerlach @ 2016-11-02 16:03 UTC (permalink / raw)
To: Viresh Kumar
Cc: Rob Herring, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rafael J . Wysocki,
Tony Lindgren, Nishanth Menon
In-Reply-To: <20161102035941.GA10786@vireshk-i7>
Hi,
On 11/01/2016 10:59 PM, Viresh Kumar wrote:
> On 27-10-16, 16:41, Dave Gerlach wrote:
>> Add the device tree bindings document for the TI CPUFreq/OPP driver
>> on AM33xx and AM43xx SoCs. The operating-points-v2 binding allows us
>> to provide an opp-supported-hw property for each OPP to define when
>> it is available. This driver is responsible for reading and parsing
>> registers to determine which OPPs can be selectively enabled based
>> on the specific SoC in use by matching against the opp-supported-hw
>> data.
>>
>> Signed-off-by: Dave Gerlach <d-gerlach-l0cyMroinI0@public.gmane.org>
>> ---
>> v2->v3:
>> - Move ti,syscon-* properties under opp table instead of cpu node, as
>> that is a better location for them.
>> - For the opp table do not use platform specific compatible strings
>> but instead a operating-points-v2-ti-cpu
>>
>> .../devicetree/bindings/cpufreq/ti-cpufreq.txt | 132 +++++++++++++++++++++
>> 1 file changed, 132 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>>
>> diff --git a/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>> new file mode 100644
>> index 000000000000..467ad29c75c9
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/cpufreq/ti-cpufreq.txt
>> @@ -0,0 +1,132 @@
>> +TI CPUFreq and OPP bindings
>> +================================
>> +
>> +Certain TI SoCs, like those in the am335x, am437x, am57xx, and dra7xx
>> +families support different OPPs depending on the silicon variant in use.
>> +The ti_cpufreq driver can use revision and an efuse value from the SoC to
>> +provide the OPP framework with supported hardware information. This is
>> +used to determine which OPPs from the operating-points-v2 table get enabled
>> +when it is parsed by the OPP framework.
>> +
>> +Required properties:
>> +--------------------
>> +In 'cpus' nodes:
>> +- operating-points-v2: Phandle to the operating-points-v2 table to use.
>> +
>> +In 'operating-points-v2' table:
>> +- compatible: Should be 'operating-points-v2-ti-cpu' for am335x, am43xx,
>> + and dra7xx/am57xx SoCs
>> +- ti,syscon-efuse: Syscon phandle, offset to efuse register, efuse register
>> + mask, and efuse register shift to get the relevant bits
>> + that describe OPP availability.
>> +- ti,syscon-rev: Syscon and offset used to look up revision value on SoC.
>> +
>> +Optional properties:
>> +--------------------
>> +For each opp entry in 'operating-points-v2' table:
>> +- opp-supported-hw: Two bitfields indicating:
>> + 1. Which revision of the SoC the OPP is supported by
>> + 2. Which eFuse bits indicate this OPP is available
>> +
>> + A bitwise AND is performed against these values and if any bit
>> + matches, the OPP gets enabled. Not providing the property for an
>> + entry indicates that an OPP is always supported.
>> +
>> +Example:
>> +--------
>> +
>> +/* From arch/arm/boot/dts/am33xx.dtsi */
>> +cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + cpu@0 {
>> + compatible = "arm,cortex-a8";
>> + device_type = "cpu";
>> + reg = <0>;
>> +
>> + operating-points-v2 = <&cpu0_opp_table>;
>> +
>> + clocks = <&dpll_mpu_ck>;
>> + clock-names = "cpu";
>> +
>> + clock-latency = <300000>; /* From omap-cpufreq driver */
>> + };
>> +};
>> +
>> +/*
>> + * cpu0 has different OPPs depending on SoC revision and some on revisions
>> + * 0x2 and 0x4 have eFuse bits that indicate if they are available or not
>> + */
>> +cpu0_opp_table: opp_table0 {
>> + compatible = "operating-points-v2-ti-am3352-cpu";
>> + ti,syscon-efuse = <&scm_conf 0x7fc 0x1fff 0>;
>> + ti,syscon-rev = <&scm_conf 0x600>;
>> +
>> + /*
>> + * The three following nodes are marked with opp-suspend
>> + * because they can not be enabled simultaneously on a
>> + * single SoC.
>> + */
>> + opp50@300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + opp-microvolt = <950000 931000 969000>;
>> + opp-supported-hw = <0x06 0x0010>;
>> + opp-suspend;
>> + };
>> +
>> + opp100@275000000 {
>> + opp-hz = /bits/ 64 <275000000>;
>> + opp-microvolt = <1100000 1078000 1122000>;
>> + opp-supported-hw = <0x01 0x00FF>;
>> + opp-suspend;
>> + };
>> +
>> + opp100@300000000 {
>> + opp-hz = /bits/ 64 <300000000>;
>> + opp-microvolt = <1100000 1078000 1122000>;
>> + opp-supported-hw = <0x06 0x0020>;
>> + opp-suspend;
>
> Only one OPP in the table can be marked as suspend OPP.
>
Does that still apply when opp-supported-hw is involved? Based on the
comment at the start of the table, those OPPs are all mutually exclusive
and will not ever be enabled on the same piece of silicon, they
represent the lowest OPP for each of three different supported-hw
configurations.
Regards,
Dave
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^ permalink raw reply
* [PATCH v9 3/3] clk: qcom: Always add factor clock for xo clocks
From: Georgi Djakov @ 2016-11-02 15:56 UTC (permalink / raw)
To: sboyd-sgV2jX0FEOL9JmXXK+q4OQ, mturquette-rdvid1DuHRBWk0Htik3J/w
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <20161102155658.32203-1-georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Currently the RPM/RPM-SMD clock drivers do not register the xo clocks,
so we should always add factor clock. When we later add xo clocks support
into the drivers, we should update this function to skip registration.
By doing so we avoid any DT dependencies.
Signed-off-by: Georgi Djakov <georgi.djakov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
drivers/clk/qcom/common.c | 15 ++++++---------
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/clk/qcom/common.c b/drivers/clk/qcom/common.c
index fffcbaf0fba7..27566a0098ca 100644
--- a/drivers/clk/qcom/common.c
+++ b/drivers/clk/qcom/common.c
@@ -153,15 +153,12 @@ int qcom_cc_register_board_clk(struct device *dev, const char *path,
const char *name, unsigned long rate)
{
bool add_factor = true;
- struct device_node *node;
-
- /* The RPM clock driver will add the factor clock if present */
- if (IS_ENABLED(CONFIG_QCOM_RPMCC)) {
- node = of_find_compatible_node(NULL, NULL, "qcom,rpmcc");
- if (of_device_is_available(node))
- add_factor = false;
- of_node_put(node);
- }
+
+ /*
+ * TODO: The RPM clock driver currently does not support the xo clock.
+ * When xo is added to the RPM clock driver, we should change this
+ * function to skip registration of xo factor clocks.
+ */
return _qcom_cc_register_board_clk(dev, path, name, rate, add_factor);
}
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^ permalink raw reply related
* [PATCH v9 2/3] clk: qcom: Add support for RPM Clocks
From: Georgi Djakov @ 2016-11-02 15:56 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-clk, devicetree, robh+dt, mark.rutland, linux-kernel,
linux-arm-msm, georgi.djakov
In-Reply-To: <20161102155658.32203-1-georgi.djakov@linaro.org>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_rpm driver to communicate with RPM.
Such platforms are apq8064 and msm8960.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/Kconfig | 13 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-rpm.c | 489 +++++++++++++++++++++
include/dt-bindings/clock/qcom,rpmcc.h | 24 +
5 files changed, 528 insertions(+)
create mode 100644 drivers/clk/qcom/clk-rpm.c
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index e3e13226d798..87d3714b956a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
compatible "qcom,rpmcc" should be also included.
"qcom,rpmcc-msm8916", "qcom,rpmcc"
+ "qcom,rpmcc-apq8064", "qcom,rpmcc"
- #clock-cells : shall contain 1
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index b537c59dcfe6..b82d2f33c9e4 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -12,6 +12,19 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
+config QCOM_CLK_RPM
+ tristate "RPM based Clock Controller"
+ depends on COMMON_CLK_QCOM && MFD_QCOM_RPM
+ select QCOM_RPMCC
+ help
+ The RPM (Resource Power Manager) is a dedicated hardware engine for
+ managing the shared SoC resources in order to keep the lowest power
+ profile. It communicates with other hardware subsystems via shared
+ memory and accepts clock requests, aggregates the requests and turns
+ the clocks on/off or scales them on demand.
+ Say Y if you want to support the clocks exposed by the RPM on
+ platforms such as apq8064, msm8660, msm8960 etc.
+
config QCOM_CLK_SMD_RPM
tristate "RPM over SMD based Clock Controller"
depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 0dd72e56b7e4..eb2dfb32d960 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -29,4 +29,5 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
+obj-$(CONFIG_QCOM_CLK_RPM) += clk-rpm.o
obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
diff --git a/drivers/clk/qcom/clk-rpm.c b/drivers/clk/qcom/clk-rpm.c
new file mode 100644
index 000000000000..f9fe452f49d6
--- /dev/null
+++ b/drivers/clk/qcom/clk-rpm.c
@@ -0,0 +1,489 @@
+/*
+ * Copyright (c) 2016, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/mfd/qcom_rpm.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/mfd/qcom-rpm.h>
+#include <dt-bindings/clock/qcom,rpmcc.h>
+
+#define QCOM_RPM_MISC_CLK_TYPE 0x306b6c63
+#define QCOM_RPM_SCALING_ENABLE_ID 0x2
+
+#define DEFINE_CLK_RPM(_platform, _name, _active, r_id) \
+ static struct clk_rpm _platform##_##_active; \
+ static struct clk_rpm _platform##_##_name = { \
+ .rpm_clk_id = (r_id), \
+ .peer = &_platform##_##_active, \
+ .rate = INT_MAX, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "pxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_rpm _platform##_##_active = { \
+ .rpm_clk_id = (r_id), \
+ .peer = &_platform##_##_name, \
+ .active_only = true, \
+ .rate = INT_MAX, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_ops, \
+ .name = #_active, \
+ .parent_names = (const char *[]){ "pxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define DEFINE_CLK_RPM_PXO_BRANCH(_platform, _name, _active, r_id, r) \
+ static struct clk_rpm _platform##_##_active; \
+ static struct clk_rpm _platform##_##_name = { \
+ .rpm_clk_id = (r_id), \
+ .active_only = true, \
+ .peer = &_platform##_##_active, \
+ .rate = (r), \
+ .branch = true, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_branch_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "pxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_rpm _platform##_##_active = { \
+ .rpm_clk_id = (r_id), \
+ .peer = &_platform##_##_name, \
+ .rate = (r), \
+ .branch = true, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_branch_ops, \
+ .name = #_active, \
+ .parent_names = (const char *[]){ "pxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define DEFINE_CLK_RPM_CXO_BRANCH(_platform, _name, _active, r_id, r) \
+ static struct clk_rpm _platform##_##_active; \
+ static struct clk_rpm _platform##_##_name = { \
+ .rpm_clk_id = (r_id), \
+ .peer = &_platform##_##_active, \
+ .rate = (r), \
+ .branch = true, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_branch_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "cxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_rpm _platform##_##_active = { \
+ .rpm_clk_id = (r_id), \
+ .active_only = true, \
+ .peer = &_platform##_##_name, \
+ .rate = (r), \
+ .branch = true, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_rpm_branch_ops, \
+ .name = #_active, \
+ .parent_names = (const char *[]){ "cxo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define to_clk_rpm(_hw) container_of(_hw, struct clk_rpm, hw)
+
+struct clk_rpm {
+ const int rpm_clk_id;
+ const bool active_only;
+ unsigned long rate;
+ bool enabled;
+ bool branch;
+ struct clk_rpm *peer;
+ struct clk_hw hw;
+ struct qcom_rpm *rpm;
+};
+
+struct rpm_cc {
+ struct qcom_rpm *rpm;
+ struct clk_hw_onecell_data data;
+ struct clk_hw *hws[];
+};
+
+struct rpm_clk_desc {
+ struct clk_rpm **clks;
+ size_t num_clks;
+};
+
+static DEFINE_MUTEX(rpm_clk_lock);
+
+static int clk_rpm_handoff(struct clk_rpm *r)
+{
+ int ret;
+ u32 value = INT_MAX;
+
+ ret = qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
+ r->rpm_clk_id, &value, 1);
+ if (ret)
+ return ret;
+ ret = qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
+ r->rpm_clk_id, &value, 1);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int clk_rpm_set_rate_active(struct clk_rpm *r, unsigned long rate)
+{
+ u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
+
+ return qcom_rpm_write(r->rpm, QCOM_RPM_ACTIVE_STATE,
+ r->rpm_clk_id, &value, 1);
+}
+
+static int clk_rpm_set_rate_sleep(struct clk_rpm *r, unsigned long rate)
+{
+ u32 value = DIV_ROUND_UP(rate, 1000); /* to kHz */
+
+ return qcom_rpm_write(r->rpm, QCOM_RPM_SLEEP_STATE,
+ r->rpm_clk_id, &value, 1);
+}
+
+static void to_active_sleep(struct clk_rpm *r, unsigned long rate,
+ unsigned long *active, unsigned long *sleep)
+{
+ *active = rate;
+
+ /*
+ * Active-only clocks don't care what the rate is during sleep. So,
+ * they vote for zero.
+ */
+ if (r->active_only)
+ *sleep = 0;
+ else
+ *sleep = *active;
+}
+
+static int clk_rpm_prepare(struct clk_hw *hw)
+{
+ struct clk_rpm *r = to_clk_rpm(hw);
+ struct clk_rpm *peer = r->peer;
+ unsigned long this_rate = 0, this_sleep_rate = 0;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ unsigned long active_rate, sleep_rate;
+ int ret = 0;
+
+ mutex_lock(&rpm_clk_lock);
+
+ /* Don't send requests to the RPM if the rate has not been set. */
+ if (!r->rate)
+ goto out;
+
+ to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate,
+ &peer_rate, &peer_sleep_rate);
+
+ active_rate = max(this_rate, peer_rate);
+
+ if (r->branch)
+ active_rate = !!active_rate;
+
+ ret = clk_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+ if (r->branch)
+ sleep_rate = !!sleep_rate;
+
+ ret = clk_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ /* Undo the active set vote and restore it */
+ ret = clk_rpm_set_rate_active(r, peer_rate);
+
+out:
+ if (!ret)
+ r->enabled = true;
+
+ mutex_unlock(&rpm_clk_lock);
+
+ return ret;
+}
+
+static void clk_rpm_unprepare(struct clk_hw *hw)
+{
+ struct clk_rpm *r = to_clk_rpm(hw);
+ struct clk_rpm *peer = r->peer;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ unsigned long active_rate, sleep_rate;
+ int ret;
+
+ mutex_lock(&rpm_clk_lock);
+
+ if (!r->rate)
+ goto out;
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate, &peer_rate,
+ &peer_sleep_rate);
+
+ active_rate = r->branch ? !!peer_rate : peer_rate;
+ ret = clk_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
+ ret = clk_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ goto out;
+
+ r->enabled = false;
+
+out:
+ mutex_unlock(&rpm_clk_lock);
+}
+
+static int clk_rpm_set_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long parent_rate)
+{
+ struct clk_rpm *r = to_clk_rpm(hw);
+ struct clk_rpm *peer = r->peer;
+ unsigned long active_rate, sleep_rate;
+ unsigned long this_rate = 0, this_sleep_rate = 0;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ int ret = 0;
+
+ mutex_lock(&rpm_clk_lock);
+
+ if (!r->enabled)
+ goto out;
+
+ to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate,
+ &peer_rate, &peer_sleep_rate);
+
+ active_rate = max(this_rate, peer_rate);
+ ret = clk_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+ ret = clk_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ goto out;
+
+ r->rate = rate;
+
+out:
+ mutex_unlock(&rpm_clk_lock);
+
+ return ret;
+}
+
+static long clk_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ /*
+ * RPM handles rate rounding and we don't have a way to
+ * know what the rate will be, so just return whatever
+ * rate is requested.
+ */
+ return rate;
+}
+
+static unsigned long clk_rpm_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_rpm *r = to_clk_rpm(hw);
+
+ /*
+ * RPM handles rate rounding and we don't have a way to
+ * know what the rate will be, so just return whatever
+ * rate was set.
+ */
+ return r->rate;
+}
+
+static const struct clk_ops clk_rpm_ops = {
+ .prepare = clk_rpm_prepare,
+ .unprepare = clk_rpm_unprepare,
+ .set_rate = clk_rpm_set_rate,
+ .round_rate = clk_rpm_round_rate,
+ .recalc_rate = clk_rpm_recalc_rate,
+};
+
+static const struct clk_ops clk_rpm_branch_ops = {
+ .prepare = clk_rpm_prepare,
+ .unprepare = clk_rpm_unprepare,
+ .round_rate = clk_rpm_round_rate,
+ .recalc_rate = clk_rpm_recalc_rate,
+};
+
+/* apq8064 */
+DEFINE_CLK_RPM(apq8064, afab_clk, afab_a_clk, QCOM_RPM_APPS_FABRIC_CLK);
+DEFINE_CLK_RPM(apq8064, cfpb_clk, cfpb_a_clk, QCOM_RPM_CFPB_CLK);
+DEFINE_CLK_RPM(apq8064, daytona_clk, daytona_a_clk, QCOM_RPM_DAYTONA_FABRIC_CLK);
+DEFINE_CLK_RPM(apq8064, ebi1_clk, ebi1_a_clk, QCOM_RPM_EBI1_CLK);
+DEFINE_CLK_RPM(apq8064, mmfab_clk, mmfab_a_clk, QCOM_RPM_MM_FABRIC_CLK);
+DEFINE_CLK_RPM(apq8064, mmfpb_clk, mmfpb_a_clk, QCOM_RPM_MMFPB_CLK);
+DEFINE_CLK_RPM(apq8064, sfab_clk, sfab_a_clk, QCOM_RPM_SYS_FABRIC_CLK);
+DEFINE_CLK_RPM(apq8064, sfpb_clk, sfpb_a_clk, QCOM_RPM_SFPB_CLK);
+DEFINE_CLK_RPM(apq8064, qdss_clk, qdss_a_clk, QCOM_RPM_QDSS_CLK);
+
+static struct clk_rpm *apq8064_clks[] = {
+ [RPM_APPS_FABRIC_CLK] = &apq8064_afab_clk,
+ [RPM_APPS_FABRIC_A_CLK] = &apq8064_afab_a_clk,
+ [RPM_CFPB_CLK] = &apq8064_cfpb_clk,
+ [RPM_CFPB_A_CLK] = &apq8064_cfpb_a_clk,
+ [RPM_DAYTONA_FABRIC_CLK] = &apq8064_daytona_clk,
+ [RPM_DAYTONA_FABRIC_A_CLK] = &apq8064_daytona_a_clk,
+ [RPM_EBI1_CLK] = &apq8064_ebi1_clk,
+ [RPM_EBI1_A_CLK] = &apq8064_ebi1_a_clk,
+ [RPM_MM_FABRIC_CLK] = &apq8064_mmfab_clk,
+ [RPM_MM_FABRIC_A_CLK] = &apq8064_mmfab_a_clk,
+ [RPM_MMFPB_CLK] = &apq8064_mmfpb_clk,
+ [RPM_MMFPB_A_CLK] = &apq8064_mmfpb_a_clk,
+ [RPM_SYS_FABRIC_CLK] = &apq8064_sfab_clk,
+ [RPM_SYS_FABRIC_A_CLK] = &apq8064_sfab_a_clk,
+ [RPM_SFPB_CLK] = &apq8064_sfpb_clk,
+ [RPM_SFPB_A_CLK] = &apq8064_sfpb_a_clk,
+ [RPM_QDSS_CLK] = &apq8064_qdss_clk,
+ [RPM_QDSS_A_CLK] = &apq8064_qdss_a_clk,
+};
+
+static const struct rpm_clk_desc rpm_clk_apq8064 = {
+ .clks = apq8064_clks,
+ .num_clks = ARRAY_SIZE(apq8064_clks),
+};
+
+static const struct of_device_id rpm_clk_match_table[] = {
+ { .compatible = "qcom,rpmcc-apq8064", .data = &rpm_clk_apq8064 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rpm_clk_match_table);
+
+static int rpm_clk_probe(struct platform_device *pdev)
+{
+ struct clk_hw **hws;
+ struct rpm_cc *rcc;
+ struct clk_hw_onecell_data *data;
+ int ret;
+ size_t num_clks, i;
+ struct qcom_rpm *rpm;
+ struct clk_rpm **rpm_clks;
+ const struct rpm_clk_desc *desc;
+
+ rpm = dev_get_drvdata(pdev->dev.parent);
+ if (!rpm) {
+ dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
+ return -ENODEV;
+ }
+
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ rpm_clks = desc->clks;
+ num_clks = desc->num_clks;
+
+ rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
+ GFP_KERNEL);
+ if (!rcc)
+ return -ENOMEM;
+
+ hws = rcc->hws;
+ data = &rcc->data;
+ data->num = num_clks;
+
+ for (i = 0; i < num_clks; i++) {
+ if (!rpm_clks[i])
+ continue;
+
+ rpm_clks[i]->rpm = rpm;
+
+ ret = clk_rpm_handoff(rpm_clks[i]);
+ if (ret)
+ goto err;
+ }
+
+ for (i = 0; i < num_clks; i++) {
+ if (!rpm_clks[i]) {
+ data->hws[i] = ERR_PTR(-ENOENT);
+ continue;
+ }
+
+ ret = devm_clk_hw_register(&pdev->dev, &rpm_clks[i]->hw);
+ if (ret)
+ goto err;
+ }
+
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+ data);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ dev_err(&pdev->dev, "Error registering RPM Clock driver (%d)\n", ret);
+ return ret;
+}
+
+static int rpm_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+ return 0;
+}
+
+static struct platform_driver rpm_clk_driver = {
+ .driver = {
+ .name = "qcom-clk-rpm",
+ .of_match_table = rpm_clk_match_table,
+ },
+ .probe = rpm_clk_probe,
+ .remove = rpm_clk_remove,
+};
+
+static int __init rpm_clk_init(void)
+{
+ return platform_driver_register(&rpm_clk_driver);
+}
+core_initcall(rpm_clk_init);
+
+static void __exit rpm_clk_exit(void)
+{
+ platform_driver_unregister(&rpm_clk_driver);
+}
+module_exit(rpm_clk_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM Clock Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-clk-rpm");
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 9fae52dfe35a..5924cdb71336 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -14,6 +14,30 @@
#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
#define _DT_BINDINGS_CLK_MSM_RPMCC_H
+/* apq8064 */
+#define RPM_PXO_CLK 0
+#define RPM_PXO_A_CLK 1
+#define RPM_CXO_CLK 2
+#define RPM_CXO_A_CLK 3
+#define RPM_APPS_FABRIC_CLK 4
+#define RPM_APPS_FABRIC_A_CLK 5
+#define RPM_CFPB_CLK 6
+#define RPM_CFPB_A_CLK 7
+#define RPM_QDSS_CLK 8
+#define RPM_QDSS_A_CLK 9
+#define RPM_DAYTONA_FABRIC_CLK 10
+#define RPM_DAYTONA_FABRIC_A_CLK 11
+#define RPM_EBI1_CLK 12
+#define RPM_EBI1_A_CLK 13
+#define RPM_MM_FABRIC_CLK 14
+#define RPM_MM_FABRIC_A_CLK 15
+#define RPM_MMFPB_CLK 16
+#define RPM_MMFPB_A_CLK 17
+#define RPM_SYS_FABRIC_CLK 18
+#define RPM_SYS_FABRIC_A_CLK 19
+#define RPM_SFPB_CLK 20
+#define RPM_SFPB_A_CLK 21
+
/* msm8916 */
#define RPM_SMD_XO_CLK_SRC 0
#define RPM_SMD_XO_A_CLK_SRC 1
^ permalink raw reply related
* [PATCH v9 1/3] clk: qcom: Add support for SMD-RPM Clocks
From: Georgi Djakov @ 2016-11-02 15:56 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-clk, devicetree, robh+dt, mark.rutland, linux-kernel,
linux-arm-msm, georgi.djakov
In-Reply-To: <20161102155658.32203-1-georgi.djakov@linaro.org>
This adds initial support for clocks controlled by the Resource
Power Manager (RPM) processor on some Qualcomm SoCs, which use
the qcom_smd_rpm driver to communicate with RPM.
Such platforms are msm8916, apq8084 and msm8974.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.
This driver is based on the codeaurora.org driver:
https://www.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/clk/qcom/clock-rpm.c
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 36 ++
drivers/clk/qcom/Kconfig | 16 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
include/dt-bindings/clock/qcom,rpmcc.h | 45 ++
5 files changed, 669 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
new file mode 100644
index 000000000000..e3e13226d798
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -0,0 +1,36 @@
+Qualcomm RPM Clock Controller Binding
+------------------------------------------------
+The RPM is a dedicated hardware engine for managing the shared
+SoC resources in order to keep the lowest power profile. It
+communicates with other hardware subsystems via shared memory
+and accepts clock requests, aggregates the requests and turns
+the clocks on/off or scales them on demand.
+
+Required properties :
+- compatible : shall contain only one of the following. The generic
+ compatible "qcom,rpmcc" should be also included.
+
+ "qcom,rpmcc-msm8916", "qcom,rpmcc"
+
+- #clock-cells : shall contain 1
+
+Example:
+ smd {
+ compatible = "qcom,smd";
+
+ rpm {
+ interrupts = <0 168 1>;
+ qcom,ipc = <&apcs 8 0>;
+ qcom,smd-edge = <15>;
+
+ rpm_requests {
+ compatible = "qcom,rpm-msm8916";
+ qcom,smd-channels = "rpm_requests";
+
+ rpmcc: clock-controller {
+ compatible = "qcom,rpmcc-msm8916", "qcom,rpmcc";
+ #clock-cells = <1>;
+ };
+ };
+ };
+ };
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 0146d3c2547f..b537c59dcfe6 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -2,6 +2,9 @@ config QCOM_GDSC
bool
select PM_GENERIC_DOMAINS if PM
+config QCOM_RPMCC
+ bool
+
config COMMON_CLK_QCOM
tristate "Support for Qualcomm's clock controllers"
depends on OF
@@ -9,6 +12,19 @@ config COMMON_CLK_QCOM
select REGMAP_MMIO
select RESET_CONTROLLER
+config QCOM_CLK_SMD_RPM
+ tristate "RPM over SMD based Clock Controller"
+ depends on COMMON_CLK_QCOM && QCOM_SMD_RPM
+ select QCOM_RPMCC
+ help
+ The RPM (Resource Power Manager) is a dedicated hardware engine for
+ managing the shared SoC resources in order to keep the lowest power
+ profile. It communicates with other hardware subsystems via shared
+ memory and accepts clock requests, aggregates the requests and turns
+ the clocks on/off or scales them on demand.
+ Say Y if you want to support the clocks exposed by the RPM on
+ platforms such as apq8016, apq8084, msm8974 etc.
+
config APQ_GCC_8084
tristate "APQ8084 Global Clock Controller"
select QCOM_GDSC
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 1fb1f5476cb0..0dd72e56b7e4 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -29,3 +29,4 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o
obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o
obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o
+obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
new file mode 100644
index 000000000000..8aba9ab2ccfd
--- /dev/null
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -0,0 +1,571 @@
+/*
+ * Copyright (c) 2016, Linaro Limited
+ * Copyright (c) 2014, The Linux Foundation. All rights reserved.
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/err.h>
+#include <linux/export.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/soc/qcom/smd-rpm.h>
+
+#include <dt-bindings/clock/qcom,rpmcc.h>
+#include <dt-bindings/mfd/qcom-rpm.h>
+
+#define QCOM_RPM_KEY_SOFTWARE_ENABLE 0x6e657773
+#define QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY 0x62636370
+#define QCOM_RPM_SMD_KEY_RATE 0x007a484b
+#define QCOM_RPM_SMD_KEY_ENABLE 0x62616e45
+#define QCOM_RPM_SMD_KEY_STATE 0x54415453
+#define QCOM_RPM_SCALING_ENABLE_ID 0x2
+
+#define __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, stat_id, \
+ key) \
+ static struct clk_smd_rpm _platform##_##_active; \
+ static struct clk_smd_rpm _platform##_##_name = { \
+ .rpm_res_type = (type), \
+ .rpm_clk_id = (r_id), \
+ .rpm_status_id = (stat_id), \
+ .rpm_key = (key), \
+ .peer = &_platform##_##_active, \
+ .rate = INT_MAX, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_smd_rpm_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_smd_rpm _platform##_##_active = { \
+ .rpm_res_type = (type), \
+ .rpm_clk_id = (r_id), \
+ .rpm_status_id = (stat_id), \
+ .active_only = true, \
+ .rpm_key = (key), \
+ .peer = &_platform##_##_name, \
+ .rate = INT_MAX, \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_smd_rpm_ops, \
+ .name = #_active, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, \
+ stat_id, r, key) \
+ static struct clk_smd_rpm _platform##_##_active; \
+ static struct clk_smd_rpm _platform##_##_name = { \
+ .rpm_res_type = (type), \
+ .rpm_clk_id = (r_id), \
+ .rpm_status_id = (stat_id), \
+ .rpm_key = (key), \
+ .branch = true, \
+ .peer = &_platform##_##_active, \
+ .rate = (r), \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_smd_rpm_branch_ops, \
+ .name = #_name, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }; \
+ static struct clk_smd_rpm _platform##_##_active = { \
+ .rpm_res_type = (type), \
+ .rpm_clk_id = (r_id), \
+ .rpm_status_id = (stat_id), \
+ .active_only = true, \
+ .rpm_key = (key), \
+ .branch = true, \
+ .peer = &_platform##_##_name, \
+ .rate = (r), \
+ .hw.init = &(struct clk_init_data){ \
+ .ops = &clk_smd_rpm_branch_ops, \
+ .name = #_active, \
+ .parent_names = (const char *[]){ "xo_board" }, \
+ .num_parents = 1, \
+ }, \
+ }
+
+#define DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id) \
+ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
+ 0, QCOM_RPM_SMD_KEY_RATE)
+
+#define DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, r_id, r) \
+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, type, \
+ r_id, 0, r, QCOM_RPM_SMD_KEY_ENABLE)
+
+#define DEFINE_CLK_SMD_RPM_QDSS(_platform, _name, _active, type, r_id) \
+ __DEFINE_CLK_SMD_RPM(_platform, _name, _active, type, r_id, \
+ 0, QCOM_RPM_SMD_KEY_STATE)
+
+#define DEFINE_CLK_SMD_RPM_XO_BUFFER(_platform, _name, _active, r_id) \
+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
+ QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
+ QCOM_RPM_KEY_SOFTWARE_ENABLE)
+
+#define DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(_platform, _name, _active, r_id) \
+ __DEFINE_CLK_SMD_RPM_BRANCH(_platform, _name, _active, \
+ QCOM_SMD_RPM_CLK_BUF_A, r_id, 0, 1000, \
+ QCOM_RPM_KEY_PIN_CTRL_CLK_BUFFER_ENABLE_KEY)
+
+#define to_clk_smd_rpm(_hw) container_of(_hw, struct clk_smd_rpm, hw)
+
+struct clk_smd_rpm {
+ const int rpm_res_type;
+ const int rpm_key;
+ const int rpm_clk_id;
+ const int rpm_status_id;
+ const bool active_only;
+ bool enabled;
+ bool branch;
+ struct clk_smd_rpm *peer;
+ struct clk_hw hw;
+ unsigned long rate;
+ struct qcom_smd_rpm *rpm;
+};
+
+struct clk_smd_rpm_req {
+ __le32 key;
+ __le32 nbytes;
+ __le32 value;
+};
+
+struct rpm_cc {
+ struct qcom_rpm *rpm;
+ struct clk_hw_onecell_data data;
+ struct clk_hw *hws[];
+};
+
+struct rpm_smd_clk_desc {
+ struct clk_smd_rpm **clks;
+ size_t num_clks;
+};
+
+static DEFINE_MUTEX(rpm_smd_clk_lock);
+
+static int clk_smd_rpm_handoff(struct clk_smd_rpm *r)
+{
+ int ret;
+ struct clk_smd_rpm_req req = {
+ .key = cpu_to_le32(r->rpm_key),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(INT_MAX),
+ };
+
+ ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
+ r->rpm_res_type, r->rpm_clk_id, &req,
+ sizeof(req));
+ if (ret)
+ return ret;
+ ret = qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
+ r->rpm_res_type, r->rpm_clk_id, &req,
+ sizeof(req));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int clk_smd_rpm_set_rate_active(struct clk_smd_rpm *r,
+ unsigned long rate)
+{
+ struct clk_smd_rpm_req req = {
+ .key = cpu_to_le32(r->rpm_key),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
+ };
+
+ return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_ACTIVE_STATE,
+ r->rpm_res_type, r->rpm_clk_id, &req,
+ sizeof(req));
+}
+
+static int clk_smd_rpm_set_rate_sleep(struct clk_smd_rpm *r,
+ unsigned long rate)
+{
+ struct clk_smd_rpm_req req = {
+ .key = cpu_to_le32(r->rpm_key),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(DIV_ROUND_UP(rate, 1000)), /* to kHz */
+ };
+
+ return qcom_rpm_smd_write(r->rpm, QCOM_SMD_RPM_SLEEP_STATE,
+ r->rpm_res_type, r->rpm_clk_id, &req,
+ sizeof(req));
+}
+
+static void to_active_sleep(struct clk_smd_rpm *r, unsigned long rate,
+ unsigned long *active, unsigned long *sleep)
+{
+ *active = rate;
+
+ /*
+ * Active-only clocks don't care what the rate is during sleep. So,
+ * they vote for zero.
+ */
+ if (r->active_only)
+ *sleep = 0;
+ else
+ *sleep = *active;
+}
+
+static int clk_smd_rpm_prepare(struct clk_hw *hw)
+{
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+ struct clk_smd_rpm *peer = r->peer;
+ unsigned long this_rate = 0, this_sleep_rate = 0;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ unsigned long active_rate, sleep_rate;
+ int ret = 0;
+
+ mutex_lock(&rpm_smd_clk_lock);
+
+ /* Don't send requests to the RPM if the rate has not been set. */
+ if (!r->rate)
+ goto out;
+
+ to_active_sleep(r, r->rate, &this_rate, &this_sleep_rate);
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate,
+ &peer_rate, &peer_sleep_rate);
+
+ active_rate = max(this_rate, peer_rate);
+
+ if (r->branch)
+ active_rate = !!active_rate;
+
+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+ if (r->branch)
+ sleep_rate = !!sleep_rate;
+
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ /* Undo the active set vote and restore it */
+ ret = clk_smd_rpm_set_rate_active(r, peer_rate);
+
+out:
+ if (!ret)
+ r->enabled = true;
+
+ mutex_unlock(&rpm_smd_clk_lock);
+
+ return ret;
+}
+
+static void clk_smd_rpm_unprepare(struct clk_hw *hw)
+{
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+ struct clk_smd_rpm *peer = r->peer;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ unsigned long active_rate, sleep_rate;
+ int ret;
+
+ mutex_lock(&rpm_smd_clk_lock);
+
+ if (!r->rate)
+ goto out;
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate, &peer_rate,
+ &peer_sleep_rate);
+
+ active_rate = r->branch ? !!peer_rate : peer_rate;
+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = r->branch ? !!peer_sleep_rate : peer_sleep_rate;
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ goto out;
+
+ r->enabled = false;
+
+out:
+ mutex_unlock(&rpm_smd_clk_lock);
+}
+
+static int clk_smd_rpm_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+ struct clk_smd_rpm *peer = r->peer;
+ unsigned long active_rate, sleep_rate;
+ unsigned long this_rate = 0, this_sleep_rate = 0;
+ unsigned long peer_rate = 0, peer_sleep_rate = 0;
+ int ret = 0;
+
+ mutex_lock(&rpm_smd_clk_lock);
+
+ if (!r->enabled)
+ goto out;
+
+ to_active_sleep(r, rate, &this_rate, &this_sleep_rate);
+
+ /* Take peer clock's rate into account only if it's enabled. */
+ if (peer->enabled)
+ to_active_sleep(peer, peer->rate,
+ &peer_rate, &peer_sleep_rate);
+
+ active_rate = max(this_rate, peer_rate);
+ ret = clk_smd_rpm_set_rate_active(r, active_rate);
+ if (ret)
+ goto out;
+
+ sleep_rate = max(this_sleep_rate, peer_sleep_rate);
+ ret = clk_smd_rpm_set_rate_sleep(r, sleep_rate);
+ if (ret)
+ goto out;
+
+ r->rate = rate;
+
+out:
+ mutex_unlock(&rpm_smd_clk_lock);
+
+ return ret;
+}
+
+static long clk_smd_rpm_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *parent_rate)
+{
+ /*
+ * RPM handles rate rounding and we don't have a way to
+ * know what the rate will be, so just return whatever
+ * rate is requested.
+ */
+ return rate;
+}
+
+static unsigned long clk_smd_rpm_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_smd_rpm *r = to_clk_smd_rpm(hw);
+
+ /*
+ * RPM handles rate rounding and we don't have a way to
+ * know what the rate will be, so just return whatever
+ * rate was set.
+ */
+ return r->rate;
+}
+
+static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
+{
+ int ret;
+ struct clk_smd_rpm_req req = {
+ .key = cpu_to_le32(QCOM_RPM_SMD_KEY_ENABLE),
+ .nbytes = cpu_to_le32(sizeof(u32)),
+ .value = cpu_to_le32(1),
+ };
+
+ ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_SLEEP_STATE,
+ QCOM_SMD_RPM_MISC_CLK,
+ QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
+ if (ret) {
+ pr_err("RPM clock scaling (sleep set) not enabled!\n");
+ return ret;
+ }
+
+ ret = qcom_rpm_smd_write(rpm, QCOM_SMD_RPM_ACTIVE_STATE,
+ QCOM_SMD_RPM_MISC_CLK,
+ QCOM_RPM_SCALING_ENABLE_ID, &req, sizeof(req));
+ if (ret) {
+ pr_err("RPM clock scaling (active set) not enabled!\n");
+ return ret;
+ }
+
+ pr_debug("%s: RPM clock scaling is enabled\n", __func__);
+ return 0;
+}
+
+static const struct clk_ops clk_smd_rpm_ops = {
+ .prepare = clk_smd_rpm_prepare,
+ .unprepare = clk_smd_rpm_unprepare,
+ .set_rate = clk_smd_rpm_set_rate,
+ .round_rate = clk_smd_rpm_round_rate,
+ .recalc_rate = clk_smd_rpm_recalc_rate,
+};
+
+static const struct clk_ops clk_smd_rpm_branch_ops = {
+ .prepare = clk_smd_rpm_prepare,
+ .unprepare = clk_smd_rpm_unprepare,
+ .round_rate = clk_smd_rpm_round_rate,
+ .recalc_rate = clk_smd_rpm_recalc_rate,
+};
+
+/* msm8916 */
+DEFINE_CLK_SMD_RPM(msm8916, pcnoc_clk, pcnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8916, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8916, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM_QDSS(msm8916, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk1, bb_clk1_a, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, bb_clk2, bb_clk2_a, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk1, rf_clk1_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8916, rf_clk2, rf_clk2_a, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk1_pin, bb_clk1_a_pin, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, bb_clk2_pin, bb_clk2_a_pin, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk1_pin, rf_clk1_a_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8916, rf_clk2_pin, rf_clk2_a_pin, 5);
+
+static struct clk_smd_rpm *msm8916_clks[] = {
+ [RPM_SMD_PCNOC_CLK] = &msm8916_pcnoc_clk,
+ [RPM_SMD_PCNOC_A_CLK] = &msm8916_pcnoc_a_clk,
+ [RPM_SMD_SNOC_CLK] = &msm8916_snoc_clk,
+ [RPM_SMD_SNOC_A_CLK] = &msm8916_snoc_a_clk,
+ [RPM_SMD_BIMC_CLK] = &msm8916_bimc_clk,
+ [RPM_SMD_BIMC_A_CLK] = &msm8916_bimc_a_clk,
+ [RPM_SMD_QDSS_CLK] = &msm8916_qdss_clk,
+ [RPM_SMD_QDSS_A_CLK] = &msm8916_qdss_a_clk,
+ [RPM_SMD_BB_CLK1] = &msm8916_bb_clk1,
+ [RPM_SMD_BB_CLK1_A] = &msm8916_bb_clk1_a,
+ [RPM_SMD_BB_CLK2] = &msm8916_bb_clk2,
+ [RPM_SMD_BB_CLK2_A] = &msm8916_bb_clk2_a,
+ [RPM_SMD_RF_CLK1] = &msm8916_rf_clk1,
+ [RPM_SMD_RF_CLK1_A] = &msm8916_rf_clk1_a,
+ [RPM_SMD_RF_CLK2] = &msm8916_rf_clk2,
+ [RPM_SMD_RF_CLK2_A] = &msm8916_rf_clk2_a,
+ [RPM_SMD_BB_CLK1_PIN] = &msm8916_bb_clk1_pin,
+ [RPM_SMD_BB_CLK1_A_PIN] = &msm8916_bb_clk1_a_pin,
+ [RPM_SMD_BB_CLK2_PIN] = &msm8916_bb_clk2_pin,
+ [RPM_SMD_BB_CLK2_A_PIN] = &msm8916_bb_clk2_a_pin,
+ [RPM_SMD_RF_CLK1_PIN] = &msm8916_rf_clk1_pin,
+ [RPM_SMD_RF_CLK1_A_PIN] = &msm8916_rf_clk1_a_pin,
+ [RPM_SMD_RF_CLK2_PIN] = &msm8916_rf_clk2_pin,
+ [RPM_SMD_RF_CLK2_A_PIN] = &msm8916_rf_clk2_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
+ .clks = msm8916_clks,
+ .num_clks = ARRAY_SIZE(msm8916_clks),
+};
+
+static const struct of_device_id rpm_smd_clk_match_table[] = {
+ { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
+ { }
+};
+MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
+
+static int rpm_smd_clk_probe(struct platform_device *pdev)
+{
+ struct clk_hw **hws;
+ struct rpm_cc *rcc;
+ struct clk_hw_onecell_data *data;
+ int ret;
+ size_t num_clks, i;
+ struct qcom_smd_rpm *rpm;
+ struct clk_smd_rpm **rpm_smd_clks;
+ const struct rpm_smd_clk_desc *desc;
+
+ rpm = dev_get_drvdata(pdev->dev.parent);
+ if (!rpm) {
+ dev_err(&pdev->dev, "Unable to retrieve handle to RPM\n");
+ return -ENODEV;
+ }
+
+ desc = of_device_get_match_data(&pdev->dev);
+ if (!desc)
+ return -EINVAL;
+
+ rpm_smd_clks = desc->clks;
+ num_clks = desc->num_clks;
+
+ rcc = devm_kzalloc(&pdev->dev, sizeof(*rcc) + sizeof(*hws) * num_clks,
+ GFP_KERNEL);
+ if (!rcc)
+ return -ENOMEM;
+
+ hws = rcc->hws;
+ data = &rcc->data;
+ data->num = num_clks;
+
+ for (i = 0; i < num_clks; i++) {
+ if (!rpm_smd_clks[i]) {
+ continue;
+ }
+
+ rpm_smd_clks[i]->rpm = rpm;
+
+ ret = clk_smd_rpm_handoff(rpm_smd_clks[i]);
+ if (ret)
+ goto err;
+ }
+
+ ret = clk_smd_rpm_enable_scaling(rpm);
+ if (ret)
+ goto err;
+
+ for (i = 0; i < num_clks; i++) {
+ if (!rpm_smd_clks[i]) {
+ data->hws[i] = ERR_PTR(-ENOENT);
+ continue;
+ }
+
+ ret = devm_clk_hw_register(&pdev->dev, &rpm_smd_clks[i]->hw);
+ if (ret)
+ goto err;
+ }
+
+ ret = of_clk_add_hw_provider(pdev->dev.of_node, of_clk_hw_onecell_get,
+ data);
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ dev_err(&pdev->dev, "Error registering SMD clock driver (%d)\n", ret);
+ return ret;
+}
+
+static int rpm_smd_clk_remove(struct platform_device *pdev)
+{
+ of_clk_del_provider(pdev->dev.of_node);
+ return 0;
+}
+
+static struct platform_driver rpm_smd_clk_driver = {
+ .driver = {
+ .name = "qcom-clk-smd-rpm",
+ .of_match_table = rpm_smd_clk_match_table,
+ },
+ .probe = rpm_smd_clk_probe,
+ .remove = rpm_smd_clk_remove,
+};
+
+static int __init rpm_smd_clk_init(void)
+{
+ return platform_driver_register(&rpm_smd_clk_driver);
+}
+core_initcall(rpm_smd_clk_init);
+
+static void __exit rpm_smd_clk_exit(void)
+{
+ platform_driver_unregister(&rpm_smd_clk_driver);
+}
+module_exit(rpm_smd_clk_exit);
+
+MODULE_DESCRIPTION("Qualcomm RPM over SMD Clock Controller Driver");
+MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:qcom-clk-smd-rpm");
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
new file mode 100644
index 000000000000..9fae52dfe35a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2015 Linaro Limited
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
+#define _DT_BINDINGS_CLK_MSM_RPMCC_H
+
+/* msm8916 */
+#define RPM_SMD_XO_CLK_SRC 0
+#define RPM_SMD_XO_A_CLK_SRC 1
+#define RPM_SMD_PCNOC_CLK 2
+#define RPM_SMD_PCNOC_A_CLK 3
+#define RPM_SMD_SNOC_CLK 4
+#define RPM_SMD_SNOC_A_CLK 5
+#define RPM_SMD_BIMC_CLK 6
+#define RPM_SMD_BIMC_A_CLK 7
+#define RPM_SMD_QDSS_CLK 8
+#define RPM_SMD_QDSS_A_CLK 9
+#define RPM_SMD_BB_CLK1 10
+#define RPM_SMD_BB_CLK1_A 11
+#define RPM_SMD_BB_CLK2 12
+#define RPM_SMD_BB_CLK2_A 13
+#define RPM_SMD_RF_CLK1 14
+#define RPM_SMD_RF_CLK1_A 15
+#define RPM_SMD_RF_CLK2 16
+#define RPM_SMD_RF_CLK2_A 17
+#define RPM_SMD_BB_CLK1_PIN 18
+#define RPM_SMD_BB_CLK1_A_PIN 19
+#define RPM_SMD_BB_CLK2_PIN 20
+#define RPM_SMD_BB_CLK2_A_PIN 21
+#define RPM_SMD_RF_CLK1_PIN 22
+#define RPM_SMD_RF_CLK1_A_PIN 23
+#define RPM_SMD_RF_CLK2_PIN 24
+#define RPM_SMD_RF_CLK2_A_PIN 25
+
+#endif
^ permalink raw reply related
* [PATCH v9 0/3] Add initial support for RPM clocks
From: Georgi Djakov @ 2016-11-02 15:56 UTC (permalink / raw)
To: sboyd, mturquette
Cc: linux-clk, devicetree, robh+dt, mark.rutland, linux-kernel,
linux-arm-msm, georgi.djakov
This patchset adds initial support for the clocks controlled by
the RPM (Resource Power Manager) processor on Qualcomm platforms.
The RPM is a dedicated hardware engine for managing the shared
SoC resources in order to keep the lowest power profile. It
communicates with other hardware subsystems via shared memory
and accepts clock requests, aggregates the requests and turns
the clocks on/off or scales them on demand.
Until now the RPM clock controller was not supported and a hard-
coded fixed-rate clocks were registered in the drivers. Now we
are moving the on-board clocks to the DT (where they actually
belong). If the RPM clock controller is enabled we insert it
right after the DT clocks making it a parent of some GCC clocks.
Changes since v8 (https://lkml.org/lkml/2016/4/14/495)
* Rebase and switch to clk_hw APIs
* Drop registration of all xo/cxo/pxo clocks and replace patch 3
with another one, which always registers factor clocks. With
this approuch we avoid having a DT dependency.
Changes since v7 (https://lkml.org/lkml/2016/2/23/542)
* Add handoff support.
* Remove smd-rpm XO clocks until clk deferring is supported.
Changes since v6 (https://lkml.org/lkml/2015/12/15/279)
* Remove header files and exported ops.
* Add support for active only RPM clocks.
Changes since v5 (https://lkml.org/lkml/2015/12/3/376)
* Drop all DT patches as they are already picked.
* Fix dependencies in Kconfig.
* Minor changes.
Changes since v4 (https://lkml.org/lkml/2015/11/19/309)
* Re-organize code into two separate drivers:
- clk-smd-rpm for RPM over SMD based clocks like msm8916
- clk-rpm for RPM based clocks like apq8064
* Drop the patches that are already merged.
* Added the extra compatible string to docs and example.
Changes since v3 (https://lkml.org/lkml/2015/10/20/613)
* Drop some of the patches as now we handle both scenarios -
RPMCC enabled or disabled.
* Addressed more comments from Stephen. Thanks again!
Changes since v2 (https://lkml.org/lkml/2015/8/3/513)
* Addressed various comments from Stephen. Thanks!
* Added sleep sets support.
* Added a mutex in the RPM driver.
* Support both scenarios - RPMCC enabled or disabled.
* Make RPMCC more generic in order to support other SMD RPM
based platforms.
Changes since v1 (https://lkml.org/lkml/2015/7/9/257):
* Changed the driver name to clk-smd-rpm, also build it only
when it is needed - suggested by Srini and Bjorn.
* More detailed binding example.
* Minor changes.
Georgi Djakov (3):
clk: qcom: Add support for SMD-RPM Clocks
clk: qcom: Add support for RPM Clocks
clk: qcom: Always add factor clock for xo clocks
.../devicetree/bindings/clock/qcom,rpmcc.txt | 37 ++
drivers/clk/qcom/Kconfig | 29 ++
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/clk-rpm.c | 489 ++++++++++++++++++
drivers/clk/qcom/clk-smd-rpm.c | 571 +++++++++++++++++++++
drivers/clk/qcom/common.c | 15 +-
include/dt-bindings/clock/qcom,rpmcc.h | 69 +++
7 files changed, 1203 insertions(+), 9 deletions(-)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
create mode 100644 drivers/clk/qcom/clk-rpm.c
create mode 100644 drivers/clk/qcom/clk-smd-rpm.c
create mode 100644 include/dt-bindings/clock/qcom,rpmcc.h
^ permalink raw reply
* Re: [PATCH 2/2] clk: renesas: cpg-mssr: add R8A7745 support
From: Geert Uytterhoeven @ 2016-11-02 15:47 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Michael Turquette, linux-clk, Stephen Boyd, Rob Herring,
Mark Rutland, devicetree@vger.kernel.org, Linux-Renesas,
Simon Horman
In-Reply-To: <5012234.NZmvoVqhq0@wasted.cogentembedded.com>
Hi Sergei,
On Thu, Oct 27, 2016 at 10:43 PM, Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Add RZ/G1E (R8A7745) Clock Pulse Generator / Module Standby and Software
> Reset support, using the CPG/MSSR driver core and the common R-Car Gen2
> (and RZ/G) code.
>
> Based on the proof-of-concept R8A7791 CPG/MSSR patch by Geert Uytterhoeven
> <geert+renesas@glider.be>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks a lot for your patch!
> --- /dev/null
> +++ linux/drivers/clk/renesas/r8a7745-cpg-mssr.c
> @@ -0,0 +1,261 @@
> +static const struct cpg_core_clk r8a7745_core_clks[] __initconst = {
> + /* Core Clock Outputs */
> + DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1),
If you remove the "div = 3" in rcar-gen2-cpg.c, you can use "... 3, 1" here,
cfr. zg, zx, and zs below.
> + DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1),
> + DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1),
> + DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),
> +static const struct mssr_mod_clk r8a7745_mod_clks[] __initconst = {
> + DEF_MOD("fdp1-1", 118, R8A7745_CLK_ZS),
FDP1-1 does not exist on RZ/G1E.
With these fixed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* [PATCH v2 2/2] mmc: sdhci: Use sdhci-caps-mask and sdhci-caps to change the caps read during __sdhci_read_caps
From: Zach Brown @ 2016-11-02 15:26 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A
Cc: adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, zach.brown-acOepvfBmUk
In-Reply-To: <1478100376-602-1-git-send-email-zach.brown-acOepvfBmUk@public.gmane.org>
The sdhci capabilities register can be incorrect. The sdhci-caps-mask
and sdhci-caps dt properties specify which bits of the register are
incorrect and what their values should be. This patch makes the sdhci
driver use those properties to correct the caps during
__sdhci_read_caps.
During __sdhci_read_caps
Use the sdhci-caps-mask property to turn off the incorrect bits of the
sdhci register after reading them.
Use the sdhci-caps to turn on bits after using sdhci-caps-mask to turn
off the incorrect ones.
Signed-off-by: Zach Brown <zach.brown-acOepvfBmUk@public.gmane.org>
Acked-by: Adrian Hunter <adrian.hunter-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
---
drivers/mmc/host/sdhci.c | 24 ++++++++++++++++++++++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 1e25b01..eba5f39 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -22,6 +22,7 @@
#include <linux/scatterlist.h>
#include <linux/regulator/consumer.h>
#include <linux/pm_runtime.h>
+#include <linux/of.h>
#include <linux/leds.h>
@@ -2991,6 +2992,8 @@ static int sdhci_set_dma_mask(struct sdhci_host *host)
void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
{
u16 v;
+ u64 dt_caps_mask = 0;
+ u64 dt_caps = 0;
if (host->read_caps)
return;
@@ -3005,18 +3008,35 @@ void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1)
sdhci_do_reset(host, SDHCI_RESET_ALL);
+ of_property_read_u64(mmc_dev(host->mmc)->of_node,
+ "sdhci-caps-mask", &dt_caps_mask);
+ of_property_read_u64(mmc_dev(host->mmc)->of_node,
+ "sdhci-caps", &dt_caps);
+
v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION);
host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT;
if (host->quirks & SDHCI_QUIRK_MISSING_CAPS)
return;
- host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES);
+ if (caps) {
+ host->caps = *caps;
+ } else {
+ host->caps = sdhci_readl(host, SDHCI_CAPABILITIES);
+ host->caps &= ~lower_32_bits(dt_caps_mask);
+ host->caps |= lower_32_bits(dt_caps);
+ }
if (host->version < SDHCI_SPEC_300)
return;
- host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ if (caps1) {
+ host->caps1 = *caps1;
+ } else {
+ host->caps1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
+ host->caps1 &= ~upper_32_bits(dt_caps_mask);
+ host->caps1 |= upper_32_bits(dt_caps);
+ }
}
EXPORT_SYMBOL_GPL(__sdhci_read_caps);
--
2.7.4
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^ permalink raw reply related
* [PATCH v2 1/2] mmc: sdhci: dt: Add device tree properties sdhci-caps and sdhci-caps-mask
From: Zach Brown @ 2016-11-02 15:26 UTC (permalink / raw)
To: ulf.hansson
Cc: adrian.hunter, robh+dt, mark.rutland, linux-mmc, devicetree,
linux-kernel, zach.brown
In-Reply-To: <1478100376-602-1-git-send-email-zach.brown@ni.com>
On some systems the sdhci capabilty register is incorrect for one
reason or another.
The sdhci-caps-mask property specifies which bits in the register
are incorrect and should be turned off before using sdhci-caps to turn
on bits.
The sdhci-caps property specifies which bits should be turned on.
Signed-off-by: Zach Brown <zach.brown@ni.com>
Acked-by: Rob Herring <robh@kernel.org>
---
Documentation/devicetree/bindings/mmc/sdhci.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci.txt
diff --git a/Documentation/devicetree/bindings/mmc/sdhci.txt b/Documentation/devicetree/bindings/mmc/sdhci.txt
new file mode 100644
index 0000000..0f4f1bb
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/sdhci.txt
@@ -0,0 +1,14 @@
+The properties specific for SD host controllers. For properties shared by MMC
+host controllers refer to the mmc[1] bindings.
+
+ [1] Documentation/devicetree/bindings/mmc/mmc.txt
+
+Optional properties:
+- sdhci-caps-mask: The sdhci capabilities register is incorrect. This 64bit
+ property corresponds to the bits in the sdhci capabilty register. If the bit
+ is on in the mask then the bit is incorrect in the register and should be
+ turned off, before applying sdhci-caps.
+- sdhci-caps: The sdhci capabilities register is incorrect. This 64bit
+ property corresponds to the bits in the sdhci capability register. If the
+ bit is on in the property then the bit should be turned on.
+
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/2] mmc: sdhci: Fix sdhci caps register bits with corrections provided by dt
From: Zach Brown @ 2016-11-02 15:26 UTC (permalink / raw)
To: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A
Cc: adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, zach.brown-acOepvfBmUk
For various reasons the sdhci caps register can be incorrect. This patch set
introduces a general way to correct the bits when they are read to accurately
reflect the capabilties of the controller/board combo.
The first patch creates sdhci-caps and sdhci-caps-mask dt properties that
combined represent the correction to the sdhci caps register.
The second patch uses the new dt properties to correct the caps from the
register as they read during __sdhci_read_caps.
Changes from RFC:
* /s/registers/register
* Moved sdhci dt properties into new documentation file sdhci.txt
v2:
* Fixed style issue, all branches of 'if' should have {}
Zach Brown (2):
mmc: sdhci: dt: Add device tree properties sdhci-caps and
sdhci-caps-mask
mmc: sdhci: Use sdhci-caps-mask and sdhci-caps to change the caps read
during __sdhci_read_caps
Documentation/devicetree/bindings/mmc/sdhci.txt | 14 ++++++++++++++
drivers/mmc/host/sdhci.c | 24 ++++++++++++++++++++++--
2 files changed, 36 insertions(+), 2 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mmc/sdhci.txt
--
2.7.4
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^ permalink raw reply
* Re: [PATCH] clk: cdce925: add support for CDCE913, CDCE937, and CDCE949
From: Akinobu Mita @ 2016-11-02 14:42 UTC (permalink / raw)
To: Stephen Boyd
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA, open list:OPEN FIRMWARE AND...,
Mike Looijmans, Michael Turquette
In-Reply-To: <20161101174808.GU16026-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2016-11-02 2:48 GMT+09:00 Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>:
> On 11/01, Akinobu Mita wrote:
>> 2016-11-01 3:15 GMT+09:00 Stephen Boyd <sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>:
>> > On 10/31, Akinobu Mita wrote:
>> >> @@ -728,13 +780,19 @@ static int cdce925_probe(struct i2c_client *client,
>> >> }
>> >>
>> >> static const struct i2c_device_id cdce925_id[] = {
>> >> - { "cdce925", 0 },
>> >> + { "cdce913", CDCE913 },
>> >> + { "cdce925", CDCE925 },
>> >> + { "cdce937", CDCE937 },
>> >> + { "cdce949", CDCE949 },
>> >> { }
>> >> };
>> >> MODULE_DEVICE_TABLE(i2c, cdce925_id);
>> >>
>> >> static const struct of_device_id clk_cdce925_of_match[] = {
>> >> + { .compatible = "ti,cdce913" },
>> >> { .compatible = "ti,cdce925" },
>> >> + { .compatible = "ti,cdce937" },
>> >> + { .compatible = "ti,cdce949" },
>> >
>> > Doesn't this need to be updated to point to the correct enum
>> > values?
>>
>> I think it isn't needed. Because the data field in struct of_device_id
>> for this driver is not used even if the device is registered from
>> device tree. But the driver_data in i2c_device_id is used instead.
>
> Ok. Have you tested this driver with DT or platform data? Do you
> prefix the compatible string with "ti," in the DT case?
I have tested with DT with compatible = "ti,cdce937" and checked that
correct i2c_device_id is passed by the caller of cdce925_probe().
According to of_i2c_register_device() in drivers/i2c/i2c-core.c,
the manufacturer prefix like "ti," is stripped from i2c_client->name by
of_modalias_node(). So i2c_match_id() can find correct i2c_device_id
entry and ->probe() is called with it.
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^ permalink raw reply
* [PATCH v2 6/6] pinctrl: aspeed-g5: Add mux configuration for all pins
From: Andrew Jeffery @ 2016-11-02 14:38 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andrew Jeffery
In-Reply-To: <1478097481-14895-1-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
The patch introducing the g5 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms and the AST2500 evaluation board.
Now, update the bindings document to reflect the complete functionality
and implement the necessary pin configuration tables in the driver.
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
Acked-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
---
No significant change since v1.
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 17 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1475 +++++++++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 1 +
3 files changed, 1486 insertions(+), 7 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index f5c427d11337..f16be8fe6c76 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -53,10 +53,19 @@ VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
-GPID0 GPID2 GPIE0 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8
-I2C9 MAC1LINK MDIO1 MDIO2 OSCCLK PEWAKE PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7
-RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
-TIMER7 TIMER8 VGABIOSROM
+ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
+ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT ESPI FWSPICS1 FWSPICS2 GPID0 GPID2 GPID4
+GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4 I2C5 I2C6
+I2C7 I2C8 I2C9 LAD0 LAD1 LAD2 LAD3 LCLK LFRAME LPCHC LPCPD LPCPLUS LPCPME
+LPCRST LPCSMI LSIRQ MAC1LINK MAC2LINK MDIO1 MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1
+NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4 NDTR1 NDTR2 NDTR3 NDTR4 NRI1 NRI2
+NRI3 NRI4 NRTS1 NRTS2 NRTS3 NRTS4 OSCCLK PEWAKE PNOR PWM0 PWM1 PWM2 PWM3 PWM4
+PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 RXD1 RXD2 RXD3 RXD4 SALT1 SALT10
+SALT11 SALT12 SALT13 SALT14 SALT2 SALT3 SALT4 SALT5 SALT6 SALT7 SALT8 SALT9
+SCL1 SCL2 SD1 SD2 SDA1 SDA2 SGPS1 SGPS2 SIOONCTRL SIOPBI SIOPBO SIOPWREQ
+SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1CS1 SPI1DEBUG SPI1PASSTHRU SPI2CK SPI2CS0
+SPI2CS1 SPI2MISO SPI2MOSI TIMER3 TIMER4 TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2
+TXD3 TXD4 UART6 USBCKI VGABIOSROM VGAHS VGAVS VPI24 VPO WDTRST1 WDTRST2
g4 Example:
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 99c4fa9bf861..9d4ad10dd1c6 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -25,14 +25,27 @@
#include "../pinctrl-utils.h"
#include "pinctrl-aspeed.h"
-#define ASPEED_G5_NR_PINS 228
+#define ASPEED_G5_NR_PINS 232
#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
+#define LHCR0 0x00
+#define GFX064 0x64
+
#define B14 0
SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
+#define D14 1
+SSSF_PIN_DECL(D14, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
+
+#define D13 2
+SIG_EXPR_LIST_DECL_SINGLE(SPI1CS1, SPI1CS1, SIG_DESC_SET(SCU80, 15));
+SIG_EXPR_LIST_DECL_SINGLE(TIMER3, TIMER3, SIG_DESC_SET(SCU80, 2));
+MS_PIN_DECL(D13, GPIOA2, SPI1CS1, TIMER3);
+FUNC_GROUP_DECL(SPI1CS1, D13);
+FUNC_GROUP_DECL(TIMER3, D13);
+
#define E13 3
SSSF_PIN_DECL(E13, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
@@ -72,6 +85,32 @@ FUNC_GROUP_DECL(TIMER8, B13);
FUNC_GROUP_DECL(MDIO2, C13, B13);
+#define K19 8
+GPIO_PIN_DECL(K19, GPIOB0);
+
+#define L19 9
+GPIO_PIN_DECL(L19, GPIOB1);
+
+#define L18 10
+GPIO_PIN_DECL(L18, GPIOB2);
+
+#define K18 11
+GPIO_PIN_DECL(K18, GPIOB3);
+
+#define J20 12
+SSSF_PIN_DECL(J20, GPIOB4, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
+
+#define H21 13
+#define H21_DESC SIG_DESC_SET(SCU80, 13)
+SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H21_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LPCSMI, LPCSMI, H21_DESC);
+MS_PIN_DECL(H21, GPIOB5, LPCPD, LPCSMI);
+FUNC_GROUP_DECL(LPCPD, H21);
+FUNC_GROUP_DECL(LPCSMI, H21);
+
+#define H22 14
+SSSF_PIN_DECL(H22, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
+
#define H20 15
GPIO_PIN_DECL(H20, GPIOB7);
@@ -168,7 +207,44 @@ MS_PIN_DECL(D20, GPIOD3, SD2DAT1, GPID2OUT);
FUNC_GROUP_DECL(GPID2, F20, D20);
-#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 21)
+#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
+
+#define D21 28
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
+SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
+MS_PIN_DECL(D21, GPIOD4, SD2DAT2, GPID4IN);
+
+#define E20 29
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
+SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
+MS_PIN_DECL(E20, GPIOD5, SD2DAT3, GPID4OUT);
+
+FUNC_GROUP_DECL(GPID4, D21, E20);
+
+#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
+
+#define G18 30
+SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
+SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
+MS_PIN_DECL(G18, GPIOD6, SD2CD, GPID6IN);
+
+#define C21 31
+SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
+SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
+MS_PIN_DECL(C21, GPIOD7, SD2WP, GPID6OUT);
+
+FUNC_GROUP_DECL(GPID6, G18, C21);
+FUNC_GROUP_DECL(SD2, F19, E21, F20, D20, D21, E20, G18, C21);
+
+#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define B20 32
@@ -177,6 +253,7 @@ SIG_EXPR_DECL(GPIE0IN, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL(GPIE0IN, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(GPIE0IN, GPIE0, GPIE);
MS_PIN_DECL(B20, GPIOE0, NCTS3, GPIE0IN);
+FUNC_GROUP_DECL(NCTS3, B20);
#define C20 33
SIG_EXPR_LIST_DECL_SINGLE(NDCD3, NDCD3, SIG_DESC_SET(SCU80, 17));
@@ -184,9 +261,227 @@ SIG_EXPR_DECL(GPIE0OUT, GPIE0, GPIE0_DESC);
SIG_EXPR_DECL(GPIE0OUT, GPIE, GPIE_DESC);
SIG_EXPR_LIST_DECL_DUAL(GPIE0OUT, GPIE0, GPIE);
MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
+FUNC_GROUP_DECL(NDCD3, C20);
FUNC_GROUP_DECL(GPIE0, B20, C20);
+#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
+
+#define F18 34
+SIG_EXPR_LIST_DECL_SINGLE(NDSR3, NDSR3, SIG_DESC_SET(SCU80, 18));
+SIG_EXPR_DECL(GPIE2IN, GPIE2, GPIE2_DESC);
+SIG_EXPR_DECL(GPIE2IN, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE2IN, GPIE2, GPIE);
+MS_PIN_DECL(F18, GPIOE2, NDSR3, GPIE2IN);
+FUNC_GROUP_DECL(NDSR3, F18);
+
+
+#define F17 35
+SIG_EXPR_LIST_DECL_SINGLE(NRI3, NRI3, SIG_DESC_SET(SCU80, 19));
+SIG_EXPR_DECL(GPIE2OUT, GPIE2, GPIE2_DESC);
+SIG_EXPR_DECL(GPIE2OUT, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE2OUT, GPIE2, GPIE);
+MS_PIN_DECL(F17, GPIOE3, NRI3, GPIE2OUT);
+FUNC_GROUP_DECL(NRI3, F17);
+
+FUNC_GROUP_DECL(GPIE2, F18, F17);
+
+#define GPIE4_DESC SIG_DESC_SET(SCU8C, 14)
+
+#define E18 36
+SIG_EXPR_LIST_DECL_SINGLE(NDTR3, NDTR3, SIG_DESC_SET(SCU80, 20));
+SIG_EXPR_DECL(GPIE4IN, GPIE4, GPIE4_DESC);
+SIG_EXPR_DECL(GPIE4IN, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE4IN, GPIE4, GPIE);
+MS_PIN_DECL(E18, GPIOE4, NDTR3, GPIE4IN);
+FUNC_GROUP_DECL(NDTR3, E18);
+
+#define D19 37
+SIG_EXPR_LIST_DECL_SINGLE(NRTS3, NRTS3, SIG_DESC_SET(SCU80, 21));
+SIG_EXPR_DECL(GPIE4OUT, GPIE4, GPIE4_DESC);
+SIG_EXPR_DECL(GPIE4OUT, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE4OUT, GPIE4, GPIE);
+MS_PIN_DECL(D19, GPIOE5, NRTS3, GPIE4OUT);
+FUNC_GROUP_DECL(NRTS3, D19);
+
+FUNC_GROUP_DECL(GPIE4, E18, D19);
+
+#define GPIE6_DESC SIG_DESC_SET(SCU8C, 15)
+
+#define A20 38
+SIG_EXPR_LIST_DECL_SINGLE(TXD3, TXD3, SIG_DESC_SET(SCU80, 22));
+SIG_EXPR_DECL(GPIE6IN, GPIE6, GPIE6_DESC);
+SIG_EXPR_DECL(GPIE6IN, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE6IN, GPIE6, GPIE);
+MS_PIN_DECL(A20, GPIOE6, TXD3, GPIE6IN);
+FUNC_GROUP_DECL(TXD3, A20);
+
+#define B19 39
+SIG_EXPR_LIST_DECL_SINGLE(RXD3, RXD3, SIG_DESC_SET(SCU80, 23));
+SIG_EXPR_DECL(GPIE6OUT, GPIE6, GPIE6_DESC);
+SIG_EXPR_DECL(GPIE6OUT, GPIE, GPIE_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPIE6OUT, GPIE6, GPIE);
+MS_PIN_DECL(B19, GPIOE7, RXD3, GPIE6OUT);
+FUNC_GROUP_DECL(RXD3, B19);
+
+FUNC_GROUP_DECL(GPIE6, A20, B19);
+
+#define LPCHC_DESC SIG_DESC_IP_SET(ASPEED_IP_LPCHC, LHCR0, 0)
+#define LPCPLUS_DESC SIG_DESC_SET(SCU90, 30)
+
+#define J19 40
+SIG_EXPR_DECL(LHAD0, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHAD0, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHAD0, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NCTS4, NCTS4, SIG_DESC_SET(SCU80, 24));
+MS_PIN_DECL(J19, GPIOF0, LHAD0, NCTS4);
+FUNC_GROUP_DECL(NCTS4, J19);
+
+#define J18 41
+SIG_EXPR_DECL(LHAD1, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHAD1, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHAD1, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NDCD4, NDCD4, SIG_DESC_SET(SCU80, 25));
+MS_PIN_DECL(J18, GPIOF1, LHAD1, NDCD4);
+FUNC_GROUP_DECL(NDCD4, J18);
+
+#define B22 42
+SIG_EXPR_DECL(LHAD2, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHAD2, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHAD2, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
+MS_PIN_DECL(B22, GPIOF2, LHAD2, NDSR4);
+FUNC_GROUP_DECL(NDSR4, B22);
+
+#define B21 43
+SIG_EXPR_DECL(LHAD3, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHAD3, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHAD3, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
+MS_PIN_DECL(B21, GPIOF3, LHAD3, NRI4);
+FUNC_GROUP_DECL(NRI4, B21);
+
+#define A21 44
+SIG_EXPR_DECL(LHCLK, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHCLK, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHCLK, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NDTR4, NDTR4, SIG_DESC_SET(SCU80, 28));
+MS_PIN_DECL(A21, GPIOF4, LHCLK, NDTR4);
+FUNC_GROUP_DECL(NDTR4, A21);
+
+#define H19 45
+SIG_EXPR_DECL(LHFRAME, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHFRAME, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHFRAME, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(NRTS4, NRTS4, SIG_DESC_SET(SCU80, 29));
+MS_PIN_DECL(H19, GPIOF5, LHFRAME, NRTS4);
+FUNC_GROUP_DECL(NRTS4, H19);
+
+#define G17 46
+SIG_EXPR_LIST_DECL_SINGLE(LHSIRQ, LPCHC, LPCHC_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TXD4, TXD4, SIG_DESC_SET(SCU80, 30));
+MS_PIN_DECL(G17, GPIOF6, LHSIRQ, TXD4);
+FUNC_GROUP_DECL(TXD4, G17);
+
+#define H18 47
+SIG_EXPR_DECL(LHRST, LPCHC, LPCHC_DESC);
+SIG_EXPR_DECL(LHRST, LPCPLUS, LPCPLUS_DESC);
+SIG_EXPR_LIST_DECL_DUAL(LHRST, LPCHC, LPCPLUS);
+SIG_EXPR_LIST_DECL_SINGLE(RXD4, RXD4, SIG_DESC_SET(SCU80, 31));
+MS_PIN_DECL(H18, GPIOF7, LHRST, RXD4);
+FUNC_GROUP_DECL(RXD4, H18);
+
+FUNC_GROUP_DECL(LPCHC, J19, J18, B22, B21, A21, H19, G17, H18);
+FUNC_GROUP_DECL(LPCPLUS, J19, J18, B22, B21, A21, H19, H18);
+
+#define A19 48
+SIG_EXPR_LIST_DECL_SINGLE(SGPS1CK, SGPS1, COND1, SIG_DESC_SET(SCU84, 0));
+SS_PIN_DECL(A19, GPIOG0, SGPS1CK);
+
+#define E19 49
+SIG_EXPR_LIST_DECL_SINGLE(SGPS1LD, SGPS1, COND1, SIG_DESC_SET(SCU84, 1));
+SS_PIN_DECL(E19, GPIOG1, SGPS1LD);
+
+#define C19 50
+SIG_EXPR_LIST_DECL_SINGLE(SGPS1I0, SGPS1, COND1, SIG_DESC_SET(SCU84, 2));
+SS_PIN_DECL(C19, GPIOG2, SGPS1I0);
+
+#define E16 51
+SIG_EXPR_LIST_DECL_SINGLE(SGPS1I1, SGPS1, COND1, SIG_DESC_SET(SCU84, 3));
+SS_PIN_DECL(E16, GPIOG3, SGPS1I1);
+
+FUNC_GROUP_DECL(SGPS1, A19, E19, C19, E16);
+
+#define SGPS2_DESC SIG_DESC_SET(SCU94, 12)
+
+#define E17 52
+SIG_EXPR_LIST_DECL_SINGLE(SGPS2CK, SGPS2, COND1, SGPS2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SALT1, SALT1, COND1, SIG_DESC_SET(SCU84, 4));
+MS_PIN_DECL(E17, GPIOG4, SGPS2CK, SALT1);
+FUNC_GROUP_DECL(SALT1, E17);
+
+#define D16 53
+SIG_EXPR_LIST_DECL_SINGLE(SGPS2LD, SGPS2, COND1, SGPS2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SALT2, SALT2, COND1, SIG_DESC_SET(SCU84, 5));
+MS_PIN_DECL(D16, GPIOG5, SGPS2LD, SALT2);
+FUNC_GROUP_DECL(SALT2, D16);
+
+#define D15 54
+SIG_EXPR_LIST_DECL_SINGLE(SGPS2I0, SGPS2, COND1, SGPS2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SALT3, SALT3, COND1, SIG_DESC_SET(SCU84, 6));
+MS_PIN_DECL(D15, GPIOG6, SGPS2I0, SALT3);
+FUNC_GROUP_DECL(SALT3, D15);
+
+#define E14 55
+SIG_EXPR_LIST_DECL_SINGLE(SGPS2I1, SGPS2, COND1, SGPS2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(SALT4, SALT4, COND1, SIG_DESC_SET(SCU84, 7));
+MS_PIN_DECL(E14, GPIOG7, SGPS2I1, SALT4);
+FUNC_GROUP_DECL(SALT4, E14);
+
+FUNC_GROUP_DECL(SGPS2, E17, D16, D15, E14);
+
+#define UART6_DESC SIG_DESC_SET(SCU90, 7)
+
+#define A18 56
+SIG_EXPR_LIST_DECL_SINGLE(DASHA18, DASHA18, COND1, SIG_DESC_SET(SCU94, 5));
+SIG_EXPR_LIST_DECL_SINGLE(NCTS6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(A18, GPIOH0, DASHA18, NCTS6);
+
+#define B18 57
+SIG_EXPR_LIST_DECL_SINGLE(DASHB18, DASHB18, COND1, SIG_DESC_SET(SCU94, 5));
+SIG_EXPR_LIST_DECL_SINGLE(NDCD6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(B18, GPIOH1, DASHB18, NDCD6);
+
+#define D17 58
+SIG_EXPR_LIST_DECL_SINGLE(DASHD17, DASHD17, COND1, SIG_DESC_SET(SCU94, 6));
+SIG_EXPR_LIST_DECL_SINGLE(NDSR6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(D17, GPIOH2, DASHD17, NDSR6);
+
+#define C17 59
+SIG_EXPR_LIST_DECL_SINGLE(DASHC17, DASHC17, COND1, SIG_DESC_SET(SCU94, 6));
+SIG_EXPR_LIST_DECL_SINGLE(NRI6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(C17, GPIOH3, DASHC17, NRI6);
+
+#define A17 60
+SIG_EXPR_LIST_DECL_SINGLE(DASHA17, DASHA17, COND1, SIG_DESC_SET(SCU94, 7));
+SIG_EXPR_LIST_DECL_SINGLE(NDTR6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(A17, GPIOH4, DASHA17, NDTR6);
+
+#define B17 61
+SIG_EXPR_LIST_DECL_SINGLE(DASHB17, DASHB17, COND1, SIG_DESC_SET(SCU94, 7));
+SIG_EXPR_LIST_DECL_SINGLE(NRTS6, UART6, COND1, UART6_DESC);
+MS_PIN_DECL(B17, GPIOH5, DASHB17, NRTS6);
+
+#define A16 62
+SIG_EXPR_LIST_DECL_SINGLE(TXD6, UART6, COND1, UART6_DESC);
+SS_PIN_DECL(A16, GPIOH6, TXD6);
+
+#define D18 63
+SIG_EXPR_LIST_DECL_SINGLE(RXD6, UART6, COND1, UART6_DESC);
+SS_PIN_DECL(D18, GPIOH7, RXD6);
+
+FUNC_GROUP_DECL(UART6, A18, B18, D17, C17, A17, B17, A16, D18);
+
#define SPI1_DESC \
{ ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
#define SPI1DEBUG_DESC \
@@ -281,6 +576,30 @@ SS_PIN_DECL(N3, GPIOJ2, SGPMO);
SIG_EXPR_LIST_DECL_SINGLE(SGPMI, SGPM, SIG_DESC_SET(SCU84, 11));
SS_PIN_DECL(N4, GPIOJ3, SGPMI);
+#define N5 76
+SIG_EXPR_LIST_DECL_SINGLE(VGAHS, VGAHS, SIG_DESC_SET(SCU84, 12));
+SIG_EXPR_LIST_DECL_SINGLE(DASHN5, DASHN5, SIG_DESC_SET(SCU94, 8));
+MS_PIN_DECL(N5, GPIOJ4, VGAHS, DASHN5);
+FUNC_GROUP_DECL(VGAHS, N5);
+
+#define R4 77
+SIG_EXPR_LIST_DECL_SINGLE(VGAVS, VGAVS, SIG_DESC_SET(SCU84, 13));
+SIG_EXPR_LIST_DECL_SINGLE(DASHR4, DASHR4, SIG_DESC_SET(SCU94, 8));
+MS_PIN_DECL(R4, GPIOJ5, VGAVS, DASHR4);
+FUNC_GROUP_DECL(VGAVS, R4);
+
+#define R3 78
+SIG_EXPR_LIST_DECL_SINGLE(DDCCLK, DDCCLK, SIG_DESC_SET(SCU84, 14));
+SIG_EXPR_LIST_DECL_SINGLE(DASHR3, DASHR3, SIG_DESC_SET(SCU94, 9));
+MS_PIN_DECL(R3, GPIOJ6, DDCCLK, DASHR3);
+FUNC_GROUP_DECL(DDCCLK, R3);
+
+#define T3 79
+SIG_EXPR_LIST_DECL_SINGLE(DDCDAT, DDCDAT, SIG_DESC_SET(SCU84, 15));
+SIG_EXPR_LIST_DECL_SINGLE(DASHT3, DASHT3, SIG_DESC_SET(SCU94, 9));
+MS_PIN_DECL(T3, GPIOJ7, DDCDAT, DASHT3);
+FUNC_GROUP_DECL(DDCDAT, T3);
+
#define I2C5_DESC SIG_DESC_SET(SCU90, 18)
#define L3 80
@@ -329,11 +648,119 @@ SS_PIN_DECL(R1, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, P2, R1);
+#define T2 88
+SSSF_PIN_DECL(T2, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
+
#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
+#define VPI_24_RSVD_DESC SIG_DESC_SET(SCU90, 5)
+#define T1 89
+#define T1_DESC SIG_DESC_SET(SCU84, 17)
+SIG_EXPR_LIST_DECL_SINGLE(VPIDE, VPI24, VPI_24_RSVD_DESC, T1_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NDCD1, NDCD1, T1_DESC, COND2);
+MS_PIN_DECL(T1, GPIOL1, VPIDE, NDCD1);
+FUNC_GROUP_DECL(NDCD1, T1);
+
+#define U1 90
+#define U1_DESC SIG_DESC_SET(SCU84, 18)
+SIG_EXPR_LIST_DECL_SINGLE(DASHU1, VPI24, VPI_24_RSVD_DESC, U1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NDSR1, NDSR1, U1_DESC);
+MS_PIN_DECL(U1, GPIOL2, DASHU1, NDSR1);
+FUNC_GROUP_DECL(NDSR1, U1);
+
+#define U2 91
+#define U2_DESC SIG_DESC_SET(SCU84, 19)
+SIG_EXPR_LIST_DECL_SINGLE(VPIHS, VPI24, VPI_24_RSVD_DESC, U2_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NRI1, NRI1, U2_DESC, COND2);
+MS_PIN_DECL(U2, GPIOL3, VPIHS, NRI1);
+FUNC_GROUP_DECL(NRI1, U2);
+
+#define P4 92
+#define P4_DESC SIG_DESC_SET(SCU84, 20)
+SIG_EXPR_LIST_DECL_SINGLE(VPIVS, VPI24, VPI_24_RSVD_DESC, P4_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NDTR1, NDTR1, P4_DESC, COND2);
+MS_PIN_DECL(P4, GPIOL4, VPIVS, NDTR1);
+FUNC_GROUP_DECL(NDTR1, P4);
+
+#define P3 93
+#define P3_DESC SIG_DESC_SET(SCU84, 21)
+SIG_EXPR_LIST_DECL_SINGLE(VPICLK, VPI24, VPI_24_RSVD_DESC, P3_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NRTS1, NRTS1, P3_DESC, COND2);
+MS_PIN_DECL(P3, GPIOL5, VPICLK, NRTS1);
+FUNC_GROUP_DECL(NRTS1, P3);
+
+#define V1 94
+#define V1_DESC SIG_DESC_SET(SCU84, 22)
+SIG_EXPR_LIST_DECL_SINGLE(DASHV1, DASHV1, VPIRSVD_DESC, V1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(TXD1, TXD1, V1_DESC, COND2);
+MS_PIN_DECL(V1, GPIOL6, DASHV1, TXD1);
+FUNC_GROUP_DECL(TXD1, V1);
+
+#define W1 95
+#define W1_DESC SIG_DESC_SET(SCU84, 23)
+SIG_EXPR_LIST_DECL_SINGLE(DASHW1, DASHW1, VPIRSVD_DESC, W1_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, W1_DESC, COND2);
+MS_PIN_DECL(W1, GPIOL7, DASHW1, RXD1);
+FUNC_GROUP_DECL(RXD1, W1);
+
+#define Y1 96
+#define Y1_DESC SIG_DESC_SET(SCU84, 24)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB2, VPI24, VPI_24_RSVD_DESC, Y1_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, Y1_DESC, COND2);
+MS_PIN_DECL(Y1, GPIOM0, VPIB2, NCTS2);
+FUNC_GROUP_DECL(NCTS2, Y1);
+
+#define AB2 97
+#define AB2_DESC SIG_DESC_SET(SCU84, 25)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB3, VPI24, VPI_24_RSVD_DESC, AB2_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, AB2_DESC, COND2);
+MS_PIN_DECL(AB2, GPIOM1, VPIB3, NDCD2);
+FUNC_GROUP_DECL(NDCD2, AB2);
+
+#define AA1 98
+#define AA1_DESC SIG_DESC_SET(SCU84, 26)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB4, VPI24, VPI_24_RSVD_DESC, AA1_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, AA1_DESC, COND2);
+MS_PIN_DECL(AA1, GPIOM2, VPIB4, NDSR2);
+FUNC_GROUP_DECL(NDSR2, AA1);
+
+#define Y2 99
+#define Y2_DESC SIG_DESC_SET(SCU84, 27)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB5, VPI24, VPI_24_RSVD_DESC, Y2_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, Y2_DESC, COND2);
+MS_PIN_DECL(Y2, GPIOM3, VPIB5, NRI2);
+FUNC_GROUP_DECL(NRI2, Y2);
+
+#define AA2 100
+#define AA2_DESC SIG_DESC_SET(SCU84, 28)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB6, VPI24, VPI_24_RSVD_DESC, AA2_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, AA2_DESC, COND2);
+MS_PIN_DECL(AA2, GPIOM4, VPIB6, NDTR2);
+FUNC_GROUP_DECL(NDTR2, AA2);
+
+#define P5 101
+#define P5_DESC SIG_DESC_SET(SCU84, 29)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB7, VPI24, VPI_24_RSVD_DESC, P5_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, P5_DESC, COND2);
+MS_PIN_DECL(P5, GPIOM5, VPIB7, NRTS2);
+FUNC_GROUP_DECL(NRTS2, P5);
+
+#define R5 102
+#define R5_DESC SIG_DESC_SET(SCU84, 30)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB8, VPI24, VPI_24_RSVD_DESC, R5_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, R5_DESC, COND2);
+MS_PIN_DECL(R5, GPIOM6, VPIB8, TXD2);
+FUNC_GROUP_DECL(TXD2, R5);
+
+#define T5 103
+#define T5_DESC SIG_DESC_SET(SCU84, 31)
+SIG_EXPR_LIST_DECL_SINGLE(VPIB9, VPI24, VPI_24_RSVD_DESC, T5_DESC, COND2);
+SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, T5_DESC, COND2);
+MS_PIN_DECL(T5, GPIOM7, VPIB9, RXD2);
+FUNC_GROUP_DECL(RXD2, T5);
#define V2 104
#define V2_DESC SIG_DESC_SET(SCU88, 0)
@@ -399,9 +826,88 @@ SIG_EXPR_LIST_DECL_SINGLE(PWM7, PWM7, T4_DESC, COND2);
MS_PIN_DECL(T4, GPION7, VPIG7, PWM7);
FUNC_GROUP_DECL(PWM7, T4);
+#define U5 112
+SIG_EXPR_LIST_DECL_SINGLE(VPIG8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 8),
+ COND2);
+SS_PIN_DECL(U5, GPIOO0, VPIG8);
+
+#define U4 113
+SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9),
+ COND2);
+SS_PIN_DECL(U4, GPIOO1, VPIG9);
+
+#define V5 114
+SIG_EXPR_LIST_DECL_SINGLE(DASHV5, DASHV5, VPI_24_RSVD_DESC,
+ SIG_DESC_SET(SCU88, 10));
+SS_PIN_DECL(V5, GPIOO2, DASHV5);
+
+#define AB4 115
+SIG_EXPR_LIST_DECL_SINGLE(DASHAB4, DASHAB4, VPI_24_RSVD_DESC,
+ SIG_DESC_SET(SCU88, 11));
+SS_PIN_DECL(AB4, GPIOO3, DASHAB4);
+
+#define AB3 116
+SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12),
+ COND2);
+SS_PIN_DECL(AB3, GPIOO4, VPIR2);
+
+#define Y4 117
+SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13),
+ COND2);
+SS_PIN_DECL(Y4, GPIOO5, VPIR3);
+
+#define AA4 118
+SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14),
+ COND2);
+SS_PIN_DECL(AA4, GPIOO6, VPIR4);
+
+#define W4 119
+SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15),
+ COND2);
+SS_PIN_DECL(W4, GPIOO7, VPIR5);
+
+#define V4 120
+SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16),
+ COND2);
+SS_PIN_DECL(V4, GPIOP0, VPIR6);
+
+#define W5 121
+SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17),
+ COND2);
+SS_PIN_DECL(W5, GPIOP1, VPIR7);
+
+#define AA5 122
+SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18),
+ COND2);
+SS_PIN_DECL(AA5, GPIOP2, VPIR8);
+
+#define AB5 123
+SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19),
+ COND2);
+SS_PIN_DECL(AB5, GPIOP3, VPIR9);
+
+FUNC_GROUP_DECL(VPI24, T1, U2, P4, P3, Y1, AB2, AA1, Y2, AA2, P5, R5, T5, V3,
+ U3, W3, AA3, Y3, T4, U5, U4, AB3, Y4, AA4, W4, V4, W5, AA5,
+ AB5);
+
+#define Y6 124
+SIG_EXPR_LIST_DECL_SINGLE(DASHY6, DASHY6, SIG_DESC_SET(SCU90, 28),
+ SIG_DESC_SET(SCU88, 20));
+SS_PIN_DECL(Y6, GPIOP4, DASHY6);
+
+#define Y5 125
+SIG_EXPR_LIST_DECL_SINGLE(DASHY5, DASHY5, SIG_DESC_SET(SCU90, 28),
+ SIG_DESC_SET(SCU88, 21));
+SS_PIN_DECL(Y5, GPIOP5, DASHY5);
+
+#define W6 126
+SIG_EXPR_LIST_DECL_SINGLE(DASHW6, DASHW6, SIG_DESC_SET(SCU90, 28),
+ SIG_DESC_SET(SCU88, 22));
+SS_PIN_DECL(W6, GPIOP6, DASHW6);
+
#define V6 127
SIG_EXPR_LIST_DECL_SINGLE(DASHV6, DASHV6, SIG_DESC_SET(SCU90, 28),
- SIG_DESC_SET(SCU88, 23));
+ SIG_DESC_SET(SCU88, 23));
SS_PIN_DECL(V6, GPIOP7, DASHV6);
#define I2C3_DESC SIG_DESC_SET(SCU90, 16)
@@ -446,6 +952,24 @@ SSSF_PIN_DECL(B10, GPIOQ6, OSCCLK, SIG_DESC_SET(SCU2C, 1));
#define N20 135
SSSF_PIN_DECL(N20, GPIOQ7, PEWAKE, SIG_DESC_SET(SCU2C, 29));
+#define AA19 136
+SSSF_PIN_DECL(AA19, GPIOR0, FWSPICS1, SIG_DESC_SET(SCU88, 24), COND2);
+
+#define T19 137
+SSSF_PIN_DECL(T19, GPIOR1, FWSPICS2, SIG_DESC_SET(SCU88, 25), COND2);
+
+#define T17 138
+SSSF_PIN_DECL(T17, GPIOR2, SPI2CS0, SIG_DESC_SET(SCU88, 26), COND2);
+
+#define Y19 139
+SSSF_PIN_DECL(Y19, GPIOR3, SPI2CK, SIG_DESC_SET(SCU88, 27), COND2);
+
+#define W19 140
+SSSF_PIN_DECL(W19, GPIOR4, SPI2MOSI, SIG_DESC_SET(SCU88, 28), COND2);
+
+#define V19 141
+SSSF_PIN_DECL(V19, GPIOR5, SPI2MISO, SIG_DESC_SET(SCU88, 29), COND2);
+
#define D8 142
SIG_EXPR_LIST_DECL_SINGLE(MDC1, MDIO1, SIG_DESC_SET(SCU88, 30));
SS_PIN_DECL(D8, GPIOR6, MDC1);
@@ -456,6 +980,93 @@ SS_PIN_DECL(E10, GPIOR7, MDIO1);
FUNC_GROUP_DECL(MDIO1, D8, E10);
+#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
+#define VPO_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
+#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
+#define VPOOFF2_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
+
+#define CRT_DVO_EN_DESC SIG_DESC_IP_SET(ASPEED_IP_GFX, GFX064, 7)
+
+#define V20 144
+#define V20_DESC SIG_DESC_SET(SCU8C, 0)
+SIG_EXPR_DECL(VPOB2, VPO, V20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB2, VPOOFF1, V20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB2, VPOOFF2, V20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO),
+ SIG_EXPR_PTR(VPOB2, VPOOFF1), SIG_EXPR_PTR(VPOB2, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SPI2CS1, SPI2CS1, V20_DESC);
+MS_PIN_DECL(V20, GPIOS0, VPOB2, SPI2CS1);
+FUNC_GROUP_DECL(SPI2CS1, V20);
+
+#define U19 145
+#define U19_DESC SIG_DESC_SET(SCU8C, 1)
+SIG_EXPR_DECL(VPOB3, VPO, U19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB3, VPOOFF1, U19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB3, VPOOFF2, U19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO),
+ SIG_EXPR_PTR(VPOB3, VPOOFF1), SIG_EXPR_PTR(VPOB3, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(BMCINT, BMCINT, U19_DESC);
+MS_PIN_DECL(U19, GPIOS1, VPOB3, BMCINT);
+FUNC_GROUP_DECL(BMCINT, U19);
+
+#define R18 146
+#define R18_DESC SIG_DESC_SET(SCU8C, 2)
+SIG_EXPR_DECL(VPOB4, VPO, R18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB4, VPOOFF1, R18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB4, VPOOFF2, R18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO),
+ SIG_EXPR_PTR(VPOB4, VPOOFF1), SIG_EXPR_PTR(VPOB4, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT5, SALT5, R18_DESC);
+MS_PIN_DECL(R18, GPIOS2, VPOB4, SALT5);
+FUNC_GROUP_DECL(SALT5, R18);
+
+#define P18 147
+#define P18_DESC SIG_DESC_SET(SCU8C, 3)
+SIG_EXPR_DECL(VPOB5, VPO, P18_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB5, VPOOFF1, P18_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB5, VPOOFF2, P18_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO),
+ SIG_EXPR_PTR(VPOB5, VPOOFF1), SIG_EXPR_PTR(VPOB5, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT6, SALT6, P18_DESC);
+MS_PIN_DECL(P18, GPIOS3, VPOB5, SALT6);
+FUNC_GROUP_DECL(SALT6, P18);
+
+#define R19 148
+#define R19_DESC SIG_DESC_SET(SCU8C, 4)
+SIG_EXPR_DECL(VPOB6, VPO, R19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB6, VPOOFF1, R19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB6, VPOOFF2, R19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO),
+ SIG_EXPR_PTR(VPOB6, VPOOFF1), SIG_EXPR_PTR(VPOB6, VPOOFF2));
+SS_PIN_DECL(R19, GPIOS4, VPOB6);
+
+#define W20 149
+#define W20_DESC SIG_DESC_SET(SCU8C, 5)
+SIG_EXPR_DECL(VPOB7, VPO, W20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB7, VPOOFF1, W20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB7, VPOOFF2, W20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO),
+ SIG_EXPR_PTR(VPOB7, VPOOFF1), SIG_EXPR_PTR(VPOB7, VPOOFF2));
+SS_PIN_DECL(W20, GPIOS5, VPOB7);
+
+#define U20 150
+#define U20_DESC SIG_DESC_SET(SCU8C, 6)
+SIG_EXPR_DECL(VPOB8, VPO, U20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB8, VPOOFF1, U20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB8, VPOOFF2, U20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB8, SIG_EXPR_PTR(VPOB8, VPO),
+ SIG_EXPR_PTR(VPOB8, VPOOFF1), SIG_EXPR_PTR(VPOB8, VPOOFF2));
+SS_PIN_DECL(U20, GPIOS6, VPOB8);
+
+#define AA20 151
+#define AA20_DESC SIG_DESC_SET(SCU8C, 7)
+SIG_EXPR_DECL(VPOB9, VPO, AA20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB9, VPOOFF1, AA20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOB9, VPOOFF2, AA20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOB9, SIG_EXPR_PTR(VPOB9, VPO),
+ SIG_EXPR_PTR(VPOB9, VPOOFF1), SIG_EXPR_PTR(VPOB9, VPOOFF2));
+SS_PIN_DECL(AA20, GPIOS7, VPOB9);
+
/* RGMII1/RMII1 */
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
@@ -637,6 +1248,481 @@ MS_PIN_DECL_(E6, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
FUNC_GROUP_DECL(RGMII2, B2, B1, A2, B3, D5, D4, C2, C1, C3, D1, D2, E6);
FUNC_GROUP_DECL(RMII2, B2, B1, A2, B3, C2, C3, D1, D2, E6);
+#define F4 176
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
+SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
+MS_PIN_DECL_(F4, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
+FUNC_GROUP_DECL(ADC0, F4);
+
+#define F5 177
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
+SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
+MS_PIN_DECL_(F5, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
+FUNC_GROUP_DECL(ADC1, F5);
+
+#define E2 178
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
+SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
+MS_PIN_DECL_(E2, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
+FUNC_GROUP_DECL(ADC2, E2);
+
+#define E1 179
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
+SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
+MS_PIN_DECL_(E1, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
+FUNC_GROUP_DECL(ADC3, E1);
+
+#define F3 180
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
+SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
+MS_PIN_DECL_(F3, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
+FUNC_GROUP_DECL(ADC4, F3);
+
+#define E3 181
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
+SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
+MS_PIN_DECL_(E3, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
+FUNC_GROUP_DECL(ADC5, E3);
+
+#define G5 182
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
+SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
+MS_PIN_DECL_(G5, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
+FUNC_GROUP_DECL(ADC6, G5);
+
+#define G4 183
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
+SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
+MS_PIN_DECL_(G4, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
+FUNC_GROUP_DECL(ADC7, G4);
+
+#define F2 184
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
+SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
+MS_PIN_DECL_(F2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
+FUNC_GROUP_DECL(ADC8, F2);
+
+#define G3 185
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
+SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
+MS_PIN_DECL_(G3, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
+FUNC_GROUP_DECL(ADC9, G3);
+
+#define G2 186
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
+SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
+MS_PIN_DECL_(G2, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
+FUNC_GROUP_DECL(ADC10, G2);
+
+#define F1 187
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
+SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
+MS_PIN_DECL_(F1, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
+FUNC_GROUP_DECL(ADC11, F1);
+
+#define H5 188
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
+SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
+MS_PIN_DECL_(H5, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
+FUNC_GROUP_DECL(ADC12, H5);
+
+#define G1 189
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
+SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
+MS_PIN_DECL_(G1, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
+FUNC_GROUP_DECL(ADC13, G1);
+
+#define H3 190
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
+SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
+MS_PIN_DECL_(H3, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
+FUNC_GROUP_DECL(ADC14, H3);
+
+#define H4 191
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
+SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
+MS_PIN_DECL_(H4, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
+FUNC_GROUP_DECL(ADC15, H4);
+
+#define ACPI_DESC SIG_DESC_SET(HW_STRAP1, 19)
+
+#define R22 192
+SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
+SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(DASHR22, DASHR22, SIG_DESC_SET(SCU94, 10));
+MS_PIN_DECL(R22, GPIOY0, SIOS3, DASHR22);
+FUNC_GROUP_DECL(SIOS3, R22);
+
+#define R21 193
+SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
+SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(DASHR21, DASHR21, SIG_DESC_SET(SCU94, 10));
+MS_PIN_DECL(R21, GPIOY1, SIOS5, DASHR21);
+FUNC_GROUP_DECL(SIOS5, R21);
+
+#define P22 194
+SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
+SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(DASHP22, DASHP22, SIG_DESC_SET(SCU94, 11));
+MS_PIN_DECL(P22, GPIOY2, SIOPWREQ, DASHP22);
+FUNC_GROUP_DECL(SIOPWREQ, P22);
+
+#define P21 195
+SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
+SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(DASHP21, DASHP21, SIG_DESC_SET(SCU94, 11));
+MS_PIN_DECL(P21, GPIOY3, SIOONCTRL, DASHP21);
+FUNC_GROUP_DECL(SIOONCTRL, P21);
+
+#define M18 196
+SSSF_PIN_DECL(M18, GPIOY4, SCL1, SIG_DESC_SET(SCUA4, 12));
+
+#define M19 197
+SSSF_PIN_DECL(M19, GPIOY5, SDA1, SIG_DESC_SET(SCUA4, 13));
+
+#define M20 198
+SSSF_PIN_DECL(M20, GPIOY6, SCL2, SIG_DESC_SET(SCUA4, 14));
+
+#define P20 199
+SSSF_PIN_DECL(P20, GPIOY7, SDA2, SIG_DESC_SET(SCUA4, 15));
+
+#define PNOR_DESC SIG_DESC_SET(SCU90, 31)
+
+#define Y20 200
+#define Y20_DESC SIG_DESC_SET(SCUA4, 16)
+SIG_EXPR_DECL(VPOG2, VPO, Y20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG2, VPOOFF1, Y20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG2, VPOOFF2, Y20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO),
+ SIG_EXPR_PTR(VPOG2, VPOOFF1), SIG_EXPR_PTR(VPOG2, VPOOFF2));
+SIG_EXPR_DECL(SIOPBI, SIOPBI, Y20_DESC);
+SIG_EXPR_DECL(SIOPBI, ACPI, Y20_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPBI, SIOPBI, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(NORA0, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOZ0, GPIOZ0);
+MS_PIN_DECL_(Y20, SIG_EXPR_LIST_PTR(VPOG2), SIG_EXPR_LIST_PTR(SIOPBI),
+ SIG_EXPR_LIST_PTR(NORA0), SIG_EXPR_LIST_PTR(GPIOZ0));
+FUNC_GROUP_DECL(SIOPBI, Y20);
+
+#define AB20 201
+#define AB20_DESC SIG_DESC_SET(SCUA4, 17)
+SIG_EXPR_DECL(VPOG3, VPO, AB20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG3, VPOOFF1, AB20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG3, VPOOFF2, AB20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO),
+ SIG_EXPR_PTR(VPOG3, VPOOFF1), SIG_EXPR_PTR(VPOG3, VPOOFF2));
+SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, AB20_DESC);
+SIG_EXPR_DECL(SIOPWRGD, ACPI, AB20_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(NORA1, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOZ1, GPIOZ1);
+MS_PIN_DECL_(AB20, SIG_EXPR_LIST_PTR(VPOG3), SIG_EXPR_LIST_PTR(SIOPWRGD),
+ SIG_EXPR_LIST_PTR(NORA1), SIG_EXPR_LIST_PTR(GPIOZ1));
+FUNC_GROUP_DECL(SIOPWRGD, AB20);
+
+#define AB21 202
+#define AB21_DESC SIG_DESC_SET(SCUA4, 18)
+SIG_EXPR_DECL(VPOG4, VPO, AB21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG4, VPOOFF1, AB21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG4, VPOOFF2, AB21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOG4, SIG_EXPR_PTR(VPOG4, VPO),
+ SIG_EXPR_PTR(VPOG4, VPOOFF1), SIG_EXPR_PTR(VPOG4, VPOOFF2));
+SIG_EXPR_DECL(SIOPBO, SIOPBO, AB21_DESC);
+SIG_EXPR_DECL(SIOPBO, ACPI, AB21_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPBO, SIOPBO, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(NORA2, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOZ2, GPIOZ2);
+MS_PIN_DECL_(AB21, SIG_EXPR_LIST_PTR(VPOG4), SIG_EXPR_LIST_PTR(SIOPBO),
+ SIG_EXPR_LIST_PTR(NORA2), SIG_EXPR_LIST_PTR(GPIOZ2));
+FUNC_GROUP_DECL(SIOPBO, AB21);
+
+#define AA21 203
+#define AA21_DESC SIG_DESC_SET(SCUA4, 19)
+SIG_EXPR_DECL(VPOG5, VPO, AA21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG5, VPOOFF1, AA21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOG5, VPOOFF2, AA21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOG5, SIG_EXPR_PTR(VPOG5, VPO),
+ SIG_EXPR_PTR(VPOG5, VPOOFF1), SIG_EXPR_PTR(VPOG5, VPOOFF2));
+SIG_EXPR_DECL(SIOSCI, SIOSCI, AA21_DESC);
+SIG_EXPR_DECL(SIOSCI, ACPI, AA21_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
+SIG_EXPR_LIST_DECL_SINGLE(NORA3, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOZ3, GPIOZ3);
+MS_PIN_DECL_(AA21, SIG_EXPR_LIST_PTR(VPOG5), SIG_EXPR_LIST_PTR(SIOSCI),
+ SIG_EXPR_LIST_PTR(NORA3), SIG_EXPR_LIST_PTR(GPIOZ3));
+FUNC_GROUP_DECL(SIOSCI, AA21);
+
+FUNC_GROUP_DECL(ACPI, R22, R21, P22, P21, Y20, AB20, AB21, AA21);
+
+/* CRT DVO disabled, configured for single-edge mode */
+#define CRT_DVO_DS_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 0, 0 }
+
+/* CRT DVO disabled, configured for dual-edge mode */
+#define CRT_DVO_DD_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 1, 1 }
+
+/* CRT DVO enabled, configured for single-edge mode */
+#define CRT_DVO_ES_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 2, 2 }
+
+/* CRT DVO enabled, configured for dual-edge mode */
+#define CRT_DVO_ED_DESC { ASPEED_IP_GFX, GFX064, GENMASK(7, 6), 3, 3 }
+
+#define U21 204
+#define U21_DESC SIG_DESC_SET(SCUA4, 20)
+SIG_EXPR_DECL(VPOG6, VPO, U21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG6, VPOOFF1, U21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG6, VPOOFF2, U21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOG6, SIG_EXPR_PTR(VPOG6, VPO),
+ SIG_EXPR_PTR(VPOG6, VPOOFF1), SIG_EXPR_PTR(VPOG6, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NORA4, PNOR, PNOR_DESC);
+MS_PIN_DECL(U21, GPIOZ4, VPOG6, NORA4);
+
+#define W22 205
+#define W22_DESC SIG_DESC_SET(SCUA4, 21)
+SIG_EXPR_DECL(VPOG7, VPO, W22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG7, VPOOFF1, W22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG7, VPOOFF2, W22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOG7, SIG_EXPR_PTR(VPOG7, VPO),
+ SIG_EXPR_PTR(VPOG7, VPOOFF1), SIG_EXPR_PTR(VPOG7, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NORA5, PNOR, PNOR_DESC);
+MS_PIN_DECL(W22, GPIOZ5, VPOG7, NORA5);
+
+#define V22 206
+#define V22_DESC SIG_DESC_SET(SCUA4, 22)
+SIG_EXPR_DECL(VPOG8, VPO, V22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG8, VPOOFF1, V22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG8, VPOOFF2, V22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOG8, SIG_EXPR_PTR(VPOG8, VPO),
+ SIG_EXPR_PTR(VPOG8, VPOOFF1), SIG_EXPR_PTR(VPOG8, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NORA6, PNOR, PNOR_DESC);
+MS_PIN_DECL(V22, GPIOZ6, VPOG8, NORA6);
+
+#define W21 207
+#define W21_DESC SIG_DESC_SET(SCUA4, 23)
+SIG_EXPR_DECL(VPOG9, VPO, W21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG9, VPOOFF1, W21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOG9, VPOOFF2, W21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOG9, SIG_EXPR_PTR(VPOG9, VPO),
+ SIG_EXPR_PTR(VPOG9, VPOOFF1), SIG_EXPR_PTR(VPOG9, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NORA7, PNOR, PNOR_DESC);
+MS_PIN_DECL(W21, GPIOZ7, VPOG9, NORA7);
+
+#define Y21 208
+#define Y21_DESC SIG_DESC_SET(SCUA4, 24)
+SIG_EXPR_DECL(VPOR2, VPO, Y21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR2, VPOOFF1, Y21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR2, VPOOFF2, Y21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR2, SIG_EXPR_PTR(VPOR2, VPO),
+ SIG_EXPR_PTR(VPOR2, VPOOFF1), SIG_EXPR_PTR(VPOR2, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT7, SALT7, Y21_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD0, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA0, GPIOAA0);
+MS_PIN_DECL_(Y21, SIG_EXPR_LIST_PTR(VPOR2), SIG_EXPR_LIST_PTR(SALT7),
+ SIG_EXPR_LIST_PTR(NORD0), SIG_EXPR_LIST_PTR(GPIOAA0));
+FUNC_GROUP_DECL(SALT7, Y21);
+
+#define V21 209
+#define V21_DESC SIG_DESC_SET(SCUA4, 25)
+SIG_EXPR_DECL(VPOR3, VPO, V21_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR3, VPOOFF1, V21_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR3, VPOOFF2, V21_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR3, SIG_EXPR_PTR(VPOR3, VPO),
+ SIG_EXPR_PTR(VPOR3, VPOOFF1), SIG_EXPR_PTR(VPOR3, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT8, SALT8, V21_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD1, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA1, GPIOAA1);
+MS_PIN_DECL_(V21, SIG_EXPR_LIST_PTR(VPOR3), SIG_EXPR_LIST_PTR(SALT8),
+ SIG_EXPR_LIST_PTR(NORD1), SIG_EXPR_LIST_PTR(GPIOAA1));
+FUNC_GROUP_DECL(SALT8, V21);
+
+#define Y22 210
+#define Y22_DESC SIG_DESC_SET(SCUA4, 26)
+SIG_EXPR_DECL(VPOR4, VPO, Y22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR4, VPOOFF1, Y22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR4, VPOOFF2, Y22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR4, SIG_EXPR_PTR(VPOR4, VPO),
+ SIG_EXPR_PTR(VPOR4, VPOOFF1), SIG_EXPR_PTR(VPOR4, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT9, SALT9, Y22_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD2, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA2, GPIOAA2);
+MS_PIN_DECL_(Y22, SIG_EXPR_LIST_PTR(VPOR4), SIG_EXPR_LIST_PTR(SALT9),
+ SIG_EXPR_LIST_PTR(NORD2), SIG_EXPR_LIST_PTR(GPIOAA2));
+FUNC_GROUP_DECL(SALT9, Y22);
+
+#define AA22 211
+#define AA22_DESC SIG_DESC_SET(SCUA4, 27)
+SIG_EXPR_DECL(VPOR5, VPO, AA22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR5, VPOOFF1, AA22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR5, VPOOFF2, AA22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR5, SIG_EXPR_PTR(VPOR5, VPO),
+ SIG_EXPR_PTR(VPOR5, VPOOFF1), SIG_EXPR_PTR(VPOR5, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT10, SALT10, AA22_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD3, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA3, GPIOAA3);
+MS_PIN_DECL_(AA22, SIG_EXPR_LIST_PTR(VPOR5), SIG_EXPR_LIST_PTR(SALT10),
+ SIG_EXPR_LIST_PTR(NORD3), SIG_EXPR_LIST_PTR(GPIOAA3));
+FUNC_GROUP_DECL(SALT10, AA22);
+
+#define U22 212
+#define U22_DESC SIG_DESC_SET(SCUA4, 28)
+SIG_EXPR_DECL(VPOR6, VPO, U22_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR6, VPOOFF1, U22_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR6, VPOOFF2, U22_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR6, SIG_EXPR_PTR(VPOR6, VPO),
+ SIG_EXPR_PTR(VPOR6, VPOOFF1), SIG_EXPR_PTR(VPOR6, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT11, SALT11, U22_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD4, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA4, GPIOAA4);
+MS_PIN_DECL_(U22, SIG_EXPR_LIST_PTR(VPOR6), SIG_EXPR_LIST_PTR(SALT11),
+ SIG_EXPR_LIST_PTR(NORD4), SIG_EXPR_LIST_PTR(GPIOAA4));
+FUNC_GROUP_DECL(SALT11, U22);
+
+#define T20 213
+#define T20_DESC SIG_DESC_SET(SCUA4, 29)
+SIG_EXPR_DECL(VPOR7, VPO, T20_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR7, VPOOFF1, T20_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR7, VPOOFF2, T20_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR7, SIG_EXPR_PTR(VPOR7, VPO),
+ SIG_EXPR_PTR(VPOR7, VPOOFF1), SIG_EXPR_PTR(VPOR7, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT12, SALT12, T20_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD5, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA5, GPIOAA5);
+MS_PIN_DECL_(T20, SIG_EXPR_LIST_PTR(VPOR7), SIG_EXPR_LIST_PTR(SALT12),
+ SIG_EXPR_LIST_PTR(NORD5), SIG_EXPR_LIST_PTR(GPIOAA5));
+FUNC_GROUP_DECL(SALT12, T20);
+
+#define N18 214
+#define N18_DESC SIG_DESC_SET(SCUA4, 30)
+SIG_EXPR_DECL(VPOR8, VPO, N18_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR8, VPOOFF1, N18_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR8, VPOOFF2, N18_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR8, SIG_EXPR_PTR(VPOR8, VPO),
+ SIG_EXPR_PTR(VPOR8, VPOOFF1), SIG_EXPR_PTR(VPOR8, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT13, SALT13, N18_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD6, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA6, GPIOAA6);
+MS_PIN_DECL_(N18, SIG_EXPR_LIST_PTR(VPOR8), SIG_EXPR_LIST_PTR(SALT13),
+ SIG_EXPR_LIST_PTR(NORD6), SIG_EXPR_LIST_PTR(GPIOAA6));
+FUNC_GROUP_DECL(SALT13, N18);
+
+#define P19 215
+#define P19_DESC SIG_DESC_SET(SCUA4, 31)
+SIG_EXPR_DECL(VPOR9, VPO, P19_DESC, VPO_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR9, VPOOFF1, P19_DESC, VPOOFF1_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_DECL(VPOR9, VPOOFF2, P19_DESC, VPOOFF2_DESC, CRT_DVO_ES_DESC);
+SIG_EXPR_LIST_DECL(VPOR9, SIG_EXPR_PTR(VPOR9, VPO),
+ SIG_EXPR_PTR(VPOR9, VPOOFF1), SIG_EXPR_PTR(VPOR9, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(SALT14, SALT14, P19_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(NORD7, PNOR, PNOR_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(GPIOAA7, GPIOAA7);
+MS_PIN_DECL_(P19, SIG_EXPR_LIST_PTR(VPOR9), SIG_EXPR_LIST_PTR(SALT14),
+ SIG_EXPR_LIST_PTR(NORD7), SIG_EXPR_LIST_PTR(GPIOAA7));
+FUNC_GROUP_DECL(SALT14, P19);
+
+#define N19 216
+#define N19_DESC SIG_DESC_SET(SCUA8, 0)
+SIG_EXPR_DECL(VPODE, VPO, N19_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPODE, VPOOFF1, N19_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPODE, VPOOFF2, N19_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPODE, SIG_EXPR_PTR(VPODE, VPO),
+ SIG_EXPR_PTR(VPODE, VPOOFF1), SIG_EXPR_PTR(VPODE, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NOROE, PNOR, PNOR_DESC);
+MS_PIN_DECL(N19, GPIOAB0, VPODE, NOROE);
+
+#define T21 217
+#define T21_DESC SIG_DESC_SET(SCUA8, 1)
+SIG_EXPR_DECL(VPOHS, VPO, T21_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOHS, VPOOFF1, T21_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOHS, VPOOFF2, T21_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOHS, SIG_EXPR_PTR(VPOHS, VPO),
+ SIG_EXPR_PTR(VPOHS, VPOOFF1), SIG_EXPR_PTR(VPOHS, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(NORWE, PNOR, PNOR_DESC);
+MS_PIN_DECL(T21, GPIOAB1, VPOHS, NORWE);
+
+FUNC_GROUP_DECL(PNOR, Y20, AB20, AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22,
+ AA22, U22, T20, N18, P19, N19, T21);
+
+#define T22 218
+#define T22_DESC SIG_DESC_SET(SCUA8, 2)
+SIG_EXPR_DECL(VPOVS, VPO, T22_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOVS, VPOOFF1, T22_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOVS, VPOOFF2, T22_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOVS, SIG_EXPR_PTR(VPOVS, VPO),
+ SIG_EXPR_PTR(VPOVS, VPOOFF1), SIG_EXPR_PTR(VPOVS, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, T22_DESC);
+MS_PIN_DECL(T22, GPIOAB2, VPOVS, WDTRST1);
+FUNC_GROUP_DECL(WDTRST1, T22);
+
+#define R20 219
+#define R20_DESC SIG_DESC_SET(SCUA8, 3)
+SIG_EXPR_DECL(VPOCLK, VPO, R20_DESC, VPO_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOCLK, VPOOFF1, R20_DESC, VPOOFF1_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_DECL(VPOCLK, VPOOFF2, R20_DESC, VPOOFF2_DESC, CRT_DVO_EN_DESC);
+SIG_EXPR_LIST_DECL(VPOCLK, SIG_EXPR_PTR(VPOCLK, VPO),
+ SIG_EXPR_PTR(VPOCLK, VPOOFF1), SIG_EXPR_PTR(VPOCLK, VPOOFF2));
+SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, R20_DESC);
+MS_PIN_DECL(R20, GPIOAB3, VPOCLK, WDTRST2);
+FUNC_GROUP_DECL(WDTRST2, R20);
+
+FUNC_GROUP_DECL(VPO, V20, U19, R18, P18, R19, W20, U20, AA20, Y20, AB20,
+ AB21, AA21, U21, W22, V22, W21, Y21, V21, Y22, AA22, U22, T20,
+ N18, P19, N19, T21, T22, R20);
+
+#define ESPI_DESC SIG_DESC_SET(HW_STRAP1, 25)
+
+#define G21 224
+SIG_EXPR_LIST_DECL_SINGLE(ESPID0, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LAD0, LAD0, SIG_DESC_SET(SCUAC, 0));
+MS_PIN_DECL(G21, GPIOAC0, ESPID0, LAD0);
+FUNC_GROUP_DECL(LAD0, G21);
+
+#define G20 225
+SIG_EXPR_LIST_DECL_SINGLE(ESPID1, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LAD1, LAD1, SIG_DESC_SET(SCUAC, 1));
+MS_PIN_DECL(G20, GPIOAC1, ESPID1, LAD1);
+FUNC_GROUP_DECL(LAD1, G20);
+
+#define D22 226
+SIG_EXPR_LIST_DECL_SINGLE(ESPID2, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LAD2, LAD2, SIG_DESC_SET(SCUAC, 2));
+MS_PIN_DECL(D22, GPIOAC2, ESPID2, LAD2);
+FUNC_GROUP_DECL(LAD2, D22);
+
+#define E22 227
+SIG_EXPR_LIST_DECL_SINGLE(ESPID3, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LAD3, LAD3, SIG_DESC_SET(SCUAC, 3));
+MS_PIN_DECL(E22, GPIOAC3, ESPID3, LAD3);
+FUNC_GROUP_DECL(LAD3, E22);
+
+#define C22 228
+SIG_EXPR_LIST_DECL_SINGLE(ESPICK, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LCLK, LCLK, SIG_DESC_SET(SCUAC, 4));
+MS_PIN_DECL(C22, GPIOAC4, ESPICK, LCLK);
+FUNC_GROUP_DECL(LCLK, C22);
+
+#define F21 229
+SIG_EXPR_LIST_DECL_SINGLE(ESPICS, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LFRAME, LFRAME, SIG_DESC_SET(SCUAC, 5));
+MS_PIN_DECL(F21, GPIOAC5, ESPICS, LFRAME);
+FUNC_GROUP_DECL(LFRAME, F21);
+
+#define F22 230
+SIG_EXPR_LIST_DECL_SINGLE(ESPIALT, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LSIRQ, LSIRQ, SIG_DESC_SET(SCUAC, 6));
+MS_PIN_DECL(F22, GPIOAC6, ESPIALT, LSIRQ);
+FUNC_GROUP_DECL(LSIRQ, F22);
+
+#define G22 231
+SIG_EXPR_LIST_DECL_SINGLE(ESPIRST, ESPI, ESPI_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(LPCRST, LPCRST, SIG_DESC_SET(SCUAC, 7));
+MS_PIN_DECL(G22, GPIOAC7, ESPIRST, LPCRST);
+FUNC_GROUP_DECL(LPCRST, G22);
+
+FUNC_GROUP_DECL(ESPI, G21, G20, D22, E22, C22, F21, F22, G22);
+
/* Pins, groups and functions are sort(1):ed alphabetically for sanity */
static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
@@ -646,12 +1732,32 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(A13),
ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
+ ASPEED_PINCTRL_PIN(A16),
+ ASPEED_PINCTRL_PIN(A17),
+ ASPEED_PINCTRL_PIN(A18),
+ ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
+ ASPEED_PINCTRL_PIN(A20),
+ ASPEED_PINCTRL_PIN(A21),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A9),
+ ASPEED_PINCTRL_PIN(AA1),
+ ASPEED_PINCTRL_PIN(AA19),
+ ASPEED_PINCTRL_PIN(AA2),
+ ASPEED_PINCTRL_PIN(AA20),
+ ASPEED_PINCTRL_PIN(AA21),
+ ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
+ ASPEED_PINCTRL_PIN(AA4),
+ ASPEED_PINCTRL_PIN(AA5),
+ ASPEED_PINCTRL_PIN(AB2),
+ ASPEED_PINCTRL_PIN(AB20),
+ ASPEED_PINCTRL_PIN(AB21),
+ ASPEED_PINCTRL_PIN(AB3),
+ ASPEED_PINCTRL_PIN(AB4),
+ ASPEED_PINCTRL_PIN(AB5),
ASPEED_PINCTRL_PIN(B1),
ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
@@ -660,8 +1766,13 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
ASPEED_PINCTRL_PIN(B16),
+ ASPEED_PINCTRL_PIN(B17),
+ ASPEED_PINCTRL_PIN(B18),
+ ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
ASPEED_PINCTRL_PIN(B20),
+ ASPEED_PINCTRL_PIN(B21),
+ ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
ASPEED_PINCTRL_PIN(B5),
@@ -673,62 +1784,210 @@ static struct pinctrl_pin_desc aspeed_g5_pins[ASPEED_G5_NR_PINS] = {
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
ASPEED_PINCTRL_PIN(C16),
+ ASPEED_PINCTRL_PIN(C17),
ASPEED_PINCTRL_PIN(C18),
+ ASPEED_PINCTRL_PIN(C19),
ASPEED_PINCTRL_PIN(C2),
ASPEED_PINCTRL_PIN(C20),
+ ASPEED_PINCTRL_PIN(C21),
+ ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(D1),
ASPEED_PINCTRL_PIN(D10),
+ ASPEED_PINCTRL_PIN(D13),
+ ASPEED_PINCTRL_PIN(D14),
+ ASPEED_PINCTRL_PIN(D15),
+ ASPEED_PINCTRL_PIN(D16),
+ ASPEED_PINCTRL_PIN(D17),
+ ASPEED_PINCTRL_PIN(D18),
+ ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D20),
+ ASPEED_PINCTRL_PIN(D21),
+ ASPEED_PINCTRL_PIN(D22),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
ASPEED_PINCTRL_PIN(D8),
ASPEED_PINCTRL_PIN(D9),
+ ASPEED_PINCTRL_PIN(E1),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E12),
ASPEED_PINCTRL_PIN(E13),
+ ASPEED_PINCTRL_PIN(E14),
ASPEED_PINCTRL_PIN(E15),
+ ASPEED_PINCTRL_PIN(E16),
+ ASPEED_PINCTRL_PIN(E17),
+ ASPEED_PINCTRL_PIN(E18),
+ ASPEED_PINCTRL_PIN(E19),
+ ASPEED_PINCTRL_PIN(E2),
+ ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E21),
+ ASPEED_PINCTRL_PIN(E22),
+ ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
ASPEED_PINCTRL_PIN(E9),
+ ASPEED_PINCTRL_PIN(F1),
+ ASPEED_PINCTRL_PIN(F17),
+ ASPEED_PINCTRL_PIN(F18),
ASPEED_PINCTRL_PIN(F19),
+ ASPEED_PINCTRL_PIN(F2),
ASPEED_PINCTRL_PIN(F20),
+ ASPEED_PINCTRL_PIN(F21),
+ ASPEED_PINCTRL_PIN(F22),
+ ASPEED_PINCTRL_PIN(F3),
+ ASPEED_PINCTRL_PIN(F4),
+ ASPEED_PINCTRL_PIN(F5),
ASPEED_PINCTRL_PIN(F9),
+ ASPEED_PINCTRL_PIN(G1),
+ ASPEED_PINCTRL_PIN(G17),
+ ASPEED_PINCTRL_PIN(G18),
+ ASPEED_PINCTRL_PIN(G2),
+ ASPEED_PINCTRL_PIN(G20),
+ ASPEED_PINCTRL_PIN(G21),
+ ASPEED_PINCTRL_PIN(G22),
+ ASPEED_PINCTRL_PIN(G3),
+ ASPEED_PINCTRL_PIN(G4),
+ ASPEED_PINCTRL_PIN(G5),
+ ASPEED_PINCTRL_PIN(H18),
+ ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H20),
+ ASPEED_PINCTRL_PIN(H21),
+ ASPEED_PINCTRL_PIN(H22),
+ ASPEED_PINCTRL_PIN(H3),
+ ASPEED_PINCTRL_PIN(H4),
+ ASPEED_PINCTRL_PIN(H5),
+ ASPEED_PINCTRL_PIN(J18),
+ ASPEED_PINCTRL_PIN(J19),
+ ASPEED_PINCTRL_PIN(J20),
+ ASPEED_PINCTRL_PIN(K18),
+ ASPEED_PINCTRL_PIN(K19),
ASPEED_PINCTRL_PIN(L1),
+ ASPEED_PINCTRL_PIN(L18),
+ ASPEED_PINCTRL_PIN(L19),
ASPEED_PINCTRL_PIN(L2),
ASPEED_PINCTRL_PIN(L3),
ASPEED_PINCTRL_PIN(L4),
+ ASPEED_PINCTRL_PIN(M18),
+ ASPEED_PINCTRL_PIN(M19),
+ ASPEED_PINCTRL_PIN(M20),
ASPEED_PINCTRL_PIN(N1),
+ ASPEED_PINCTRL_PIN(N18),
+ ASPEED_PINCTRL_PIN(N19),
ASPEED_PINCTRL_PIN(N2),
ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
ASPEED_PINCTRL_PIN(N22),
ASPEED_PINCTRL_PIN(N3),
ASPEED_PINCTRL_PIN(N4),
+ ASPEED_PINCTRL_PIN(N5),
ASPEED_PINCTRL_PIN(P1),
+ ASPEED_PINCTRL_PIN(P18),
+ ASPEED_PINCTRL_PIN(P19),
ASPEED_PINCTRL_PIN(P2),
+ ASPEED_PINCTRL_PIN(P20),
+ ASPEED_PINCTRL_PIN(P21),
+ ASPEED_PINCTRL_PIN(P22),
+ ASPEED_PINCTRL_PIN(P3),
+ ASPEED_PINCTRL_PIN(P4),
+ ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R1),
+ ASPEED_PINCTRL_PIN(R18),
+ ASPEED_PINCTRL_PIN(R19),
+ ASPEED_PINCTRL_PIN(R2),
+ ASPEED_PINCTRL_PIN(R20),
+ ASPEED_PINCTRL_PIN(R21),
+ ASPEED_PINCTRL_PIN(R22),
+ ASPEED_PINCTRL_PIN(R3),
+ ASPEED_PINCTRL_PIN(R4),
+ ASPEED_PINCTRL_PIN(R5),
+ ASPEED_PINCTRL_PIN(T1),
+ ASPEED_PINCTRL_PIN(T17),
+ ASPEED_PINCTRL_PIN(T19),
+ ASPEED_PINCTRL_PIN(T2),
+ ASPEED_PINCTRL_PIN(T20),
+ ASPEED_PINCTRL_PIN(T21),
+ ASPEED_PINCTRL_PIN(T22),
+ ASPEED_PINCTRL_PIN(T3),
ASPEED_PINCTRL_PIN(T4),
+ ASPEED_PINCTRL_PIN(T5),
+ ASPEED_PINCTRL_PIN(U1),
+ ASPEED_PINCTRL_PIN(U19),
+ ASPEED_PINCTRL_PIN(U2),
+ ASPEED_PINCTRL_PIN(U20),
+ ASPEED_PINCTRL_PIN(U21),
+ ASPEED_PINCTRL_PIN(U22),
ASPEED_PINCTRL_PIN(U3),
+ ASPEED_PINCTRL_PIN(U4),
+ ASPEED_PINCTRL_PIN(U5),
+ ASPEED_PINCTRL_PIN(V1),
+ ASPEED_PINCTRL_PIN(V19),
ASPEED_PINCTRL_PIN(V2),
+ ASPEED_PINCTRL_PIN(V20),
+ ASPEED_PINCTRL_PIN(V21),
+ ASPEED_PINCTRL_PIN(V22),
ASPEED_PINCTRL_PIN(V3),
+ ASPEED_PINCTRL_PIN(V4),
+ ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
+ ASPEED_PINCTRL_PIN(W1),
+ ASPEED_PINCTRL_PIN(W19),
ASPEED_PINCTRL_PIN(W2),
+ ASPEED_PINCTRL_PIN(W20),
+ ASPEED_PINCTRL_PIN(W21),
+ ASPEED_PINCTRL_PIN(W22),
ASPEED_PINCTRL_PIN(W3),
+ ASPEED_PINCTRL_PIN(W4),
+ ASPEED_PINCTRL_PIN(W5),
+ ASPEED_PINCTRL_PIN(W6),
+ ASPEED_PINCTRL_PIN(Y1),
+ ASPEED_PINCTRL_PIN(Y19),
+ ASPEED_PINCTRL_PIN(Y2),
+ ASPEED_PINCTRL_PIN(Y20),
+ ASPEED_PINCTRL_PIN(Y21),
+ ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
+ ASPEED_PINCTRL_PIN(Y4),
+ ASPEED_PINCTRL_PIN(Y5),
+ ASPEED_PINCTRL_PIN(Y6),
};
static const struct aspeed_pin_group aspeed_g5_groups[] = {
+ ASPEED_PINCTRL_GROUP(ACPI),
+ ASPEED_PINCTRL_GROUP(ADC0),
+ ASPEED_PINCTRL_GROUP(ADC1),
+ ASPEED_PINCTRL_GROUP(ADC10),
+ ASPEED_PINCTRL_GROUP(ADC11),
+ ASPEED_PINCTRL_GROUP(ADC12),
+ ASPEED_PINCTRL_GROUP(ADC13),
+ ASPEED_PINCTRL_GROUP(ADC14),
+ ASPEED_PINCTRL_GROUP(ADC15),
+ ASPEED_PINCTRL_GROUP(ADC2),
+ ASPEED_PINCTRL_GROUP(ADC3),
+ ASPEED_PINCTRL_GROUP(ADC4),
+ ASPEED_PINCTRL_GROUP(ADC5),
+ ASPEED_PINCTRL_GROUP(ADC6),
+ ASPEED_PINCTRL_GROUP(ADC7),
+ ASPEED_PINCTRL_GROUP(ADC8),
+ ASPEED_PINCTRL_GROUP(ADC9),
+ ASPEED_PINCTRL_GROUP(BMCINT),
+ ASPEED_PINCTRL_GROUP(DDCCLK),
+ ASPEED_PINCTRL_GROUP(DDCDAT),
+ ASPEED_PINCTRL_GROUP(ESPI),
+ ASPEED_PINCTRL_GROUP(FWSPICS1),
+ ASPEED_PINCTRL_GROUP(FWSPICS2),
ASPEED_PINCTRL_GROUP(GPID0),
ASPEED_PINCTRL_GROUP(GPID2),
+ ASPEED_PINCTRL_GROUP(GPID4),
+ ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
+ ASPEED_PINCTRL_GROUP(GPIE2),
+ ASPEED_PINCTRL_GROUP(GPIE4),
+ ASPEED_PINCTRL_GROUP(GPIE6),
ASPEED_PINCTRL_GROUP(I2C10),
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
@@ -741,11 +2000,50 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(I2C7),
ASPEED_PINCTRL_GROUP(I2C8),
ASPEED_PINCTRL_GROUP(I2C9),
+ ASPEED_PINCTRL_GROUP(LAD0),
+ ASPEED_PINCTRL_GROUP(LAD1),
+ ASPEED_PINCTRL_GROUP(LAD2),
+ ASPEED_PINCTRL_GROUP(LAD3),
+ ASPEED_PINCTRL_GROUP(LCLK),
+ ASPEED_PINCTRL_GROUP(LFRAME),
+ ASPEED_PINCTRL_GROUP(LPCHC),
+ ASPEED_PINCTRL_GROUP(LPCPD),
+ ASPEED_PINCTRL_GROUP(LPCPLUS),
+ ASPEED_PINCTRL_GROUP(LPCPME),
+ ASPEED_PINCTRL_GROUP(LPCRST),
+ ASPEED_PINCTRL_GROUP(LPCSMI),
+ ASPEED_PINCTRL_GROUP(LSIRQ),
ASPEED_PINCTRL_GROUP(MAC1LINK),
+ ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
+ ASPEED_PINCTRL_GROUP(NCTS1),
+ ASPEED_PINCTRL_GROUP(NCTS2),
+ ASPEED_PINCTRL_GROUP(NCTS3),
+ ASPEED_PINCTRL_GROUP(NCTS4),
+ ASPEED_PINCTRL_GROUP(NDCD1),
+ ASPEED_PINCTRL_GROUP(NDCD2),
+ ASPEED_PINCTRL_GROUP(NDCD3),
+ ASPEED_PINCTRL_GROUP(NDCD4),
+ ASPEED_PINCTRL_GROUP(NDSR1),
+ ASPEED_PINCTRL_GROUP(NDSR2),
+ ASPEED_PINCTRL_GROUP(NDSR3),
+ ASPEED_PINCTRL_GROUP(NDSR4),
+ ASPEED_PINCTRL_GROUP(NDTR1),
+ ASPEED_PINCTRL_GROUP(NDTR2),
+ ASPEED_PINCTRL_GROUP(NDTR3),
+ ASPEED_PINCTRL_GROUP(NDTR4),
+ ASPEED_PINCTRL_GROUP(NRI1),
+ ASPEED_PINCTRL_GROUP(NRI2),
+ ASPEED_PINCTRL_GROUP(NRI3),
+ ASPEED_PINCTRL_GROUP(NRI4),
+ ASPEED_PINCTRL_GROUP(NRTS1),
+ ASPEED_PINCTRL_GROUP(NRTS2),
+ ASPEED_PINCTRL_GROUP(NRTS3),
+ ASPEED_PINCTRL_GROUP(NRTS4),
ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PEWAKE),
+ ASPEED_PINCTRL_GROUP(PNOR),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
@@ -758,22 +2056,102 @@ static const struct aspeed_pin_group aspeed_g5_groups[] = {
ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
ASPEED_PINCTRL_GROUP(RMII2),
+ ASPEED_PINCTRL_GROUP(RXD1),
+ ASPEED_PINCTRL_GROUP(RXD2),
+ ASPEED_PINCTRL_GROUP(RXD3),
+ ASPEED_PINCTRL_GROUP(RXD4),
+ ASPEED_PINCTRL_GROUP(SALT1),
+ ASPEED_PINCTRL_GROUP(SALT10),
+ ASPEED_PINCTRL_GROUP(SALT11),
+ ASPEED_PINCTRL_GROUP(SALT12),
+ ASPEED_PINCTRL_GROUP(SALT13),
+ ASPEED_PINCTRL_GROUP(SALT14),
+ ASPEED_PINCTRL_GROUP(SALT2),
+ ASPEED_PINCTRL_GROUP(SALT3),
+ ASPEED_PINCTRL_GROUP(SALT4),
+ ASPEED_PINCTRL_GROUP(SALT5),
+ ASPEED_PINCTRL_GROUP(SALT6),
+ ASPEED_PINCTRL_GROUP(SALT7),
+ ASPEED_PINCTRL_GROUP(SALT8),
+ ASPEED_PINCTRL_GROUP(SALT9),
+ ASPEED_PINCTRL_GROUP(SCL1),
+ ASPEED_PINCTRL_GROUP(SCL2),
ASPEED_PINCTRL_GROUP(SD1),
+ ASPEED_PINCTRL_GROUP(SD2),
+ ASPEED_PINCTRL_GROUP(SDA1),
+ ASPEED_PINCTRL_GROUP(SDA2),
+ ASPEED_PINCTRL_GROUP(SGPS1),
+ ASPEED_PINCTRL_GROUP(SGPS2),
+ ASPEED_PINCTRL_GROUP(SIOONCTRL),
+ ASPEED_PINCTRL_GROUP(SIOPBI),
+ ASPEED_PINCTRL_GROUP(SIOPBO),
+ ASPEED_PINCTRL_GROUP(SIOPWREQ),
+ ASPEED_PINCTRL_GROUP(SIOPWRGD),
+ ASPEED_PINCTRL_GROUP(SIOS3),
+ ASPEED_PINCTRL_GROUP(SIOS5),
+ ASPEED_PINCTRL_GROUP(SIOSCI),
ASPEED_PINCTRL_GROUP(SPI1),
+ ASPEED_PINCTRL_GROUP(SPI1CS1),
ASPEED_PINCTRL_GROUP(SPI1DEBUG),
ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
+ ASPEED_PINCTRL_GROUP(SPI2CK),
+ ASPEED_PINCTRL_GROUP(SPI2CS0),
+ ASPEED_PINCTRL_GROUP(SPI2CS1),
+ ASPEED_PINCTRL_GROUP(SPI2MISO),
+ ASPEED_PINCTRL_GROUP(SPI2MOSI),
+ ASPEED_PINCTRL_GROUP(TIMER3),
ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
+ ASPEED_PINCTRL_GROUP(TXD1),
+ ASPEED_PINCTRL_GROUP(TXD2),
+ ASPEED_PINCTRL_GROUP(TXD3),
+ ASPEED_PINCTRL_GROUP(TXD4),
+ ASPEED_PINCTRL_GROUP(UART6),
+ ASPEED_PINCTRL_GROUP(USBCKI),
ASPEED_PINCTRL_GROUP(VGABIOSROM),
+ ASPEED_PINCTRL_GROUP(VGAHS),
+ ASPEED_PINCTRL_GROUP(VGAVS),
+ ASPEED_PINCTRL_GROUP(VPI24),
+ ASPEED_PINCTRL_GROUP(VPO),
+ ASPEED_PINCTRL_GROUP(WDTRST1),
+ ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g5_functions[] = {
+ ASPEED_PINCTRL_FUNC(ACPI),
+ ASPEED_PINCTRL_FUNC(ADC0),
+ ASPEED_PINCTRL_FUNC(ADC1),
+ ASPEED_PINCTRL_FUNC(ADC10),
+ ASPEED_PINCTRL_FUNC(ADC11),
+ ASPEED_PINCTRL_FUNC(ADC12),
+ ASPEED_PINCTRL_FUNC(ADC13),
+ ASPEED_PINCTRL_FUNC(ADC14),
+ ASPEED_PINCTRL_FUNC(ADC15),
+ ASPEED_PINCTRL_FUNC(ADC2),
+ ASPEED_PINCTRL_FUNC(ADC3),
+ ASPEED_PINCTRL_FUNC(ADC4),
+ ASPEED_PINCTRL_FUNC(ADC5),
+ ASPEED_PINCTRL_FUNC(ADC6),
+ ASPEED_PINCTRL_FUNC(ADC7),
+ ASPEED_PINCTRL_FUNC(ADC8),
+ ASPEED_PINCTRL_FUNC(ADC9),
+ ASPEED_PINCTRL_FUNC(BMCINT),
+ ASPEED_PINCTRL_FUNC(DDCCLK),
+ ASPEED_PINCTRL_FUNC(DDCDAT),
+ ASPEED_PINCTRL_FUNC(ESPI),
+ ASPEED_PINCTRL_FUNC(FWSPICS1),
+ ASPEED_PINCTRL_FUNC(FWSPICS2),
ASPEED_PINCTRL_FUNC(GPID0),
ASPEED_PINCTRL_FUNC(GPID2),
+ ASPEED_PINCTRL_FUNC(GPID4),
+ ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
+ ASPEED_PINCTRL_FUNC(GPIE2),
+ ASPEED_PINCTRL_FUNC(GPIE4),
+ ASPEED_PINCTRL_FUNC(GPIE6),
ASPEED_PINCTRL_FUNC(I2C10),
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
@@ -786,11 +2164,50 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(I2C7),
ASPEED_PINCTRL_FUNC(I2C8),
ASPEED_PINCTRL_FUNC(I2C9),
+ ASPEED_PINCTRL_FUNC(LAD0),
+ ASPEED_PINCTRL_FUNC(LAD1),
+ ASPEED_PINCTRL_FUNC(LAD2),
+ ASPEED_PINCTRL_FUNC(LAD3),
+ ASPEED_PINCTRL_FUNC(LCLK),
+ ASPEED_PINCTRL_FUNC(LFRAME),
+ ASPEED_PINCTRL_FUNC(LPCHC),
+ ASPEED_PINCTRL_FUNC(LPCPD),
+ ASPEED_PINCTRL_FUNC(LPCPLUS),
+ ASPEED_PINCTRL_FUNC(LPCPME),
+ ASPEED_PINCTRL_FUNC(LPCRST),
+ ASPEED_PINCTRL_FUNC(LPCSMI),
+ ASPEED_PINCTRL_FUNC(LSIRQ),
ASPEED_PINCTRL_FUNC(MAC1LINK),
+ ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
+ ASPEED_PINCTRL_FUNC(NCTS1),
+ ASPEED_PINCTRL_FUNC(NCTS2),
+ ASPEED_PINCTRL_FUNC(NCTS3),
+ ASPEED_PINCTRL_FUNC(NCTS4),
+ ASPEED_PINCTRL_FUNC(NDCD1),
+ ASPEED_PINCTRL_FUNC(NDCD2),
+ ASPEED_PINCTRL_FUNC(NDCD3),
+ ASPEED_PINCTRL_FUNC(NDCD4),
+ ASPEED_PINCTRL_FUNC(NDSR1),
+ ASPEED_PINCTRL_FUNC(NDSR2),
+ ASPEED_PINCTRL_FUNC(NDSR3),
+ ASPEED_PINCTRL_FUNC(NDSR4),
+ ASPEED_PINCTRL_FUNC(NDTR1),
+ ASPEED_PINCTRL_FUNC(NDTR2),
+ ASPEED_PINCTRL_FUNC(NDTR3),
+ ASPEED_PINCTRL_FUNC(NDTR4),
+ ASPEED_PINCTRL_FUNC(NRI1),
+ ASPEED_PINCTRL_FUNC(NRI2),
+ ASPEED_PINCTRL_FUNC(NRI3),
+ ASPEED_PINCTRL_FUNC(NRI4),
+ ASPEED_PINCTRL_FUNC(NRTS1),
+ ASPEED_PINCTRL_FUNC(NRTS2),
+ ASPEED_PINCTRL_FUNC(NRTS3),
+ ASPEED_PINCTRL_FUNC(NRTS4),
ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PEWAKE),
+ ASPEED_PINCTRL_FUNC(PNOR),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
@@ -803,16 +2220,68 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = {
ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
ASPEED_PINCTRL_FUNC(RMII2),
+ ASPEED_PINCTRL_FUNC(RXD1),
+ ASPEED_PINCTRL_FUNC(RXD2),
+ ASPEED_PINCTRL_FUNC(RXD3),
+ ASPEED_PINCTRL_FUNC(RXD4),
+ ASPEED_PINCTRL_FUNC(SALT1),
+ ASPEED_PINCTRL_FUNC(SALT10),
+ ASPEED_PINCTRL_FUNC(SALT11),
+ ASPEED_PINCTRL_FUNC(SALT12),
+ ASPEED_PINCTRL_FUNC(SALT13),
+ ASPEED_PINCTRL_FUNC(SALT14),
+ ASPEED_PINCTRL_FUNC(SALT2),
+ ASPEED_PINCTRL_FUNC(SALT3),
+ ASPEED_PINCTRL_FUNC(SALT4),
+ ASPEED_PINCTRL_FUNC(SALT5),
+ ASPEED_PINCTRL_FUNC(SALT6),
+ ASPEED_PINCTRL_FUNC(SALT7),
+ ASPEED_PINCTRL_FUNC(SALT8),
+ ASPEED_PINCTRL_FUNC(SALT9),
+ ASPEED_PINCTRL_FUNC(SCL1),
+ ASPEED_PINCTRL_FUNC(SCL2),
ASPEED_PINCTRL_FUNC(SD1),
+ ASPEED_PINCTRL_FUNC(SD2),
+ ASPEED_PINCTRL_FUNC(SDA1),
+ ASPEED_PINCTRL_FUNC(SDA2),
+ ASPEED_PINCTRL_FUNC(SGPS1),
+ ASPEED_PINCTRL_FUNC(SGPS2),
+ ASPEED_PINCTRL_FUNC(SIOONCTRL),
+ ASPEED_PINCTRL_FUNC(SIOPBI),
+ ASPEED_PINCTRL_FUNC(SIOPBO),
+ ASPEED_PINCTRL_FUNC(SIOPWREQ),
+ ASPEED_PINCTRL_FUNC(SIOPWRGD),
+ ASPEED_PINCTRL_FUNC(SIOS3),
+ ASPEED_PINCTRL_FUNC(SIOS5),
+ ASPEED_PINCTRL_FUNC(SIOSCI),
ASPEED_PINCTRL_FUNC(SPI1),
+ ASPEED_PINCTRL_FUNC(SPI1CS1),
ASPEED_PINCTRL_FUNC(SPI1DEBUG),
ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
+ ASPEED_PINCTRL_FUNC(SPI2CK),
+ ASPEED_PINCTRL_FUNC(SPI2CS0),
+ ASPEED_PINCTRL_FUNC(SPI2CS1),
+ ASPEED_PINCTRL_FUNC(SPI2MISO),
+ ASPEED_PINCTRL_FUNC(SPI2MOSI),
+ ASPEED_PINCTRL_FUNC(TIMER3),
ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
+ ASPEED_PINCTRL_FUNC(TXD1),
+ ASPEED_PINCTRL_FUNC(TXD2),
+ ASPEED_PINCTRL_FUNC(TXD3),
+ ASPEED_PINCTRL_FUNC(TXD4),
+ ASPEED_PINCTRL_FUNC(UART6),
+ ASPEED_PINCTRL_FUNC(USBCKI),
ASPEED_PINCTRL_FUNC(VGABIOSROM),
+ ASPEED_PINCTRL_FUNC(VGAHS),
+ ASPEED_PINCTRL_FUNC(VGAVS),
+ ASPEED_PINCTRL_FUNC(VPI24),
+ ASPEED_PINCTRL_FUNC(VPO),
+ ASPEED_PINCTRL_FUNC(WDTRST1),
+ ASPEED_PINCTRL_FUNC(WDTRST2),
};
static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = {
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
index 727728b86c07..f0dad016c9fd 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -260,6 +260,7 @@
#define SCUA0 0xA0 /* Multi-function Pin Control #7 */
#define SCUA4 0xA4 /* Multi-function Pin Control #8 */
#define SCUA8 0xA8 /* Multi-function Pin Control #9 */
+#define SCUAC 0xAC /* Multi-function Pin Control #10 */
#define HW_STRAP2 0xD0 /* Strapping */
/**
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v2 5/6] pinctrl: aspeed-g4: Add mux configuration for all pins
From: Andrew Jeffery @ 2016-11-02 14:38 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring, linux-gpio,
linux-arm-kernel, linux-kernel, devicetree, Andrew Jeffery,
Timothy Pearson
In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au>
The patch introducing the g4 pinctrl driver implemented a smattering of
pins to flesh out the implementation of the core and provide bare-bones
support for some OpenPOWER platforms. Now, update the bindings document
to reflect the complete functionality and implement the necessary pin
configuration tables in the driver.
Cc: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Acked-by: Joel Stanley <joel@jms.id.au>
Acked-by: Rob Herring <robh@kernel.org>
---
No significant change since v1.
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 19 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1097 +++++++++++++++++++-
2 files changed, 1096 insertions(+), 20 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index 115b0cce6c1c..f5c427d11337 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -38,13 +38,18 @@ supported:
aspeed,ast2400-pinctrl, aspeed,g4-pinctrl:
-ACPI BMCINT DDCCLK DDCDAT FLACK FLBUSY FLWP GPID0 GPIE0 GPIE2 GPIE4 GPIE6 I2C10
-I2C11 I2C12 I2C13 I2C3 I2C4 I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCSMI MDIO1
-MDIO2 NCTS1 NCTS3 NCTS4 NDCD1 NDCD3 NDCD4 NDSR1 NDSR3 NDTR1 NDTR3 NRI1 NRI3
-NRI4 NRTS1 NRTS3 PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RMII1 ROM16
-ROM8 ROMCS1 ROMCS2 ROMCS3 ROMCS4 RXD1 RXD3 RXD4 SD1 SGPMI SIOPBI SIOPBO TIMER3
-TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD3 TXD4 UART6 VGAHS VGAVS VPI18 VPI24 VPI30
-VPO12 VPO24
+ACPI ADC0 ADC1 ADC10 ADC11 ADC12 ADC13 ADC14 ADC15 ADC2 ADC3 ADC4 ADC5 ADC6
+ADC7 ADC8 ADC9 BMCINT DDCCLK DDCDAT EXTRST FLACK FLBUSY FLWP GPID GPID0 GPID2
+GPID4 GPID6 GPIE0 GPIE2 GPIE4 GPIE6 I2C10 I2C11 I2C12 I2C13 I2C14 I2C3 I2C4
+I2C5 I2C6 I2C7 I2C8 I2C9 LPCPD LPCPME LPCRST LPCSMI MAC1LINK MAC2LINK MDIO1
+MDIO2 NCTS1 NCTS2 NCTS3 NCTS4 NDCD1 NDCD2 NDCD3 NDCD4 NDSR1 NDSR2 NDSR3 NDSR4
+NDTR1 NDTR2 NDTR3 NDTR4 NDTS4 NRI1 NRI2 NRI3 NRI4 NRTS1 NRTS2 NRTS3 OSCCLK PWM0
+PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 RGMII1 RGMII2 RMII1 RMII2 ROM16 ROM8 ROMCS1
+ROMCS2 ROMCS3 ROMCS4 RXD1 RXD2 RXD3 RXD4 SALT1 SALT2 SALT3 SALT4 SD1 SD2 SGPMCK
+SGPMI SGPMLD SGPMO SGPSCK SGPSI0 SGPSI1 SGPSLD SIOONCTRL SIOPBI SIOPBO SIOPWREQ
+SIOPWRGD SIOS3 SIOS5 SIOSCI SPI1 SPI1DEBUG SPI1PASSTHRU SPICS1 TIMER3 TIMER4
+TIMER5 TIMER6 TIMER7 TIMER8 TXD1 TXD2 TXD3 TXD4 UART6 USBCKI VGABIOS_ROM VGAHS
+VGAVS VPI18 VPI24 VPI30 VPO12 VPO24 WDTRST1 WDTRST2
aspeed,ast2500-pinctrl, aspeed,g5-pinctrl:
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index 558bd102416c..09b668415c56 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -43,9 +43,18 @@
* Not all pins have their signals defined (yet).
*/
+#define D6 0
+SSSF_PIN_DECL(D6, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
+
+#define B5 1
+SSSF_PIN_DECL(B5, GPIOA1, MAC2LINK, SIG_DESC_SET(SCU80, 1));
+
#define A4 2
SSSF_PIN_DECL(A4, GPIOA2, TIMER3, SIG_DESC_SET(SCU80, 2));
+#define E6 3
+SSSF_PIN_DECL(E6, GPIOA3, TIMER4, SIG_DESC_SET(SCU80, 3));
+
#define I2C9_DESC SIG_DESC_SET(SCU90, 22)
#define C5 4
@@ -80,6 +89,26 @@ MS_PIN_DECL(D5, GPIOA7, MDIO2, TIMER8);
FUNC_GROUP_DECL(TIMER8, D5);
FUNC_GROUP_DECL(MDIO2, A3, D5);
+#define J21 8
+SSSF_PIN_DECL(J21, GPIOB0, SALT1, SIG_DESC_SET(SCU80, 8));
+
+#define J20 9
+SSSF_PIN_DECL(J20, GPIOB1, SALT2, SIG_DESC_SET(SCU80, 9));
+
+#define H18 10
+SSSF_PIN_DECL(H18, GPIOB2, SALT3, SIG_DESC_SET(SCU80, 10));
+
+#define F18 11
+SSSF_PIN_DECL(F18, GPIOB3, SALT4, SIG_DESC_SET(SCU80, 11));
+
+#define E19 12
+SIG_EXPR_DECL(LPCRST, LPCRST, SIG_DESC_SET(SCU80, 12));
+SIG_EXPR_DECL(LPCRST, LPCRSTS, SIG_DESC_SET(HW_STRAP1, 14));
+SIG_EXPR_LIST_DECL_DUAL(LPCRST, LPCRST, LPCRSTS);
+SS_PIN_DECL(E19, GPIOB4, LPCRST);
+
+FUNC_GROUP_DECL(LPCRST, E19);
+
#define H19 13
#define H19_DESC SIG_DESC_SET(SCU80, 13)
SIG_EXPR_LIST_DECL_SINGLE(LPCPD, LPCPD, H19_DESC);
@@ -92,6 +121,19 @@ FUNC_GROUP_DECL(LPCSMI, H19);
#define H20 14
SSSF_PIN_DECL(H20, GPIOB6, LPCPME, SIG_DESC_SET(SCU80, 14));
+#define E18 15
+SIG_EXPR_LIST_DECL_SINGLE(EXTRST, EXTRST,
+ SIG_DESC_SET(SCU80, 15),
+ SIG_DESC_BIT(SCU90, 31, 0),
+ SIG_DESC_SET(SCU3C, 3));
+SIG_EXPR_LIST_DECL_SINGLE(SPICS1, SPICS1,
+ SIG_DESC_SET(SCU80, 15),
+ SIG_DESC_SET(SCU90, 31));
+MS_PIN_DECL(E18, GPIOB7, EXTRST, SPICS1);
+
+FUNC_GROUP_DECL(EXTRST, E18);
+FUNC_GROUP_DECL(SPICS1, E18);
+
#define SD1_DESC SIG_DESC_SET(SCU90, 0)
#define I2C10_DESC SIG_DESC_SET(SCU90, 23)
@@ -170,6 +212,62 @@ MS_PIN_DECL(D16, GPIOD1, SD2CMD, GPID0OUT);
FUNC_GROUP_DECL(GPID0, A18, D16);
+#define GPID2_DESC SIG_DESC_SET(SCU8C, 9)
+
+#define B17 26
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT0, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID2IN, GPID2, GPID2_DESC);
+SIG_EXPR_DECL(GPID2IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID2IN, GPID2, GPID);
+MS_PIN_DECL(B17, GPIOD2, SD2DAT0, GPID2IN);
+
+#define A17 27
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT1, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID2OUT, GPID2, GPID2_DESC);
+SIG_EXPR_DECL(GPID2OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID2OUT, GPID2, GPID);
+MS_PIN_DECL(A17, GPIOD3, SD2DAT1, GPID2OUT);
+
+FUNC_GROUP_DECL(GPID2, B17, A17);
+
+#define GPID4_DESC SIG_DESC_SET(SCU8C, 10)
+
+#define C16 28
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT2, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID4IN, GPID4, GPID4_DESC);
+SIG_EXPR_DECL(GPID4IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID4IN, GPID4, GPID);
+MS_PIN_DECL(C16, GPIOD4, SD2DAT2, GPID4IN);
+
+#define B16 29
+SIG_EXPR_LIST_DECL_SINGLE(SD2DAT3, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID4OUT, GPID4, GPID4_DESC);
+SIG_EXPR_DECL(GPID4OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID4OUT, GPID4, GPID);
+MS_PIN_DECL(B16, GPIOD5, SD2DAT3, GPID4OUT);
+
+FUNC_GROUP_DECL(GPID4, C16, B16);
+
+#define GPID6_DESC SIG_DESC_SET(SCU8C, 11)
+
+#define A16 30
+SIG_EXPR_LIST_DECL_SINGLE(SD2CD, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID6IN, GPID6, GPID6_DESC);
+SIG_EXPR_DECL(GPID6IN, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID6IN, GPID6, GPID);
+MS_PIN_DECL(A16, GPIOD6, SD2CD, GPID6IN);
+
+#define E15 31
+SIG_EXPR_LIST_DECL_SINGLE(SD2WP, SD2, SD2_DESC);
+SIG_EXPR_DECL(GPID6OUT, GPID6, GPID6_DESC);
+SIG_EXPR_DECL(GPID6OUT, GPID, GPID_DESC);
+SIG_EXPR_LIST_DECL_DUAL(GPID6OUT, GPID6, GPID);
+MS_PIN_DECL(E15, GPIOD7, SD2WP, GPID6OUT);
+
+FUNC_GROUP_DECL(GPID6, A16, E15);
+FUNC_GROUP_DECL(SD2, A18, D16, B17, A17, C16, B16, A16, E15);
+FUNC_GROUP_DECL(GPID, A18, D16, B17, A17, C16, B16, A16, E15);
+
#define GPIE_DESC SIG_DESC_SET(HW_STRAP1, 22)
#define GPIE0_DESC SIG_DESC_SET(SCU8C, 12)
#define GPIE2_DESC SIG_DESC_SET(SCU8C, 13)
@@ -266,6 +364,15 @@ MS_PIN_DECL(B19, GPIOF1, NDCD4, SIOPBI);
FUNC_GROUP_DECL(NDCD4, B19);
FUNC_GROUP_DECL(SIOPBI, B19);
+#define A20 42
+SIG_EXPR_LIST_DECL_SINGLE(NDSR4, NDSR4, SIG_DESC_SET(SCU80, 26));
+SIG_EXPR_DECL(SIOPWRGD, SIOPWRGD, SIG_DESC_SET(SCUA4, 12));
+SIG_EXPR_DECL(SIOPWRGD, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPWRGD, SIOPWRGD, ACPI);
+MS_PIN_DECL(A20, GPIOF2, NDSR4, SIOPWRGD);
+FUNC_GROUP_DECL(NDSR4, A20);
+FUNC_GROUP_DECL(SIOPWRGD, A20);
+
#define D17 43
SIG_EXPR_LIST_DECL_SINGLE(NRI4, NRI4, SIG_DESC_SET(SCU80, 27));
SIG_EXPR_DECL(SIOPBO, SIOPBO, SIG_DESC_SET(SCUA4, 14));
@@ -275,7 +382,17 @@ MS_PIN_DECL(D17, GPIOF3, NRI4, SIOPBO);
FUNC_GROUP_DECL(NRI4, D17);
FUNC_GROUP_DECL(SIOPBO, D17);
-FUNC_GROUP_DECL(ACPI, B19, D17);
+#define B18 44
+SSSF_PIN_DECL(B18, GPIOF4, NDTR4, SIG_DESC_SET(SCU80, 28));
+
+#define A19 45
+SIG_EXPR_LIST_DECL_SINGLE(NDTS4, NDTS4, SIG_DESC_SET(SCU80, 29));
+SIG_EXPR_DECL(SIOSCI, SIOSCI, SIG_DESC_SET(SCUA4, 15));
+SIG_EXPR_DECL(SIOSCI, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOSCI, SIOSCI, ACPI);
+MS_PIN_DECL(A19, GPIOF5, NDTS4, SIOSCI);
+FUNC_GROUP_DECL(NDTS4, A19);
+FUNC_GROUP_DECL(SIOSCI, A19);
#define E16 46
SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
@@ -283,6 +400,34 @@ SSSF_PIN_DECL(E16, GPIOF6, TXD4, SIG_DESC_SET(SCU80, 30));
#define C17 47
SSSF_PIN_DECL(C17, GPIOF7, RXD4, SIG_DESC_SET(SCU80, 31));
+#define A14 48
+SSSF_PIN_DECL(A14, GPIOG0, SGPSCK, SIG_DESC_SET(SCU84, 0));
+
+#define E13 49
+SSSF_PIN_DECL(E13, GPIOG1, SGPSLD, SIG_DESC_SET(SCU84, 1));
+
+#define D13 50
+SSSF_PIN_DECL(D13, GPIOG2, SGPSI0, SIG_DESC_SET(SCU84, 2));
+
+#define C13 51
+SSSF_PIN_DECL(C13, GPIOG3, SGPSI1, SIG_DESC_SET(SCU84, 3));
+
+#define B13 52
+SIG_EXPR_LIST_DECL_SINGLE(OSCCLK, OSCCLK, SIG_DESC_SET(SCU2C, 1));
+SIG_EXPR_LIST_DECL_SINGLE(WDTRST1, WDTRST1, SIG_DESC_SET(SCU84, 4));
+MS_PIN_DECL(B13, GPIOG4, OSCCLK, WDTRST1);
+
+FUNC_GROUP_DECL(OSCCLK, B13);
+FUNC_GROUP_DECL(WDTRST1, B13);
+
+#define Y21 53
+SIG_EXPR_LIST_DECL_SINGLE(USBCKI, USBCKI, SIG_DESC_SET(HW_STRAP1, 23));
+SIG_EXPR_LIST_DECL_SINGLE(WDTRST2, WDTRST2, SIG_DESC_SET(SCU84, 5));
+MS_PIN_DECL(Y21, GPIOG5, USBCKI, WDTRST2);
+
+FUNC_GROUP_DECL(USBCKI, Y21);
+FUNC_GROUP_DECL(WDTRST2, Y21);
+
#define AA22 54
SSSF_PIN_DECL(AA22, GPIOG6, FLBUSY, SIG_DESC_SET(SCU84, 6));
@@ -352,6 +497,93 @@ MS_PIN_DECL(E7, GPIOH7, ROMD15, RXD6);
FUNC_GROUP_DECL(UART6, A8, C7, B7, A7, D7, B6, A6, E7);
+#define SPI1_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
+#define SPI1DEBUG_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
+#define SPI1PASSTHRU_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
+
+#define C22 64
+SIG_EXPR_DECL(SYSCS, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SYSCS, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SYSCS, SPI1DEBUG, SPI1PASSTHRU);
+SS_PIN_DECL(C22, GPIOI0, SYSCS);
+
+#define G18 65
+SIG_EXPR_DECL(SYSCK, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SYSCK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SYSCK, SPI1DEBUG, SPI1PASSTHRU);
+SS_PIN_DECL(G18, GPIOI1, SYSCK);
+
+#define D19 66
+SIG_EXPR_DECL(SYSDO, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SYSDO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SYSDO, SPI1DEBUG, SPI1PASSTHRU);
+SS_PIN_DECL(D19, GPIOI2, SYSDO);
+
+#define C20 67
+SIG_EXPR_DECL(SYSDI, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SYSDI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SYSDI, SPI1DEBUG, SPI1PASSTHRU);
+SS_PIN_DECL(C20, GPIOI3, SYSDI);
+
+#define VB_DESC SIG_DESC_SET(HW_STRAP1, 5)
+
+#define B22 68
+SIG_EXPR_DECL(SPI1CS0, SPI1, SPI1_DESC);
+SIG_EXPR_DECL(SPI1CS0, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SPI1CS0, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1CS0, SIG_EXPR_PTR(SPI1CS0, SPI1),
+ SIG_EXPR_PTR(SPI1CS0, SPI1DEBUG),
+ SIG_EXPR_PTR(SPI1CS0, SPI1PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBCS, VGABIOS_ROM, VB_DESC);
+MS_PIN_DECL(B22, GPIOI4, SPI1CS0, VBCS);
+
+#define G19 69
+SIG_EXPR_DECL(SPI1CK, SPI1, SPI1_DESC);
+SIG_EXPR_DECL(SPI1CK, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SPI1CK, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1CK, SIG_EXPR_PTR(SPI1CK, SPI1),
+ SIG_EXPR_PTR(SPI1CK, SPI1DEBUG),
+ SIG_EXPR_PTR(SPI1CK, SPI1PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBCK, VGABIOS_ROM, VB_DESC);
+MS_PIN_DECL(G19, GPIOI5, SPI1CK, VBCK);
+
+#define C18 70
+SIG_EXPR_DECL(SPI1DO, SPI1, SPI1_DESC);
+SIG_EXPR_DECL(SPI1DO, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SPI1DO, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1DO, SIG_EXPR_PTR(SPI1DO, SPI1),
+ SIG_EXPR_PTR(SPI1DO, SPI1DEBUG),
+ SIG_EXPR_PTR(SPI1DO, SPI1PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBDO, VGABIOS_ROM, VB_DESC);
+MS_PIN_DECL(C18, GPIOI6, SPI1DO, VBDO);
+
+#define E20 71
+SIG_EXPR_DECL(SPI1DI, SPI1, SPI1_DESC);
+SIG_EXPR_DECL(SPI1DI, SPI1DEBUG, SPI1DEBUG_DESC);
+SIG_EXPR_DECL(SPI1DI, SPI1PASSTHRU, SPI1PASSTHRU_DESC);
+SIG_EXPR_LIST_DECL(SPI1DI, SIG_EXPR_PTR(SPI1DI, SPI1),
+ SIG_EXPR_PTR(SPI1DI, SPI1DEBUG),
+ SIG_EXPR_PTR(SPI1DI, SPI1PASSTHRU));
+SIG_EXPR_LIST_DECL_SINGLE(VBDI, VGABIOS_ROM, VB_DESC);
+MS_PIN_DECL(E20, GPIOI7, SPI1DI, VBDI);
+
+FUNC_GROUP_DECL(SPI1, B22, G19, C18, E20);
+FUNC_GROUP_DECL(SPI1DEBUG, C22, G18, D19, C20, B22, G19, C18, E20);
+FUNC_GROUP_DECL(SPI1PASSTHRU, C22, G18, D19, C20, B22, G19, C18, E20);
+FUNC_GROUP_DECL(VGABIOS_ROM, B22, G19, C18, E20);
+
+#define J5 72
+SSSF_PIN_DECL(J5, GPIOJ0, SGPMCK, SIG_DESC_SET(SCU84, 8));
+
+#define J4 73
+SSSF_PIN_DECL(J4, GPIOJ1, SGPMLD, SIG_DESC_SET(SCU84, 9));
+
+#define K5 74
+SSSF_PIN_DECL(K5, GPIOJ2, SGPMO, SIG_DESC_SET(SCU84, 10));
+
#define J3 75
SSSF_PIN_DECL(J3, GPIOJ3, SGPMI, SIG_DESC_SET(SCU84, 11));
@@ -496,6 +728,102 @@ SIG_EXPR_LIST_DECL_SINGLE(RXD1, RXD1, U5_DESC);
MS_PIN_DECL(U5, GPIOL7, VPIB1, RXD1);
FUNC_GROUP_DECL(RXD1, U5);
+#define V3 96
+#define V3_DESC SIG_DESC_SET(SCU84, 24)
+SIG_EXPR_DECL(VPIOB2, VPI18, VPI18_DESC, V3_DESC);
+SIG_EXPR_DECL(VPIOB2, VPI24, VPI24_DESC, V3_DESC);
+SIG_EXPR_DECL(VPIOB2, VPI30, VPI30_DESC, V3_DESC);
+SIG_EXPR_LIST_DECL(VPIOB2, SIG_EXPR_PTR(VPIOB2, VPI18),
+ SIG_EXPR_PTR(VPIOB2, VPI24),
+ SIG_EXPR_PTR(VPIOB2, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NCTS2, NCTS2, V3_DESC);
+MS_PIN_DECL(V3, GPIOM0, VPIOB2, NCTS2);
+FUNC_GROUP_DECL(NCTS2, V3);
+
+#define W2 97
+#define W2_DESC SIG_DESC_SET(SCU84, 25)
+SIG_EXPR_DECL(VPIOB3, VPI18, VPI18_DESC, W2_DESC);
+SIG_EXPR_DECL(VPIOB3, VPI24, VPI24_DESC, W2_DESC);
+SIG_EXPR_DECL(VPIOB3, VPI30, VPI30_DESC, W2_DESC);
+SIG_EXPR_LIST_DECL(VPIOB3, SIG_EXPR_PTR(VPIOB3, VPI18),
+ SIG_EXPR_PTR(VPIOB3, VPI24),
+ SIG_EXPR_PTR(VPIOB3, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDCD2, NDCD2, W2_DESC);
+MS_PIN_DECL(W2, GPIOM1, VPIOB3, NDCD2);
+FUNC_GROUP_DECL(NDCD2, W2);
+
+#define Y1 98
+#define Y1_DESC SIG_DESC_SET(SCU84, 26)
+SIG_EXPR_DECL(VPIOB4, VPI18, VPI18_DESC, Y1_DESC);
+SIG_EXPR_DECL(VPIOB4, VPI24, VPI24_DESC, Y1_DESC);
+SIG_EXPR_DECL(VPIOB4, VPI30, VPI30_DESC, Y1_DESC);
+SIG_EXPR_LIST_DECL(VPIOB4, SIG_EXPR_PTR(VPIOB4, VPI18),
+ SIG_EXPR_PTR(VPIOB4, VPI24),
+ SIG_EXPR_PTR(VPIOB4, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDSR2, NDSR2, Y1_DESC);
+MS_PIN_DECL(Y1, GPIOM2, VPIOB4, NDSR2);
+FUNC_GROUP_DECL(NDSR2, Y1);
+
+#define V4 99
+#define V4_DESC SIG_DESC_SET(SCU84, 27)
+SIG_EXPR_DECL(VPIOB5, VPI18, VPI18_DESC, V4_DESC);
+SIG_EXPR_DECL(VPIOB5, VPI24, VPI24_DESC, V4_DESC);
+SIG_EXPR_DECL(VPIOB5, VPI30, VPI30_DESC, V4_DESC);
+SIG_EXPR_LIST_DECL(VPIOB5, SIG_EXPR_PTR(VPIOB5, VPI18),
+ SIG_EXPR_PTR(VPIOB5, VPI24),
+ SIG_EXPR_PTR(VPIOB5, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NRI2, NRI2, V4_DESC);
+MS_PIN_DECL(V4, GPIOM3, VPIOB5, NRI2);
+FUNC_GROUP_DECL(NRI2, V4);
+
+#define W3 100
+#define W3_DESC SIG_DESC_SET(SCU84, 28)
+SIG_EXPR_DECL(VPIOB6, VPI18, VPI18_DESC, W3_DESC);
+SIG_EXPR_DECL(VPIOB6, VPI24, VPI24_DESC, W3_DESC);
+SIG_EXPR_DECL(VPIOB6, VPI30, VPI30_DESC, W3_DESC);
+SIG_EXPR_LIST_DECL(VPIOB6, SIG_EXPR_PTR(VPIOB6, VPI18),
+ SIG_EXPR_PTR(VPIOB6, VPI24),
+ SIG_EXPR_PTR(VPIOB6, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NDTR2, NDTR2, W3_DESC);
+MS_PIN_DECL(W3, GPIOM4, VPIOB6, NDTR2);
+FUNC_GROUP_DECL(NDTR2, W3);
+
+#define Y2 101
+#define Y2_DESC SIG_DESC_SET(SCU84, 29)
+SIG_EXPR_DECL(VPIOB7, VPI18, VPI18_DESC, Y2_DESC);
+SIG_EXPR_DECL(VPIOB7, VPI24, VPI24_DESC, Y2_DESC);
+SIG_EXPR_DECL(VPIOB7, VPI30, VPI30_DESC, Y2_DESC);
+SIG_EXPR_LIST_DECL(VPIOB7, SIG_EXPR_PTR(VPIOB7, VPI18),
+ SIG_EXPR_PTR(VPIOB7, VPI24),
+ SIG_EXPR_PTR(VPIOB7, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(NRTS2, NRTS2, Y2_DESC);
+MS_PIN_DECL(Y2, GPIOM5, VPIOB7, NRTS2);
+FUNC_GROUP_DECL(NRTS2, Y2);
+
+#define AA1 102
+#define AA1_DESC SIG_DESC_SET(SCU84, 30)
+SIG_EXPR_DECL(VPIOB8, VPI18, VPI18_DESC, AA1_DESC);
+SIG_EXPR_DECL(VPIOB8, VPI24, VPI24_DESC, AA1_DESC);
+SIG_EXPR_DECL(VPIOB8, VPI30, VPI30_DESC, AA1_DESC);
+SIG_EXPR_LIST_DECL(VPIOB8, SIG_EXPR_PTR(VPIOB8, VPI18),
+ SIG_EXPR_PTR(VPIOB8, VPI24),
+ SIG_EXPR_PTR(VPIOB8, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(TXD2, TXD2, AA1_DESC);
+MS_PIN_DECL(AA1, GPIOM6, VPIOB8, TXD2);
+FUNC_GROUP_DECL(TXD2, AA1);
+
+#define V5 103
+#define V5_DESC SIG_DESC_SET(SCU84, 31)
+SIG_EXPR_DECL(VPIOB9, VPI18, VPI18_DESC, V5_DESC);
+SIG_EXPR_DECL(VPIOB9, VPI24, VPI24_DESC, V5_DESC);
+SIG_EXPR_DECL(VPIOB9, VPI30, VPI30_DESC, V5_DESC);
+SIG_EXPR_LIST_DECL(VPIOB9, SIG_EXPR_PTR(VPIOB9, VPI18),
+ SIG_EXPR_PTR(VPIOB9, VPI24),
+ SIG_EXPR_PTR(VPIOB9, VPI30));
+SIG_EXPR_LIST_DECL_SINGLE(RXD2, RXD2, V5_DESC);
+MS_PIN_DECL(V5, GPIOM7, VPIOB9, RXD2);
+FUNC_GROUP_DECL(RXD2, V5);
+
#define W4 104
#define W4_DESC SIG_DESC_SET(SCU88, 0)
SIG_EXPR_LIST_DECL_SINGLE(VPIG0, VPI30, VPI30_DESC, W4_DESC);
@@ -580,10 +908,57 @@ SS_PIN_DECL(V6, GPIOO0, VPIG8);
SIG_EXPR_LIST_DECL_SINGLE(VPIG9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 9));
SS_PIN_DECL(Y5, GPIOO1, VPIG9);
-FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2);
-FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, AA22, W5, Y4, AA3, AB2, V6, Y5);
-FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, W4, Y3, AA22, W5, Y4, AA3,
- AB2);
+#define AA4 114
+SIG_EXPR_LIST_DECL_SINGLE(VPIR0, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 10));
+SS_PIN_DECL(AA4, GPIOO2, VPIR0);
+
+#define AB3 115
+SIG_EXPR_LIST_DECL_SINGLE(VPIR1, VPI30, VPI30_DESC, SIG_DESC_SET(SCU88, 11));
+SS_PIN_DECL(AB3, GPIOO3, VPIR1);
+
+#define W6 116
+SIG_EXPR_LIST_DECL_SINGLE(VPIR2, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 12));
+SS_PIN_DECL(W6, GPIOO4, VPIR2);
+
+#define AA5 117
+SIG_EXPR_LIST_DECL_SINGLE(VPIR3, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 13));
+SS_PIN_DECL(AA5, GPIOO5, VPIR3);
+
+#define AB4 118
+SIG_EXPR_LIST_DECL_SINGLE(VPIR4, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 14));
+SS_PIN_DECL(AB4, GPIOO6, VPIR4);
+
+#define V7 119
+SIG_EXPR_LIST_DECL_SINGLE(VPIR5, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 15));
+SS_PIN_DECL(V7, GPIOO7, VPIR5);
+
+#define Y6 120
+SIG_EXPR_LIST_DECL_SINGLE(VPIR6, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 16));
+SS_PIN_DECL(Y6, GPIOP0, VPIR6);
+
+#define AB5 121
+SIG_EXPR_LIST_DECL_SINGLE(VPIR7, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 17));
+SS_PIN_DECL(AB5, GPIOP1, VPIR7);
+
+#define W7 122
+SIG_EXPR_LIST_DECL_SINGLE(VPIR8, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 18));
+SS_PIN_DECL(W7, GPIOP2, VPIR8);
+
+#define AA6 123
+SIG_EXPR_LIST_DECL_SINGLE(VPIR9, VPI24, VPI24_DESC, SIG_DESC_SET(SCU88, 19));
+SS_PIN_DECL(AA6, GPIOP3, VPIR9);
+
+FUNC_GROUP_DECL(VPI18, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
+ AA22, W5, Y4, AA3, AB2);
+FUNC_GROUP_DECL(VPI24, T5, U3, V1, U4, V2, V3, W2, Y1, V4, W3, Y2, AA1, V5,
+ AA22, W5, Y4, AA3, AB2, V6, Y5, W6, AA5, AB4, V7, Y6, AB5, W7,
+ AA6);
+FUNC_GROUP_DECL(VPI30, T5, U3, V1, U4, V2, W1, U5, V3, W2, Y1, V4, W3, Y2, AA1,
+ V5, W4, Y3, AA22, W5, Y4, AA3, AB2, AA4, AB3);
+
+#define AB6 124
+SIG_EXPR_LIST_DECL_SINGLE(GPIOP4, GPIOP4);
+MS_PIN_DECL_(AB6, SIG_EXPR_LIST_PTR(GPIOP4));
#define Y7 125
SIG_EXPR_LIST_DECL_SINGLE(GPIOP5, GPIOP5);
@@ -619,6 +994,18 @@ SS_PIN_DECL(F5, GPIOQ3, SDA4);
FUNC_GROUP_DECL(I2C4, B1, F5);
+#define I2C14_DESC SIG_DESC_SET(SCU90, 27)
+
+#define H4 132
+SIG_EXPR_LIST_DECL_SINGLE(SCL14, I2C14, I2C14_DESC);
+SS_PIN_DECL(H4, GPIOQ4, SCL14);
+
+#define H3 133
+SIG_EXPR_LIST_DECL_SINGLE(SDA14, I2C14, I2C14_DESC);
+SS_PIN_DECL(H3, GPIOQ5, SDA14);
+
+FUNC_GROUP_DECL(I2C14, H4, H3);
+
#define DASH9028_DESC SIG_DESC_SET(SCU90, 28)
#define H2 134
@@ -776,13 +1163,6 @@ SIG_EXPR_LIST_DECL(ROMA23, SIG_EXPR_PTR(ROMA23, ROM8),
SIG_EXPR_LIST_DECL_SINGLE(VPOR5, VPO24, K18_DESC, VPO_24_OFF);
MS_PIN_DECL(K18, GPIOS7, ROMA23, VPOR5);
-FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
- U19);
-FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
- A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19);
-FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20);
-FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22);
-
#define RMII1_DESC SIG_DESC_BIT(HW_STRAP1, 6, 0)
#define A12 152
@@ -827,6 +1207,50 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1TXD3, RGMII1);
MS_PIN_DECL_(A13, SIG_EXPR_LIST_PTR(GPIOT5), SIG_EXPR_LIST_PTR(DASHA13),
SIG_EXPR_LIST_PTR(RGMII1TXD3));
+#define RMII2_DESC SIG_DESC_BIT(HW_STRAP1, 7, 0)
+
+#define D9 158
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT6, GPIOT6, SIG_DESC_SET(SCUA0, 6));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXEN, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCK, RGMII2);
+MS_PIN_DECL_(D9, SIG_EXPR_LIST_PTR(GPIOT6), SIG_EXPR_LIST_PTR(RMII2TXEN),
+ SIG_EXPR_LIST_PTR(RGMII2TXCK));
+
+#define E9 159
+SIG_EXPR_LIST_DECL_SINGLE(GPIOT7, GPIOT7, SIG_DESC_SET(SCUA0, 7));
+SIG_EXPR_LIST_DECL_SINGLE(DASHE9, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXCTL, RGMII2);
+MS_PIN_DECL_(E9, SIG_EXPR_LIST_PTR(GPIOT7), SIG_EXPR_LIST_PTR(DASHE9),
+ SIG_EXPR_LIST_PTR(RGMII2TXCTL));
+
+#define A10 160
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU0, GPIOU0, SIG_DESC_SET(SCUA0, 8));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD0, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD0, RGMII2);
+MS_PIN_DECL_(A10, SIG_EXPR_LIST_PTR(GPIOU0), SIG_EXPR_LIST_PTR(RMII2TXD0),
+ SIG_EXPR_LIST_PTR(RGMII2TXD0));
+
+#define B10 161
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU1, GPIOU1, SIG_DESC_SET(SCUA0, 9));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2TXD1, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD1, RGMII2);
+MS_PIN_DECL_(B10, SIG_EXPR_LIST_PTR(GPIOU1), SIG_EXPR_LIST_PTR(RMII2TXD1),
+ SIG_EXPR_LIST_PTR(RGMII2TXD1));
+
+#define C10 162
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU2, GPIOU2, SIG_DESC_SET(SCUA0, 10));
+SIG_EXPR_LIST_DECL_SINGLE(DASHC10, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD2, RGMII2);
+MS_PIN_DECL_(C10, SIG_EXPR_LIST_PTR(GPIOU2), SIG_EXPR_LIST_PTR(DASHC10),
+ SIG_EXPR_LIST_PTR(RGMII2TXD2));
+
+#define D10 163
+SIG_EXPR_LIST_DECL_SINGLE(GPIOU3, GPIOU3, SIG_DESC_SET(SCUA0, 11));
+SIG_EXPR_LIST_DECL_SINGLE(DASHD10, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2TXD3, RGMII2);
+MS_PIN_DECL_(D10, SIG_EXPR_LIST_PTR(GPIOU3), SIG_EXPR_LIST_PTR(DASHD10),
+ SIG_EXPR_LIST_PTR(RGMII2TXD3));
+
#define E11 164
SIG_EXPR_LIST_DECL_SINGLE(GPIOU4, GPIOU4, SIG_DESC_SET(SCUA0, 12));
SIG_EXPR_LIST_DECL_SINGLE(RMII1RCLK, RMII1, RMII1_DESC);
@@ -869,11 +1293,419 @@ SIG_EXPR_LIST_DECL_SINGLE(RGMII1RXD3, RGMII1);
MS_PIN_DECL_(E10, SIG_EXPR_LIST_PTR(GPIOV1), SIG_EXPR_LIST_PTR(RMII1RXER),
SIG_EXPR_LIST_PTR(RGMII1RXD3));
+#define C9 170
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV2, GPIOV2, SIG_DESC_SET(SCUA0, 18));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RCLK, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCK, RGMII2);
+MS_PIN_DECL_(C9, SIG_EXPR_LIST_PTR(GPIOV2), SIG_EXPR_LIST_PTR(RMII2RCLK),
+ SIG_EXPR_LIST_PTR(RGMII2RXCK));
+
+#define B9 171
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV3, GPIOV3, SIG_DESC_SET(SCUA0, 19));
+SIG_EXPR_LIST_DECL_SINGLE(DASHB9, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXCTL, RGMII2);
+MS_PIN_DECL_(B9, SIG_EXPR_LIST_PTR(GPIOV3), SIG_EXPR_LIST_PTR(DASHB9),
+ SIG_EXPR_LIST_PTR(RGMII2RXCTL));
+
+#define A9 172
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV4, GPIOV4, SIG_DESC_SET(SCUA0, 20));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD0, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD0, RGMII2);
+MS_PIN_DECL_(A9, SIG_EXPR_LIST_PTR(GPIOV4), SIG_EXPR_LIST_PTR(RMII2RXD0),
+ SIG_EXPR_LIST_PTR(RGMII2RXD0));
+
+#define E8 173
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV5, GPIOV5, SIG_DESC_SET(SCUA0, 21));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXD1, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD1, RGMII2);
+MS_PIN_DECL_(E8, SIG_EXPR_LIST_PTR(GPIOV5), SIG_EXPR_LIST_PTR(RMII2RXD1),
+ SIG_EXPR_LIST_PTR(RGMII2RXD1));
+
+#define D8 174
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV6, GPIOV6, SIG_DESC_SET(SCUA0, 22));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2CRSDV, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD2, RGMII2);
+MS_PIN_DECL_(D8, SIG_EXPR_LIST_PTR(GPIOV6), SIG_EXPR_LIST_PTR(RMII2CRSDV),
+ SIG_EXPR_LIST_PTR(RGMII2RXD2));
+
+#define C8 175
+SIG_EXPR_LIST_DECL_SINGLE(GPIOV7, GPIOV7, SIG_DESC_SET(SCUA0, 23));
+SIG_EXPR_LIST_DECL_SINGLE(RMII2RXER, RMII2, RMII2_DESC);
+SIG_EXPR_LIST_DECL_SINGLE(RGMII2RXD3, RGMII2);
+MS_PIN_DECL_(C8, SIG_EXPR_LIST_PTR(GPIOV7), SIG_EXPR_LIST_PTR(RMII2RXER),
+ SIG_EXPR_LIST_PTR(RGMII2RXD3));
+
FUNC_GROUP_DECL(RMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
E10);
+FUNC_GROUP_DECL(RMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
+FUNC_GROUP_DECL(RGMII2, D9, E9, A10, B10, C10, D10, C9, B9, A9, E8, D8, C8);
+
+#define L5 176
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW0, GPIOW0, SIG_DESC_SET(SCUA0, 24));
+SIG_EXPR_LIST_DECL_SINGLE(ADC0, ADC0);
+MS_PIN_DECL_(L5, SIG_EXPR_LIST_PTR(GPIOW0), SIG_EXPR_LIST_PTR(ADC0));
+FUNC_GROUP_DECL(ADC0, L5);
+
+#define L4 177
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW1, GPIOW1, SIG_DESC_SET(SCUA0, 25));
+SIG_EXPR_LIST_DECL_SINGLE(ADC1, ADC1);
+MS_PIN_DECL_(L4, SIG_EXPR_LIST_PTR(GPIOW1), SIG_EXPR_LIST_PTR(ADC1));
+FUNC_GROUP_DECL(ADC1, L4);
+
+#define L3 178
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW2, GPIOW2, SIG_DESC_SET(SCUA0, 26));
+SIG_EXPR_LIST_DECL_SINGLE(ADC2, ADC2);
+MS_PIN_DECL_(L3, SIG_EXPR_LIST_PTR(GPIOW2), SIG_EXPR_LIST_PTR(ADC2));
+FUNC_GROUP_DECL(ADC2, L3);
+
+#define L2 179
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW3, GPIOW3, SIG_DESC_SET(SCUA0, 27));
+SIG_EXPR_LIST_DECL_SINGLE(ADC3, ADC3);
+MS_PIN_DECL_(L2, SIG_EXPR_LIST_PTR(GPIOW3), SIG_EXPR_LIST_PTR(ADC3));
+FUNC_GROUP_DECL(ADC3, L2);
+
+#define L1 180
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW4, GPIOW4, SIG_DESC_SET(SCUA0, 28));
+SIG_EXPR_LIST_DECL_SINGLE(ADC4, ADC4);
+MS_PIN_DECL_(L1, SIG_EXPR_LIST_PTR(GPIOW4), SIG_EXPR_LIST_PTR(ADC4));
+FUNC_GROUP_DECL(ADC4, L1);
+
+#define M5 181
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW5, GPIOW5, SIG_DESC_SET(SCUA0, 29));
+SIG_EXPR_LIST_DECL_SINGLE(ADC5, ADC5);
+MS_PIN_DECL_(M5, SIG_EXPR_LIST_PTR(GPIOW5), SIG_EXPR_LIST_PTR(ADC5));
+FUNC_GROUP_DECL(ADC5, M5);
+
+#define M4 182
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW6, GPIOW6, SIG_DESC_SET(SCUA0, 30));
+SIG_EXPR_LIST_DECL_SINGLE(ADC6, ADC6);
+MS_PIN_DECL_(M4, SIG_EXPR_LIST_PTR(GPIOW6), SIG_EXPR_LIST_PTR(ADC6));
+FUNC_GROUP_DECL(ADC6, M4);
+
+#define M3 183
+SIG_EXPR_LIST_DECL_SINGLE(GPIOW7, GPIOW7, SIG_DESC_SET(SCUA0, 31));
+SIG_EXPR_LIST_DECL_SINGLE(ADC7, ADC7);
+MS_PIN_DECL_(M3, SIG_EXPR_LIST_PTR(GPIOW7), SIG_EXPR_LIST_PTR(ADC7));
+FUNC_GROUP_DECL(ADC7, M3);
+
+#define M2 184
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX0, GPIOX0, SIG_DESC_SET(SCUA4, 0));
+SIG_EXPR_LIST_DECL_SINGLE(ADC8, ADC8);
+MS_PIN_DECL_(M2, SIG_EXPR_LIST_PTR(GPIOX0), SIG_EXPR_LIST_PTR(ADC8));
+FUNC_GROUP_DECL(ADC8, M2);
+
+#define M1 185
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX1, GPIOX1, SIG_DESC_SET(SCUA4, 1));
+SIG_EXPR_LIST_DECL_SINGLE(ADC9, ADC9);
+MS_PIN_DECL_(M1, SIG_EXPR_LIST_PTR(GPIOX1), SIG_EXPR_LIST_PTR(ADC9));
+FUNC_GROUP_DECL(ADC9, M1);
+
+#define N5 186
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX2, GPIOX2, SIG_DESC_SET(SCUA4, 2));
+SIG_EXPR_LIST_DECL_SINGLE(ADC10, ADC10);
+MS_PIN_DECL_(N5, SIG_EXPR_LIST_PTR(GPIOX2), SIG_EXPR_LIST_PTR(ADC10));
+FUNC_GROUP_DECL(ADC10, N5);
+
+#define N4 187
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX3, GPIOX3, SIG_DESC_SET(SCUA4, 3));
+SIG_EXPR_LIST_DECL_SINGLE(ADC11, ADC11);
+MS_PIN_DECL_(N4, SIG_EXPR_LIST_PTR(GPIOX3), SIG_EXPR_LIST_PTR(ADC11));
+FUNC_GROUP_DECL(ADC11, N4);
+
+#define N3 188
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX4, GPIOX4, SIG_DESC_SET(SCUA4, 4));
+SIG_EXPR_LIST_DECL_SINGLE(ADC12, ADC12);
+MS_PIN_DECL_(N3, SIG_EXPR_LIST_PTR(GPIOX4), SIG_EXPR_LIST_PTR(ADC12));
+FUNC_GROUP_DECL(ADC12, N3);
+
+#define N2 189
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX5, GPIOX5, SIG_DESC_SET(SCUA4, 5));
+SIG_EXPR_LIST_DECL_SINGLE(ADC13, ADC13);
+MS_PIN_DECL_(N2, SIG_EXPR_LIST_PTR(GPIOX5), SIG_EXPR_LIST_PTR(ADC13));
+FUNC_GROUP_DECL(ADC13, N2);
+
+#define N1 190
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX6, GPIOX6, SIG_DESC_SET(SCUA4, 6));
+SIG_EXPR_LIST_DECL_SINGLE(ADC14, ADC14);
+MS_PIN_DECL_(N1, SIG_EXPR_LIST_PTR(GPIOX6), SIG_EXPR_LIST_PTR(ADC14));
+FUNC_GROUP_DECL(ADC14, N1);
+
+#define P5 191
+SIG_EXPR_LIST_DECL_SINGLE(GPIOX7, GPIOX7, SIG_DESC_SET(SCUA4, 7));
+SIG_EXPR_LIST_DECL_SINGLE(ADC15, ADC15);
+MS_PIN_DECL_(P5, SIG_EXPR_LIST_PTR(GPIOX7), SIG_EXPR_LIST_PTR(ADC15));
+FUNC_GROUP_DECL(ADC15, P5);
+
+#define C21 192
+SIG_EXPR_DECL(SIOS3, SIOS3, SIG_DESC_SET(SCUA4, 8));
+SIG_EXPR_DECL(SIOS3, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOS3, SIOS3, ACPI);
+SS_PIN_DECL(C21, GPIOY0, SIOS3);
+FUNC_GROUP_DECL(SIOS3, C21);
+
+#define F20 193
+SIG_EXPR_DECL(SIOS5, SIOS5, SIG_DESC_SET(SCUA4, 9));
+SIG_EXPR_DECL(SIOS5, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOS5, SIOS5, ACPI);
+SS_PIN_DECL(F20, GPIOY1, SIOS5);
+FUNC_GROUP_DECL(SIOS5, F20);
+
+#define G20 194
+SIG_EXPR_DECL(SIOPWREQ, SIOPWREQ, SIG_DESC_SET(SCUA4, 10));
+SIG_EXPR_DECL(SIOPWREQ, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOPWREQ, SIOPWREQ, ACPI);
+SS_PIN_DECL(G20, GPIOY2, SIOPWREQ);
+FUNC_GROUP_DECL(SIOPWREQ, G20);
+
+#define K20 195
+SIG_EXPR_DECL(SIOONCTRL, SIOONCTRL, SIG_DESC_SET(SCUA4, 11));
+SIG_EXPR_DECL(SIOONCTRL, ACPI, ACPI_DESC);
+SIG_EXPR_LIST_DECL_DUAL(SIOONCTRL, SIOONCTRL, ACPI);
+SS_PIN_DECL(K20, GPIOY3, SIOONCTRL);
+FUNC_GROUP_DECL(SIOONCTRL, K20);
+
+FUNC_GROUP_DECL(ACPI, B19, A20, D17, A19, C21, F20, G20, K20);
+
+#define R22 200
+#define R22_DESC SIG_DESC_SET(SCUA4, 16)
+SIG_EXPR_DECL(ROMA2, ROM8, R22_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA2, ROM16, R22_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA2, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB0, VPO12, R22_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB0, VPO24, R22_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB0, VPOOFF1, R22_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB0, SIG_EXPR_PTR(VPOB0, VPO12),
+ SIG_EXPR_PTR(VPOB0, VPO24), SIG_EXPR_PTR(VPOB0, VPOOFF1));
+MS_PIN_DECL(R22, GPIOZ0, ROMA2, VPOB0);
+
+#define P18 201
+#define P18_DESC SIG_DESC_SET(SCUA4, 17)
+SIG_EXPR_DECL(ROMA3, ROM8, P18_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA3, ROM16, P18_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA3, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB1, VPO12, P18_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB1, VPO24, P18_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB1, VPOOFF1, P18_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB1, SIG_EXPR_PTR(VPOB1, VPO12),
+ SIG_EXPR_PTR(VPOB1, VPO24), SIG_EXPR_PTR(VPOB1, VPOOFF1));
+MS_PIN_DECL(P18, GPIOZ1, ROMA3, VPOB1);
+
+#define P19 202
+#define P19_DESC SIG_DESC_SET(SCUA4, 18)
+SIG_EXPR_DECL(ROMA4, ROM8, P19_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA4, ROM16, P19_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA4, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB2, VPO12, P19_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB2, VPO24, P19_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB2, VPOOFF1, P19_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB2, SIG_EXPR_PTR(VPOB2, VPO12),
+ SIG_EXPR_PTR(VPOB2, VPO24), SIG_EXPR_PTR(VPOB2, VPOOFF1));
+MS_PIN_DECL(P19, GPIOZ2, ROMA4, VPOB2);
+
+#define P20 203
+#define P20_DESC SIG_DESC_SET(SCUA4, 19)
+SIG_EXPR_DECL(ROMA5, ROM8, P20_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA5, ROM16, P20_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA5, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB3, VPO12, P20_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB3, VPO24, P20_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB3, VPOOFF1, P20_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB3, SIG_EXPR_PTR(VPOB3, VPO12),
+ SIG_EXPR_PTR(VPOB3, VPO24), SIG_EXPR_PTR(VPOB3, VPOOFF1));
+MS_PIN_DECL(P20, GPIOZ3, ROMA5, VPOB3);
+
+#define P21 204
+#define P21_DESC SIG_DESC_SET(SCUA4, 20)
+SIG_EXPR_DECL(ROMA6, ROM8, P21_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA6, ROM16, P21_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA6, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB4, VPO12, P21_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB4, VPO24, P21_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB4, VPOOFF1, P21_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB4, SIG_EXPR_PTR(VPOB4, VPO12),
+ SIG_EXPR_PTR(VPOB4, VPO24), SIG_EXPR_PTR(VPOB4, VPOOFF1));
+MS_PIN_DECL(P21, GPIOZ4, ROMA6, VPOB4);
+
+#define P22 205
+#define P22_DESC SIG_DESC_SET(SCUA4, 21)
+SIG_EXPR_DECL(ROMA7, ROM8, P22_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA7, ROM16, P22_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA7, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB5, VPO12, P22_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB5, VPO24, P22_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB5, VPOOFF1, P22_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB5, SIG_EXPR_PTR(VPOB5, VPO12),
+ SIG_EXPR_PTR(VPOB5, VPO24), SIG_EXPR_PTR(VPOB5, VPOOFF1));
+MS_PIN_DECL(P22, GPIOZ5, ROMA7, VPOB5);
+
+#define M19 206
+#define M19_DESC SIG_DESC_SET(SCUA4, 22)
+SIG_EXPR_DECL(ROMA8, ROM8, M19_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA8, ROM16, M19_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA8, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB6, VPO12, M19_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB6, VPO24, M19_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB6, VPOOFF1, M19_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB6, SIG_EXPR_PTR(VPOB6, VPO12),
+ SIG_EXPR_PTR(VPOB6, VPO24), SIG_EXPR_PTR(VPOB6, VPOOFF1));
+MS_PIN_DECL(M19, GPIOZ6, ROMA8, VPOB6);
+
+#define M20 207
+#define M20_DESC SIG_DESC_SET(SCUA4, 23)
+SIG_EXPR_DECL(ROMA9, ROM8, M20_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA9, ROM16, M20_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA9, ROM8, ROM16);
+SIG_EXPR_DECL(VPOB7, VPO12, M20_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOB7, VPO24, M20_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOB7, VPOOFF1, M20_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOB7, SIG_EXPR_PTR(VPOB7, VPO12),
+ SIG_EXPR_PTR(VPOB7, VPO24), SIG_EXPR_PTR(VPOB7, VPOOFF1));
+MS_PIN_DECL(M20, GPIOZ7, ROMA9, VPOB7);
+
+#define M21 208
+#define M21_DESC SIG_DESC_SET(SCUA4, 24)
+SIG_EXPR_DECL(ROMA10, ROM8, M21_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA10, ROM16, M21_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA10, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG0, VPO12, M21_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOG0, VPO24, M21_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG0, VPOOFF1, M21_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOG0, SIG_EXPR_PTR(VPOG0, VPO12),
+ SIG_EXPR_PTR(VPOG0, VPO24), SIG_EXPR_PTR(VPOG0, VPOOFF1));
+MS_PIN_DECL(M21, GPIOAA0, ROMA10, VPOG0);
+
+#define M22 209
+#define M22_DESC SIG_DESC_SET(SCUA4, 25)
+SIG_EXPR_DECL(ROMA11, ROM8, M22_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA11, ROM16, M22_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA11, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG1, VPO12, M22_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOG1, VPO24, M22_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG1, VPOOFF1, M22_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOG1, SIG_EXPR_PTR(VPOG1, VPO12),
+ SIG_EXPR_PTR(VPOG1, VPO24), SIG_EXPR_PTR(VPOG1, VPOOFF1));
+MS_PIN_DECL(M22, GPIOAA1, ROMA11, VPOG1);
+
+#define L18 210
+#define L18_DESC SIG_DESC_SET(SCUA4, 26)
+SIG_EXPR_DECL(ROMA12, ROM8, L18_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA12, ROM16, L18_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA12, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG2, VPO12, L18_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOG2, VPO24, L18_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG2, VPOOFF1, L18_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOG2, SIG_EXPR_PTR(VPOG2, VPO12),
+ SIG_EXPR_PTR(VPOG2, VPO24), SIG_EXPR_PTR(VPOG2, VPOOFF1));
+MS_PIN_DECL(L18, GPIOAA2, ROMA12, VPOG2);
+
+#define L19 211
+#define L19_DESC SIG_DESC_SET(SCUA4, 27)
+SIG_EXPR_DECL(ROMA13, ROM8, L19_DESC, VPOOFF0_DESC);
+SIG_EXPR_DECL(ROMA13, ROM16, L19_DESC, VPOOFF0_DESC);
+SIG_EXPR_LIST_DECL_DUAL(ROMA13, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG3, VPO12, L19_DESC, VPO12_DESC);
+SIG_EXPR_DECL(VPOG3, VPO24, L19_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG3, VPOOFF1, L19_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL(VPOG3, SIG_EXPR_PTR(VPOG3, VPO12),
+ SIG_EXPR_PTR(VPOG3, VPO24), SIG_EXPR_PTR(VPOG3, VPOOFF1));
+MS_PIN_DECL(L19, GPIOAA3, ROMA13, VPOG3);
+
+#define L20 212
+#define L20_DESC SIG_DESC_SET(SCUA4, 28)
+SIG_EXPR_DECL(ROMA14, ROM8, L20_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA14, ROM16, L20_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA14, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG4, VPO24, L20_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG4, VPOOFF1, L20_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOG4, VPO24, VPOOFF1);
+MS_PIN_DECL(L20, GPIOAA4, ROMA14, VPOG4);
+
+#define L21 213
+#define L21_DESC SIG_DESC_SET(SCUA4, 29)
+SIG_EXPR_DECL(ROMA15, ROM8, L21_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA15, ROM16, L21_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA15, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG5, VPO24, L21_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG5, VPOOFF1, L21_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOG5, VPO24, VPOOFF1);
+MS_PIN_DECL(L21, GPIOAA5, ROMA15, VPOG5);
+
+#define T18 214
+#define T18_DESC SIG_DESC_SET(SCUA4, 30)
+SIG_EXPR_DECL(ROMA16, ROM8, T18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA16, ROM16, T18_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA16, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG6, VPO24, T18_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG6, VPOOFF1, T18_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOG6, VPO24, VPOOFF1);
+MS_PIN_DECL(T18, GPIOAA6, ROMA16, VPOG6);
+
+#define N18 215
+#define N18_DESC SIG_DESC_SET(SCUA4, 31)
+SIG_EXPR_DECL(ROMA17, ROM8, N18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA17, ROM16, N18_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA17, ROM8, ROM16);
+SIG_EXPR_DECL(VPOG7, VPO24, N18_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOG7, VPOOFF1, N18_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOG7, VPO24, VPOOFF1);
+MS_PIN_DECL(N18, GPIOAA7, ROMA17, VPOG7);
+
+#define N19 216
+#define N19_DESC SIG_DESC_SET(SCUA8, 0)
+SIG_EXPR_DECL(ROMA18, ROM8, N19_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA18, ROM16, N19_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA18, ROM8, ROM16);
+SIG_EXPR_DECL(VPOR0, VPO24, N19_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOR0, VPOOFF1, N19_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOR0, VPO24, VPOOFF1);
+MS_PIN_DECL(N19, GPIOAB0, ROMA18, VPOR0);
+
+#define M18 217
+#define M18_DESC SIG_DESC_SET(SCUA8, 1)
+SIG_EXPR_DECL(ROMA19, ROM8, M18_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA19, ROM16, M18_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA19, ROM8, ROM16);
+SIG_EXPR_DECL(VPOR1, VPO24, M18_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOR1, VPOOFF1, M18_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOR1, VPO24, VPOOFF1);
+MS_PIN_DECL(M18, GPIOAB1, ROMA19, VPOR1);
+
+#define N22 218
+#define N22_DESC SIG_DESC_SET(SCUA8, 2)
+SIG_EXPR_DECL(ROMA20, ROM8, N22_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA20, ROM16, N22_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA20, ROM8, ROM16);
+SIG_EXPR_DECL(VPOR2, VPO24, N22_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOR2, VPOOFF1, N22_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOR2, VPO24, VPOOFF1);
+MS_PIN_DECL(N22, GPIOAB2, ROMA20, VPOR2);
+
+#define N20 219
+#define N20_DESC SIG_DESC_SET(SCUA8, 3)
+SIG_EXPR_DECL(ROMA21, ROM8, N20_DESC, VPO_24_OFF);
+SIG_EXPR_DECL(ROMA21, ROM16, N20_DESC, VPO_24_OFF);
+SIG_EXPR_LIST_DECL_DUAL(ROMA21, ROM8, ROM16);
+SIG_EXPR_DECL(VPOR3, VPO24, N20_DESC, VPO24_DESC);
+SIG_EXPR_DECL(VPOR3, VPOOFF1, N20_DESC, VPOOFF1_DESC);
+SIG_EXPR_LIST_DECL_DUAL(VPOR3, VPO24, VPOOFF1);
+MS_PIN_DECL(N20, GPIOAB3, ROMA21, VPOR3);
+
+FUNC_GROUP_DECL(ROM8, V20, U21, T19, V22, U20, R18, N21, L22, K18, W21, Y22,
+ U19, R22, P18, P19, P20, P21, P22, M19, M20, M21, M22, L18,
+ L19, L20, L21, T18, N18, N19, M18, N22, N20);
+FUNC_GROUP_DECL(ROM16, V20, U21, T19, V22, U20, R18, N21, L22, K18,
+ A8, C7, B7, A7, D7, B6, A6, E7, W21, Y22, U19, R22, P18, P19,
+ P20, P21, P22, M19, M20, M21, M22, L18, L19, L20, L21, T18,
+ N18, N19, M18, N22, N20);
+FUNC_GROUP_DECL(VPO12, U21, T19, V22, U20, R22, P18, P19, P20, P21, P22, M19,
+ M20, M21, M22, L18, L19, L20, L21, T18, N18, N19, M18, N22,
+ N20);
+FUNC_GROUP_DECL(VPO24, U21, T19, V22, U20, L22, K18, V21, W22, R22, P18, P19,
+ P20, P21, P22, M19, M20, M21, M22, L18, L19);
+
/* Note we account for GPIOY4-GPIOY7 even though they're not valid, thus 216
* pins becomes 220.
*/
@@ -883,84 +1715,180 @@ FUNC_GROUP_DECL(RGMII1, A12, B12, C12, D12, E12, A13, E11, D11, C11, B11, A11,
static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(A1),
+ ASPEED_PINCTRL_PIN(A10),
ASPEED_PINCTRL_PIN(A11),
ASPEED_PINCTRL_PIN(A12),
ASPEED_PINCTRL_PIN(A13),
+ ASPEED_PINCTRL_PIN(A14),
ASPEED_PINCTRL_PIN(A15),
+ ASPEED_PINCTRL_PIN(A16),
+ ASPEED_PINCTRL_PIN(A17),
ASPEED_PINCTRL_PIN(A18),
+ ASPEED_PINCTRL_PIN(A19),
ASPEED_PINCTRL_PIN(A2),
+ ASPEED_PINCTRL_PIN(A20),
ASPEED_PINCTRL_PIN(A3),
ASPEED_PINCTRL_PIN(A4),
ASPEED_PINCTRL_PIN(A5),
ASPEED_PINCTRL_PIN(A6),
ASPEED_PINCTRL_PIN(A7),
ASPEED_PINCTRL_PIN(A8),
+ ASPEED_PINCTRL_PIN(A9),
+ ASPEED_PINCTRL_PIN(AA1),
ASPEED_PINCTRL_PIN(AA2),
ASPEED_PINCTRL_PIN(AA22),
ASPEED_PINCTRL_PIN(AA3),
+ ASPEED_PINCTRL_PIN(AA4),
+ ASPEED_PINCTRL_PIN(AA5),
+ ASPEED_PINCTRL_PIN(AA6),
ASPEED_PINCTRL_PIN(AA7),
ASPEED_PINCTRL_PIN(AB1),
ASPEED_PINCTRL_PIN(AB2),
+ ASPEED_PINCTRL_PIN(AB3),
+ ASPEED_PINCTRL_PIN(AB4),
+ ASPEED_PINCTRL_PIN(AB5),
+ ASPEED_PINCTRL_PIN(AB6),
ASPEED_PINCTRL_PIN(AB7),
ASPEED_PINCTRL_PIN(B1),
+ ASPEED_PINCTRL_PIN(B10),
ASPEED_PINCTRL_PIN(B11),
ASPEED_PINCTRL_PIN(B12),
+ ASPEED_PINCTRL_PIN(B13),
ASPEED_PINCTRL_PIN(B14),
ASPEED_PINCTRL_PIN(B15),
+ ASPEED_PINCTRL_PIN(B16),
+ ASPEED_PINCTRL_PIN(B17),
+ ASPEED_PINCTRL_PIN(B18),
ASPEED_PINCTRL_PIN(B19),
ASPEED_PINCTRL_PIN(B2),
+ ASPEED_PINCTRL_PIN(B22),
ASPEED_PINCTRL_PIN(B3),
ASPEED_PINCTRL_PIN(B4),
+ ASPEED_PINCTRL_PIN(B5),
ASPEED_PINCTRL_PIN(B6),
ASPEED_PINCTRL_PIN(B7),
+ ASPEED_PINCTRL_PIN(B9),
ASPEED_PINCTRL_PIN(C1),
+ ASPEED_PINCTRL_PIN(C10),
ASPEED_PINCTRL_PIN(C11),
ASPEED_PINCTRL_PIN(C12),
+ ASPEED_PINCTRL_PIN(C13),
ASPEED_PINCTRL_PIN(C14),
ASPEED_PINCTRL_PIN(C15),
+ ASPEED_PINCTRL_PIN(C16),
ASPEED_PINCTRL_PIN(C17),
+ ASPEED_PINCTRL_PIN(C18),
ASPEED_PINCTRL_PIN(C2),
+ ASPEED_PINCTRL_PIN(C20),
+ ASPEED_PINCTRL_PIN(C21),
+ ASPEED_PINCTRL_PIN(C22),
ASPEED_PINCTRL_PIN(C3),
ASPEED_PINCTRL_PIN(C4),
ASPEED_PINCTRL_PIN(C5),
ASPEED_PINCTRL_PIN(C6),
ASPEED_PINCTRL_PIN(C7),
+ ASPEED_PINCTRL_PIN(C8),
+ ASPEED_PINCTRL_PIN(C9),
ASPEED_PINCTRL_PIN(D1),
+ ASPEED_PINCTRL_PIN(D10),
ASPEED_PINCTRL_PIN(D11),
ASPEED_PINCTRL_PIN(D12),
+ ASPEED_PINCTRL_PIN(D13),
ASPEED_PINCTRL_PIN(D14),
ASPEED_PINCTRL_PIN(D15),
ASPEED_PINCTRL_PIN(D16),
ASPEED_PINCTRL_PIN(D17),
ASPEED_PINCTRL_PIN(D18),
+ ASPEED_PINCTRL_PIN(D19),
ASPEED_PINCTRL_PIN(D2),
ASPEED_PINCTRL_PIN(D3),
ASPEED_PINCTRL_PIN(D4),
ASPEED_PINCTRL_PIN(D5),
+ ASPEED_PINCTRL_PIN(D6),
ASPEED_PINCTRL_PIN(D7),
+ ASPEED_PINCTRL_PIN(D8),
+ ASPEED_PINCTRL_PIN(D9),
ASPEED_PINCTRL_PIN(E10),
ASPEED_PINCTRL_PIN(E11),
ASPEED_PINCTRL_PIN(E12),
+ ASPEED_PINCTRL_PIN(E13),
ASPEED_PINCTRL_PIN(E14),
+ ASPEED_PINCTRL_PIN(E15),
ASPEED_PINCTRL_PIN(E16),
+ ASPEED_PINCTRL_PIN(E18),
+ ASPEED_PINCTRL_PIN(E19),
ASPEED_PINCTRL_PIN(E2),
+ ASPEED_PINCTRL_PIN(E20),
ASPEED_PINCTRL_PIN(E3),
ASPEED_PINCTRL_PIN(E5),
+ ASPEED_PINCTRL_PIN(E6),
ASPEED_PINCTRL_PIN(E7),
+ ASPEED_PINCTRL_PIN(E8),
+ ASPEED_PINCTRL_PIN(E9),
+ ASPEED_PINCTRL_PIN(F18),
+ ASPEED_PINCTRL_PIN(F20),
ASPEED_PINCTRL_PIN(F3),
ASPEED_PINCTRL_PIN(F4),
ASPEED_PINCTRL_PIN(F5),
+ ASPEED_PINCTRL_PIN(G18),
+ ASPEED_PINCTRL_PIN(G19),
+ ASPEED_PINCTRL_PIN(G20),
ASPEED_PINCTRL_PIN(G5),
ASPEED_PINCTRL_PIN(H1),
+ ASPEED_PINCTRL_PIN(H18),
ASPEED_PINCTRL_PIN(H19),
ASPEED_PINCTRL_PIN(H2),
ASPEED_PINCTRL_PIN(H20),
+ ASPEED_PINCTRL_PIN(H3),
+ ASPEED_PINCTRL_PIN(H4),
+ ASPEED_PINCTRL_PIN(J20),
+ ASPEED_PINCTRL_PIN(J21),
ASPEED_PINCTRL_PIN(J3),
+ ASPEED_PINCTRL_PIN(J4),
+ ASPEED_PINCTRL_PIN(J5),
ASPEED_PINCTRL_PIN(K18),
+ ASPEED_PINCTRL_PIN(K20),
+ ASPEED_PINCTRL_PIN(K5),
+ ASPEED_PINCTRL_PIN(L1),
+ ASPEED_PINCTRL_PIN(L18),
+ ASPEED_PINCTRL_PIN(L19),
+ ASPEED_PINCTRL_PIN(L2),
+ ASPEED_PINCTRL_PIN(L20),
+ ASPEED_PINCTRL_PIN(L21),
ASPEED_PINCTRL_PIN(L22),
+ ASPEED_PINCTRL_PIN(L3),
+ ASPEED_PINCTRL_PIN(L4),
+ ASPEED_PINCTRL_PIN(L5),
+ ASPEED_PINCTRL_PIN(M1),
+ ASPEED_PINCTRL_PIN(M18),
+ ASPEED_PINCTRL_PIN(M19),
+ ASPEED_PINCTRL_PIN(M2),
+ ASPEED_PINCTRL_PIN(M20),
+ ASPEED_PINCTRL_PIN(M21),
+ ASPEED_PINCTRL_PIN(M22),
+ ASPEED_PINCTRL_PIN(M3),
+ ASPEED_PINCTRL_PIN(M4),
+ ASPEED_PINCTRL_PIN(M5),
+ ASPEED_PINCTRL_PIN(N1),
+ ASPEED_PINCTRL_PIN(N18),
+ ASPEED_PINCTRL_PIN(N19),
+ ASPEED_PINCTRL_PIN(N2),
+ ASPEED_PINCTRL_PIN(N20),
ASPEED_PINCTRL_PIN(N21),
+ ASPEED_PINCTRL_PIN(N22),
+ ASPEED_PINCTRL_PIN(N3),
+ ASPEED_PINCTRL_PIN(N4),
+ ASPEED_PINCTRL_PIN(N5),
+ ASPEED_PINCTRL_PIN(P18),
+ ASPEED_PINCTRL_PIN(P19),
+ ASPEED_PINCTRL_PIN(P20),
+ ASPEED_PINCTRL_PIN(P21),
+ ASPEED_PINCTRL_PIN(P22),
+ ASPEED_PINCTRL_PIN(P5),
ASPEED_PINCTRL_PIN(R18),
+ ASPEED_PINCTRL_PIN(R22),
ASPEED_PINCTRL_PIN(T1),
+ ASPEED_PINCTRL_PIN(T18),
ASPEED_PINCTRL_PIN(T19),
ASPEED_PINCTRL_PIN(T2),
ASPEED_PINCTRL_PIN(T4),
@@ -979,28 +1907,61 @@ static struct pinctrl_pin_desc aspeed_g4_pins[ASPEED_G4_NR_PINS] = {
ASPEED_PINCTRL_PIN(V20),
ASPEED_PINCTRL_PIN(V21),
ASPEED_PINCTRL_PIN(V22),
+ ASPEED_PINCTRL_PIN(V3),
+ ASPEED_PINCTRL_PIN(V4),
+ ASPEED_PINCTRL_PIN(V5),
ASPEED_PINCTRL_PIN(V6),
+ ASPEED_PINCTRL_PIN(V7),
ASPEED_PINCTRL_PIN(W1),
+ ASPEED_PINCTRL_PIN(W2),
ASPEED_PINCTRL_PIN(W21),
ASPEED_PINCTRL_PIN(W22),
+ ASPEED_PINCTRL_PIN(W3),
ASPEED_PINCTRL_PIN(W4),
ASPEED_PINCTRL_PIN(W5),
+ ASPEED_PINCTRL_PIN(W6),
+ ASPEED_PINCTRL_PIN(W7),
+ ASPEED_PINCTRL_PIN(Y1),
+ ASPEED_PINCTRL_PIN(Y2),
+ ASPEED_PINCTRL_PIN(Y21),
ASPEED_PINCTRL_PIN(Y22),
ASPEED_PINCTRL_PIN(Y3),
ASPEED_PINCTRL_PIN(Y4),
ASPEED_PINCTRL_PIN(Y5),
+ ASPEED_PINCTRL_PIN(Y6),
ASPEED_PINCTRL_PIN(Y7),
};
static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(ACPI),
+ ASPEED_PINCTRL_GROUP(ADC0),
+ ASPEED_PINCTRL_GROUP(ADC1),
+ ASPEED_PINCTRL_GROUP(ADC10),
+ ASPEED_PINCTRL_GROUP(ADC11),
+ ASPEED_PINCTRL_GROUP(ADC12),
+ ASPEED_PINCTRL_GROUP(ADC13),
+ ASPEED_PINCTRL_GROUP(ADC14),
+ ASPEED_PINCTRL_GROUP(ADC15),
+ ASPEED_PINCTRL_GROUP(ADC2),
+ ASPEED_PINCTRL_GROUP(ADC3),
+ ASPEED_PINCTRL_GROUP(ADC4),
+ ASPEED_PINCTRL_GROUP(ADC5),
+ ASPEED_PINCTRL_GROUP(ADC6),
+ ASPEED_PINCTRL_GROUP(ADC7),
+ ASPEED_PINCTRL_GROUP(ADC8),
+ ASPEED_PINCTRL_GROUP(ADC9),
ASPEED_PINCTRL_GROUP(BMCINT),
ASPEED_PINCTRL_GROUP(DDCCLK),
ASPEED_PINCTRL_GROUP(DDCDAT),
+ ASPEED_PINCTRL_GROUP(EXTRST),
ASPEED_PINCTRL_GROUP(FLACK),
ASPEED_PINCTRL_GROUP(FLBUSY),
ASPEED_PINCTRL_GROUP(FLWP),
+ ASPEED_PINCTRL_GROUP(GPID),
ASPEED_PINCTRL_GROUP(GPID0),
+ ASPEED_PINCTRL_GROUP(GPID2),
+ ASPEED_PINCTRL_GROUP(GPID4),
+ ASPEED_PINCTRL_GROUP(GPID6),
ASPEED_PINCTRL_GROUP(GPIE0),
ASPEED_PINCTRL_GROUP(GPIE2),
ASPEED_PINCTRL_GROUP(GPIE4),
@@ -1009,6 +1970,7 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(I2C11),
ASPEED_PINCTRL_GROUP(I2C12),
ASPEED_PINCTRL_GROUP(I2C13),
+ ASPEED_PINCTRL_GROUP(I2C14),
ASPEED_PINCTRL_GROUP(I2C3),
ASPEED_PINCTRL_GROUP(I2C4),
ASPEED_PINCTRL_GROUP(I2C5),
@@ -1018,25 +1980,37 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(I2C9),
ASPEED_PINCTRL_GROUP(LPCPD),
ASPEED_PINCTRL_GROUP(LPCPME),
- ASPEED_PINCTRL_GROUP(LPCPME),
+ ASPEED_PINCTRL_GROUP(LPCRST),
ASPEED_PINCTRL_GROUP(LPCSMI),
+ ASPEED_PINCTRL_GROUP(MAC1LINK),
+ ASPEED_PINCTRL_GROUP(MAC2LINK),
ASPEED_PINCTRL_GROUP(MDIO1),
ASPEED_PINCTRL_GROUP(MDIO2),
ASPEED_PINCTRL_GROUP(NCTS1),
+ ASPEED_PINCTRL_GROUP(NCTS2),
ASPEED_PINCTRL_GROUP(NCTS3),
ASPEED_PINCTRL_GROUP(NCTS4),
ASPEED_PINCTRL_GROUP(NDCD1),
+ ASPEED_PINCTRL_GROUP(NDCD2),
ASPEED_PINCTRL_GROUP(NDCD3),
ASPEED_PINCTRL_GROUP(NDCD4),
ASPEED_PINCTRL_GROUP(NDSR1),
+ ASPEED_PINCTRL_GROUP(NDSR2),
ASPEED_PINCTRL_GROUP(NDSR3),
+ ASPEED_PINCTRL_GROUP(NDSR4),
ASPEED_PINCTRL_GROUP(NDTR1),
+ ASPEED_PINCTRL_GROUP(NDTR2),
ASPEED_PINCTRL_GROUP(NDTR3),
+ ASPEED_PINCTRL_GROUP(NDTR4),
+ ASPEED_PINCTRL_GROUP(NDTS4),
ASPEED_PINCTRL_GROUP(NRI1),
+ ASPEED_PINCTRL_GROUP(NRI2),
ASPEED_PINCTRL_GROUP(NRI3),
ASPEED_PINCTRL_GROUP(NRI4),
ASPEED_PINCTRL_GROUP(NRTS1),
+ ASPEED_PINCTRL_GROUP(NRTS2),
ASPEED_PINCTRL_GROUP(NRTS3),
+ ASPEED_PINCTRL_GROUP(OSCCLK),
ASPEED_PINCTRL_GROUP(PWM0),
ASPEED_PINCTRL_GROUP(PWM1),
ASPEED_PINCTRL_GROUP(PWM2),
@@ -1046,7 +2020,9 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(PWM6),
ASPEED_PINCTRL_GROUP(PWM7),
ASPEED_PINCTRL_GROUP(RGMII1),
+ ASPEED_PINCTRL_GROUP(RGMII2),
ASPEED_PINCTRL_GROUP(RMII1),
+ ASPEED_PINCTRL_GROUP(RMII2),
ASPEED_PINCTRL_GROUP(ROM16),
ASPEED_PINCTRL_GROUP(ROM8),
ASPEED_PINCTRL_GROUP(ROMCS1),
@@ -1054,21 +2030,48 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(ROMCS3),
ASPEED_PINCTRL_GROUP(ROMCS4),
ASPEED_PINCTRL_GROUP(RXD1),
+ ASPEED_PINCTRL_GROUP(RXD2),
ASPEED_PINCTRL_GROUP(RXD3),
ASPEED_PINCTRL_GROUP(RXD4),
+ ASPEED_PINCTRL_GROUP(SALT1),
+ ASPEED_PINCTRL_GROUP(SALT2),
+ ASPEED_PINCTRL_GROUP(SALT3),
+ ASPEED_PINCTRL_GROUP(SALT4),
ASPEED_PINCTRL_GROUP(SD1),
+ ASPEED_PINCTRL_GROUP(SD2),
+ ASPEED_PINCTRL_GROUP(SGPMCK),
ASPEED_PINCTRL_GROUP(SGPMI),
+ ASPEED_PINCTRL_GROUP(SGPMLD),
+ ASPEED_PINCTRL_GROUP(SGPMO),
+ ASPEED_PINCTRL_GROUP(SGPSCK),
+ ASPEED_PINCTRL_GROUP(SGPSI0),
+ ASPEED_PINCTRL_GROUP(SGPSI1),
+ ASPEED_PINCTRL_GROUP(SGPSLD),
+ ASPEED_PINCTRL_GROUP(SIOONCTRL),
ASPEED_PINCTRL_GROUP(SIOPBI),
ASPEED_PINCTRL_GROUP(SIOPBO),
+ ASPEED_PINCTRL_GROUP(SIOPWREQ),
+ ASPEED_PINCTRL_GROUP(SIOPWRGD),
+ ASPEED_PINCTRL_GROUP(SIOS3),
+ ASPEED_PINCTRL_GROUP(SIOS5),
+ ASPEED_PINCTRL_GROUP(SIOSCI),
+ ASPEED_PINCTRL_GROUP(SPI1),
+ ASPEED_PINCTRL_GROUP(SPI1DEBUG),
+ ASPEED_PINCTRL_GROUP(SPI1PASSTHRU),
+ ASPEED_PINCTRL_GROUP(SPICS1),
ASPEED_PINCTRL_GROUP(TIMER3),
+ ASPEED_PINCTRL_GROUP(TIMER4),
ASPEED_PINCTRL_GROUP(TIMER5),
ASPEED_PINCTRL_GROUP(TIMER6),
ASPEED_PINCTRL_GROUP(TIMER7),
ASPEED_PINCTRL_GROUP(TIMER8),
ASPEED_PINCTRL_GROUP(TXD1),
+ ASPEED_PINCTRL_GROUP(TXD2),
ASPEED_PINCTRL_GROUP(TXD3),
ASPEED_PINCTRL_GROUP(TXD4),
ASPEED_PINCTRL_GROUP(UART6),
+ ASPEED_PINCTRL_GROUP(USBCKI),
+ ASPEED_PINCTRL_GROUP(VGABIOS_ROM),
ASPEED_PINCTRL_GROUP(VGAHS),
ASPEED_PINCTRL_GROUP(VGAVS),
ASPEED_PINCTRL_GROUP(VPI18),
@@ -1076,17 +2079,40 @@ static const struct aspeed_pin_group aspeed_g4_groups[] = {
ASPEED_PINCTRL_GROUP(VPI30),
ASPEED_PINCTRL_GROUP(VPO12),
ASPEED_PINCTRL_GROUP(VPO24),
+ ASPEED_PINCTRL_GROUP(WDTRST1),
+ ASPEED_PINCTRL_GROUP(WDTRST2),
};
static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(ACPI),
+ ASPEED_PINCTRL_FUNC(ADC0),
+ ASPEED_PINCTRL_FUNC(ADC1),
+ ASPEED_PINCTRL_FUNC(ADC10),
+ ASPEED_PINCTRL_FUNC(ADC11),
+ ASPEED_PINCTRL_FUNC(ADC12),
+ ASPEED_PINCTRL_FUNC(ADC13),
+ ASPEED_PINCTRL_FUNC(ADC14),
+ ASPEED_PINCTRL_FUNC(ADC15),
+ ASPEED_PINCTRL_FUNC(ADC2),
+ ASPEED_PINCTRL_FUNC(ADC3),
+ ASPEED_PINCTRL_FUNC(ADC4),
+ ASPEED_PINCTRL_FUNC(ADC5),
+ ASPEED_PINCTRL_FUNC(ADC6),
+ ASPEED_PINCTRL_FUNC(ADC7),
+ ASPEED_PINCTRL_FUNC(ADC8),
+ ASPEED_PINCTRL_FUNC(ADC9),
ASPEED_PINCTRL_FUNC(BMCINT),
ASPEED_PINCTRL_FUNC(DDCCLK),
ASPEED_PINCTRL_FUNC(DDCDAT),
+ ASPEED_PINCTRL_FUNC(EXTRST),
ASPEED_PINCTRL_FUNC(FLACK),
ASPEED_PINCTRL_FUNC(FLBUSY),
ASPEED_PINCTRL_FUNC(FLWP),
+ ASPEED_PINCTRL_FUNC(GPID),
ASPEED_PINCTRL_FUNC(GPID0),
+ ASPEED_PINCTRL_FUNC(GPID2),
+ ASPEED_PINCTRL_FUNC(GPID4),
+ ASPEED_PINCTRL_FUNC(GPID6),
ASPEED_PINCTRL_FUNC(GPIE0),
ASPEED_PINCTRL_FUNC(GPIE2),
ASPEED_PINCTRL_FUNC(GPIE4),
@@ -1095,6 +2121,7 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(I2C11),
ASPEED_PINCTRL_FUNC(I2C12),
ASPEED_PINCTRL_FUNC(I2C13),
+ ASPEED_PINCTRL_FUNC(I2C14),
ASPEED_PINCTRL_FUNC(I2C3),
ASPEED_PINCTRL_FUNC(I2C4),
ASPEED_PINCTRL_FUNC(I2C5),
@@ -1104,24 +2131,37 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(I2C9),
ASPEED_PINCTRL_FUNC(LPCPD),
ASPEED_PINCTRL_FUNC(LPCPME),
+ ASPEED_PINCTRL_FUNC(LPCRST),
ASPEED_PINCTRL_FUNC(LPCSMI),
+ ASPEED_PINCTRL_FUNC(MAC1LINK),
+ ASPEED_PINCTRL_FUNC(MAC2LINK),
ASPEED_PINCTRL_FUNC(MDIO1),
ASPEED_PINCTRL_FUNC(MDIO2),
ASPEED_PINCTRL_FUNC(NCTS1),
+ ASPEED_PINCTRL_FUNC(NCTS2),
ASPEED_PINCTRL_FUNC(NCTS3),
ASPEED_PINCTRL_FUNC(NCTS4),
ASPEED_PINCTRL_FUNC(NDCD1),
+ ASPEED_PINCTRL_FUNC(NDCD2),
ASPEED_PINCTRL_FUNC(NDCD3),
ASPEED_PINCTRL_FUNC(NDCD4),
ASPEED_PINCTRL_FUNC(NDSR1),
+ ASPEED_PINCTRL_FUNC(NDSR2),
ASPEED_PINCTRL_FUNC(NDSR3),
+ ASPEED_PINCTRL_FUNC(NDSR4),
ASPEED_PINCTRL_FUNC(NDTR1),
+ ASPEED_PINCTRL_FUNC(NDTR2),
ASPEED_PINCTRL_FUNC(NDTR3),
+ ASPEED_PINCTRL_FUNC(NDTR4),
+ ASPEED_PINCTRL_FUNC(NDTS4),
ASPEED_PINCTRL_FUNC(NRI1),
+ ASPEED_PINCTRL_FUNC(NRI2),
ASPEED_PINCTRL_FUNC(NRI3),
ASPEED_PINCTRL_FUNC(NRI4),
ASPEED_PINCTRL_FUNC(NRTS1),
+ ASPEED_PINCTRL_FUNC(NRTS2),
ASPEED_PINCTRL_FUNC(NRTS3),
+ ASPEED_PINCTRL_FUNC(OSCCLK),
ASPEED_PINCTRL_FUNC(PWM0),
ASPEED_PINCTRL_FUNC(PWM1),
ASPEED_PINCTRL_FUNC(PWM2),
@@ -1131,7 +2171,9 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(PWM6),
ASPEED_PINCTRL_FUNC(PWM7),
ASPEED_PINCTRL_FUNC(RGMII1),
+ ASPEED_PINCTRL_FUNC(RGMII2),
ASPEED_PINCTRL_FUNC(RMII1),
+ ASPEED_PINCTRL_FUNC(RMII2),
ASPEED_PINCTRL_FUNC(ROM16),
ASPEED_PINCTRL_FUNC(ROM8),
ASPEED_PINCTRL_FUNC(ROMCS1),
@@ -1139,21 +2181,48 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(ROMCS3),
ASPEED_PINCTRL_FUNC(ROMCS4),
ASPEED_PINCTRL_FUNC(RXD1),
+ ASPEED_PINCTRL_FUNC(RXD2),
ASPEED_PINCTRL_FUNC(RXD3),
ASPEED_PINCTRL_FUNC(RXD4),
+ ASPEED_PINCTRL_FUNC(SALT1),
+ ASPEED_PINCTRL_FUNC(SALT2),
+ ASPEED_PINCTRL_FUNC(SALT3),
+ ASPEED_PINCTRL_FUNC(SALT4),
ASPEED_PINCTRL_FUNC(SD1),
+ ASPEED_PINCTRL_FUNC(SD2),
+ ASPEED_PINCTRL_FUNC(SGPMCK),
ASPEED_PINCTRL_FUNC(SGPMI),
+ ASPEED_PINCTRL_FUNC(SGPMLD),
+ ASPEED_PINCTRL_FUNC(SGPMO),
+ ASPEED_PINCTRL_FUNC(SGPSCK),
+ ASPEED_PINCTRL_FUNC(SGPSI0),
+ ASPEED_PINCTRL_FUNC(SGPSI1),
+ ASPEED_PINCTRL_FUNC(SGPSLD),
+ ASPEED_PINCTRL_FUNC(SIOONCTRL),
ASPEED_PINCTRL_FUNC(SIOPBI),
ASPEED_PINCTRL_FUNC(SIOPBO),
+ ASPEED_PINCTRL_FUNC(SIOPWREQ),
+ ASPEED_PINCTRL_FUNC(SIOPWRGD),
+ ASPEED_PINCTRL_FUNC(SIOS3),
+ ASPEED_PINCTRL_FUNC(SIOS5),
+ ASPEED_PINCTRL_FUNC(SIOSCI),
+ ASPEED_PINCTRL_FUNC(SPI1),
+ ASPEED_PINCTRL_FUNC(SPI1DEBUG),
+ ASPEED_PINCTRL_FUNC(SPI1PASSTHRU),
+ ASPEED_PINCTRL_FUNC(SPICS1),
ASPEED_PINCTRL_FUNC(TIMER3),
+ ASPEED_PINCTRL_FUNC(TIMER4),
ASPEED_PINCTRL_FUNC(TIMER5),
ASPEED_PINCTRL_FUNC(TIMER6),
ASPEED_PINCTRL_FUNC(TIMER7),
ASPEED_PINCTRL_FUNC(TIMER8),
ASPEED_PINCTRL_FUNC(TXD1),
+ ASPEED_PINCTRL_FUNC(TXD2),
ASPEED_PINCTRL_FUNC(TXD3),
ASPEED_PINCTRL_FUNC(TXD4),
ASPEED_PINCTRL_FUNC(UART6),
+ ASPEED_PINCTRL_FUNC(USBCKI),
+ ASPEED_PINCTRL_FUNC(VGABIOS_ROM),
ASPEED_PINCTRL_FUNC(VGAHS),
ASPEED_PINCTRL_FUNC(VGAVS),
ASPEED_PINCTRL_FUNC(VPI18),
@@ -1161,6 +2230,8 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = {
ASPEED_PINCTRL_FUNC(VPI30),
ASPEED_PINCTRL_FUNC(VPO12),
ASPEED_PINCTRL_FUNC(VPO24),
+ ASPEED_PINCTRL_FUNC(WDTRST1),
+ ASPEED_PINCTRL_FUNC(WDTRST2),
};
static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = {
--
2.7.4
^ permalink raw reply related
* [PATCH v2 4/6] pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers
From: Andrew Jeffery @ 2016-11-02 14:37 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andrew Jeffery
In-Reply-To: <1478097481-14895-1-git-send-email-andrew-zrmu5oMJ5Fs@public.gmane.org>
The System Control Unit IP block in the Aspeed SoCs is typically where
the pinmux configuration is found, but not always. A number of pins
depend on state in one of LPC Host Control (LPCHC) or SoC Display
Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
means to adjust these as necessary.
We use syscon to cast a regmap over the GFX and LPCHCR blocks, which is
used as an arbitration layer between the relevant driver and the pinctrl
subsystem. The regmaps are then exposed to the SoC-specific pinctrl
drivers by phandles in the devicetree, and are selected during a mux
request by querying a new 'ip' member in struct aspeed_sig_desc.
Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
---
Since v1:
The change is now proactive: instead of reporting that we need to flip bits in
controllers we can't access, the patch provides access via regmaps for the
relevant controllers. The implementation also splits out the IP block ID into
its own variable rather than packing the value into the upper bits of the reg
member of struct aspeed_sig_desc. This drives some churn in the diff, but I've
tried to minimise it.
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 50 +++++++++++++---
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +++---
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 39 ++++++++++---
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 66 +++++++++++++---------
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++++++++---
5 files changed, 144 insertions(+), 61 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
index 2ad18c4ea55c..115b0cce6c1c 100644
--- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
+++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
@@ -4,12 +4,19 @@ Aspeed Pin Controllers
The Aspeed SoCs vary in functionality inside a generation but have a common mux
device register layout.
-Required properties:
-- compatible : Should be any one of the following:
- "aspeed,ast2400-pinctrl"
- "aspeed,g4-pinctrl"
- "aspeed,ast2500-pinctrl"
- "aspeed,g5-pinctrl"
+Required properties for g4:
+- compatible : Should be any one of the following:
+ "aspeed,ast2400-pinctrl"
+ "aspeed,g4-pinctrl"
+
+Required properties for g5:
+- compatible : Should be any one of the following:
+ "aspeed,ast2500-pinctrl"
+ "aspeed,g5-pinctrl"
+
+- aspeed,external-nodes: A cell of phandles to external controller nodes:
+ 0: compatible with "aspeed,ast2500-gfx", "syscon"
+ 1: compatible with "aspeed,ast2500-lpchc", "syscon"
The pin controller node should be a child of a syscon node with the required
property:
@@ -47,7 +54,7 @@ RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
TIMER7 TIMER8 VGABIOSROM
-Examples:
+g4 Example:
syscon: scu@1e6e2000 {
compatible = "syscon", "simple-mfd";
@@ -63,5 +70,34 @@ syscon: scu@1e6e2000 {
};
};
+g5 Example:
+
+apb {
+ gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+ };
+
+ lpchc: lpchc@1e7890a0 {
+ compatible = "aspeed,ast2500-lpchc", "syscon";
+ reg = <0x1e7890a0 0xc4>;
+ };
+
+ syscon: scu@1e6e2000 {
+ compatible = "syscon", "simple-mfd";
+ reg = <0x1e6e2000 0x1a8>;
+
+ pinctrl: pinctrl {
+ compatible = "aspeed,g5-pinctrl";
+ aspeed,external-nodes = <&gfx, &lpchc>;
+
+ pinctrl_i2c3_default: i2c3_default {
+ function = "I2C3";
+ groups = "I2C3";
+ };
+ };
+ };
+};
+
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
index a21b071ff290..558bd102416c 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
@@ -292,7 +292,7 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
#define UART6_DESC SIG_DESC_SET(SCU90, 7)
#define ROM16_DESC SIG_DESC_SET(SCU90, 6)
#define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
-#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 }
+#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
#define A8 56
SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC);
@@ -418,9 +418,9 @@ FUNC_GROUP_DECL(I2C8, G5, F3);
#define U1 88
SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
-#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 }
-#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
-#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 }
+#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
+#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
+#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
#define T5 89
#define T5_DESC SIG_DESC_SET(SCU84, 17)
@@ -641,11 +641,11 @@ SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26));
#define U19 139
SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27));
-#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 }
-#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 }
-#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 }
-#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 }
-#define VPO_OFF_12 { SCU94, 0x2, 0, 0 }
+#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
+#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
+#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
+#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
+#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }
#define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
#define V21 140
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index 87b46390b695..99c4fa9bf861 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -10,6 +10,7 @@
#include <linux/init.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
#include <linux/mutex.h>
#include <linux/of.h>
#include <linux/platform_device.h>
@@ -26,8 +27,8 @@
#define ASPEED_G5_NR_PINS 228
-#define COND1 { SCU90, BIT(6), 0, 0 }
-#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
+#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
+#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
#define B14 0
SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
@@ -186,9 +187,12 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
FUNC_GROUP_DECL(GPIE0, B20, C20);
-#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
-#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
-#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
+#define SPI1_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
+#define SPI1DEBUG_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
+#define SPI1PASSTHRU_DESC \
+ { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
#define C18 64
SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
@@ -325,10 +329,11 @@ SS_PIN_DECL(R1, GPIOK7, SDA8);
FUNC_GROUP_DECL(I2C8, P2, R1);
-#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
-#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
-#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
-#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
+#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
+#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
+#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
+#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
+
#define V2 104
#define V2_DESC SIG_DESC_SET(SCU88, 0)
@@ -848,10 +853,26 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
{
int i;
+ struct regmap **map;
+ struct device_node *node;
for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
aspeed_g5_pins[i].number = i;
+ map = &aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX];
+ node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0);
+ *map = syscon_node_to_regmap(node);
+ of_node_put(node);
+ if (IS_ERR(*map))
+ return PTR_ERR(*map);
+
+ map = &aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPCHC];
+ node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
+ *map = syscon_node_to_regmap(node);
+ of_node_put(node);
+ if (IS_ERR(*map))
+ return PTR_ERR(*map);
+
return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
&aspeed_g5_pinctrl_data);
}
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
index 49aeba912531..23586aac7a5a 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
@@ -14,6 +14,12 @@
#include "../core.h"
#include "pinctrl-aspeed.h"
+static const char *const aspeed_pinmux_ips[] = {
+ [ASPEED_IP_SCU] = "SCU",
+ [ASPEED_IP_GFX] = "GFX",
+ [ASPEED_IP_LPCHC] = "LHCR",
+};
+
int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
{
struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
@@ -78,7 +84,8 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
static inline void aspeed_sig_desc_print_val(
const struct aspeed_sig_desc *desc, bool enable, u32 rv)
{
- pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
+ pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
+ aspeed_pinmux_ips[desc->ip], desc->reg,
desc->mask, enable ? desc->enable : desc->disable,
(rv & desc->mask) >> __ffs(desc->mask), rv);
}
@@ -88,7 +95,7 @@ static inline void aspeed_sig_desc_print_val(
*
* @desc: The signal descriptor of interest
* @enabled: True to query the enabled state, false to query disabled state
- * @regmap: The SCU regmap instance
+ * @regmap: The IP block's regmap instance
*
* @return True if the descriptor's bitfield is configured to the state
* selected by @enabled, false otherwise
@@ -119,7 +126,7 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
*
* @expr: An expression controlling the signal for a mux function on a pin
* @enabled: True to query the enabled state, false to query disabled state
- * @regmap: The SCU regmap instance
+ * @maps: The list of regmap instances
*
* @return True if the expression composed by @enabled evaluates true, false
* otherwise
@@ -136,15 +143,16 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
* either condition as required.
*/
static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
- bool enabled, struct regmap *map)
+ bool enabled, struct regmap * const *maps)
{
int i;
for (i = 0; i < expr->ndescs; i++) {
const struct aspeed_sig_desc *desc = &expr->descs[i];
- if (!aspeed_sig_desc_eval(desc, enabled, map))
+ if (!aspeed_sig_desc_eval(desc, enabled, maps[desc->ip]))
return false;
+
}
return true;
@@ -158,12 +166,12 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
* configured
* @enable: true to enable an function's signal through a pin's signal
* expression, false to disable the function's signal
- * @map: The SCU's regmap instance for pinmux register access.
+ * @maps: The list of regmap instances for pinmux register access.
*
* @return true if the expression is configured as requested, false otherwise
*/
static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
- bool enable, struct regmap *map)
+ bool enable, struct regmap * const *maps)
{
int i;
@@ -171,6 +179,7 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
bool ret;
const struct aspeed_sig_desc *desc = &expr->descs[i];
u32 pattern = enable ? desc->enable : desc->disable;
+ u32 val = (pattern << __ffs(desc->mask));
/*
* Strap registers are configured in hardware or by early-boot
@@ -179,48 +188,49 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
* deconfigured and is the reason we re-evaluate after writing
* all descriptor bits.
*/
- if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2)
+ if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) &&
+ desc->ip == ASPEED_IP_SCU)
continue;
- ret = regmap_update_bits(map, desc->reg, desc->mask,
- pattern << __ffs(desc->mask)) == 0;
+ ret = regmap_update_bits(maps[desc->ip], desc->reg,
+ desc->mask, val) == 0;
if (!ret)
return ret;
}
- return aspeed_sig_expr_eval(expr, enable, map);
+ return aspeed_sig_expr_eval(expr, enable, maps);
}
static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
- struct regmap *map)
+ struct regmap * const *maps)
{
- if (aspeed_sig_expr_eval(expr, true, map))
+ if (aspeed_sig_expr_eval(expr, true, maps))
return true;
- return aspeed_sig_expr_set(expr, true, map);
+ return aspeed_sig_expr_set(expr, true, maps);
}
static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
- struct regmap *map)
+ struct regmap * const *maps)
{
- if (!aspeed_sig_expr_eval(expr, true, map))
+ if (!aspeed_sig_expr_eval(expr, true, maps))
return true;
- return aspeed_sig_expr_set(expr, false, map);
+ return aspeed_sig_expr_set(expr, false, maps);
}
/**
* Disable a signal on a pin by disabling all provided signal expressions.
*
* @exprs: The list of signal expressions (from a priority level on a pin)
- * @map: The SCU's regmap instance for pinmux register access.
+ * @maps: The list of regmap instances for pinmux register access.
*
* @return true if all expressions in the list are successfully disabled, false
* otherwise
*/
static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
- struct regmap *map)
+ struct regmap * const *maps)
{
bool disabled = true;
@@ -230,7 +240,7 @@ static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
while (*exprs) {
bool ret;
- ret = aspeed_sig_expr_disable(*exprs, map);
+ ret = aspeed_sig_expr_disable(*exprs, maps);
disabled = disabled && ret;
exprs++;
@@ -343,6 +353,8 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
const struct aspeed_sig_expr **funcs;
const struct aspeed_sig_expr ***prios;
+ pr_debug("Muxing pin %d for %s\n", pin, pfunc->name);
+
if (!pdesc)
return -EINVAL;
@@ -358,7 +370,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
if (expr)
break;
- if (!aspeed_disable_sig(funcs, pdata->map))
+ if (!aspeed_disable_sig(funcs, pdata->maps))
return -EPERM;
prios++;
@@ -377,7 +389,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
return -ENXIO;
}
- if (!aspeed_sig_expr_enable(expr, pdata->map))
+ if (!aspeed_sig_expr_enable(expr, pdata->maps))
return -EPERM;
}
@@ -432,7 +444,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
if (aspeed_gpio_in_exprs(funcs))
break;
- if (!aspeed_disable_sig(funcs, pdata->map))
+ if (!aspeed_disable_sig(funcs, pdata->maps))
return -EPERM;
prios++;
@@ -462,7 +474,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
* If GPIO is not the lowest priority signal type, assume there is only
* one expression defined to enable the GPIO function
*/
- if (!aspeed_sig_expr_enable(expr, pdata->map))
+ if (!aspeed_sig_expr_enable(expr, pdata->maps))
return -EPERM;
return 0;
@@ -481,10 +493,10 @@ int aspeed_pinctrl_probe(struct platform_device *pdev,
return -ENODEV;
}
- pdata->map = syscon_node_to_regmap(parent->of_node);
- if (IS_ERR(pdata->map)) {
+ pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node);
+ if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) {
dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
- return PTR_ERR(pdata->map);
+ return PTR_ERR(pdata->maps[ASPEED_IP_SCU]);
}
pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
index 3e72ef8c54bf..727728b86c07 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
@@ -232,6 +232,11 @@
* group.
*/
+#define ASPEED_IP_SCU 0
+#define ASPEED_IP_GFX 1
+#define ASPEED_IP_LPCHC 2
+#define ASPEED_NR_PINMUX_IPS 3
+
/*
* The "Multi-function Pins Mapping and Control" table in the SoC datasheet
* references registers by the device/offset mnemonic. The register macros
@@ -261,7 +266,9 @@
* A signal descriptor, which describes the register, bits and the
* enable/disable values that should be compared or written.
*
- * @reg: The register offset from base in bytes
+ * @ip: The IP block identifier, used as an index into the regmap array in
+ * struct aspeed_pinctrl_data
+ * @reg: The register offset with respect to the base address of the IP block
* @mask: The mask to apply to the register. The lowest set bit of the mask is
* used to derive the shift value.
* @enable: The value that enables the function. Value should be in the LSBs,
@@ -270,6 +277,7 @@
* LSBs, not at the position of the mask.
*/
struct aspeed_sig_desc {
+ unsigned int ip;
unsigned int reg;
u32 mask;
u32 enable;
@@ -313,24 +321,30 @@ struct aspeed_pin_desc {
/* Macro hell */
+#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
+ { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
+
/**
- * Short-hand macro for describing a configuration enabled by the state of one
- * bit. The disable value is derived.
+ * Short-hand macro for describing an SCU descriptor enabled by the state of
+ * one bit. The disable value is derived.
*
* @reg: The signal's associated register, offset from base
* @idx: The signal's bit index in the register
* @val: The value (0 or 1) that enables the function
*/
#define SIG_DESC_BIT(reg, idx, val) \
- { reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
+ SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
+
+#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
/**
- * A further short-hand macro describing a configuration enabled with a set bit.
+ * A further short-hand macro expanding to an SCU descriptor enabled by a set
+ * bit.
*
- * @reg: The configuration's associated register, offset from base
- * @idx: The configuration's bit index in the register
+ * @reg: The register, offset from base
+ * @idx: The bit index in the register
*/
-#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1)
+#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
#define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
#define SIG_DESC_LIST_DECL(sig, func, ...) \
@@ -500,7 +514,7 @@ struct aspeed_pin_desc {
MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
struct aspeed_pinctrl_data {
- struct regmap *map;
+ struct regmap *maps[ASPEED_NR_PINMUX_IPS];
const struct pinctrl_pin_desc *pins;
const unsigned int npins;
--
2.7.4
--
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^ permalink raw reply related
* [PATCH v2 3/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
From: Andrew Jeffery @ 2016-11-02 14:37 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring, linux-gpio,
linux-arm-kernel, linux-kernel, devicetree, Andrew Jeffery
In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au>
The Aspeed LPC Host Controller is presented as a syscon device to
arbitrate access by LPC and pinmux drivers. LPC pinmux configuration on
fifth generation SoCs depends on bits in both the System Control Unit
and the LPC Host Controller.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
new file mode 100644
index 000000000000..792651488c3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for the Aspeed LPC Host Controller (LPCHC)
+
+The LPCHC registers configure LPC behaviour between the BMC and the host
+system. The LPCHC also participates in pinmux requests on g5 SoCs and is
+therefore considered a syscon device.
+
+Required properties:
+- compatible: "aspeed,ast2500-lpchc", "syscon"
+- reg: contains offset/length value of the LPCHC memory
+ region.
+
+Example:
+
+lpchc: lpchc@1e7890a0 {
+ compatible = "aspeed,ast2500-lpchc", "syscon";
+ reg = <0x1e7890a0 0xc4>;
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 2/6] mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
From: Andrew Jeffery @ 2016-11-02 14:37 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring, linux-gpio,
linux-arm-kernel, linux-kernel, devicetree, Andrew Jeffery
In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au>
The Aspeed SoC Display Controller is presented as a syscon device to
arbitrate access by display and pinmux drivers. Video pinmux
configuration on fifth generation SoCs depends on bits in both the
System Control Unit and the Display Controller.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
Documentation/devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
new file mode 100644
index 000000000000..aea5370efd97
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
@@ -0,0 +1,17 @@
+* Device tree bindings for Aspeed SoC Display Controller (GFX)
+
+The Aspeed SoC Display Controller primarily does as its name suggests, but also
+participates in pinmux requests on the g5 SoCs. It is therefore considered a
+syscon device.
+
+Required properties:
+- compatible: "aspeed,ast2500-gfx", "syscon"
+- reg: contains offset/length value of the GFX memory
+ region.
+
+Example:
+
+gfx: display@1e6e6000 {
+ compatible = "aspeed,ast2500-gfx", "syscon";
+ reg = <0x1e6e6000 0x1000>;
+};
--
2.7.4
^ permalink raw reply related
* [PATCH v2 1/6] pinctrl-aspeed-g5: Never set SCU90[6]
From: Andrew Jeffery @ 2016-11-02 14:37 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring, linux-gpio,
linux-arm-kernel, linux-kernel, devicetree, Andrew Jeffery
In-Reply-To: <1478097481-14895-1-git-send-email-andrew@aj.id.au>
If a pin depending on bit 6 in SCU90 is requested for GPIO, the export
will succeed but changes to the GPIO's value will not be accepted by the
hardware. This is because the pinmux driver has misconfigured the SCU by
writing 1 to the reserved bit.
The description of SCU90[6] from the datasheet is 'Reserved, must keep
at value ”0”'. The fix is to switch pinmux from the bit-flipping macro
to explicitly configuring the .enable and .disable values to zero.
The patch has been tested on an AST2500 EVB.
Fixes: 56e57cb6c07f (pinctrl: Add pinctrl-aspeed-g5 driver)
Reported-by: Uma Yadlapati <yadlapat@us.ibm.com>
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
---
This patch should be applied for 4.9.
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
index c8c72e8259d3..87b46390b695 100644
--- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
+++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
@@ -26,7 +26,7 @@
#define ASPEED_G5_NR_PINS 228
-#define COND1 SIG_DESC_BIT(SCU90, 6, 0)
+#define COND1 { SCU90, BIT(6), 0, 0 }
#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
#define B14 0
--
2.7.4
^ permalink raw reply related
* [PATCH v2 0/6] pinctrl: aspeed: Fixes for g5, implement remaining pins
From: Andrew Jeffery @ 2016-11-02 14:37 UTC (permalink / raw)
To: Lee Jones, Linus Walleij
Cc: Joel Stanley, Mark Rutland, Rob Herring,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Andrew Jeffery
Hi all,
This is v2 of the series implementing the remainder of the pinmux tables for
the AST2400 and AST2500 SoCs. v1 of the series can be found here:
https://lkml.org/lkml/2016/9/27/309
The first patch, "pinctrl-aspeed-g5: Never set SCU90[6]", is another fix that
should be applied for 4.9. Please let me know if I should send such patches
separately, as the series otherwise targets 4.10.
v2 is based on 4.9-rc2 as requested in feedback on v1.
Cheers,
Andrew
Significant changes since v1:
* Fixes from v1 have been applied, so have been dropped for v2
* A new fix has appeared, "pinctrl-aspeed-g5: Never set SCU90[6]", as noted
above
* New bindings documents for the SoC Display and LPC Host Controllers, driven
by the patch "pinctrl: aspeed: Read and write bits in LPCHC and GFX
controllers"
* The v1 patch "pinctrl: aspeed: Enable capture of off-SCU pinmux state" has
been significantly reworked and is now titled "pinctrl: aspeed: Read and
write bits in LPCHC and GFX controllers"
Andrew Jeffery (6):
pinctrl-aspeed-g5: Never set SCU90[6]
mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
mfd: dt: Add bindings for the Aspeed LPC Host Controller (LPCHC)
pinctrl: aspeed: Read and write bits in LPCHC and GFX controllers
pinctrl: aspeed-g4: Add mux configuration for all pins
pinctrl: aspeed-g5: Add mux configuration for all pins
.../devicetree/bindings/mfd/aspeed-gfx.txt | 17 +
.../devicetree/bindings/mfd/aspeed-lpchc.txt | 17 +
.../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 86 +-
drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 1115 +++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 1514 +++++++++++++++++++-
drivers/pinctrl/aspeed/pinctrl-aspeed.c | 66 +-
drivers/pinctrl/aspeed/pinctrl-aspeed.h | 33 +-
7 files changed, 2760 insertions(+), 88 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpchc.txt
--
2.7.4
--
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^ permalink raw reply
* [PATCHv3 4/4] ARM: socfpga: dts: Add Monitor to A10-SR MFD
From: tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx @ 2016-11-02 14:32 UTC (permalink / raw)
To: lee.jones-QSEj5FYQhm4dnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8,
dinguyen-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, arnd-r2nGTMty4D4,
gregkh-hQyY1W1yCW8ekmWlsbkhG0B+6BGkLq7r
Cc: davem-fT/PcQaiUtIeIZ0/mPfg9Q, geert-Td1EMuHUCqxL1ZNQvxDV9g,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Thor Thayer
In-Reply-To: <1478097178-24341-1-git-send-email-tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
From: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
Add the Monitor functionality to the Arria10 DevKit
System Resource chip.
Signed-off-by: Thor Thayer <tthayer-yzvPICuk2ABMcg4IHK0kFoH6Mc4MB0Vx@public.gmane.org>
---
v2 Change from -mon to -monitor for clarity.
v3 Change node name from a10_monitor to monitor.
---
arch/arm/boot/dts/socfpga_arria10_socdk.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
index eb00ae3..996e745 100644
--- a/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10_socdk.dtsi
@@ -121,6 +121,10 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ monitor {
+ compatible = "altr,a10sr-monitor";
+ };
};
};
--
1.9.1
--
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^ permalink raw reply related
* [PATCHv3 3/4] mfd: altr-a10sr: Add Arria10 SR Monitor
From: tthayer @ 2016-11-02 14:32 UTC (permalink / raw)
To: lee.jones, robh+dt, mark.rutland, dinguyen, linux, arnd, gregkh
Cc: davem, geert, devicetree, linux-kernel, linux-arm-kernel,
Thor Thayer
In-Reply-To: <1478097178-24341-1-git-send-email-tthayer@opensource.altera.com>
From: Thor Thayer <tthayer@opensource.altera.com>
Add the Altera Arria10 DevKit System Resource Monitor functionality
to the MFD device.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-for-MFD-by: Lee Jones <lee.jones@linaro.org>
---
v2 Change from -mon to -monitor for clarity
v3 Shorten driver name (remove altr_).
---
drivers/mfd/altera-a10sr.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/mfd/altera-a10sr.c b/drivers/mfd/altera-a10sr.c
index 06e1f7f..2ddf235 100644
--- a/drivers/mfd/altera-a10sr.c
+++ b/drivers/mfd/altera-a10sr.c
@@ -30,9 +30,13 @@
static const struct mfd_cell altr_a10sr_subdev_info[] = {
{
- .name = "altr_a10sr_gpio",
+ .name = "a10sr_gpio",
.of_compatible = "altr,a10sr-gpio",
},
+ {
+ .name = "a10sr_monitor",
+ .of_compatible = "altr,a10sr-monitor",
+ },
};
static bool altr_a10sr_reg_readable(struct device *dev, unsigned int reg)
--
1.9.1
^ permalink raw reply related
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