* Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Jon Hunter @ 2016-11-03 13:45 UTC (permalink / raw)
To: Mirza Krak, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477576872-2665-2-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
> is max rate.
>
> The maximum rate value of 92 MHz is pulled from the downstream L4T
> kernel.
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Jon Hunter @ 2016-11-03 13:45 UTC (permalink / raw)
To: Mirza Krak
Cc: Stephen Warren, Thierry Reding, Alexandre Courbot, linux,
pdeschrijver, Prashant Gaikwad, Michael Turquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk, Marcel Ziswiler
In-Reply-To: <CALw8SCWC7RmNLVv4vxO9xw3jHVkgCaevbL61sJcpcva9CiaAVQ@mail.gmail.com>
On 03/11/16 12:30, Mirza Krak wrote:
> 2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak@gmail.com>:
>> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
>>> Hi Mirza,
>>>
>>> On 27/10/16 15:01, Mirza Krak wrote:
>>>>
>>>> From: Mirza Krak <mirza.krak@gmail.com>
>>>>
>>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>>> is max rate.
>>>>
>>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>>> kernel.
>>>
>>>
>>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>>> clocks. Can you point me to the appropriate sources so I can ACK this?
>>
>> I use the kernel sources provided by Toradex, and these sources are
>> based on L4T r16 release.
>>
>> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
>
> Ops, pre-mature send.
>
> I also added Marcel from Toradex on CC.
>
> The link to the source are [1] for Tegra2 and [2] for Tegra3.
>
> [1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
> [2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353
Great. Yes I see the same. Thanks!
Jon
--
nvpublic
^ permalink raw reply
* [PATCH] ARM: DTS: r8a7794: alt: Fix PCF names for DU
From: Jacopo Mondi @ 2016-11-03 13:42 UTC (permalink / raw)
To: horms, magnus.damm, robh+dt, mark.rutland, linux
Cc: linux-renesas-soc, devicetree, Jacopo Mondi, linux-arm-kernel
Update the PCF pin groups and function names of DU interface for
r8a7794 ALT board.
The currently specified pin groups and function names prevented PCF and
DU interfaces from being correctly configured:
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
sh-pfc e6060000.pin-controller: function 'du' not supported
sh-pfc e6060000.pin-controller: invalid function du in map table
rcar-du: probe of feb00000.display failed with error -22
Signed-off-by: Jacopo Mondi <jacopo@jmondi.org>
---
Patch applied against Simon Horman's renesas/master branch.
The PCF pin groups and function renaming was introduced by commit 56ed4bb9 and
DTS for ALT board has never been update accordingly.
Tested displaying frames on VGA interface: the rcar-du driver loads correctly.
arch/arm/boot/dts/r8a7794-alt.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 8d1b35a..9d65fb3 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -165,8 +165,8 @@
pinctrl-names = "default";
du_pins: du {
- groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_dotclkout0";
- function = "du";
+ groups = "du1_rgb666", "du1_sync", "du1_disp", "du1_clk0_out";
+ function = "du1";
};
scif2_pins: scif2 {
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V7 0/4] dmaengine: qcom_hidma: add MSI interrupt support
From: Koul, Vinod @ 2016-11-03 13:17 UTC (permalink / raw)
To: dmaengine-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
timur-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
cov-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
jcm-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org
Cc: agross-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
arnd-r2nGTMty4D4@public.gmane.org
In-Reply-To: <1477067879-23750-1-git-send-email-okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Fri, 2016-10-21 at 12:37 -0400, Sinan Kaya wrote:
> The new version of the HW supports MSI interrupts instead of wired
> interrupts. The MSI interrupts are especially useful for the guest
> machine
> execution. The wired interrupts usually trap to the hypervisor and
> then are
> relayed to the actual interrupt.
>
> The MSI interrupts can be directly fed into the interrupt controller.
>
> Adding a new OF compat string (qcom,hidma-1.1) and ACPI string
> (QCOM8062)
> to distinguish newer HW from the older ones.
Applied, thanks
--
~Vinod
--
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^ permalink raw reply
* Re: [PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface
From: Mirza Krak @ 2016-11-03 13:08 UTC (permalink / raw)
To: Jon Hunter
Cc: Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
Prashant Gaikwad, Michael Turquette, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-kernel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3cdf7281-840f-1aa0-5a57-fe58501165f4-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2016-11-03 11:51 GMT+01:00 Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>:
>
> On 27/10/16 15:01, Mirza Krak wrote:
>>
>> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>
>> The Generic Memory Interface bus can be used to connect high-speed
>> devices such as NOR flash, FPGAs, DSPs...
>>
>> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
>> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
>> ---
>>
>> Changes in v2:
>> - Fixed some checkpatch errors
>> - Re-ordered probe to get rid of local variables
>> - Moved of_platform_default_populate call to the end of probe
>> - Use the timing and configuration properties from the child device
>> - Added warning if more then 1 child device exist
>>
>> Changes in v3:
>> - added helper function to disable the controller which is used in remove
>> and
>> on error.
>> - Added logic to parse CS# from "ranges" property with fallback to "reg"
>> property
>>
>> drivers/bus/Kconfig | 8 ++
>> drivers/bus/Makefile | 1 +
>> drivers/bus/tegra-gmi.c | 267
>> ++++++++++++++++++++++++++++++++++++++++++++++++
>> 3 files changed, 276 insertions(+)
>> create mode 100644 drivers/bus/tegra-gmi.c
>>
>> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
>> index 4ed7d26..2e75a7f 100644
>> --- a/drivers/bus/Kconfig
>> +++ b/drivers/bus/Kconfig
>> @@ -141,6 +141,14 @@ config TEGRA_ACONNECT
>> Driver for the Tegra ACONNECT bus which is used to interface
>> with
>> the devices inside the Audio Processing Engine (APE) for
>> Tegra210.
>>
>> +config TEGRA_GMI
>> + tristate "Tegra Generic Memory Interface bus driver"
>> + depends on ARCH_TEGRA
>> + help
>> + Driver for the Tegra Generic Memory Interface bus which can be
>> used
>> + to attach devices such as NOR, UART, FPGA and more.
>> +
>> +
>
>
> Nit-pick ... only one additional line above is needed to be consistent with
> the rest of the file.
Will fix that.
>
>
>> config UNIPHIER_SYSTEM_BUS
>> tristate "UniPhier System Bus driver"
>> depends on ARCH_UNIPHIER && OF
>> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
>> index ac84cc4..34e2bab 100644
>> --- a/drivers/bus/Makefile
>> +++ b/drivers/bus/Makefile
>> @@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
>> obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
>> obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
>> obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
>> +obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
>> obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
>> obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
>> diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
>> new file mode 100644
>> index 0000000..dd9623e
>> --- /dev/null
>> +++ b/drivers/bus/tegra-gmi.c
>> @@ -0,0 +1,267 @@
>> +/*
>> + * Driver for NVIDIA Generic Memory Interface
>> + *
>> + * Copyright (C) 2016 Host Mobility AB. All rights reserved.
>> + *
>> + * This file is licensed under the terms of the GNU General Public
>> + * License version 2. This program is licensed "as is" without any
>> + * warranty of any kind, whether express or implied.
>> + */
>> +#include <linux/clk.h>
>> +#include <linux/delay.h>
>> +#include <linux/io.h>
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <linux/reset.h>
>> +
>> +#define TEGRA_GMI_CONFIG 0x00
>> +#define TEGRA_GMI_CONFIG_GO BIT(31)
>> +#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
>> +#define TEGRA_GMI_MUX_MODE BIT(28)
>> +#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
>> +#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
>> +#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
>> +#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
>> +#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
>> +#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
>> +
>> +#define TEGRA_GMI_TIMING0 0x10
>> +#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
>> +#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
>> +#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
>> +#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
>> +
>> +#define TEGRA_GMI_TIMING1 0x14
>> +#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
>> +#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
>> +#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
>> +
>> +struct tegra_gmi_priv {
>> + void __iomem *base;
>> + struct reset_control *rst;
>> + struct clk *clk;
>> +
>> + u32 snor_config;
>> + u32 snor_timing0;
>> + u32 snor_timing1;
>> +};
>> +
>> +static void tegra_gmi_disable(struct tegra_gmi_priv *priv)
>> +{
>> + u32 config;
>> +
>> + /* stop GMI operation */
>> + config = readl(priv->base + TEGRA_GMI_CONFIG);
>> + config &= ~TEGRA_GMI_CONFIG_GO;
>> + writel(config, priv->base + TEGRA_GMI_CONFIG);
>> +
>> + reset_control_assert(priv->rst);
>> + clk_disable_unprepare(priv->clk);
>> +}
>> +
>> +static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv
>> *priv)
>> +{
>> + writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0);
>> + writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1);
>> +
>> + priv->snor_config |= TEGRA_GMI_CONFIG_GO;
>> + writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG);
>> +}
>> +
>> +static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv
>> *priv)
>> +{
>> + struct device_node *child =
>> of_get_next_available_child(dev->of_node,
>> + NULL);
>> + u32 property, ranges[4];
>> + int ret;
>> +
>> + if (!child) {
>> + dev_warn(dev, "no child nodes found\n");
>> + return 0;
>
>
> Don't we want to return an error here? Otherwise, we will call
> tegra_gmi_init() with an invalid configuration.
True, we probably want that. My thought was that we might accept a
tegra-gmi node without any child nodes and just print a warning. But
since it is the child node that holds the bus configuration it makes
sense to fail probe due to no child nodes.
>
>
>> + }
>> +
>> + /*
>> + * We currently only support one child device due to lack of
>> + * chip-select address decoding. Which means that we only have one
>> + * chip-select line from the GMI controller.
>> + */
>> + if (of_get_child_count(dev->of_node) > 1)
>> + dev_warn(dev, "only one child device is supported.");
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
>> + priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
>> + priv->snor_config |= TEGRA_GMI_MUX_MODE;
>> +
>> + if (of_property_read_bool(child,
>> "nvidia,snor-rdy-active-before-data"))
>> + priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-rdy-inv"))
>> + priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-adv-inv"))
>> + priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-oe-inv"))
>> + priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
>> +
>> + if (of_property_read_bool(child, "nvidia,snor-cs-inv"))
>> + priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
>> +
>> + /* Decode the CS# */
>> + ret = of_property_read_u32_array(child, "ranges", ranges, 4);
>> + if (ret < 0) {
>> + /* Invalid binding */
>> + if (ret == -EOVERFLOW) {
>> + dev_err(dev, "invalid ranges length\n");
>> + goto error_cs_decode;
>> + }
>> +
>> + /*
>> + * If we reach here it means that the child node has an
>> empty
>> + * ranges or it does not exist at all. Attempt to decode
>> the
>> + * CS# from the reg property instead.
>> + */
>> + ret = of_property_read_u32(child, "reg", &property);
>> + if (ret < 0) {
>> + dev_err(dev, "no reg property found\n");
>> + goto error_cs_decode;
>> + }
>> + } else {
>> + property = ranges[1];
>> + }
>> +
>> + priv->snor_config |= TEGRA_GMI_CS_SELECT(property);
>
>
> Should we make sure the CS is a valid value before setting?
The TEGRA_GMI_CS_SELECT(x) macro will truncate any erroneous CS value.
But yeah we could do a sanity check instead and return an error if it
is invalid.
>
>
>> +
>> + /* The default values that are provided below are reset values */
>> + if (!of_property_read_u32(child, "nvidia,snor-muxed-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-hold-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-adv-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-ce-width",
>> &property))
>> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
>> + else
>> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-we-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-oe-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
>> +
>> + if (!of_property_read_u32(child, "nvidia,snor-wait-width",
>> &property))
>> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
>> + else
>> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
>> +
>> +error_cs_decode:
>> + if (ret < 0)
>> + dev_err(dev, "failed to decode chip-select number\n");
>
>
> Nit do we need another error message here? Can we add the "failed to decode
> CS" part the earlier message?
Does it make sense to drop the two earlier messages instead and keep this one?
Best Regards
Mirza
^ permalink raw reply
* Re: [PATCH v4] media: et8ek8: add device tree binding documentation
From: Pavel Machek @ 2016-11-03 12:47 UTC (permalink / raw)
To: Rob Herring
Cc: ivo.g.dimitrov.75, sakari.ailus, sre, pali.rohar, linux-media,
pawel.moll, mark.rutland, ijc+devicetree, galak, mchehab,
devicetree, linux-kernel
In-Reply-To: <20161030204134.hpmfrnqhd4mg563o@rob-hp-laptop>
[-- Attachment #1: Type: text/plain, Size: 1051 bytes --]
Hi!
> > +Mandatory properties
> > +--------------------
> > +
> > +- compatible: "toshiba,et8ek8"
> > +- reg: I2C address (0x3e, or an alternative address)
> > +- vana-supply: Analogue voltage supply (VANA), 2.8 volts
> > +- clocks: External clock to the sensor
> > +- clock-frequency: Frequency of the external clock to the sensor. Camera
> > + driver will set this frequency on the external clock.
>
> This is fine if the frequency is fixed (e.g. an oscillator), but you
> should use the clock binding if clocks are programable.
It is fixed. So I assume this can stay as is? Or do you want me to add
"The clock frequency is a pre-determined frequency known to be
suitable to the board." as Sakari suggests?
> > +- reset-gpios: XSHUTDOWN GPIO
>
> Please state what the active polarity is.
As in "This gpio will be set to 1 when the chip is powered." ?
Thanks,
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
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^ permalink raw reply
* [PATCH 6/6] ARM: dts: rockchip: add rockchip RK1108 Evaluation board
From: Andy Yan @ 2016-11-03 12:43 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andy Yan
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
RK1108EVB is designed by Rockchip for CVR field.
This patch add basic support for it, which can boot with
initramfs into shell.
Signed-off-by: Andy Yan <andy.yan-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Documentation/devicetree/bindings/arm/rockchip.txt | 3 +
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk1108-evb.dts | 69 ++++++++++++++++++++++
3 files changed, 73 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
diff --git a/Documentation/devicetree/bindings/arm/rockchip.txt b/Documentation/devicetree/bindings/arm/rockchip.txt
index 10b92b5..8670181 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.txt
+++ b/Documentation/devicetree/bindings/arm/rockchip.txt
@@ -1,5 +1,8 @@
Rockchip platforms device tree bindings
---------------------------------------
+- Rockchip RK1108 Evaluation board
+ Required root node properties:
+ - compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
- Kylin RK3036 board:
Required root node properties:
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index e49476a..249dca9 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -635,6 +635,7 @@ dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pba8.dtb \
arm-realview-pbx-a9.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += \
+ rk1108-evb.dtb \
rk3036-evb.dtb \
rk3036-kylin.dtb \
rk3066a-bqcurie2.dtb \
diff --git a/arch/arm/boot/dts/rk1108-evb.dts b/arch/arm/boot/dts/rk1108-evb.dts
new file mode 100644
index 0000000..3956cff
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108-evb.dts
@@ -0,0 +1,69 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "rk1108.dtsi"
+
+/ {
+ model = "Rockchip RK1108 Evaluation board";
+ compatible = "rockchip,rk1108-evb", "rockchip,rk1108";
+
+ memory@60000000 {
+ device_type = "memory";
+ reg = <0x60000000 0x08000000>;
+ };
+
+ chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&uart1 {
+ status = "okay";
+};
+
+&uart2 {
+ status = "okay";
+};
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 4/6] ARM: dts: add basic support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-03 12:40 UTC (permalink / raw)
To: heiko
Cc: elaine.zhang, mturquette, linux-rockchip, devicetree, robh+dt,
mark.rutland, linux, linux-clk, linux-arm-kernel, linux-kernel,
Andy Yan
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch add basic support for it with DMAC / UART / CRU / pinctrl
enabled.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
arch/arm/boot/dts/rk1108.dtsi | 420 ++++++++++++++++++++++++++++++++++++++
arch/arm/mach-rockchip/rockchip.c | 1 +
2 files changed, 421 insertions(+)
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
diff --git a/arch/arm/boot/dts/rk1108.dtsi b/arch/arm/boot/dts/rk1108.dtsi
new file mode 100644
index 0000000..9dccfea
--- /dev/null
+++ b/arch/arm/boot/dts/rk1108.dtsi
@@ -0,0 +1,420 @@
+/*
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/rk1108-cru.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ compatible = "rockchip,rk1108";
+
+ interrupt-parent = <&gic>;
+
+ aliases {
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &uart2;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@f00 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0xf00>;
+ };
+
+ };
+
+ amba {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ pdma: pdma@102a0000 {
+ compatible = "arm,pl330", "arm,primecell";
+ reg = <0x102a0000 0x4000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ #dma-cells = <1>;
+ arm,pl330-broken-no-flushp;
+ clocks = <&cru ACLK_DMAC>;
+ clock-names = "apb_pclk";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a7-pmu";
+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
+ clock-frequency = <24000000>;
+ };
+
+ xin24m: oscillator {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xin24m";
+ #clock-cells = <0>;
+ };
+
+ bus_intmem@10080000 {
+ compatible = "mmio-sram";
+ reg = <0x10080000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x10080000 0x2000>;
+ };
+
+ grf: syscon@10300000 {
+ compatible = "rockchip,rk1108-grf", "syscon";
+ reg = <0x10300000 0x1000>;
+ };
+
+ emmc: dwmmc@30110000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
+ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30110000 0x4000>;
+ status = "disabled";
+ };
+
+ sdio: dwmmc@30120000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 150000000>;
+ clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
+ <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30120000 0x4000>;
+ status = "disabled";
+ };
+
+ sdmmc: dwmmc@30130000 {
+ compatible = "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc";
+ clock-freq-min-max = <400000 100000000>;
+ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
+ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
+ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
+ fifo-depth = <0x100>;
+ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x30130000 0x4000>;
+ status = "disabled";
+ };
+
+ uart2: serial@10210000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10210000 0x100>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2m0_xfer>;
+ status = "disabled";
+ };
+
+ uart1: serial@10220000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10220000 0x100>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_xfer>;
+ status = "disabled";
+ };
+
+ uart0: serial@10230000 {
+ compatible = "rockchip,rk1108-uart", "snps,dw-apb-uart";
+ reg = <0x10230000 0x100>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ clock-frequency = <24000000>;
+ clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
+ clock-names = "baudclk", "apb_pclk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
+ status = "disabled";
+ };
+
+ cru: clock-controller@20200000 {
+ compatible = "rockchip,rk1108-cru";
+ reg = <0x20200000 0x1000>;
+ rockchip,grf = <&grf>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ gic: interrupt-controller@32010000 {
+ compatible = "arm,cortex-a15-gic";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+
+ reg = <0x32011000 0x1000>,
+ <0x32012000 0x1000>;
+ };
+
+ pinctrl: pinctrl {
+ compatible = "rockchip,rk1108-pinctrl";
+ rockchip,grf = <&grf>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio0: gpio0@20030000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x20030000 0x100>;
+ interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio1@10310000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10310000 0x100>;
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio2: gpio2@10320000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10320000 0x100>;
+ interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio3: gpio3@10330000 {
+ compatible = "rockchip,gpio-bank";
+ reg = <0x10330000 0x100>;
+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&xin24m>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ pcfg_pull_up: pcfg-pull-up {
+ bias-pull-up;
+ };
+
+ pcfg_pull_down: pcfg-pull-down {
+ bias-pull-down;
+ };
+
+ pcfg_pull_none: pcfg-pull-none {
+ bias-disable;
+ };
+
+ pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_12ma: pcfg-pull-none-drv-12ma {
+ drive-strength = <12>;
+ };
+
+ pcfg_pull_up_drv_8ma: pcfg-pull-up-drv-8ma {
+ bias-pull-up;
+ drive-strength = <8>;
+ };
+
+ pcfg_pull_none_drv_4ma: pcfg-pull-none-drv-4ma {
+ drive-strength = <4>;
+ };
+
+ pcfg_pull_up_drv_4ma: pcfg-pull-up-drv-4ma {
+ bias-pull-up;
+ drive-strength = <4>;
+ };
+
+ pcfg_output_high: pcfg-output-high {
+ output-high;
+ };
+
+ pcfg_output_low: pcfg-output-low {
+ output-low;
+ };
+
+ pcfg_input_high: pcfg-input-high {
+ bias-pull-up;
+ input-enable;
+ };
+
+ i2c1 {
+ i2c1_xfer: i2c1-xfer {
+ rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD4 RK_FUNC_1 &pcfg_pull_up>;
+ };
+ };
+
+ i2c2m1 {
+ i2c2m1_xfer: i2c2m1-xfer {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_2 &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_3 &pcfg_pull_none>;
+ };
+
+ i2c2m1_gpio: i2c2m1-gpio {
+ rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>,
+ <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c2m05v {
+ i2c2m05v_xfer: i2c2m05v-xfer {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_2 &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+
+ i2c2m05v_gpio: i2c2m05v-gpio {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>,
+ <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ i2c3 {
+ i2c3_xfer: i2c3-xfer {
+ rockchip,pins = <0 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,
+ <0 RK_PC4 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart0 {
+ uart0_xfer: uart0-xfer {
+ rockchip,pins = <3 RK_PA6 RK_FUNC_1 &pcfg_pull_up>,
+ <3 RK_PA5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_cts: uart0-cts {
+ rockchip,pins = <3 RK_PA4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts: uart0-rts {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart0_rts_gpio: uart0-rts-gpio {
+ rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ uart1 {
+ uart1_xfer: uart1-xfer {
+ rockchip,pins = <1 RK_PD3 RK_FUNC_1 &pcfg_pull_up>,
+ <1 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_cts: uart1-cts {
+ rockchip,pins = <1 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart1_rts: uart1-rts {
+ rockchip,pins = <1 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m0 {
+ uart2m0_xfer: uart2m0-xfer {
+ rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_up>,
+ <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+
+ uart2m1 {
+ uart2m1_xfer: uart2m1-xfer {
+ rockchip,pins = <3 RK_PC3 RK_FUNC_2 &pcfg_pull_up>,
+ <3 RK_PC2 RK_FUNC_2 &pcfg_pull_none>;
+ };
+ };
+
+ uart2_5v {
+ uart2_5v_cts: uart2_5v-cts {
+ rockchip,pins = <1 RK_PD4 RK_FUNC_1 &pcfg_pull_none>;
+ };
+
+ uart2_5v_rts: uart2_5v-rts {
+ rockchip,pins = <1 RK_PD5 RK_FUNC_1 &pcfg_pull_none>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
index a7ab9ec..e7fdf06 100644
--- a/arch/arm/mach-rockchip/rockchip.c
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -76,6 +76,7 @@ static void __init rockchip_dt_init(void)
}
static const char * const rockchip_board_dt_compat[] = {
+ "rockchip,rk1108",
"rockchip,rk2928",
"rockchip,rk3066a",
"rockchip,rk3066b",
--
2.7.4
^ permalink raw reply related
* [PATCH 1/6] dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
From: Andy Yan @ 2016-11-03 12:30 UTC (permalink / raw)
To: heiko
Cc: robh+dt, shawn.lin, linux-rockchip, devicetree, linux-arm-kernel,
ulf.hansson, linux-kernel, mark.rutland, Andy Yan
In-Reply-To: <1478175975-11779-1-git-send-email-andy.yan@rock-chips.com>
From: Shawn Lin <shawn.lin@rock-chips.com>
Add "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc" for
dwmmc on rk1108 platform.
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
---
Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
index 07184e8..ea9c1c9 100644
--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
+++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt
@@ -13,6 +13,7 @@ Required Properties:
- "rockchip,rk2928-dw-mshc": for Rockchip RK2928 and following,
before RK3288
- "rockchip,rk3288-dw-mshc": for Rockchip RK3288
+ - "rockchip,rk1108-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK1108
- "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3036
- "rockchip,rk3368-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3368
- "rockchip,rk3399-dw-mshc", "rockchip,rk3288-dw-mshc": for Rockchip RK3399
--
2.7.4
^ permalink raw reply related
* Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-03 12:30 UTC (permalink / raw)
To: Jon Hunter
Cc: Stephen Warren, Thierry Reding, Alexandre Courbot,
linux-I+IVW8TIWO2tmTQ+vhA3Yw, pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
Prashant Gaikwad, Michael Turquette, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA, linux-kernel,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA, Marcel Ziswiler
In-Reply-To: <CALw8SCWyLAw=yZ-W_nAFuDAazpa4HJfZuzqLDKQKYLWjV5JzYw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2016-11-03 13:26 GMT+01:00 Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>:
> 2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>:
>> Hi Mirza,
>>
>> On 27/10/16 15:01, Mirza Krak wrote:
>>>
>>> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>>>
>>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>>> is max rate.
>>>
>>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>>> kernel.
>>
>>
>> Thanks for adding this. I assume that this is from an L4T r16 release with a
>> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
>> unable to see where this is set. Obviously v3.1 did not have CCF and so
>> everything seems to be in the arch/arm/mach-tegra directory for setting up
>> clocks. Can you point me to the appropriate sources so I can ACK this?
>
> I use the kernel sources provided by Toradex, and these sources are
> based on L4T r16 release.
>
> http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
Ops, pre-mature send.
I also added Marcel from Toradex on CC.
The link to the source are [1] for Tegra2 and [2] for Tegra3.
[1]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
[2]. http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra3_clocks.c?h=tegra#n4353
Best Regards
Mirza
^ permalink raw reply
* Re: [PATCH v3 5/5] arm64: dts: exynos: Add dts file for Exynos5433-based TM2E board
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: Chanwoo Choi
Cc: krzk, kgene, javier, robh+dt, mark.rutland, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, jh80.chung, sw0312.kim, jy0922.shim, inki.dae,
jonghwa3.lee, beomho.seo, jaewon02.kim, human.hwang, ideal.song,
ingi2.kim, m.szyprowski, a.hajda, s.nawrocki, chanwoo
In-Reply-To: <1478155149-28527-6-git-send-email-cw00.choi@samsung.com>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti@samsung.com>
Andi
On Thu, Nov 03, 2016 at 03:39:09PM +0900, Chanwoo Choi wrote:
> This patch adds the Device Tree source for Exynos5433-based Samsung TM2E
> board. TM2E board is the most similar with TM2 board. The exynos5433-tm2e.dts
> include the difference between TM2 and TM2E.
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
> Acked-by: Rob Herring <robh@kernel.org>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 1 +
> arch/arm64/boot/dts/exynos/Makefile | 1 +
> arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts | 41 ++++++++++++++++++++++
> 3 files changed, 43 insertions(+)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index 339af8b9cdc5..c64c7b515777 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -16,6 +16,7 @@ Required root node properties:
> - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
> - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
> - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
> + - "samsung,tm2e" - for Exynos5433-based Samsung TM2E board.
> - "samsung,sd5v1" - for Exynos5440-based Samsung board.
> - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index 947c750acba1..7ddea53769a7 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,5 +1,6 @@
> dtb-$(CONFIG_ARCH_EXYNOS) += \
> exynos5433-tm2.dtb \
> + exynos5433-tm2e.dtb \
> exynos7-espresso.dtb
>
> always := $(dtb-y)
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> new file mode 100644
> index 000000000000..1db4e7f363a9
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2e.dts
> @@ -0,0 +1,41 @@
> +/*
> + * SAMSUNG Exynos5433 TM2E board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2E(TM2 EDGE) board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include "exynos5433-tm2.dts"
> +
> +/ {
> + model = "Samsung TM2E board";
> + compatible = "samsung,tm2e", "samsung,exynos5433";
> +};
> +
> +&ldo23_reg {
> + regulator-name = "CAM_SEN_CORE_1.025V_AP";
> + regulator-max-microvolt = <1050000>;
> +};
> +
> +&ldo25_reg {
> + regulator-name = "UNUSED_LDO25";
> + regulator-always-off;
> +};
> +
> +&ldo31_reg {
> + regulator-name = "TSP_VDD_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> +};
> +
> +&ldo38_reg {
> + regulator-name = "VCC_3.3V_MOTOR_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> +};
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH v3 4/5] arm64: dts: exynos: Add dts file for Exynos5433-based TM2 board
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: Chanwoo Choi
Cc: krzk-DgEjT+Ai2ygdnm+yROfE0A, kgene-DgEjT+Ai2ygdnm+yROfE0A,
javier-JPH+aEBZ4P+UEJcrhfAQsw, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
jh80.chung-Sze3O3UU22JBDgjK7y7TUQ,
sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ,
jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ,
inki.dae-Sze3O3UU22JBDgjK7y7TUQ,
jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ,
beomho.seo-Sze3O3UU22JBDgjK7y7TUQ,
jaewon02.kim-Sze3O3UU22JBDgjK7y7TUQ,
human.hwang-Sze3O3UU22JBDgjK7y7TUQ,
ideal.song-Sze3O3UU22JBDgjK7y7TUQ,
ingi2.kim-Sze3O3UU22JBDgjK7y7TUQ,
m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ,
a.hajda-Sze3O3UU22JBDgjK7y7TUQ, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
chanwoo-DgEjT+Ai2ygdnm+yROfE0A
In-Reply-To: <1478155149-28527-5-git-send-email-cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Andi
On Thu, Nov 03, 2016 at 03:39:08PM +0900, Chanwoo Choi wrote:
> This patch adds the Device Tree source for Exynos5433-based Samsung TM2 board.
> This board fully support the all things for mobile target.
>
> This patch supports the following devices:
> 1. basic SoC
> - Initial booting for Samsung Exynos5433 SoC
> - DRAM LPDDR3 (3GB)
> - eMMC (32GB)
> - ARM architecture timer
>
> 2. power management devices
> - Sasmung S2MPS13 PMIC for the power supply
> - CPUFREQ for big.LITTLE cores
> - TMU for big.LITTLE cores and GPU
> - ADC with thermistor to measure the temperature of AP/Battery/Charger
> - Maxim MAX77843 Interface PMIC (MUIC/Haptic/Regulator)
>
> 3. sound devices
> - I2S for sound bus
> - LPASS for sound power control
> - Wolfson WM5110 for sound codec
> - Maxim MAX98504 for speaker amplifier
> - TM2 ASoC Machine device driver node
>
> 3. display devices
> - DECON, DSI and MIC for the panel output
>
> 4. usb devices
> - USB 3.0 DRD (Dual Role Device)
> - USB 3.0 Host controller
>
> 5. storage devices
> - MSHC (Mobile Storage Host Controller) for eMMC device
>
> 6. misc devices
> - gpio-keys (power, volume up/down, home key)
> - PWM (Pulse Width Modulation Timer)
>
> Signed-off-by: Chanwoo Choi <cw00.choi-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Seung-Woo Kim <sw0312.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Joonyoung Shim <jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Inki Dae <inki.dae-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Beomho Seo <beomho.seo-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Jaewon Kim <jaewon02.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Hyungwon Hwang <human.hwang-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Inha Song <ideal.song-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Ingi kim <ingi2.kim-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Andrzej Hajda <a.hajda-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Reviewed-by: Krzysztof Kozlowski <krzk-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Reviewed-by: Javier Martinez Canillas <javier-JPH+aEBZ4P+UEJcrhfAQsw@public.gmane.org>
> ---
> .../bindings/arm/samsung/samsung-boards.txt | 1 +
> arch/arm64/boot/dts/exynos/Makefile | 4 +-
> arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 974 +++++++++++++++++++++
> 3 files changed, 978 insertions(+), 1 deletion(-)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
>
> diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> index 0ea7f14ef294..339af8b9cdc5 100644
> --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.txt
> @@ -15,6 +15,7 @@ Required root node properties:
> - "samsung,xyref5260" - for Exynos5260-based Samsung board.
> - "samsung,smdk5410" - for Exynos5410-based Samsung SMDK5410 eval board.
> - "samsung,smdk5420" - for Exynos5420-based Samsung SMDK5420 eval board.
> + - "samsung,tm2" - for Exynos5433-based Samsung TM2 board.
> - "samsung,sd5v1" - for Exynos5440-based Samsung board.
> - "samsung,ssdk5440" - for Exynos5440-based Samsung board.
>
> diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile
> index 50c9b9383cfa..947c750acba1 100644
> --- a/arch/arm64/boot/dts/exynos/Makefile
> +++ b/arch/arm64/boot/dts/exynos/Makefile
> @@ -1,4 +1,6 @@
> -dtb-$(CONFIG_ARCH_EXYNOS) += exynos7-espresso.dtb
> +dtb-$(CONFIG_ARCH_EXYNOS) += \
> + exynos5433-tm2.dtb \
> + exynos7-espresso.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> new file mode 100644
> index 000000000000..9ea3f32bae9e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
> @@ -0,0 +1,974 @@
> +/*
> + * SAMSUNG Exynos5433 TM2 board device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Device tree source file for Samsung's TM2 board which is based on
> + * Samsung Exynos5433 SoC.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +/dts-v1/;
> +#include "exynos5433.dtsi"
> +#include <dt-bindings/clock/samsung,s2mps11.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + model = "Samsung TM2 board";
> + compatible = "samsung,tm2", "samsung,exynos5433";
> +
> + aliases {
> + pinctrl0 = &pinctrl_alive;
> + pinctrl1 = &pinctrl_aud;
> + pinctrl2 = &pinctrl_cpif;
> + pinctrl3 = &pinctrl_ese;
> + pinctrl4 = &pinctrl_finger;
> + pinctrl5 = &pinctrl_fsys;
> + pinctrl6 = &pinctrl_imem;
> + pinctrl7 = &pinctrl_nfc;
> + pinctrl8 = &pinctrl_peric;
> + pinctrl9 = &pinctrl_touch;
> + serial0 = &serial_0;
> + serial1 = &serial_1;
> + serial2 = &serial_2;
> + serial3 = &serial_3;
> + spi0 = &spi_0;
> + spi1 = &spi_1;
> + spi2 = &spi_2;
> + spi3 = &spi_3;
> + spi4 = &spi_4;
> + };
> +
> + chosen {
> + stdout-path = &serial_1;
> + };
> +
> + memory@20000000 {
> + device_type = "memory";
> + reg = <0x0 0x20000000 0x0 0xc0000000>;
> + };
> +
> + gpio-keys {
> + compatible = "gpio-keys";
> +
> + power-key {
> + gpios = <&gpa2 7 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_POWER>;
> + label = "power key";
> + debounce-interval = <10>;
> + };
> +
> + volume-up-key {
> + gpios = <&gpa2 0 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEUP>;
> + label = "volume-up key";
> + debounce-interval = <10>;
> + };
> +
> + volume-down-key {
> + gpios = <&gpa2 1 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_VOLUMEDOWN>;
> + label = "volume-down key";
> + debounce-interval = <10>;
> + };
> +
> + homepage-key {
> + gpios = <&gpa0 3 GPIO_ACTIVE_LOW>;
> + linux,code = <KEY_MENU>;
> + label = "homepage key";
> + debounce-interval = <10>;
> + };
> + };
> +
> + i2c_max98504: i2c-gpio-0 {
> + compatible = "i2c-gpio";
> + gpios = <&gpd0 1 GPIO_ACTIVE_HIGH /* SPK_AMP_SDA */
> + &gpd0 0 GPIO_ACTIVE_HIGH /* SPK_AMP_SCL */ >;
> + i2c-gpio,delay-us = <2>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "okay";
> +
> + max98504: max98504@31 {
> + compatible = "maxim,max98504";
> + reg = <0x31>;
> + maxim,rx-path = <1>;
> + maxim,tx-path = <1>;
> + maxim,tx-channel-mask = <3>;
> + maxim,tx-channel-source = <2>;
> + };
> + };
> +
> + sound {
> + compatible = "samsung,tm2-audio";
> + audio-codec = <&wm5110>;
> + i2s-controller = <&i2s0>;
> + audio-amplifier = <&max98504>;
> + mic-bias-gpios = <&gpr3 2 GPIO_ACTIVE_HIGH>;
> + model = "wm5110";
> + samsung,audio-routing =
> + /* Headphone */
> + "HP", "HPOUT1L",
> + "HP", "HPOUT1R",
> +
> + /* Speaker */
> + "SPK", "SPKOUT",
> + "SPKOUT", "HPOUT2L",
> + "SPKOUT", "HPOUT2R",
> +
> + /* Receiver */
> + "RCV", "HPOUT3L",
> + "RCV", "HPOUT3R";
> + status = "okay";
> + };
> +};
> +
> +&adc {
> + vdd-supply = <&ldo3_reg>;
> + status = "okay";
> +
> + thermistor-ap {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 0>;
> + };
> +
> + thermistor-battery {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 1>;
> + #thermal-sensor-cells = <0>;
> + };
> +
> + thermistor-charger {
> + compatible = "murata,ncp03wf104";
> + pullup-uv = <1800000>;
> + pullup-ohm = <100000>;
> + pulldown-ohm = <0>;
> + io-channels = <&adc 2>;
> + };
> +};
> +
> +&cpu0 {
> + cpu-supply = <&buck3_reg>;
> +};
> +
> +&cpu4 {
> + cpu-supply = <&buck2_reg>;
> +};
> +
> +&decon {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&dsi {
> + status = "okay";
> + vddcore-supply = <&ldo6_reg>;
> + vddio-supply = <&ldo7_reg>;
> + samsung,pll-clock-frequency = <24000000>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&te_irq>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> +
> + dsi_out: endpoint {
> + samsung,burst-clock-frequency = <512000000>;
> + samsung,esc-clock-frequency = <16000000>;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_0 {
> + status = "okay";
> + clock-frequency = <2500000>;
> +
> + s2mps13-pmic@66 {
> + compatible = "samsung,s2mps13-pmic";
> + interrupt-parent = <&gpa0>;
> + interrupts = <7 IRQ_TYPE_NONE>;
> + reg = <0x66>;
> + samsung,s2mps11-wrstbi-ground;
> +
> + s2mps13_osc: clocks {
> + compatible = "samsung,s2mps13-clk";
> + #clock-cells = <1>;
> + clock-output-names = "s2mps13_ap", "s2mps13_cp",
> + "s2mps13_bt";
> + };
> +
> + regulators {
> + ldo1_reg: LDO1 {
> + regulator-name = "VDD_ALIVE_0.9V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <900000>;
> + regulator-always-on;
> + };
> +
> + ldo2_reg: LDO2 {
> + regulator-name = "VDDQ_MMC2_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo3_reg: LDO3 {
> + regulator-name = "VDD1_E_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo4_reg: LDO4 {
> + regulator-name = "VDD10_MIF_PLL_1.0V_AP";
> + regulator-min-microvolt = <1300000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo5_reg: LDO5 {
> + regulator-name = "VDD10_DPLL_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo6_reg: LDO6 {
> + regulator-name = "VDD10_MIPI2L_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo7_reg: LDO7 {
> + regulator-name = "VDD18_MIPI2L_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo8_reg: LDO8 {
> + regulator-name = "VDD18_LLI_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo9_reg: LDO9 {
> + regulator-name = "VDD18_ABB_ETC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo10_reg: LDO10 {
> + regulator-name = "VDD33_USB30_3.0V_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo11_reg: LDO11 {
> + regulator-name = "VDD_INT_M_1.0V_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo12_reg: LDO12 {
> + regulator-name = "VDD_KFC_M_1.1V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1350000>;
> + regulator-always-on;
> + };
> +
> + ldo13_reg: LDO13 {
> + regulator-name = "VDD_G3D_M_0.95V_AP";
> + regulator-min-microvolt = <950000>;
> + regulator-max-microvolt = <950000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo14_reg: LDO14 {
> + regulator-name = "VDDQ_M1_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo15_reg: LDO15 {
> + regulator-name = "VDDQ_M2_LDO_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + ldo16_reg: LDO16 {
> + regulator-name = "VDDQ_EFUSE";
> + regulator-min-microvolt = <1400000>;
> + regulator-max-microvolt = <3400000>;
> + regulator-always-on;
> + };
> +
> + ldo17_reg: LDO17 {
> + regulator-name = "V_TFLASH_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo18_reg: LDO18 {
> + regulator-name = "V_CODEC_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo19_reg: LDO19 {
> + regulator-name = "VDDA_1.8V_COMP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + ldo20_reg: LDO20 {
> + regulator-name = "VCC_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + regulator-always-on;
> + };
> +
> + ldo21_reg: LDO21 {
> + regulator-name = "VT_CAM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo22_reg: LDO22 {
> + regulator-name = "CAM_IO_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo23_reg: LDO23 {
> + regulator-name = "CAM_SEN_CORE_1.2V_AP";
> + regulator-min-microvolt = <1050000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo24_reg: LDO24 {
> + regulator-name = "VT_CAM_1.2V";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + };
> +
> + ldo25_reg: LDO25 {
> + regulator-name = "CAM_SEN_A2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo26_reg: LDO26 {
> + regulator-name = "CAM_AF_2.8V_AP";
> + regulator-min-microvolt = <2800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo27_reg: LDO27 {
> + regulator-name = "VCC_3.0V_LCD_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo28_reg: LDO28 {
> + regulator-name = "VCC_1.8V_LCD_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo29_reg: LDO29 {
> + regulator-name = "VT_CAM_2.8V";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo30_reg: LDO30 {
> + regulator-name = "TSP_AVDD_3.3V_AP";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + ldo31_reg: LDO31 {
> + regulator-name = "TSP_VDD_1.85V_AP";
> + regulator-min-microvolt = <1850000>;
> + regulator-max-microvolt = <1850000>;
> + };
> +
> + ldo32_reg: LDO32 {
> + regulator-name = "VTOUCH_1.8V_AP";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo33_reg: LDO33 {
> + regulator-name = "VTOUCH_LED_3.3V";
> + regulator-min-microvolt = <2500000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-ramp-delay = <12500>;
> + };
> +
> + ldo34_reg: LDO34 {
> + regulator-name = "VCC_1.8V_MHL_AP";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <2100000>;
> + };
> +
> + ldo35_reg: LDO35 {
> + regulator-name = "OIS_VM_2.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <2800000>;
> + };
> +
> + ldo36_reg: LDO36 {
> + regulator-name = "VSIL_1.0V";
> + regulator-min-microvolt = <1000000>;
> + regulator-max-microvolt = <1000000>;
> + };
> +
> + ldo37_reg: LDO37 {
> + regulator-name = "VF_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo38_reg: LDO38 {
> + regulator-name = "VCC_3.0V_MOTOR_AP";
> + regulator-min-microvolt = <3000000>;
> + regulator-max-microvolt = <3000000>;
> + };
> +
> + ldo39_reg: LDO39 {
> + regulator-name = "V_HRM_1.8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + ldo40_reg: LDO40 {
> + regulator-name = "V_HRM_3.3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + buck1_reg: BUCK1 {
> + regulator-name = "VDD_MIF_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck2_reg: BUCK2 {
> + regulator-name = "VDD_EGL_1.0V_AP";
> + regulator-min-microvolt = <900000>;
> + regulator-max-microvolt = <1300000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck3_reg: BUCK3 {
> + regulator-name = "VDD_KFC_1.0V_AP";
> + regulator-min-microvolt = <800000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck4_reg: BUCK4 {
> + regulator-name = "VDD_INT_0.95V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck5_reg: BUCK5 {
> + regulator-name = "VDD_DISP_CAM0_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck6_reg: BUCK6 {
> + regulator-name = "VDD_G3D_0.9V_AP";
> + regulator-min-microvolt = <600000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + regulator-state-mem {
> + regulator-off-in-suspend;
> + };
> + };
> +
> + buck7_reg: BUCK7 {
> + regulator-name = "VDD_MEM1_1.2V_AP";
> + regulator-min-microvolt = <1200000>;
> + regulator-max-microvolt = <1200000>;
> + regulator-always-on;
> + };
> +
> + buck8_reg: BUCK8 {
> + regulator-name = "VDD_LLDO_1.35V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck9_reg: BUCK9 {
> + regulator-name = "VDD_MLDO_2.0V_AP";
> + regulator-min-microvolt = <1350000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + buck10_reg: BUCK10 {
> + regulator-name = "vdd_mem2";
> + regulator-min-microvolt = <550000>;
> + regulator-max-microvolt = <1500000>;
> + regulator-always-on;
> + };
> + };
> + };
> +};
> +
> +&hsi2c_8 {
> + status = "okay";
> +
> + max77843@66 {
> + compatible = "maxim,max77843";
> + interrupt-parent = <&gpa1>;
> + interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
> + reg = <0x66>;
> +
> + muic: max77843-muic {
> + compatible = "maxim,max77843-muic";
> + };
> +
> + regulators {
> + compatible = "maxim,max77843-regulator";
> + safeout1_reg: SAFEOUT1 {
> + regulator-name = "SAFEOUT1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + safeout2_reg: SAFEOUT2 {
> + regulator-name = "SAFEOUT2";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <4950000>;
> + };
> +
> + charger_reg: CHARGER {
> + regulator-name = "CHARGER";
> + regulator-min-microamp = <100000>;
> + regulator-max-microamp = <3150000>;
> + };
> + };
> +
> + haptic: max77843-haptic {
> + compatible = "maxim,max77843-haptic";
> + haptic-supply = <&ldo38_reg>;
> + pwms = <&pwm 0 33670 0>;
> + pwm-names = "haptic";
> + };
> + };
> +};
> +
> +&i2s0 {
> + status = "okay";
> +};
> +
> +&mshc_0 {
> + status = "okay";
> + num-slots = <1>;
> + non-removable;
> + card-detect-delay = <200>;
> + samsung,dw-mshc-ciu-div = <3>;
> + samsung,dw-mshc-sdr-timing = <0 4>;
> + samsung,dw-mshc-ddr-timing = <0 2>;
> + samsung,dw-mshc-hs400-timing = <0 3>;
> + samsung,read-strobe-delay = <90>;
> + fifo-depth = <0x80>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_qrdy &sd0_bus1 &sd0_bus4
> + &sd0_bus8 &sd0_rdqs>;
> + bus-width = <8>;
> + assigned-clocks = <&cmu_top CLK_SCLK_MMC0_FSYS>;
> + assigned-clock-rates = <800000000>;
> +};
> +
> +&pinctrl_alive {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_alive>;
> +
> + initial_alive: initial-state {
> + PIN(IN, gpa0-0, DOWN, LV1);
> + PIN(IN, gpa0-1, NONE, LV1);
> + PIN(IN, gpa0-2, DOWN, LV1);
> + PIN(IN, gpa0-3, NONE, LV1);
> + PIN(IN, gpa0-4, NONE, LV1);
> + PIN(IN, gpa0-5, DOWN, LV1);
> + PIN(IN, gpa0-6, NONE, LV1);
> + PIN(IN, gpa0-7, NONE, LV1);
> +
> + PIN(IN, gpa1-0, UP, LV1);
> + PIN(IN, gpa1-1, NONE, LV1);
> + PIN(IN, gpa1-2, NONE, LV1);
> + PIN(IN, gpa1-3, DOWN, LV1);
> + PIN(IN, gpa1-4, DOWN, LV1);
> + PIN(IN, gpa1-5, NONE, LV1);
> + PIN(IN, gpa1-6, NONE, LV1);
> + PIN(IN, gpa1-7, NONE, LV1);
> +
> + PIN(IN, gpa2-0, NONE, LV1);
> + PIN(IN, gpa2-1, NONE, LV1);
> + PIN(IN, gpa2-2, NONE, LV1);
> + PIN(IN, gpa2-3, DOWN, LV1);
> + PIN(IN, gpa2-4, NONE, LV1);
> + PIN(IN, gpa2-5, DOWN, LV1);
> + PIN(IN, gpa2-6, DOWN, LV1);
> + PIN(IN, gpa2-7, NONE, LV1);
> +
> + PIN(IN, gpa3-0, DOWN, LV1);
> + PIN(IN, gpa3-1, DOWN, LV1);
> + PIN(IN, gpa3-2, NONE, LV1);
> + PIN(IN, gpa3-3, DOWN, LV1);
> + PIN(IN, gpa3-4, NONE, LV1);
> + PIN(IN, gpa3-5, DOWN, LV1);
> + PIN(IN, gpa3-6, DOWN, LV1);
> + PIN(IN, gpa3-7, DOWN, LV1);
> +
> + PIN(IN, gpf1-0, NONE, LV1);
> + PIN(IN, gpf1-1, NONE, LV1);
> + PIN(IN, gpf1-2, DOWN, LV1);
> + PIN(IN, gpf1-4, UP, LV1);
> + PIN(OUT, gpf1-5, NONE, LV1);
> + PIN(IN, gpf1-6, DOWN, LV1);
> + PIN(IN, gpf1-7, DOWN, LV1);
> +
> + PIN(IN, gpf2-0, DOWN, LV1);
> + PIN(IN, gpf2-1, DOWN, LV1);
> + PIN(IN, gpf2-2, DOWN, LV1);
> + PIN(IN, gpf2-3, DOWN, LV1);
> +
> + PIN(IN, gpf3-0, DOWN, LV1);
> + PIN(IN, gpf3-1, DOWN, LV1);
> + PIN(IN, gpf3-2, NONE, LV1);
> + PIN(IN, gpf3-3, DOWN, LV1);
> +
> + PIN(IN, gpf4-0, DOWN, LV1);
> + PIN(IN, gpf4-1, DOWN, LV1);
> + PIN(IN, gpf4-2, DOWN, LV1);
> + PIN(IN, gpf4-3, DOWN, LV1);
> + PIN(IN, gpf4-4, DOWN, LV1);
> + PIN(IN, gpf4-5, DOWN, LV1);
> + PIN(IN, gpf4-6, DOWN, LV1);
> + PIN(IN, gpf4-7, DOWN, LV1);
> +
> + PIN(IN, gpf5-0, DOWN, LV1);
> + PIN(IN, gpf5-1, DOWN, LV1);
> + PIN(IN, gpf5-2, DOWN, LV1);
> + PIN(IN, gpf5-3, DOWN, LV1);
> + PIN(OUT, gpf5-4, NONE, LV1);
> + PIN(IN, gpf5-5, DOWN, LV1);
> + PIN(IN, gpf5-6, DOWN, LV1);
> + PIN(IN, gpf5-7, DOWN, LV1);
> + };
> +
> + te_irq: te_irq {
> + samsung,pins = "gpf1-3";
> + samsung,pin-function = <0xf>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_cpif>;
> +
> + initial_cpif: initial-state {
> + PIN(IN, gpv6-0, DOWN, LV1);
> + PIN(IN, gpv6-1, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_ese {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_ese>;
> +
> + initial_ese: initial-state {
> + PIN(IN, gpj2-0, DOWN, LV1);
> + PIN(IN, gpj2-1, DOWN, LV1);
> + PIN(IN, gpj2-2, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_fsys {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_fsys>;
> +
> + initial_fsys: initial-state {
> + PIN(IN, gpr3-0, NONE, LV1);
> + PIN(IN, gpr3-1, DOWN, LV1);
> + PIN(IN, gpr3-2, DOWN, LV1);
> + PIN(IN, gpr3-3, DOWN, LV1);
> + PIN(IN, gpr3-7, NONE, LV1);
> + };
> +};
> +
> +&pinctrl_imem {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_imem>;
> +
> + initial_imem: initial-state {
> + PIN(IN, gpf0-0, UP, LV1);
> + PIN(IN, gpf0-1, UP, LV1);
> + PIN(IN, gpf0-2, DOWN, LV1);
> + PIN(IN, gpf0-3, UP, LV1);
> + PIN(IN, gpf0-4, DOWN, LV1);
> + PIN(IN, gpf0-5, NONE, LV1);
> + PIN(IN, gpf0-6, DOWN, LV1);
> + PIN(IN, gpf0-7, UP, LV1);
> + };
> +};
> +
> +&pinctrl_nfc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_nfc>;
> +
> + initial_nfc: initial-state {
> + PIN(IN, gpj0-2, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_peric {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_peric>;
> +
> + initial_peric: initial-state {
> + PIN(IN, gpv7-0, DOWN, LV1);
> + PIN(IN, gpv7-1, DOWN, LV1);
> + PIN(IN, gpv7-2, NONE, LV1);
> + PIN(IN, gpv7-3, DOWN, LV1);
> + PIN(IN, gpv7-4, DOWN, LV1);
> + PIN(IN, gpv7-5, DOWN, LV1);
> +
> + PIN(IN, gpb0-4, DOWN, LV1);
> +
> + PIN(IN, gpc0-2, DOWN, LV1);
> + PIN(IN, gpc0-5, DOWN, LV1);
> + PIN(IN, gpc0-7, DOWN, LV1);
> +
> + PIN(IN, gpc1-1, DOWN, LV1);
> +
> + PIN(IN, gpc3-4, NONE, LV1);
> + PIN(IN, gpc3-5, NONE, LV1);
> + PIN(IN, gpc3-6, NONE, LV1);
> + PIN(IN, gpc3-7, NONE, LV1);
> +
> + PIN(OUT, gpg0-0, NONE, LV1);
> + PIN(FUNC1, gpg0-1, DOWN, LV1);
> +
> + PIN(IN, gpd2-5, DOWN, LV1);
> +
> + PIN(IN, gpd4-0, NONE, LV1);
> + PIN(IN, gpd4-1, DOWN, LV1);
> + PIN(IN, gpd4-2, DOWN, LV1);
> + PIN(IN, gpd4-3, DOWN, LV1);
> + PIN(IN, gpd4-4, DOWN, LV1);
> +
> + PIN(IN, gpd6-3, DOWN, LV1);
> +
> + PIN(IN, gpd8-1, UP, LV1);
> +
> + PIN(IN, gpg1-0, DOWN, LV1);
> + PIN(IN, gpg1-1, DOWN, LV1);
> + PIN(IN, gpg1-2, DOWN, LV1);
> + PIN(IN, gpg1-3, DOWN, LV1);
> + PIN(IN, gpg1-4, DOWN, LV1);
> +
> + PIN(IN, gpg2-0, DOWN, LV1);
> + PIN(IN, gpg2-1, DOWN, LV1);
> +
> + PIN(IN, gpg3-0, DOWN, LV1);
> + PIN(IN, gpg3-1, DOWN, LV1);
> + PIN(IN, gpg3-5, DOWN, LV1);
> + PIN(IN, gpg3-7, DOWN, LV1);
> + };
> +};
> +
> +&pinctrl_touch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&initial_touch>;
> +
> + initial_touch: initial-state {
> + PIN(IN, gpj1-2, DOWN, LV1);
> + };
> +};
> +
> +&pwm {
> + pinctrl-0 = <&pwm0_out>;
> + pinctrl-names = "default";
> + status = "okay";
> +};
> +
> +&mic {
> + status = "okay";
> +
> + i80-if-timings {
> + };
> +};
> +
> +&serial_1 {
> + status = "okay";
> +};
> +
> +&serial_3 {
> + assigned-clocks = <&cmu_aud CLK_MOUT_AUD_PLL_USER>;
> + assigned-clock-parents = <&cmu_top CLK_FOUT_AUD_PLL>;
> + status = "okay";
> +};
> +
> +&spi_1 {
> + cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
> + status = "okay";
> +
> + wm5110: wm5110-codec@0 {
> + compatible = "wlf,wm5110";
> + reg = <0x0>;
> + spi-max-frequency = <20000000>;
> + interrupt-parent = <&gpa0>;
> + interrupts = <4 IRQ_TYPE_NONE>;
> + clocks = <&pmu_system_controller 0>,
> + <&s2mps13_osc S2MPS11_CLK_BT>;
> + clock-names = "mclk1", "mclk2";
> +
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + wlf,micd-detect-debounce = <300>;
> + wlf,micd-bias-start-time = <0x1>;
> + wlf,micd-rate = <0x7>;
> + wlf,micd-dbtime = <0x1>;
> + wlf,micd-force-micbias;
> + wlf,micd-configs = <0x0 1 0>;
> + wlf,hpdet-channel = <1>;
> + wlf,gpsw = <0x1>;
> + wlf,inmode = <2 0 2 0>;
> +
> + wlf,reset = <&gpc0 7 GPIO_ACTIVE_HIGH>;
> + wlf,ldoena = <&gpf0 0 GPIO_ACTIVE_HIGH>;
> +
> + /* core supplies */
> + AVDD-supply = <&ldo18_reg>;
> + DBVDD1-supply = <&ldo18_reg>;
> + CPVDD-supply = <&ldo18_reg>;
> + DBVDD2-supply = <&ldo18_reg>;
> + DBVDD3-supply = <&ldo18_reg>;
> +
> + controller-data {
> + samsung,spi-feedback-delay = <0>;
> + };
> + };
> +};
> +
> +&timer {
> + clock-frequency = <24000000>;
> +};
> +
> +&tmu_atlas0 {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_apollo {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&tmu_g3d {
> + vtmu-supply = <&ldo3_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd30 {
> + vdd33-supply = <&ldo10_reg>;
> + vdd10-supply = <&ldo6_reg>;
> + status = "okay";
> +};
> +
> +&usbdrd_dwc3_0 {
> + dr_mode = "otg";
> +};
> +
> +&usbdrd30_phy {
> + vbus-supply = <&safeout1_reg>;
> + status = "okay";
> +};
> +
> +&xxti {
> + clock-frequency = <24000000>;
> +};
> --
> 1.9.1
>
--
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^ permalink raw reply
* Re: [PATCH V3 1/6] clk: tegra: add TEGRA20_CLK_NOR to init table
From: Mirza Krak @ 2016-11-03 12:26 UTC (permalink / raw)
To: Jon Hunter
Cc: Stephen Warren, Thierry Reding, Alexandre Courbot, linux,
pdeschrijver, Prashant Gaikwad, Michael Turquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk
In-Reply-To: <df12a1f0-316d-64a4-54fe-f7559742eeca@nvidia.com>
2016-11-03 11:06 GMT+01:00 Jon Hunter <jonathanh@nvidia.com>:
> Hi Mirza,
>
> On 27/10/16 15:01, Mirza Krak wrote:
>>
>> From: Mirza Krak <mirza.krak@gmail.com>
>>
>> Add TEGRA20_CLK_NOR to init table and set default rate to 92 MHz which
>> is max rate.
>>
>> The maximum rate value of 92 MHz is pulled from the downstream L4T
>> kernel.
>
>
> Thanks for adding this. I assume that this is from an L4T r16 release with a
> v3.1 kernel. I had a quick poke through the kernel sources for v3.1 but was
> unable to see where this is set. Obviously v3.1 did not have CCF and so
> everything seems to be in the arch/arm/mach-tegra directory for setting up
> clocks. Can you point me to the appropriate sources so I can ACK this?
I use the kernel sources provided by Toradex, and these sources are
based on L4T r16 release.
http://git.toradex.com/cgit/linux-toradex.git/tree/arch/arm/mach-tegra/tegra2_clocks.c?h=tegra#n2463
Best Regards
Mirza Krak
^ permalink raw reply
* [PATCH 0/6] Add basic support for support for Rockchip RK1108 SOC
From: Andy Yan @ 2016-11-03 12:26 UTC (permalink / raw)
To: heiko
Cc: linus.walleij, robh+dt, shawn.lin, linux-clk, briannorris,
linux-rockchip, devicetree, mturquette, sboyd, linux-gpio, linux,
linux-arm-kernel, ulf.hansson, linux-kernel, mark.rutland,
elaine.zhang, Andy Yan
RK1108 is embedded with an ARM Cortex-A7 single core and a DSP core.
It is designed for varies application scenario such as car DVR, sports
DV, secure camera and UAV camera.
This patch series add basic support for it, which can boot a board with
initramfs into shell.
More new feathers will come soon.
Andy Yan (4):
pinctrl: rockchip: add support for rk1108
ARM: dts: add basic support for Rockchip RK1108 SOC
ARM: add low level debug uart for rk1108
ARM: dts: rockchip: add rockchip RK1108 Evaluation board
Shawn Lin (2):
dt-bindings: rockchip-dw-mshc: add RK1108 dw-mshc description
clk: rockchip: add clock controller for rk1108
Documentation/devicetree/bindings/arm/rockchip.txt | 3 +
.../devicetree/bindings/mmc/rockchip-dw-mshc.txt | 1 +
arch/arm/Kconfig.debug | 30 ++
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/rk1108-evb.dts | 69 +++
arch/arm/boot/dts/rk1108.dtsi | 420 +++++++++++++++++++
arch/arm/mach-rockchip/rockchip.c | 1 +
drivers/clk/rockchip/Makefile | 1 +
drivers/clk/rockchip/clk-rk1108.c | 463 +++++++++++++++++++++
drivers/clk/rockchip/clk.h | 14 +
drivers/pinctrl/pinctrl-rockchip.c | 27 +-
include/dt-bindings/clock/rk1108-cru.h | 308 ++++++++++++++
12 files changed, 1337 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/rk1108-evb.dts
create mode 100644 arch/arm/boot/dts/rk1108.dtsi
create mode 100644 drivers/clk/rockchip/clk-rk1108.c
create mode 100644 include/dt-bindings/clock/rk1108-cru.h
--
2.7.4
^ permalink raw reply
* Re: [PATCH v3 3/5] arm64: dts: exynos: Add dts files for Samsung Exynos5433 64bit SoC
From: Andi Shyti @ 2016-11-03 12:26 UTC (permalink / raw)
To: Chanwoo Choi
Cc: krzk, kgene, javier, robh+dt, mark.rutland, catalin.marinas,
will.deacon, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel, jh80.chung, sw0312.kim, jy0922.shim, inki.dae,
jonghwa3.lee, beomho.seo, jaewon02.kim, human.hwang, ideal.song,
ingi2.kim, m.szyprowski, a.hajda, s.nawrocki, chanwoo
In-Reply-To: <1478155149-28527-4-git-send-email-cw00.choi@samsung.com>
Hi Chanwoo,
Tested-by: Andi Shyti <andi.shyti@samsung.com>
Andi
On Thu, Nov 03, 2016 at 03:39:07PM +0900, Chanwoo Choi wrote:
> This patch adds new Exynos5433 dtsi to support 64-bit Exynos5433 SoC based on
> Octa-core CPUs (quad Cortex-A57 and quad Cortex-A53). And Exynos5433 supports
> PSCI (Power State Coordination Interface) v0.1.
>
> This patch includes following Device Tree node to support Exynos5433 SoC:
> 1. Octa cores for big.LITTLE architecture
> - Cortex-A53 LITTLE Quad-core
> - Cortex-A57 big Quad-core
> - Support PSCI v0.1
>
> 2. Clock controller node
> - CMU_TOP : clocks for IMEM/FSYS/G3D/GSCL/HEVC/MSCL/G2D/MFC/PERIC/PERIS
> - CMU_CPIF : clocks for LLI (Low Latency Interface)
> - CMU_MIF : clocks for DRAM Memory Controller
> - CMU_PERIC : clocks for UART/I2C/SPI/I2S/PCM/SPDIF/PWM/SLIMBUS
> - CMU_PERIS : clocks for PMU/TMU/MCT/WDT/RTC/SECKEY/TZPC
> - CMU_FSYS : clocks for USB/UFS/SDMMC/TSI/PDMA
> - CMU_G2D : clocks for G2D/MDMA
> - CMU_DISP : clocks for DECON/HDMI/DSIM/MIXER
> - CMU_AUD : clocks for Cortex-A5/BUS/AUDIO
> - CMU_BUS{0|1|2} : clocks for global data buses and global peripheral buses
> - CMU_G3D : clocks for 3D Graphics Engine
> - CMU_GSCL : clocks for GSCALER
> - CMU_APOLLO: clocks for Cortex-A53 Quad-core processor.
> - CMU_ATLAS : clocks for Cortex-A57 Quad-core processor,
> CoreSight and L2 cache controller.
> - CMU_MSCL : clocks for M2M (Memory to Memory) scaler and JPEG IPs.
> - CMU_MFC : clocks for MFC (Multi-Format Codec) IP.
> - CMU_HEVC : clocks for HEVC(High Efficiency Video Codec) decoder IP.
> - CMU_ISP : clocks for FIMC-ISP/DRC/SCLC/DIS/3DNR IPs.
> - CMU_CAM0 : clocks for MIPI_CSIS{0|1}/FIMC_LITE_{A|B|D}/FIMC_3AA{0|1} IPs.
> - CMU_CAM1 : clocks for COrtex-A5/MIPI_CSIS2/FIMC_LITE_C/FIMC-FD IPs.
>
> 3. pinctrl node for GPIO
> - alive/aud/cpif/ese/finger/fsys/imem/nfc/peric/touch pad
>
> 4. Timer
> - ARM architecture timer (armv8-timer)
> - MCT (Multi Core Timer) timer
>
> 5. Interrupt controller (GIC-400)
>
> 6. BUS devices
> - HS-I2C (High-Speed I2C) device
> - SPI (Serial Peripheral Interface) device
>
> 7. Sound devices
> - I2S bus
> - LPASS (Low Power Audio Subsystem)
>
> 8. Power management devices
> - CPUFREQ for for Cortex-A53/A57
> - TMU (Thermal Management Unit) for Cortex-A53/A57, G3D, ISP
>
> 9. Display controller devices
> - DECON (Display and enhancement controller) for panel output
> - DSI (Display Serial Interface)
> - MIC (Mobile Image Compressor)
>
> 10. USB
> - USB 3.0 DRD (Dual Role Device) controller
> - USB 3.0 Host controller
>
> 11. Storage devices
> - MSHC (Mobile Storage Host Controller)
>
> 12. Misc devices
> - UART device
> - ADC (Analog Digital Converter)
> - PWM (Pulse Width Modulation)
> - ADMA (Advanced DMA) and PDMA (Peripheral DMA)
>
> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
> Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
> Signed-off-by: Inki Dae <inki.dae@samsung.com>
> Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
> Signed-off-by: Beomho Seo <beomho.seo@samsung.com>
> Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com>
> Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
> Signed-off-by: Inha Song <ideal.song@samsung.com>
> Signed-off-by: Ingi kim <ingi2.kim@samsung.com>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
> ---
> arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi | 794 ++++++++++++
> .../dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi | 23 +
> .../dts/exynos/exynos5433-tmu-sensor-conf.dtsi | 22 +
> arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi | 296 +++++
> arch/arm64/boot/dts/exynos/exynos5433.dtsi | 1356 ++++++++++++++++++++
> 5 files changed, 2491 insertions(+)
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> create mode 100644 arch/arm64/boot/dts/exynos/exynos5433.dtsi
>
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> new file mode 100644
> index 000000000000..796881310bf6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-pinctrl.dtsi
> @@ -0,0 +1,794 @@
> +/*
> + * Samsung's Exynos5433 SoC pin-mux and pin-config device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + * Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * Samsung's Exynos5433 SoC pin-mux and pin-config options are listed as device
> + * tree nodes are listed in this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#define PIN_PULL_NONE 0
> +#define PIN_PULL_DOWN 1
> +#define PIN_PULL_UP 3
> +
> +#define PIN_DRV_LV1 0
> +#define PIN_DRV_LV2 2
> +#define PIN_DRV_LV3 1
> +#define PIN_DRV_LV4 3
> +
> +#define PIN_IN 0
> +#define PIN_OUT 1
> +#define PIN_FUNC1 2
> +
> +#define PIN(_func, _pin, _pull, _drv) \
> + _pin { \
> + samsung,pins = #_pin; \
> + samsung,pin-function = <PIN_ ##_func>; \
> + samsung,pin-pud = <PIN_PULL_ ##_pull>; \
> + samsung,pin-drv = <PIN_DRV_ ##_drv>; \
> + }
> +
> +&pinctrl_alive {
> + gpa0: gpa0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 0 0>, <GIC_SPI 1 0>, <GIC_SPI 2 0>,
> + <GIC_SPI 3 0>, <GIC_SPI 4 0>, <GIC_SPI 5 0>,
> + <GIC_SPI 6 0>, <GIC_SPI 7 0>;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa1: gpa1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 8 0>, <GIC_SPI 9 0>, <GIC_SPI 10 0>,
> + <GIC_SPI 11 0>, <GIC_SPI 12 0>, <GIC_SPI 13 0>,
> + <GIC_SPI 14 0>, <GIC_SPI 15 0>;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa2: gpa2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpa3: gpa3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf1: gpf1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf2: gpf2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf3: gpf3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf4: gpf4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpf5: gpf5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_aud {
> + gpz0: gpz0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpz1: gpz1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + i2s0_bus: i2s0-bus {
> + samsung,pins = "gpz0-0", "gpz0-1", "gpz0-2", "gpz0-3",
> + "gpz0-4", "gpz0-5", "gpz0-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pcm0_bus: pcm0-bus {
> + samsung,pins = "gpz1-0", "gpz1-1", "gpz1-2", "gpz1-3";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart_aud_bus: uart-aud-bus {
> + samsung,pins = "gpz1-3", "gpz1-2", "gpz1-1", "gpz1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_cpif {
> + gpv6: gpv6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_ese {
> + gpj2: gpj2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_finger {
> + gpd5: gpd5 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + spi2_bus: spi2-bus {
> + samsung,pins = "gpd5-0", "gpd5-2", "gpd5-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c6_bus: hs-i2c6-bus {
> + samsung,pins = "gpd5-3", "gpd5-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_fsys {
> + gph1: gph1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr4: gpr4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr0: gpr0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr1: gpr1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr2: gpr2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpr3: gpr3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + sd0_clk: sd0-clk {
> + samsung,pins = "gpr0-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_cmd: sd0-cmd {
> + samsung,pins = "gpr0-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_rdqs: sd0-rdqs {
> + samsung,pins = "gpr0-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_qrdy: sd0-qrdy {
> + samsung,pins = "gpr0-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus1: sd0-bus-width1 {
> + samsung,pins = "gpr1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus4: sd0-bus-width4 {
> + samsung,pins = "gpr1-1", "gpr1-2", "gpr1-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd0_bus8: sd0-bus-width8 {
> + samsung,pins = "gpr1-4", "gpr1-5", "gpr1-6", "gpr1-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_clk: sd1-clk {
> + samsung,pins = "gpr2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_cmd: sd1-cmd {
> + samsung,pins = "gpr2-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus1: sd1-bus-width1 {
> + samsung,pins = "gpr3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus4: sd1-bus-width4 {
> + samsung,pins = "gpr3-1", "gpr3-2", "gpr3-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd1_bus8: sd1-bus-width8 {
> + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + pcie_bus: pcie_bus {
> + samsung,pins = "gpr3-4", "gpr3-5", "gpr3-6", "gpr3-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + };
> +
> + sd2_clk: sd2-clk {
> + samsung,pins = "gpr4-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_cmd: sd2-cmd {
> + samsung,pins = "gpr4-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_cd: sd2-cd {
> + samsung,pins = "gpr4-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_bus1: sd2-bus-width1 {
> + samsung,pins = "gpr4-3";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_bus4: sd2-bus-width4 {
> + samsung,pins = "gpr4-4", "gpr4-5", "gpr4-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <3>;
> + };
> +
> + sd2_clk_output: sd2-clk-output {
> + samsung,pins = "gpr4-0";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <2>;
> + };
> +
> + sd2_cmd_output: sd2-cmd-output {
> + samsung,pins = "gpr4-1";
> + samsung,pin-function = <1>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <2>;
> + };
> +};
> +
> +&pinctrl_imem {
> + gpf0: gpf0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +};
> +
> +&pinctrl_nfc {
> + gpj0: gpj0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c4_bus: hs-i2c4-bus {
> + samsung,pins = "gpj0-1", "gpj0-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_peric {
> + gpv7: gpv7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpb0: gpb0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc0: gpc0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc1: gpc1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc2: gpc2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpc3: gpc3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg0: gpg0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd0: gpd0 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd1: gpd1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd2: gpd2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd4: gpd4 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd8: gpd8 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd6: gpd6 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpd7: gpd7 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg1: gpg1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg2: gpg2 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpg3: gpg3 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c8_bus: hs-i2c8-bus {
> + samsung,pins = "gpb0-1", "gpb0-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c9_bus: hs-i2c9-bus {
> + samsung,pins = "gpb0-3", "gpb0-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + i2s1_bus: i2s1-bus {
> + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
> + "gpd4-3", "gpd4-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pcm1_bus: pcm1-bus {
> + samsung,pins = "gpd4-0", "gpd4-1", "gpd4-2",
> + "gpd4-3", "gpd4-4";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spdif_bus: spdif-bus {
> + samsung,pins = "gpd4-3", "gpd4-4";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <1>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_spi_pin0: fimc-is-spi-pin0 {
> + samsung,pins = "gpc3-3", "gpc3-2", "gpc3-1", "gpc3-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_spi_pin1: fimc-is-spi-pin1 {
> + samsung,pins = "gpc3-7", "gpc3-6", "gpc3-5", "gpc3-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart0_bus: uart0-bus {
> + samsung,pins = "gpd0-3", "gpd0-2", "gpd0-1", "gpd0-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + hs_i2c2_bus: hs-i2c2-bus {
> + samsung,pins = "gpd0-3", "gpd0-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + uart2_bus: uart2-bus {
> + samsung,pins = "gpd1-5", "gpd1-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + uart1_bus: uart1-bus {
> + samsung,pins = "gpd1-3", "gpd1-2", "gpd1-1", "gpd1-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + };
> +
> + hs_i2c3_bus: hs-i2c3-bus {
> + samsung,pins = "gpd1-3", "gpd1-2";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c0_bus: hs-i2c0-bus {
> + samsung,pins = "gpd2-1", "gpd2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c1_bus: hs-i2c1-bus {
> + samsung,pins = "gpd2-3", "gpd2-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm0_out: pwm0-out {
> + samsung,pins = "gpd2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm1_out: pwm1-out {
> + samsung,pins = "gpd2-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm2_out: pwm2-out {
> + samsung,pins = "gpd2-6";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + pwm3_out: pwm3-out {
> + samsung,pins = "gpd2-7";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi1_bus: spi1-bus {
> + samsung,pins = "gpd6-2", "gpd6-4", "gpd6-5";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c7_bus: hs-i2c7-bus {
> + samsung,pins = "gpd2-7", "gpd2-6";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi0_bus: spi0-bus {
> + samsung,pins = "gpd8-0", "gpd6-0", "gpd6-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c10_bus: hs-i2c10-bus {
> + samsung,pins = "gpg3-1", "gpg3-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + hs_i2c11_bus: hs-i2c11-bus {
> + samsung,pins = "gpg3-3", "gpg3-2";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi3_bus: spi3-bus {
> + samsung,pins = "gpg3-4", "gpg3-6", "gpg3-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + spi4_bus: spi4-bus {
> + samsung,pins = "gpv7-1", "gpv7-3", "gpv7-4";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_uart: fimc-is-uart {
> + samsung,pins = "gpc1-1", "gpc0-7";
> + samsung,pin-function = <3>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch0_i2c: fimc-is-ch0_i2c {
> + samsung,pins = "gpc2-1", "gpc2-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch0_mclk: fimc-is-ch0_mclk {
> + samsung,pins = "gpd7-0";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch1_i2c: fimc-is-ch1-i2c {
> + samsung,pins = "gpc2-3", "gpc2-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch1_mclk: fimc-is-ch1-mclk {
> + samsung,pins = "gpd7-1";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch2_i2c: fimc-is-ch2-i2c {
> + samsung,pins = "gpc2-5", "gpc2-4";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +
> + fimc_is_ch2_mclk: fimc-is-ch2-mclk {
> + samsung,pins = "gpd7-2";
> + samsung,pin-function = <2>;
> + samsung,pin-pud = <0>;
> + samsung,pin-drv = <0>;
> + };
> +};
> +
> +&pinctrl_touch {
> + gpj1: gpj1 {
> + gpio-controller;
> + #gpio-cells = <2>;
> +
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + hs_i2c5_bus: hs-i2c5-bus {
> + samsung,pins = "gpj1-1", "gpj1-0";
> + samsung,pin-function = <4>;
> + samsung,pin-pud = <3>;
> + samsung,pin-drv = <0>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> new file mode 100644
> index 000000000000..9be2978f1b9a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-g3d-sensor-conf.dtsi
> @@ -0,0 +1,23 @@
> +/*
> + * Device tree sources for Exynos5433 TMU sensor configuration
> + *
> + * Copyright (c) 2016 Jonghwa Lee <jonghwa3.lee@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal_exynos.h>
> +
> +#thermal-sensor-cells = <0>;
> +samsung,tmu_gain = <8>;
> +samsung,tmu_reference_voltage = <23>;
> +samsung,tmu_noise_cancel_mode = <4>;
> +samsung,tmu_efuse_value = <75>;
> +samsung,tmu_min_efuse_value = <40>;
> +samsung,tmu_max_efuse_value = <150>;
> +samsung,tmu_first_point_trim = <25>;
> +samsung,tmu_second_point_trim = <85>;
> +samsung,tmu_default_temp_offset = <50>;
> +samsung,tmu_mux_addr = <6>;
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> new file mode 100644
> index 000000000000..125fe58d77ce
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu-sensor-conf.dtsi
> @@ -0,0 +1,22 @@
> +/*
> + * Device tree sources for Exynos5433 TMU sensor configuration
> + *
> + * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal_exynos.h>
> +
> +#thermal-sensor-cells = <0>;
> +samsung,tmu_gain = <8>;
> +samsung,tmu_reference_voltage = <16>;
> +samsung,tmu_noise_cancel_mode = <4>;
> +samsung,tmu_efuse_value = <75>;
> +samsung,tmu_min_efuse_value = <40>;
> +samsung,tmu_max_efuse_value = <150>;
> +samsung,tmu_first_point_trim = <25>;
> +samsung,tmu_second_point_trim = <85>;
> +samsung,tmu_default_temp_offset = <50>;
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> new file mode 100644
> index 000000000000..ceaa05145b8a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433-tmu.dtsi
> @@ -0,0 +1,296 @@
> +/*
> + * Device tree sources for Exynos5433 thermal zone
> + *
> + * Copyright (c) 2016 Chanwoo Choi <cw00.choi@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> +thermal-zones {
> + atlas0_thermal: atlas0-thermal {
> + thermal-sensors = <&tmu_atlas0>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + atlas0_alert_0: atlas0-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_1: atlas0-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_2: atlas0-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_3: atlas0-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_4: atlas0-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_5: atlas0-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas0_alert_6: atlas0-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + /* Set maximum frequency as 1800MHz */
> + trip = <&atlas0_alert_0>;
> + cooling-device = <&cpu4 1 2>;
> + };
> + map1 {
> + /* Set maximum frequency as 1700MHz */
> + trip = <&atlas0_alert_1>;
> + cooling-device = <&cpu4 2 3>;
> + };
> + map2 {
> + /* Set maximum frequency as 1600MHz */
> + trip = <&atlas0_alert_2>;
> + cooling-device = <&cpu4 3 4>;
> + };
> + map3 {
> + /* Set maximum frequency as 1500MHz */
> + trip = <&atlas0_alert_3>;
> + cooling-device = <&cpu4 4 5>;
> + };
> + map4 {
> + /* Set maximum frequency as 1400MHz */
> + trip = <&atlas0_alert_4>;
> + cooling-device = <&cpu4 5 7>;
> + };
> + map5 {
> + /* Set maximum frequencyas 1200MHz */
> + trip = <&atlas0_alert_5>;
> + cooling-device = <&cpu4 7 9>;
> + };
> + map6 {
> + /* Set maximum frequency as 1000MHz */
> + trip = <&atlas0_alert_6>;
> + cooling-device = <&cpu4 9 14>;
> + };
> + };
> + };
> +
> + atlas1_thermal: atlas1-thermal {
> + thermal-sensors = <&tmu_atlas1>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + atlas1_alert_0: atlas1-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_1: atlas1-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_2: atlas1-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_3: atlas1-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_4: atlas1-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_5: atlas1-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + atlas1_alert_6: atlas1-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +
> + g3d_thermal: g3d-thermal {
> + thermal-sensors = <&tmu_g3d>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + g3d_alert_0: g3d-alert-0 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_1: g3d-alert-1 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_2: g3d-alert-2 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_3: g3d-alert-3 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_4: g3d-alert-4 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_5: g3d-alert-5 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + g3d_alert_6: g3d-alert-6 {
> + temperature = <100000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +
> + apollo_thermal: apollo-thermal {
> + thermal-sensors = <&tmu_apollo>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + apollo_alert_0: apollo-alert-0 {
> + temperature = <65000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_1: apollo-alert-1 {
> + temperature = <70000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_2: apollo-alert-2 {
> + temperature = <75000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_3: apollo-alert-3 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_4: apollo-alert-4 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_5: apollo-alert-5 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + apollo_alert_6: apollo-alert-6 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> +
> + cooling-maps {
> + map0 {
> + /* Set maximum frequency as 1200MHz */
> + trip = <&apollo_alert_2>;
> + cooling-device = <&cpu0 1 2>;
> + };
> + map1 {
> + /* Set maximum frequency as 1100MHz */
> + trip = <&apollo_alert_3>;
> + cooling-device = <&cpu0 2 3>;
> + };
> + map2 {
> + /* Set maximum frequency as 1000MHz */
> + trip = <&apollo_alert_4>;
> + cooling-device = <&cpu0 3 4>;
> + };
> + map3 {
> + /* Set maximum frequency as 900MHz */
> + trip = <&apollo_alert_5>;
> + cooling-device = <&cpu0 4 5>;
> + };
> + map4 {
> + /* Set maximum frequency as 800MHz */
> + trip = <&apollo_alert_6>;
> + cooling-device = <&cpu0 5 9>;
> + };
> + };
> + };
> +
> + isp_thermal: isp-thermal {
> + thermal-sensors = <&tmu_isp>;
> + polling-delay-passive = <0>;
> + polling-delay = <0>;
> + trips {
> + isp_alert_0: isp-alert-0 {
> + temperature = <80000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_1: isp-alert-1 {
> + temperature = <85000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_2: isp-alert-2 {
> + temperature = <90000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_3: isp-alert-3 {
> + temperature = <95000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_4: isp-alert-4 {
> + temperature = <100000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_5: isp-alert-5 {
> + temperature = <105000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + isp_alert_6: isp-alert-6 {
> + temperature = <110000>; /* millicelsius */
> + hysteresis = <1000>; /* millicelsius */
> + type = "active";
> + };
> + };
> + };
> +};
> +};
> diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> new file mode 100644
> index 000000000000..1188630823a7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
> @@ -0,0 +1,1356 @@
> +/*
> + * Samsung's Exynos5433 SoC device tree source
> + *
> + * Copyright (c) 2016 Samsung Electronics Co., Ltd.
> + *
> + * Samsung's Exynos5433 SoC device nodes are listed in this file.
> + * Exynos5433 based board files can include this file and provide
> + * values for board specific bindings.
> + *
> + * Note: This file does not include device nodes for all the controllers in
> + * Exynos5433 SoC. As device tree coverage for Exynos5433 increases,
> + * additional nodes can be added to this file.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <dt-bindings/clock/exynos5433.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "samsung,exynos5433";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + interrupt-parent = <&gic>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x100>;
> + clock-frequency = <1300000000>;
> + clocks = <&cmu_apollo CLK_SCLK_APOLLO>;
> + clock-names = "apolloclk";
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu1: cpu@101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x101>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu2: cpu@102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x102>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu3: cpu@103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x103>;
> + clock-frequency = <1300000000>;
> + operating-points-v2 = <&cluster_a53_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu4: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x0>;
> + clock-frequency = <1900000000>;
> + clocks = <&cmu_atlas CLK_SCLK_ATLAS>;
> + clock-names = "atlasclk";
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu5: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x1>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu6: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x2>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> +
> + cpu7: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a57", "arm,armv8";
> + enable-method = "psci";
> + reg = <0x3>;
> + clock-frequency = <1900000000>;
> + operating-points-v2 = <&cluster_a57_opp_table>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + cluster_a53_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp@400000000 {
> + opp-hz = /bits/ 64 <400000000>;
> + opp-microvolt = <900000>;
> + };
> + opp@500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <925000>;
> + };
> + opp@600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <950000>;
> + };
> + opp@700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <975000>;
> + };
> + opp@800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <1000000>;
> + };
> + opp@900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <1050000>;
> + };
> + opp@1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <1075000>;
> + };
> + opp@1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1112500>;
> + };
> + opp@1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1112500>;
> + };
> + opp@1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1150000>;
> + };
> + };
> +
> + cluster_a57_opp_table: opp_table1 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> + opp@500000000 {
> + opp-hz = /bits/ 64 <500000000>;
> + opp-microvolt = <900000>;
> + };
> + opp@600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <900000>;
> + };
> + opp@700000000 {
> + opp-hz = /bits/ 64 <700000000>;
> + opp-microvolt = <912500>;
> + };
> + opp@800000000 {
> + opp-hz = /bits/ 64 <800000000>;
> + opp-microvolt = <912500>;
> + };
> + opp@900000000 {
> + opp-hz = /bits/ 64 <900000000>;
> + opp-microvolt = <937500>;
> + };
> + opp@1000000000 {
> + opp-hz = /bits/ 64 <1000000000>;
> + opp-microvolt = <975000>;
> + };
> + opp@1100000000 {
> + opp-hz = /bits/ 64 <1100000000>;
> + opp-microvolt = <1012500>;
> + };
> + opp@1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1037500>;
> + };
> + opp@1300000000 {
> + opp-hz = /bits/ 64 <1300000000>;
> + opp-microvolt = <1062500>;
> + };
> + opp@1400000000 {
> + opp-hz = /bits/ 64 <1400000000>;
> + opp-microvolt = <1087500>;
> + };
> + opp@1500000000 {
> + opp-hz = /bits/ 64 <1500000000>;
> + opp-microvolt = <1125000>;
> + };
> + opp@1600000000 {
> + opp-hz = /bits/ 64 <1600000000>;
> + opp-microvolt = <1137500>;
> + };
> + opp@1700000000 {
> + opp-hz = /bits/ 64 <1700000000>;
> + opp-microvolt = <1175000>;
> + };
> + opp@1800000000 {
> + opp-hz = /bits/ 64 <1800000000>;
> + opp-microvolt = <1212500>;
> + };
> + opp@1900000000 {
> + opp-hz = /bits/ 64 <1900000000>;
> + opp-microvolt = <1262500>;
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci";
> + method = "smc";
> + cpu_off = <0x84000002>;
> + cpu_on = <0xC4000003>;
> + };
> +
> + reboot: syscon-reboot {
> + compatible = "syscon-reboot";
> + regmap = <&pmu_system_controller>;
> + offset = <0x400>; /* SWRESET */
> + mask = <0x1>;
> + };
> +
> + soc: soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0x0 0x0 0x18000000>;
> +
> + chipid@10000000 {
> + compatible = "samsung,exynos4210-chipid";
> + reg = <0x10000000 0x100>;
> + };
> +
> + xxti: xxti {
> + compatible = "fixed-clock";
> + clock-output-names = "oscclk";
> + #clock-cells = <0>;
> + };
> +
> + cmu_top: clock-controller@10030000 {
> + compatible = "samsung,exynos5433-cmu-top";
> + reg = <0x10030000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_mphy_pll",
> + "sclk_mfc_pll",
> + "sclk_bus_pll";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_MPHY_PLL>,
> + <&cmu_mif CLK_SCLK_MFC_PLL>,
> + <&cmu_mif CLK_SCLK_BUS_PLL>;
> + };
> +
> + cmu_cpif: clock-controller@10fc0000 {
> + compatible = "samsung,exynos5433-cmu-cpif";
> + reg = <0x10fc0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk";
> + clocks = <&xxti>;
> + };
> +
> + cmu_mif: clock-controller@105b0000 {
> + compatible = "samsung,exynos5433-cmu-mif";
> + reg = <0x105b0000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_mphy_pll";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_MPHY_PLL>;
> + };
> +
> + cmu_peric: clock-controller@14c80000 {
> + compatible = "samsung,exynos5433-cmu-peric";
> + reg = <0x14c80000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_peris: clock-controller@0x10040000 {
> + compatible = "samsung,exynos5433-cmu-peris";
> + reg = <0x10040000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_fsys: clock-controller@156e0000 {
> + compatible = "samsung,exynos5433-cmu-fsys";
> + reg = <0x156e0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_ufs_mphy",
> + "div_aclk_fsys_200",
> + "sclk_pcie_100_fsys",
> + "sclk_ufsunipro_fsys",
> + "sclk_mmc2_fsys",
> + "sclk_mmc1_fsys",
> + "sclk_mmc0_fsys",
> + "sclk_usbhost30_fsys",
> + "sclk_usbdrd30_fsys";
> + clocks = <&xxti>,
> + <&cmu_cpif CLK_SCLK_UFS_MPHY>,
> + <&cmu_top CLK_DIV_ACLK_FSYS_200>,
> + <&cmu_top CLK_SCLK_PCIE_100_FSYS>,
> + <&cmu_top CLK_SCLK_UFSUNIPRO_FSYS>,
> + <&cmu_top CLK_SCLK_MMC2_FSYS>,
> + <&cmu_top CLK_SCLK_MMC1_FSYS>,
> + <&cmu_top CLK_SCLK_MMC0_FSYS>,
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>;
> + };
> +
> + cmu_g2d: clock-controller@12460000 {
> + compatible = "samsung,exynos5433-cmu-g2d";
> + reg = <0x12460000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_g2d_266",
> + "aclk_g2d_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_G2D_266>,
> + <&cmu_top CLK_ACLK_G2D_400>;
> + };
> +
> + cmu_disp: clock-controller@13b90000 {
> + compatible = "samsung,exynos5433-cmu-disp";
> + reg = <0x13b90000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_dsim1_disp",
> + "sclk_dsim0_disp",
> + "sclk_dsd_disp",
> + "sclk_decon_tv_eclk_disp",
> + "sclk_decon_vclk_disp",
> + "sclk_decon_eclk_disp",
> + "sclk_decon_tv_vclk_disp",
> + "aclk_disp_333";
> + clocks = <&xxti>,
> + <&cmu_mif CLK_SCLK_DSIM1_DISP>,
> + <&cmu_mif CLK_SCLK_DSIM0_DISP>,
> + <&cmu_mif CLK_SCLK_DSD_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_TV_ECLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_VCLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_ECLK_DISP>,
> + <&cmu_mif CLK_SCLK_DECON_TV_VCLK_DISP>,
> + <&cmu_mif CLK_ACLK_DISP_333>;
> + };
> +
> + cmu_aud: clock-controller@114c0000 {
> + compatible = "samsung,exynos5433-cmu-aud";
> + reg = <0x114c0000 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> + cmu_bus0: clock-controller@13600000 {
> + compatible = "samsung,exynos5433-cmu-bus0";
> + reg = <0x13600000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "aclk_bus0_400";
> + clocks = <&cmu_top CLK_ACLK_BUS0_400>;
> + };
> +
> + cmu_bus1: clock-controller@14800000 {
> + compatible = "samsung,exynos5433-cmu-bus1";
> + reg = <0x14800000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "aclk_bus1_400";
> + clocks = <&cmu_top CLK_ACLK_BUS1_400>;
> + };
> +
> + cmu_bus2: clock-controller@13400000 {
> + compatible = "samsung,exynos5433-cmu-bus2";
> + reg = <0x13400000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_bus2_400";
> + clocks = <&xxti>, <&cmu_mif CLK_ACLK_BUS2_400>;
> + };
> +
> + cmu_g3d: clock-controller@14aa0000 {
> + compatible = "samsung,exynos5433-cmu-g3d";
> + reg = <0x14aa0000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_g3d_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_G3D_400>;
> + };
> +
> + cmu_gscl: clock-controller@13cf0000 {
> + compatible = "samsung,exynos5433-cmu-gscl";
> + reg = <0x13cf0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_gscl_111",
> + "aclk_gscl_333";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_GSCL_111>,
> + <&cmu_top CLK_ACLK_GSCL_333>;
> + };
> +
> + cmu_apollo: clock-controller@11900000 {
> + compatible = "samsung,exynos5433-cmu-apollo";
> + reg = <0x11900000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "sclk_bus_pll_apollo";
> + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_APOLLO>;
> + };
> +
> + cmu_atlas: clock-controller@11800000 {
> + compatible = "samsung,exynos5433-cmu-atlas";
> + reg = <0x11800000 0x2000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "sclk_bus_pll_atlas";
> + clocks = <&xxti>, <&cmu_mif CLK_SCLK_BUS_PLL_ATLAS>;
> + };
> +
> + cmu_mscl: clock-controller@105d0000 {
> + compatible = "samsung,exynos5433-cmu-mscl";
> + reg = <0x150d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_jpeg_mscl",
> + "aclk_mscl_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_SCLK_JPEG_MSCL>,
> + <&cmu_top CLK_ACLK_MSCL_400>;
> + };
> +
> + cmu_mfc: clock-controller@15280000 {
> + compatible = "samsung,exynos5433-cmu-mfc";
> + reg = <0x15280000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_mfc_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
> + };
> +
> + cmu_hevc: clock-controller@14f80000 {
> + compatible = "samsung,exynos5433-cmu-hevc";
> + reg = <0x14f80000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk", "aclk_hevc_400";
> + clocks = <&xxti>, <&cmu_top CLK_ACLK_HEVC_400>;
> + };
> +
> + cmu_isp: clock-controller@146d0000 {
> + compatible = "samsung,exynos5433-cmu-isp";
> + reg = <0x146d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_isp_dis_400",
> + "aclk_isp_400";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_ISP_DIS_400>,
> + <&cmu_top CLK_ACLK_ISP_400>;
> + };
> +
> + cmu_cam0: clock-controller@120d0000 {
> + compatible = "samsung,exynos5433-cmu-cam0";
> + reg = <0x120d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "aclk_cam0_333",
> + "aclk_cam0_400",
> + "aclk_cam0_552";
> + clocks = <&xxti>,
> + <&cmu_top CLK_ACLK_CAM0_333>,
> + <&cmu_top CLK_ACLK_CAM0_400>,
> + <&cmu_top CLK_ACLK_CAM0_552>;
> + };
> +
> + cmu_cam1: clock-controller@145d0000 {
> + compatible = "samsung,exynos5433-cmu-cam1";
> + reg = <0x145d0000 0x1000>;
> + #clock-cells = <1>;
> +
> + clock-names = "oscclk",
> + "sclk_isp_uart_cam1",
> + "sclk_isp_spi1_cam1",
> + "sclk_isp_spi0_cam1",
> + "aclk_cam1_333",
> + "aclk_cam1_400",
> + "aclk_cam1_552";
> + clocks = <&xxti>,
> + <&cmu_top CLK_SCLK_ISP_UART_CAM1>,
> + <&cmu_top CLK_SCLK_ISP_SPI1_CAM1>,
> + <&cmu_top CLK_SCLK_ISP_SPI0_CAM1>,
> + <&cmu_top CLK_ACLK_CAM1_333>,
> + <&cmu_top CLK_ACLK_CAM1_400>,
> + <&cmu_top CLK_ACLK_CAM1_552>;
> + };
> +
> + tmu_atlas0: tmu@10060000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10060000 0x200>;
> + interrupts = <GIC_SPI 95 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU0>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_atlas1: tmu@10068000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10068000 0x200>;
> + interrupts = <GIC_SPI 96 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU0_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU0>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_g3d: tmu@10070000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10070000 0x200>;
> + interrupts = <GIC_SPI 99 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-g3d-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_apollo: tmu@10078000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x10078000 0x200>;
> + interrupts = <GIC_SPI 115 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + tmu_isp: tmu@1007c000 {
> + compatible = "samsung,exynos5433-tmu";
> + reg = <0x1007c000 0x200>;
> + interrupts = <GIC_SPI 94 0>;
> + clocks = <&cmu_peris CLK_PCLK_TMU1_APBIF>,
> + <&cmu_peris CLK_SCLK_TMU1>;
> + clock-names = "tmu_apbif", "tmu_sclk";
> + #include "exynos5433-tmu-sensor-conf.dtsi"
> + status = "disabled";
> + };
> +
> + mct@101c0000 {
> + compatible = "samsung,exynos4210-mct";
> + reg = <0x101c0000 0x800>;
> + interrupts = <GIC_SPI 102 0>, <GIC_SPI 103 0>,
> + <GIC_SPI 104 0>, <GIC_SPI 105 0>,
> + <GIC_SPI 106 0>, <GIC_SPI 107 0>,
> + <GIC_SPI 108 0>, <GIC_SPI 109 0>,
> + <GIC_SPI 110 0>, <GIC_SPI 111 0>,
> + <GIC_SPI 112 0>, <GIC_SPI 113 0>;
> + clocks = <&xxti>, <&cmu_peris CLK_PCLK_MCT>;
> + clock-names = "fin_pll", "mct";
> + };
> +
> + pinctrl_alive: pinctrl@10580000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
> +
> + wakeup-interrupt-controller {
> + compatible = "samsung,exynos7-wakeup-eint";
> + interrupts = <GIC_SPI 16 0>;
> + };
> + };
> +
> + pinctrl_aud: pinctrl@114b0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x114b0000 0x1000>;
> + interrupts = <GIC_SPI 68 0>;
> + };
> +
> + pinctrl_cpif: pinctrl@10fe0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x10fe0000 0x1000>;
> + interrupts = <GIC_SPI 179 0>;
> + };
> +
> + pinctrl_ese: pinctrl@14ca0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14ca0000 0x1000>;
> + interrupts = <GIC_SPI 413 0>;
> + };
> +
> + pinctrl_finger: pinctrl@14cb0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cb0000 0x1000>;
> + interrupts = <GIC_SPI 414 0>;
> + };
> +
> + pinctrl_fsys: pinctrl@15690000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x15690000 0x1000>;
> + interrupts = <GIC_SPI 229 0>;
> + };
> +
> + pinctrl_imem: pinctrl@11090000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x11090000 0x1000>;
> + interrupts = <GIC_SPI 325 0>;
> + };
> +
> + pinctrl_nfc: pinctrl@14cd0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cd0000 0x1000>;
> + interrupts = <GIC_SPI 441 0>;
> + };
> +
> + pinctrl_peric: pinctrl@14cc0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14cc0000 0x1100>;
> + interrupts = <GIC_SPI 440 0>;
> + };
> +
> + pinctrl_touch: pinctrl@14ce0000 {
> + compatible = "samsung,exynos5433-pinctrl";
> + reg = <0x14ce0000 0x1100>;
> + interrupts = <GIC_SPI 442 0>;
> + };
> +
> + pmu_system_controller: system-controller@105c0000 {
> + compatible = "samsung,exynos5433-pmu", "syscon";
> + reg = <0x105c0000 0x5008>;
> + #clock-cells = <1>;
> + clock-names = "clkout16";
> + clocks = <&xxti>;
> + };
> +
> + gic: interrupt-controller@11001000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x11001000 0x1000>,
> + <0x11002000 0x2000>,
> + <0x11004000 0x2000>,
> + <0x11006000 0x2000>;
> + interrupts = <GIC_PPI 9 0xf04>;
> + };
> +
> + mipi_phy: video-phy@105c0710 {
> + compatible = "samsung,exynos5433-mipi-video-phy";
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + samsung,cam0-sysreg = <&syscon_cam0>;
> + samsung,cam1-sysreg = <&syscon_cam1>;
> + samsung,disp-sysreg = <&syscon_disp>;
> + };
> +
> + decon: decon@13800000 {
> + compatible = "samsung,exynos5433-decon";
> + reg = <0x13800000 0x2104>;
> + clocks = <&cmu_disp CLK_PCLK_DECON>,
> + <&cmu_disp CLK_ACLK_DECON>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_ACLK_XIU_DECON0X>,
> + <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_SCLK_DECON_VCLK>,
> + <&cmu_disp CLK_SCLK_DECON_ECLK>;
> + clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
> + "aclk_xiu_decon0x", "pclk_smmu_decon0x",
> + "sclk_decon_vclk", "sclk_decon_eclk";
> + interrupt-names = "fifo", "vsync", "lcd_sys";
> + interrupts = <GIC_SPI 201 0>, <GIC_SPI 202 0>,
> + <GIC_SPI 203 0>;
> + samsung,disp-sysreg = <&syscon_disp>;
> + status = "disabled";
> + iommus = <&sysmmu_decon0x>, <&sysmmu_decon1x>;
> + iommu-names = "m0", "m1";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + decon_to_mic: endpoint {
> + remote-endpoint =
> + <&mic_to_decon>;
> + };
> + };
> + };
> + };
> +
> + dsi: dsi@13900000 {
> + compatible = "samsung,exynos5433-mipi-dsi";
> + reg = <0x13900000 0xC0>;
> + interrupts = <GIC_SPI 205 0>;
> + phys = <&mipi_phy 1>;
> + phy-names = "dsim";
> + clocks = <&cmu_disp CLK_PCLK_DSIM0>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
> + <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
> + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
> + <&cmu_disp CLK_SCLK_DSIM0>;
> + clock-names = "bus_clk",
> + "phyclk_mipidphy0_bitclkdiv8",
> + "phyclk_mipidphy0_rxclkesc0",
> + "sclk_rgb_vclk_to_dsim0",
> + "sclk_mipi";
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + dsi_to_mic: endpoint {
> + remote-endpoint = <&mic_to_dsi>;
> + };
> + };
> + };
> + };
> +
> + mic: mic@13930000 {
> + compatible = "samsung,exynos5433-mic";
> + reg = <0x13930000 0x48>;
> + clocks = <&cmu_disp CLK_PCLK_MIC0>,
> + <&cmu_disp CLK_SCLK_RGB_VCLK_TO_MIC0>;
> + clock-names = "pclk_mic0", "sclk_rgb_vclk_to_mic0";
> + samsung,disp-syscon = <&syscon_disp>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mic_to_decon: endpoint {
> + remote-endpoint =
> + <&decon_to_mic>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> + mic_to_dsi: endpoint {
> + remote-endpoint = <&dsi_to_mic>;
> + };
> + };
> + };
> + };
> +
> + syscon_disp: syscon@13b80000 {
> + compatible = "syscon";
> + reg = <0x13b80000 0x1010>;
> + };
> +
> + syscon_cam0: syscon@120f0000 {
> + compatible = "syscon";
> + reg = <0x120f0000 0x1020>;
> + };
> +
> + syscon_cam1: syscon@145f0000 {
> + compatible = "syscon";
> + reg = <0x145f0000 0x1038>;
> + };
> +
> + sysmmu_decon0x: sysmmu@0x13a00000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a00000 0x1000>;
> + interrupts = <GIC_SPI 192 0>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON0X>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON0X>;
> + #iommu-cells = <0>;
> + };
> +
> + sysmmu_decon1x: sysmmu@0x13a10000 {
> + compatible = "samsung,exynos-sysmmu";
> + reg = <0x13a10000 0x1000>;
> + interrupts = <GIC_SPI 194 0>;
> + clock-names = "pclk", "aclk";
> + clocks = <&cmu_disp CLK_PCLK_SMMU_DECON1X>,
> + <&cmu_disp CLK_ACLK_SMMU_DECON1X>;
> + #iommu-cells = <0>;
> + };
> +
> + serial_0: serial@14c10000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c10000 0x100>;
> + interrupts = <GIC_SPI 421 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART0>,
> + <&cmu_peric CLK_SCLK_UART0>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_bus>;
> + status = "disabled";
> + };
> +
> + serial_1: serial@14c20000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c20000 0x100>;
> + interrupts = <GIC_SPI 422 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART1>,
> + <&cmu_peric CLK_SCLK_UART1>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_bus>;
> + status = "disabled";
> + };
> +
> + serial_2: serial@14c30000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x14c30000 0x100>;
> + interrupts = <GIC_SPI 423 0>;
> + clocks = <&cmu_peric CLK_PCLK_UART2>,
> + <&cmu_peric CLK_SCLK_UART2>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_bus>;
> + status = "disabled";
> + };
> +
> + spi_0: spi@14d20000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d20000 0x100>;
> + interrupts = <GIC_SPI 432 0>;
> + dmas = <&pdma0 9>, <&pdma0 8>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI0>,
> + <&cmu_peric CLK_SCLK_SPI0>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI0>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_1: spi@14d30000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d30000 0x100>;
> + interrupts = <GIC_SPI 433 0>;
> + dmas = <&pdma0 11>, <&pdma0 10>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI1>,
> + <&cmu_peric CLK_SCLK_SPI1>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI1>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi1_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_2: spi@14d40000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d40000 0x100>;
> + interrupts = <GIC_SPI 434 0>;
> + dmas = <&pdma0 13>, <&pdma0 12>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI2>,
> + <&cmu_peric CLK_SCLK_SPI2>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI2>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi2_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_3: spi@14d50000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d50000 0x100>;
> + interrupts = <GIC_SPI 447 0>;
> + dmas = <&pdma0 23>, <&pdma0 22>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI3>,
> + <&cmu_peric CLK_SCLK_SPI3>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI3>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi3_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + spi_4: spi@14d00000 {
> + compatible = "samsung,exynos5433-spi";
> + reg = <0x14d00000 0x100>;
> + interrupts = <GIC_SPI 412 0>;
> + dmas = <&pdma0 25>, <&pdma0 24>;
> + dma-names = "tx", "rx";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_peric CLK_PCLK_SPI4>,
> + <&cmu_peric CLK_SCLK_SPI4>,
> + <&cmu_peric CLK_SCLK_IOCLK_SPI4>;
> + clock-names = "spi", "spi_busclk0", "spi_ioclk";
> + samsung,spi-src-clk = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi4_bus>;
> + num-cs = <1>;
> + status = "disabled";
> + };
> +
> + adc: adc@14d10000 {
> + compatible = "samsung,exynos7-adc";
> + reg = <0x14d10000 0x100>;
> + interrupts = <GIC_SPI 438 0>;
> + clock-names = "adc";
> + clocks = <&cmu_peric CLK_PCLK_ADCIF>;
> + #io-channel-cells = <1>;
> + io-channel-ranges;
> + status = "disabled";
> + };
> +
> + pwm: pwm@14dd0000 {
> + compatible = "samsung,exynos4210-pwm";
> + reg = <0x14dd0000 0x100>;
> + interrupts = <GIC_SPI 416 0>, <GIC_SPI 417 0>,
> + <GIC_SPI 418 0>, <GIC_SPI 419 0>,
> + <GIC_SPI 420 0>;
> + samsung,pwm-outputs = <0>, <1>, <2>, <3>;
> + clocks = <&cmu_peric CLK_PCLK_PWM>;
> + clock-names = "timers";
> + #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> + hsi2c_0: hsi2c@14e40000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e40000 0x1000>;
> + interrupts = <GIC_SPI 428 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c0_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C0>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_1: hsi2c@14e50000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e50000 0x1000>;
> + interrupts = <GIC_SPI 429 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c1_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C1>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_2: hsi2c@14e60000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e60000 0x1000>;
> + interrupts = <GIC_SPI 430 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c2_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C2>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_3: hsi2c@14e70000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14e70000 0x1000>;
> + interrupts = <GIC_SPI 431 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c3_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C3>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_4: hsi2c@14ec0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ec0000 0x1000>;
> + interrupts = <GIC_SPI 424 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c4_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C4>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_5: hsi2c@14ed0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ed0000 0x1000>;
> + interrupts = <GIC_SPI 425 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c5_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C5>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_6: hsi2c@14ee0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ee0000 0x1000>;
> + interrupts = <GIC_SPI 426 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c6_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C6>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_7: hsi2c@14ef0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14ef0000 0x1000>;
> + interrupts = <GIC_SPI 427 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c7_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C7>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_8: hsi2c@14d90000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14d90000 0x1000>;
> + interrupts = <GIC_SPI 443 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c8_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C8>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_9: hsi2c@14da0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14da0000 0x1000>;
> + interrupts = <GIC_SPI 444 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c9_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C9>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_10: hsi2c@14de0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14de0000 0x1000>;
> + interrupts = <GIC_SPI 445 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c10_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C10>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + hsi2c_11: hsi2c@14df0000 {
> + compatible = "samsung,exynos7-hsi2c";
> + reg = <0x14df0000 0x1000>;
> + interrupts = <GIC_SPI 446 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&hs_i2c11_bus>;
> + clocks = <&cmu_peric CLK_PCLK_HSI2C11>;
> + clock-names = "hsi2c";
> + status = "disabled";
> + };
> +
> + usbdrd30: usb@15400000 {
> + compatible = "samsung,exynos5250-dwusb3";
> + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>,
> + <&cmu_fsys CLK_SCLK_USBDRD30>;
> + clock-names = "usbdrd30", "usbdrd30_susp_clk";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_SCLK_USBDRD30_USER>,
> + <&cmu_top CLK_MOUT_SCLK_USBDRD30>,
> + <&cmu_top CLK_DIV_SCLK_USBDRD30>;
> + assigned-clock-parents =
> + <&cmu_top CLK_SCLK_USBDRD30_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> + assigned-clock-rates = <0>, <0>, <66700000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + dwc3@15400000 {
> + compatible = "snps,dwc3";
> + reg = <0x15400000 0x10000>;
> + interrupts = <GIC_SPI 231 0>;
> + phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> + };
> +
> + usbdrd30_phy: phy@15500000 {
> + compatible = "samsung,exynos5433-usbdrd-phy";
> + reg = <0x15500000 0x100>;
> + clocks = <&cmu_fsys CLK_ACLK_USBDRD30>, <&xxti>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK>,
> + <&cmu_fsys CLK_SCLK_USBDRD30>;
> + clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> + "itp";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER>;
> + assigned-clock-parents =
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY>;
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + status = "disabled";
> + };
> +
> + usbhost30_phy: phy@15580000 {
> + compatible = "samsung,exynos5433-usbdrd-phy";
> + reg = <0x15580000 0x100>;
> + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>, <&xxti>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK>,
> + <&cmu_fsys CLK_SCLK_USBHOST30>;
> + clock-names = "phy", "ref", "phy_utmi", "phy_pipe",
> + "itp";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER>,
> + <&cmu_fsys CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER>;
> + assigned-clock-parents =
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY>,
> + <&cmu_fsys CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY>;
> + #phy-cells = <1>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + status = "disabled";
> + };
> +
> + usbhost30: usb@15a00000 {
> + compatible = "samsung,exynos5250-dwusb3";
> + clocks = <&cmu_fsys CLK_ACLK_USBHOST30>,
> + <&cmu_fsys CLK_SCLK_USBHOST30>;
> + clock-names = "usbdrd30", "usbdrd30_susp_clk";
> + assigned-clocks =
> + <&cmu_fsys CLK_MOUT_SCLK_USBHOST30_USER>,
> + <&cmu_top CLK_MOUT_SCLK_USBHOST30>,
> + <&cmu_top CLK_DIV_SCLK_USBHOST30>;
> + assigned-clock-parents =
> + <&cmu_top CLK_SCLK_USBHOST30_FSYS>,
> + <&cmu_top CLK_MOUT_BUS_PLL_USER>;
> + assigned-clock-rates = <0>, <0>, <66700000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + status = "disabled";
> +
> + usbdrd_dwc3_0: dwc3@15a00000 {
> + compatible = "snps,dwc3";
> + reg = <0x15a00000 0x10000>;
> + interrupts = <GIC_SPI 244 0>;
> + phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
> + phy-names = "usb2-phy", "usb3-phy";
> + };
> + };
> +
> + mshc_0: mshc@15540000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 225 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15540000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC0>,
> + <&cmu_fsys CLK_SCLK_MMC0>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + mshc_1: mshc@15550000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 226 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15550000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC1>,
> + <&cmu_fsys CLK_SCLK_MMC1>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + mshc_2: mshc@15560000 {
> + compatible = "samsung,exynos7-dw-mshc-smu";
> + interrupts = <GIC_SPI 227 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x15560000 0x2000>;
> + clocks = <&cmu_fsys CLK_ACLK_MMC2>,
> + <&cmu_fsys CLK_SCLK_MMC2>;
> + clock-names = "biu", "ciu";
> + fifo-depth = <0x40>;
> + status = "disabled";
> + };
> +
> + amba {
> + compatible = "arm,amba-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + pdma0: pdma@15610000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x15610000 0x1000>;
> + interrupts = <GIC_SPI 228 0>;
> + clocks = <&cmu_fsys CLK_PDMA0>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> +
> + pdma1: pdma@15600000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x15600000 0x1000>;
> + interrupts = <GIC_SPI 246 0>;
> + clocks = <&cmu_fsys CLK_PDMA1>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> + };
> +
> + audio-subsystem@11400000 {
> + compatible = "samsung,exynos5433-lpass";
> + reg = <0x11400000 0x100>, <0x11500000 0x08>;
> + samsung,pmu-syscon = <&pmu_system_controller>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + adma: adma@11420000 {
> + compatible = "arm,pl330", "arm,primecell";
> + reg = <0x11420000 0x1000>;
> + interrupts = <GIC_SPI 73 0>;
> + clocks = <&cmu_aud CLK_ACLK_DMAC>;
> + clock-names = "apb_pclk";
> + #dma-cells = <1>;
> + #dma-channels = <8>;
> + #dma-requests = <32>;
> + };
> +
> + i2s0: i2s0@11440000 {
> + compatible = "samsung,exynos7-i2s";
> + reg = <0x11440000 0x100>;
> + dmas = <&adma 0 &adma 2>;
> + dma-names = "tx", "rx";
> + interrupts = <GIC_SPI 70 0>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&cmu_aud CLK_PCLK_AUD_I2S>,
> + <&cmu_aud CLK_SCLK_AUD_I2S>,
> + <&cmu_aud CLK_SCLK_I2S_BCLK>;
> + clock-names = "iis", "i2s_opclk0", "i2s_opclk1";
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2s0_bus>;
> + status = "disabled";
> + };
> +
> + serial_3: serial@11460000 {
> + compatible = "samsung,exynos5433-uart";
> + reg = <0x11460000 0x100>;
> + interrupts = <GIC_SPI 67 0>;
> + clocks = <&cmu_aud CLK_PCLK_AUD_UART>,
> + <&cmu_aud CLK_SCLK_AUD_UART>;
> + clock-names = "uart", "clk_uart_baud0";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart_aud_bus>;
> + status = "disabled";
> + };
> + };
> + };
> +
> + timer: timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 14
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 11
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>,
> + <GIC_PPI 10
> + (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
> + };
> +};
> +
> +#include "exynos5433-pinctrl.dtsi"
> +#include "exynos5433-tmu.dtsi"
> --
> 1.9.1
>
^ permalink raw reply
* [PATCH 2/2] Documentation: DT: Add bmi160 imu binding
From: Marcin Niestroj @ 2016-11-03 11:25 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
Daniel Baluta, Gregor Boirie, Sanchayan Maity, Rob Herring,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Marcin Niestroj
In-Reply-To: <20161103112527.29623-1-m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
This adds documentation for Bosch BMI160 Inertial Measurement Unit
device-tree bindings.
Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
---
.../devicetree/bindings/iio/imu/bmi160.txt | 34 ++++++++++++++++++++++
1 file changed, 34 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/imu/bmi160.txt
diff --git a/Documentation/devicetree/bindings/iio/imu/bmi160.txt b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
new file mode 100644
index 0000000..b02ef3e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/imu/bmi160.txt
@@ -0,0 +1,34 @@
+Bosch BMI160 - Inertial Measurement Unit with Accelerometer, Gyroscope
+and externally connectable Magnetometer
+
+https://www.bosch-sensortec.com/bst/products/all_products/bmi160
+
+Required properties:
+ - compatible : should be "bosch,bmi160"
+ - reg : the I2C address or SPI chip select number of the sensor
+ - spi-max-frequency : set maximum clock frequency (only for SPI)
+
+Optional properties:
+ - interrupt-parent : should be the phandle of the interrupt controller
+ - interrupts : interrupt mapping for GPIO IRQ, must be IRQ_TYPE_LEVEL_LOW
+ - interrupt-names : set to "INT2" if using INT2 pin
+
+Examples:
+
+bmi160@68 {
+ compatible = "bosch,bmi160";
+ reg = <0x68>;
+
+ interrupt-parent = <&gpio4>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+};
+
+bmi160@0 {
+ compatible = "bosch,bmi160";
+ reg = <0>;
+ spi-max-frequency = <10000000>;
+
+ interrupt-parent = <&gpio2>;
+ interrupts = <12 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "INT2";
+};
--
2.10.1
--
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^ permalink raw reply related
* [PATCH 1/2] iio: bmi160: Support hardware fifo
From: Marcin Niestroj @ 2016-11-03 11:25 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Hartmut Knaack, Lars-Peter Clausen, Peter Meerwald-Stadler,
Daniel Baluta, Gregor Boirie, Sanchayan Maity, Rob Herring,
Mark Rutland, linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Marcin Niestroj
This patch was developed primarily based on bmc150_accel hardware fifo
implementation.
IRQ handler was added, which for now is responsible only for handling
watermark interrupts. The BMI160 chip has two interrupt outputs. By
default INT is considered to be connected. If INT2 is used instead, the
interrupt-names device-tree property can be used to specify that.
Signed-off-by: Marcin Niestroj <m.niestroj-z3quKL4iOrmQ6ZAhV5LmOA@public.gmane.org>
---
drivers/iio/imu/bmi160/bmi160.h | 3 +-
drivers/iio/imu/bmi160/bmi160_core.c | 633 +++++++++++++++++++++++++++++++++--
drivers/iio/imu/bmi160/bmi160_i2c.c | 7 +-
drivers/iio/imu/bmi160/bmi160_spi.c | 3 +-
4 files changed, 618 insertions(+), 28 deletions(-)
diff --git a/drivers/iio/imu/bmi160/bmi160.h b/drivers/iio/imu/bmi160/bmi160.h
index d2ae6ed..4a7c10e 100644
--- a/drivers/iio/imu/bmi160/bmi160.h
+++ b/drivers/iio/imu/bmi160/bmi160.h
@@ -4,7 +4,8 @@
extern const struct regmap_config bmi160_regmap_config;
int bmi160_core_probe(struct device *dev, struct regmap *regmap,
- const char *name, bool use_spi);
+ const char *name, int irq,
+ bool use_spi, bool block_supported);
void bmi160_core_remove(struct device *dev);
#endif /* BMI160_H_ */
diff --git a/drivers/iio/imu/bmi160/bmi160_core.c b/drivers/iio/imu/bmi160/bmi160_core.c
index e0251b8..153734c 100644
--- a/drivers/iio/imu/bmi160/bmi160_core.c
+++ b/drivers/iio/imu/bmi160/bmi160_core.c
@@ -2,6 +2,7 @@
* BMI160 - Bosch IMU (accel, gyro plus external magnetometer)
*
* Copyright (c) 2016, Intel Corporation.
+ * Copyright (c) 2016, Grinn
*
* This file is subject to the terms and conditions of version 2 of
* the GNU General Public License. See the file COPYING in the main
@@ -9,7 +10,7 @@
*
* IIO core driver for BMI160, with support for I2C/SPI busses
*
- * TODO: magnetometer, interrupts, hardware FIFO
+ * TODO: magnetometer, interrupts
*/
#include <linux/module.h>
#include <linux/regmap.h>
@@ -22,8 +23,12 @@
#include <linux/iio/buffer.h>
#include <linux/iio/sysfs.h>
+#include <linux/of_irq.h>
+
#include "bmi160.h"
+#define BMI160_IRQ_NAME "bmi160_event"
+
#define BMI160_REG_CHIP_ID 0x00
#define BMI160_CHIP_ID_VAL 0xD1
@@ -34,6 +39,21 @@
#define BMI160_REG_DATA_GYRO_XOUT_L 0x0C
#define BMI160_REG_DATA_ACCEL_XOUT_L 0x12
+#define BMI160_REG_STATUS 0x1B
+#define BMI160_STATUS_MAG_MAN_OP BIT(2)
+
+#define BMI160_REG_INT_STATUS0 0x1C
+
+#define BMI160_REG_INT_STATUS1 0x1D
+#define BMI160_INT_STATUS_FWM BIT(6)
+
+#define BMI160_REG_INT_STATUS2 0x1E
+
+#define BMI160_REG_INT_STATUS3 0x1F
+
+#define BMI160_REG_FIFO_LENGTH 0x22
+#define BMI160_REG_FIFO_DATA 0x24
+
#define BMI160_REG_ACCEL_CONFIG 0x40
#define BMI160_ACCEL_CONFIG_ODR_MASK GENMASK(3, 0)
#define BMI160_ACCEL_CONFIG_BWP_MASK GENMASK(6, 4)
@@ -55,6 +75,36 @@
#define BMI160_GYRO_RANGE_250DPS 0x03
#define BMI160_GYRO_RANGE_125DPS 0x04
+#define BMI160_REG_FIFO_CONFIG_0 0x46
+
+#define BMI160_REG_FIFO_CONFIG_1 0x47
+#define BMI160_FIFO_GYRO_EN BIT(7)
+#define BMI160_FIFO_ACCEL_EN BIT(6)
+#define BMI160_FIFO_MAGN_EN BIT(5)
+#define BMI160_FIFO_HEADER_EN BIT(4)
+#define BMI160_FIFO_TAG_INT1_EN BIT(3)
+#define BMI160_FIFO_TAG_INT2_EN BIT(2)
+#define BMI160_FIFO_TIME_EN BIT(1)
+
+#define BMI160_REG_INT_EN_1 0x51
+#define BMI160_INT_FWM_EN BIT(6)
+#define BMI160_INT_FFULL_EN BIT(5)
+#define BMI160_INT_DRDY_EN BIT(4)
+
+#define BMI160_REG_INT_OUT_CTRL 0x53
+#define BMI160_INT2_OUTPUT_EN BIT(7)
+#define BMI160_INT1_OUTPUT_EN BIT(3)
+
+#define BMI160_REG_INT_LATCH 0x54
+
+#define BMI160_REG_INT_MAP_1 0x56
+#define BMI160_INT1_MAP_DRDY BIT(7)
+#define BMI160_INT1_MAP_FWM BIT(6)
+#define BMI160_INT1_MAP_FFULL BIT(5)
+#define BMI160_INT2_MAP_DRDY BIT(3)
+#define BMI160_INT2_MAP_FWM BIT(2)
+#define BMI160_INT2_MAP_FFULL BIT(1)
+
#define BMI160_REG_CMD 0x7E
#define BMI160_CMD_ACCEL_PM_SUSPEND 0x10
#define BMI160_CMD_ACCEL_PM_NORMAL 0x11
@@ -66,6 +116,8 @@
#define BMI160_REG_DUMMY 0x7F
+#define BMI160_FIFO_LENGTH 1024
+
#define BMI160_ACCEL_PMU_MIN_USLEEP 3200
#define BMI160_ACCEL_PMU_MAX_USLEEP 3800
#define BMI160_GYRO_PMU_MIN_USLEEP 55000
@@ -110,8 +162,33 @@ enum bmi160_sensor_type {
BMI160_NUM_SENSORS /* must be last */
};
+struct bmi160_irq_data {
+ unsigned int map_fwm;
+ unsigned int output_en;
+};
+
+static const struct bmi160_irq_data bmi160_irq1_data = {
+ .map_fwm = BMI160_INT1_MAP_FWM,
+ .output_en = BMI160_INT1_OUTPUT_EN,
+};
+
+static const struct bmi160_irq_data bmi160_irq2_data = {
+ .map_fwm = BMI160_INT2_MAP_FWM,
+ .output_en = BMI160_INT2_OUTPUT_EN,
+};
+
struct bmi160_data {
struct regmap *regmap;
+ struct mutex mutex;
+ const struct bmi160_irq_data *irq_data;
+ int irq;
+ int64_t timestamp;
+ int64_t fifo_sample_period;
+ bool fifo_enabled;
+ unsigned int fifo_config;
+ unsigned int fifo_sample_size;
+ u8 *fifo_buffer;
+ unsigned int watermark;
};
const struct regmap_config bmi160_regmap_config = {
@@ -159,11 +236,11 @@ struct bmi160_pmu_time {
static struct bmi160_pmu_time bmi160_pmu_time[] = {
[BMI160_ACCEL] = {
.min = BMI160_ACCEL_PMU_MIN_USLEEP,
- .max = BMI160_ACCEL_PMU_MAX_USLEEP
+ .max = BMI160_ACCEL_PMU_MAX_USLEEP,
},
[BMI160_GYRO] = {
.min = BMI160_GYRO_PMU_MIN_USLEEP,
- .max = BMI160_GYRO_PMU_MIN_USLEEP,
+ .max = BMI160_GYRO_PMU_MAX_USLEEP,
},
};
@@ -285,7 +362,9 @@ int bmi160_set_mode(struct bmi160_data *data, enum bmi160_sensor_type t,
else
cmd = bmi160_regs[t].pmu_cmd_suspend;
+ mutex_lock(&data->mutex);
ret = regmap_write(data->regmap, BMI160_REG_CMD, cmd);
+ mutex_unlock(&data->mutex);
if (ret < 0)
return ret;
@@ -298,6 +377,7 @@ static
int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
int uscale)
{
+ int ret;
int i;
for (i = 0; i < bmi160_scale_table[t].num; i++)
@@ -307,8 +387,12 @@ int bmi160_set_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
if (i == bmi160_scale_table[t].num)
return -EINVAL;
- return regmap_write(data->regmap, bmi160_regs[t].range,
- bmi160_scale_table[t].tbl[i].bits);
+ mutex_lock(&data->mutex);
+ ret = regmap_write(data->regmap, bmi160_regs[t].range,
+ bmi160_scale_table[t].tbl[i].bits);
+ mutex_unlock(&data->mutex);
+
+ return ret;
}
static
@@ -317,7 +401,9 @@ int bmi160_get_scale(struct bmi160_data *data, enum bmi160_sensor_type t,
{
int i, ret, val;
+ mutex_lock(&data->mutex);
ret = regmap_read(data->regmap, bmi160_regs[t].range, &val);
+ mutex_unlock(&data->mutex);
if (ret < 0)
return ret;
@@ -340,7 +426,9 @@ static int bmi160_get_data(struct bmi160_data *data, int chan_type,
reg = bmi160_regs[t].data + (axis - IIO_MOD_X) * sizeof(__le16);
+ mutex_lock(&data->mutex);
ret = regmap_bulk_read(data->regmap, reg, &sample, sizeof(__le16));
+ mutex_unlock(&data->mutex);
if (ret < 0)
return ret;
@@ -353,6 +441,7 @@ static
int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
int odr, int uodr)
{
+ int ret;
int i;
for (i = 0; i < bmi160_odr_table[t].num; i++)
@@ -363,20 +452,30 @@ int bmi160_set_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
if (i >= bmi160_odr_table[t].num)
return -EINVAL;
- return regmap_update_bits(data->regmap,
- bmi160_regs[t].config,
- bmi160_regs[t].config_odr_mask,
- bmi160_odr_table[t].tbl[i].bits);
+ mutex_lock(&data->mutex);
+ ret = regmap_update_bits(data->regmap,
+ bmi160_regs[t].config,
+ bmi160_regs[t].config_odr_mask,
+ bmi160_odr_table[t].tbl[i].bits);
+ mutex_unlock(&data->mutex);
+
+ return ret;
}
-static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
- int *odr, int *uodr)
+static int64_t bmi160_frequency_to_period(int odr, int uodr)
{
- int i, val, ret;
+ uint64_t period = 1000000000000000;
+ int64_t frequency = (int64_t) odr * 1000000 + uodr;
- ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
- if (ret < 0)
- return ret;
+ do_div(period, frequency);
+
+ return period;
+}
+
+static const struct bmi160_odr *bmi160_reg_to_odr(enum bmi160_sensor_type t,
+ unsigned int val)
+{
+ int i;
val &= bmi160_regs[t].config_odr_mask;
@@ -385,10 +484,52 @@ static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
break;
if (i >= bmi160_odr_table[t].num)
- return -EINVAL;
+ return ERR_PTR(-EINVAL);
+
+ return &bmi160_odr_table[t].tbl[i];
+}
+
+static int bmi160_get_sample_period(struct bmi160_data *data,
+ enum bmi160_sensor_type t,
+ int64_t *sample_period)
+{
+ const struct bmi160_odr *odr_entry;
+ int ret;
+ unsigned int val;
+
+ ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
+ if (ret < 0)
+ return ret;
- *odr = bmi160_odr_table[t].tbl[i].odr;
- *uodr = bmi160_odr_table[t].tbl[i].uodr;
+ odr_entry = bmi160_reg_to_odr(t, val);
+ if (IS_ERR(odr_entry))
+ return PTR_ERR(odr_entry);
+
+ *sample_period = bmi160_frequency_to_period(odr_entry->odr,
+ odr_entry->uodr);
+
+ return 0;
+}
+
+static int bmi160_get_odr(struct bmi160_data *data, enum bmi160_sensor_type t,
+ int *odr, int *uodr)
+{
+ const struct bmi160_odr *odr_entry;
+ int ret;
+ unsigned int val;
+
+ mutex_lock(&data->mutex);
+ ret = regmap_read(data->regmap, bmi160_regs[t].config, &val);
+ mutex_unlock(&data->mutex);
+ if (ret < 0)
+ return ret;
+
+ odr_entry = bmi160_reg_to_odr(t, val);
+ if (IS_ERR(odr_entry))
+ return PTR_ERR(odr_entry);
+
+ *odr = odr_entry->odr;
+ *uodr = odr_entry->uodr;
return 0;
}
@@ -402,14 +543,18 @@ static irqreturn_t bmi160_trigger_handler(int irq, void *p)
int i, ret, j = 0, base = BMI160_REG_DATA_MAGN_XOUT_L;
__le16 sample;
+ mutex_lock(&data->mutex);
for_each_set_bit(i, indio_dev->active_scan_mask,
indio_dev->masklength) {
ret = regmap_bulk_read(data->regmap, base + i * sizeof(__le16),
&sample, sizeof(__le16));
- if (ret < 0)
+ if (ret < 0) {
+ mutex_unlock(&data->mutex);
goto done;
+ }
buf[j++] = sample;
}
+ mutex_unlock(&data->mutex);
iio_push_to_buffers_with_timestamp(indio_dev, buf,
iio_get_time_ns(indio_dev));
@@ -493,11 +638,364 @@ static const struct attribute_group bmi160_attrs_group = {
.attrs = bmi160_attrs,
};
+static int bmi160_update_sample_period(struct bmi160_data *data,
+ enum bmi160_sensor_type sensor_type)
+{
+ struct device *dev = regmap_get_device(data->regmap);
+ int64_t sample_period;
+ int ret;
+
+ ret = bmi160_get_sample_period(data, sensor_type, &sample_period);
+ if (ret < 0)
+ return ret;
+
+ if (data->fifo_sample_period) {
+ if (data->fifo_sample_period != sample_period) {
+ dev_warn(dev, "Enabled sensors have unequal ODR values\n");
+ return -EINVAL;
+ }
+ } else {
+ data->fifo_sample_period = sample_period;
+ }
+
+ return 0;
+}
+
+static int bmi160_fifo_enable(struct iio_dev *indio_dev,
+ struct bmi160_data *data)
+{
+ struct regmap *regmap = data->regmap;
+ struct device *dev = regmap_get_device(regmap);
+ int ret;
+ int i;
+ unsigned int val;
+ unsigned int fifo_config = 0;
+
+ /* Set fifo sample size and period */
+ for_each_set_bit(i, indio_dev->active_scan_mask,
+ indio_dev->masklength) {
+ if (i <= BMI160_SCAN_GYRO_Z)
+ fifo_config |= BMI160_FIFO_GYRO_EN;
+ else if (i <= BMI160_SCAN_ACCEL_Z)
+ fifo_config |= BMI160_FIFO_ACCEL_EN;
+ }
+
+ data->fifo_sample_period = 0;
+ data->fifo_sample_size = 0;
+ if (fifo_config & BMI160_FIFO_GYRO_EN) {
+ data->fifo_sample_size += 6;
+ ret = bmi160_update_sample_period(data, BMI160_GYRO);
+ if (ret < 0)
+ return ret;
+ }
+ if (fifo_config & BMI160_FIFO_ACCEL_EN) {
+ data->fifo_sample_size += 6;
+ ret = bmi160_update_sample_period(data, BMI160_ACCEL);
+ if (ret < 0)
+ return ret;
+ }
+
+ /*
+ * Set watermark level and write real value back, as it will be used
+ * in timestamp calculation.
+ */
+ val = data->watermark * data->fifo_sample_size;
+ if (val > BMI160_FIFO_LENGTH - 1) {
+ val = BMI160_FIFO_LENGTH - 1;
+ data->watermark = val / data->fifo_sample_size;
+ }
+ val = data->watermark * data->fifo_sample_size / 4;
+
+ ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_0, val);
+ if (ret < 0) {
+ dev_err(dev, "Failed to set watermark\n");
+ return ret;
+ }
+
+ /* Enable FIFO channels */
+ ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_1,
+ fifo_config);
+ if (ret < 0) {
+ dev_err(dev, "Failed to write FIFO_CONFIG_1\n");
+ return ret;
+ }
+
+ data->fifo_config = fifo_config;
+ data->fifo_enabled = true;
+
+ return 0;
+}
+
+static int bmi160_fifo_disable(struct bmi160_data *data)
+{
+ struct regmap *regmap = data->regmap;
+ struct device *dev = regmap_get_device(regmap);
+ int ret;
+
+ /* Disable all FIFO channels */
+ ret = regmap_write(regmap, BMI160_REG_FIFO_CONFIG_1, 0);
+ if (ret < 0) {
+ dev_err(dev, "Failed to write FIFO_CONFIG_1\n");
+ return ret;
+ }
+
+ data->fifo_enabled = false;
+
+ return 0;
+}
+
+static int bmi160_buffer_postenable(struct iio_dev *indio_dev)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+ int ret;
+
+ if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
+ return iio_triggered_buffer_postenable(indio_dev);
+
+ mutex_lock(&data->mutex);
+ ret = regmap_update_bits(data->regmap, BMI160_REG_INT_MAP_1,
+ data->irq_data->map_fwm, data->irq_data->map_fwm);
+ if (ret < 0)
+ goto unlock;
+
+ ret = regmap_update_bits(data->regmap, BMI160_REG_INT_EN_1,
+ BMI160_INT_FWM_EN, BMI160_INT_FWM_EN);
+ if (ret < 0)
+ goto unlock;
+
+ ret = bmi160_fifo_enable(indio_dev, data);
+
+unlock:
+ mutex_unlock(&data->mutex);
+
+ return ret;
+}
+
+static int bmi160_buffer_predisable(struct iio_dev *indio_dev)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+ struct regmap *regmap = data->regmap;
+ int ret = 0;
+
+ if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
+ return iio_triggered_buffer_predisable(indio_dev);
+
+ mutex_lock(&data->mutex);
+
+ ret = regmap_update_bits(regmap, BMI160_REG_INT_EN_1,
+ BMI160_INT_FWM_EN, 0);
+ if (ret < 0)
+ goto unlock;
+
+ ret = bmi160_fifo_disable(data);
+
+unlock:
+ mutex_unlock(&data->mutex);
+
+ return ret;
+}
+
+static const struct iio_buffer_setup_ops bmi160_buffer_ops = {
+ .postenable = bmi160_buffer_postenable,
+ .predisable = bmi160_buffer_predisable,
+};
+
+static ssize_t bmi160_get_fifo_state(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
+ struct bmi160_data *data = iio_priv(indio_dev);
+ bool state;
+
+ mutex_lock(&data->mutex);
+ state = data->fifo_enabled;
+ mutex_unlock(&data->mutex);
+
+ return sprintf(buf, "%d\n", (int) state);
+}
+
+static ssize_t bmi160_get_fifo_watermark(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_to_iio_dev(dev);
+ struct bmi160_data *data = iio_priv(indio_dev);
+ int wm;
+
+ mutex_lock(&data->mutex);
+ wm = data->watermark;
+ mutex_unlock(&data->mutex);
+
+ return sprintf(buf, "%d\n", wm);
+}
+
+static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
+static IIO_CONST_ATTR(hwfifo_watermark_max,
+ __stringify(BMI160_FIFO_LENGTH));
+static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
+ bmi160_get_fifo_state, NULL, 0);
+static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
+ bmi160_get_fifo_watermark, NULL, 0);
+
+static const struct attribute *bmi160_fifo_attributes[] = {
+ &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
+ &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
+ &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
+ &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
+ NULL,
+};
+
+static int bmi160_set_watermark(struct iio_dev *indio_dev, unsigned int val)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+
+ if (val > BMI160_FIFO_LENGTH)
+ val = BMI160_FIFO_LENGTH;
+
+ data->watermark = val;
+
+ return 0;
+}
+
+static int bmi160_fifo_transfer(struct bmi160_data *data,
+ char *buffer, int num_bytes)
+{
+ struct regmap *regmap = data->regmap;
+ struct device *dev = regmap_get_device(regmap);
+ size_t step = regmap_get_raw_read_max(regmap);
+ int ret = 0;
+ int i;
+
+ if (!step || step > num_bytes)
+ step = num_bytes;
+ else if (step < num_bytes)
+ step = data->fifo_sample_size;
+
+ for (i = 0; i < num_bytes; i += step) {
+ ret = regmap_raw_read(regmap, BMI160_REG_FIFO_DATA,
+ &buffer[i], step);
+
+ if (ret)
+ break;
+ }
+
+ if (ret)
+ dev_err(dev,
+ "Error transferring data from fifo in single steps of %zu\n",
+ step);
+
+ return ret;
+}
+
+static int __bmi160_fifo_flush(struct iio_dev *indio_dev,
+ unsigned int samples, bool irq)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+ struct regmap *regmap = data->regmap;
+ struct device *dev = regmap_get_device(regmap);
+ int ret;
+ __le16 fifo_length;
+ unsigned int fifo_samples;
+ unsigned int fifo_bytes;
+ u8 *buffer = data->fifo_buffer;
+ u8 *buffer_iter;
+ int64_t last_timestamp, timestamp;
+ unsigned int last_samples;
+ unsigned int i;
+
+ /* Get the current FIFO length */
+ ret = regmap_bulk_read(regmap, BMI160_REG_FIFO_LENGTH,
+ &fifo_length, sizeof(__le16));
+ if (ret < 0) {
+ dev_err(dev, "Error reading FIFO_LENGTH\n");
+ return ret;
+ }
+
+ fifo_bytes = le16_to_cpu(fifo_length);
+ fifo_samples = fifo_bytes / data->fifo_sample_size;
+
+ if (fifo_bytes % data->fifo_sample_size)
+ dev_warn(dev, "fifo_bytes %u is not dividable by %u\n",
+ fifo_bytes, data->fifo_sample_size);
+
+ if (!fifo_samples)
+ return 0;
+
+ if (samples && fifo_samples > samples) {
+ fifo_samples = samples;
+ fifo_bytes = fifo_samples * data->fifo_sample_size;
+ }
+
+ /*
+ * If we are not called from IRQ, it means that we are flushing data
+ * on demand. In that case we do not have latest timestamp saved in
+ * data->timestamp. Get the time now instead.
+ *
+ * In case of IRQ flush, saved timestamp shows the time when number
+ * of samples configured by watermark were ready. Currently there might
+ * be more samples already.
+ * If we are not called from IRQ, than we are getting the current fifo
+ * length, as we are setting timestamp just after getting it.
+ */
+ if (!irq) {
+ last_timestamp = iio_get_time_ns(indio_dev);
+ last_samples = fifo_samples;
+ } else {
+ last_timestamp = data->timestamp;
+ last_samples = data->watermark;
+ }
+
+ /* Get all measurements */
+ ret = bmi160_fifo_transfer(data, buffer, fifo_bytes);
+ if (ret)
+ return ret;
+
+ /* Handle demux */
+ timestamp = last_timestamp - (last_samples * data->fifo_sample_period);
+ buffer_iter = buffer;
+ for (i = 0; i < fifo_samples; i++) {
+ u8 tmp_buf[indio_dev->scan_bytes];
+
+ memcpy(tmp_buf, buffer_iter, data->fifo_sample_size);
+
+ timestamp += data->fifo_sample_period;
+ iio_push_to_buffers_with_timestamp(indio_dev,
+ tmp_buf,
+ timestamp);
+
+ buffer_iter += data->fifo_sample_size;
+ }
+
+ return fifo_samples;
+}
+
+static int bmi160_fifo_flush(struct iio_dev *indio_dev, unsigned int samples)
+{
+ struct bmi160_data *data = iio_priv(indio_dev);
+ int ret;
+
+ mutex_lock(&data->mutex);
+ ret = __bmi160_fifo_flush(indio_dev, samples, false);
+ mutex_unlock(&data->mutex);
+
+ return ret;
+}
+
static const struct iio_info bmi160_info = {
- .driver_module = THIS_MODULE,
- .read_raw = bmi160_read_raw,
- .write_raw = bmi160_write_raw,
- .attrs = &bmi160_attrs_group,
+ .driver_module = THIS_MODULE,
+ .read_raw = bmi160_read_raw,
+ .write_raw = bmi160_write_raw,
+ .attrs = &bmi160_attrs_group,
+};
+
+static const struct iio_info bmi160_info_fifo = {
+ .driver_module = THIS_MODULE,
+ .read_raw = bmi160_read_raw,
+ .write_raw = bmi160_write_raw,
+ .attrs = &bmi160_attrs_group,
+ .hwfifo_set_watermark = bmi160_set_watermark,
+ .hwfifo_flush_to_buffer = bmi160_fifo_flush,
};
static const char *bmi160_match_acpi_device(struct device *dev)
@@ -561,12 +1059,54 @@ static void bmi160_chip_uninit(struct bmi160_data *data)
bmi160_set_mode(data, BMI160_ACCEL, false);
}
+static int bmi160_enable_irq(struct bmi160_data *data)
+{
+ int ret;
+
+ mutex_lock(&data->mutex);
+ ret = regmap_update_bits(data->regmap, BMI160_REG_INT_OUT_CTRL,
+ data->irq_data->output_en,
+ data->irq_data->output_en);
+ mutex_unlock(&data->mutex);
+
+ return ret;
+}
+
+static irqreturn_t bmi160_irq_thread_handler(int irq, void *p)
+{
+ struct iio_dev *indio_dev = p;
+ struct bmi160_data *data = iio_priv(indio_dev);
+ struct device *dev = regmap_get_device(data->regmap);
+
+ mutex_lock(&data->mutex);
+ if (data->fifo_enabled)
+ __bmi160_fifo_flush(indio_dev, BMI160_FIFO_LENGTH, true);
+ else
+ dev_warn(dev,
+ "IRQ has been triggered, but FIFO is not enabled.\n");
+ mutex_unlock(&data->mutex);
+
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t bmi160_irq_handler(int irq, void *p)
+{
+ struct iio_dev *indio_dev = p;
+ struct bmi160_data *data = iio_priv(indio_dev);
+
+ data->timestamp = iio_get_time_ns(indio_dev);
+
+ return IRQ_WAKE_THREAD;
+}
+
int bmi160_core_probe(struct device *dev, struct regmap *regmap,
- const char *name, bool use_spi)
+ const char *name, int irq,
+ bool use_spi, bool block_supported)
{
struct iio_dev *indio_dev;
struct bmi160_data *data;
int ret;
+ int irq2;
indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
if (!indio_dev)
@@ -574,8 +1114,11 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
data = iio_priv(indio_dev);
dev_set_drvdata(dev, indio_dev);
+ data->irq = irq;
data->regmap = regmap;
+ mutex_init(&data->mutex);
+
ret = bmi160_chip_init(data, use_spi);
if (ret < 0)
return ret;
@@ -591,10 +1134,50 @@ int bmi160_core_probe(struct device *dev, struct regmap *regmap,
indio_dev->info = &bmi160_info;
ret = iio_triggered_buffer_setup(indio_dev, NULL,
- bmi160_trigger_handler, NULL);
+ bmi160_trigger_handler,
+ &bmi160_buffer_ops);
if (ret < 0)
goto uninit;
+ if (data->irq > 0) {
+ /* Check which interrupt pin is connected to our board */
+ irq2 = of_irq_get_byname(dev->of_node, "INT2");
+ if (irq2 == data->irq) {
+ dev_dbg(dev, "Using interrupt line INT2\n");
+ data->irq_data = &bmi160_irq2_data;
+ } else {
+ dev_dbg(dev, "Using interrupt line INT1\n");
+ data->irq_data = &bmi160_irq1_data;
+ }
+
+ ret = devm_request_threaded_irq(dev,
+ data->irq,
+ bmi160_irq_handler,
+ bmi160_irq_thread_handler,
+ IRQF_ONESHOT,
+ BMI160_IRQ_NAME,
+ indio_dev);
+ if (ret)
+ return ret;
+
+ ret = bmi160_enable_irq(data);
+ if (ret < 0)
+ goto buffer_cleanup;
+
+ if (block_supported) {
+ indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
+ indio_dev->info = &bmi160_info_fifo;
+ indio_dev->buffer->attrs = bmi160_fifo_attributes;
+ data->fifo_buffer = devm_kmalloc(dev,
+ BMI160_FIFO_LENGTH,
+ GFP_KERNEL);
+ if (!data->fifo_buffer) {
+ ret = -ENOMEM;
+ goto buffer_cleanup;
+ }
+ }
+ }
+
ret = iio_device_register(indio_dev);
if (ret < 0)
goto buffer_cleanup;
diff --git a/drivers/iio/imu/bmi160/bmi160_i2c.c b/drivers/iio/imu/bmi160/bmi160_i2c.c
index 07a179d..aa63f89 100644
--- a/drivers/iio/imu/bmi160/bmi160_i2c.c
+++ b/drivers/iio/imu/bmi160/bmi160_i2c.c
@@ -23,6 +23,10 @@ static int bmi160_i2c_probe(struct i2c_client *client,
{
struct regmap *regmap;
const char *name = NULL;
+ bool block_supported =
+ i2c_check_functionality(client->adapter, I2C_FUNC_I2C) ||
+ i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_READ_I2C_BLOCK);
regmap = devm_regmap_init_i2c(client, &bmi160_regmap_config);
if (IS_ERR(regmap)) {
@@ -34,7 +38,8 @@ static int bmi160_i2c_probe(struct i2c_client *client,
if (id)
name = id->name;
- return bmi160_core_probe(&client->dev, regmap, name, false);
+ return bmi160_core_probe(&client->dev, regmap, name, client->irq,
+ false, block_supported);
}
static int bmi160_i2c_remove(struct i2c_client *client)
diff --git a/drivers/iio/imu/bmi160/bmi160_spi.c b/drivers/iio/imu/bmi160/bmi160_spi.c
index 1ec8b12..9b57fbe 100644
--- a/drivers/iio/imu/bmi160/bmi160_spi.c
+++ b/drivers/iio/imu/bmi160/bmi160_spi.c
@@ -25,7 +25,8 @@ static int bmi160_spi_probe(struct spi_device *spi)
(int)PTR_ERR(regmap));
return PTR_ERR(regmap);
}
- return bmi160_core_probe(&spi->dev, regmap, id->name, true);
+ return bmi160_core_probe(&spi->dev, regmap, id->name, spi->irq,
+ true, true);
}
static int bmi160_spi_remove(struct spi_device *spi)
--
2.10.1
--
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^ permalink raw reply related
* [PATCH/RFC v2 2/3] regulator: fixed: dt: Allow an optional over current pin
From: Axel Haslam @ 2016-11-03 11:11 UTC (permalink / raw)
To: broonie-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
khilman-rdvid1DuHRBWk0Htik3J/w, nsekhar-l0cyMroinI0,
david-nq/r/kbU++upp/zk7JDF2g, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Axel Haslam,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161103111144.511-1-ahaslam-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Add support for an optional over current input pin which
can be used to send an over current event to the regulator
consumer.
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Signed-off-by: Axel Haslam <ahaslam-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
Documentation/devicetree/bindings/regulator/fixed-regulator.txt | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
index 4fae41d..b145abb 100644
--- a/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/fixed-regulator.txt
@@ -11,6 +11,7 @@ If this property is missing, the default assumed is Active low.
- gpio-open-drain: GPIO is open drain type.
If this property is missing then default assumption is false.
-vin-supply: Input supply name.
+- over-current-gpios: Input gpio that signal an over current condition.
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
@@ -26,6 +27,7 @@ Example:
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&gpio1 16 0>;
+ over-current-gpios = <&gpio1 18 0>;
startup-delay-us = <70000>;
enable-active-high;
regulator-boot-on;
--
2.10.1
--
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^ permalink raw reply related
* Re: [PATCH 01/10] Documentation: dt-bindings: Document STM32 ADC DT bindings
From: Fabrice Gasnier @ 2016-11-03 11:11 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland, devicetree, lars, alexandre.torgue, linux-iio,
pmeerw, linux, linux-kernel, jic23, mcoquelin.stm32, knaack.h,
linux-arm-kernel
In-Reply-To: <20161031030222.vjxcxklpaua3o77d@rob-hp-laptop>
On 10/31/2016 04:02 AM, Rob Herring wrote:
> On Tue, Oct 25, 2016 at 06:25:13PM +0200, Fabrice Gasnier wrote:
>> This patch adds documentation of device tree bindings for the STM32 ADC.
>>
>> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
>> ---
>> .../devicetree/bindings/iio/adc/st,stm32-adc.txt | 78 ++++++++++++++++++++++
>> 1 file changed, 78 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
>> new file mode 100644
>> index 0000000..a9a8b3c
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/adc/st,stm32-adc.txt
>> @@ -0,0 +1,78 @@
>> +STMicroelectronics STM32 ADC device driver
>> +
>> +STM32 ADC is a successive approximation analog-to-digital converter.
>> +It has several multiplexed input channels. Conversions can be performed
>> +in single, continuous, scan or discontinuous mode. Result of the ADC is
>> +stored in a left-aligned or right-aligned 32-bit data register.
>> +Conversions can be launched in software or using hardware triggers.
>> +
>> +The analog watchdog feature allows the application to detect if the input
>> +voltage goes beyond the user-defined, higher or lower thresholds.
>> +
>> +Each STM32 ADC block can have up to 3 ADC instances.
>> +
>> +Each instance supports two contexts to manage conversions, each one has its
>> +own configurable sequence and trigger:
>> +- regular conversion can be done in sequence, running in background
>> +- injected conversions have higher priority, and so have the ability to
>> + interrupt regular conversion sequence (either triggered in SW or HW).
>> + Regular sequence is resumed, in case it has been interrupted.
>> +
>> +Required properties:
>> +- compatible: Should be "st,stm32f4-adc".
>> +- reg: Offset and length of the ADC block register set.
>> +- interrupts: Must contain the interrupt for ADC.
>> +- clocks: Clock for the analog circuitry (common to all ADCs).
>> +- clock-names: Must be "adc".
>> +- vref-supply: Phandle to the vref input analog reference voltage.
>> +- #address-cells = <1>;
>> +- #size-cells = <0>;
>> +
>> +Optional properties:
>> +- A pinctrl state named "default" for each ADC channel may be defined to set
>> + inX ADC pins in mode of operation for analog input on external pin.
>> +- gpios: Array of gpios that may be configured as EXTi trigger sources.
>> +
>> +Example:
> This should be last.
Hi Rob,
I'll fix this.
>
>> + adc: adc@40012000 {
>> + compatible = "st,stm32f4-adc";
>> + reg = <0x40012000 0x400>;
>> + interrupts = <18>;
>> + clocks = <&rcc 0 168>;
>> + clock-names = "adc";
>> + vref-supply = <®_vref>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&adc3_in8_pin>;
>> + gpios = <&gpioa 11 0>,
>> + <&gpioa 15 0>;
>> +
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + adc1: adc1-master@0 {
> adc@0 sufficient?
Yes, if you agree, I'd go for adc1@0, adc2@100, adc3@200, to reflect reg
property for child node.
Is it ok from your point of view ?
>
>> + #io-channel-cells = <1>;
>> + reg = <0x0>;
>> + clocks = <&rcc 0 168>;
>> + st,adc-channels = <8>;
>> + };
>> + ...
>> + other adc child nodes follow...
>> + };
>> +
>> +Contents of a stm32 adc child node:
>> +-----------------------------------
>> +An ADC block node should contain at least one subnode, representing an
>> +ADC instance available on the machine.
>> +
>> +Required properties:
>> +- reg: Offset of ADC instance in ADC block (e.g. may be 0x0, 0x100, 0x200).
>> +- st,adc-channels: List of single-ended channels muxed for this ADC.
> How many? What are valid values?
stm32f4 can have up to 19 channels, numbered from 0 to 18 to match with
reference manual.
I'll add this.
>
>> +- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers" in
>> + Documentation/devicetree/bindings/iio/iio-bindings.txt
>> +
>> +Optional properties:
>> +- clocks: Input clock private to this ADC instance.
>> +- st,injected: Use injected conversion sequence on an ADC, rather than regular.
> Not sure about this one. Seems like this would either be a user choice
> or depend on what's connected to the ADC.
It's related to ADC sequencer, and the way it's being configured/used
(see above paragraph on regular/injected).
This is not related to what's connected to adc inputs.
As suggested by Jonathan, I think I'll drop injected support for now, to
simplify the driver and review.
Thanks,
Best Regards,
Fabrice
>
>> +- dmas: Phandle to dma channel for this ADC instance, only for regular
>> + conversions. See ../../dma/dma.txt for details.
>> +- dma-names: Must be "rx" when dmas property is being used.
>> --
>> 1.9.1
>>
^ permalink raw reply
* Re: [PATCH V3 6/6] bus: Add support for Tegra Generic Memory Interface
From: Jon Hunter @ 2016-11-03 10:51 UTC (permalink / raw)
To: Mirza Krak, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477576872-2665-7-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> The Generic Memory Interface bus can be used to connect high-speed
> devices such as NOR flash, FPGAs, DSPs...
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> ---
>
> Changes in v2:
> - Fixed some checkpatch errors
> - Re-ordered probe to get rid of local variables
> - Moved of_platform_default_populate call to the end of probe
> - Use the timing and configuration properties from the child device
> - Added warning if more then 1 child device exist
>
> Changes in v3:
> - added helper function to disable the controller which is used in remove and
> on error.
> - Added logic to parse CS# from "ranges" property with fallback to "reg"
> property
>
> drivers/bus/Kconfig | 8 ++
> drivers/bus/Makefile | 1 +
> drivers/bus/tegra-gmi.c | 267 ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 276 insertions(+)
> create mode 100644 drivers/bus/tegra-gmi.c
>
> diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
> index 4ed7d26..2e75a7f 100644
> --- a/drivers/bus/Kconfig
> +++ b/drivers/bus/Kconfig
> @@ -141,6 +141,14 @@ config TEGRA_ACONNECT
> Driver for the Tegra ACONNECT bus which is used to interface with
> the devices inside the Audio Processing Engine (APE) for Tegra210.
>
> +config TEGRA_GMI
> + tristate "Tegra Generic Memory Interface bus driver"
> + depends on ARCH_TEGRA
> + help
> + Driver for the Tegra Generic Memory Interface bus which can be used
> + to attach devices such as NOR, UART, FPGA and more.
> +
> +
Nit-pick ... only one additional line above is needed to be consistent
with the rest of the file.
> config UNIPHIER_SYSTEM_BUS
> tristate "UniPhier System Bus driver"
> depends on ARCH_UNIPHIER && OF
> diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
> index ac84cc4..34e2bab 100644
> --- a/drivers/bus/Makefile
> +++ b/drivers/bus/Makefile
> @@ -18,5 +18,6 @@ obj-$(CONFIG_OMAP_OCP2SCP) += omap-ocp2scp.o
> obj-$(CONFIG_SUNXI_RSB) += sunxi-rsb.o
> obj-$(CONFIG_SIMPLE_PM_BUS) += simple-pm-bus.o
> obj-$(CONFIG_TEGRA_ACONNECT) += tegra-aconnect.o
> +obj-$(CONFIG_TEGRA_GMI) += tegra-gmi.o
> obj-$(CONFIG_UNIPHIER_SYSTEM_BUS) += uniphier-system-bus.o
> obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress-config.o
> diff --git a/drivers/bus/tegra-gmi.c b/drivers/bus/tegra-gmi.c
> new file mode 100644
> index 0000000..dd9623e
> --- /dev/null
> +++ b/drivers/bus/tegra-gmi.c
> @@ -0,0 +1,267 @@
> +/*
> + * Driver for NVIDIA Generic Memory Interface
> + *
> + * Copyright (C) 2016 Host Mobility AB. All rights reserved.
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +#include <linux/clk.h>
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <linux/reset.h>
> +
> +#define TEGRA_GMI_CONFIG 0x00
> +#define TEGRA_GMI_CONFIG_GO BIT(31)
> +#define TEGRA_GMI_BUS_WIDTH_32BIT BIT(30)
> +#define TEGRA_GMI_MUX_MODE BIT(28)
> +#define TEGRA_GMI_RDY_BEFORE_DATA BIT(24)
> +#define TEGRA_GMI_RDY_ACTIVE_HIGH BIT(23)
> +#define TEGRA_GMI_ADV_ACTIVE_HIGH BIT(22)
> +#define TEGRA_GMI_OE_ACTIVE_HIGH BIT(21)
> +#define TEGRA_GMI_CS_ACTIVE_HIGH BIT(20)
> +#define TEGRA_GMI_CS_SELECT(x) ((x & 0x7) << 4)
> +
> +#define TEGRA_GMI_TIMING0 0x10
> +#define TEGRA_GMI_MUXED_WIDTH(x) ((x & 0xf) << 12)
> +#define TEGRA_GMI_HOLD_WIDTH(x) ((x & 0xf) << 8)
> +#define TEGRA_GMI_ADV_WIDTH(x) ((x & 0xf) << 4)
> +#define TEGRA_GMI_CE_WIDTH(x) (x & 0xf)
> +
> +#define TEGRA_GMI_TIMING1 0x14
> +#define TEGRA_GMI_WE_WIDTH(x) ((x & 0xff) << 16)
> +#define TEGRA_GMI_OE_WIDTH(x) ((x & 0xff) << 8)
> +#define TEGRA_GMI_WAIT_WIDTH(x) (x & 0xff)
> +
> +struct tegra_gmi_priv {
> + void __iomem *base;
> + struct reset_control *rst;
> + struct clk *clk;
> +
> + u32 snor_config;
> + u32 snor_timing0;
> + u32 snor_timing1;
> +};
> +
> +static void tegra_gmi_disable(struct tegra_gmi_priv *priv)
> +{
> + u32 config;
> +
> + /* stop GMI operation */
> + config = readl(priv->base + TEGRA_GMI_CONFIG);
> + config &= ~TEGRA_GMI_CONFIG_GO;
> + writel(config, priv->base + TEGRA_GMI_CONFIG);
> +
> + reset_control_assert(priv->rst);
> + clk_disable_unprepare(priv->clk);
> +}
> +
> +static void tegra_gmi_init(struct device *dev, struct tegra_gmi_priv *priv)
> +{
> + writel(priv->snor_timing0, priv->base + TEGRA_GMI_TIMING0);
> + writel(priv->snor_timing1, priv->base + TEGRA_GMI_TIMING1);
> +
> + priv->snor_config |= TEGRA_GMI_CONFIG_GO;
> + writel(priv->snor_config, priv->base + TEGRA_GMI_CONFIG);
> +}
> +
> +static int tegra_gmi_parse_dt(struct device *dev, struct tegra_gmi_priv *priv)
> +{
> + struct device_node *child = of_get_next_available_child(dev->of_node,
> + NULL);
> + u32 property, ranges[4];
> + int ret;
> +
> + if (!child) {
> + dev_warn(dev, "no child nodes found\n");
> + return 0;
Don't we want to return an error here? Otherwise, we will call
tegra_gmi_init() with an invalid configuration.
> + }
> +
> + /*
> + * We currently only support one child device due to lack of
> + * chip-select address decoding. Which means that we only have one
> + * chip-select line from the GMI controller.
> + */
> + if (of_get_child_count(dev->of_node) > 1)
> + dev_warn(dev, "only one child device is supported.");
> +
> + if (of_property_read_bool(child, "nvidia,snor-data-width-32bit"))
> + priv->snor_config |= TEGRA_GMI_BUS_WIDTH_32BIT;
> +
> + if (of_property_read_bool(child, "nvidia,snor-mux-mode"))
> + priv->snor_config |= TEGRA_GMI_MUX_MODE;
> +
> + if (of_property_read_bool(child, "nvidia,snor-rdy-active-before-data"))
> + priv->snor_config |= TEGRA_GMI_RDY_BEFORE_DATA;
> +
> + if (of_property_read_bool(child, "nvidia,snor-rdy-inv"))
> + priv->snor_config |= TEGRA_GMI_RDY_ACTIVE_HIGH;
> +
> + if (of_property_read_bool(child, "nvidia,snor-adv-inv"))
> + priv->snor_config |= TEGRA_GMI_ADV_ACTIVE_HIGH;
> +
> + if (of_property_read_bool(child, "nvidia,snor-oe-inv"))
> + priv->snor_config |= TEGRA_GMI_OE_ACTIVE_HIGH;
> +
> + if (of_property_read_bool(child, "nvidia,snor-cs-inv"))
> + priv->snor_config |= TEGRA_GMI_CS_ACTIVE_HIGH;
> +
> + /* Decode the CS# */
> + ret = of_property_read_u32_array(child, "ranges", ranges, 4);
> + if (ret < 0) {
> + /* Invalid binding */
> + if (ret == -EOVERFLOW) {
> + dev_err(dev, "invalid ranges length\n");
> + goto error_cs_decode;
> + }
> +
> + /*
> + * If we reach here it means that the child node has an empty
> + * ranges or it does not exist at all. Attempt to decode the
> + * CS# from the reg property instead.
> + */
> + ret = of_property_read_u32(child, "reg", &property);
> + if (ret < 0) {
> + dev_err(dev, "no reg property found\n");
> + goto error_cs_decode;
> + }
> + } else {
> + property = ranges[1];
> + }
> +
> + priv->snor_config |= TEGRA_GMI_CS_SELECT(property);
Should we make sure the CS is a valid value before setting?
> +
> + /* The default values that are provided below are reset values */
> + if (!of_property_read_u32(child, "nvidia,snor-muxed-width", &property))
> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(property);
> + else
> + priv->snor_timing0 |= TEGRA_GMI_MUXED_WIDTH(1);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-hold-width", &property))
> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(property);
> + else
> + priv->snor_timing0 |= TEGRA_GMI_HOLD_WIDTH(1);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-adv-width", &property))
> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(property);
> + else
> + priv->snor_timing0 |= TEGRA_GMI_ADV_WIDTH(1);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-ce-width", &property))
> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(property);
> + else
> + priv->snor_timing0 |= TEGRA_GMI_CE_WIDTH(4);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-we-width", &property))
> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(property);
> + else
> + priv->snor_timing1 |= TEGRA_GMI_WE_WIDTH(1);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-oe-width", &property))
> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(property);
> + else
> + priv->snor_timing1 |= TEGRA_GMI_OE_WIDTH(1);
> +
> + if (!of_property_read_u32(child, "nvidia,snor-wait-width", &property))
> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(property);
> + else
> + priv->snor_timing1 |= TEGRA_GMI_WAIT_WIDTH(3);
> +
> +error_cs_decode:
> + if (ret < 0)
> + dev_err(dev, "failed to decode chip-select number\n");
Nit do we need another error message here? Can we add the "failed to
decode CS" part the earlier message?
> +
> + of_node_put(child);
> + return ret;
> +}
> +
> +static int tegra_gmi_probe(struct platform_device *pdev)
> +{
> + struct resource *res;
> + struct device *dev = &pdev->dev;
> + struct tegra_gmi_priv *priv;
> + int ret;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + priv->base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->base))
> + return PTR_ERR(priv->base);
> +
> + priv->clk = devm_clk_get(dev, "gmi");
> + if (IS_ERR(priv->clk)) {
> + dev_err(dev, "can not get clock\n");
> + return PTR_ERR(priv->clk);
> + }
> +
> + priv->rst = devm_reset_control_get(dev, "gmi");
> + if (IS_ERR(priv->rst)) {
> + dev_err(dev, "can not get reset\n");
> + return PTR_ERR(priv->rst);
> + }
> +
> + ret = tegra_gmi_parse_dt(dev, priv);
> + if (ret)
> + return ret;
> +
> + ret = clk_prepare_enable(priv->clk);
> + if (ret) {
> + dev_err(dev, "fail to enable clock.\n");
> + return ret;
> + }
> +
> + reset_control_assert(priv->rst);
> + udelay(2);
> + reset_control_deassert(priv->rst);
> +
> + tegra_gmi_init(dev, priv);
> +
> + ret = of_platform_default_populate(dev->of_node, NULL, dev);
> + if (ret < 0) {
> + dev_err(dev, "fail to create devices.\n");
> + tegra_gmi_disable(priv);
> + return ret;
> + }
> +
> + dev_set_drvdata(dev, priv);
> +
> + return 0;
> +}
> +
> +static int tegra_gmi_remove(struct platform_device *pdev)
> +{
> + struct tegra_gmi_priv *priv = dev_get_drvdata(&pdev->dev);
> +
> + of_platform_depopulate(&pdev->dev);
> +
> + tegra_gmi_disable(priv);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id tegra_gmi_id_table[] = {
> + { .compatible = "nvidia,tegra20-gmi", },
> + { .compatible = "nvidia,tegra30-gmi", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, tegra_gmi_id_table);
> +
> +static struct platform_driver tegra_gmi_driver = {
> + .probe = tegra_gmi_probe,
> + .remove = tegra_gmi_remove,
> + .driver = {
> + .name = "tegra-gmi",
> + .of_match_table = tegra_gmi_id_table,
> + },
> +};
> +module_platform_driver(tegra_gmi_driver);
> +
> +MODULE_AUTHOR("Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org");
> +MODULE_DESCRIPTION("NVIDIA Tegra GMI Bus Driver");
> +MODULE_LICENSE("GPL v2");
> --
> 2.1.4
>
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH v3 5/6] Documentation: bindings: add documentation for ir-spi device driver
From: Jacek Anaszewski @ 2016-11-03 10:39 UTC (permalink / raw)
To: Andi Shyti
Cc: Mauro Carvalho Chehab, Sean Young, Rob Herring, Mark Rutland,
Richard Purdie, linux-media, devicetree, linux-leds, linux-kernel
In-Reply-To: <20161103101048.ofyoko4mkcypf44u@gangnam.samsung>
On 11/03/2016 11:10 AM, Andi Shyti wrote:
> Hi Jacek,
>
>> Only DT bindings of LED class drivers should be placed in
>> Documentation/devicetree/bindings/leds. Please move it to the
>> media bindings.
>
> that's where I placed it first, but Rob asked me to put it in the
> LED directory and Cc the LED mailining list.
>
> That's the discussion of the version 2:
>
> https://lkml.org/lkml/2016/9/12/380
>
> Rob, Jacek, could you please agree where I can put the binding?
I'm not sure if this is a good approach. I've noticed also that
backlight bindings have been moved to leds, whereas they don't look
similarly.
We have common.txt LED bindings, that all LED class drivers' bindings
have to follow. Neither backlight bindings nor these ones do that,
which introduces some mess.
Eventually adding a sub-directory, e.g. remote_control could make it
somehow logically justified, but still - shouldn't bindings be
placed in the documentation directory related to the subsystem of the
driver they are predestined to?
--
Best regards,
Jacek Anaszewski
^ permalink raw reply
* Re: [PATCH V3 5/6] ARM: tegra: Add Tegra20 GMI support
From: Jon Hunter @ 2016-11-03 10:29 UTC (permalink / raw)
To: Mirza Krak, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
pdeschrijver-DDmLM1+adcrQT0dZR+AlfA,
pgaikwad-DDmLM1+adcrQT0dZR+AlfA,
mturquette-rdvid1DuHRBWk0Htik3J/w, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1477576872-2665-6-git-send-email-mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> Add a device node for the GMI controller found on Tegra20.
>
> Signed-off-by: Mirza Krak <mirza.krak-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> Tested-by: Marcel Ziswiler <marcel.ziswiler-2KBjVHiyJgBBDgjK7y7TUQ@public.gmane.org>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> ---
>
> Changes in v2:
> - added address-cells, size-cells and ranges properties
>
> Changes in v3:
> - fixed range address which is not the same as Tegra30.
>
> arch/arm/boot/dts/tegra20.dtsi | 16 +++++++++++++++-
> 1 file changed, 15 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
> index 2207c08..b22cddb 100644
> --- a/arch/arm/boot/dts/tegra20.dtsi
> +++ b/arch/arm/boot/dts/tegra20.dtsi
> @@ -1,4 +1,4 @@
> -#include <dt-bindings/clock/tegra20-car.h>
> +include <dt-bindings/clock/tegra20-car.h>
After fixing up this, can you also ...
> #include <dt-bindings/gpio/tegra-gpio.h>
> #include <dt-bindings/pinctrl/pinctrl-tegra.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -376,6 +376,20 @@
> status = "disabled";
> };
>
> +
Drop this additional line?
> + gmi@70009000 {
> + compatible = "nvidia,tegra20-gmi";
> + reg = <0x70009000 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0xd0000000 0xfffffff>;
> + clocks = <&tegra_car TEGRA20_CLK_NOR>;
> + clock-names = "gmi";
> + resets = < &tegra_car 42>;
Get rid of this additional space?
> + reset-names = "gmi";
> + status = "disabled";
> + };
> +
Otherwise ...
Acked-by: Jon Hunter <jonathanh-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH 2/3] drm/bridge: Add ti-ftp410 HDMI transmitter driver
From: Tomi Valkeinen @ 2016-11-03 10:24 UTC (permalink / raw)
To: Jyri Sarha, dri-devel, devicetree
Cc: bcousson, khilman, bgolaszewski, laurent.pinchart
In-Reply-To: <9b6a6a4405de344cb9fbea735fea37adee1d726e.1478103726.git.jsarha@ti.com>
[-- Attachment #1.1.1: Type: text/plain, Size: 150 bytes --]
On 02/11/16 18:32, Jyri Sarha wrote:
> Add very basic ti-ftp410 HDMI transmitter driver. The only feature
It's DVI encoder, not HDMI.
Tomi
[-- Attachment #1.2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 819 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply
* Re: [PATCH V3 4/6] ARM: tegra: Add Tegra30 GMI support
From: Jon Hunter @ 2016-11-03 10:15 UTC (permalink / raw)
To: Mirza Krak, swarren, thierry.reding
Cc: gnurou, linux, pdeschrijver, pgaikwad, mturquette, sboyd, robh+dt,
mark.rutland, devicetree, linux-tegra, linux-kernel,
linux-arm-kernel, linux-clk
In-Reply-To: <1477576872-2665-5-git-send-email-mirza.krak@gmail.com>
On 27/10/16 15:01, Mirza Krak wrote:
> From: Mirza Krak <mirza.krak@gmail.com>
>
> Add a device node for the GMI controller found on Tegra30.
>
> Signed-off-by: Mirza Krak <mirza.krak@gmail.com>
> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
> Tested-on: Colibri T20/T30 on EvalBoard V3.x and GMI-Memory Board
> ---
>
> Changes in v2:
> - added address-cells, size-cells and ranges properties
>
> Changes in v3:
> - no changes
>
> arch/arm/boot/dts/tegra30.dtsi | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
> index 5030065..bbb1c00 100644
> --- a/arch/arm/boot/dts/tegra30.dtsi
> +++ b/arch/arm/boot/dts/tegra30.dtsi
> @@ -439,6 +439,19 @@
> status = "disabled";
> };
>
> + gmi@70009000 {
> + compatible = "nvidia,tegra30-gmi";
> + reg = <0x70009000 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <1>;
> + ranges = <0 0 0x48000000 0x7ffffff>;
> + clocks = <&tegra_car TEGRA30_CLK_NOR>;
> + clock-names = "gmi";
> + resets = <&tegra_car 42>;
> + reset-names = "gmi";
> + status = "disabled";
> + };
> +
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Cheers
Jon
--
nvpublic
^ permalink raw reply
* Re: [PATCH v3 5/6] Documentation: bindings: add documentation for ir-spi device driver
From: Andi Shyti @ 2016-11-03 10:10 UTC (permalink / raw)
To: Jacek Anaszewski
Cc: Mauro Carvalho Chehab, Sean Young, Rob Herring, Mark Rutland,
Richard Purdie, linux-media, devicetree, linux-leds, linux-kernel
In-Reply-To: <70f4426b-e2e6-1fb7-187a-65ed4bce0668@samsung.com>
Hi Jacek,
> Only DT bindings of LED class drivers should be placed in
> Documentation/devicetree/bindings/leds. Please move it to the
> media bindings.
that's where I placed it first, but Rob asked me to put it in the
LED directory and Cc the LED mailining list.
That's the discussion of the version 2:
https://lkml.org/lkml/2016/9/12/380
Rob, Jacek, could you please agree where I can put the binding?
Thanks,
Andi
^ permalink raw reply
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