* Re: [PATCH v2 1/3] binding: irqchip: mtk-cirq: Add binding document
From: Youlin Pei @ 2016-11-15 3:09 UTC (permalink / raw)
To: Rob Herring
Cc: Marc Zyngier, Matthias Brugger, Thomas Gleixner, Jason Cooper,
Mark Rutland, Russell King, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
hongkun.cao-NuS5LvNUpcJWk0Htik3J/w,
yong.wu-NuS5LvNUpcJWk0Htik3J/w, erin.lo-NuS5LvNUpcJWk0Htik3J/w,
chieh-jay.liu-NuS5LvNUpcJWk0Htik3J/w
In-Reply-To: <20161109182613.7tvzewua6ewxdvjc@rob-hp-laptop>
On Wed, 2016-11-09 at 12:26 -0600, Rob Herring wrote:
> On Tue, Nov 01, 2016 at 07:52:00PM +0800, Youlin Pei wrote:
> > This commit adds the device tree binding document for
> > the mediatek cirq.
> >
> > Signed-off-by: Youlin Pei <youlin.pei-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> > ---
> > .../interrupt-controller/mediatek,cirq.txt | 30 ++++++++++++++++++++
> > 1 file changed, 30 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
> >
> > diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
> > new file mode 100644
> > index 0000000..84e8123
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,cirq.txt
> > @@ -0,0 +1,30 @@
> > +* Mediatek 27xx cirq
> > +
> > +In Mediatek SOCs, the CIRQ is a low power interrupt controller designed to
> > +works outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
>
> s/works/work/
will fix in next version.
>
> > +The external interrupts (outside MCUSYS) will feed through CIRQ and connect
> > +to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
> > +interrupts and generated a pulse signal to parent interrupt controller when
>
> s/generated/generate/
will fix in next version.
>
> > +flush command is executed. With CIRQ, MCUSYS can be completely turned off
> > +to improve the system power consumption without losing interrupts.
> > +
> > +Required properties:
> > +- compatible: should be: "mediatek,mtk-cirq".
>
> This should be SoC specific. This is fine as a fallback if the same
> block is in many SoCs, but mediatek and mtk is a bit redundant.
>
In next version, i will improve as following:
- compatible: Should be one of
- "mediatek,mt2701-cirq" for mt2701 CIRQ
- "mediatek,mt8173-cirq" for mt8173 CIRQ
- "mediatek,mt8135-cirq" for mt8135 CIRQ
and "mediatek,cirq" as a fallback.
> > +- interrupt-controller : Identifies the node as an interrupt controller.
> > +- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
> > +- interrupt-parent: phandle of irq parent for cirq. The parent must
> > + use the same interrupt-cells format as GIC.
> > +- reg: Physical base address of the cirq registers and length of memory
> > + mapped region.
> > +- mediatek,ext-irq-start: Identifies external irq start number in different
> > + SOCs.
>
> Wouldn't this always be 32 if the GIC is the parent? If 32 is the common
> case, then use the SoC compatible to determine this value.
>
ext-irq-start is not always 32. In different Socs, this value is
different.
Thanks a lot!
> > +
> > +Example:
> > + cirq: interrupt-controller@10204000 {
> > + compatible = "mediatek,mtk-cirq";
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > + interrupt-parent = <&sysirq>;
> > + reg = <0 0x10204000 0 0x4000>;
> > + mediatek,ext-irq-start = <32>;
> > + };
> > --
> > 1.7.9.5
> >
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^ permalink raw reply
* Re: [PATCH v2 1/2] phy: rockchip-inno-usb2: correct clk_ops callback
From: wlf @ 2016-11-15 3:22 UTC (permalink / raw)
To: Doug Anderson
Cc: Kishon Vijay Abraham I, Heiko Stübner,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
open list:ARM/Rockchip SoC...,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Frank Wang, 黄涛, Brian Norris, Guenter Roeck
In-Reply-To: <CAD=FV=W36tdw3LqPq3tp58U4trYX6n=qaotMTsP6tm0QzZrRWQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Doug,
在 2016年11月15日 02:15, Doug Anderson 写道:
> William
>
> On Sun, Nov 13, 2016 at 11:01 PM, William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Since we needs to delay ~1ms to wait for 480MHz output clock
>> of USB2 PHY to become stable after turn on it, the delay time
>> is pretty long for something that's supposed to be "atomic"
>> like a clk_enable(). Consider that clk_enable() will disable
>> interrupt and that a 1ms interrupt latency is not sensible.
>>
>> The 480MHz output clock should be handled in prepare callbacks
>> which support gate a clk if the operation may sleep.
>>
>> Signed-off-by: William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------
>> 1 file changed, 6 insertions(+), 6 deletions(-)
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Thanks! I'll add Reviewed-by.
>
>
>
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^ permalink raw reply
* Re: [PATCH v3 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: wlf @ 2016-11-15 3:23 UTC (permalink / raw)
To: Doug Anderson
Cc: Kishon Vijay Abraham I, Heiko Stübner,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
open list:ARM/Rockchip SoC...,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Rob Herring,
Frank Wang, 黄涛, Brian Norris, Guenter Roeck
In-Reply-To: <CAD=FV=VJsuiXV3NS0uroF2OWJEDn5eiCpX-jP3BOYgLZ8gy6Hw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Doug,
在 2016年11月15日 02:17, Doug Anderson 写道:
> William,
>
> On Mon, Nov 14, 2016 at 1:27 AM, William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> We found that the system crashed due to 480MHz output clock of
>> USB2 PHY was unstable after clock had been enabled by gpu module.
>>
>> Theoretically, 1 millisecond is a critical value for 480MHz
>> output clock stable time, so we try to change the delay time
>> to 1.2 millisecond to avoid this issue.
>>
>> And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
>> clk_ops callback") used prepare callbacks instead of enable
>> callbacks to support gate a clk if the operation may sleep. So
>> we can switch from delay to sleep functions.
>>
>> Signed-off-by: William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>> Changes in v3:
>> - fix kbuild test error: too few arguments to function 'usleep_range'
>>
>> Changes in v2:
>> - use usleep_range() function instead of mdelay()
>>
>> drivers/phy/phy-rockchip-inno-usb2.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
>> index 365e077..0e52b25 100644
>> --- a/drivers/phy/phy-rockchip-inno-usb2.c
>> +++ b/drivers/phy/phy-rockchip-inno-usb2.c
>> @@ -166,7 +166,7 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
>> return ret;
>>
>> /* waitting for the clk become stable */
>> - mdelay(1);
>> + usleep_range(1200, 1300);
> Sight nit that you could also fix the spelling from "waitting" to "waiting".
>
> ...but that's pre-existing, so:
>
> Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Thanks! I'll add Reviewed-by and fix the spelling issue.
>
>
>
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^ permalink raw reply
* Re: [PATCH V3 1/9] PM / OPP: Reword binding supporting multiple regulators per device
From: Viresh Kumar @ 2016-11-15 3:31 UTC (permalink / raw)
To: Stephen Boyd
Cc: Rob Herring, Mark Brown, Rafael Wysocki, nm, Viresh Kumar,
linaro-kernel, linux-pm, linux-kernel, Vincent Guittot, d-gerlach,
devicetree
In-Reply-To: <20161115021302.GR5177@codeaurora.org>
First of all, thanks to all of you for commenting here. Please
continue doing so as I want to finish this stuff quickly, it has
already killed a lot of time :)
On 14-11-16, 18:13, Stephen Boyd wrote:
> On 11/14, Rob Herring wrote:
> > On Fri, Nov 11, 2016 at 08:41:20AM +0530, Viresh Kumar wrote:
> > > On 10-11-16, 14:51, Stephen Boyd wrote:
> > > >
> > > > No. The supply names (and also clock names/index) should be left
> > > > up to the consumer of the OPP table. We don't want to encode any
> > > > sort of details like this between the OPP table and the consumer
> > > > of it in DT because then it seriously couples the OPP table to
> > > > the consumer device. "The binding" in this case that needs to be
> > > > updated is the consumer binding, to indicate that it correlated
> > > > foo-supply and bar-supply to index 0 and 1 of the OPP table
> > > > voltages.
> > >
> > > Are you saying that we shall have a property like this then?
> > >
> > > diff --git a/Documentation/devicetree/bindings/opp/opp.txt b/Documentation/devicetree/bindings/opp/opp.txt
> > > index ee91cbdd95ee..733946df2fb8 100644
> > > --- a/Documentation/devicetree/bindings/opp/opp.txt
> > > +++ b/Documentation/devicetree/bindings/opp/opp.txt
> > > @@ -389,7 +389,10 @@ Example 4: Handling multiple regulators
> > > compatible = "arm,cortex-a7";
> > > ...
> > >
> > > - cpu-supply = <&cpu_supply0>, <&cpu_supply1>, <&cpu_supply2>;
> > > + vcc0-supply = <&cpu_supply0>;
> > > + vcc1-supply = <&cpu_supply1>;
> > > + vcc2-supply = <&cpu_supply2>;
> > > + opp-supply-names = "vcc0", "vcc1", "vcc2";
> >
> > Uh, no. You already have the names in the *-supply properties. Yes, they
> > are a PIA to retrieve compared to a *-names property, but that is the
> > nature of this style of binding.
Its not just PIA, but impossible AFAICT.
There are two important pieces of information we need for multiple
regulator support:
- Which regulator in the consumer node corresponds to which entry in
the OPP table. As Mark mentioned earlier, DT should be able to get
us this.
- The order in which the supplies need to be programmed. We have all
agreed to do this in code instead of inferring it from DT and this
patch series already does that.
I want to solve the first problem here and I don't see how it can be
solved using such entries:
cpus {
cpu@0 {
compatible = "arm,cortex-a7";
...
vcc0-supply = <&cpu_supply0>;
vcc1-supply = <&cpu_supply1>;
vcc2-supply = <&cpu_supply2>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
cpu0_opp_table: opp_table0 {
compatible = "operating-points-v2";
opp-shared;
opp@1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-microvolt = <970000>, /* Supply 0 */
<960000>, /* Supply 1 */
<960000>; /* Supply 2 */
};
};
The code can't figure out which of vcc0, vcc1, vcc2 is added first in
the CPU node and so we need to get the order somehow. A separate
binding as I mentioned earlier is a probably (ugly) solution.
> I think the problem is that Viresh wants the binding to be "self
> describing" so that the OPP can be used without a driver knowing
> that a supply corresponds to a particular column in the voltage
> table.
Right, and that's what Mark suggested as well.
> I don't understand that though. Can't we set the supply
> names from C code somewhere based on the consumer of the OPPs?
That's what this patch series is doing right now.
So, are you saying that the way this patchset does it is fine with you
?
--
viresh
^ permalink raw reply
* Re: [PATCH v2 1/4] dt-bindings: drm/bridge: adv7511: Add regulator bindings
From: Archit Taneja @ 2016-11-15 3:35 UTC (permalink / raw)
To: Rob Herring
Cc: Laurent Pinchart, Andy Gross, linux-arm-msm,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_Jsq+KMPoyWvh1U3OKL6pX8D4QByqVFgcMks8myDfZEYeFCg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 11/10/2016 07:04 AM, Rob Herring wrote:
> On Fri, Oct 14, 2016 at 12:40 AM, Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>> Hi Rob,
>>
>>
>> On 09/26/2016 01:42 PM, Laurent Pinchart wrote:
>>>
>>> Hi Archit,
>>>
>>> On Monday 26 Sep 2016 12:10:11 Archit Taneja wrote:
>>>>
>>>> On 9/25/2016 10:58 PM, Laurent Pinchart wrote:
>>>>>
>>>>> On Friday 23 Sep 2016 14:50:27 Archit Taneja wrote:
>>>>>>
>>>>>> Add the regulator supply properties needed by ADV7511 and ADV7533. The
>>>>>> regulator names are named after the pin names, except for DVDD_3V on
>>>>>> ADV7511, which is left v3p3 to have the same name as it's on ADV7533.
>>>>>>
>>>>>> ADV7511 has a BGVDD pin for which the voltage to be configured isn't
>>>>>> clear. This needs to be updated in the document later.
>>>>>>
>>>>>> The regulators are specified as optional properties since there can
>>>>>> be boards which have a fixed supply directly routed to the pins, and
>>>>>> these may not be modelled as regulator supplies.
>>>>>>
>>>>>> Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>>>>>> Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>>>>>> Signed-off-by: Archit Taneja <architt-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>>>>>> ---
>>>>>> v2:
>>>>>> - Specify regulator supplies for ADV7511 too.
>>>>>> - Have separate supply entries for AVDD, DVDD, PVDD, A2VDD pins.
>>>>>> - Add additional BGVDD supply for ADV7511.
>>>>>>
>>>>>> .../devicetree/bindings/display/bridge/adi,adv7511.txt | 14
>>>>>> +++++++
>>>>>> 1 file changed, 14 insertions(+)
>>>>>>
>>>>>> diff --git
>>>>>> a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
>>>>>> b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
>>>>>> index
>>>>>> 6532a59..66e6bae 100644
>>>>>> --- a/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
>>>>>> +++ b/Documentation/devicetree/bindings/display/bridge/adi,adv7511.txt
>>>>>>
>>>>>> @@ -56,6 +56,20 @@ Optional properties:
>>>>>> - adi,disable-timing-generator: Only for ADV7533. Disables the
>>>>>> internal
>>>>>>
>>>>>> timing generator. The chip will rely on the sync signals in the DSI
>>>>>> data
>>>>>> lanes, rather than generate its own timings for HDMI output.
>>>>>> +- avdd-supply: A 1.8V supply that powers up the AVDD pin on the chip.
>>>>>> +- dvdd-supply: A 1.8V supply that powers up the DVDD pin on the chip.
>>>>>> +- pvdd-supply: A 1.8V supply that powers up the PVDD pin on the chip.
>>>>>> +- v3p3-supply: A 3.3V supply that powers up the pin called DVDD_3V on
>>>>>> + ADV7511 and V3P3 on ADV7533.
>>>>>> +
>>>>>> +ADV7511 specific supplies:
>>>>>> +- bgvdd-supply: Powers the BGVDD pin. The voltage isn't clear from
>>>>>> + available datasheets.
>>>>>
>>>>>
>>>>> It's a 1.8V supply. The ADV7511 hardware user's guide recommends tying
>>>>> it
>>>>> to the PVDD supply, so I'm not sure we need a separate supply in DT.
>>>>
>>>>
>>>> Thanks for providing the info. I'll update it in the doc.
>>>>
>>>>> Similarly, the user's guide recommends supplying the AVDD, DVDD and PVDD
>>>>> pins with a single 1.8V LDO and three independent filters. We could thus
>>>>> possibly combine them into a single 1.8V supply.
>>>>
>>>>
>>>> I'd originally specified only one AVDD supply for all the 1.8 V
>>>> supplies, but Rob had recommended using separate supplies for each pin.
>>>>
>>>> I guess it doesn't do much harm specifying separate supplies, a
>>>> board can just provide avdd-supply, and the rest would be assumed dummy.
>>>
>>>
>>> DT should use the same regulator phandle for all power supplies in that
>>> case,
>>> not specify a single one.
>>>
>>>> It could also help describe boards which may not have followed the
>>>> user guide's recommendation, but I agree that's probably a rare
>>>> scenario.
>>>>
>>>> Is it okay if we stick with multiple supplies as it is in this version?
>>>
>>>
>>> It seems overkill to me but I can live with that. I'd remove the bgvdd
>>> supply
>>> though.
>>>
>>> Rob, what's your opinion on this ? Is there a specific reason why you
>>> prefer
>>> splitting the 1.8V supply in one supply per pin, when the hardware user's
>>> guide recommend powering them from the same LDO ?
>>
>>
>> Could you suggest us which way to go?
>
> If they are really intended to be the same supply, then combining them
> is fine with me.
Thanks, I'll change my patchset accordingly.
Archit
>
> Rob
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^ permalink raw reply
* [PATCH v4 0/2] phy: rockchip-inno-usb2: correct 480MHz clk_ops callbacks and stable time
From: William Wu @ 2016-11-15 3:54 UTC (permalink / raw)
To: kishon-l0cyMroinI0, heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frank.wang-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, dianders-hpIqsD4AKlfQT0dZR+AlfA,
briannorris-hpIqsD4AKlfQT0dZR+AlfA, groeck-hpIqsD4AKlfQT0dZR+AlfA,
wulf-TNX95d0MmH7DzftRWevZcw
This series try to correct the 480MHz output clock of USB2 PHY
clk_ops callback and fix the delay time. It aims to make the
480MHz clock gate more sensible and stable.
Tested on rk3366/rk3399 EVB board.
William Wu (2):
phy: rockchip-inno-usb2: correct clk_ops callback
phy: rockchip-inno-usb2: correct 480MHz output clock stable time
drivers/phy/phy-rockchip-inno-usb2.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
--
2.0.0
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^ permalink raw reply
* [PATCH v4 1/2] phy: rockchip-inno-usb2: correct clk_ops callback
From: William Wu @ 2016-11-15 3:54 UTC (permalink / raw)
To: kishon, heiko
Cc: linux-kernel, linux-arm-kernel, linux-rockchip, devicetree,
robh+dt, frank.wang, huangtao, dianders, briannorris, groeck,
wulf
In-Reply-To: <1479182047-3399-1-git-send-email-wulf@rock-chips.com>
Since we needs to delay ~1ms to wait for 480MHz output clock
of USB2 PHY to become stable after turn on it, the delay time
is pretty long for something that's supposed to be "atomic"
like a clk_enable(). Consider that clk_enable() will disable
interrupt and that a 1ms interrupt latency is not sensible.
The 480MHz output clock should be handled in prepare callbacks
which support gate a clk if the operation may sleep.
Signed-off-by: William Wu <wulf@rock-chips.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
---
Changes in v4:
- add Reviewed-by
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index ac20310..365e077 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -153,7 +153,7 @@ static inline bool property_enabled(struct rockchip_usb2phy *rphy,
return tmp == reg->enable;
}
-static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
+static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
@@ -172,7 +172,7 @@ static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
return 0;
}
-static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
+static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
@@ -181,7 +181,7 @@ static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
}
-static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
+static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
{
struct rockchip_usb2phy *rphy =
container_of(hw, struct rockchip_usb2phy, clk480m_hw);
@@ -197,9 +197,9 @@ rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
}
static const struct clk_ops rockchip_usb2phy_clkout_ops = {
- .enable = rockchip_usb2phy_clk480m_enable,
- .disable = rockchip_usb2phy_clk480m_disable,
- .is_enabled = rockchip_usb2phy_clk480m_enabled,
+ .prepare = rockchip_usb2phy_clk480m_prepare,
+ .unprepare = rockchip_usb2phy_clk480m_unprepare,
+ .is_prepared = rockchip_usb2phy_clk480m_prepared,
.recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
};
--
2.0.0
^ permalink raw reply related
* [PATCH v4 2/2] phy: rockchip-inno-usb2: correct 480MHz output clock stable time
From: William Wu @ 2016-11-15 3:54 UTC (permalink / raw)
To: kishon-l0cyMroinI0, heiko-4mtYJXux2i+zQB+pC5nmwQ
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frank.wang-TNX95d0MmH7DzftRWevZcw,
huangtao-TNX95d0MmH7DzftRWevZcw, dianders-hpIqsD4AKlfQT0dZR+AlfA,
briannorris-hpIqsD4AKlfQT0dZR+AlfA, groeck-hpIqsD4AKlfQT0dZR+AlfA,
wulf-TNX95d0MmH7DzftRWevZcw
In-Reply-To: <1479182047-3399-1-git-send-email-wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
We found that the system crashed due to 480MHz output clock of
USB2 PHY was unstable after clock had been enabled by gpu module.
Theoretically, 1 millisecond is a critical value for 480MHz
output clock stable time, so we try to change the delay time
to 1.2 millisecond to avoid this issue.
And the commit ed907fb1d7c3 ("phy: rockchip-inno-usb2: correct
clk_ops callback") used prepare callbacks instead of enable
callbacks to support gate a clk if the operation may sleep. So
we can switch from delay to sleep functions.
Also fix a spelling error from "waitting" to "waiting".
Signed-off-by: William Wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
---
Changes in v4:
- add Reviewed-by and fix a spelling error
Changes in v3:
- None
Changes in v2:
- None
drivers/phy/phy-rockchip-inno-usb2.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-rockchip-inno-usb2.c b/drivers/phy/phy-rockchip-inno-usb2.c
index 365e077..5d922fc 100644
--- a/drivers/phy/phy-rockchip-inno-usb2.c
+++ b/drivers/phy/phy-rockchip-inno-usb2.c
@@ -165,8 +165,8 @@ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
if (ret)
return ret;
- /* waitting for the clk become stable */
- mdelay(1);
+ /* waiting for the clk become stable */
+ usleep_range(1200, 1300);
}
return 0;
--
2.0.0
--
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^ permalink raw reply related
* Re: [PATCH v7 14/14] sdhci: sdhci-msm: update dll configuration
From: Ritesh Harjani @ 2016-11-15 4:23 UTC (permalink / raw)
To: Stephen Boyd
Cc: ulf.hansson, linux-mmc, adrian.hunter, shawn.lin, andy.gross,
devicetree, linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd, kdorfman,
david.griego, stummala, venkatg, rnayak, pramod.gurav,
Krishna Konda
In-Reply-To: <20161114195749.GJ5177@codeaurora.org>
On 11/15/2016 1:27 AM, Stephen Boyd wrote:
> On 11/14, Ritesh Harjani wrote:
>> @@ -903,7 +998,33 @@ static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>> config |= CORE_HC_SELECT_IN_EN;
>> writel_relaxed(config, host->ioaddr + CORE_VENDOR_SPEC);
>> }
>> + if (!msm_host->clk_rate && !msm_host->use_cdclp533) {
>> + /*
>> + * Poll on DLL_LOCK or DDR_DLL_LOCK bits in
>> + * CORE_DLL_STATUS to be set. This should get set
>> + * within 15 us at 200 MHz.
>> + */
>> + rc = readl_relaxed_poll_timeout(host->ioaddr +
>> + CORE_DLL_STATUS,
>> + dll_lock,
>> + (dll_lock &
>> + (CORE_DLL_LOCK |
>> + CORE_DDR_DLL_LOCK)), 10,
>> + 1000);
>> + if (rc == -ETIMEDOUT)
>> + pr_err("%s: Unable to get DLL_LOCK/DDR_DLL_LOCK, dll_status: 0x%08x\n",
>> + mmc_hostname(host->mmc), dll_lock);
>> + }
>> } else {
>> + if (!msm_host->use_cdclp533) {
>> + /* set CORE_PWRSAVE_DLL bit in CORE_VENDOR_SPEC3 */
>
> These types of comments are totally useless. The code says
> exactly what is being done, and the comment is actually wrong in
> this case. Please remove all these "set/clear bit X in register
> Y" comments.
Ok, done.
>
>> + config = readl_relaxed(host->ioaddr +
>> + CORE_VENDOR_SPEC3);
>> + config &= ~CORE_PWRSAVE_DLL;
>> + writel_relaxed(config, host->ioaddr +
>> + CORE_VENDOR_SPEC3);
>> + }
>> +
>> /* Select the default clock (free running MCLK) */
>> config = readl_relaxed(host->ioaddr + CORE_VENDOR_SPEC);
>> config &= ~CORE_HC_MCLK_SEL_MASK;
>> @@ -1100,6 +1221,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>> msm_host->use_14lpp_dll_reset = true;
>>
>> /*
>> + * SDCC 5 controller with major version 1, minor version 0x34 and later
>> + * with HS 400 mode support will use CM DLL instead of CDC LP 533 DLL.
>> + */
>> + if ((core_major == 1) && (core_minor < 0x34))
>
> Drop useless parenthesis please.
Done.
>
>> + msm_host->use_cdclp533 = true;
>> +
>> + /*
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v7 13/14] mmc: sdhci-msm: Add calibration tuning for CDCLP533 circuit
From: Ritesh Harjani @ 2016-11-15 4:24 UTC (permalink / raw)
To: Stephen Boyd
Cc: ulf.hansson, linux-mmc, adrian.hunter, shawn.lin, andy.gross,
devicetree, linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd, kdorfman,
david.griego, stummala, venkatg, rnayak, pramod.gurav
In-Reply-To: <20161114195928.GK5177@codeaurora.org>
On 11/15/2016 1:29 AM, Stephen Boyd wrote:
> On 11/14, Ritesh Harjani wrote:
>> @@ -575,6 +729,15 @@ static void sdhci_msm_set_uhs_signaling(struct sdhci_host *host,
>> dev_dbg(mmc_dev(mmc), "%s: clock=%u uhs=%u ctrl_2=0x%x\n",
>> mmc_hostname(host->mmc), host->clock, uhs, ctrl_2);
>> sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
>> +
>> + spin_unlock_irq(&host->lock);
>> + /* CDCLP533 HW calibration is only required for HS400 mode*/
>> + if (host->clock > CORE_FREQ_100MHZ &&
>> + msm_host->tuning_done && !msm_host->calibration_done &&
>> + (mmc->ios.timing == MMC_TIMING_MMC_HS400))
>
> Drop useless parenthesis.
Ok, sure.
>
>> + if (!sdhci_msm_cdclp533_calibration(host))
>> + msm_host->calibration_done = true;
>> + spin_lock_irq(&host->lock);
>> }
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v7 08/14] mmc: sdhci-msm: Implement set_clock callback for sdhci-msm
From: Ritesh Harjani @ 2016-11-15 5:10 UTC (permalink / raw)
To: Stephen Boyd, adrian.hunter
Cc: ulf.hansson, linux-mmc, shawn.lin, andy.gross, devicetree,
linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd, kdorfman,
david.griego, stummala, venkatg, rnayak, pramod.gurav
In-Reply-To: <20161114193004.GI5177@codeaurora.org>
Hi Stephen/Adrian,
On 11/15/2016 1:07 AM, Stephen Boyd wrote:
> On 11/14, Ritesh Harjani wrote:
>> @@ -577,6 +578,90 @@ static unsigned int sdhci_msm_get_min_clock(struct sdhci_host *host)
>> return SDHCI_MSM_MIN_CLOCK;
>> }
>>
>> +/**
>> + * __sdhci_msm_set_clock - sdhci_msm clock control.
>> + *
>> + * Description:
>> + * Implement MSM version of sdhci_set_clock.
>> + * This is required since MSM controller does not
>> + * use internal divider and instead directly control
>> + * the GCC clock as per HW recommendation.
>> + **/
>> +void __sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>> +{
>> + u16 clk;
>> + unsigned long timeout;
>> +
>> + /*
>> + * Keep actual_clock as zero -
>> + * - since there is no divider used so no need of having actual_clock.
>> + * - MSM controller uses SDCLK for data timeout calculation. If
>> + * actual_clock is zero, host->clock is taken for calculation.
>> + */
>> + host->mmc->actual_clock = 0;
>> +
>> + sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
>> +
>> + if (clock == 0)
>> + return;
>> +
>> + /*
>> + * MSM controller do not use clock divider.
>> + * Thus read SDHCI_CLOCK_CONTROL and only enable
>> + * clock with no divider value programmed.
>> + */
>> + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
>> +
>> + clk |= SDHCI_CLOCK_INT_EN;
>> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>> +
>> + /* Wait max 20 ms */
>> + timeout = 20;
>> + while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
>> + & SDHCI_CLOCK_INT_STABLE)) {
>> + if (timeout == 0) {
>> + pr_err("%s: Internal clock never stabilised\n",
>> + mmc_hostname(host->mmc));
>> + return;
>> + }
>> + timeout--;
>> + mdelay(1);
>> + }
>> +
>> + clk |= SDHCI_CLOCK_CARD_EN;
>> + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
>
> This is almost a copy/paste of sdhci_set_clock(). Can we make
> sdhci_set_clock() call a __sdhci_set_clock() function that takes
> unsigned int clock, and also a flag indicating if we want to set
> the internal clock divider or not? Then we can call
> __sdhci_set_clock() from sdhci_set_clock() with (clock, true) as
> arguments and (clock, false).
Adrian,
Could you please comment here ?
>
>> +}
>> +
>> +/* sdhci_msm_set_clock - Called with (host->lock) spinlock held. */
>> +static void sdhci_msm_set_clock(struct sdhci_host *host, unsigned int clock)
>> +{
>> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> + struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
>> + int rc;
>> +
>> + if (!clock) {
>> + msm_host->clk_rate = clock;
>> + goto out;
>> + }
>> +
>> + spin_unlock_irq(&host->lock);
>> + if (clock != msm_host->clk_rate) {
>
> Why do we need to check here? Can't we call clk_set_rate()
> Unconditionally?
Since it may so happen that above layers may call for ->set_clock
function with same requested clock more than once, hence we cache the
host->clock here.
Also, since requested clock (host->clock) can be say 400Mhz but the
actual pltfm supported clock would be say 384MHz.
>
>> + rc = clk_set_rate(msm_host->clk, clock);
>> + if (rc) {
>> + pr_err("%s: Failed to set clock at rate %u\n",
>> + mmc_hostname(host->mmc), clock);
>> + spin_lock_irq(&host->lock);
>> + goto out;
>
> Or replace the above two lines with goto err;
Ok, I will have another label out_lock instead of err.
>
>> + }
>> + msm_host->clk_rate = clock;
>> + pr_debug("%s: Setting clock at rate %lu\n",
>> + mmc_hostname(host->mmc), clk_get_rate(msm_host->clk));
>> + }
>
> And put an err label here.
will put the label here as out_lock;
>
>> + spin_lock_irq(&host->lock);
>> +out:
>> + __sdhci_msm_set_clock(host, clock);
>> +}
>> +
>> static const struct of_device_id sdhci_msm_dt_match[] = {
>> { .compatible = "qcom,sdhci-msm-v4" },
>> {},
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v7 04/14] ARM: dts: Add xo_clock to sdhc nodes on qcom platforms
From: Ritesh Harjani @ 2016-11-15 5:10 UTC (permalink / raw)
To: Stephen Boyd, adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
andy.gross-QSEj5FYQhm4dnm+yROfE0A
Cc: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ, kdorfman-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <20161114200115.GL5177-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 11/15/2016 1:31 AM, Stephen Boyd wrote:
> On 11/14, Ritesh Harjani wrote:
>> Add xo_clock to sdhc clock node on all qcom platforms.
>>
>> Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>> ---
>> arch/arm/boot/dts/qcom-apq8084.dtsi | 14 ++++++++------
>> arch/arm/boot/dts/qcom-msm8974.dtsi | 14 ++++++++------
>> arch/arm64/boot/dts/qcom/msm8916.dtsi | 10 ++++++----
>> arch/arm64/boot/dts/qcom/msm8996.dtsi | 9 +++++----
>> 4 files changed, 27 insertions(+), 20 deletions(-)
>>
>
> Is there an update to
> Documentation/devicetree/bindings/mmc/sdhci-msm.txt as well?
Sure, I will update.
>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [PATCH v2 2/2] of: changesets: Introduce changeset helper methods
From: Frank Rowand @ 2016-11-15 5:17 UTC (permalink / raw)
To: Rob Herring
Cc: Hans de Goede, Pantelis Antoniou,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <582A6B69.4070704-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Rob, Hans, Pantelis,
On 11/14/16 17:56, Frank Rowand wrote:
> On 11/14/16 14:16, Rob Herring wrote:
>> On Mon, Nov 14, 2016 at 12:44 PM, Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
< snip >
>>
>> These helpers are useful and easier to use than the existing API
>> independent of any issues to sort out with how we use overlays. So I
>> plan to take them whether there's a user right away or not.
>>
>> Rob
>
> OK, expect a more detailed review from me this week.
>
> -Frank
Part of my issues with these patches is related to using a format
string and the variables required by that format string as arguments
to several of the proposed helper functions. That construct is driven
by the helper functions calling __of_node_dup() which has that same
pattern of arguments. Blindly accepting a format string as an argument
to populate a buffer is not good from a security or robustness standpoint.
The only callers of __of_node_dup() are one site in drivers/of/overlay.c
and three sites in drivers/of/unittest.c.
I would like to see if I can find a good alternate to the format
string approach in __of_node_dup(), which would remove that issue
in the helper functions.
I do not expect Hans to fix the existing __of_node_dup(), I am
willing to do that myself.
Rob, are you in a hurry to accept the helper functions or are you
willing to give me some time to resolve the __of_node_dup() issue
and come up with a new version of the helper function patches?
Caveat, I have a hard deadline late Monday Nov 21 so I can't
start on this until Nov 22. Then that is Thanksgiving week and
I have some other work commitments that will demand much of my
time the next two weeks. I can commit to starting Nov 22, then
making it my top priority starting Dec 12.
-Frank
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^ permalink raw reply
* Re: [PATCH v2 2/2] ARM: dts: apq8064: add support to pm8821
From: Bjorn Andersson @ 2016-11-15 5:19 UTC (permalink / raw)
To: Srinivas Kandagatla
Cc: Lee Jones, Rob Herring, Andy Gross,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1479145933-9849-2-git-send-email-srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Mon 14 Nov 09:52 PST 2016, Srinivas Kandagatla wrote:
Acked-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Regards,
Bjorn
> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> ---
> arch/arm/boot/dts/qcom-apq8064.dtsi | 27 +++++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
> index 268bd47..c61ba32 100644
> --- a/arch/arm/boot/dts/qcom-apq8064.dtsi
> +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
> @@ -627,6 +627,33 @@
> clock-names = "core";
> };
>
> + ssbi@c00000 {
> + compatible = "qcom,ssbi";
> + reg = <0x00c00000 0x1000>;
> + qcom,controller-type = "pmic-arbiter";
> +
> + pm8821: pmic@1 {
> + compatible = "qcom,pm8821";
> + interrupt-parent = <&tlmm_pinmux>;
> + interrupts = <76 IRQ_TYPE_LEVEL_LOW>;
> + #interrupt-cells = <2>;
> + interrupt-controller;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pm8821_mpps: mpps@50 {
> + compatible = "qcom,pm8821-mpp", "qcom,ssbi-mpp";
> + reg = <0x50>;
> + interrupts = <24 IRQ_TYPE_NONE>,
> + <25 IRQ_TYPE_NONE>,
> + <26 IRQ_TYPE_NONE>,
> + <27 IRQ_TYPE_NONE>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> + };
> + };
> +
> qcom,ssbi@500000 {
> compatible = "qcom,ssbi";
> reg = <0x00500000 0x1000>;
> --
> 2.10.1
>
--
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^ permalink raw reply
* Re: [PATCH v18 2/2] drm/bridge: Add I2C based driver for ps8640 bridge
From: Archit Taneja @ 2016-11-15 6:03 UTC (permalink / raw)
To: Jitao Shi, David Airlie, Thierry Reding, Matthias Brugger
Cc: Rob Herring, Pawel Moll, Mark Rutland, Ian Campbell, Kumar Gala,
Ajay Kumar, Inki Dae, Rahul Sharma, Sean Paul, Vincent Palatin,
Andy Yan, Philipp Zabel, Russell King,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, Sascha Hauer,
yingjoe.chen-NuS5LvNUpcJWk0Htik3J/w, eddie.h
In-Reply-To: <1479130908-17593-2-git-send-email-jitao.shi-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Hi,
On 11/14/2016 07:11 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
Thanks for the incorporating the fixes. I have commented on one issue
below.
The only thing that seems to be left now is the firmware update bits, right?
Can we get the firmware pushed on the linux-firmware git repo [1]?
Or
Remove the firmware update parts for now (including the SPI stuff,
since that seems to be only used for writing fw)?
[1] http://git.kernel.org/cgit/linux/kernel/git/firmware/linux-firmware.git/
Thanks,
Archit
>
> Signed-off-by: Jitao Shi <jitao.shi-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> Reviewed-by: Daniel Kurtz <djkurtz-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
> Reviewed-by: Enric Balletbo i Serra <enric.balletbo-ZGY8ohtN/8qB+jHODAdFcQ@public.gmane.org>
> ---
> Changes since v17:
> - remove some unused head files.
> - add macros for ps8640 pages.
> - remove ddc_i2c client
> - add mipi_dsi_device_register_full
> - remove the manufacturer from the name and i2c_device_id
>
> Changes since v16:
> - Disable ps8640 DSI MCS Function.
> - Rename gpios name more clearly.
> - Tune the ps8640 power on sequence.
>
> Changes since v15:
> - Drop drm_connector_(un)register calls from parade ps8640.
> The main DRM driver mtk_drm_drv now calls
> drm_connector_register_all() after drm_dev_register() in the
> mtk_drm_bind() function. That function should iterate over all
> connectors and call drm_connector_register() for each of them.
> So, remove drm_connector_(un)register calls from parade ps8640.
>
> Changes since v14:
> - update copyright info.
> - change bridge_to_ps8640 and connector_to_ps8640 to inline function.
> - fix some coding style.
> - use sizeof as array counter.
> - use drm_get_edid when read edid.
> - add mutex when firmware updating.
>
> Changes since v13:
> - add const on data, ps8640_write_bytes(struct i2c_client *client, const u8 *data, u16 data_len)
> - fix PAGE2_SW_REST tyro.
> - move the buf[3] init to entrance of the function.
>
> Changes since v12:
> - fix hw_chip_id build warning
>
> Changes since v11:
> - Remove depends on I2C, add DRM depends
> - Reuse ps8640_write_bytes() in ps8640_write_byte()
> - Use timer check for polling like the routines in <linux/iopoll.h>
> - Fix no drm_connector_unregister/drm_connector_cleanup when ps8640_bridge_attach fail
> - Check the ps8640 hardware id in ps8640_validate_firmware
> - Remove fw_version check
> - Move ps8640_validate_firmware before ps8640_enter_bl
> - Add ddc_i2c unregister when probe fail and ps8640_remove
> ---
> drivers/gpu/drm/bridge/Kconfig | 12 +
> drivers/gpu/drm/bridge/Makefile | 1 +
> drivers/gpu/drm/bridge/parade-ps8640.c | 1079 ++++++++++++++++++++++++++++++++
> 3 files changed, 1092 insertions(+)
> create mode 100644 drivers/gpu/drm/bridge/parade-ps8640.c
>
> diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig
> index 10e12e7..7f41bbc 100644
> --- a/drivers/gpu/drm/bridge/Kconfig
> +++ b/drivers/gpu/drm/bridge/Kconfig
> @@ -57,6 +57,18 @@ config DRM_PARADE_PS8622
> ---help---
> Parade eDP-LVDS bridge chip driver.
>
> +config DRM_PARADE_PS8640
> + tristate "Parade PS8640 MIPI DSI to eDP Converter"
> + depends on DRM
> + depends on OF
> + select DRM_KMS_HELPER
> + select DRM_MIPI_DSI
> + select DRM_PANEL
> + ---help---
> + Choose this option if you have PS8640 for display
> + The PS8640 is a high-performance and low-power
> + MIPI DSI to eDP converter
> +
> config DRM_SII902X
> tristate "Silicon Image sii902x RGB/HDMI bridge"
> depends on OF
> diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile
> index cdf3a3c..7d93d40 100644
> --- a/drivers/gpu/drm/bridge/Makefile
> +++ b/drivers/gpu/drm/bridge/Makefile
> @@ -6,6 +6,7 @@ obj-$(CONFIG_DRM_DW_HDMI) += dw-hdmi.o
> obj-$(CONFIG_DRM_DW_HDMI_AHB_AUDIO) += dw-hdmi-ahb-audio.o
> obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
> obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
> +obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o
> obj-$(CONFIG_DRM_SII902X) += sii902x.o
> obj-$(CONFIG_DRM_TOSHIBA_TC358767) += tc358767.o
> obj-$(CONFIG_DRM_ANALOGIX_DP) += analogix/
> diff --git a/drivers/gpu/drm/bridge/parade-ps8640.c b/drivers/gpu/drm/bridge/parade-ps8640.c
> new file mode 100644
> index 0000000..2d9c337
> --- /dev/null
> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> @@ -0,0 +1,1079 @@
> +/*
> + * Copyright (c) 2016 MediaTek Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/err.h>
> +#include <linux/firmware.h>
> +#include <linux/gpio/consumer.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/of_graph.h>
> +#include <linux/regulator/consumer.h>
> +#include <asm/unaligned.h>
> +#include <drm/drm_panel.h>
> +
> +#include <drmP.h>
> +#include <drm_atomic_helper.h>
> +#include <drm_crtc_helper.h>
> +#include <drm_edid.h>
> +#include <drm_mipi_dsi.h>
> +
> +#define PAGE1_VSTART 0x6b
> +#define PAGE2_SPI_CFG3 0x82
> +#define I2C_TO_SPI_RESET 0x20
> +#define PAGE2_ROMADD_BYTE1 0x8e
> +#define PAGE2_ROMADD_BYTE2 0x8f
> +#define PAGE2_SWSPI_WDATA 0x90
> +#define PAGE2_SWSPI_RDATA 0x91
> +#define PAGE2_SWSPI_LEN 0x92
> +#define PAGE2_SWSPI_CTL 0x93
> +#define TRIGGER_NO_READBACK 0x05
> +#define TRIGGER_READBACK 0x01
> +#define PAGE2_SPI_STATUS 0x9e
> +#define SPI_READY 0x0c
> +#define PAGE2_GPIO_L 0xa6
> +#define PAGE2_GPIO_H 0xa7
> +#define PS_GPIO9 BIT(1)
> +#define PAGE2_IROM_CTRL 0xb0
> +#define IROM_ENABLE 0xc0
> +#define IROM_DISABLE 0x80
> +#define PAGE2_SW_RESET 0xbc
> +#define SPI_SW_RESET BIT(7)
> +#define MPU_SW_RESET BIT(6)
> +#define PAGE2_ENCTLSPI_WR 0xda
> +#define PAGE2_I2C_BYPASS 0xea
> +#define I2C_BYPASS_EN 0xd0
> +#define PAGE2_MCS_EN 0xf3
> +#define MCS_EN BIT(0)
> +#define PAGE3_SET_ADD 0xfe
> +#define PAGE3_SET_VAL 0xff
> +#define VDO_CTL_ADD 0x13
> +#define VDO_DIS 0x18
> +#define VDO_EN 0x1c
> +#define PAGE4_REV_L 0xf0
> +#define PAGE4_REV_H 0xf1
> +#define PAGE4_CHIP_L 0xf2
> +#define PAGE4_CHIP_H 0xf3
> +
> +#define PAGE0_DP_CNTL 0
> +#define PAGE1_VDO_BDG 1
> +#define PAGE2_TOP_CNTL 2
> +#define PAGE3_DSI_CNTL1 3
> +#define PAGE4_MIPI_PHY 4
> +#define PAGE5_VPLL 5
> +#define PAGE6_DSI_CNTL2 6
> +#define PAGE7_SPI_CNTL 7
> +#define MAX_DEVS 0x8
> +
> +/* Firmware */
> +#define PS_FW_NAME "ps864x_fw.bin"
> +
> +#define FW_CHIP_ID_OFFSET 0
> +#define FW_VERSION_OFFSET 2
> +#define EDID_I2C_ADDR 0x50
> +
> +#define WRITE_STATUS_REG_CMD 0x01
> +#define READ_STATUS_REG_CMD 0x05
> +#define BUSY BIT(0)
> +#define CLEAR_ALL_PROTECT 0x00
> +#define BLK_PROTECT_BITS 0x0c
> +#define STATUS_REG_PROTECT BIT(7)
> +#define WRITE_ENABLE_CMD 0x06
> +#define CHIP_ERASE_CMD 0xc7
> +
> +struct ps8640_info {
> + u8 family_id;
> + u8 variant_id;
> + u16 version;
> +};
> +
> +struct ps8640 {
> + struct drm_connector connector;
> + struct drm_bridge bridge;
> + struct edid *edid;
> + struct mipi_dsi_device *dsi;
> + struct i2c_client *page[MAX_DEVS];
> + struct regulator_bulk_data supplies[2];
> + struct drm_panel *panel;
> + struct gpio_desc *gpio_reset;
> + struct gpio_desc *gpio_power_down;
> + struct gpio_desc *gpio_mode_sel;
> + bool enabled;
> +
> + /* firmware file info */
> + struct ps8640_info info;
> + bool in_fw_update;
> + /* for firmware update protect */
> + struct mutex fw_mutex;
> +};
> +
> +static const u8 enc_ctrl_code[6] = { 0xaa, 0x55, 0x50, 0x41, 0x52, 0x44 };
> +static const u8 hw_chip_id[4] = { 0x00, 0x0a, 0x00, 0x30 };
> +
> +static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
> +{
> + return container_of(e, struct ps8640, bridge);
> +}
> +
> +static inline struct ps8640 *connector_to_ps8640(struct drm_connector *e)
> +{
> + return container_of(e, struct ps8640, connector);
> +}
> +
> +static int ps8640_read(struct i2c_client *client, u8 reg, u8 *data,
> + u16 data_len)
> +{
> + int ret;
> + struct i2c_msg msgs[] = {
> + {
> + .addr = client->addr,
> + .flags = 0,
> + .len = 1,
> + .buf = ®,
> + },
> + {
> + .addr = client->addr,
> + .flags = I2C_M_RD,
> + .len = data_len,
> + .buf = data,
> + }
> + };
> +
> + ret = i2c_transfer(client->adapter, msgs, 2);
> +
> + if (ret == 2)
> + return 0;
> + if (ret < 0)
> + return ret;
> + else
> + return -EIO;
> +}
> +
> +static int ps8640_write_bytes(struct i2c_client *client, const u8 *data,
> + u16 data_len)
> +{
> + int ret;
> + struct i2c_msg msg;
> +
> + msg.addr = client->addr;
> + msg.flags = 0;
> + msg.len = data_len;
> + msg.buf = (u8 *)data;
> +
> + ret = i2c_transfer(client->adapter, &msg, 1);
> + if (ret == 1)
> + return 0;
> + if (ret < 0)
> + return ret;
> + else
> + return -EIO;
> +}
> +
> +static int ps8640_write_byte(struct i2c_client *client, u8 reg, u8 data)
> +{
> + u8 buf[] = { reg, data };
> +
> + return ps8640_write_bytes(client, buf, sizeof(buf));
> +}
> +
> +static void ps8640_get_mcu_fw_version(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE5_VPLL];
> + u8 fw_ver[2];
> +
> + ps8640_read(client, 0x4, fw_ver, sizeof(fw_ver));
> + ps_bridge->info.version = (fw_ver[0] << 8) | fw_ver[1];
> +
> + DRM_INFO_ONCE("ps8640 rom fw version %d.%d\n", fw_ver[0], fw_ver[1]);
> +}
> +
> +static int ps8640_bridge_unmute(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
> + u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_EN };
> +
> + return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
> +}
> +
> +static int ps8640_bridge_mute(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
> + u8 vdo_ctrl_buf[3] = { PAGE3_SET_ADD, VDO_CTL_ADD, VDO_DIS };
> +
> + return ps8640_write_bytes(client, vdo_ctrl_buf, sizeof(vdo_ctrl_buf));
> +}
> +
> +static void ps8640_pre_enable(struct drm_bridge *bridge)
> +{
> + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + struct i2c_client *page1 = ps_bridge->page[PAGE1_VDO_BDG];
> + int err;
> + u8 set_vdo_done, mcs_en, vstart;
> + ktime_t timeout;
> +
> + if (ps_bridge->in_fw_update)
> + return;
> +
> + if (ps_bridge->enabled)
> + return;
> +
> + err = drm_panel_prepare(ps_bridge->panel);
> + if (err < 0) {
> + DRM_ERROR("failed to prepare panel: %d\n", err);
> + return;
> + }
> +
> + err = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
> + ps_bridge->supplies);
> + if (err < 0) {
> + DRM_ERROR("cannot enable regulators %d\n", err);
> + goto err_panel_unprepare;
> + }
> +
> + gpiod_set_value(ps_bridge->gpio_power_down, 1);
> + gpiod_set_value(ps_bridge->gpio_reset, 0);
> + usleep_range(2000, 2500);
> + gpiod_set_value(ps_bridge->gpio_reset, 1);
> +
> + /*
> + * Wait for the ps8640 embed mcu ready
> + * First wait 200ms and then check the mcu ready flag every 20ms
> + */
> + msleep(200);
> +
> + timeout = ktime_add_ms(ktime_get(), 200);
> + for (;;) {
> + err = ps8640_read(client, PAGE2_GPIO_H, &set_vdo_done, 1);
> + if (err < 0) {
> + DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", err);
> + goto err_regulators_disable;
> + }
> + if ((set_vdo_done & PS_GPIO9) == PS_GPIO9)
> + break;
> + if (ktime_compare(ktime_get(), timeout) > 0)
> + break;
> + msleep(20);
> + }
> +
> + msleep(50);
> +
> + ps8640_read(page1, PAGE1_VSTART, &vstart, 1);
> + DRM_INFO("PS8640 PAGE1.0x6B = 0x%x\n", vstart);
> +
> + /**
> + * The Manufacturer Command Set (MCS) is a device dependent interface
> + * intended for factory programming of the display module default
> + * parameters. Once the display module is configured, the MCS shall be
> + * disabled by the manufacturer. Once disabled, all MCS commands are
> + * ignored by the display interface.
> + */
> + ps8640_read(client, PAGE2_MCS_EN, &mcs_en, 1);
> + ps8640_write_byte(client, PAGE2_MCS_EN, mcs_en & ~MCS_EN);
> +
> + if (ps_bridge->info.version == 0)
> + ps8640_get_mcu_fw_version(ps_bridge);
> +
> + err = ps8640_bridge_unmute(ps_bridge);
> + if (err)
> + DRM_ERROR("failed to enable unmutevideo: %d\n", err);
> + /* Switch access edp panel's edid through i2c */
> + ps8640_write_byte(client, PAGE2_I2C_BYPASS, I2C_BYPASS_EN);
> + ps_bridge->enabled = true;
> +
> + return;
> +
> +err_regulators_disable:
> + regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
> + ps_bridge->supplies);
> +err_panel_unprepare:
> + drm_panel_unprepare(ps_bridge->panel);
> +}
> +
> +static void ps8640_enable(struct drm_bridge *bridge)
> +{
> + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> + int err;
> +
> + err = drm_panel_enable(ps_bridge->panel);
> + if (err < 0)
> + DRM_ERROR("failed to enable panel: %d\n", err);
> +}
> +
> +static void ps8640_disable(struct drm_bridge *bridge)
> +{
> + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> + int err;
> +
> + err = drm_panel_disable(ps_bridge->panel);
> + if (err < 0)
> + DRM_ERROR("failed to disable panel: %d\n", err);
> +}
> +
> +static void ps8640_post_disable(struct drm_bridge *bridge)
> +{
> + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> + int err;
> +
> + if (ps_bridge->in_fw_update)
> + return;
> +
> + if (!ps_bridge->enabled)
> + return;
> +
> + ps_bridge->enabled = false;
> +
> + err = ps8640_bridge_mute(ps_bridge);
> + if (err < 0)
> + DRM_ERROR("failed to unmutevideo: %d\n", err);
> +
> + gpiod_set_value(ps_bridge->gpio_reset, 0);
> + gpiod_set_value(ps_bridge->gpio_power_down, 0);
> + err = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
> + ps_bridge->supplies);
> + if (err < 0)
> + DRM_ERROR("cannot disable regulators %d\n", err);
> +
> + err = drm_panel_unprepare(ps_bridge->panel);
> + if (err)
> + DRM_ERROR("failed to unprepare panel: %d\n", err);
> +}
> +
> +static int ps8640_get_modes(struct drm_connector *connector)
> +{
> + struct ps8640 *ps_bridge = connector_to_ps8640(connector);
> + struct edid *edid;
> + int num_modes = 0;
> + bool power_off;
> +
> + if (ps_bridge->edid)
> + return drm_add_edid_modes(connector, ps_bridge->edid);
> +
> + power_off = !ps_bridge->enabled;
> + ps8640_pre_enable(&ps_bridge->bridge);
> +
> + edid = drm_get_edid(connector, ps_bridge->page[0]->adapter);
> + if (!edid)
> + goto out;
> +
> + ps_bridge->edid = edid;
> + drm_mode_connector_update_edid_property(connector, ps_bridge->edid);
> + num_modes = drm_add_edid_modes(connector, ps_bridge->edid);
> +
> +out:
> + if (power_off)
> + ps8640_post_disable(&ps_bridge->bridge);
> +
> + return num_modes;
> +}
> +
> +static const struct drm_connector_helper_funcs ps8640_connector_helper_funcs = {
> + .get_modes = ps8640_get_modes,
> +};
> +
> +static enum drm_connector_status ps8640_detect(struct drm_connector *connector,
> + bool force)
> +{
> + return connector_status_connected;
> +}
> +
> +static const struct drm_connector_funcs ps8640_connector_funcs = {
> + .dpms = drm_atomic_helper_connector_dpms,
> + .fill_modes = drm_helper_probe_single_connector_modes,
> + .detect = ps8640_detect,
> + .reset = drm_atomic_helper_connector_reset,
> + .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
> +};
> +
> +int ps8640_bridge_attach(struct drm_bridge *bridge)
> +{
> + struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
> + struct device *dev = &ps_bridge->page[0]->dev;
> + struct device_node *in_ep, *dsi_node = NULL;
> + struct mipi_dsi_device *dsi;
> + struct mipi_dsi_host *host = NULL;
> + int ret;
> + const struct mipi_dsi_device_info info = { .type = "ps8640",
> + .channel = 0,
> + .node = NULL,
> + };
> +
> + ret = drm_connector_init(bridge->dev, &ps_bridge->connector,
> + &ps8640_connector_funcs,
> + DRM_MODE_CONNECTOR_eDP);
> +
> + if (ret) {
> + DRM_ERROR("Failed to initialize connector with drm: %d\n", ret);
> + return ret;
> + }
> +
> + drm_connector_helper_add(&ps_bridge->connector,
> + &ps8640_connector_helper_funcs);
> +
> + ps_bridge->connector.dpms = DRM_MODE_DPMS_ON;
> + drm_mode_connector_attach_encoder(&ps_bridge->connector,
> + bridge->encoder);
> +
> + if (ps_bridge->panel)
> + drm_panel_attach(ps_bridge->panel, &ps_bridge->connector);
> +
> + /* port@0 is ps8640 dsi input port */
> + in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
> + if (in_ep) {
> + dsi_node = of_graph_get_remote_port_parent(in_ep);
> + of_node_put(in_ep);
> + }
> +
> + if (dsi_node) {
> + host = of_find_mipi_dsi_host_by_node(dsi_node);
> + of_node_put(dsi_node);
> + if (!host) {
> + ret = -ENODEV;
> + goto err;
> + }
> + }
There's still a possibility of us trying to register the dsi
device here to a null host.
Suggested code:
in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
if (!in_ep) {
ret = -ENODEV;
goto err;
}
dsi_node = of_graph_get_remote_port_parent(in_ep);
if (!dsi_node) {
of_node_put(in_ep);
ret = -ENODEV;
goto err;
}
of_node_put(in_ep);
of_node_put(dsi_node);
host = of_find_mipi_dsi_host_by_node(dsi_node);
if (!host) {
ret = -EPROBE_DEFER;
goto err;
}
Thanks,
Archit
> +
> + dsi = mipi_dsi_device_register_full(host, &info);
> + if (IS_ERR(dsi)) {
> + dev_err(dev, "failed to create dsi device\n");
> + ret = PTR_ERR(dsi);
> + goto err;
> + }
> +
> + ps_bridge->dsi = dsi;
> +
> + dsi->host = host;
> + dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
> + MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
> + dsi->format = MIPI_DSI_FMT_RGB888;
> + dsi->lanes = 4;
> + ret = mipi_dsi_attach(dsi);
> + if (ret)
> + goto err_dsi_attach;
> +
> + return 0;
> +
> +err_dsi_attach:
> + mipi_dsi_device_unregister(dsi);
> +err:
> + if (ps_bridge->panel)
> + drm_panel_detach(ps_bridge->panel);
> + drm_connector_cleanup(&ps_bridge->connector);
> + return ret;
> +}
> +
> +static const struct drm_bridge_funcs ps8640_bridge_funcs = {
> + .attach = ps8640_bridge_attach,
> + .disable = ps8640_disable,
> + .post_disable = ps8640_post_disable,
> + .pre_enable = ps8640_pre_enable,
> + .enable = ps8640_enable,
> +};
> +
> +/* Firmware Version is returned as Major.Minor */
> +static ssize_t ps8640_fw_version_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct ps8640 *ps_bridge = dev_get_drvdata(dev);
> + struct ps8640_info *info = &ps_bridge->info;
> +
> + return scnprintf(buf, PAGE_SIZE, "%u.%u\n", info->version >> 8,
> + info->version & 0xff);
> +}
> +
> +/* Hardware Version is returned as FamilyID.VariantID */
> +static ssize_t ps8640_hw_version_show(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct ps8640 *ps_bridge = dev_get_drvdata(dev);
> + struct ps8640_info *info = &ps_bridge->info;
> +
> + return scnprintf(buf, PAGE_SIZE, "ps%u.%u\n", info->family_id,
> + info->variant_id);
> +}
> +
> +static int ps8640_spi_send_cmd(struct ps8640 *ps_bridge, u8 *cmd, u8 cmd_len)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + u8 i, buf[3] = { PAGE2_SWSPI_LEN, cmd_len - 1, TRIGGER_NO_READBACK };
> + int ret;
> +
> + ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
> + if (ret)
> + goto err;
> +
> + /* write command in write port */
> + for (i = 0; i < cmd_len; i++) {
> + ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA, cmd[i]);
> + if (ret)
> + goto err_irom_disable;
> + }
> +
> + ret = ps8640_write_bytes(client, buf, sizeof(buf));
> + if (ret)
> + goto err_irom_disable;
> +
> + ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
> + if (ret)
> + goto err;
> +
> + return 0;
> +err_irom_disable:
> + ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
> +err:
> + dev_err(&client->dev, "send command err: %d\n", ret);
> + return ret;
> +}
> +
> +static int ps8640_wait_spi_ready(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + u8 spi_rdy_st;
> + ktime_t timeout;
> +
> + timeout = ktime_add_ms(ktime_get(), 200);
> + for (;;) {
> + ps8640_read(client, PAGE2_SPI_STATUS, &spi_rdy_st, 1);
> + if ((spi_rdy_st & SPI_READY) != SPI_READY)
> + break;
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(&client->dev, "wait spi ready timeout\n");
> + return -EBUSY;
> + }
> +
> + msleep(20);
> + }
> +
> + return 0;
> +}
> +
> +static int ps8640_wait_spi_nobusy(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + u8 spi_status, buf[3] = { PAGE2_SWSPI_LEN, 0, TRIGGER_READBACK };
> + int ret;
> + ktime_t timeout;
> +
> + timeout = ktime_add_ms(ktime_get(), 500);
> + for (;;) {
> + /* 0x05 RDSR; Read-Status-Register */
> + ret = ps8640_write_byte(client, PAGE2_SWSPI_WDATA,
> + READ_STATUS_REG_CMD);
> + if (ret)
> + goto err_send_cmd_exit;
> +
> + ret = ps8640_write_bytes(client, buf, 3);
> + if (ret)
> + goto err_send_cmd_exit;
> +
> + /* delay for cmd send */
> + usleep_range(300, 500);
> + /* wait for SPI ROM until not busy */
> + ret = ps8640_read(client, PAGE2_SWSPI_RDATA, &spi_status, 1);
> + if (ret)
> + goto err_send_cmd_exit;
> +
> + if (!(spi_status & BUSY))
> + break;
> +
> + if (ktime_compare(ktime_get(), timeout) > 0) {
> + dev_err(&client->dev, "wait spi no busy timeout: %d\n",
> + ret);
> + return -EBUSY;
> + }
> + }
> +
> + return 0;
> +
> +err_send_cmd_exit:
> + dev_err(&client->dev, "send command err: %d\n", ret);
> + return ret;
> +}
> +
> +static int ps8640_wait_rom_idle(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
> + int ret;
> +
> + ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
> + if (ret)
> + goto exit;
> +
> + ret = ps8640_wait_spi_ready(ps_bridge);
> + if (ret)
> + goto err_spi;
> +
> + ret = ps8640_wait_spi_nobusy(ps_bridge);
> + if (ret)
> + goto err_spi;
> +
> + ret = ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
> + if (ret)
> + goto exit;
> +
> + return 0;
> +
> +err_spi:
> + ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
> +exit:
> + dev_err(&client->dev, "wait ps8640 rom idle fail: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int ps8640_spi_dl_mode(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + int ret;
> +
> + /* switch ps8640 mode to spi dl mode */
> + if (ps_bridge->gpio_mode_sel)
> + gpiod_set_value(ps_bridge->gpio_mode_sel, 0);
> +
> + /* reset spi interface */
> + ret = ps8640_write_byte(client, PAGE2_SW_RESET,
> + SPI_SW_RESET | MPU_SW_RESET);
> + if (ret)
> + goto exit;
> +
> + ret = ps8640_write_byte(client, PAGE2_SW_RESET, MPU_SW_RESET);
> + if (ret)
> + goto exit;
> +
> + return 0;
> +
> +exit:
> + dev_err(&client->dev, "fail reset spi interface: %d\n", ret);
> +
> + return ret;
> +}
> +
> +static int ps8640_rom_prepare(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> + struct device *dev = &client->dev;
> + u8 i, cmd[2];
> + int ret;
> +
> + cmd[0] = WRITE_ENABLE_CMD;
> + ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
> + if (ret) {
> + dev_err(dev, "failed enable-write-status-register: %d\n", ret);
> + return ret;
> + }
> +
> + cmd[0] = WRITE_STATUS_REG_CMD;
> + cmd[1] = CLEAR_ALL_PROTECT;
> + ret = ps8640_spi_send_cmd(ps_bridge, cmd, 2);
> + if (ret) {
> + dev_err(dev, "fail disable all protection: %d\n", ret);
> + return ret;
> + }
> +
> + /* wait for SPI module ready */
> + ret = ps8640_wait_rom_idle(ps_bridge);
> + if (ret) {
> + dev_err(dev, "fail wait rom idle: %d\n", ret);
> + return ret;
> + }
> +
> + ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_ENABLE);
> + for (i = 0; i < ARRAY_SIZE(enc_ctrl_code); i++)
> + ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, enc_ctrl_code[i]);
> + ps8640_write_byte(client, PAGE2_IROM_CTRL, IROM_DISABLE);
> +
> + /* Enable-Write-Status-Register */
> + cmd[0] = WRITE_ENABLE_CMD;
> + ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
> + if (ret) {
> + dev_err(dev, "fail enable-write-status-register: %d\n", ret);
> + return ret;
> + }
> +
> + /* chip erase command */
> + cmd[0] = CHIP_ERASE_CMD;
> + ret = ps8640_spi_send_cmd(ps_bridge, cmd, 1);
> + if (ret) {
> + dev_err(dev, "fail disable all protection: %d\n", ret);
> + return ret;
> + }
> +
> + ret = ps8640_wait_rom_idle(ps_bridge);
> + if (ret) {
> + dev_err(dev, "fail wait rom idle: %d\n", ret);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int ps8640_check_chip_id(struct ps8640 *ps_bridge)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE4_MIPI_PHY];
> + u8 buf[4];
> +
> + ps8640_read(client, PAGE4_REV_L, buf, 4);
> + return memcmp(buf, hw_chip_id, sizeof(buf));
> +}
> +
> +static int ps8640_validate_firmware(struct ps8640 *ps_bridge,
> + const struct firmware *fw)
> +{
> + struct i2c_client *client = ps_bridge->page[0];
> + u16 fw_chip_id;
> +
> + /*
> + * Get the chip_id from the firmware. Make sure that it is the
> + * right controller to do the firmware and config update.
> + */
> + fw_chip_id = get_unaligned_le16(fw->data + FW_CHIP_ID_OFFSET);
> +
> + if (fw_chip_id != 0x8640 && ps8640_check_chip_id(ps_bridge) == 0) {
> + dev_err(&client->dev,
> + "chip id mismatch: fw 0x%x vs. chip 0x8640\n",
> + fw_chip_id);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int ps8640_write_rom(struct ps8640 *ps_bridge, const struct firmware *fw)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
> + struct device *dev = &client->dev;
> + struct i2c_client *client2 = ps_bridge->page[PAGE2_TOP_CNTL];
> + struct i2c_client *client7 = ps_bridge->page[PAGE7_SPI_CNTL];
> + size_t pos, cpy_len;
> + u8 buf[257];
> + int ret;
> +
> + ps8640_write_byte(client2, PAGE2_SPI_CFG3, I2C_TO_SPI_RESET);
> + msleep(100);
> + ps8640_write_byte(client2, PAGE2_SPI_CFG3, 0x00);
> +
> + for (pos = 0; pos < fw->size; pos += cpy_len) {
> + buf[0] = PAGE2_ROMADD_BYTE1;
> + buf[1] = pos >> 8;
> + buf[2] = pos >> 16;
> + ret = ps8640_write_bytes(client2, buf, 3);
> + if (ret)
> + goto error;
> + cpy_len = fw->size >= 256 + pos ? 256 : fw->size - pos;
> + buf[0] = 0;
> + memcpy(buf + 1, fw->data + pos, cpy_len);
> + ret = ps8640_write_bytes(client7, buf, cpy_len + 1);
> + if (ret)
> + goto error;
> +
> + dev_dbg(dev, "fw update completed %zu / %zu bytes\n", pos,
> + fw->size);
> + }
> + return 0;
> +
> +error:
> + dev_err(dev, "failed write external flash, %d\n", ret);
> + return ret;
> +}
> +
> +static int ps8640_spi_normal_mode(struct ps8640 *ps_bridge)
> +{
> + u8 cmd[2];
> + struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
> +
> + /* Enable-Write-Status-Register */
> + cmd[0] = WRITE_ENABLE_CMD;
> + ps8640_spi_send_cmd(ps_bridge, cmd, 1);
> +
> + /* protect BPL/BP0/BP1 */
> + cmd[0] = WRITE_STATUS_REG_CMD;
> + cmd[1] = BLK_PROTECT_BITS | STATUS_REG_PROTECT;
> + ps8640_spi_send_cmd(ps_bridge, cmd, 2);
> +
> + /* wait for SPI rom ready */
> + ps8640_wait_rom_idle(ps_bridge);
> +
> + /* disable PS8640 mapping function */
> + ps8640_write_byte(client, PAGE2_ENCTLSPI_WR, 0x00);
> +
> + if (ps_bridge->gpio_mode_sel)
> + gpiod_set_value(ps_bridge->gpio_mode_sel, 1);
> + return 0;
> +}
> +
> +static int ps8640_enter_bl(struct ps8640 *ps_bridge)
> +{
> + ps_bridge->in_fw_update = true;
> + return ps8640_spi_dl_mode(ps_bridge);
> +}
> +
> +static void ps8640_exit_bl(struct ps8640 *ps_bridge, const struct firmware *fw)
> +{
> + ps8640_spi_normal_mode(ps_bridge);
> + ps_bridge->in_fw_update = false;
> +}
> +
> +static int ps8640_load_fw(struct ps8640 *ps_bridge, const struct firmware *fw)
> +{
> + struct i2c_client *client = ps_bridge->page[PAGE0_DP_CNTL];
> + struct device *dev = &client->dev;
> + int ret;
> + bool ps8640_status_backup = ps_bridge->enabled;
> +
> + ret = ps8640_validate_firmware(ps_bridge, fw);
> + if (ret)
> + return ret;
> +
> + mutex_lock(&ps_bridge->fw_mutex);
> + if (!ps_bridge->in_fw_update) {
> + if (!ps8640_status_backup)
> + ps8640_pre_enable(&ps_bridge->bridge);
> +
> + ret = ps8640_enter_bl(ps_bridge);
> + if (ret)
> + goto exit;
> + }
> +
> + ret = ps8640_rom_prepare(ps_bridge);
> + if (ret)
> + goto exit;
> +
> + ret = ps8640_write_rom(ps_bridge, fw);
> +
> +exit:
> + if (ret)
> + dev_err(dev, "Failed to load firmware, %d\n", ret);
> +
> + ps8640_exit_bl(ps_bridge, fw);
> + if (!ps8640_status_backup)
> + ps8640_post_disable(&ps_bridge->bridge);
> + mutex_unlock(&ps_bridge->fw_mutex);
> + return ret;
> +}
> +
> +static ssize_t ps8640_update_fw_store(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t count)
> +{
> + struct i2c_client *client = to_i2c_client(dev);
> + struct ps8640 *ps_bridge = i2c_get_clientdata(client);
> + const struct firmware *fw;
> + int error;
> +
> + error = request_firmware(&fw, PS_FW_NAME, dev);
> + if (error) {
> + dev_err(dev, "Unable to open firmware %s: %d\n",
> + PS_FW_NAME, error);
> + return error;
> + }
> +
> + error = ps8640_load_fw(ps_bridge, fw);
> + if (error)
> + dev_err(dev, "The firmware update failed(%d)\n", error);
> + else
> + dev_info(dev, "The firmware update succeeded\n");
> +
> + release_firmware(fw);
> + return error ? error : count;
> +}
> +
> +static DEVICE_ATTR(fw_version, S_IRUGO, ps8640_fw_version_show, NULL);
> +static DEVICE_ATTR(hw_version, S_IRUGO, ps8640_hw_version_show, NULL);
> +static DEVICE_ATTR(update_fw, S_IWUSR, NULL, ps8640_update_fw_store);
> +
> +static struct attribute *ps8640_attrs[] = {
> + &dev_attr_fw_version.attr,
> + &dev_attr_hw_version.attr,
> + &dev_attr_update_fw.attr,
> + NULL
> +};
> +
> +static const struct attribute_group ps8640_attr_group = {
> + .attrs = ps8640_attrs,
> +};
> +
> +static void ps8640_remove_sysfs_group(void *data)
> +{
> + struct ps8640 *ps_bridge = data;
> +
> + sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
> +}
> +
> +static int ps8640_probe(struct i2c_client *client,
> + const struct i2c_device_id *id)
> +{
> + struct device *dev = &client->dev;
> + struct ps8640 *ps_bridge;
> + struct device_node *np = dev->of_node;
> + struct device_node *port, *out_ep;
> + struct device_node *panel_node = NULL;
> + int ret;
> + u32 i;
> +
> + ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
> + if (!ps_bridge)
> + return -ENOMEM;
> +
> + /* port@1 is ps8640 output port */
> + port = of_graph_get_port_by_id(np, 1);
> + if (port) {
> + out_ep = of_get_child_by_name(port, "endpoint");
> + of_node_put(port);
> + if (out_ep) {
> + panel_node = of_graph_get_remote_port_parent(out_ep);
> + of_node_put(out_ep);
> + }
> + }
> + if (panel_node) {
> + ps_bridge->panel = of_drm_find_panel(panel_node);
> + of_node_put(panel_node);
> + if (!ps_bridge->panel)
> + return -EPROBE_DEFER;
> + }
> +
> + mutex_init(&ps_bridge->fw_mutex);
> + ps_bridge->supplies[0].supply = "vdd33";
> + ps_bridge->supplies[1].supply = "vdd12";
> + ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
> + ps_bridge->supplies);
> + if (ret) {
> + dev_info(dev, "failed to get regulators: %d\n", ret);
> + return ret;
> + }
> +
> + ps_bridge->gpio_mode_sel = devm_gpiod_get_optional(&client->dev,
> + "mode-sel",
> + GPIOD_OUT_HIGH);
> + if (IS_ERR(ps_bridge->gpio_mode_sel)) {
> + ret = PTR_ERR(ps_bridge->gpio_mode_sel);
> + dev_err(dev, "cannot get mode-sel %d\n", ret);
> + return ret;
> + }
> +
> + ps_bridge->gpio_power_down = devm_gpiod_get(&client->dev, "sleep",
> + GPIOD_OUT_LOW);
> + if (IS_ERR(ps_bridge->gpio_power_down)) {
> + ret = PTR_ERR(ps_bridge->gpio_power_down);
> + dev_err(dev, "cannot get sleep: %d\n", ret);
> + return ret;
> + }
> +
> + /*
> + * Request the reset pin low to avoid the bridge being
> + * initialized prematurely
> + */
> + ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
> + GPIOD_OUT_LOW);
> + if (IS_ERR(ps_bridge->gpio_reset)) {
> + ret = PTR_ERR(ps_bridge->gpio_reset);
> + dev_err(dev, "cannot get reset: %d\n", ret);
> + return ret;
> + }
> +
> + ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
> + ps_bridge->bridge.of_node = dev->of_node;
> +
> + ps_bridge->page[0] = client;
> +
> + /*
> + * ps8640 uses multiple addresses, use dummy devices for them
> + * page[0]: for DP control
> + * page[1]: for VIDEO Bridge
> + * page[2]: for control top
> + * page[3]: for DSI Link Control1
> + * page[4]: for MIPI Phy
> + * page[5]: for VPLL
> + * page[6]: for DSI Link Control2
> + * page[7]: for spi rom mapping
> + */
> + for (i = 1; i < MAX_DEVS; i++) {
> + ps_bridge->page[i] = i2c_new_dummy(client->adapter,
> + client->addr + i);
> + if (!ps_bridge->page[i]) {
> + dev_err(dev, "failed i2c dummy device, address%02x\n",
> + client->addr + i);
> + ret = -EBUSY;
> + goto exit_dummy;
> + }
> + }
> + i2c_set_clientdata(client, ps_bridge);
> +
> + ret = sysfs_create_group(&client->dev.kobj, &ps8640_attr_group);
> + if (ret) {
> + dev_err(dev, "failed to create sysfs entries: %d\n", ret);
> + goto exit_dummy;
> + }
> +
> + ret = devm_add_action(dev, ps8640_remove_sysfs_group, ps_bridge);
> + if (ret) {
> + dev_err(dev, "failed to add sysfs cleanup action: %d\n", ret);
> + goto exit_remove_sysfs;
> + }
> +
> + ret = drm_bridge_add(&ps_bridge->bridge);
> + if (ret) {
> + dev_err(dev, "Failed to add bridge: %d\n", ret);
> + goto exit_remove_sysfs;
> + }
> + return 0;
> +
> +exit_remove_sysfs:
> + sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
> +exit_dummy:
> + while (--i)
> + i2c_unregister_device(ps_bridge->page[i]);
> + return ret;
> +}
> +
> +static int ps8640_remove(struct i2c_client *client)
> +{
> + struct ps8640 *ps_bridge = i2c_get_clientdata(client);
> + int i = MAX_DEVS;
> +
> + drm_bridge_remove(&ps_bridge->bridge);
> + sysfs_remove_group(&ps_bridge->page[0]->dev.kobj, &ps8640_attr_group);
> + while (--i)
> + i2c_unregister_device(ps_bridge->page[i]);
> +
> + return 0;
> +}
> +
> +static const struct i2c_device_id ps8640_i2c_table[] = {
> + { "ps8640", 0 },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(i2c, ps8640_i2c_table);
> +
> +static const struct of_device_id ps8640_match[] = {
> + { .compatible = "parade,ps8640" },
> + { /* sentinel */ },
> +};
> +MODULE_DEVICE_TABLE(of, ps8640_match);
> +
> +static struct i2c_driver ps8640_driver = {
> + .id_table = ps8640_i2c_table,
> + .probe = ps8640_probe,
> + .remove = ps8640_remove,
> + .driver = {
> + .name = "ps8640",
> + .of_match_table = ps8640_match,
> + },
> +};
> +module_i2c_driver(ps8640_driver);
> +
> +MODULE_AUTHOR("Jitao Shi <jitao.shi-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>");
> +MODULE_AUTHOR("CK Hu <ck.hu-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>");
> +MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
> +MODULE_LICENSE("GPL v2");
>
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^ permalink raw reply
* Re: [PATCH 3/3] powerpc/fsl/dts: add FMan node for t1042d4rdb
From: Scott Wood @ 2016-11-15 6:18 UTC (permalink / raw)
To: madalin.bucur-3arQi8VN3Tc, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, mpe-Gsx/Oe8HsFggBc27wqDAHg
In-Reply-To: <1478879598-3362-3-git-send-email-madalin.bucur-3arQi8VN3Tc@public.gmane.org>
On Fri, 2016-11-11 at 17:53 +0200, Madalin Bucur wrote:
> Signed-off-by: Madalin Bucur <madalin.bucur-3arQi8VN3Tc@public.gmane.org>
> ---
> arch/powerpc/boot/dts/fsl/t1042d4rdb.dts | 47
> ++++++++++++++++++++++++++++++++
> 1 file changed, 47 insertions(+)
>
> diff --git a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
> b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
> index 2a5a90d..8c0c318 100644
> --- a/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
> +++ b/arch/powerpc/boot/dts/fsl/t1042d4rdb.dts
> @@ -48,6 +48,53 @@
> "fsl,deepsleep-cpld";
> };
> };
> + soc: soc@ffe000000 {
Please leave a blank line between nodes, especially here at the top level.
-Scott
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* RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2016-11-15 6:45 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Bhaskar U,
oss@buserror.net, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20161114071308.GL3310@dragon>
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
>
> It seems that the patch is not generated against mainline kernel. We do not
> have fsl-ls1046a-qds.dtb target in mainline kernel.
You already clarified in the following mail :)
> > +
> > + reg_1p8v: regulator@0 {
>
> Drop the unit-address from node name, and name it like regulator-1p8v.
Ok. Will take care in V2
> > +
> > +&duart0 {
>
> Please sort labeled nodes alphabetically.
Ok Sure
>
> > + status = "okay";
> > +};
> > +
> > +&sai2 {
> > + status = "okay";
> > +};
>
> <snip>
>
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> > new file mode 100644
> > index 0000000..0bf5b64
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> > @@ -0,0 +1,248 @@
> > +/*
> > + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
> > + *
> > + * Copyright 2016, Freescale Semiconductor
> > + *
> > + * This file is dual-licensed: you can use it either under the terms
> > + * of the GPLv2 or the X11 license, at your option. Note that this
> > +dual
> > + * licensing only applies to this file, and not this project as a
> > + * whole.
> > + *
> > + * a) This library is free software; you can redistribute it and/or
> > + * modify it under the terms of the GNU General Public License as
> > + * published by the Free Software Foundation; either version 2 of the
> > + * License, or (at your option) any later version.
> > + *
> > + * This library is distributed in the hope that it will be useful,
> > + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> > + * GNU General Public License for more details.
> > + *
> > + * Or, alternatively,
> > + *
> > + * b) Permission is hereby granted, free of charge, to any person
> > + * obtaining a copy of this software and associated documentation
> > + * files (the "Software"), to deal in the Software without
> > + * restriction, including without limitation the rights to use,
> > + * copy, modify, merge, publish, distribute, sublicense, and/or
> > + * sell copies of the Software, and to permit persons to whom the
> > + * Software is furnished to do so, subject to the following
> > + * conditions:
> > + *
> > + * The above copyright notice and this permission notice shall be
> > + * included in all copies or substantial portions of the Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> > + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> > + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> > + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> > + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> > + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> > + * OTHER DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > + compatible = "fsl,ls1012a";
> > + interrupt-parent = <&gic>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > +
> > + cpus {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + cpu0: cpu@0 {
> > + device_type = "cpu";
> > + compatible = "arm,cortex-a53";
> > + reg = <0x0>;
> > + clocks = <&clockgen 1 0>;
> > + #cooling-cells = <2>;
> > + };
> > + };
> > +
> > + sysclk: sysclk {
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <100000000>;
> > + clock-output-names = "sysclk";
> > + };
> > +
> > + timer {
> > + compatible = "arm,armv8-timer";
> > + /* Physical Secure PPI */
> > + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> > + /* Physical Non-Secure PPI */
> > + <1 14 IRQ_TYPE_LEVEL_LOW>,
> > + /* Virtual PPI */
> > + <1 11 IRQ_TYPE_LEVEL_LOW>,
> > + /* Hypervisor PPI */
> > + <1 10 IRQ_TYPE_LEVEL_LOW>;
>
> The following form should be easier for read.
>
> interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure
> PPI */
> <1 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-
> Secure PPI */
> <1 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual PPI */
> <1 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor PPI
> */
>
>
Agreed. My bad. Will correct in v2
> > + };
> > +
> > + pmu {
> > + compatible = "arm,armv8-pmuv3";
> > + interrupts = <0 106 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + gic: interrupt-controller@1400000 {
> > + compatible = "arm,gic-400";
> > + #interrupt-cells = <3>;
> > + interrupt-controller;
> > + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> > + <0x0 0x1402000 0 0x2000>, /* GICC */
> > + <0x0 0x1404000 0 0x2000>, /* GICH */
> > + <0x0 0x1406000 0 0x2000>; /* GICV */
> > + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
> > + };
> > +
> > + reboot {
> > + compatible = "syscon-reboot";
> > + regmap = <&dcfg>;
> > + offset = <0xb0>;
> > + mask = <0x02>;
> > + };
> > +
> > + soc {
> > + compatible = "simple-bus";
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + clockgen: clocking@1ee1000 {
> > + compatible = "fsl,ls1012a-clockgen";
> > + reg = <0x0 0x1ee1000 0x0 0x1000>;
> > + #clock-cells = <2>;
> > + clocks = <&sysclk>;
> > + };
> > +
> > + scfg: scfg@1570000 {
> > + compatible = "fsl,ls1012a-scfg", "syscon";
> > + reg = <0x0 0x1570000 0x0 0x10000>;
> > + big-endian;
> > + };
>
> Please sort these nodes with unit-address in order of the address.
>
> Shawn
>
> > +
> > + dcfg: dcfg@1ee0000 {
> > + compatible = "fsl,ls1012a-dcfg",
> > + "syscon";
> > + reg = <0x0 0x1ee0000 0x0 0x10000>;
> > + big-endian;
> > + };
> > +
> > + i2c0: i2c@2180000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2180000 0x0 0x10000>;
> > + interrupts = <0 56 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 0>;
> > + status = "disabled";
> > + };
> > +
> > + i2c1: i2c@2190000 {
> > + compatible = "fsl,vf610-i2c";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + reg = <0x0 0x2190000 0x0 0x10000>;
> > + interrupts = <0 57 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 0>;
> > + status = "disabled";
> > + };
> > +
> > + duart0: serial@21c0500 {
> > + compatible = "fsl,ns16550", "ns16550a";
> > + reg = <0x00 0x21c0500 0x0 0x100>;
> > + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clockgen 4 0>;
> > + };
> > +
> > + duart1: serial@21c0600 {
> > + compatible = "fsl,ns16550", "ns16550a";
> > + reg = <0x00 0x21c0600 0x0 0x100>;
> > + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&clockgen 4 0>;
> > + };
> > +
> > + gpio0: gpio@2300000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2300000 0x0 0x10000>;
> > + interrupts = <0 66 IRQ_TYPE_LEVEL_LOW>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + gpio1: gpio@2310000 {
> > + compatible = "fsl,qoriq-gpio";
> > + reg = <0x0 0x2310000 0x0 0x10000>;
> > + interrupts = <0 67 IRQ_TYPE_LEVEL_LOW>;
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + interrupt-controller;
> > + #interrupt-cells = <2>;
> > + };
> > +
> > + wdog0: wdog@2ad0000 {
> > + compatible = "fsl,ls1012a-wdt",
> > + "fsl,imx21-wdt";
> > + reg = <0x0 0x2ad0000 0x0 0x10000>;
> > + interrupts = <0 83 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 0>;
> > + big-endian;
> > + };
> > +
> > + sai1: sai@2b50000 {
> > + #sound-dai-cells = <0>;
> > + compatible = "fsl,vf610-sai";
> > + reg = <0x0 0x2b50000 0x0 0x10000>;
> > + interrupts = <0 148 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> > + <&clockgen 4 3>, <&clockgen 4 3>;
> > + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> > + dma-names = "tx", "rx";
> > + dmas = <&edma0 1 47>,
> > + <&edma0 1 46>;
> > + status = "disabled";
> > + };
> > +
> > + sai2: sai@2b60000 {
> > + #sound-dai-cells = <0>;
> > + compatible = "fsl,vf610-sai";
> > + reg = <0x0 0x2b60000 0x0 0x10000>;
> > + interrupts = <0 149 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> > + <&clockgen 4 3>, <&clockgen 4 3>;
> > + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> > + dma-names = "tx", "rx";
> > + dmas = <&edma0 1 45>,
> > + <&edma0 1 44>;
> > + status = "disabled";
> > + };
> > +
> > + edma0: edma@2c00000 {
> > + #dma-cells = <2>;
> > + compatible = "fsl,vf610-edma";
> > + reg = <0x0 0x2c00000 0x0 0x10000>,
> > + <0x0 0x2c10000 0x0 0x10000>,
> > + <0x0 0x2c20000 0x0 0x10000>;
> > + interrupts = <0 103 IRQ_TYPE_LEVEL_LOW>,
> > + <0 103 IRQ_TYPE_LEVEL_LOW>;
> > + interrupt-names = "edma-tx", "edma-err";
> > + dma-channels = <32>;
> > + big-endian;
> > + clock-names = "dmamux0", "dmamux1";
> > + clocks = <&clockgen 4 3>,
> > + <&clockgen 4 3>;
> > + };
> > +
> > + sata: sata@3200000 {
> > + compatible = "fsl,ls1012a-ahci";
> > + reg = <0x0 0x3200000 0x0 0x10000>;
> > + interrupts = <0 69 IRQ_TYPE_LEVEL_LOW>;
> > + clocks = <&clockgen 4 0>;
> > + };
> > + };
> > +};
> > --
> > 2.7.4
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Harninder Rai @ 2016-11-15 6:46 UTC (permalink / raw)
To: Shawn Guo
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org, Bhaskar U,
oss@buserror.net, robh+dt@kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <DB5PR04MB16887A9480FD29B75735C707E6BF0@DB5PR04MB1688.eurprd04.prod.outlook.com>
> -----Original Message-----
> From: Harninder Rai
> Sent: Tuesday, November 15, 2016 12:15 PM
> To: 'Shawn Guo' <shawnguo@kernel.org>
> Cc: devicetree@vger.kernel.org; robh+dt@kernel.org;
> mark.rutland@arm.com; oss@buserror.net; Bhaskar U
> <bhaskar.upadhaya@nxp.com>; linux-arm-kernel@lists.infradead.org
> Subject: RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
>
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> > > dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb
> >
> > It seems that the patch is not generated against mainline kernel. We
> > do not have fsl-ls1046a-qds.dtb target in mainline kernel.
> You already clarified in the following mail :)
>
> > > +
> > > + reg_1p8v: regulator@0 {
> >
> > Drop the unit-address from node name, and name it like regulator-1p8v.
> Ok. Will take care in V2
>
> > > +
> > > +&duart0 {
> >
> > Please sort labeled nodes alphabetically.
> Ok Sure
> >
> > > + status = "okay";
> > > +};
> > > +
> > > +&sai2 {
> > > + status = "okay";
> > > +};
> >
> > <snip>
> > > + };
> > > +
> > > + timer {
> > > + compatible = "arm,armv8-timer";
> > > + /* Physical Secure PPI */
> > > + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Physical Non-Secure PPI */
> > > + <1 14 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Virtual PPI */
> > > + <1 11 IRQ_TYPE_LEVEL_LOW>,
> > > + /* Hypervisor PPI */
> > > + <1 10 IRQ_TYPE_LEVEL_LOW>;
> >
> > The following form should be easier for read.
> >
> > interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure
> PPI */
> > <1 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-
> Secure PPI */
> > <1 11 IRQ_TYPE_LEVEL_LOW>, /* Virtual PPI */
> > <1 10 IRQ_TYPE_LEVEL_LOW>; /* Hypervisor PPI
> */
> >
> >
> Agreed. My bad. Will correct in v2
>
> > > + scfg: scfg@1570000 {
> > > + compatible = "fsl,ls1012a-scfg", "syscon";
> > > + reg = <0x0 0x1570000 0x0 0x10000>;
> > > + big-endian;
> > > + };
> >
> > Please sort these nodes with unit-address in order of the address.
ok
> >
> > Shawn
^ permalink raw reply
* Re: [PATCH 1/5] pinctrl: core: Use delayed work for hogs
From: Linus Walleij @ 2016-11-15 6:52 UTC (permalink / raw)
To: Tony Lindgren
Cc: Haojian Zhuang, Masahiro Yamada, Grygorii Strashko,
Nishanth Menon,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Linux-OMAP
In-Reply-To: <20161115004703.GG4082-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
On Tue, Nov 15, 2016 at 1:47 AM, Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org> wrote:
> 8< --------------------------------
> From tony Mon Sep 17 00:00:00 2001
> From: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
> Date: Tue, 25 Oct 2016 08:33:35 -0700
> Subject: [PATCH] pinctrl: core: Use delayed work for hogs
>
> Having the pin control framework call pin controller functions
> before it's probe has finished is not nice as the pin controller
> device driver does not yet have struct pinctrl_dev handle.
>
> Let's fix this issue by adding deferred work for late init. This is
> needed to be able to add pinctrl generic helper functions that expect
> to know struct pinctrl_dev handle. Note that we now need to call
> create_pinctrl() directly as we don't want to add the pin controller
> to the list of controllers until the hogs are claimed. We also need
> to pass the pinctrl_dev to the device tree parser functions as they
> otherwise won't find the right controller at this point.
>
> Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
This looks a lot better!
So if I understand correctly, we can guarantee that the delayed
work will not execute until the device driver probe() has finished,
and it *will* execute immediately after that?
So:
- Device driver probes
- Delayed work is called
- Next initcall
I'm not 100% familiar with how delayed work works... :/
Yours,
Linus Walleij
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^ permalink raw reply
* [PATCH] clk: qcom: smd-rpm: Add msm8974 clocks
From: Bjorn Andersson @ 2016-11-15 6:54 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-clk-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA
This adds all RPM based clocks for msm8974 except cxo and gfx3d_clk_src.
Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
.../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
drivers/clk/qcom/clk-smd-rpm.c | 71 ++++++++++++++++++++++
include/dt-bindings/clock/qcom,rpmcc.h | 40 +++++++++++-
3 files changed, 110 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
index 87d3714b956a..a7235e9e1c97 100644
--- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
+++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
@@ -11,6 +11,7 @@ Required properties :
compatible "qcom,rpmcc" should be also included.
"qcom,rpmcc-msm8916", "qcom,rpmcc"
+ "qcom,rpmcc-msm8974", "qcom,rpmcc"
"qcom,rpmcc-apq8064", "qcom,rpmcc"
- #clock-cells : shall contain 1
diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
index a27013dbc0aa..b8fcac6f2f87 100644
--- a/drivers/clk/qcom/clk-smd-rpm.c
+++ b/drivers/clk/qcom/clk-smd-rpm.c
@@ -462,8 +462,79 @@ static const struct rpm_smd_clk_desc rpm_clk_msm8916 = {
.num_clks = ARRAY_SIZE(msm8916_clks),
};
+/* msm8974 */
+DEFINE_CLK_SMD_RPM(msm8974, pnoc_clk, pnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8974, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8974, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
+DEFINE_CLK_SMD_RPM(msm8974, mmssnoc_ahb_clk, mmssnoc_ahb_a_clk, QCOM_SMD_RPM_BUS_CLK, 3);
+DEFINE_CLK_SMD_RPM(msm8974, bimc_clk, bimc_a_clk, QCOM_SMD_RPM_MEM_CLK, 0);
+DEFINE_CLK_SMD_RPM(msm8974, gfx3d_clk_src, gfx3d_a_clk_src, QCOM_SMD_RPM_MEM_CLK, 1);
+DEFINE_CLK_SMD_RPM(msm8974, ocmemgx_clk, ocmemgx_a_clk, QCOM_SMD_RPM_MEM_CLK, 2);
+DEFINE_CLK_SMD_RPM_QDSS(msm8974, qdss_clk, qdss_a_clk, QCOM_SMD_RPM_MISC_CLK, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d0, cxo_d0_a, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_d1, cxo_d1_a, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a0, cxo_a0_a, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a1, cxo_a1_a, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, cxo_a2, cxo_a2_a, 6);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, diff_clk, diff_a_clk, 7);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk1, div_a_clk1, 11);
+DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8974, div_clk2, div_a_clk2, 12);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d0_pin, cxo_d0_a_pin, 1);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_d1_pin, cxo_d1_a_pin, 2);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a0_pin, cxo_a0_a_pin, 4);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a1_pin, cxo_a1_a_pin, 5);
+DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8974, cxo_a2_pin, cxo_a2_a_pin, 6);
+
+static struct clk_smd_rpm *msm8974_clks[] = {
+ [RPM_SMD_PNOC_CLK] = &msm8974_pnoc_clk,
+ [RPM_SMD_PNOC_A_CLK] = &msm8974_pnoc_a_clk,
+ [RPM_SMD_SNOC_CLK] = &msm8974_snoc_clk,
+ [RPM_SMD_SNOC_A_CLK] = &msm8974_snoc_a_clk,
+ [RPM_SMD_CNOC_CLK] = &msm8974_cnoc_clk,
+ [RPM_SMD_CNOC_A_CLK] = &msm8974_cnoc_a_clk,
+ [RPM_SMD_MMSSNOC_AHB_CLK] = &msm8974_mmssnoc_ahb_clk,
+ [RPM_SMD_MMSSNOC_AHB_A_CLK] = &msm8974_mmssnoc_ahb_a_clk,
+ [RPM_SMD_BIMC_CLK] = &msm8974_bimc_clk,
+ [RPM_SMD_BIMC_A_CLK] = &msm8974_bimc_a_clk,
+ [RPM_SMD_OCMEMGX_CLK] = &msm8974_ocmemgx_clk,
+ [RPM_SMD_OCMEMGX_A_CLK] = &msm8974_ocmemgx_a_clk,
+ [RPM_SMD_QDSS_CLK] = &msm8974_qdss_clk,
+ [RPM_SMD_QDSS_A_CLK] = &msm8974_qdss_a_clk,
+ [RPM_SMD_CXO_D0] = &msm8974_cxo_d0,
+ [RPM_SMD_CXO_D0_A] = &msm8974_cxo_d0_a,
+ [RPM_SMD_CXO_D1] = &msm8974_cxo_d1,
+ [RPM_SMD_CXO_D1_A] = &msm8974_cxo_d1_a,
+ [RPM_SMD_CXO_A0] = &msm8974_cxo_a0,
+ [RPM_SMD_CXO_A0_A] = &msm8974_cxo_a0_a,
+ [RPM_SMD_CXO_A1] = &msm8974_cxo_a1,
+ [RPM_SMD_CXO_A1_A] = &msm8974_cxo_a1_a,
+ [RPM_SMD_CXO_A2] = &msm8974_cxo_a2,
+ [RPM_SMD_CXO_A2_A] = &msm8974_cxo_a2_a,
+ [RPM_SMD_DIFF_CLK] = &msm8974_diff_clk,
+ [RPM_SMD_DIFF_A_CLK] = &msm8974_diff_a_clk,
+ [RPM_SMD_DIV_CLK1] = &msm8974_div_clk1,
+ [RPM_SMD_DIV_A_CLK1] = &msm8974_div_a_clk1,
+ [RPM_SMD_DIV_CLK2] = &msm8974_div_clk2,
+ [RPM_SMD_DIV_A_CLK2] = &msm8974_div_a_clk2,
+ [RPM_SMD_CXO_D0_PIN] = &msm8974_cxo_d0_pin,
+ [RPM_SMD_CXO_D0_A_PIN] = &msm8974_cxo_d0_a_pin,
+ [RPM_SMD_CXO_D1_PIN] = &msm8974_cxo_d1_pin,
+ [RPM_SMD_CXO_D1_A_PIN] = &msm8974_cxo_d1_a_pin,
+ [RPM_SMD_CXO_A0_PIN] = &msm8974_cxo_a0_pin,
+ [RPM_SMD_CXO_A0_A_PIN] = &msm8974_cxo_a0_a_pin,
+ [RPM_SMD_CXO_A1_PIN] = &msm8974_cxo_a1_pin,
+ [RPM_SMD_CXO_A1_A_PIN] = &msm8974_cxo_a1_a_pin,
+ [RPM_SMD_CXO_A2_PIN] = &msm8974_cxo_a2_pin,
+ [RPM_SMD_CXO_A2_A_PIN] = &msm8974_cxo_a2_a_pin,
+};
+
+static const struct rpm_smd_clk_desc rpm_clk_msm8974 = {
+ .clks = msm8974_clks,
+ .num_clks = ARRAY_SIZE(msm8974_clks),
+};
static const struct of_device_id rpm_smd_clk_match_table[] = {
{ .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
+ { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
{ }
};
MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
diff --git a/include/dt-bindings/clock/qcom,rpmcc.h b/include/dt-bindings/clock/qcom,rpmcc.h
index 5924cdb71336..96b63c00249e 100644
--- a/include/dt-bindings/clock/qcom,rpmcc.h
+++ b/include/dt-bindings/clock/qcom,rpmcc.h
@@ -14,7 +14,7 @@
#ifndef _DT_BINDINGS_CLK_MSM_RPMCC_H
#define _DT_BINDINGS_CLK_MSM_RPMCC_H
-/* apq8064 */
+/* RPM clocks */
#define RPM_PXO_CLK 0
#define RPM_PXO_A_CLK 1
#define RPM_CXO_CLK 2
@@ -38,7 +38,7 @@
#define RPM_SFPB_CLK 20
#define RPM_SFPB_A_CLK 21
-/* msm8916 */
+/* SMD RPM clocks */
#define RPM_SMD_XO_CLK_SRC 0
#define RPM_SMD_XO_A_CLK_SRC 1
#define RPM_SMD_PCNOC_CLK 2
@@ -65,5 +65,41 @@
#define RPM_SMD_RF_CLK1_A_PIN 23
#define RPM_SMD_RF_CLK2_PIN 24
#define RPM_SMD_RF_CLK2_A_PIN 25
+#define RPM_SMD_PNOC_CLK 26
+#define RPM_SMD_PNOC_A_CLK 27
+#define RPM_SMD_CNOC_CLK 28
+#define RPM_SMD_CNOC_A_CLK 29
+#define RPM_SMD_MMSSNOC_AHB_CLK 30
+#define RPM_SMD_MMSSNOC_AHB_A_CLK 31
+#define RPM_SMD_GFX3D_CLK_SRC 32
+#define RPM_SMD_GFX3D_A_CLK_SRC 33
+#define RPM_SMD_OCMEMGX_CLK 34
+#define RPM_SMD_OCMEMGX_A_CLK 35
+#define RPM_SMD_CXO_D0 36
+#define RPM_SMD_CXO_D0_A 37
+#define RPM_SMD_CXO_D1 38
+#define RPM_SMD_CXO_D1_A 39
+#define RPM_SMD_CXO_A0 40
+#define RPM_SMD_CXO_A0_A 41
+#define RPM_SMD_CXO_A1 42
+#define RPM_SMD_CXO_A1_A 43
+#define RPM_SMD_CXO_A2 44
+#define RPM_SMD_CXO_A2_A 45
+#define RPM_SMD_DIV_CLK1 46
+#define RPM_SMD_DIV_A_CLK1 47
+#define RPM_SMD_DIV_CLK2 48
+#define RPM_SMD_DIV_A_CLK2 49
+#define RPM_SMD_DIFF_CLK 50
+#define RPM_SMD_DIFF_A_CLK 51
+#define RPM_SMD_CXO_D0_PIN 52
+#define RPM_SMD_CXO_D0_A_PIN 53
+#define RPM_SMD_CXO_D1_PIN 54
+#define RPM_SMD_CXO_D1_A_PIN 55
+#define RPM_SMD_CXO_A0_PIN 56
+#define RPM_SMD_CXO_A0_A_PIN 57
+#define RPM_SMD_CXO_A1_PIN 58
+#define RPM_SMD_CXO_A1_A_PIN 59
+#define RPM_SMD_CXO_A2_PIN 60
+#define RPM_SMD_CXO_A2_A_PIN 61
#endif
--
2.5.0
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^ permalink raw reply related
* Re: [PATCH v7 2/5] mm: remove x86-only restriction of movable_node
From: Aneesh Kumar K.V @ 2016-11-15 7:05 UTC (permalink / raw)
To: Reza Arbab, Michael Ellerman, Benjamin Herrenschmidt,
Paul Mackerras, Andrew Morton, Rob Herring, Frank Rowand,
Thomas Gleixner, Ingo Molnar, H. Peter Anvin
Cc: linuxppc-dev, linux-mm, devicetree, Bharata B Rao,
Nathan Fontenot, Stewart Smith, Alistair Popple, Balbir Singh,
linux-kernel
In-Reply-To: <1479160961-25840-3-git-send-email-arbab@linux.vnet.ibm.com>
Reza Arbab <arbab@linux.vnet.ibm.com> writes:
> In commit c5320926e370 ("mem-hotplug: introduce movable_node boot
> option"), the memblock allocation direction is changed to bottom-up and
> then back to top-down like this:
>
> 1. memblock_set_bottom_up(true), called by cmdline_parse_movable_node().
> 2. memblock_set_bottom_up(false), called by x86's numa_init().
>
> Even though (1) occurs in generic mm code, it is wrapped by #ifdef
> CONFIG_MOVABLE_NODE, which depends on X86_64.
>
> This means that when we extend CONFIG_MOVABLE_NODE to non-x86 arches,
> things will be unbalanced. (1) will happen for them, but (2) will not.
>
> This toggle was added in the first place because x86 has a delay between
> adding memblocks and marking them as hotpluggable. Since other arches do
> this marking either immediately or not at all, they do not require the
> bottom-up toggle.
>
> So, resolve things by moving (1) from cmdline_parse_movable_node() to
> x86's setup_arch(), immediately after the movable_node parameter has
> been parsed.
Considering that we now can mark memblock hotpluggable, do we need to
enable the bottom up allocation for ppc64 also ?
>
> Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
> ---
> Documentation/kernel-parameters.txt | 2 +-
> arch/x86/kernel/setup.c | 24 ++++++++++++++++++++++++
-aneesh
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^ permalink raw reply
* RE: [PATCH 2/3] devicetree: bindings: nvmem: Add compatible string for imx6ul
From: Jacky Bai @ 2016-11-15 7:25 UTC (permalink / raw)
To: Rob Herring
Cc: mark.rutland@arm.com, devicetree@vger.kernel.org,
srinivas.kandagatla@linaro.org, kernel@pengutronix.de,
Fabio Estevam, maxime.ripard@free-electrons.com,
shawnguo@kernel.org, linux-arm-kernel@lists.infradead.org
In-Reply-To: <20161114161423.fs7dlt5firmj4q3s@rob-hp-laptop>
> > Add new compatible string for i.MX6UL SOC.
> >
> > Signed-off-by: Bai Ping <ping.bai@nxp.com>
> > ---
> > Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 7 ++++---
> > 1 file changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > index 383d588..a7ff65d 100644
> > --- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > +++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
> > @@ -1,13 +1,14 @@
> > Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
> >
> > This binding represents the on-chip eFuse OTP controller found on
> > -i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
> > +i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
> >
> > Required properties:
> > - compatible: should be one of
> > "fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
> > - "fsl,imx6sl-ocotp" (i.MX6SL), or
> > - "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
> > + "fsl,imx6sl-ocotp" (i.MX6SL),
> > + "fsl,imx6sx-ocotp" (i.MX6SX), or
> > + "fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
>
> This should be reformatted such that it's not a 5 line change to add a
> compatible. "one of" defines this is an OR relationship, so drop that.
> Move 'followed by "syscon"' to below the list of compatibles.
>
Thanks for review, I will adopt in V2.
Jacky Bai
> > - reg: Should contain the register base and length.
> > - clocks: Should contain a phandle pointing to the gated peripheral clock.
> >
> > --
> > 2.8.2
> >
> >
> > _______________________________________________
> > linux-arm-kernel mailing list
> > linux-arm-kernel@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] [media] ir-hix5hd2: make hisilicon,power-syscon property deprecated
From: Jiancheng Xue @ 2016-11-15 7:31 UTC (permalink / raw)
To: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
mchehab-DgEjT+Ai2ygdnm+yROfE0A
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA,
yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q,
xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
hermit.wangheming-C8/M+/jPZTeaMJb+Lgu22Q,
elder-QSEj5FYQhm4dnm+yROfE0A, bin.chen-QSEj5FYQhm4dnm+yROfE0A,
Ruqiang Ju
From: Ruqiang Ju <juruqiang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
The clock of IR can be provided by the clock provider and controlled
by common clock framework APIs.
Signed-off-by: Ruqiang Ju <juruqiang-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
Signed-off-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
.../devicetree/bindings/media/hix5hd2-ir.txt | 6 +++---
drivers/media/rc/ir-hix5hd2.c | 25 ++++++++++++++--------
2 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
index fb5e760..54e1bed 100644
--- a/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
+++ b/Documentation/devicetree/bindings/media/hix5hd2-ir.txt
@@ -8,10 +8,11 @@ Required properties:
the device. The interrupt specifier format depends on the interrupt
controller parent.
- clocks: clock phandle and specifier pair.
- - hisilicon,power-syscon: phandle of syscon used to control power.
Optional properties:
- linux,rc-map-name : Remote control map name.
+ - hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
+ Provide correct clocks instead.
Example node:
@@ -19,7 +20,6 @@ Example node:
compatible = "hisilicon,hix5hd2-ir";
reg = <0xf8001000 0x1000>;
interrupts = <0 47 4>;
- clocks = <&clock HIX5HD2_FIXED_24M>;
- hisilicon,power-syscon = <&sysctrl>;
+ clocks = <&clock HIX5HD2_IR_CLOCK>;
linux,rc-map-name = "rc-tivo";
};
diff --git a/drivers/media/rc/ir-hix5hd2.c b/drivers/media/rc/ir-hix5hd2.c
index d0549fb..d26907e 100644
--- a/drivers/media/rc/ir-hix5hd2.c
+++ b/drivers/media/rc/ir-hix5hd2.c
@@ -75,15 +75,22 @@ static void hix5hd2_ir_enable(struct hix5hd2_ir_priv *dev, bool on)
{
u32 val;
- regmap_read(dev->regmap, IR_CLK, &val);
- if (on) {
- val &= ~IR_CLK_RESET;
- val |= IR_CLK_ENABLE;
+ if (dev->regmap) {
+ regmap_read(dev->regmap, IR_CLK, &val);
+ if (on) {
+ val &= ~IR_CLK_RESET;
+ val |= IR_CLK_ENABLE;
+ } else {
+ val &= ~IR_CLK_ENABLE;
+ val |= IR_CLK_RESET;
+ }
+ regmap_write(dev->regmap, IR_CLK, val);
} else {
- val &= ~IR_CLK_ENABLE;
- val |= IR_CLK_RESET;
+ if (on)
+ clk_prepare_enable(dev->clock);
+ else
+ clk_disable_unprepare(dev->clock);
}
- regmap_write(dev->regmap, IR_CLK, val);
}
static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
@@ -207,8 +214,8 @@ static int hix5hd2_ir_probe(struct platform_device *pdev)
priv->regmap = syscon_regmap_lookup_by_phandle(node,
"hisilicon,power-syscon");
if (IS_ERR(priv->regmap)) {
- dev_err(dev, "no power-reg\n");
- return -EINVAL;
+ dev_info(dev, "no power-reg\n");
+ priv->regmap = NULL;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
--
1.9.1
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^ permalink raw reply related
* RE: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
From: Y.T. Tang @ 2016-11-15 7:59 UTC (permalink / raw)
To: devicetree@vger.kernel.org, shawnguo@kernel.org,
robh+dt@kernel.org, mark.rutland@arm.com
Cc: oss@buserror.net, Harninder Rai, Bhaskar U,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1478715118-12848-1-git-send-email-harninder.rai@nxp.com>
Hi Harninder,
Please add compatible string "fsl,ls1043a-ahci" to sata node because they are compatible.
In this way, sata can be enabled.
Regards,
Yuantian
> -----Original Message-----
> From: linux-arm-kernel [mailto:linux-arm-kernel-
> bounces@lists.infradead.org] On Behalf Of Harninder Rai
> Sent: Thursday, November 10, 2016 2:12 AM
> To: devicetree@vger.kernel.org; shawnguo@kernel.org;
> robh+dt@kernel.org; mark.rutland@arm.com
> Cc: oss@buserror.net; Harninder Rai <harninder.rai@nxp.com>; Bhaskar U
> <bhaskar.upadhaya@nxp.com>; linux-arm-kernel@lists.infradead.org
> Subject: [PATCH] arm64: Add DTS support for FSL's LS1012A SoC
>
> Add the device tree support for FSL LS1012A SoC.
> Following levels of DTSI/DTS files have been created for the LS1012A
> SoC family:
>
> - fsl-ls1012a.dtsi:
> DTS-Include file for FSL LS1012A SoC.
>
> - fsl-ls1012a-frdm.dts:
> DTS file for FSL LS1012A FRDM board.
>
> - fsl-ls1012a-qds.dts:
> DTS file for FSL LS1012A QDS board.
>
> - fsl-ls1012a-rdb.dts:
> DTS file for FSL LS1012A RDB board.
>
> Signed-off-by: Harninder Rai <harninder.rai@nxp.com>
> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 3 +
> arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 115 ++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 128 +++++++++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 59 +++++
> arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 248
> +++++++++++++++++++++
> 5 files changed, 553 insertions(+)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile
> b/arch/arm64/boot/dts/freescale/Makefile
> index 6602718..39db645 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,3 +1,6 @@
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb diff --git
> a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> new file mode 100644
> index 0000000..1f2da79
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
> @@ -0,0 +1,115 @@
> +/*
> + * Device Tree file for Freescale LS1012A Freedom Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A Freedom Board";
> + compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
> +
> + sys_mclk: clock-mclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <25000000>;
> + };
> +
> + reg_1p8v: regulator@0 {
> + compatible = "regulator-fixed";
> + regulator-name = "1P8V";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Speaker", "Speaker Ext",
> + "Line", "Line In Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Microphone Jack",
> + "Microphone Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT",
> + "Speaker Ext", "LINE_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + frame-master;
> + bitclock-master;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&codec>;
> + frame-master;
> + bitclock-master;
> + system-clock-frequency = <25000000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + codec: sgtl5000@a {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,sgtl5000";
> + reg = <0xa>;
> + VDDA-supply = <®_1p8v>;
> + VDDIO-supply = <®_1p8v>;
> + clocks = <&sys_mclk>;
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> new file mode 100644
> index 0000000..ca680a7
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
> @@ -0,0 +1,128 @@
> +/*
> + * Device Tree file for Freescale LS1012A QDS Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A QDS Board";
> + compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
> +
> + sys_mclk: clock-mclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <24576000>;
> + };
> +
> + reg_3p3v: regulator@0 {
> + compatible = "regulator-fixed";
> + regulator-name = "3P3V";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + sound {
> + compatible = "simple-audio-card";
> + simple-audio-card,format = "i2s";
> + simple-audio-card,widgets =
> + "Microphone", "Microphone Jack",
> + "Headphone", "Headphone Jack",
> + "Speaker", "Speaker Ext",
> + "Line", "Line In Jack";
> + simple-audio-card,routing =
> + "MIC_IN", "Microphone Jack",
> + "Microphone Jack", "Mic Bias",
> + "LINE_IN", "Line In Jack",
> + "Headphone Jack", "HP_OUT",
> + "Speaker Ext", "LINE_OUT";
> +
> + simple-audio-card,cpu {
> + sound-dai = <&sai2>;
> + frame-master;
> + bitclock-master;
> + };
> +
> + simple-audio-card,codec {
> + sound-dai = <&codec>;
> + frame-master;
> + bitclock-master;
> + system-clock-frequency = <24576000>;
> + };
> + };
> +};
> +
> +&i2c0 {
> + status = "okay";
> +
> + pca9547@77 {
> + compatible = "nxp,pca9547";
> + reg = <0x77>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> +
> + codec: sgtl5000@a {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,sgtl5000";
> + reg = <0xa>;
> + VDDA-supply = <®_3p3v>;
> + VDDIO-supply = <®_3p3v>;
> + clocks = <&sys_mclk>;
> + };
> + };
> + };
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> +
> +&sai2 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> new file mode 100644
> index 0000000..924dad6
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
> @@ -0,0 +1,59 @@
> +/*
> + * Device Tree file for Freescale LS1012A RDB Board.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +/dts-v1/;
> +
> +#include "fsl-ls1012a.dtsi"
> +
> +/ {
> + model = "LS1012A RDB Board";
> + compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; };
> +
> +&i2c0 {
> + status = "okay";
> +};
> +
> +&duart0 {
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> new file mode 100644
> index 0000000..0bf5b64
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
> @@ -0,0 +1,248 @@
> +/*
> + * Device Tree Include file for Freescale Layerscape-1012A family SoC.
> + *
> + * Copyright 2016, Freescale Semiconductor
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPLv2 or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY
> KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE
> WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
> COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
> OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> + compatible = "fsl,ls1012a";
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53";
> + reg = <0x0>;
> + clocks = <&clockgen 1 0>;
> + #cooling-cells = <2>;
> + };
> + };
> +
> + sysclk: sysclk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <100000000>;
> + clock-output-names = "sysclk";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + /* Physical Secure PPI */
> + interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,
> + /* Physical Non-Secure PPI */
> + <1 14 IRQ_TYPE_LEVEL_LOW>,
> + /* Virtual PPI */
> + <1 11 IRQ_TYPE_LEVEL_LOW>,
> + /* Hypervisor PPI */
> + <1 10 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + pmu {
> + compatible = "arm,armv8-pmuv3";
> + interrupts = <0 106 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + gic: interrupt-controller@1400000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + reg = <0x0 0x1401000 0 0x1000>, /* GICD */
> + <0x0 0x1402000 0 0x2000>, /* GICC */
> + <0x0 0x1404000 0 0x2000>, /* GICH */
> + <0x0 0x1406000 0 0x2000>; /* GICV */
> + interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>;
> + };
> +
> + reboot {
> + compatible = "syscon-reboot";
> + regmap = <&dcfg>;
> + offset = <0xb0>;
> + mask = <0x02>;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + clockgen: clocking@1ee1000 {
> + compatible = "fsl,ls1012a-clockgen";
> + reg = <0x0 0x1ee1000 0x0 0x1000>;
> + #clock-cells = <2>;
> + clocks = <&sysclk>;
> + };
> +
> + scfg: scfg@1570000 {
> + compatible = "fsl,ls1012a-scfg", "syscon";
> + reg = <0x0 0x1570000 0x0 0x10000>;
> + big-endian;
> + };
> +
> + dcfg: dcfg@1ee0000 {
> + compatible = "fsl,ls1012a-dcfg",
> + "syscon";
> + reg = <0x0 0x1ee0000 0x0 0x10000>;
> + big-endian;
> + };
> +
> + i2c0: i2c@2180000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2180000 0x0 0x10000>;
> + interrupts = <0 56 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + i2c1: i2c@2190000 {
> + compatible = "fsl,vf610-i2c";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0 0x2190000 0x0 0x10000>;
> + interrupts = <0 57 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + status = "disabled";
> + };
> +
> + duart0: serial@21c0500 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0500 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + duart1: serial@21c0600 {
> + compatible = "fsl,ns16550", "ns16550a";
> + reg = <0x00 0x21c0600 0x0 0x100>;
> + interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clockgen 4 0>;
> + };
> +
> + gpio0: gpio@2300000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2300000 0x0 0x10000>;
> + interrupts = <0 66 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + gpio1: gpio@2310000 {
> + compatible = "fsl,qoriq-gpio";
> + reg = <0x0 0x2310000 0x0 0x10000>;
> + interrupts = <0 67 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + interrupt-controller;
> + #interrupt-cells = <2>;
> + };
> +
> + wdog0: wdog@2ad0000 {
> + compatible = "fsl,ls1012a-wdt",
> + "fsl,imx21-wdt";
> + reg = <0x0 0x2ad0000 0x0 0x10000>;
> + interrupts = <0 83 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + big-endian;
> + };
> +
> + sai1: sai@2b50000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b50000 0x0 0x10000>;
> + interrupts = <0 148 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 47>,
> + <&edma0 1 46>;
> + status = "disabled";
> + };
> +
> + sai2: sai@2b60000 {
> + #sound-dai-cells = <0>;
> + compatible = "fsl,vf610-sai";
> + reg = <0x0 0x2b60000 0x0 0x10000>;
> + interrupts = <0 149 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 3>, <&clockgen 4 3>,
> + <&clockgen 4 3>, <&clockgen 4 3>;
> + clock-names = "bus", "mclk1", "mclk2", "mclk3";
> + dma-names = "tx", "rx";
> + dmas = <&edma0 1 45>,
> + <&edma0 1 44>;
> + status = "disabled";
> + };
> +
> + edma0: edma@2c00000 {
> + #dma-cells = <2>;
> + compatible = "fsl,vf610-edma";
> + reg = <0x0 0x2c00000 0x0 0x10000>,
> + <0x0 0x2c10000 0x0 0x10000>,
> + <0x0 0x2c20000 0x0 0x10000>;
> + interrupts = <0 103 IRQ_TYPE_LEVEL_LOW>,
> + <0 103 IRQ_TYPE_LEVEL_LOW>;
> + interrupt-names = "edma-tx", "edma-err";
> + dma-channels = <32>;
> + big-endian;
> + clock-names = "dmamux0", "dmamux1";
> + clocks = <&clockgen 4 3>,
> + <&clockgen 4 3>;
> + };
> +
> + sata: sata@3200000 {
> + compatible = "fsl,ls1012a-ahci";
> + reg = <0x0 0x3200000 0x0 0x10000>;
> + interrupts = <0 69 IRQ_TYPE_LEVEL_LOW>;
> + clocks = <&clockgen 4 0>;
> + };
> + };
> +};
> --
> 2.7.4
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> linux-arm-kernel@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v4 1/3] bus: simple-pm: add support to pm clocks
From: Geert Uytterhoeven @ 2016-11-15 8:23 UTC (permalink / raw)
To: Bjorn Helgaas, Srinivas Kandagatla
Cc: svarbanov-NEYub+7Iv8PQT0dZR+AlfA, linux-pci, Bjorn Helgaas,
Rob Herring,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Geert Uytterhoeven, Kevin Hilman, Simon Horman, Linux PM list
In-Reply-To: <20161114221447.GH9868-1RhO1Y9PlrlHTL0Zs8A6p5iNqAH0jzoTYJqu5kTmcBRl57MIdRCFDg@public.gmane.org>
+cc linux-pm
On Mon, Nov 14, 2016 at 11:14 PM, Bjorn Helgaas <helgaas-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> [+cc Geert, Kevin, Simon]
>
> On Mon, Nov 14, 2016 at 11:15:53AM +0000, Srinivas Kandagatla wrote:
>> This patch adds support to pm clocks via device tree, so that the clocks
>> can be turned on and off during runtime pm. This patch is required for
>> Qualcomm msm8996 pcie controller which sits on a bus with its own
>> power-domain and clocks.
>>
>> Without this patch the clock associated with the bus are never turned on.
>>
>> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> I don't see a formal maintainer for drivers/bus/simple-pm-bus.c, but I'd
> like an ack or at least a review from Geert or Simon.
Thanks for letting me know!
>> ---
>> drivers/bus/simple-pm-bus.c | 13 ++++++++++++-
>> 1 file changed, 12 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/bus/simple-pm-bus.c b/drivers/bus/simple-pm-bus.c
>> index c5eb46c..63b7e8c 100644
>> --- a/drivers/bus/simple-pm-bus.c
>> +++ b/drivers/bus/simple-pm-bus.c
>> @@ -11,6 +11,7 @@
>> #include <linux/module.h>
>> #include <linux/of_platform.h>
>> #include <linux/platform_device.h>
>> +#include <linux/pm_clock.h>
>> #include <linux/pm_runtime.h>
>>
>>
>> @@ -22,17 +23,26 @@ static int simple_pm_bus_probe(struct platform_device *pdev)
>>
>> pm_runtime_enable(&pdev->dev);
>>
>> - if (np)
>> + if (np) {
>> + of_pm_clk_add_clks(&pdev->dev);
This should work out-of-the-box (that's the actual purpose of this driver),
if the platform code that registers your PM Domain would take care
of registering the clocks needed for PM management of the bus.
Adding of_pm_clk_add_clks() here will start managing all clocks of the bus,
which may not be wanted on all platforms.
>> of_platform_populate(np, NULL, NULL, &pdev->dev);
>> + }
>>
>> return 0;
>> }
>>
>> +static const struct dev_pm_ops simple_pm_bus_pm_ops = {
>> + SET_RUNTIME_PM_OPS(pm_clk_suspend,
>> + pm_clk_resume, NULL)
>> +};
>> +
>> static int simple_pm_bus_remove(struct platform_device *pdev)
>> {
>> dev_dbg(&pdev->dev, "%s\n", __func__);
>>
>> pm_runtime_disable(&pdev->dev);
>> + pm_clk_destroy(&pdev->dev);
>> +
>> return 0;
>> }
>>
>> @@ -48,6 +58,7 @@ static struct platform_driver simple_pm_bus_driver = {
>> .driver = {
>> .name = "simple-pm-bus",
>> .of_match_table = simple_pm_bus_of_match,
>> + .pm = &simple_pm_bus_pm_ops,
>> },
>> };
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
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