* Re: [PATCH v3 1/3] dt-bindings: firmware: scm: Add MSM8996 DT bindings
From: Stephen Boyd @ 2016-11-17 23:12 UTC (permalink / raw)
To: Sarangdhar Joshi
Cc: Andy Gross, David Brown, Rob Herring, Mark Rutland,
Catalin Marinas, Will Deacon, linux-arm-msm, linux-soc,
devicetree, linux-arm-kernel, linux-kernel, Bjorn Andersson,
Jordan Crouse, Trilok Soni
In-Reply-To: <1479259165-1601-2-git-send-email-spjoshi@codeaurora.org>
On 11/15, Sarangdhar Joshi wrote:
> Add SCM DT bindings for Qualcomm's MSM8996 platform.
>
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Sarangdhar Joshi <spjoshi@codeaurora.org>
> ---
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH 0/2] arm64: dts: NS2: Add sdio1, PCI phys
From: Jon Mason @ 2016-11-17 23:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
The second SDIO seems to have been forgotten to be enabled in the
Northstar2 SVK dts. Also, the PCI PHY entries are missing from the PCI
bus device tree entries.
Jon Mason (2):
arm64: dts: NS2: enable sdio1
arm64: dts: NS2: Add PCI PHYs
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 4 ++++
arch/arm64/boot/dts/broadcom/ns2.dtsi | 6 ++++++
2 files changed, 10 insertions(+)
--
2.7.4
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^ permalink raw reply
* [PATCH 1/2] arm64: dts: NS2: enable sdio1
From: Jon Mason @ 2016-11-17 23:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
bcm-kernel-feedback-list-dY08KVG/lbpWk0Htik3J/w,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479425103-2119-1-git-send-email-jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
Enable sdio1 in the Northstar2 SVK device tree file
Signed-off-by: Jon Mason <jon.mason-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
---
arch/arm64/boot/dts/broadcom/ns2-svk.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2-svk.dts b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
index 07c69a3e..de8d379 100644
--- a/arch/arm64/boot/dts/broadcom/ns2-svk.dts
+++ b/arch/arm64/boot/dts/broadcom/ns2-svk.dts
@@ -161,6 +161,10 @@
status = "ok";
};
+&sdio1 {
+ status = "ok";
+};
+
&nand {
nandcs@0 {
compatible = "brcm,nandcs";
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 2/2] arm64: dts: NS2: Add PCI PHYs
From: Jon Mason @ 2016-11-17 23:25 UTC (permalink / raw)
To: Rob Herring, Mark Rutland, Florian Fainelli
Cc: devicetree, bcm-kernel-feedback-list, linux-arm-kernel,
linux-kernel
In-Reply-To: <1479425103-2119-1-git-send-email-jon.mason@broadcom.com>
PCI PHYs are missing from the Northstar2 DT entries for the 2 PCI buses.
Add them so that PCI devices can be discovered.
Signed-off-by: Jon Mason <jon.mason@broadcom.com>
---
arch/arm64/boot/dts/broadcom/ns2.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/ns2.dtsi b/arch/arm64/boot/dts/broadcom/ns2.dtsi
index e4cd868..4fcdeca 100644
--- a/arch/arm64/boot/dts/broadcom/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/ns2.dtsi
@@ -133,6 +133,9 @@
status = "disabled";
+ phys = <&pci_phy0>;
+ phy-names = "pcie-phy";
+
msi-parent = <&msi0>;
msi0: msi@20020000 {
compatible = "brcm,iproc-msi";
@@ -171,6 +174,9 @@
status = "disabled";
+ phys = <&pci_phy1>;
+ phy-names = "pcie-phy";
+
msi-parent = <&msi4>;
msi4: msi@50020000 {
compatible = "brcm,iproc-msi";
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v2 3/3] hwmon: ltc2990: support all measurement modes
From: Tom Levens @ 2016-11-17 23:25 UTC (permalink / raw)
To: Guenter Roeck
Cc: Mike Looijmans, jdelvare@suse.com, robh+dt@kernel.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org,
linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <20161117215454.GA23571@roeck-us.net>
On 17 Nov 2016, at 22:54, Guenter Roeck <linux@roeck-us.net> wrote:
> On Thu, Nov 17, 2016 at 08:52:12PM +0100, Mike Looijmans wrote:
>> On 17-11-2016 19:56, Guenter Roeck wrote:
>>> On Thu, Nov 17, 2016 at 06:40:17PM +0100, Mike Looijmans wrote:
>>>> On 17-11-16 17:56, Guenter Roeck wrote:
>>>>> On 11/17/2016 04:10 AM, Tom Levens wrote:
>>>>>> Updated version of the ltc2990 driver which supports all measurement
>>>>>> modes available in the chip. The mode can be set through a devicetree
>>>>>> attribute.
>>>>>
>>> [ ... ]
>>>
>>>>>>
>>>>>> static int ltc2990_i2c_probe(struct i2c_client *i2c,
>>>>>> const struct i2c_device_id *id)
>>>>>> {
>>>>>> int ret;
>>>>>> struct device *hwmon_dev;
>>>>>> + struct ltc2990_data *data;
>>>>>> + struct device_node *of_node = i2c->dev.of_node;
>>>>>>
>>>>>> if (!i2c_check_functionality(i2c->adapter,
>>>>>> I2C_FUNC_SMBUS_BYTE_DATA |
>>>>>> I2C_FUNC_SMBUS_WORD_DATA))
>>>>>> return -ENODEV;
>>>>>>
>>>>>> - /* Setup continuous mode, current monitor */
>>>>>> + data = devm_kzalloc(&i2c->dev, sizeof(struct ltc2990_data),
>>>>>> GFP_KERNEL);
>>>>>> + if (unlikely(!data))
>>>>>> + return -ENOMEM;
>>>>>> + data->i2c = i2c;
>>>>>> +
>>>>>> + if (!of_node || of_property_read_u32(of_node, "lltc,mode",
>>>>>> &data->mode))
>>>>>> + data->mode = LTC2990_CONTROL_MODE_DEFAULT;
>>>>>
>>>>> Iam arguing with myself if we should still do this or if we should read
>>>>> the mode
>>>>> from the chip instead if it isn't provided (after all, it may have been
>>>>> initialized
>>>>> by the BIOS/ROMMON).
>>>>
>>>> I think the mode should be explicitly set, without default. There's no way
>>>> to tell whether the BIOS or bootloader has really set it up or whether the
>>>> chip is just reporting whatever it happened to default to. And given the
>>>> chip's function, it's unlikely a bootloader would want to initialize it.
>>>>
>>> Unlikely but possible. Even if we all agree that the chip should be configured
>>> by the driver, I don't like imposing that view on everyone else.
>>>
>>>> My advice would be to make it a required property. If not set, display an
>>>> error and bail out.
>>>>
>>> It is not that easy, unfortunately. It also has to work on a non-devicetree
>>> system. I would not object to making the property mandatory, but we would
>>> still need to provide non-DT support.
>>>
>>> My "use case" for taking the current mode from the chip if not specified
>>> is that it would enable me to run a module test with all modes. I consider
>>> this extremely valuable.
>>
>> Good point.
>>
>> The chip defaults to measuring internal temperature only, and the mode
>> defaults to "0".
>>
>> Choosing a mode that doesn't match the actual circuitry could be bad for the
>> chip or the board (though unlikely, it'll probably just be useless) since it
>> will actively drive some of the inputs in the temperature modes (which is
>> default for V3/V4 pins).
>>
>> Instead of failing, one could choose to set the default mode to "7", which
>> just measures the 4 voltages, which would be a harmless mode in all cases.
>>
>> As a way to let a bootloader set things up, I think it would be a good check
>> to see if CONTROL register bits 4:3 are set. If "00", the chip is not
>> acquiring data at all, and probably needs configuration still. In that case,
>> the mode must be provided by the devicetree (or the default "7").
>> If bits 4:3 are "11", it has already been set up to measure its inputs, and
>> it's okay to continue doing just that and use the current value of 2:0
>> register as default mode (if the devicetree didn't specify any mode at all).
>>
>
> At first glance, agreed, though by default b[3:4] are 00, and only the
> internal temperature is measured. Actually, the 5 mode bits are all
> relevant to determine what is measured. Maybe it would be better to take
> all 5 bits into account instead of blindly setting b[34]:=11 and a specific
> setting of b[0:2]. Sure, that would make the mode table a bit larger,
> but then ltc2990_attrs_ena[] could be made an u16 array, and a table size
> of 64 bytes would not be that bad.
I would tend to agree that it should be possible to configure all 5 mode
bits through the devicetree. What I would propose is as follows.
If a devicetree node exists, the mode parameter(s?) are required and the
chip is initialised.
If a devicetree node doesn't exist, it is assumed that the chip has
already been configured (by the BIOS, etc). The mode is read from the
chip to set the visibility of the sysfs attributes. In the worst case, where the
chip has not been configured by another source, it would only be possible
to measure the internal temperature -- but I think this is an acceptable
limitation.
The only case that this does not cover is if the device tree node
exists but the chip is expected to be configured by some other source.
Maybe I am wrong, but I would not expect this to be a terribly common
situation.
What do you think?
Cheers,
Tom
^ permalink raw reply
* [PATCH] of: Fix issue where code would fall through to error case.
From: Moritz Fischer @ 2016-11-17 23:25 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA
Cc: pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w,
moritz-62aBmqa6xEOcmJEhUYGoYg, devicetree-u79uwXL29TY76Z2rM5mHXA,
Moritz Fischer
No longer fall through into the error case that prints out
an error if no error (err = 0) occurred.
Fixes d9181b20a83(of: Add back an error message, restructured)
Signed-off-by: Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
---
drivers/of/resolver.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
index 783bd09..785076d 100644
--- a/drivers/of/resolver.c
+++ b/drivers/of/resolver.c
@@ -358,9 +358,13 @@ int of_resolve_phandles(struct device_node *overlay)
err = update_usages_of_a_phandle_reference(overlay, prop, phandle);
if (err)
- break;
+ goto err_out;
}
+ of_node_put(tree_symbols);
+
+ return 0;
+
err_out:
pr_err("overlay phandle fixup failed: %d\n", err);
out:
--
2.7.4
--
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^ permalink raw reply related
* Re: [PATCH v2 3/3] hwmon: ltc2990: support all measurement modes
From: Guenter Roeck @ 2016-11-17 23:40 UTC (permalink / raw)
To: Tom Levens
Cc: Mike Looijmans, jdelvare@suse.com, robh+dt@kernel.org,
mark.rutland@arm.com, linux-kernel@vger.kernel.org,
linux-hwmon@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <09DCF2E6-3F08-4F0E-837B-55F591008AAB@cern.ch>
On Thu, Nov 17, 2016 at 11:25:30PM +0000, Tom Levens wrote:
> On 17 Nov 2016, at 22:54, Guenter Roeck <linux@roeck-us.net> wrote:
> > On Thu, Nov 17, 2016 at 08:52:12PM +0100, Mike Looijmans wrote:
> >> On 17-11-2016 19:56, Guenter Roeck wrote:
> >>> On Thu, Nov 17, 2016 at 06:40:17PM +0100, Mike Looijmans wrote:
> >>>> On 17-11-16 17:56, Guenter Roeck wrote:
> >>>>> On 11/17/2016 04:10 AM, Tom Levens wrote:
> >>>>>> Updated version of the ltc2990 driver which supports all measurement
> >>>>>> modes available in the chip. The mode can be set through a devicetree
> >>>>>> attribute.
> >>>>>
> >>> [ ... ]
> >>>
> >>>>>>
> >>>>>> static int ltc2990_i2c_probe(struct i2c_client *i2c,
> >>>>>> const struct i2c_device_id *id)
> >>>>>> {
> >>>>>> int ret;
> >>>>>> struct device *hwmon_dev;
> >>>>>> + struct ltc2990_data *data;
> >>>>>> + struct device_node *of_node = i2c->dev.of_node;
> >>>>>>
> >>>>>> if (!i2c_check_functionality(i2c->adapter,
> >>>>>> I2C_FUNC_SMBUS_BYTE_DATA |
> >>>>>> I2C_FUNC_SMBUS_WORD_DATA))
> >>>>>> return -ENODEV;
> >>>>>>
> >>>>>> - /* Setup continuous mode, current monitor */
> >>>>>> + data = devm_kzalloc(&i2c->dev, sizeof(struct ltc2990_data),
> >>>>>> GFP_KERNEL);
> >>>>>> + if (unlikely(!data))
> >>>>>> + return -ENOMEM;
> >>>>>> + data->i2c = i2c;
> >>>>>> +
> >>>>>> + if (!of_node || of_property_read_u32(of_node, "lltc,mode",
> >>>>>> &data->mode))
> >>>>>> + data->mode = LTC2990_CONTROL_MODE_DEFAULT;
> >>>>>
> >>>>> Iam arguing with myself if we should still do this or if we should read
> >>>>> the mode
> >>>>> from the chip instead if it isn't provided (after all, it may have been
> >>>>> initialized
> >>>>> by the BIOS/ROMMON).
> >>>>
> >>>> I think the mode should be explicitly set, without default. There's no way
> >>>> to tell whether the BIOS or bootloader has really set it up or whether the
> >>>> chip is just reporting whatever it happened to default to. And given the
> >>>> chip's function, it's unlikely a bootloader would want to initialize it.
> >>>>
> >>> Unlikely but possible. Even if we all agree that the chip should be configured
> >>> by the driver, I don't like imposing that view on everyone else.
> >>>
> >>>> My advice would be to make it a required property. If not set, display an
> >>>> error and bail out.
> >>>>
> >>> It is not that easy, unfortunately. It also has to work on a non-devicetree
> >>> system. I would not object to making the property mandatory, but we would
> >>> still need to provide non-DT support.
> >>>
> >>> My "use case" for taking the current mode from the chip if not specified
> >>> is that it would enable me to run a module test with all modes. I consider
> >>> this extremely valuable.
> >>
> >> Good point.
> >>
> >> The chip defaults to measuring internal temperature only, and the mode
> >> defaults to "0".
> >>
> >> Choosing a mode that doesn't match the actual circuitry could be bad for the
> >> chip or the board (though unlikely, it'll probably just be useless) since it
> >> will actively drive some of the inputs in the temperature modes (which is
> >> default for V3/V4 pins).
> >>
> >> Instead of failing, one could choose to set the default mode to "7", which
> >> just measures the 4 voltages, which would be a harmless mode in all cases.
> >>
> >> As a way to let a bootloader set things up, I think it would be a good check
> >> to see if CONTROL register bits 4:3 are set. If "00", the chip is not
> >> acquiring data at all, and probably needs configuration still. In that case,
> >> the mode must be provided by the devicetree (or the default "7").
> >> If bits 4:3 are "11", it has already been set up to measure its inputs, and
> >> it's okay to continue doing just that and use the current value of 2:0
> >> register as default mode (if the devicetree didn't specify any mode at all).
> >>
> >
> > At first glance, agreed, though by default b[3:4] are 00, and only the
> > internal temperature is measured. Actually, the 5 mode bits are all
> > relevant to determine what is measured. Maybe it would be better to take
> > all 5 bits into account instead of blindly setting b[34]:=11 and a specific
> > setting of b[0:2]. Sure, that would make the mode table a bit larger,
> > but then ltc2990_attrs_ena[] could be made an u16 array, and a table size
> > of 64 bytes would not be that bad.
>
> I would tend to agree that it should be possible to configure all 5 mode
> bits through the devicetree. What I would propose is as follows.
>
> If a devicetree node exists, the mode parameter(s?) are required and the
> chip is initialised.
>
> If a devicetree node doesn't exist, it is assumed that the chip has
> already been configured (by the BIOS, etc). The mode is read from the
> chip to set the visibility of the sysfs attributes. In the worst case, where the
> chip has not been configured by another source, it would only be possible
> to measure the internal temperature -- but I think this is an acceptable
> limitation.
>
SGTM.
> The only case that this does not cover is if the device tree node
> exists but the chip is expected to be configured by some other source.
> Maybe I am wrong, but I would not expect this to be a terribly common
> situation.
>
> What do you think?
>
I would not bother about this case. Just make the mode property mandatory.
Thanks,
Guenter
^ permalink raw reply
* Re: [PATCH] of: Fix issue where code would fall through to error case.
From: Frank Rowand @ 2016-11-17 23:40 UTC (permalink / raw)
To: Moritz Fischer, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w,
moritz-62aBmqa6xEOcmJEhUYGoYg, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479425157-6235-1-git-send-email-moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
On 11/17/16 15:25, Moritz Fischer wrote:
> No longer fall through into the error case that prints out
> an error if no error (err = 0) occurred.
>
> Fixes d9181b20a83(of: Add back an error message, restructured)
> Signed-off-by: Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
> ---
> drivers/of/resolver.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
> index 783bd09..785076d 100644
> --- a/drivers/of/resolver.c
> +++ b/drivers/of/resolver.c
> @@ -358,9 +358,13 @@ int of_resolve_phandles(struct device_node *overlay)
>
> err = update_usages_of_a_phandle_reference(overlay, prop, phandle);
> if (err)
> - break;
> + goto err_out;
> }
>
> + of_node_put(tree_symbols);
> +
> + return 0;
> +
> err_out:
> pr_err("overlay phandle fixup failed: %d\n", err);
> out:
Thanks for catching that.
Rob, please apply.
Reviewed-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
-Frank
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^ permalink raw reply
* Re: [RFC PATCH] mfd: dt: Add Aspeed LPC binding
From: Andrew Jeffery @ 2016-11-17 23:41 UTC (permalink / raw)
To: Linus Walleij
Cc: Arnd Bergmann, Lee Jones, Benjamin Herrenschmidt, Joel Stanley,
Rob Herring, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
In-Reply-To: <CACRpkdazPEbU2gmDyke=GTYtjVp8aeauS+PVkp-zuiVoVz7kbw@mail.gmail.com>
[-- Attachment #1: Type: text/plain, Size: 1413 bytes --]
On Thu, 2016-11-17 at 10:30 +0100, Linus Walleij wrote:
> > On Thu, Nov 17, 2016 at 7:06 AM, Andrew Jeffery <andrew@aj.id.au> wrote:
>
> > +* Device tree bindings for the Aspeed LPC Controller
>
> We are going overboard with the lingo sometimes, to the point that we do not
> understand how terse things become.
Sorry for that, it is a bit terse. Sometimes I struggle to gauge how
much context I should provide.
Joel's reply covers the details of your queries below, but I'll make
sure to add the information to the bindings as well.
>
> LPC = Low Pin Count, right?
> Explain that right here: it is a slow external bus, right?
> > +The Aspeed LPC controller contains registers for a variety of functions. Not
> > +all registers for a function are contiguous, and some registers are referenced
> > +by functions outside the LPC controller.
> > +
> > +Note that this is separate from the H8S/2168 compatible register set occupying
> > +the start of the LPC controller address space.
> > +
> > +Some significant functions in the LPC controller:
> > +
> > +* LPC Host Controller
> > +* Host Interface Controller
>
> Host interface to what?
>
> > +* iBT Controller
>
> What is iBT?
>
> > +* SuperIO Scratch registers
>
> Again more context please.
>
> With standards documents, either explain everything or provide
> pointers for the information.
ACK!
Andrew
[-- Attachment #2: This is a digitally signed message part --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* Re: [PATCH] of: Fix issue where code would fall through to error case.
From: Frank Rowand @ 2016-11-18 0:02 UTC (permalink / raw)
To: Moritz Fischer, linux-kernel, robh+dt
Cc: pantelis.antoniou, moritz, devicetree
In-Reply-To: <582E3FFC.80305@gmail.com>
On 11/17/16 15:40, Frank Rowand wrote:
> On 11/17/16 15:25, Moritz Fischer wrote:
>> No longer fall through into the error case that prints out
>> an error if no error (err = 0) occurred.
>>
>> Fixes d9181b20a83(of: Add back an error message, restructured)
>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>> ---
>> drivers/of/resolver.c | 6 +++++-
>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
>> index 783bd09..785076d 100644
>> --- a/drivers/of/resolver.c
>> +++ b/drivers/of/resolver.c
>> @@ -358,9 +358,13 @@ int of_resolve_phandles(struct device_node *overlay)
>>
>> err = update_usages_of_a_phandle_reference(overlay, prop, phandle);
>> if (err)
>> - break;
>> + goto err_out;
>> }
>>
>> + of_node_put(tree_symbols);
>> +
>> + return 0;
>> +
>> err_out:
>> pr_err("overlay phandle fixup failed: %d\n", err);
>> out:
>
> Thanks for catching that.
>
> Rob, please apply.
>
> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
>
> -Frank
On second thought, isn't the common pattern when clean up is needed for
both the no-error path and the error path something like:
out:
of_node_put(tree_symbols);
return err;
err_out:
pr_err("overlay phandle fixup failed: %d\n", err);
goto out;
}
I don't have a strong opinion, whatever Rob wants to take is fine with me.
-Frank
^ permalink raw reply
* Re: [PATCH] of: Fix issue where code would fall through to error case.
From: Moritz Fischer @ 2016-11-18 0:10 UTC (permalink / raw)
To: Frank Rowand
Cc: Moritz Fischer, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w,
moritz-62aBmqa6xEOcmJEhUYGoYg, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <582E452E.3080909-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Nov 17, 2016 at 4:02 PM, Frank Rowand <frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 11/17/16 15:40, Frank Rowand wrote:
>> On 11/17/16 15:25, Moritz Fischer wrote:
>>> No longer fall through into the error case that prints out
>>> an error if no error (err = 0) occurred.
>>>
>>> Fixes d9181b20a83(of: Add back an error message, restructured)
>>> Signed-off-by: Moritz Fischer <moritz.fischer-+aYTwkv1SeIAvxtiuMwx3w@public.gmane.org>
>>> ---
>>> drivers/of/resolver.c | 6 +++++-
>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
>>> index 783bd09..785076d 100644
>>> --- a/drivers/of/resolver.c
>>> +++ b/drivers/of/resolver.c
>>> @@ -358,9 +358,13 @@ int of_resolve_phandles(struct device_node *overlay)
>>>
>>> err = update_usages_of_a_phandle_reference(overlay, prop, phandle);
>>> if (err)
>>> - break;
>>> + goto err_out;
>>> }
>>>
>>> + of_node_put(tree_symbols);
>>> +
>>> + return 0;
>>> +
>>> err_out:
>>> pr_err("overlay phandle fixup failed: %d\n", err);
>>> out:
>>
>> Thanks for catching that.
>>
>> Rob, please apply.
>>
>> Reviewed-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
>>
>> -Frank
>
> On second thought, isn't the common pattern when clean up is needed for
> both the no-error path and the error path something like:
>
>
> out:
> of_node_put(tree_symbols);
> return err;
>
> err_out:
> pr_err("overlay phandle fixup failed: %d\n", err);
> goto out;
> }
>
>
> I don't have a strong opinion, whatever Rob wants to take is fine with me.
Same here. I tried to avoid the jumping back part, but if that's the
common pattern,
I can submit a v2 doing that instead.
Cheers,
Moritz
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^ permalink raw reply
* Re: [PATCH 1/3] ipmi/bt-bmc: change compatible node to 'aspeed,ast2400-ibt-bmc'
From: Olof Johansson @ 2016-11-18 0:33 UTC (permalink / raw)
To: Arnd Bergmann
Cc: minyard-HInyCGIudOg, C?dric Le Goater, Joel Stanley,
openipmi-developer-5NWGOfrQmneRv+LV9MX5uipxlwaOVQ5f, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Benjamin Herrenschmidt, arm
In-Reply-To: <2278270.0oJqDfoDd9@wuerfel>
On Wed, Nov 09, 2016 at 05:09:12PM +0100, Arnd Bergmann wrote:
> On Tuesday, November 8, 2016 12:15:57 PM CET Corey Minyard wrote:
> > On 11/08/2016 09:52 AM, C?dric Le Goater wrote:
> > > O
> > snip
> >
> > >>>> While we're modifying the binding, should we add a compat string for
> > >>>> the ast2500?
> > >>> Well, if the change in this patch is fine for all, may be we can add
> > >>> the ast2500 compat string in a followup patch ?
> > >> Sounds good to me.
> > > OK. So, how do we proceed with this patch ? Who would include it in its
> > > tree ?
> >
> > I don't have anything for 4.9 at the moment. Arnd, if you have
> > something, can
> > you take this? Otherwise I will.
> >
> > And I guess I should add:
> >
> > Acked-by: Corey Minyard <cminyard-Igf4POYTYCDQT0dZR+AlfA@public.gmane.org>
>
> Thanks, I've added it to my todo folder.
>
> Olof, if you do fixes before I do, please pick up this patch with
> Corey's Ack.
Done, applied to fixes.
-Olof
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^ permalink raw reply
* [PATCH V3 2/4] mfd: pv88080: MFD core support
From: Eric Jeong @ 2016-11-18 0:35 UTC (permalink / raw)
To: LINUX-KERNEL, Lee Jones
Cc: Alexandre Courbot, DEVICETREE, LINUX-GPIO, Liam Girdwood,
Linus Walleij, Mark Brown, Mark Rutland, Rob Herring,
Support Opensource
In-Reply-To: <cover.1479429347.git.eric.jeong@diasemi.com>
From: Eric Jeong <eric.jeong.opensource@diasemi.com>
This patch adds supports for PV88080 MFD core device.
It provides communication through the I2C interface.
It contains the following components:
- Regulators
- Configurable GPIOs
Kconfig and Makefile are updated to reflect support for PV88080 PMIC.
Signed-off-by: Eric Jeong <eric.jeong.opensource@diasemi.com>
---
This patch applies against linux-next and next-20161117
Hi,
This patch adds MFD core driver for PV88080 PMIC.
This is done as part of the existing PV88080 regulator driver by expending
the driver for GPIO function support.
Change since PATCH V2
- Make one file insted of usging core and i2c file
- Use devm_ function to be managed resource automatically
- Separated mfd_cell and regmap_irq_chip declaration for clarification.
- Updated Kconfig to use OF and assign yes to I2C
Change since PATCH V1
- Patch separated from PATCH V1
Regards,
Eric Jeong, Dialog Semiconductor Ltd.
drivers/mfd/Kconfig | 12 ++
drivers/mfd/Makefile | 1 +
drivers/mfd/pv88080.c | 331 +++++++++++++++++++++++++++++++++++++++++++
include/linux/mfd/pv88080.h | 222 +++++++++++++++++++++++++++++
4 files changed, 566 insertions(+)
create mode 100644 drivers/mfd/pv88080.c
create mode 100644 include/linux/mfd/pv88080.h
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 06dc9b0..75abf2d 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -792,6 +792,18 @@ config MFD_PM8921_CORE
Say M here if you want to include support for PM8921 chip as a module.
This will build a module called "pm8921-core".
+config MFD_PV88080
+ tristate "Powerventure Semiconductor PV88080 PMIC Support"
+ select MFD_CORE
+ select REGMAP_I2C
+ select REGMAP_IRQ
+ depends on I2C=y && OF
+ help
+ Say yes here for support for the Powerventure Semiconductor PV88080 PMIC.
+ This includes the I2C driver and core APIs.
+ Additional drivers must be enabled in order to use the functionality
+ of the device.
+
config MFD_QCOM_RPM
tristate "Qualcomm Resource Power Manager (RPM)"
depends on ARCH_QCOM && OF
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index db39377..e9e16c6 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -173,6 +173,7 @@ obj-$(CONFIG_MFD_SI476X_CORE) += si476x-core.o
obj-$(CONFIG_MFD_CS5535) += cs5535-mfd.o
obj-$(CONFIG_MFD_OMAP_USB_HOST) += omap-usb-host.o omap-usb-tll.o
obj-$(CONFIG_MFD_PM8921_CORE) += pm8921-core.o ssbi.o
+obj-$(CONFIG_MFD_PV88080) += pv88080.o
obj-$(CONFIG_MFD_QCOM_RPM) += qcom_rpm.o
obj-$(CONFIG_MFD_SPMI_PMIC) += qcom-spmi-pmic.o
obj-$(CONFIG_TPS65911_COMPARATOR) += tps65911-comparator.o
diff --git a/drivers/mfd/pv88080.c b/drivers/mfd/pv88080.c
new file mode 100644
index 0000000..518b44f
--- /dev/null
+++ b/drivers/mfd/pv88080.c
@@ -0,0 +1,331 @@
+/*
+ * pv88080-i2c.c - I2C access driver for PV88080
+ *
+ * Copyright (C) 2016 Powerventure Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+
+#include <linux/mfd/pv88080.h>
+
+#define PV88080_REG_EVENT_A_OFFSET 0
+#define PV88080_REG_EVENT_B_OFFSET 1
+#define PV88080_REG_EVENT_C_OFFSET 2
+
+static const struct resource regulators_aa_resources[] = {
+ {
+ .name = "VDD_TEMP_FAULT",
+ .start = PV88080_AA_IRQ_VDD_FLT,
+ .end = PV88080_AA_IRQ_OVER_TEMP,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static const struct resource regulators_ba_resources[] = {
+ {
+ .name = "VDD_TEMP_FAULT",
+ .start = PV88080_BA_IRQ_VDD_FLT,
+ .end = PV88080_BA_IRQ_OVER_TEMP,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static const struct mfd_cell pv88080_aa_cells[] = {
+ {
+ .name = "pv88080-regulator",
+ .num_resources = ARRAY_SIZE(regulators_aa_resources),
+ .resources = regulators_aa_resources,
+ .of_compatible = "pvs,pv88080-regulator",
+ },
+ {
+ .name = "pv88080-gpio",
+ .of_compatible = "pvs,pv88080-gpio",
+ },
+};
+
+static const struct mfd_cell pv88080_ba_cells[] = {
+ {
+ .name = "pv88080-regulator",
+ .num_resources = ARRAY_SIZE(regulators_ba_resources),
+ .resources = regulators_ba_resources,
+ .of_compatible = "pvs,pv88080-regulator",
+ },
+ {
+ .name = "pv88080-gpio",
+ .of_compatible = "pvs,pv88080-gpio",
+ },
+};
+
+static const struct regmap_irq pv88080_aa_irqs[] = {
+ /* PV88080 event A register for AA/AB silicon */
+ [PV88080_AA_IRQ_VDD_FLT] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_VDD_FLT,
+ },
+ [PV88080_AA_IRQ_OVER_TEMP] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_OVER_TEMP,
+ },
+ [PV88080_AA_IRQ_SEQ_RDY] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_SEQ_RDY,
+ },
+ /* PV88080 event B register for AA/AB silicon */
+ [PV88080_AA_IRQ_HVBUCK_OV] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_OV,
+ },
+ [PV88080_AA_IRQ_HVBUCK_UV] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_UV,
+ },
+ [PV88080_AA_IRQ_HVBUCK_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_SCP,
+ },
+ [PV88080_AA_IRQ_BUCK1_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK1_SCP,
+ },
+ [PV88080_AA_IRQ_BUCK2_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK2_SCP,
+ },
+ [PV88080_AA_IRQ_BUCK3_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK3_SCP,
+ },
+ /* PV88080 event C register for AA/AB silicon */
+ [PV88080_AA_IRQ_GPIO_FLAG0] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_GPIO_FLAG0,
+ },
+ [PV88080_AA_IRQ_GPIO_FLAG1] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_GPIO_FLAG1,
+ },
+};
+
+static const struct regmap_irq pv88080_ba_irqs[] = {
+ /* PV88080 event A register for BA/BB silicon */
+ [PV88080_BA_IRQ_VDD_FLT] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_VDD_FLT,
+ },
+ [PV88080_BA_IRQ_OVER_TEMP] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_OVER_TEMP,
+ },
+ [PV88080_BA_IRQ_SEQ_RDY] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_SEQ_RDY,
+ },
+ [PV88080_BA_IRQ_EXT_OT] = {
+ .reg_offset = PV88080_REG_EVENT_A_OFFSET,
+ .mask = PV88080_M_EXT_OT,
+ },
+ /* PV88080 event B register for BA/BB silicon */
+ [PV88080_BA_IRQ_HVBUCK_OV] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_OV,
+ },
+ [PV88080_BA_IRQ_HVBUCK_UV] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_UV,
+ },
+ [PV88080_BA_IRQ_HVBUCK_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_HVBUCK_SCP,
+ },
+ [PV88080_BA_IRQ_BUCK1_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK1_SCP,
+ },
+ [PV88080_BA_IRQ_BUCK2_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK2_SCP,
+ },
+ [PV88080_BA_IRQ_BUCK3_SCP] = {
+ .reg_offset = PV88080_REG_EVENT_B_OFFSET,
+ .mask = PV88080_M_BUCK3_SCP,
+ },
+ /* PV88080 event C register for BA/BB silicon */
+ [PV88080_BA_IRQ_GPIO_FLAG0] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_GPIO_FLAG0,
+ },
+ [PV88080_BA_IRQ_GPIO_FLAG1] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_GPIO_FLAG1,
+ },
+ [PV88080_BA_IRQ_BUCK1_DROP_TIMEOUT] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_BUCK1_DROP_TIMEOUT,
+ },
+ [PV88080_BA_IRQ_BUCK2_DROP_TIMEOUT] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_BUCK2_DROP_TIMEOUT,
+ },
+ [PB88080_BA_IRQ_BUCK3_DROP_TIMEOUT] = {
+ .reg_offset = PV88080_REG_EVENT_C_OFFSET,
+ .mask = PV88080_M_BUCk3_DROP_TIMEOUT,
+ },
+};
+
+static const struct regmap_irq_chip pv88080_aa_irq_chip = {
+ .name = "pv88080-irq",
+ .irqs = pv88080_aa_irqs,
+ .num_irqs = ARRAY_SIZE(pv88080_aa_irqs),
+ .num_regs = 3,
+ .status_base = PV88080_REG_EVENT_A,
+ .mask_base = PV88080_REG_MASK_A,
+ .ack_base = PV88080_REG_EVENT_A,
+ .init_ack_masked = true,
+};
+
+static const struct regmap_irq_chip pv88080_ba_irq_chip = {
+ .name = "pv88080-irq",
+ .irqs = pv88080_ba_irqs,
+ .num_irqs = ARRAY_SIZE(pv88080_ba_irqs),
+ .num_regs = 3,
+ .status_base = PV88080_REG_EVENT_A,
+ .mask_base = PV88080_REG_MASK_A,
+ .ack_base = PV88080_REG_EVENT_A,
+ .init_ack_masked = true,
+};
+
+static const struct regmap_config pv88080_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+
+static const struct of_device_id pv88080_of_match_table[] = {
+ { .compatible = "pvs,pv88080", .data = (void *)TYPE_PV88080_AA },
+ { .compatible = "pvs,pv88080-aa", .data = (void *)TYPE_PV88080_AA },
+ { .compatible = "pvs,pv88080-ba", .data = (void *)TYPE_PV88080_BA },
+ { },
+};
+MODULE_DEVICE_TABLE(of, pv88080_of_match_table);
+
+static int pv88080_probe(struct i2c_client *client,
+ const struct i2c_device_id *ids)
+{
+ struct pv88080 *chip;
+ const struct of_device_id *match;
+ const struct regmap_irq_chip *pv88080_irq_chips;
+ const struct mfd_cell *pv88080_mfd_cells;
+ int ret, n_devs;
+
+ chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ if (client->dev.of_node) {
+ match = of_match_node(pv88080_of_match_table,
+ client->dev.of_node);
+ if (!match) {
+ dev_err(&client->dev, "Failed to get of_match_node\n");
+ return -EINVAL;
+ }
+ chip->type = (unsigned long)match->data;
+ } else {
+ chip->type = ids->driver_data;
+ }
+
+ i2c_set_clientdata(client, chip);
+
+ chip->irq = client->irq;
+ chip->dev = &client->dev;
+
+ chip->regmap = devm_regmap_init_i2c(client, &pv88080_regmap_config);
+ if (IS_ERR(chip->regmap)) {
+ dev_err(chip->dev, "Failed to initialize register map\n");
+ return PTR_ERR(chip->regmap);
+ }
+
+ ret = regmap_write(chip->regmap, PV88080_REG_MASK_A, 0xFF);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to mask A reg: %d\n", ret);
+ return ret;
+ }
+ ret = regmap_write(chip->regmap, PV88080_REG_MASK_B, 0xFF);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to mask B reg: %d\n", ret);
+ return ret;
+ }
+ ret = regmap_write(chip->regmap, PV88080_REG_MASK_C, 0xFF);
+ if (ret < 0) {
+ dev_err(chip->dev, "Failed to mask C reg: %d\n", ret);
+ return ret;
+ }
+
+ switch (chip->type) {
+ case TYPE_PV88080_AA:
+ pv88080_irq_chips = &pv88080_aa_irq_chip;
+ pv88080_mfd_cells = pv88080_aa_cells;
+ n_devs = ARRAY_SIZE(pv88080_aa_cells);
+ break;
+ case TYPE_PV88080_BA:
+ pv88080_irq_chips = &pv88080_ba_irq_chip;
+ pv88080_mfd_cells = pv88080_ba_cells;
+ n_devs = ARRAY_SIZE(pv88080_ba_cells);
+ break;
+ }
+
+ ret = devm_regmap_add_irq_chip(chip->dev, chip->regmap,
+ chip->irq, IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ 0, pv88080_irq_chips, &chip->irq_data);
+ if (ret) {
+ dev_err(chip->dev, "Failed to add IRQ %d: %d\n",
+ chip->irq, ret);
+ return ret;
+ }
+
+ ret = devm_mfd_add_devices(chip->dev, PLATFORM_DEVID_NONE,
+ pv88080_mfd_cells, n_devs,
+ NULL, 0, NULL);
+ if (ret) {
+ dev_err(chip->dev, "Failed to add MFD devices\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct i2c_device_id pv88080_id_table[] = {
+ { "pv88080", TYPE_PV88080_AA },
+ { "pv88080-aa", TYPE_PV88080_AA },
+ { "pv88080-ba", TYPE_PV88080_BA },
+ { },
+};
+MODULE_DEVICE_TABLE(i2c, pv88080_id_table);
+
+static struct i2c_driver pv88080_driver = {
+ .driver = {
+ .name = "pv88080",
+ .of_match_table = of_match_ptr(pv88080_of_match_table),
+ },
+ .probe = pv88080_probe,
+ .id_table = pv88080_id_table,
+};
+module_i2c_driver(pv88080_driver);
+
+MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
+MODULE_DESCRIPTION("MFD Driver for Powerventure PV88080");
+MODULE_LICENSE("GPL");
+
diff --git a/include/linux/mfd/pv88080.h b/include/linux/mfd/pv88080.h
new file mode 100644
index 0000000..76d6656
--- /dev/null
+++ b/include/linux/mfd/pv88080.h
@@ -0,0 +1,222 @@
+/*
+ * pv88080.h - Declarations for PV88080.
+ * Copyright (C) 2016 Powerventure Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __PV88080_H__
+#define __PV88080_H__
+
+#include <linux/regulator/machine.h>
+#include <linux/device.h>
+#include <linux/regmap.h>
+
+/* System Control and Event Registers */
+#define PV88080_REG_STATUS_A 0x01
+#define PV88080_REG_EVENT_A 0x04
+#define PV88080_REG_MASK_A 0x09
+#define PV88080_REG_MASK_B 0x0A
+#define PV88080_REG_MASK_C 0x0B
+
+/* GPIO Registers - rev. AA */
+#define PV88080AA_REG_GPIO_INPUT 0x18
+#define PV88080AA_REG_GPIO_OUTPUT 0x19
+#define PV88080AA_REG_GPIO_GPIO0 0x1A
+
+/* Regulator Registers - rev. AA */
+#define PV88080AA_REG_HVBUCK_CONF1 0x2D
+#define PV88080AA_REG_HVBUCK_CONF2 0x2E
+#define PV88080AA_REG_BUCK1_CONF0 0x27
+#define PV88080AA_REG_BUCK1_CONF1 0x28
+#define PV88080AA_REG_BUCK1_CONF2 0x59
+#define PV88080AA_REG_BUCK1_CONF5 0x5C
+#define PV88080AA_REG_BUCK2_CONF0 0x29
+#define PV88080AA_REG_BUCK2_CONF1 0x2A
+#define PV88080AA_REG_BUCK2_CONF2 0x61
+#define PV88080AA_REG_BUCK2_CONF5 0x64
+#define PV88080AA_REG_BUCK3_CONF0 0x2B
+#define PV88080AA_REG_BUCK3_CONF1 0x2C
+#define PV88080AA_REG_BUCK3_CONF2 0x69
+#define PV88080AA_REG_BUCK3_CONF5 0x6C
+
+/* GPIO Registers - rev. BA */
+#define PV88080BA_REG_GPIO_INPUT 0x17
+#define PV88080BA_REG_GPIO_OUTPUT 0x18
+#define PV88080BA_REG_GPIO_GPIO0 0x19
+
+/* Regulator Registers - rev. BA */
+#define PV88080BA_REG_HVBUCK_CONF1 0x33
+#define PV88080BA_REG_HVBUCK_CONF2 0x34
+#define PV88080BA_REG_BUCK1_CONF0 0x2A
+#define PV88080BA_REG_BUCK1_CONF1 0x2C
+#define PV88080BA_REG_BUCK1_CONF2 0x5A
+#define PV88080BA_REG_BUCK1_CONF5 0x5D
+#define PV88080BA_REG_BUCK2_CONF0 0x2D
+#define PV88080BA_REG_BUCK2_CONF1 0x2F
+#define PV88080BA_REG_BUCK2_CONF2 0x63
+#define PV88080BA_REG_BUCK2_CONF5 0x66
+#define PV88080BA_REG_BUCK3_CONF0 0x30
+#define PV88080BA_REG_BUCK3_CONF1 0x32
+#define PV88080BA_REG_BUCK3_CONF2 0x6C
+#define PV88080BA_REG_BUCK3_CONF5 0x6F
+
+/* PV88080_REG_EVENT_A (addr=0x04) */
+#define PV88080_E_VDD_FLT 0x01
+#define PV88080_E_OVER_TEMP 0x02
+#define PV88080_E_SEQ_RDY 0x04
+#define PV88080_E_EXT_OT 0x08
+
+/* PV88080_REG_MASK_A (addr=0x09) */
+#define PV88080_M_VDD_FLT 0x01
+#define PV88080_M_OVER_TEMP 0x02
+#define PV88080_M_SEQ_RDY 0x04
+#define PV88080_M_EXT_OT 0x08
+
+/* PV88080_REG_EVENT_B (addr=0x05) */
+#define PV88080_E_HVBUCK_OV 0x01
+#define PV88080_E_HVBUCK_UV 0x02
+#define PV88080_E_HVBUCK_SCP 0x04
+#define PV88080_E_BUCK1_SCP 0x08
+#define PV88080_E_BUCK2_SCP 0x10
+#define PV88080_E_BUCK3_SCP 0x20
+
+/* PV88080_REG_MASK_B (addr=0x0A) */
+#define PV88080_M_HVBUCK_OV 0x01
+#define PV88080_M_HVBUCK_UV 0x02
+#define PV88080_M_HVBUCK_SCP 0x04
+#define PV88080_M_BUCK1_SCP 0x08
+#define PV88080_M_BUCK2_SCP 0x10
+#define PV88080_M_BUCK3_SCP 0x20
+
+/* PV88080_REG_EVENT_C (addr=0x06) */
+#define PV88080_E_GPIO_FLAG0 0x01
+#define PV88080_E_GPIO_FLAG1 0x02
+#define PV88080_E_BUCK1_DROP_TIMEOUT 0x08
+#define PV88080_E_BUCK2_DROP_TIMEOUT 0x10
+#define PV88080_E_BUCk3_DROP_TIMEOUT 0x20
+
+/* PV88080_REG_MASK_C (addr=0x0B) */
+#define PV88080_M_GPIO_FLAG0 0x01
+#define PV88080_M_GPIO_FLAG1 0x02
+#define PV88080_M_BUCK1_DROP_TIMEOUT 0x08
+#define PV88080_M_BUCK2_DROP_TIMEOUT 0x10
+#define PV88080_M_BUCk3_DROP_TIMEOUT 0x20
+
+/* PV88080xx_REG_GPIO_GPIO0 (addr=0x1A|0x19) */
+#define PV88080_GPIO_DIRECTION_MASK 0x01
+#define PV88080_GPIO_SINGLE_ENDED_MASK 0x02
+
+/* PV88080_REG_BUCK1_CONF0 (addr=0x27|0x2A) */
+#define PV88080_BUCK1_EN 0x80
+#define PV88080_VBUCK1_MASK 0x7F
+
+/* PV88080_REG_BUCK2_CONF0 (addr=0x29|0x2D) */
+#define PV88080_BUCK2_EN 0x80
+#define PV88080_VBUCK2_MASK 0x7F
+
+/* PV88080_REG_BUCK3_CONF0 (addr=0x2B|0x30) */
+#define PV88080_BUCK3_EN 0x80
+#define PV88080_VBUCK3_MASK 0x7F
+
+/* PV88080_REG_BUCK1_CONF1 (addr=0x28|0x2C) */
+#define PV88080_BUCK1_ILIM_SHIFT 2
+#define PV88080_BUCK1_ILIM_MASK 0x0C
+#define PV88080_BUCK1_MODE_MASK 0x03
+
+/* PV88080_REG_BUCK2_CONF1 (addr=0x2A|0x2F) */
+#define PV88080_BUCK2_ILIM_SHIFT 2
+#define PV88080_BUCK2_ILIM_MASK 0x0C
+#define PV88080_BUCK2_MODE_MASK 0x03
+
+/* PV88080_REG_BUCK3_CONF1 (addr=0x2C|0x32) */
+#define PV88080_BUCK3_ILIM_SHIFT 2
+#define PV88080_BUCK3_ILIM_MASK 0x0C
+#define PV88080_BUCK3_MODE_MASK 0x03
+
+#define PV88080_BUCK_MODE_SLEEP 0x00
+#define PV88080_BUCK_MODE_AUTO 0x01
+#define PV88080_BUCK_MODE_SYNC 0x02
+
+/* PV88080_REG_HVBUCK_CONF1 (addr=0x2D|0x33) */
+#define PV88080_VHVBUCK_MASK 0xFF
+
+/* PV88080_REG_HVBUCK_CONF1 (addr=0x2E|0x34) */
+#define PV88080_HVBUCK_EN 0x01
+
+/* PV88080_REG_BUCK2_CONF2 (addr=0x61|0x63) */
+/* PV88080_REG_BUCK3_CONF2 (addr=0x69|0x6C) */
+#define PV88080_BUCK_VDAC_RANGE_SHIFT 7
+#define PV88080_BUCK_VDAC_RANGE_MASK 0x01
+
+#define PV88080_BUCK_VDAC_RANGE_1 0x00
+#define PV88080_BUCK_VDAC_RANGE_2 0x01
+
+/* PV88080_REG_BUCK2_CONF5 (addr=0x64|0x66) */
+/* PV88080_REG_BUCK3_CONF5 (addr=0x6C|0x6F) */
+#define PV88080_BUCK_VRANGE_GAIN_SHIFT 0
+#define PV88080_BUCK_VRANGE_GAIN_MASK 0x01
+
+#define PV88080_BUCK_VRANGE_GAIN_1 0x00
+#define PV88080_BUCK_VRANGE_GAIN_2 0x01
+
+#define PV88080_MAX_REGULATORS 4
+
+enum pv88080_types {
+ TYPE_PV88080_AA,
+ TYPE_PV88080_BA,
+};
+
+/* Interrupts */
+enum pv88080_aa_irqs {
+ PV88080_AA_IRQ_VDD_FLT,
+ PV88080_AA_IRQ_OVER_TEMP,
+ PV88080_AA_IRQ_SEQ_RDY,
+ PV88080_AA_IRQ_HVBUCK_OV,
+ PV88080_AA_IRQ_HVBUCK_UV,
+ PV88080_AA_IRQ_HVBUCK_SCP,
+ PV88080_AA_IRQ_BUCK1_SCP,
+ PV88080_AA_IRQ_BUCK2_SCP,
+ PV88080_AA_IRQ_BUCK3_SCP,
+ PV88080_AA_IRQ_GPIO_FLAG0,
+ PV88080_AA_IRQ_GPIO_FLAG1,
+};
+
+enum pv88080_ba_irqs {
+ PV88080_BA_IRQ_VDD_FLT,
+ PV88080_BA_IRQ_OVER_TEMP,
+ PV88080_BA_IRQ_SEQ_RDY,
+ PV88080_BA_IRQ_EXT_OT,
+ PV88080_BA_IRQ_HVBUCK_OV,
+ PV88080_BA_IRQ_HVBUCK_UV,
+ PV88080_BA_IRQ_HVBUCK_SCP,
+ PV88080_BA_IRQ_BUCK1_SCP,
+ PV88080_BA_IRQ_BUCK2_SCP,
+ PV88080_BA_IRQ_BUCK3_SCP,
+ PV88080_BA_IRQ_GPIO_FLAG0,
+ PV88080_BA_IRQ_GPIO_FLAG1,
+ PV88080_BA_IRQ_BUCK1_DROP_TIMEOUT,
+ PV88080_BA_IRQ_BUCK2_DROP_TIMEOUT,
+ PB88080_BA_IRQ_BUCK3_DROP_TIMEOUT,
+};
+
+struct pv88080 {
+ struct device *dev;
+ struct regmap *regmap;
+ unsigned long type;
+
+ /* IRQ Data */
+ int irq;
+ struct regmap_irq_chip_data *irq_data;
+};
+
+#endif /* __PV88080_H__ */
+
--
end-of-patch for PATCH V3
^ permalink raw reply related
* [PATCH V3 3/4] regulator: pv88080: Update Regulator driver for MFD support
From: Eric Jeong @ 2016-11-18 0:35 UTC (permalink / raw)
To: LINUX-KERNEL, Liam Girdwood, Mark Brown
Cc: Alexandre Courbot, DEVICETREE, LINUX-GPIO, Lee Jones,
Linus Walleij, Mark Rutland, Rob Herring, Support Opensource
In-Reply-To: <cover.1479429347.git.eric.jeong@diasemi.com>
From: Eric Jeong <eric.jeong.opensource@diasemi.com>
This change convert from using struct i2c_clinet
to using struct platform_device for MFD structure.
And, the declaration of of_device_id and regmap_config
are also move to MFD driver.
The configuration for MASK registers is moved
to MFD core.
Kconfig is updated to reflect support for PV88080 regulator.
Signed-off-by: Eric Jeong <eric.jeong.opensource@diasemi.com>
---
This patch applies against linux-next and next-20161117
Hi,
The existing PV88080 regulstor driver is updated to support
MFD structure by adding GPIO function.
Most of changes are related with MFD structure support.
Change since PATCH V2
- Fix regression in config and driver
- Change IRQ name.
Change since PATCH V1
- Patch separated from PATCH V1
Regards,
Eric Jeong, Dialog Semiconductor Ltd.
drivers/regulator/Kconfig | 9 +-
drivers/regulator/pv88080-regulator.c | 185 +++++++++++----------------------
drivers/regulator/pv88080-regulator.h | 118 ---------------------
3 files changed, 66 insertions(+), 246 deletions(-)
delete mode 100644 drivers/regulator/pv88080-regulator.h
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index 936f7cc..ea89653 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -577,10 +577,13 @@ config REGULATOR_PV88060
config REGULATOR_PV88080
tristate "Powerventure Semiconductor PV88080 regulator"
- depends on I2C
- select REGMAP_I2C
+ depends on MFD_PV88080
help
- Say y here to support the buck convertors on PV88080
+ Say y here to support the BUCKs regulators found on
+ PV88080 PMICs.
+
+ This driver can also be built as a module. If so, the module
+ will be called pv88080-regulator.
config REGULATOR_PV88090
tristate "Powerventure Semiconductor PV88090 regulator"
diff --git a/drivers/regulator/pv88080-regulator.c b/drivers/regulator/pv88080-regulator.c
index 954a20e..eb9024d 100644
--- a/drivers/regulator/pv88080-regulator.c
+++ b/drivers/regulator/pv88080-regulator.c
@@ -14,8 +14,8 @@
*/
#include <linux/err.h>
-#include <linux/i2c.h>
#include <linux/module.h>
+#include <linux/platform_device.h>
#include <linux/of.h>
#include <linux/init.h>
#include <linux/slab.h>
@@ -25,9 +25,8 @@
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/regulator/of_regulator.h>
-#include "pv88080-regulator.h"
-#define PV88080_MAX_REGULATORS 4
+#include <linux/mfd/pv88080.h>
/* PV88080 REGULATOR IDs */
enum {
@@ -38,11 +37,6 @@ enum {
PV88080_ID_HVBUCK,
};
-enum pv88080_types {
- TYPE_PV88080_AA,
- TYPE_PV88080_BA,
-};
-
struct pv88080_regulator {
struct regulator_desc desc;
/* Current limiting */
@@ -55,14 +49,6 @@ struct pv88080_regulator {
unsigned int conf5;
};
-struct pv88080 {
- struct device *dev;
- struct regmap *regmap;
- struct regulator_dev *rdev[PV88080_MAX_REGULATORS];
- unsigned long type;
- const struct pv88080_compatible_regmap *regmap_config;
-};
-
struct pv88080_buck_voltage {
int min_uV;
int max_uV;
@@ -93,9 +79,11 @@ struct pv88080_compatible_regmap {
int hvbuck_vsel_mask;
};
-static const struct regmap_config pv88080_regmap_config = {
- .reg_bits = 8,
- .val_bits = 8,
+struct pv88080_regulators {
+ int virq;
+ struct pv88080 *pv88080;
+ struct regulator_dev *rdev[PV88080_MAX_REGULATORS];
+ const struct pv88080_compatible_regmap *regmap_config;
};
/* Current limits array (in uA) for BUCK1, BUCK2, BUCK3.
@@ -211,16 +199,6 @@ struct pv88080_compatible_regmap {
.hvbuck_vsel_mask = PV88080_VHVBUCK_MASK,
};
-#ifdef CONFIG_OF
-static const struct of_device_id pv88080_dt_ids[] = {
- { .compatible = "pvs,pv88080", .data = (void *)TYPE_PV88080_AA },
- { .compatible = "pvs,pv88080-aa", .data = (void *)TYPE_PV88080_AA },
- { .compatible = "pvs,pv88080-ba", .data = (void *)TYPE_PV88080_BA },
- {},
-};
-MODULE_DEVICE_TABLE(of, pv88080_dt_ids);
-#endif
-
static unsigned int pv88080_buck_get_mode(struct regulator_dev *rdev)
{
struct pv88080_regulator *info = rdev_get_drvdata(rdev);
@@ -372,9 +350,10 @@ static int pv88080_get_current_limit(struct regulator_dev *rdev)
PV88080_HVBUCK(PV88080, HVBUCK, 0, 5000, 1275000),
};
-static irqreturn_t pv88080_irq_handler(int irq, void *data)
+static irqreturn_t pv88080_vdd_overtemp_event(int irq, void *data)
{
- struct pv88080 *chip = data;
+ struct pv88080_regulators *regulators = data;
+ struct pv88080 *chip = regulators->pv88080;
int i, reg_val, err, ret = IRQ_NONE;
err = regmap_read(chip->regmap, PV88080_REG_EVENT_A, ®_val);
@@ -383,8 +362,9 @@ static irqreturn_t pv88080_irq_handler(int irq, void *data)
if (reg_val & PV88080_E_VDD_FLT) {
for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
- if (chip->rdev[i] != NULL) {
- regulator_notifier_call_chain(chip->rdev[i],
+ if (regulators->rdev[i] != NULL) {
+ regulator_notifier_call_chain(
+ regulators->rdev[i],
REGULATOR_EVENT_UNDER_VOLTAGE,
NULL);
}
@@ -400,8 +380,9 @@ static irqreturn_t pv88080_irq_handler(int irq, void *data)
if (reg_val & PV88080_E_OVER_TEMP) {
for (i = 0; i < PV88080_MAX_REGULATORS; i++) {
- if (chip->rdev[i] != NULL) {
- regulator_notifier_call_chain(chip->rdev[i],
+ if (regulators->rdev[i] != NULL) {
+ regulator_notifier_call_chain(
+ regulators->rdev[i],
REGULATOR_EVENT_OVER_TEMP,
NULL);
}
@@ -425,94 +406,61 @@ static irqreturn_t pv88080_irq_handler(int irq, void *data)
/*
* I2C driver interface functions
*/
-static int pv88080_i2c_probe(struct i2c_client *i2c,
- const struct i2c_device_id *id)
+static int pv88080_regulator_probe(struct platform_device *pdev)
{
- struct regulator_init_data *init_data = dev_get_platdata(&i2c->dev);
- struct pv88080 *chip;
+ struct regulator_init_data *init_data = dev_get_platdata(&pdev->dev);
+ struct pv88080 *chip = dev_get_drvdata(pdev->dev.parent);
+ struct pv88080_regulators *regulators;
const struct pv88080_compatible_regmap *regmap_config;
- const struct of_device_id *match;
struct regulator_config config = { };
- int i, error, ret;
+ int i, ret, irq;
unsigned int conf2, conf5;
- chip = devm_kzalloc(&i2c->dev, sizeof(struct pv88080), GFP_KERNEL);
- if (!chip)
+ regulators = devm_kzalloc(&pdev->dev,
+ sizeof(struct pv88080_regulators), GFP_KERNEL);
+ if (!regulators)
return -ENOMEM;
- chip->dev = &i2c->dev;
- chip->regmap = devm_regmap_init_i2c(i2c, &pv88080_regmap_config);
- if (IS_ERR(chip->regmap)) {
- error = PTR_ERR(chip->regmap);
- dev_err(chip->dev, "Failed to allocate register map: %d\n",
- error);
- return error;
- }
+ platform_set_drvdata(pdev, regulators);
- if (i2c->dev.of_node) {
- match = of_match_node(pv88080_dt_ids, i2c->dev.of_node);
- if (!match) {
- dev_err(chip->dev, "Failed to get of_match_node\n");
- return -EINVAL;
- }
- chip->type = (unsigned long)match->data;
- } else {
- chip->type = id->driver_data;
+ irq = platform_get_irq_byname(pdev, "VDD_TEMP_FAULT");
+ if (irq < 0) {
+ dev_err(&pdev->dev, "Failed to get IRQ.\n");
+ return irq;
}
- i2c_set_clientdata(i2c, chip);
-
- if (i2c->irq != 0) {
- ret = regmap_write(chip->regmap, PV88080_REG_MASK_A, 0xFF);
- if (ret < 0) {
- dev_err(chip->dev,
- "Failed to mask A reg: %d\n", ret);
- return ret;
- }
- ret = regmap_write(chip->regmap, PV88080_REG_MASK_B, 0xFF);
- if (ret < 0) {
- dev_err(chip->dev,
- "Failed to mask B reg: %d\n", ret);
- return ret;
- }
- ret = regmap_write(chip->regmap, PV88080_REG_MASK_C, 0xFF);
- if (ret < 0) {
- dev_err(chip->dev,
- "Failed to mask C reg: %d\n", ret);
- return ret;
- }
-
- ret = devm_request_threaded_irq(&i2c->dev, i2c->irq, NULL,
- pv88080_irq_handler,
- IRQF_TRIGGER_LOW|IRQF_ONESHOT,
- "pv88080", chip);
- if (ret != 0) {
- dev_err(chip->dev, "Failed to request IRQ: %d\n",
- i2c->irq);
+ regulators->virq = regmap_irq_get_virq(chip->irq_data, irq);
+ if (regulators->virq >= 0) {
+ ret = devm_request_threaded_irq(&pdev->dev,
+ regulators->virq, NULL,
+ pv88080_vdd_overtemp_event,
+ IRQF_TRIGGER_LOW|IRQF_ONESHOT,
+ "VDD_TEMP_FAULT", regulators);
+ if (ret) {
+ dev_err(chip->dev, "Failed to request IRQ: %d\n", irq);
return ret;
}
+ }
- ret = regmap_update_bits(chip->regmap, PV88080_REG_MASK_A,
- PV88080_M_VDD_FLT | PV88080_M_OVER_TEMP, 0);
- if (ret < 0) {
- dev_err(chip->dev,
- "Failed to update mask reg: %d\n", ret);
- return ret;
- }
- } else {
- dev_warn(chip->dev, "No IRQ configured\n");
+ ret = regmap_update_bits(chip->regmap, PV88080_REG_MASK_A,
+ PV88080_M_VDD_FLT | PV88080_M_OVER_TEMP, 0);
+ if (ret < 0) {
+ dev_err(chip->dev,
+ "Failed to update mask reg: %d\n", ret);
+ return ret;
}
switch (chip->type) {
case TYPE_PV88080_AA:
- chip->regmap_config = &pv88080_aa_regs;
+ regulators->regmap_config = &pv88080_aa_regs;
break;
case TYPE_PV88080_BA:
- chip->regmap_config = &pv88080_ba_regs;
+ regulators->regmap_config = &pv88080_ba_regs;
break;
}
- regmap_config = chip->regmap_config;
+ regulators->pv88080 = chip;
+ regmap_config = regulators->regmap_config;
config.dev = chip->dev;
config.regmap = chip->regmap;
@@ -564,12 +512,12 @@ static int pv88080_i2c_probe(struct i2c_client *i2c,
/(pv88080_regulator_info[i].desc.uV_step) + 1;
config.driver_data = (void *)&pv88080_regulator_info[i];
- chip->rdev[i] = devm_regulator_register(chip->dev,
+ regulators->rdev[i] = devm_regulator_register(chip->dev,
&pv88080_regulator_info[i].desc, &config);
- if (IS_ERR(chip->rdev[i])) {
+ if (IS_ERR(regulators->rdev[i])) {
dev_err(chip->dev,
"Failed to register PV88080 regulator\n");
- return PTR_ERR(chip->rdev[i]);
+ return PTR_ERR(regulators->rdev[i]);
}
}
@@ -582,40 +530,27 @@ static int pv88080_i2c_probe(struct i2c_client *i2c,
pv88080_regulator_info[PV88080_ID_HVBUCK].desc.vsel_mask
= regmap_config->hvbuck_vsel_mask;
- /* Registeration for HVBUCK */
if (init_data)
config.init_data = &init_data[PV88080_ID_HVBUCK];
config.driver_data = (void *)&pv88080_regulator_info[PV88080_ID_HVBUCK];
- chip->rdev[PV88080_ID_HVBUCK] = devm_regulator_register(chip->dev,
+ regulators->rdev[PV88080_ID_HVBUCK] = devm_regulator_register(chip->dev,
&pv88080_regulator_info[PV88080_ID_HVBUCK].desc, &config);
- if (IS_ERR(chip->rdev[PV88080_ID_HVBUCK])) {
+ if (IS_ERR(regulators->rdev[PV88080_ID_HVBUCK])) {
dev_err(chip->dev, "Failed to register PV88080 regulator\n");
- return PTR_ERR(chip->rdev[PV88080_ID_HVBUCK]);
+ return PTR_ERR(regulators->rdev[PV88080_ID_HVBUCK]);
}
return 0;
}
-
-static const struct i2c_device_id pv88080_i2c_id[] = {
- { "pv88080", TYPE_PV88080_AA },
- { "pv88080-aa", TYPE_PV88080_AA },
- { "pv88080-ba", TYPE_PV88080_BA },
- {},
-};
-MODULE_DEVICE_TABLE(i2c, pv88080_i2c_id);
-
-static struct i2c_driver pv88080_regulator_driver = {
+static struct platform_driver pv88080_regulator_driver = {
.driver = {
- .name = "pv88080",
- .of_match_table = of_match_ptr(pv88080_dt_ids),
+ .name = "pv88080-regulator",
},
- .probe = pv88080_i2c_probe,
- .id_table = pv88080_i2c_id,
+ .probe = pv88080_regulator_probe,
};
+module_platform_driver(pv88080_regulator_driver);
-module_i2c_driver(pv88080_regulator_driver);
-
-MODULE_AUTHOR("James Ban <James.Ban.opensource@diasemi.com>");
+MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource@diasemi.com>");
MODULE_DESCRIPTION("Regulator device driver for Powerventure PV88080");
MODULE_LICENSE("GPL");
diff --git a/drivers/regulator/pv88080-regulator.h b/drivers/regulator/pv88080-regulator.h
deleted file mode 100644
index ae25ff3..0000000
--- a/drivers/regulator/pv88080-regulator.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * pv88080-regulator.h - Regulator definitions for PV88080
- * Copyright (C) 2016 Powerventure Semiconductor Ltd.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __PV88080_REGISTERS_H__
-#define __PV88080_REGISTERS_H__
-
-/* System Control and Event Registers */
-#define PV88080_REG_EVENT_A 0x04
-#define PV88080_REG_MASK_A 0x09
-#define PV88080_REG_MASK_B 0x0A
-#define PV88080_REG_MASK_C 0x0B
-
-/* Regulator Registers - rev. AA */
-#define PV88080AA_REG_HVBUCK_CONF1 0x2D
-#define PV88080AA_REG_HVBUCK_CONF2 0x2E
-#define PV88080AA_REG_BUCK1_CONF0 0x27
-#define PV88080AA_REG_BUCK1_CONF1 0x28
-#define PV88080AA_REG_BUCK1_CONF2 0x59
-#define PV88080AA_REG_BUCK1_CONF5 0x5C
-#define PV88080AA_REG_BUCK2_CONF0 0x29
-#define PV88080AA_REG_BUCK2_CONF1 0x2A
-#define PV88080AA_REG_BUCK2_CONF2 0x61
-#define PV88080AA_REG_BUCK2_CONF5 0x64
-#define PV88080AA_REG_BUCK3_CONF0 0x2B
-#define PV88080AA_REG_BUCK3_CONF1 0x2C
-#define PV88080AA_REG_BUCK3_CONF2 0x69
-#define PV88080AA_REG_BUCK3_CONF5 0x6C
-
-/* Regulator Registers - rev. BA */
-#define PV88080BA_REG_HVBUCK_CONF1 0x33
-#define PV88080BA_REG_HVBUCK_CONF2 0x34
-#define PV88080BA_REG_BUCK1_CONF0 0x2A
-#define PV88080BA_REG_BUCK1_CONF1 0x2C
-#define PV88080BA_REG_BUCK1_CONF2 0x5A
-#define PV88080BA_REG_BUCK1_CONF5 0x5D
-#define PV88080BA_REG_BUCK2_CONF0 0x2D
-#define PV88080BA_REG_BUCK2_CONF1 0x2F
-#define PV88080BA_REG_BUCK2_CONF2 0x63
-#define PV88080BA_REG_BUCK2_CONF5 0x66
-#define PV88080BA_REG_BUCK3_CONF0 0x30
-#define PV88080BA_REG_BUCK3_CONF1 0x32
-#define PV88080BA_REG_BUCK3_CONF2 0x6C
-#define PV88080BA_REG_BUCK3_CONF5 0x6F
-
-/* PV88080_REG_EVENT_A (addr=0x04) */
-#define PV88080_E_VDD_FLT 0x01
-#define PV88080_E_OVER_TEMP 0x02
-
-/* PV88080_REG_MASK_A (addr=0x09) */
-#define PV88080_M_VDD_FLT 0x01
-#define PV88080_M_OVER_TEMP 0x02
-
-/* PV88080_REG_BUCK1_CONF0 (addr=0x27|0x2A) */
-#define PV88080_BUCK1_EN 0x80
-#define PV88080_VBUCK1_MASK 0x7F
-
-/* PV88080_REG_BUCK2_CONF0 (addr=0x29|0x2D) */
-#define PV88080_BUCK2_EN 0x80
-#define PV88080_VBUCK2_MASK 0x7F
-
-/* PV88080_REG_BUCK3_CONF0 (addr=0x2B|0x30) */
-#define PV88080_BUCK3_EN 0x80
-#define PV88080_VBUCK3_MASK 0x7F
-
-/* PV88080_REG_BUCK1_CONF1 (addr=0x28|0x2C) */
-#define PV88080_BUCK1_ILIM_SHIFT 2
-#define PV88080_BUCK1_ILIM_MASK 0x0C
-#define PV88080_BUCK1_MODE_MASK 0x03
-
-/* PV88080_REG_BUCK2_CONF1 (addr=0x2A|0x2F) */
-#define PV88080_BUCK2_ILIM_SHIFT 2
-#define PV88080_BUCK2_ILIM_MASK 0x0C
-#define PV88080_BUCK2_MODE_MASK 0x03
-
-/* PV88080_REG_BUCK3_CONF1 (addr=0x2C|0x32) */
-#define PV88080_BUCK3_ILIM_SHIFT 2
-#define PV88080_BUCK3_ILIM_MASK 0x0C
-#define PV88080_BUCK3_MODE_MASK 0x03
-
-#define PV88080_BUCK_MODE_SLEEP 0x00
-#define PV88080_BUCK_MODE_AUTO 0x01
-#define PV88080_BUCK_MODE_SYNC 0x02
-
-/* PV88080_REG_HVBUCK_CONF1 (addr=0x2D|0x33) */
-#define PV88080_VHVBUCK_MASK 0xFF
-
-/* PV88080_REG_HVBUCK_CONF1 (addr=0x2E|0x34) */
-#define PV88080_HVBUCK_EN 0x01
-
-/* PV88080_REG_BUCK2_CONF2 (addr=0x61|0x63) */
-/* PV88080_REG_BUCK3_CONF2 (addr=0x69|0x6C) */
-#define PV88080_BUCK_VDAC_RANGE_SHIFT 7
-#define PV88080_BUCK_VDAC_RANGE_MASK 0x01
-
-#define PV88080_BUCK_VDAC_RANGE_1 0x00
-#define PV88080_BUCK_VDAC_RANGE_2 0x01
-
-/* PV88080_REG_BUCK2_CONF5 (addr=0x64|0x66) */
-/* PV88080_REG_BUCK3_CONF5 (addr=0x6C|0x6F) */
-#define PV88080_BUCK_VRANGE_GAIN_SHIFT 0
-#define PV88080_BUCK_VRANGE_GAIN_MASK 0x01
-
-#define PV88080_BUCK_VRANGE_GAIN_1 0x00
-#define PV88080_BUCK_VRANGE_GAIN_2 0x01
-
-#endif /* __PV88080_REGISTERS_H__ */
--
end-of-patch for PATCH V3
^ permalink raw reply related
* [PATCH V3 1/4] Documentation: pv88080: Move binding document
From: Eric Jeong @ 2016-11-18 0:35 UTC (permalink / raw)
To: DEVICETREE, LINUX-KERNEL, Mark Rutland, Rob Herring
Cc: Alexandre Courbot, LINUX-GPIO, Lee Jones, Liam Girdwood,
Linus Walleij, Mark Brown, Support Opensource
In-Reply-To: <cover.1479429347.git.eric.jeong-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
From: Eric Jeong <eric.jeong.opensource-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
The change is to move pv88080 binding document
from the regulator directory to mfd binding directory
for PV88080 PMIC MFD support.
And, GPIO properties are added.
Signed-off-by: Eric Jeong <eric.jeong.opensource-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
---
This patch applies against linux-next and next-20161117
Hi,
Change since PATCH V2
- Added property and description for gpio
Change since PATCH V1
- Patch separated from PATCH V1
Regards,
Eric Jeong, Dialog Semiconductor Ltd.
.../bindings/{regulator => mfd}/pv88080.txt | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
rename Documentation/devicetree/bindings/{regulator => mfd}/pv88080.txt (79%)
diff --git a/Documentation/devicetree/bindings/regulator/pv88080.txt b/Documentation/devicetree/bindings/mfd/pv88080.txt
similarity index 79%
rename from Documentation/devicetree/bindings/regulator/pv88080.txt
rename to Documentation/devicetree/bindings/mfd/pv88080.txt
index e6e4b9c8..7e24f95 100644
--- a/Documentation/devicetree/bindings/regulator/pv88080.txt
+++ b/Documentation/devicetree/bindings/mfd/pv88080.txt
@@ -1,4 +1,4 @@
-* Powerventure Semiconductor PV88080 Voltage Regulator
+* Powerventure Semiconductor PV88080 PMIC
Required properties:
- compatible: Must be one of the following, depending on the
@@ -16,8 +16,15 @@ Required properties:
standard binding for regulators; see regulator.txt.
BUCK1, BUCK2, BUCK3 and HVBUCK.
+- gpio-controller: Marks the device node as a GPIO controller.
+- #gpio-cells: Should be 2. See gpio.txt in this directory
+ for a description of the cells format.
+
Optional properties:
+- ngpios : Number of in-use slots of available slots for GPIO.
+ Maximum is 2.
- Any optional property defined in regulator.txt
+ and gpio.txt for more information.
Example:
@@ -27,6 +34,13 @@ Example:
interrupt-parent = <&gpio>;
interrupts = <24 24>;
+ gpioex {
+ compatible = "pvs,pv88080-gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <2>;
+ };
+
regulators {
BUCK1 {
regulator-name = "buck1";
--
end-of-patch for PATCH V3
--
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^ permalink raw reply related
* [PATCH V3 4/4] gpio: pv88080: Add GPIO function support
From: Eric Jeong @ 2016-11-18 0:35 UTC (permalink / raw)
To: Alexandre Courbot, LINUX-GPIO, LINUX-KERNEL, Linus Walleij
Cc: DEVICETREE, Lee Jones, Liam Girdwood, Mark Brown, Mark Rutland,
Rob Herring, Support Opensource
In-Reply-To: <cover.1479429347.git.eric.jeong-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
From: Eric Jeong <eric.jeong.opensource-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
This patch adds support for PV88080 PMIC GPIOs.
PV88080 has two configurable GPIOs.
Kconfig and Makefile are updated to reflect support
for PV88080 PMIC GPIO.
Signed-off-by: Eric Jeong <eric.jeong.opensource-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>
---
This patch applies against linux-next and next-20161117
Hi,
Change since PATCH V2
- Add the set_single_ended function
- Add property reading function
- Simplify and clarfy the funcion of gpio_chip
Change since PATCH V1
- Patch separated from PATCH V1
Regards,
Eric Jeong, Dialog Semiconductor Ltd.
drivers/gpio/Kconfig | 11 +++
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-pv88080.c | 213 +++++++++++++++++++++++++++++++++++++++++++
3 files changed, 225 insertions(+)
create mode 100644 drivers/gpio/gpio-pv88080.c
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index a9a1c8a..cb11686 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -949,6 +949,17 @@ config GPIO_PALMAS
Select this option to enable GPIO driver for the TI PALMAS
series chip family.
+config GPIO_PV88080
+ tristate "Powerventure Semiconductor PV88080 GPIO"
+ depends on MFD_PV88080
+ help
+ Support for GPIO pins on PV88080 PMIC.
+
+ Say yes here to enable the GPIO driver for the PV88080 chip.
+
+ The Powerventure PMIC chip has 2 GPIO pins that can be
+ controlled by this driver.
+
config GPIO_RC5T583
bool "RICOH RC5T583 GPIO"
depends on MFD_RC5T583
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 8043a95..2a2311e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -92,6 +92,7 @@ obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o
obj-$(CONFIG_GPIO_PCH) += gpio-pch.o
obj-$(CONFIG_GPIO_PISOSR) += gpio-pisosr.o
obj-$(CONFIG_GPIO_PL061) += gpio-pl061.o
+obj-$(CONFIG_GPIO_PV88080) += gpio-pv88080.o
obj-$(CONFIG_GPIO_PXA) += gpio-pxa.o
obj-$(CONFIG_GPIO_RC5T583) += gpio-rc5t583.o
obj-$(CONFIG_GPIO_RDC321X) += gpio-rdc321x.o
diff --git a/drivers/gpio/gpio-pv88080.c b/drivers/gpio/gpio-pv88080.c
new file mode 100644
index 0000000..6f4734f
--- /dev/null
+++ b/drivers/gpio/gpio-pv88080.c
@@ -0,0 +1,213 @@
+/*
+ * gpio-pv88080.c - GPIO device driver for PV88080
+ * Copyright (C) 2016 Powerventure Semiconductor Ltd.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+
+#include <linux/mfd/pv88080.h>
+
+#define PV88080_PORT_DIRECTION_INPUT 0
+#define PV88080_PORT_DIRECTION_OUTPUT 1
+
+struct pv88080_gpio {
+ struct pv88080 *chip;
+ struct gpio_chip gpio_chip;
+ unsigned int input_reg;
+ unsigned int output_reg;
+ unsigned int gpio_base_reg;
+};
+
+static int pv88080_gpio_get_direction(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+ unsigned int value;
+ int ret;
+
+ ret = regmap_read(chip->regmap, priv->gpio_base_reg + offset, &value);
+ if (ret)
+ return ret;
+
+ value = !(value & PV88080_GPIO_DIRECTION_MASK);
+
+ return value;
+}
+
+static int pv88080_gpio_direction_input(struct gpio_chip *gc,
+ unsigned int offset)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+
+ return regmap_update_bits(chip->regmap, priv->gpio_base_reg + offset,
+ PV88080_GPIO_DIRECTION_MASK, 0);
+}
+
+static int pv88080_gpio_direction_output(struct gpio_chip *gc,
+ unsigned int offset, int value)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+
+ return regmap_update_bits(chip->regmap, priv->gpio_base_reg + offset,
+ PV88080_GPIO_DIRECTION_MASK, 1);
+}
+
+static int pv88080_gpio_get(struct gpio_chip *gc, unsigned int offset)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+ unsigned int reg, value;
+ int ret;
+
+ ret = regmap_read(chip->regmap, priv->gpio_base_reg + offset, &value);
+ if (ret < 0)
+ return ret;
+
+ if (value & PV88080_GPIO_DIRECTION_MASK)
+ reg = priv->output_reg;
+ else
+ reg = priv->input_reg;
+
+ ret = regmap_read(chip->regmap, reg, &value);
+ if (ret < 0)
+ return ret;
+
+ value = !!(value & BIT(offset));
+
+ return value;
+}
+
+static void pv88080_gpio_set(struct gpio_chip *gc, unsigned int offset,
+ int value)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+ int ret;
+
+ ret = regmap_update_bits(chip->regmap, priv->output_reg,
+ BIT(offset), (value << offset));
+ if (ret < 0)
+ dev_err(chip->dev, "Failed to update gpio\n");
+}
+
+static int pv88080_set_single_ended(struct gpio_chip *gc,
+ unsigned int offset,
+ enum single_ended_mode mode)
+{
+ struct pv88080_gpio *priv = gpiochip_get_data(gc);
+ struct pv88080 *chip = priv->chip;
+ int ret;
+
+ switch (mode) {
+ case LINE_MODE_OPEN_DRAIN:
+ ret = regmap_update_bits(chip->regmap,
+ priv->gpio_base_reg + offset,
+ PV88080_GPIO_SINGLE_ENDED_MASK, 0);
+ break;
+ case LINE_MODE_PUSH_PULL:
+ ret = regmap_update_bits(chip->regmap,
+ priv->gpio_base_reg + offset,
+ PV88080_GPIO_SINGLE_ENDED_MASK, 1 << 1);
+ break;
+ default:
+ ret = -ENOTSUPP;
+ break;
+ }
+
+ return ret;
+}
+
+static const struct gpio_chip template_gpio = {
+ .label = "pv88080-gpio",
+ .owner = THIS_MODULE,
+ .get_direction = pv88080_gpio_get_direction,
+ .direction_input = pv88080_gpio_direction_input,
+ .direction_output = pv88080_gpio_direction_output,
+ .get = pv88080_gpio_get,
+ .set = pv88080_gpio_set,
+ .set_single_ended = pv88080_set_single_ended,
+ .base = -1,
+ .ngpio = 2,
+};
+
+static const struct of_device_id pv88080_gpio_of_match[] = {
+ { .compatible = "pvs,pv88080-gpio", },
+ { },
+};
+MODULE_DEVICE_TABLE(of, pv88080_gpio_of_match);
+
+static int pv88080_gpio_probe(struct platform_device *pdev)
+{
+ struct pv88080 *chip = dev_get_drvdata(pdev->dev.parent);
+ struct pv88080_gpio *priv;
+ struct device_node *np = pdev->dev.of_node;
+ u32 ngpios;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev,
+ sizeof(struct pv88080_gpio), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->chip = chip;
+ priv->gpio_chip = template_gpio;
+ priv->gpio_chip.parent = &pdev->dev;
+
+ switch (chip->type) {
+ case TYPE_PV88080_AA:
+ priv->input_reg = PV88080AA_REG_GPIO_INPUT;
+ priv->output_reg = PV88080AA_REG_GPIO_OUTPUT;
+ priv->gpio_base_reg = PV88080AA_REG_GPIO_GPIO0;
+ break;
+ case TYPE_PV88080_BA:
+ priv->input_reg = PV88080BA_REG_GPIO_INPUT;
+ priv->output_reg = PV88080BA_REG_GPIO_OUTPUT;
+ priv->gpio_base_reg = PV88080BA_REG_GPIO_GPIO0;
+ break;
+ }
+
+ if (!of_property_read_u32(np, "ngpios", &ngpios))
+ priv->gpio_chip.ngpio = ngpios;
+
+ ret = devm_gpiochip_add_data(&pdev->dev, &priv->gpio_chip, priv);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "Unable to register gpiochip\n");
+ return ret;
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ return 0;
+}
+
+static struct platform_driver pv88080_gpio_driver = {
+ .driver = {
+ .name = "pv88080-gpio",
+ .of_match_table = of_match_ptr(pv88080_gpio_of_match),
+ },
+ .probe = pv88080_gpio_probe,
+};
+module_platform_driver(pv88080_gpio_driver);
+
+MODULE_AUTHOR("Eric Jeong <eric.jeong.opensource-WBD+wuPFNBhBDgjK7y7TUQ@public.gmane.org>");
+MODULE_DESCRIPTION("GPIO device driver for Powerventure PV88080");
+MODULE_LICENSE("GPL");
+
--
end-of-patch for PATCH V3
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^ permalink raw reply related
* [PATCH V3 0/4] pv88080: PV88080 driver submission
From: Eric Jeong @ 2016-11-18 0:35 UTC (permalink / raw)
To: Alexandre Courbot, DEVICETREE, LINUX-GPIO, LINUX-KERNEL,
Lee Jones, Liam Girdwood, Linus Walleij, Mark Brown, Mark Rutland,
Rob Herring
Cc: Support Opensource
From: Eric Jeong <eric.jeong.opensource@diasemi.com>
This patch set adds support for the PV88080 PMIC.
And, this patch is done as part of the existing PV88080 Regulator
driver by expanding the driver for GPIO function support.
In this patch set the following is provided:
[PATCH V3 1/4] Move binding document
[PATCH V3 2/4] MFD core support
[PATCH V3 3/4] Update regulator driver for MFD support
[PATCH V3 4/4] Add GPIO function support
This patch applies against linux-next and next-20161117
Thank you,
Eric Jeong, Dialog Semiconductor Ltd.
Eric Jeong (4):
Documentation: pv88080: Move binding document
mfd: pv88080: MFD core support
regulator: pv88080: Update Regulator driver for MFD support
gpio: pv88080: Add GPIO function support
.../bindings/{regulator => mfd}/pv88080.txt | 16 +-
drivers/gpio/Kconfig | 11 +
drivers/gpio/Makefile | 1 +
drivers/gpio/gpio-pv88080.c | 213 +++++++++++++
drivers/mfd/Kconfig | 12 +
drivers/mfd/Makefile | 1 +
drivers/mfd/pv88080.c | 331 ++++++++++++++++++++
drivers/regulator/Kconfig | 9 +-
drivers/regulator/pv88080-regulator.c | 185 ++++-------
drivers/regulator/pv88080-regulator.h | 118 -------
include/linux/mfd/pv88080.h | 222 +++++++++++++
11 files changed, 872 insertions(+), 247 deletions(-)
rename Documentation/devicetree/bindings/{regulator => mfd}/pv88080.txt (79%)
create mode 100644 drivers/gpio/gpio-pv88080.c
create mode 100644 drivers/mfd/pv88080.c
delete mode 100644 drivers/regulator/pv88080-regulator.h
create mode 100644 include/linux/mfd/pv88080.h
--
end-of-patch for PATCH V3
^ permalink raw reply
* Re: [PATCH] ARM: dts: am335x-boneblack: Add blue-and-red-wiring -property to LCDC node
From: Tony Lindgren @ 2016-11-18 1:25 UTC (permalink / raw)
To: Jyri Sarha
Cc: dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW,
devicetree-u79uwXL29TY76Z2rM5mHXA, tomi.valkeinen-l0cyMroinI0
In-Reply-To: <a7a7cd2666199316cbf13f5c1c9a387838f645bf.1479413359.git.jsarha-l0cyMroinI0@public.gmane.org>
* Jyri Sarha <jsarha-l0cyMroinI0@public.gmane.org> [161117 12:14]:
> Add blue-and-red-wiring -property to LCDC node. Also adds comments on
> how to get support 24 bit RGB mode. After this patch am335x-boneblack
> support RGB565, BGR888, and XBGR8888 color formats. See details in
> Documentation/devicetree/bindings/display/tilcdc/tilcdc.txt.
>
> The BBB has straight color wiring from am335x to tda19988, however the
> tda19988 can be configured to cross the blue and red wires. The
> comments show how to do that with video-ports property of tda19988
> node and how to tell LCDC that blue and red wires are crossed, with
> blue-and-red-wiring LCDC node property. This changes supported color
> formats from 16 bit RGB and 24 bit BGR to 16 bit BGR and 24 bit RGB.
>
> Signed-off-by: Jyri Sarha <jsarha-l0cyMroinI0@public.gmane.org>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
> ---
> Hi Tony,
> Could you pick this for 4.10. We left it out form 4.9 to avoid
> conflict with beaglebone-back hdmi audio dts patches that slipped in
> trough drm branch.
Thanks applying into omap-for-v4.10/dt.
Tony
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^ permalink raw reply
* [PATCH] mmc: pwrseq: add support for Marvell SD8787 chip
From: Matt Ranostay @ 2016-11-18 1:55 UTC (permalink / raw)
To: linux-wireless-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA
Cc: Matt Ranostay, Tony Lindgren, Ulf Hansson, Mark Rutland,
Srinivas Kandagatla
Allow power sequencing for the Marvell SD8787 Wifi/BT chip.
This can be abstracted to other chipsets if needed in the future.
Cc: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
Cc: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Srinivas Kandagatla <srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
---
.../devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt | 14 +++
.../bindings/net/wireless/marvell-sd8xxx.txt | 4 +
drivers/mmc/core/Kconfig | 10 ++
drivers/mmc/core/Makefile | 1 +
drivers/mmc/core/pwrseq_sd8787.c | 117 +++++++++++++++++++++
5 files changed, 146 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
create mode 100644 drivers/mmc/core/pwrseq_sd8787.c
diff --git a/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
new file mode 100644
index 000000000000..1b658351629b
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/mmc-pwrseq-sd8787.txt
@@ -0,0 +1,14 @@
+* Marvell SD8787 power sequence provider
+
+Required properties:
+- compatible: must be "mmc-pwrseq-sd8787".
+- pwndn-gpio: contains a power down GPIO specifier.
+- reset-gpio: contains a reset GPIO specifier.
+
+Example:
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-sd8787";
+ pwrdn-gpio = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
+ reset-gpio = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
+ }
diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
index c421aba0a5bc..08fd65d35725 100644
--- a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
+++ b/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
@@ -32,6 +32,9 @@ Optional properties:
so that the wifi chip can wakeup host platform under certain condition.
during system resume, the irq will be disabled to make sure
unnecessary interrupt is not received.
+ - vmmc-supply: a phandle of a regulator, supplying VCC to the card
+ - mmc-pwrseq: phandle to the MMC power sequence node. See "mmc-pwrseq-*"
+ for documentation of MMC power sequence bindings.
Example:
@@ -44,6 +47,7 @@ so that firmware can wakeup host using this device side pin.
&mmc3 {
status = "okay";
vmmc-supply = <&wlan_en_reg>;
+ mmc-pwrseq = <&wifi_pwrseq>;
bus-width = <4>;
cap-power-off-card;
keep-power-in-suspend;
diff --git a/drivers/mmc/core/Kconfig b/drivers/mmc/core/Kconfig
index 250f223aaa80..cf61d676ac06 100644
--- a/drivers/mmc/core/Kconfig
+++ b/drivers/mmc/core/Kconfig
@@ -12,6 +12,16 @@ config PWRSEQ_EMMC
This driver can also be built as a module. If so, the module
will be called pwrseq_emmc.
+config PWRSEQ_SD8787
+ tristate "HW reset support for SD8787 BT + Wifi module"
+ depends on OF && (MWIFIEX || BT_MRVL_SDIO)
+ help
+ This selects hardware reset support for the SD8787 BT + Wifi
+ module. By default this option is set to n.
+
+ This driver can also be built as a module. If so, the module
+ will be called pwrseq_sd8787.
+
config PWRSEQ_SIMPLE
tristate "Simple HW reset support for MMC"
default y
diff --git a/drivers/mmc/core/Makefile b/drivers/mmc/core/Makefile
index f007151dfdc6..f1c060e56d4e 100644
--- a/drivers/mmc/core/Makefile
+++ b/drivers/mmc/core/Makefile
@@ -10,5 +10,6 @@ mmc_core-y := core.o bus.o host.o \
quirks.o slot-gpio.o
mmc_core-$(CONFIG_OF) += pwrseq.o
obj-$(CONFIG_PWRSEQ_SIMPLE) += pwrseq_simple.o
+obj-$(CONFIG_PWRSEQ_SD8787) += pwrseq_sd8787.o
obj-$(CONFIG_PWRSEQ_EMMC) += pwrseq_emmc.o
mmc_core-$(CONFIG_DEBUG_FS) += debugfs.o
diff --git a/drivers/mmc/core/pwrseq_sd8787.c b/drivers/mmc/core/pwrseq_sd8787.c
new file mode 100644
index 000000000000..f4080fe6439e
--- /dev/null
+++ b/drivers/mmc/core/pwrseq_sd8787.c
@@ -0,0 +1,117 @@
+/*
+ * pwrseq_sd8787.c - power sequence support for Marvell SD8787 BT + Wifi chip
+ *
+ * Copyright (C) 2016 Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
+ *
+ * Based on the original work pwrseq_simple.c
+ * Copyright (C) 2014 Linaro Ltd
+ * Author: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/gpio/consumer.h>
+
+#include <linux/mmc/host.h>
+
+#include "pwrseq.h"
+
+struct mmc_pwrseq_sd8787 {
+ struct mmc_pwrseq pwrseq;
+ struct gpio_desc *reset_gpio;
+ struct gpio_desc *pwrdn_gpio;
+};
+
+#define to_pwrseq_sd8787(p) container_of(p, struct mmc_pwrseq_sd8787, pwrseq)
+
+static void mmc_pwrseq_sd8787_pre_power_on(struct mmc_host *host)
+{
+ struct mmc_pwrseq_sd8787 *pwrseq = to_pwrseq_sd8787(host->pwrseq);
+
+ gpiod_set_value_cansleep(pwrseq->reset_gpio, 1);
+
+ msleep(300);
+ gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 1);
+}
+
+static void mmc_pwrseq_sd8787_power_off(struct mmc_host *host)
+{
+ struct mmc_pwrseq_sd8787 *pwrseq = to_pwrseq_sd8787(host->pwrseq);
+
+ gpiod_set_value_cansleep(pwrseq->pwrdn_gpio, 0);
+ gpiod_set_value_cansleep(pwrseq->reset_gpio, 0);
+}
+
+static const struct mmc_pwrseq_ops mmc_pwrseq_sd8787_ops = {
+ .pre_power_on = mmc_pwrseq_sd8787_pre_power_on,
+ .power_off = mmc_pwrseq_sd8787_power_off,
+};
+
+static const struct of_device_id mmc_pwrseq_sd8787_of_match[] = {
+ { .compatible = "mmc-pwrseq-sd8787",},
+ {/* sentinel */},
+};
+MODULE_DEVICE_TABLE(of, mmc_pwrseq_sd8787_of_match);
+
+static int mmc_pwrseq_sd8787_probe(struct platform_device *pdev)
+{
+ struct mmc_pwrseq_sd8787 *pwrseq;
+ struct device *dev = &pdev->dev;
+
+ pwrseq = devm_kzalloc(dev, sizeof(*pwrseq), GFP_KERNEL);
+ if (!pwrseq)
+ return -ENOMEM;
+
+ pwrseq->pwrdn_gpio = devm_gpiod_get(dev, "pwrdn", GPIOD_OUT_LOW);
+ if (IS_ERR(pwrseq->pwrdn_gpio))
+ return PTR_ERR(pwrseq->pwrdn_gpio);
+
+ pwrseq->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
+ if (IS_ERR(pwrseq->reset_gpio))
+ return PTR_ERR(pwrseq->reset_gpio);
+
+ pwrseq->pwrseq.dev = dev;
+ pwrseq->pwrseq.ops = &mmc_pwrseq_sd8787_ops;
+ pwrseq->pwrseq.owner = THIS_MODULE;
+ platform_set_drvdata(pdev, pwrseq);
+
+ return mmc_pwrseq_register(&pwrseq->pwrseq);
+}
+
+static int mmc_pwrseq_sd8787_remove(struct platform_device *pdev)
+{
+ struct mmc_pwrseq_sd8787 *pwrseq = platform_get_drvdata(pdev);
+
+ mmc_pwrseq_unregister(&pwrseq->pwrseq);
+
+ return 0;
+}
+
+static struct platform_driver mmc_pwrseq_sd8787_driver = {
+ .probe = mmc_pwrseq_sd8787_probe,
+ .remove = mmc_pwrseq_sd8787_remove,
+ .driver = {
+ .name = "pwrseq_sd8787",
+ .of_match_table = mmc_pwrseq_sd8787_of_match,
+ },
+};
+
+module_platform_driver(mmc_pwrseq_sd8787_driver);
+MODULE_LICENSE("GPL v2");
--
2.7.4
^ permalink raw reply related
* [RFC 1/6] drm/etnaviv: add binding for the gc320 found in ti socs
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robert Nelson,
Julien, Christian Gmeiner, Russell King, Lucas Stach,
Nishanth Menon, Tomi Valkeinen
Signed-off-by: Robert Nelson <robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Julien <jboulnois-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Christian Gmeiner <christian.gmeiner-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
CC: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
CC: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
CC: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
CC: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt | 1 +
drivers/gpu/drm/etnaviv/etnaviv_drv.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
index ed5e0a7..9fa259d 100644
--- a/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
+++ b/Documentation/devicetree/bindings/display/etnaviv/etnaviv-drm.txt
@@ -8,6 +8,7 @@ Required properties:
- compatible: Should be one of
"fsl,imx-gpu-subsystem"
"marvell,dove-gpu-subsystem"
+ "ti,gc320-gpu-subsystem"
- cores: Should contain a list of phandles pointing to Vivante GPU devices
example:
diff --git a/drivers/gpu/drm/etnaviv/etnaviv_drv.c b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
index a6799b0..ce51270 100644
--- a/drivers/gpu/drm/etnaviv/etnaviv_drv.c
+++ b/drivers/gpu/drm/etnaviv/etnaviv_drv.c
@@ -653,6 +653,7 @@ static int etnaviv_pdev_remove(struct platform_device *pdev)
static const struct of_device_id dt_match[] = {
{ .compatible = "fsl,imx-gpu-subsystem" },
{ .compatible = "marvell,dove-gpu-subsystem" },
+ { .compatible = "ti,gc320-gpu-subsystem" },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.10.2
--
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^ permalink raw reply related
* [RFC 2/6] drm/etnaviv: allow building etnaviv on omap devices
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robert Nelson,
Christian Gmeiner, Russell King, Lucas Stach
In-Reply-To: <20161118024436.13447-1-robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Robert Nelson <robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Christian Gmeiner <christian.gmeiner-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
CC: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
---
drivers/gpu/drm/etnaviv/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/etnaviv/Kconfig b/drivers/gpu/drm/etnaviv/Kconfig
index 2cde7a5..b776f41 100644
--- a/drivers/gpu/drm/etnaviv/Kconfig
+++ b/drivers/gpu/drm/etnaviv/Kconfig
@@ -2,7 +2,7 @@
config DRM_ETNAVIV
tristate "ETNAVIV (DRM support for Vivante GPU IP cores)"
depends on DRM
- depends on ARCH_MXC || ARCH_DOVE
+ depends on ARCH_MXC || ARCH_DOVE || ARCH_OMAP2PLUS
select SHMEM
select TMPFS
select IOMMU_API
--
2.10.2
--
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^ permalink raw reply related
* [RFC 3/6] Documentation: dt: add bindings for ti bb2d
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Gowtham Tammana, Tomi Valkeinen
In-Reply-To: <20161118024436.13447-1-robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Gowtham Tammana <g-tammana-l0cyMroinI0@public.gmane.org>
Add documentation for device tree bindings description for
2D GPU blitter module present in Texas Instruments family of SoCs.
Signed-off-by: Gowtham Tammana <g-tammana-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
---
Documentation/devicetree/bindings/gpu/ti-bb2d.txt | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpu/ti-bb2d.txt
diff --git a/Documentation/devicetree/bindings/gpu/ti-bb2d.txt b/Documentation/devicetree/bindings/gpu/ti-bb2d.txt
new file mode 100644
index 0000000..af47488
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpu/ti-bb2d.txt
@@ -0,0 +1,27 @@
+* Texas Instruments BB2D blitter module
+
+This binding describes the 2D BitBlit (BB2D) graphics accelerator
+subsystem based on the GC320 core from Vivante Corporation available
+in Texas Instruments SoCs.
+
+Required properties:
+ - compatible: value should take the following format:
+ "ti,<soc>-bb2d", "vivante,<gpuversion>"
+ accepted values:
+ (a) "ti,dra7-bb2d", "vivante,gc320" for TI DRA7xx / AM57x
+
+ - reg : base address and length of BB2D IP registers
+ - interrupts : BB2D interrupt line number
+ - ti,hwmods : name of the hwmod associated with BB2D module
+ - clocks : handle to BB2D functional clock
+ - clock-names : fclk
+
+Example for DRA7x SoC:
+ bb2d: bb2d@59000000 {
+ compatible = "ti,dra7-bb2d", "vivante,gc320";
+ reg = <0x59000000 0x0700>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "bb2d";
+ clocks = <&dpll_core_h24x2_ck>;
+ clock-names = "fclk";
+ };
--
2.10.2
--
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^ permalink raw reply related
* [RFC 4/6] ARM: dts: dra7: add entry for bb2d module
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Gowtham Tammana, Tomi Valkeinen
In-Reply-To: <20161118024436.13447-1-robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Gowtham Tammana <g-tammana-l0cyMroinI0@public.gmane.org>
BB2D entry is added to the dts file. Crossbar index number is used
for interrupt mapping.
Signed-off-by: Gowtham Tammana <g-tammana-l0cyMroinI0@public.gmane.org>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index addb753..43488b6 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -959,6 +959,16 @@
ti,hwmods = "dmm";
};
+ bb2d: bb2d@59000000 {
+ compatible = "ti,dra7-bb2d";
+ reg = <0x59000000 0x0700>;
+ interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ ti,hwmods = "bb2d";
+ clocks = <&dpll_core_h24x2_ck>;
+ clock-names = "fclk";
+ status = "disabled";
+ };
+
i2c1: i2c@48070000 {
compatible = "ti,omap4-i2c";
reg = <0x48070000 0x100>;
--
2.10.2
--
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^ permalink raw reply related
* [RFC 5/6] ARM: dts: dra7: add vivante for bb2d module
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robert Nelson,
Julien, Nishanth Menon, Tomi Valkeinen
In-Reply-To: <20161118024436.13447-1-robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Robert Nelson <robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Julien <jboulnois-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
CC: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
CC: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/dra7.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 43488b6..22bd0a5 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -960,7 +960,7 @@
};
bb2d: bb2d@59000000 {
- compatible = "ti,dra7-bb2d";
+ compatible = "ti,dra7-bb2d","vivante,gc";
reg = <0x59000000 0x0700>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
ti,hwmods = "bb2d";
--
2.10.2
--
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^ permalink raw reply related
* [RFC 6/6] ARM: dts: am57xx-beagle-x15-common: enable etnaviv
From: Robert Nelson @ 2016-11-18 2:44 UTC (permalink / raw)
To: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: linux-omap-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Robert Nelson,
Julien, Nishanth Menon, Tomi Valkeinen
In-Reply-To: <20161118024436.13447-1-robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Robert Nelson <robertcnelson-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Julien <jboulnois-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
CC: Nishanth Menon <nm-l0cyMroinI0@public.gmane.org>
CC: Tomi Valkeinen <tomi.valkeinen-l0cyMroinI0@public.gmane.org>
CC: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
index 6df7829..3bc47be 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
+++ b/arch/arm/boot/dts/am57xx-beagle-x15-common.dtsi
@@ -97,6 +97,12 @@
#cooling-cells = <2>;
};
+ gpu-subsystem {
+ compatible = "ti,gc320-gpu-subsystem";
+ cores = <&bb2d>;
+ status = "okay";
+ };
+
hdmi0: connector {
compatible = "hdmi-connector";
label = "hdmi";
@@ -190,6 +196,11 @@
>;
};
};
+
+&bb2d {
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
clock-frequency = <400000>;
--
2.10.2
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