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* Re: fsldma: t4240qds: drop "SG" CAP for DMA3
From: Scott Wood @ 2016-11-22  7:25 UTC (permalink / raw)
  To: yanjiang.jin-CWA4WttNNZF54TAoqtyWWQ
  Cc: mark.rutland-5wv7dgnIgG8, benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r,
	leoli-KZfg59tc24xl57MIdRCFDg, zw-aYo+Mbtxn2uXDw4h08c5KA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	jinyanjiang-Re5JQEeQqe8AvxtiuMwx3w,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	dmaengine-u79uwXL29TY76Z2rM5mHXA,
	linuxppc-dev-uLR06cmDAlY/bJ5BZ2RsiQ, yao.yuan-3arQi8VN3Tc,
	hongbo.zhang-3arQi8VN3Tc
In-Reply-To: <1479703969-15413-1-git-send-email-yanjiang.jin-CWA4WttNNZF54TAoqtyWWQ@public.gmane.org>

On Mon, Nov 21, 2016 at 12:52:49PM +0800, yanjiang.jin-CWA4WttNNZF54TAoqtyWWQ@public.gmane.org wrote:
> From: Yanjiang Jin <yanjiang.jin-CWA4WttNNZF54TAoqtyWWQ@public.gmane.org>
> 
> T4240QDS DMA controller uses the external DMA control signals to start or
> restart a paused DMA transfer, acknowledge a DMA transfer in progress and
> also indicates a transfer completion.
> "scatterlist copy" depends on these signals.

How specifically does sg depend on these signals?

What about chips other than t4240?

> But as "T4240 Reference Manual" shown:
> "The external DMA control signals are available on DMA1 and DMA2. They are
>  not supported by DMA3."
> 
> So add an of_node property "fsl,external-dma-control-signals" to only DMA1
> and DMA2, it can prevent DMA3 from doing DMA_SG operations. Else we would
> get the below errors during doing dmatest:
> 
> modprobe dmatest run=1 iterations=42
> 
> dmatest: Started 1 threads using dma2chan0
> fsl-elo-dma ffe102300.dma: chan0: Transfer Error!
> fsl-elo-dma ffe102300.dma: chan0: irq: unhandled sr 0x00000080
> dmatest: dma2chan0-sg0: dstbuf[0x3954] not copied! Expected d8, got 2b
> ........................
> dmatest: dma2chan7-sg0: dstbuf[0x1c51] not copied! Expected df, got 2e
> dmatest: dma2chan7-sg0: 1301 errors suppressed
> dmatest: dma2chan7-sg0: result #42: 'data error' with
> src_off=0xf21 dst_off=0x1c32 len=0x535 (1333)
> dmatest: dma2chan7-sg0: summary 42 tests, 42 failures 2952 iops 23968 KB/s
> 
> Signed-off-by: Yanjiang Jin <yanjiang.jin-CWA4WttNNZF54TAoqtyWWQ@public.gmane.org>
> ---
>  arch/powerpc/boot/dts/fsl/t4240si-post.dtsi |  6 ++++++
>  drivers/dma/fsldma.c                        | 11 +++++++++--
>  2 files changed, 15 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> index 68c4ead..155997d 100644
> --- a/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> +++ b/arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
> @@ -1029,7 +1029,13 @@
>  	};
>  
>  /include/ "elo3-dma-0.dtsi"
> +	dma@100300 {
> +		fsl,external-dma-control-signals;
> +	};
>  /include/ "elo3-dma-1.dtsi"
> +	dma@101300 {
> +		fsl,external-dma-control-signals;
> +	};
>  /include/ "elo3-dma-2.dtsi"
>  
>  /include/ "qoriq-espi-0.dtsi"

Where is the binding for this property?

> diff --git a/drivers/dma/fsldma.c b/drivers/dma/fsldma.c

The device tree update should be a separate patch from the driver, as
they would likely be merged via different trees.

> index 51c75bf..f7054f4 100644
> --- a/drivers/dma/fsldma.c
> +++ b/drivers/dma/fsldma.c
> @@ -1354,12 +1354,19 @@ static int fsldma_of_probe(struct platform_device *op)
>  	fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
>  
>  	dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
> -	dma_cap_set(DMA_SG, fdev->common.cap_mask);
> +
>  	dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
> +
> +	if (of_get_property(op->dev.of_node,
> +		"fsl,external-dma-control-signals", NULL)) {
> +		dma_cap_set(DMA_SG, fdev->common.cap_mask);
> +		fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
> +	} else
> +		dma_cap_clear(DMA_SG, fdev->common.cap_mask);

This indentation is not very readable (continuation line aligned with
if-body).

How about:

	if (of_property_read_bool(op->dev.of_node,
				  "fsl,external-dma-control-signals")) {
		dma_cap_set(...);
		...
	} else {
		dma_cap_clear(...);
	}

Shortening the property name would also help (e.g. "fsl,dma-ext-ctrl").

I assume nothing bad will happen (other than performance loss) if the
updated driver is used with an existing device tree, and thus none of the
channels get DMA_SG?

Is there any need to explicitly clear the capablitity in the else path? 
Wouldn't it be clear by default?

-Scott
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* Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets
From: Vivek Gautam @ 2016-11-22  7:47 UTC (permalink / raw)
  To: Kishon Vijay Abraham I
  Cc: robh+dt, Mark Rutland,
	devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAFp+6iGMp9pkt5NVTG9f-xjF5VOmj3Om5ngvMboyjdcR94Bhag-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>

Hi Kishon,


On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
<vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> Hi Kishon,
>

>>> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
>>> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
>>> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };

>> you can have a separate reg map for each lane and all these can come from dt.
>
> The idea is to avoid the any child nodes for lanes. So, we have the complete
> ioremaped region and these offsets to tx, rx and pcs blocks.

I don't see benefits in using regmap for different lanes.
Do you see benefits in replacing a bunch of readl()/writel() with
regmap_read()/regmap_update_bits()/regmap_write() ?

I can as well use separate 'reg' values for each lanes, and have the offsets
come from dt. Something like below :

 - reg: array of offset and length of the PHY register sets.
       at index 0: offset and length of register set for PHY common
                   serdes block.
       from index 1 - N: offset and length of register set for each lane,
                         for N number of phy lanes (ports).
 - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.

Example:
       pcie_phy: pciephy@34000 {
               compatible = "qcom,msm8996-qmp-pcie-phy";
               reg = <0x034000 0x48f>,
                       <0x035000 5bf>,
                       <0x036000 5bf>,
                       <0x037000 5bf>;
                                       /* tx, rx, pcs */
               lane-offsets = <0x0 0x200 0x400>;


Does this look OK ? Or should i use regmap only ?


Thanks
Vivek
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a Linux Foundation Collaborative Project
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* [PATCH 0/6] add hisilicon reset
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao

Add reset-hi3660.c
Update reset-hi6220 as well
reset.c is shared by reset-hi3660.c and reset-hi6220.c
Change hi6220.dtsi accordingly

Zhangfei Gao (6):
  reset: hisilicon: add reset core
  dt-bindings: Document the hi3660 reset bindings
  reset: hisilicon: add reset-hi3660
  dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
  reset: hisilicon: Use new driver reset-hi6222
  arm64: dts: hi6220: update reset node according to reset-hi6220.c

 .../bindings/reset/hisilicon,hi3660-reset.txt      |  42 ++++++
 .../bindings/reset/hisilicon,hi6220-reset.txt      |  14 +-
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi          |  20 ++-
 drivers/reset/Makefile                             |   2 +-
 drivers/reset/hisilicon/Kconfig                    |   7 +
 drivers/reset/hisilicon/Makefile                   |   4 +-
 drivers/reset/hisilicon/hi6220_reset.c             | 157 ---------------------
 drivers/reset/hisilicon/reset-hi3660.c             |  78 ++++++++++
 drivers/reset/hisilicon/reset-hi6220.c             | 123 ++++++++++++++++
 drivers/reset/hisilicon/reset.c                    | 108 ++++++++++++++
 drivers/reset/hisilicon/reset.h                    |  37 +++++
 include/dt-bindings/reset/hisi,hi3660-resets.h     |  38 +++++
 include/dt-bindings/reset/hisi,hi6220-resets.h     | 130 ++++++++---------
 13 files changed, 527 insertions(+), 233 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
 delete mode 100644 drivers/reset/hisilicon/hi6220_reset.c
 create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
 create mode 100644 drivers/reset/hisilicon/reset-hi6220.c
 create mode 100644 drivers/reset/hisilicon/reset.c
 create mode 100644 drivers/reset/hisilicon/reset.h
 create mode 100644 include/dt-bindings/reset/hisi,hi3660-resets.h

-- 
2.7.4

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* [PATCH 1/6] reset: hisilicon: add reset core
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

reset.c will be shared by hisilicon chips like hi3660 and hi6220

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/reset/Makefile           |   2 +-
 drivers/reset/hisilicon/Makefile |   1 +
 drivers/reset/hisilicon/reset.c  | 108 +++++++++++++++++++++++++++++++++++++++
 drivers/reset/hisilicon/reset.h  |  37 ++++++++++++++
 4 files changed, 147 insertions(+), 1 deletion(-)
 create mode 100644 drivers/reset/hisilicon/reset.c
 create mode 100644 drivers/reset/hisilicon/reset.h

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index bbe7026..7e3dc4e 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -1,8 +1,8 @@
 obj-y += core.o
-obj-y += hisilicon/
 obj-$(CONFIG_ARCH_STI) += sti/
 obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
 obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index c932f86..df511f5 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1 +1,2 @@
+obj-y	+= reset.o
 obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/reset.c b/drivers/reset/hisilicon/reset.c
new file mode 100644
index 0000000..c4971c9
--- /dev/null
+++ b/drivers/reset/hisilicon/reset.c
@@ -0,0 +1,108 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <linux/types.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+
+#include "reset.h"
+
+struct hisi_reset_controller {
+	struct reset_controller_dev rst;
+	const struct hisi_reset_channel_data *channels;
+	struct regmap *map;
+};
+
+#define to_hisi_reset_controller(_rst) \
+	container_of(_rst, struct hisi_reset_controller, rst)
+
+static int hisi_reset_program_hw(struct reset_controller_dev *rcdev,
+				 unsigned long idx, bool assert)
+{
+	struct hisi_reset_controller *rc = to_hisi_reset_controller(rcdev);
+	const struct hisi_reset_channel_data *ch;
+
+	if (idx >= rcdev->nr_resets)
+		return -EINVAL;
+
+	ch = &rc->channels[idx];
+
+	if (assert)
+		return regmap_write(rc->map, ch->enable.reg,
+				    GENMASK(ch->enable.msb, ch->enable.lsb));
+	else
+		return regmap_write(rc->map, ch->disable.reg,
+				    GENMASK(ch->disable.msb, ch->disable.lsb));
+}
+
+static int hisi_reset_assert(struct reset_controller_dev *rcdev,
+			     unsigned long idx)
+{
+	return hisi_reset_program_hw(rcdev, idx, true);
+}
+
+static int hisi_reset_deassert(struct reset_controller_dev *rcdev,
+			       unsigned long idx)
+{
+	return hisi_reset_program_hw(rcdev, idx, false);
+}
+
+static int hisi_reset_dev(struct reset_controller_dev *rcdev,
+			  unsigned long idx)
+{
+	int err;
+
+	err = hisi_reset_assert(rcdev, idx);
+	if (err)
+		return err;
+
+	return hisi_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops hisi_reset_ops = {
+	.reset    = hisi_reset_dev,
+	.assert   = hisi_reset_assert,
+	.deassert = hisi_reset_deassert,
+};
+
+int hisi_reset_probe(struct platform_device *pdev)
+{
+	struct hisi_reset_controller *rc;
+	struct device_node *np = pdev->dev.of_node;
+	struct hisi_reset_controller_data *d;
+	struct device *dev = &pdev->dev;
+	const struct of_device_id *match;
+
+	match = of_match_device(dev->driver->of_match_table, dev);
+	if (!match || !match->data)
+		return -EINVAL;
+
+	d = (struct hisi_reset_controller_data *)match->data;
+	rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+	if (!rc)
+		return -ENOMEM;
+
+	rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
+	if (IS_ERR(rc->map)) {
+		dev_err(dev, "failed to get hisi,rst-syscon\n");
+		return PTR_ERR(rc->map);
+	}
+
+	rc->rst.ops = &hisi_reset_ops,
+	rc->rst.of_node = np;
+	rc->rst.nr_resets = d->nr_channels;
+	rc->channels = d->channels;
+
+	return reset_controller_register(&rc->rst);
+}
+EXPORT_SYMBOL_GPL(hisi_reset_probe);
diff --git a/drivers/reset/hisilicon/reset.h b/drivers/reset/hisilicon/reset.h
new file mode 100644
index 0000000..77259ee
--- /dev/null
+++ b/drivers/reset/hisilicon/reset.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __HISILICON_RESET_H
+#define __HISILICON_RESET_H
+
+#include <linux/device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+/* reset separated register offset is 0x4 */
+#define HISI_RST_SEP(off, bit)					\
+	{ .enable	= REG_FIELD(off, bit, bit),		\
+	  .disable	= REG_FIELD(off + 0x4, bit, bit),	\
+	  .status	= REG_FIELD(off + 0x8, bit, bit), }
+
+struct hisi_reset_channel_data {
+	struct reg_field enable;
+	struct reg_field disable;
+	struct reg_field status;
+};
+
+struct hisi_reset_controller_data {
+	int nr_channels;
+	const struct hisi_reset_channel_data *channels;
+};
+
+int hisi_reset_probe(struct platform_device *pdev);
+
+#endif /* __HISILICON_RESET_H */
-- 
2.7.4

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* [PATCH 2/6] dt-bindings: Document the hi3660 reset bindings
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Add DT bindings documentation for hi3660 SoC reset controller.

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 .../bindings/reset/hisilicon,hi3660-reset.txt      | 42 ++++++++++++++++++++++
 1 file changed, 42 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt

diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
new file mode 100644
index 0000000..20e03a8
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -0,0 +1,42 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi3660 SoC.
+
+Required properties:
+- compatible: should be one of the following:
+  - "hisilicon,hi3660-reset-crgctrl : reset control for peripherals in crgctrl.
+  - "hisilicon,hi3660-reset-iomcu : reset control for peripherals in iomcu.
+- hisi,rst-syscon: phandle of the reset's syscon.
+- #reset-cells: 1, see below
+
+Example:
+	crg_ctrl: crg_ctrl@fff35000 {
+		compatible = "hisilicon,hi3660-crgctrl", "syscon";
+		reg = <0x0 0xfff35000 0x0 0x1000>;
+		#clock-cells = <1>;
+	};
+
+	crg_rst: crg_rst_controller {
+		compatible = "hisilicon,hi3660-reset-crgctrl";
+		#reset-cells = <1>;
+		hisi,rst-syscon = <&crg_ctrl>;
+	};
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+        ufs: ufs@..... {
+                ...
+		resets = <&crg_rst HI3660_RST_UFS>,
+			 <&crg_rst HI3660_RST_UFS_ASSERT>;
+		reset-names = "rst", "assert";
+                ...
+        };
+
+The index could be found in <dt-bindings/reset/hisi,hi3660-resets.h>.
-- 
2.7.4

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* [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Add hi3660 reset driver based on common reset.c

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/reset/hisilicon/Kconfig                |  7 +++
 drivers/reset/hisilicon/Makefile               |  1 +
 drivers/reset/hisilicon/reset-hi3660.c         | 78 ++++++++++++++++++++++++++
 include/dt-bindings/reset/hisi,hi3660-resets.h | 38 +++++++++++++
 4 files changed, 124 insertions(+)
 create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
 create mode 100644 include/dt-bindings/reset/hisi,hi3660-resets.h

diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
index 1ff8b0c..10134dc 100644
--- a/drivers/reset/hisilicon/Kconfig
+++ b/drivers/reset/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_RESET_HI3660
+	tristate "Hi3660 Reset Driver"
+	depends on ARCH_HISI || COMPILE_TEST
+	default ARCH_HISI
+	help
+	  Build the Hisilicon Hi3660 reset driver.
+
 config COMMON_RESET_HI6220
 	tristate "Hi6220 Reset Driver"
 	depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index df511f5..57e9893 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1,2 +1,3 @@
 obj-y	+= reset.o
+obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
 obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c
new file mode 100644
index 0000000..7da3153
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi3660.c
@@ -0,0 +1,78 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/reset/hisi,hi3660-resets.h>
+
+#include "reset.h"
+
+static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
+	[HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
+	[HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
+	[HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
+	[HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
+};
+
+static struct hisi_reset_controller_data hi3660_iomcu_controller = {
+	.nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
+	.channels = hi3660_iomcu_rst,
+};
+
+static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
+	[HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
+	[HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
+	[HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
+	[HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
+	[HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
+	[HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
+	[HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
+	[HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
+	[HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
+	[HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
+	[HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
+	[HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
+	[HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
+	[HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
+	[HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
+};
+
+static struct hisi_reset_controller_data hi3660_crgctrl_controller = {
+	.nr_channels = ARRAY_SIZE(hi3660_crgctrl_rst),
+	.channels = hi3660_crgctrl_rst,
+};
+
+static const struct of_device_id hi3660_reset_match[] = {
+	{ .compatible = "hisilicon,hi3660-reset-crgctrl",
+	  .data = &hi3660_crgctrl_controller, },
+	{ .compatible = "hisilicon,hi3660-reset-iomcu",
+	  .data = &hi3660_iomcu_controller, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, hi3660_reset_match);
+
+static struct platform_driver hi3660_reset_driver = {
+	.probe = hisi_reset_probe,
+	.driver = {
+		.name = "reset-hi3660",
+		.of_match_table = hi3660_reset_match,
+	},
+};
+
+static int __init hi3660_reset_init(void)
+{
+	return platform_driver_register(&hi3660_reset_driver);
+}
+arch_initcall(hi3660_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi3660-reset");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Reset Driver");
diff --git a/include/dt-bindings/reset/hisi,hi3660-resets.h b/include/dt-bindings/reset/hisi,hi3660-resets.h
new file mode 100644
index 0000000..a65f382
--- /dev/null
+++ b/include/dt-bindings/reset/hisi,hi3660-resets.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI3660
+#define _DT_BINDINGS_RESET_CONTROLLER_HI3660
+
+/* reset in iomcu */
+#define HI3660_RST_I2C0		0
+#define HI3660_RST_I2C1		1
+#define HI3660_RST_I2C2		2
+#define HI3660_RST_I2C6		3
+
+
+/* reset in crgctrl */
+#define HI3660_RST_I2C3		0
+#define HI3660_RST_I2C4		1
+#define HI3660_RST_I2C7		2
+#define HI3660_RST_SD		3
+#define HI3660_RST_SDIO		4
+#define HI3660_RST_UFS		5
+#define HI3660_RST_UFS_ASSERT	6
+#define HI3660_RST_PCIE_SYS	7
+#define HI3660_RST_PCIE_PHY	8
+#define HI3660_RST_PCIE_BUS	9
+#define HI3660_RST_USB3OTG_PHY  10
+#define HI3660_RST_USB3OTG	11
+#define HI3660_RST_USB3OTG_32K	12
+#define HI3660_RST_USB3OTG_AHB	13
+#define HI3660_RST_USB3OTG_MUX	14
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI3660*/
-- 
2.7.4

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^ permalink raw reply related

* [PATCH 4/6] dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 .../devicetree/bindings/reset/hisilicon,hi6220-reset.txt   | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
index c25da39..6a864f3 100644
--- a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -9,10 +9,9 @@ hi6220 SoC.
 
 Required properties:
 - compatible: should be one of the following:
-  - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
-  - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
-- reg: should be register base and length as documented in the
-  datasheet
+  - "hisilicon,hi6220-reset-sysctrl" : For peripheral reset controller.
+  - "hisilicon,hi6220-reset-mediactrl" : For media reset controller.
+- hisi,rst-syscon: phandle of the reset's syscon.
 - #reset-cells: 1, see below
 
 Example:
@@ -20,7 +19,12 @@ sys_ctrl: sys_ctrl@f7030000 {
 	compatible = "hisilicon,hi6220-sysctrl", "syscon";
 	reg = <0x0 0xf7030000 0x0 0x2000>;
 	#clock-cells = <1>;
+};
+
+sys_ctrl_rst: sys_rst_controller {
+	compatible = "hisilicon,hi6220-reset-sysctrl";
 	#reset-cells = <1>;
+	hisi,rst-syscon = <&sys_ctrl>;
 };
 
 Specifying reset lines connected to IP modules
@@ -29,7 +33,7 @@ example:
 
         uart1: serial@..... {
                 ...
-                resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
+                resets = <&sys_ctrl_rst PERIPH_RSTEN3_UART1>;
                 ...
         };
 
-- 
2.7.4

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^ permalink raw reply related

* [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Using new reset-hi6220 with common reset.c
And keeps the same reset define

dts hi6220.c should be updated with new node sys_ctrl_rst
Solving potential issue of sys_ctrl can not be used as clock and reset
at the same time.

sys_ctrl: sys_ctrl@f7030000 {
	compatible = "hisilicon,hi6220-sysctrl", "syscon";
	reg = <0x0 0xf7030000 0x0 0x2000>;
	#clock-cells = <1>;
};

sys_ctrl_rst: sys_rst_controller {
	compatible = "hisilicon,hi6220-reset-sysctrl";
	#reset-cells = <1>;
	hisi,rst-syscon = <&sys_ctrl>;
};

uart1: serial@..... {
        ...
        resets = <&sys_ctrl_rst PERIPH_RSTEN3_UART1>;
        ...
};

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 drivers/reset/hisilicon/Makefile               |   2 +-
 drivers/reset/hisilicon/hi6220_reset.c         | 157 -------------------------
 drivers/reset/hisilicon/reset-hi6220.c         | 123 +++++++++++++++++++
 include/dt-bindings/reset/hisi,hi6220-resets.h | 130 ++++++++++----------
 4 files changed, 190 insertions(+), 222 deletions(-)
 delete mode 100644 drivers/reset/hisilicon/hi6220_reset.c
 create mode 100644 drivers/reset/hisilicon/reset-hi6220.c

diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index 57e9893..caddac1 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1,3 +1,3 @@
 obj-y	+= reset.o
 obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
-obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
+obj-$(CONFIG_COMMON_RESET_HI6220) += reset-hi6220.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
deleted file mode 100644
index 35ce53e..0000000
--- a/drivers/reset/hisilicon/hi6220_reset.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Hisilicon Hi6220 reset controller driver
- *
- * Copyright (c) 2016 Linaro Limited.
- * Copyright (c) 2015-2016 Hisilicon Limited.
- *
- * Author: Feng Chen <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#include <linux/io.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/regmap.h>
-#include <linux/mfd/syscon.h>
-#include <linux/reset-controller.h>
-#include <linux/reset.h>
-#include <linux/platform_device.h>
-
-#define PERIPH_ASSERT_OFFSET      0x300
-#define PERIPH_DEASSERT_OFFSET    0x304
-#define PERIPH_MAX_INDEX          0x509
-
-#define SC_MEDIA_RSTEN            0x052C
-#define SC_MEDIA_RSTDIS           0x0530
-#define MEDIA_MAX_INDEX           8
-
-#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
-
-enum hi6220_reset_ctrl_type {
-	PERIPHERAL,
-	MEDIA,
-};
-
-struct hi6220_reset_data {
-	struct reset_controller_dev rc_dev;
-	struct regmap *regmap;
-};
-
-static int hi6220_peripheral_assert(struct reset_controller_dev *rc_dev,
-				    unsigned long idx)
-{
-	struct hi6220_reset_data *data = to_reset_data(rc_dev);
-	struct regmap *regmap = data->regmap;
-	u32 bank = idx >> 8;
-	u32 offset = idx & 0xff;
-	u32 reg = PERIPH_ASSERT_OFFSET + bank * 0x10;
-
-	return regmap_write(regmap, reg, BIT(offset));
-}
-
-static int hi6220_peripheral_deassert(struct reset_controller_dev *rc_dev,
-				      unsigned long idx)
-{
-	struct hi6220_reset_data *data = to_reset_data(rc_dev);
-	struct regmap *regmap = data->regmap;
-	u32 bank = idx >> 8;
-	u32 offset = idx & 0xff;
-	u32 reg = PERIPH_DEASSERT_OFFSET + bank * 0x10;
-
-	return regmap_write(regmap, reg, BIT(offset));
-}
-
-static const struct reset_control_ops hi6220_peripheral_reset_ops = {
-	.assert = hi6220_peripheral_assert,
-	.deassert = hi6220_peripheral_deassert,
-};
-
-static int hi6220_media_assert(struct reset_controller_dev *rc_dev,
-			       unsigned long idx)
-{
-	struct hi6220_reset_data *data = to_reset_data(rc_dev);
-	struct regmap *regmap = data->regmap;
-
-	return regmap_write(regmap, SC_MEDIA_RSTEN, BIT(idx));
-}
-
-static int hi6220_media_deassert(struct reset_controller_dev *rc_dev,
-				 unsigned long idx)
-{
-	struct hi6220_reset_data *data = to_reset_data(rc_dev);
-	struct regmap *regmap = data->regmap;
-
-	return regmap_write(regmap, SC_MEDIA_RSTDIS, BIT(idx));
-}
-
-static const struct reset_control_ops hi6220_media_reset_ops = {
-	.assert = hi6220_media_assert,
-	.deassert = hi6220_media_deassert,
-};
-
-static int hi6220_reset_probe(struct platform_device *pdev)
-{
-	struct device_node *np = pdev->dev.of_node;
-	struct device *dev = &pdev->dev;
-	enum hi6220_reset_ctrl_type type;
-	struct hi6220_reset_data *data;
-	struct regmap *regmap;
-
-	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
-	if (!data)
-		return -ENOMEM;
-
-	type = (enum hi6220_reset_ctrl_type)of_device_get_match_data(dev);
-
-	regmap = syscon_node_to_regmap(np);
-	if (IS_ERR(regmap)) {
-		dev_err(dev, "failed to get reset controller regmap\n");
-		return PTR_ERR(regmap);
-	}
-
-	data->regmap = regmap;
-	data->rc_dev.of_node = np;
-	if (type == MEDIA) {
-		data->rc_dev.ops = &hi6220_media_reset_ops;
-		data->rc_dev.nr_resets = MEDIA_MAX_INDEX;
-	} else {
-		data->rc_dev.ops = &hi6220_peripheral_reset_ops;
-		data->rc_dev.nr_resets = PERIPH_MAX_INDEX;
-	}
-
-	return reset_controller_register(&data->rc_dev);
-}
-
-static const struct of_device_id hi6220_reset_match[] = {
-	{
-		.compatible = "hisilicon,hi6220-sysctrl",
-		.data = (void *)PERIPHERAL,
-	},
-	{
-		.compatible = "hisilicon,hi6220-mediactrl",
-		.data = (void *)MEDIA,
-	},
-	{ /* sentinel */ },
-};
-MODULE_DEVICE_TABLE(of, hi6220_reset_match);
-
-static struct platform_driver hi6220_reset_driver = {
-	.probe = hi6220_reset_probe,
-	.driver = {
-		.name = "reset-hi6220",
-		.of_match_table = hi6220_reset_match,
-	},
-};
-
-static int __init hi6220_reset_init(void)
-{
-	return platform_driver_register(&hi6220_reset_driver);
-}
-
-postcore_initcall(hi6220_reset_init);
diff --git a/drivers/reset/hisilicon/reset-hi6220.c b/drivers/reset/hisilicon/reset-hi6220.c
new file mode 100644
index 0000000..a2a64ae
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi6220.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <dt-bindings/reset/hisi,hi6220-resets.h>
+
+#include "reset.h"
+
+static const struct hisi_reset_channel_data hi6220_media_rst[] = {
+	[MEDIA_G3D] = HISI_RST_SEP(0x52c, 0),
+	[MEDIA_CODEC_VPU] = HISI_RST_SEP(0x52c, 2),
+	[MEDIA_CODEC_JPEG] = HISI_RST_SEP(0x52c, 3),
+	[MEDIA_ISP] = HISI_RST_SEP(0x52c, 4),
+	[MEDIA_ADE] = HISI_RST_SEP(0x52c, 5),
+	[MEDIA_MMU] = HISI_RST_SEP(0x52c, 6),
+	[MEDIA_XG2RAM1] = HISI_RST_SEP(0x52c, 7),
+};
+
+static struct hisi_reset_controller_data hi6220_media_controller = {
+	.nr_channels = ARRAY_SIZE(hi6220_media_rst),
+	.channels = hi6220_media_rst,
+};
+
+static const struct hisi_reset_channel_data hi6220_sysctrl_rst[] = {
+	[PERIPH_RSTDIS0_MMC0] = HISI_RST_SEP(0x300, 0),
+	[PERIPH_RSTDIS0_MMC1] = HISI_RST_SEP(0x300, 1),
+	[PERIPH_RSTDIS0_MMC2] = HISI_RST_SEP(0x300, 2),
+	[PERIPH_RSTDIS0_NANDC] = HISI_RST_SEP(0x300, 3),
+	[PERIPH_RSTDIS0_USBOTG_BUS] = HISI_RST_SEP(0x300, 4),
+	[PERIPH_RSTDIS0_POR_PICOPHY] = HISI_RST_SEP(0x300, 5),
+	[PERIPH_RSTDIS0_USBOTG] = HISI_RST_SEP(0x300, 6),
+	[PERIPH_RSTDIS0_USBOTG_32K] = HISI_RST_SEP(0x300, 7),
+	[PERIPH_RSTDIS1_HIFI] = HISI_RST_SEP(0x310, 0),
+	[PERIPH_RSTDIS1_DIGACODEC] = HISI_RST_SEP(0x310, 5),
+	[PERIPH_RSTEN2_IPF] = HISI_RST_SEP(0x320, 0),
+	[PERIPH_RSTEN2_SOCP] = HISI_RST_SEP(0x320, 1),
+	[PERIPH_RSTEN2_DMAC] = HISI_RST_SEP(0x320, 2),
+	[PERIPH_RSTEN2_SECENG] = HISI_RST_SEP(0x320, 3),
+	[PERIPH_RSTEN2_ABB] = HISI_RST_SEP(0x320, 4),
+	[PERIPH_RSTEN2_HPM0] = HISI_RST_SEP(0x320, 5),
+	[PERIPH_RSTEN2_HPM1] = HISI_RST_SEP(0x320, 6),
+	[PERIPH_RSTEN2_HPM2] = HISI_RST_SEP(0x320, 7),
+	[PERIPH_RSTEN2_HPM3] = HISI_RST_SEP(0x320, 8),
+	[PERIPH_RSTEN3_CSSYS] = HISI_RST_SEP(0x330, 0),
+	[PERIPH_RSTEN3_I2C0] = HISI_RST_SEP(0x330, 1),
+	[PERIPH_RSTEN3_I2C1] = HISI_RST_SEP(0x330, 2),
+	[PERIPH_RSTEN3_I2C2] = HISI_RST_SEP(0x330, 3),
+	[PERIPH_RSTEN3_I2C3] = HISI_RST_SEP(0x330, 4),
+	[PERIPH_RSTEN3_UART1] = HISI_RST_SEP(0x330, 5),
+	[PERIPH_RSTEN3_UART2] = HISI_RST_SEP(0x330, 6),
+	[PERIPH_RSTEN3_UART3] = HISI_RST_SEP(0x330, 7),
+	[PERIPH_RSTEN3_UART4] = HISI_RST_SEP(0x330, 8),
+	[PERIPH_RSTEN3_SSP] = HISI_RST_SEP(0x330, 9),
+	[PERIPH_RSTEN3_PWM] = HISI_RST_SEP(0x330, 10),
+	[PERIPH_RSTEN3_BLPWM] = HISI_RST_SEP(0x330, 11),
+	[PERIPH_RSTEN3_TSENSOR] = HISI_RST_SEP(0x330, 12),
+	[PERIPH_RSTEN3_DAPB] = HISI_RST_SEP(0x330, 18),
+	[PERIPH_RSTEN3_HKADC] = HISI_RST_SEP(0x330, 19),
+	[PERIPH_RSTEN3_CODEC_SSI] = HISI_RST_SEP(0x330, 20),
+	[PERIPH_RSTEN8_RS0] = HISI_RST_SEP(0x340, 0),
+	[PERIPH_RSTEN8_RS2] = HISI_RST_SEP(0x340, 1),
+	[PERIPH_RSTEN8_RS3] = HISI_RST_SEP(0x340, 2),
+	[PERIPH_RSTEN8_MS0] = HISI_RST_SEP(0x340, 3),
+	[PERIPH_RSTEN8_MS2] = HISI_RST_SEP(0x340, 5),
+	[PERIPH_RSTEN8_XG2RAM0] = HISI_RST_SEP(0x340, 6),
+	[PERIPH_RSTEN8_X2SRAM_TZMA] = HISI_RST_SEP(0x340, 7),
+	[PERIPH_RSTEN8_SRAM] = HISI_RST_SEP(0x340, 8),
+	[PERIPH_RSTEN8_HARQ] = HISI_RST_SEP(0x340, 10),
+	[PERIPH_RSTEN8_DDRC] = HISI_RST_SEP(0x340, 12),
+	[PERIPH_RSTEN8_DDRC_APB] = HISI_RST_SEP(0x340, 13),
+	[PERIPH_RSTEN8_DDRPACK_APB] = HISI_RST_SEP(0x340, 14),
+	[PERIPH_RSTEN8_DDRT] = HISI_RST_SEP(0x340, 17),
+	[PERIPH_RSDIST9_CARM_DAP] = HISI_RST_SEP(0x350, 0),
+	[PERIPH_RSDIST9_CARM_ATB] = HISI_RST_SEP(0x350, 1),
+	[PERIPH_RSDIST9_CARM_LBUS] = HISI_RST_SEP(0x350, 2),
+	[PERIPH_RSDIST9_CARM_POR] = HISI_RST_SEP(0x350, 3),
+	[PERIPH_RSDIST9_CARM_CORE] = HISI_RST_SEP(0x350, 4),
+	[PERIPH_RSDIST9_CARM_DBG] = HISI_RST_SEP(0x350, 5),
+	[PERIPH_RSDIST9_CARM_L2] = HISI_RST_SEP(0x350, 6),
+	[PERIPH_RSDIST9_CARM_SOCDBG] = HISI_RST_SEP(0x350, 7),
+	[PERIPH_RSDIST9_CARM_ETM] = HISI_RST_SEP(0x350, 8),
+};
+
+static struct hisi_reset_controller_data hi6220_sysctrl_controller = {
+	.nr_channels = ARRAY_SIZE(hi6220_sysctrl_rst),
+	.channels = hi6220_sysctrl_rst,
+};
+
+static const struct of_device_id hi6220_reset_match[] = {
+	{ .compatible = "hisilicon,hi6220-reset-sysctrl",
+	  .data = &hi6220_sysctrl_controller, },
+	{ .compatible = "hisilicon,hi6220-reset-mediactrl",
+	  .data = &hi6220_media_controller, },
+	{},
+};
+MODULE_DEVICE_TABLE(of, hi6220_reset_match);
+
+static struct platform_driver hi6220_reset_driver = {
+	.probe = hisi_reset_probe,
+	.driver = {
+		.name = "reset-hi6220",
+		.of_match_table = hi6220_reset_match,
+	},
+};
+
+static int __init hi6220_reset_init(void)
+{
+	return platform_driver_register(&hi6220_reset_driver);
+}
+arch_initcall(hi6220_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi6220-reset");
+MODULE_DESCRIPTION("HiSilicon hi6220 Reset Driver");
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
index 322ec53..837f1a1 100644
--- a/include/dt-bindings/reset/hisi,hi6220-resets.h
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -5,71 +5,73 @@
 #ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
 #define _DT_BINDINGS_RESET_CONTROLLER_HI6220
 
-#define PERIPH_RSTDIS0_MMC0             0x000
-#define PERIPH_RSTDIS0_MMC1             0x001
-#define PERIPH_RSTDIS0_MMC2             0x002
-#define PERIPH_RSTDIS0_NANDC            0x003
-#define PERIPH_RSTDIS0_USBOTG_BUS       0x004
-#define PERIPH_RSTDIS0_POR_PICOPHY      0x005
-#define PERIPH_RSTDIS0_USBOTG           0x006
-#define PERIPH_RSTDIS0_USBOTG_32K       0x007
-#define PERIPH_RSTDIS1_HIFI             0x100
-#define PERIPH_RSTDIS1_DIGACODEC        0x105
-#define PERIPH_RSTEN2_IPF               0x200
-#define PERIPH_RSTEN2_SOCP              0x201
-#define PERIPH_RSTEN2_DMAC              0x202
-#define PERIPH_RSTEN2_SECENG            0x203
-#define PERIPH_RSTEN2_ABB               0x204
-#define PERIPH_RSTEN2_HPM0              0x205
-#define PERIPH_RSTEN2_HPM1              0x206
-#define PERIPH_RSTEN2_HPM2              0x207
-#define PERIPH_RSTEN2_HPM3              0x208
-#define PERIPH_RSTEN3_CSSYS             0x300
-#define PERIPH_RSTEN3_I2C0              0x301
-#define PERIPH_RSTEN3_I2C1              0x302
-#define PERIPH_RSTEN3_I2C2              0x303
-#define PERIPH_RSTEN3_I2C3              0x304
-#define PERIPH_RSTEN3_UART1             0x305
-#define PERIPH_RSTEN3_UART2             0x306
-#define PERIPH_RSTEN3_UART3             0x307
-#define PERIPH_RSTEN3_UART4             0x308
-#define PERIPH_RSTEN3_SSP               0x309
-#define PERIPH_RSTEN3_PWM               0x30a
-#define PERIPH_RSTEN3_BLPWM             0x30b
-#define PERIPH_RSTEN3_TSENSOR           0x30c
-#define PERIPH_RSTEN3_DAPB              0x312
-#define PERIPH_RSTEN3_HKADC             0x313
-#define PERIPH_RSTEN3_CODEC_SSI         0x314
-#define PERIPH_RSTEN3_PMUSSI1           0x316
-#define PERIPH_RSTEN8_RS0               0x400
-#define PERIPH_RSTEN8_RS2               0x401
-#define PERIPH_RSTEN8_RS3               0x402
-#define PERIPH_RSTEN8_MS0               0x403
-#define PERIPH_RSTEN8_MS2               0x405
-#define PERIPH_RSTEN8_XG2RAM0           0x406
-#define PERIPH_RSTEN8_X2SRAM_TZMA       0x407
-#define PERIPH_RSTEN8_SRAM              0x408
-#define PERIPH_RSTEN8_HARQ              0x40a
-#define PERIPH_RSTEN8_DDRC              0x40c
-#define PERIPH_RSTEN8_DDRC_APB          0x40d
-#define PERIPH_RSTEN8_DDRPACK_APB       0x40e
-#define PERIPH_RSTEN8_DDRT              0x411
-#define PERIPH_RSDIST9_CARM_DAP         0x500
-#define PERIPH_RSDIST9_CARM_ATB         0x501
-#define PERIPH_RSDIST9_CARM_LBUS        0x502
-#define PERIPH_RSDIST9_CARM_POR         0x503
-#define PERIPH_RSDIST9_CARM_CORE        0x504
-#define PERIPH_RSDIST9_CARM_DBG         0x505
-#define PERIPH_RSDIST9_CARM_L2          0x506
-#define PERIPH_RSDIST9_CARM_SOCDBG      0x507
-#define PERIPH_RSDIST9_CARM_ETM         0x508
 
+/* reset in sysctrl */
+#define PERIPH_RSTDIS0_MMC0             0
+#define PERIPH_RSTDIS0_MMC1             1
+#define PERIPH_RSTDIS0_MMC2             2
+#define PERIPH_RSTDIS0_NANDC            3
+#define PERIPH_RSTDIS0_USBOTG_BUS       4
+#define PERIPH_RSTDIS0_POR_PICOPHY      5
+#define PERIPH_RSTDIS0_USBOTG           6
+#define PERIPH_RSTDIS0_USBOTG_32K       7
+#define PERIPH_RSTDIS1_HIFI             8
+#define PERIPH_RSTDIS1_DIGACODEC        9
+#define PERIPH_RSTEN2_IPF               10
+#define PERIPH_RSTEN2_SOCP              11
+#define PERIPH_RSTEN2_DMAC              12
+#define PERIPH_RSTEN2_SECENG            13
+#define PERIPH_RSTEN2_ABB               14
+#define PERIPH_RSTEN2_HPM0              15
+#define PERIPH_RSTEN2_HPM1              16
+#define PERIPH_RSTEN2_HPM2              17
+#define PERIPH_RSTEN2_HPM3              18
+#define PERIPH_RSTEN3_CSSYS             19
+#define PERIPH_RSTEN3_I2C0              20
+#define PERIPH_RSTEN3_I2C1              21
+#define PERIPH_RSTEN3_I2C2              22
+#define PERIPH_RSTEN3_I2C3              23
+#define PERIPH_RSTEN3_UART1             24
+#define PERIPH_RSTEN3_UART2             25
+#define PERIPH_RSTEN3_UART3             26
+#define PERIPH_RSTEN3_UART4             27
+#define PERIPH_RSTEN3_SSP               28
+#define PERIPH_RSTEN3_PWM               29
+#define PERIPH_RSTEN3_BLPWM             30
+#define PERIPH_RSTEN3_TSENSOR           31
+#define PERIPH_RSTEN3_DAPB              32
+#define PERIPH_RSTEN3_HKADC             33
+#define PERIPH_RSTEN3_CODEC_SSI         34
+#define PERIPH_RSTEN8_RS0               35
+#define PERIPH_RSTEN8_RS2               36
+#define PERIPH_RSTEN8_RS3               37
+#define PERIPH_RSTEN8_MS0               38
+#define PERIPH_RSTEN8_MS2               39
+#define PERIPH_RSTEN8_XG2RAM0           40
+#define PERIPH_RSTEN8_X2SRAM_TZMA       41
+#define PERIPH_RSTEN8_SRAM              42
+#define PERIPH_RSTEN8_HARQ              43
+#define PERIPH_RSTEN8_DDRC              44
+#define PERIPH_RSTEN8_DDRC_APB          45
+#define PERIPH_RSTEN8_DDRPACK_APB       46
+#define PERIPH_RSTEN8_DDRT              47
+#define PERIPH_RSDIST9_CARM_DAP         48
+#define PERIPH_RSDIST9_CARM_ATB         49
+#define PERIPH_RSDIST9_CARM_LBUS        50
+#define PERIPH_RSDIST9_CARM_POR         51
+#define PERIPH_RSDIST9_CARM_CORE        52
+#define PERIPH_RSDIST9_CARM_DBG         53
+#define PERIPH_RSDIST9_CARM_L2          54
+#define PERIPH_RSDIST9_CARM_SOCDBG      55
+#define PERIPH_RSDIST9_CARM_ETM         56
+
+/* reset in media */
 #define MEDIA_G3D                       0
-#define MEDIA_CODEC_VPU                 2
-#define MEDIA_CODEC_JPEG                3
-#define MEDIA_ISP                       4
-#define MEDIA_ADE                       5
-#define MEDIA_MMU                       6
-#define MEDIA_XG2RAM1                   7
+#define MEDIA_CODEC_VPU                 1
+#define MEDIA_CODEC_JPEG                2
+#define MEDIA_ISP                       3
+#define MEDIA_ADE                       4
+#define MEDIA_MMU                       5
+#define MEDIA_XG2RAM1                   6
 
 #endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
-- 
2.7.4

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^ permalink raw reply related

* [PATCH 6/6] arm64: dts: hi6220: update reset node according to reset-hi6220.c
From: Zhangfei Gao @ 2016-11-22  7:49 UTC (permalink / raw)
  To: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue
  Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Zhangfei Gao
In-Reply-To: <1479800961-6249-1-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
 arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 20 +++++++++++++++-----
 1 file changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 17839db..7918043 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -246,14 +246,24 @@
 			compatible = "hisilicon,hi6220-sysctrl", "syscon";
 			reg = <0x0 0xf7030000 0x0 0x2000>;
 			#clock-cells = <1>;
-			#reset-cells = <1>;
 		};
 
 		media_ctrl: media_ctrl@f4410000 {
 			compatible = "hisilicon,hi6220-mediactrl", "syscon";
 			reg = <0x0 0xf4410000 0x0 0x1000>;
 			#clock-cells = <1>;
+		};
+
+		sys_ctrl_rst: sys_rst_controller {
+			compatible = "hisilicon,hi6220-reset-sysctrl";
+			#reset-cells = <1>;
+			hisi,rst-syscon = <&sys_ctrl>;
+		};
+
+		media_ctrl_rst: media_rst_controller {
+			compatible = "hisilicon,hi6220-reset-mediactrl";
 			#reset-cells = <1>;
+			hisi,rst-syscon = <&media_ctrl>;
 		};
 
 		pm_ctrl: pm_ctrl@f7032000 {
@@ -771,7 +781,7 @@
 			interrupts = <0x0 0x48 0x4>;
 			clocks = <&sys_ctrl 2>, <&sys_ctrl 1>;
 			clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC0>;
+			resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC0>;
 			bus-width = <0x8>;
 			vmmc-supply = <&ldo19>;
 			pinctrl-names = "default";
@@ -794,7 +804,7 @@
 			#size-cells = <0x0>;
 			clocks = <&sys_ctrl 4>, <&sys_ctrl 3>;
 			clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC1>;
+			resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC1>;
 			vqmmc-supply = <&ldo7>;
 			vmmc-supply = <&ldo10>;
 			bus-width = <0x4>;
@@ -812,7 +822,7 @@
 			interrupts = <0x0 0x4a 0x4>;
 			clocks = <&sys_ctrl HI6220_MMC2_CIUCLK>, <&sys_ctrl HI6220_MMC2_CLK>;
 			clock-names = "ciu", "biu";
-			resets = <&sys_ctrl PERIPH_RSTDIS0_MMC2>;
+			resets = <&sys_ctrl_rst PERIPH_RSTDIS0_MMC2>;
 			bus-width = <0x4>;
 			broken-cd;
 			pinctrl-names = "default", "idle";
@@ -867,7 +877,7 @@
 			reg = <0x0 0xf4100000 0x0 0x7800>;
 			reg-names = "ade_base";
 			hisilicon,noc-syscon = <&medianoc_ade>;
-			resets = <&media_ctrl MEDIA_ADE>;
+			resets = <&media_ctrl_rst MEDIA_ADE>;
 			interrupts = <0 115 4>; /* ldi interrupt */
 
 			clocks = <&media_ctrl HI6220_ADE_CORE>,
-- 
2.7.4

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^ permalink raw reply related

* Re: [PATCH] ARM: dts: exynos: remove the cd-gpios property for eMMC of odroid-xu3/4
From: Andrzej Hajda @ 2016-11-22  7:51 UTC (permalink / raw)
  To: Jaehoon Chung, Krzysztof Kozlowski
  Cc: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA, kgene-DgEjT+Ai2ygdnm+yROfE0A,
	cw00.choi-Sze3O3UU22JBDgjK7y7TUQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8,
	will.deacon-5wv7dgnIgG8, m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ,
	jy0922.shim-Sze3O3UU22JBDgjK7y7TUQ
In-Reply-To: <9ecce088-b91d-d51a-5a19-33476961d2ea-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>

On 22.11.2016 02:24, Jaehoon Chung wrote:
> On 11/22/2016 02:06 AM, Krzysztof Kozlowski wrote:
>> On Mon, Nov 21, 2016 at 04:10:32PM +0900, Jaehoon Chung wrote:
>>> Odroid-xu3/4 didn't need to use the cd-gpios for detecting card.
>>> Because Host controller has the CDETECT register through SDx_CDN line.
>>> Host controller can know whether card is inserted or not with this
>>> register.
>>>
>>> When i have checked the Odroid-xu3/4, they are using CDETECT register.
>>> (Not using exteranl cd-gpio.)
>> Makes sense. Just one question: the sd0_cd pinctrl setting should stay,
>> right?
> Right, It needs to use SD0_CD function.
> I have tested on Odroid-XU3/XU4.
>
> Tested with the below cases.
>
> 1) On boot with SD-card (without eMMC)
> - Inserted eMMC : Detected
> - Removed eMMC : Detected
>
> 2) On boot with Sd-card (with eMMC)
> - Detected
>
> 3) On boot with eMMC 
> - Detected

I suspect that MMC device (or its parts) should be always awake to keep
working CDETECT register. With cd-gpio it should be possible to power it
off when unused but still having detection working, am I right? I am not
familiar enough with the code to be certain that it improves PM but it
could be the case.

My other question is about polling thread, original patch was developed
to avoid polling thread which caused occasional hangs, crashes and
unnecessary work. Since then lot of mmc code changed and I do not follow
these changes. So my question is if this patch will not re-enable polling?

Regards
Andrzej

>
> Best Regards,
> Jaehoon Chung
>
>> Best regards,
>> Krzysztof
>>
>>> Fixes: fb1aeedb61ad ("ARM: dts: add mmc detect gpio for exynos5422-odroidxu3")
>>> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>> ---
>>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 -
>>>  1 file changed, 1 deletion(-)
>>>
>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> index 9e63328..05b9afdd 100644
>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>> @@ -510,7 +510,6 @@
>>>  &mmc_0 {
>>>  	status = "okay";
>>>  	mmc-pwrseq = <&emmc_pwrseq>;
>>> -	cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
>>>  	card-detect-delay = <200>;
>>>  	samsung,dw-mshc-ciu-div = <3>;
>>>  	samsung,dw-mshc-sdr-timing = <0 4>;
>>> -- 
>>> 2.10.1
>>>
>>
>>
>
>

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^ permalink raw reply

* Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-22  8:13 UTC (permalink / raw)
  To: Jon Hunter, linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	swarren-3lzwWm7+Weoh9ZMKESR00Q,
	thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
  Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w,
	yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2d442ccc-c438-cf3a-24c4-032d6c906f26-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>


On Tuesday 22 November 2016 02:07 AM, Jon Hunter wrote:
> On 21/11/16 12:49, Laxman Dewangan wrote:
>> On Monday 21 November 2016 04:38 PM, Jon Hunter wrote:
>>>> I had a discussion with the ASIC on this and as per them
>>>>       1.8 V nominal is (1.62V, 1.98V)
>>>>       3.3 V nominal is (2.97V,3.63V)
>>>>
>>>> I am working with them to update the TRM document but we can assume that
>>>> this information will be there in TRM.
>>> My feeling is that if all use-cases today are using either 1.8V or 3.3V,
>>> then may be we should not worry about this and only support either 1.8V
>>> or 3.3V. I would be more in favour of supporting other voltages if there
>>> is a real need.
>> Sometimes, the regulator will not return exact 1.8V or 3.3V due to the
>> PMIC rail resolution. On such cases, it returns nearest voltage to 1.8V
>> or 3.3V.
>> That's why the PMIC resolution is considered through IO pad voltage
>> tolerances.
> Ok, gotcha. I can see that would be the case for when you call
> regulator_get_voltage() (ie. in the probe), but what about the notifier?
> I imagine that in the notifier, at least for the pre-change case, that
> the voltage is the target and not the actual. So I am wondering if we
> need to check for a range in the notifier?

I think I can use the fixed voltage 1.8V and 3.3V as the current PMIC 
does not have this issue.

If we come for some tolerance issue in future then we will review this part.
This way it will be simple for now to go ahead with simple implementation.
I am going to validate the IO rail voltage as 1800mV and 3300mV.


>>>>>> +    const struct pinctrl_pin_desc *pins_desc;
>>>>>> +    int num_pins_desc;
>>>>>> +};
>>>>>> +
>>>>>> +struct tegra_io_pads_regulator_info {
>>>>>> +    struct device *dev;
>>>>>> +    const struct tegra_io_pads_cfg_info *pads_cfg;
>>>>>> +    struct regulator *regulator;
>>>>>> +    struct notifier_block regulator_nb;
>>>>>> +};
>>>>> Is this struct necessary? Seems to be a lot of duplicated information
>>>>> from the other structs. Why not add the regulator and regulator_nb to
>>>>> the main struct? OK, not all io_pads have a regulator but you are only
>>>>> saving one pointer.
>>>> Yes, some of IO pads support multi-voltage.
>>> Yes, but I am saying why not put this information in the main struct and
>>> not bother having yet another struct where half of the information is
>>> duplicated.
>> For regulator notifier callback, we will need the driver data. If I keep
>> this in the main structure then I will not able to get proper structure
>> until I make that as global.
>>
>> The notifier registration is
>>                  ret = devm_regulator_register_notifier(regulator,
>> &rinfo->regulator_nb);
>>
>>
>> and from the pointer of rinfo->regulator_nb, I will get the rinfo as
>>
>>          rinfo = container_of(nb, struct tegra_io_pads_regulator_info,
>>                                       regulator_nb);
>>
>> if I use this in main structure then I will not be able to get the
>> driver data.
> Ah yes, you have an array of regulators. Make sense. However, shame to
> duplicate some of this data and also would be good to avoid allocating
> so much memory in probe for these structs if only a few rails actually
> have regulators ...
>
>    tiopi->rinfo = devm_kzalloc(dev, sizeof(*tiopi->rinfo) *
> 				soc_data->num_pads_cfg, GFP_KERNEL);
>
Then allocate inside loop when supply found.
This way we can optimise the size of allocation on cast of the multiple 
memory allocation.

^ permalink raw reply

* Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-22  8:15 UTC (permalink / raw)
  To: Jon Hunter, linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
	robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	swarren-3lzwWm7+Weoh9ZMKESR00Q,
	thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
  Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w,
	yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A,
	linux-gpio-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-tegra-u79uwXL29TY76Z2rM5mHXA,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <29e19381-9250-3059-b083-49e8ab56ea7f-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>


On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
> On 09/11/16 13:06, Laxman Dewangan wrote:
> +	_entry_(32, "uart", UART, true, "vddio-uart"),		\
> +	_entry_(33, "usb0", USB0, true, NULL),			\
> +	_entry_(34, "usb1", USB1, true, NULL),			\
> +	_entry_(35, "usb2", USB2, true, NULL),			\
> +	_entry_(36, "usb3", USB3, true, NULL),			\
> +	_entry_(37, "usb-bias", USB_BIAS, true, NULL)
> Can you also fix these checkpatch errors ...
>
> ERROR: Macros with complex values should be enclosed in parentheses
> #424: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:350:
>
> ERROR: Macros with complex values should be enclosed in parentheses
> #456: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:382:

I can fix this but will still have the error as:

CHECK: Macro argument reuse '_entry_' - possible side-effects?
#425: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:425:


And there is no better way to fix this.

^ permalink raw reply

* Re: [PATCH] ARM: dts: exynos: remove the cd-gpios property for eMMC of odroid-xu3/4
From: Jaehoon Chung @ 2016-11-22  8:19 UTC (permalink / raw)
  To: Andrzej Hajda, Krzysztof Kozlowski
  Cc: linux-samsung-soc, linux-kernel, devicetree, kgene, cw00.choi,
	robh+dt, mark.rutland, catalin.marinas, will.deacon, m.szyprowski,
	jy0922.shim
In-Reply-To: <7e072e61-0a14-ebee-03ac-2eff4f029848@samsung.com>

On 11/22/2016 04:51 PM, Andrzej Hajda wrote:
> On 22.11.2016 02:24, Jaehoon Chung wrote:
>> On 11/22/2016 02:06 AM, Krzysztof Kozlowski wrote:
>>> On Mon, Nov 21, 2016 at 04:10:32PM +0900, Jaehoon Chung wrote:
>>>> Odroid-xu3/4 didn't need to use the cd-gpios for detecting card.
>>>> Because Host controller has the CDETECT register through SDx_CDN line.
>>>> Host controller can know whether card is inserted or not with this
>>>> register.
>>>>
>>>> When i have checked the Odroid-xu3/4, they are using CDETECT register.
>>>> (Not using exteranl cd-gpio.)
>>> Makes sense. Just one question: the sd0_cd pinctrl setting should stay,
>>> right?
>> Right, It needs to use SD0_CD function.
>> I have tested on Odroid-XU3/XU4.
>>
>> Tested with the below cases.
>>
>> 1) On boot with SD-card (without eMMC)
>> - Inserted eMMC : Detected
>> - Removed eMMC : Detected
>>
>> 2) On boot with Sd-card (with eMMC)
>> - Detected
>>
>> 3) On boot with eMMC 
>> - Detected
> 
> I suspect that MMC device (or its parts) should be always awake to keep
> working CDETECT register. With cd-gpio it should be possible to power it
> off when unused but still having detection working, am I right? I am not
> familiar enough with the code to be certain that it improves PM but it
> could be the case.

CDETECT register is used only "card is present or not". not needs to keep power..

> 
> My other question is about polling thread, original patch was developed
> to avoid polling thread which caused occasional hangs, crashes and
> unnecessary work. Since then lot of mmc code changed and I do not follow
> these changes. So my question is if this patch will not re-enable polling?

This patch didn't use polling scheme. It just uses the CDETECT register for detecting.
And Host controller has enabled the Card detect bit at INTMSK register.
(For interrupt handling)

Best Regards,
Jaehoon Chung

> 
> Regards
> Andrzej
> 
>>
>> Best Regards,
>> Jaehoon Chung
>>
>>> Best regards,
>>> Krzysztof
>>>
>>>> Fixes: fb1aeedb61ad ("ARM: dts: add mmc detect gpio for exynos5422-odroidxu3")
>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>> ---
>>>>  arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi | 1 -
>>>>  1 file changed, 1 deletion(-)
>>>>
>>>> diff --git a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> index 9e63328..05b9afdd 100644
>>>> --- a/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> +++ b/arch/arm/boot/dts/exynos5422-odroidxu3-common.dtsi
>>>> @@ -510,7 +510,6 @@
>>>>  &mmc_0 {
>>>>  	status = "okay";
>>>>  	mmc-pwrseq = <&emmc_pwrseq>;
>>>> -	cd-gpios = <&gpc0 2 GPIO_ACTIVE_LOW>;
>>>>  	card-detect-delay = <200>;
>>>>  	samsung,dw-mshc-ciu-div = <3>;
>>>>  	samsung,dw-mshc-sdr-timing = <0 4>;
>>>> -- 
>>>> 2.10.1
>>>>
>>>
>>>
>>
>>
> 
> 
> 

^ permalink raw reply

* Re: [PATCH 1/6] reset: hisilicon: add reset core
From: Arnd Bergmann @ 2016-11-22  8:45 UTC (permalink / raw)
  To: Zhangfei Gao
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-2-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

On Tuesday, November 22, 2016 3:49:16 PM CET Zhangfei Gao wrote:
> @@ -1,8 +1,8 @@
>  obj-y += core.o
> -obj-y += hisilicon/
>  obj-$(CONFIG_ARCH_STI) += sti/
>  obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
>  obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
>  obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>  obj-$(CONFIG_RESET_MESON) += reset-meson.o
>  obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o

Please leave the obj-y line, otherwise the COMPILE_TEST variant won't work.

	Arnd
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^ permalink raw reply

* Re: [PATCH 4/6] dt-bindings: change hi6220-reset.txt according to reset-hi6220.c
From: Arnd Bergmann @ 2016-11-22  8:48 UTC (permalink / raw)
  To: Zhangfei Gao
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-5-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

On Tuesday, November 22, 2016 3:49:19 PM CET Zhangfei Gao wrote:
>  Required properties:
>  - compatible: should be one of the following:
> -  - "hisilicon,hi6220-sysctrl", "syscon" : For peripheral reset controller.
> -  - "hisilicon,hi6220-mediactrl", "syscon" : For media reset controller.
> -- reg: should be register base and length as documented in the
> -  datasheet
> +  - "hisilicon,hi6220-reset-sysctrl" : For peripheral reset controller.
> +  - "hisilicon,hi6220-reset-mediactrl" : For media reset controller.
> +- hisi,rst-syscon: phandle of the reset's syscon.
>  - #reset-cells: 1, see below
> 

Please keep the old strings around for compatibility.

	Arnd

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^ permalink raw reply

* Re: [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: Arnd Bergmann @ 2016-11-22  8:49 UTC (permalink / raw)
  To: Zhangfei Gao
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-6-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

On Tuesday, November 22, 2016 3:49:20 PM CET Zhangfei Gao wrote:
> 
> -#define PERIPH_RSTDIS0_MMC0             0x000
> -#define PERIPH_RSTDIS0_MMC1             0x001
> -#define PERIPH_RSTDIS0_MMC2             0x002
> -#define PERIPH_RSTDIS0_NANDC            0x003
> -#define PERIPH_RSTDIS0_USBOTG_BUS       0x004
> -#define PERIPH_RSTDIS0_POR_PICOPHY      0x005
> -#define PERIPH_RSTDIS0_USBOTG           0x006
> -#define PERIPH_RSTDIS0_USBOTG_32K       0x007
> -#define PERIPH_RSTDIS1_HIFI             0x100
> -#define PERIPH_RSTDIS1_DIGACODEC        0x105

> +/* reset in sysctrl */
> +#define PERIPH_RSTDIS0_MMC0             0
> +#define PERIPH_RSTDIS0_MMC1             1
> +#define PERIPH_RSTDIS0_MMC2             2
> +#define PERIPH_RSTDIS0_NANDC            3
> +#define PERIPH_RSTDIS0_USBOTG_BUS       4
> +#define PERIPH_RSTDIS0_POR_PICOPHY      5
> +#define PERIPH_RSTDIS0_USBOTG           6
> +#define PERIPH_RSTDIS0_USBOTG_32K       7
> +#define PERIPH_RSTDIS1_HIFI             8

You can't redefined the binding here, this is part of the ABI.
You can however add new numbers as long as the old ones keep
working.

	Arnd
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^ permalink raw reply

* Re: [PATCH V2 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition
From: Laxman Dewangan @ 2016-11-22  8:50 UTC (permalink / raw)
  To: Rob Herring
  Cc: broonie-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA, Douglas Anderson,
	Aleksandr Frid
In-Reply-To: <20161121161727.y6pvydowiyeyy7qs@rob-hp-laptop>


On Monday 21 November 2016 09:47 PM, Rob Herring wrote:
> On Fri, Nov 18, 2016 at 08:05:55PM +0530, Laxman Dewangan wrote:
>> Some PWM regulator has the exponential transition in voltage change as
>> opposite to fixed slew-rate linear transition on other regulators.
>> For such PWM regulators, add the property to tell that voltage change
>> is exponential and having fixed delay for any level of change.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> CC: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> CC: Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> ---
>> This patch is continuation of discussion on patch
>> 	regulator: pwm: Fix regulator ramp delay for continuous mode
>> https://patchwork.kernel.org/patch/9216857/
>> where is it discussed to have separate property for PWM which has
>> exponential voltage transition.
>>
>> Changes from V1:
>> - Pass the flag to tell that voltage ramp is exponential instead of
>>    providing delay.
>> ---
>>   .../devicetree/bindings/regulator/pwm-regulator.txt          | 12 ++++++++++++
>>   1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> index 3aeba9f..2d9ef3a 100644
>> --- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> @@ -54,6 +54,18 @@ Optional properties:
>>   --------------------
>>   - enable-gpios:		GPIO to use to enable/disable the regulator
>>   
>> +- voltage-ramp-exponential: Boolean, Some of PWM regulator has the exponential
>> +			transition in voltage ramp as opposite to fixed
>> +			slew-rate linear transition on other regulators.
>> +			For such PWM regulator, presence of this property will
>> +			tell that value of the regulator ramp delay provided by
>> +			DT property "regulator-ramp-delay" is exponential and
>> +			fixed delay for any voltage level change.
>> +			If PWM regulator supports the fixed linear slew rate
>> +			then this property should be absent from DT node and
>> +			property "regulator-ramp-delay" is used as linear slew
>> +			rate.
> Sorry, but on further thought, I don't think we should mix different
> units for the same property. Also, the fact that the ramp is exponential
> is irrelevant. You just want an absolute delay time rather than a rate,
> right? So instead, how about just "regulator-ramp-time-us". Roughly what
> you had in v1, but not PWM specific.

Can we say "regulator-settling-time-us" and make it generic i.e. part of 
the regulator core instead of PWM regulator specific?

So no change for "regulator-ramp-delay".
new property "regulator-settling-time-us" for fixed settling time in any 
voltage level change.

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^ permalink raw reply

* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: Arnd Bergmann @ 2016-11-22  8:50 UTC (permalink / raw)
  To: Zhangfei Gao
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-4-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
> 
> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
> +       [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
> +       [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
> +       [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
> +       [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
> +};
> +
> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
> +       .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
> +       .channels = hi3660_iomcu_rst,
> +};
> +
> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
> +       [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
> +       [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
> +       [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
> +       [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
> +       [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
> +       [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
> +       [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
> +       [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
> +       [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
> +       [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
> +       [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
> +       [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
> +       [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
> +       [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
> +       [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
> +};

I think you can avoid the trap of the ABI incompatibility if
you just define those as in the binding as tuples, using #reset-cells=2.

In particular for the first set, it seems really silly to redefine
the numbers when there is just a simple integer number.

	Arnd

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* Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets
From: Kishon Vijay Abraham I @ 2016-11-22  9:09 UTC (permalink / raw)
  To: Vivek Gautam
  Cc: robh+dt, Mark Rutland, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-arm-msm
In-Reply-To: <CAFp+6iFhJ245YEuLNd0jOOLVtf=_GFaD12PdiM__-32W==WRTQ@mail.gmail.com>

Hi,

On Tuesday 22 November 2016 01:17 PM, Vivek Gautam wrote:
> Hi Kishon,
> 
> 
> On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
> <vivek.gautam@codeaurora.org> wrote:
>> Hi Kishon,
>>
> 
>>>> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
>>>> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
>>>> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };
> 
>>> you can have a separate reg map for each lane and all these can come from dt.
>>
>> The idea is to avoid the any child nodes for lanes. So, we have the complete
>> ioremaped region and these offsets to tx, rx and pcs blocks.
> 
> I don't see benefits in using regmap for different lanes.
> Do you see benefits in replacing a bunch of readl()/writel() with
> regmap_read()/regmap_update_bits()/regmap_write() ?

By reg map, I meant register spaces allocated for different lanes.
> 
> I can as well use separate 'reg' values for each lanes, and have the offsets
> come from dt. Something like below :
> 
>  - reg: array of offset and length of the PHY register sets.
>        at index 0: offset and length of register set for PHY common
>                    serdes block.
>        from index 1 - N: offset and length of register set for each lane,
>                          for N number of phy lanes (ports).
>  - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.
> 
> Example:
>        pcie_phy: pciephy@34000 {
>                compatible = "qcom,msm8996-qmp-pcie-phy";
>                reg = <0x034000 0x48f>,
>                        <0x035000 5bf>,
>                        <0x036000 5bf>,
>                        <0x037000 5bf>;
>                                        /* tx, rx, pcs */
>                lane-offsets = <0x0 0x200 0x400>;

right, I meant something like this.

Thanks
Kishon

^ permalink raw reply

* RE: [PATCH v3] ARM: at91/dt: add dts file for sama5d36ek CMP board
From: Wenyou.Yang-UWL1GkI3JZL3oGB3hsPCZA @ 2016-11-22  9:11 UTC (permalink / raw)
  To: alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
  Cc: nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w,
	linux-lFZ/pmaqli7XmaaqVzeoHQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
	pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
	ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
	galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
	devicetree-u79uwXL29TY76Z2rM5mHXA,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161121140248.utlir6krokjeeobi-m++hUPXGwpdeoWH0uzbU5w@public.gmane.org>



> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com]
> Sent: 2016年11月21日 22:03
> To: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>; Russell King
> <linux@arm.linux.org.uk>; Rob Herring <robh+dt@kernel.org>; Pawel Moll
> <pawel.moll@arm.com>; Mark Rutland <mark.rutland@arm.com>; Ian Campbell
> <ijc+devicetree@hellion.org.uk>; Kumar Gala <galak@codeaurora.org>; linux-
> kernel@vger.kernel.org; Wenyou Yang - A41535
> <Wenyou.Yang@microchip.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v3] ARM: at91/dt: add dts file for sama5d36ek CMP board
> 
> Hi,
> 
> I fixed it up this time but please use the proper subject prefix next time (ARM: dts:
> at91:).

Thank you.

I keep it in mind.

> 
> On 21/11/2016 at 13:14:42 +0800, Wenyou Yang wrote :
> > The sama5d36ek CMP board is the variant of sama5d3xek board.
> > It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865 and some
> > power rail. Its main purpose is used to measure the power consumption.
> > The difference of the sama5d36ek CMP dts from sama5d36ek dts is listed
> > as below.
> >  1. The USB host nodes are removed, that is, the USB host is disabled.
> >  2. The gpio_keys node is added to wake up from the sleep.
> >  3. The LCD isn't supported due to the pins for LCD are conflicted
> >     with gpio_keys.
> >  4. The adc0 node support the pinctrl sleep state to fix the over
> >     consumption on VDDANA.
> >
> > As said in errata, "When the USB host ports are used in high speed
> > mode (EHCI), it is not possible to suspend the ports if no device is
> > attached on each port. This leads to increased power consumption even
> > if the system is in a low power mode." That is why the the USB host is
> > disabled.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > ---
> >
> > Changes in v3:
> >  - Use a dual license scheme for DT files.
> >  - Use the proper model name and the compatible string to reflect
> >    the nature of this new "CMP" board.
> >  - Change name of wakeup property to "wakeup-source".
> >  - Remove unnecessary comments.
> >  - Remove bootargs.
> >
> > Changes in v2:
> >  - Add the pinctrl sleep state for adc0 node to fix the over
> >    consumption on VDDANA.
> >  - Improve the commit log.
> >
> >  arch/arm/boot/dts/sama5d36ek_cmp.dts  |  87 ++++++++++
> > arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 201 +++++++++++++++++++++++
> > arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 301
> > ++++++++++++++++++++++++++++++++++
> >  3 files changed, 589 insertions(+)
> >  create mode 100644 arch/arm/boot/dts/sama5d36ek_cmp.dts
> >  create mode 100644 arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
> >  create mode 100644 arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
> >
> Applied, thanks.
> 
> --
> Alexandre Belloni, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com

Best Regards,
Wenyou Yang

^ permalink raw reply

* RE: [PATCH V3 1/4] Documentation: pv88080: Move binding document
From: Eric Hyeung Dong Jeong @ 2016-11-22  9:20 UTC (permalink / raw)
  To: Rob Herring, Eric Hyeung Dong Jeong
  Cc: DEVICETREE, LINUX-KERNEL, Mark Rutland, Alexandre Courbot,
	LINUX-GPIO, Lee Jones, Liam Girdwood, Linus Walleij, Mark Brown,
	Support Opensource
In-Reply-To: <20161118153842.bbcmfczxvrwamlqs@rob-hp-laptop>

On Saturday, November 19, 2016 12:39 AM, Rob Herring wrote:

> On Fri, Nov 18, 2016 at 09:35:46AM +0900, Eric Jeong wrote:
> >
> > From: Eric Jeong <eric.jeong.opensource@diasemi.com>
> >
> > The change is to move pv88080 binding document from the regulator
> > directory to mfd binding directory for PV88080 PMIC MFD support.
> > And, GPIO properties are added.
> >
> >
> > Signed-off-by: Eric Jeong <eric.jeong.opensource@diasemi.com>
> >
> > ---
> > This patch applies against linux-next and next-20161117
> >
> > Hi,
> >
> > Change since PATCH V2
> >  - Added property and description for gpio
> >
> > Change since PATCH V1
> >  - Patch separated from PATCH V1
> >
> > Regards,
> > Eric Jeong, Dialog Semiconductor Ltd.
> >
> >
> >  .../bindings/{regulator => mfd}/pv88080.txt        |   16 +++++++++++++++-
> >  1 file changed, 15 insertions(+), 1 deletion(-)  rename
> > Documentation/devicetree/bindings/{regulator => mfd}/pv88080.txt (79%)
> >
> > diff --git a/Documentation/devicetree/bindings/regulator/pv88080.txt
> > b/Documentation/devicetree/bindings/mfd/pv88080.txt
> > similarity index 79%
> > rename from Documentation/devicetree/bindings/regulator/pv88080.txt
> > rename to Documentation/devicetree/bindings/mfd/pv88080.txt
> > index e6e4b9c8..7e24f95 100644
> > --- a/Documentation/devicetree/bindings/regulator/pv88080.txt
> > +++ b/Documentation/devicetree/bindings/mfd/pv88080.txt
> > @@ -1,4 +1,4 @@
> > -* Powerventure Semiconductor PV88080 Voltage Regulator
> > +* Powerventure Semiconductor PV88080 PMIC
> >
> >  Required properties:
> >  - compatible: Must be one of the following, depending on the @@ -16,8
> > +16,15 @@ Required properties:
> >    standard binding for regulators; see regulator.txt.
> >    BUCK1, BUCK2, BUCK3 and HVBUCK.
> >
> > +- gpio-controller: Marks the device node as a GPIO controller.
> > +- #gpio-cells: Should be 2. See gpio.txt in this directory
> > +  for a description of the cells format.
> > +
> >  Optional properties:
> > +- ngpios : Number of in-use slots of available slots for GPIO.
> > +  Maximum is 2.
> >  - Any optional property defined in regulator.txt
> > +  and gpio.txt for more information.
> >
> >  Example:
> >
> > @@ -27,6 +34,13 @@ Example:
> >  		interrupt-parent = <&gpio>;
> >  		interrupts = <24 24>;
> >
> > +		gpioex {
> 
> gpio-controller {
> 
> > +			compatible = "pvs,pv88080-gpio";
> 
> Is this documented?

No, It's not documented. I will update this document with the compatible string.

> 
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			ngpios = <2>;
> > +		};
> > +
> >  		regulators {
> >  			BUCK1 {
> >  				regulator-name = "buck1";
> > --
> > end-of-patch for PATCH V3
> >

^ permalink raw reply

* Re: [PATCH 1/6] reset: hisilicon: add reset core
From: zhangfei @ 2016-11-22  9:22 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3993565.nedzUBZcVS@wuerfel>

Hi, Arnd

On 2016年11月22日 16:45, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 3:49:16 PM CET Zhangfei Gao wrote:
>> @@ -1,8 +1,8 @@
>>   obj-y += core.o
>> -obj-y += hisilicon/
>>   obj-$(CONFIG_ARCH_STI) += sti/
>>   obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
>>   obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
>> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
>>   obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>>   obj-$(CONFIG_RESET_MESON) += reset-meson.o
>>   obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> Please leave the obj-y line, otherwise the COMPILE_TEST variant won't work.

COMPILE_TEST is added in drivers/reset/hisilicon/Kconfig
like
config COMMON_RESET_HI3660
         tristate "Hi3660 Reset Driver"
         depends on ARCH_HISI || COMPILE_TEST

The reason not using "obj-y" here is that reset.c will be compiled unconditionally.

drivers/reset/hisilicon/Makefile
obj-y   += reset.o

Thanks

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^ permalink raw reply

* Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-22  9:32 UTC (permalink / raw)
  To: Joe Perches, Jon Hunter, linus.walleij, robh+dt, mark.rutland,
	swarren, thierry.reding
  Cc: gnurou, yamada.masahiro, linux-gpio, devicetree, linux-tegra,
	linux-kernel
In-Reply-To: <1479807957.1942.9.camel@perches.com>


On Tuesday 22 November 2016 03:15 PM, Joe Perches wrote:
> On Tue, 2016-11-22 at 13:45 +0530, Laxman Dewangan wrote:
>> On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
>>> On 09/11/16 13:06, Laxman Dewangan wrote:
>>> +	_entry_(32, "uart", UART, true, "vddio-uart"),		\
>>> +	_entry_(33, "usb0", USB0, true, NULL),			\
>>> +	_entry_(34, "usb1", USB1, true, NULL),			\
>>> +	_entry_(35, "usb2", USB2, true, NULL),			\
>>> +	_entry_(36, "usb3", USB3, true, NULL),			\
>>> +	_entry_(37, "usb-bias", USB_BIAS, true, NULL)
>>> Can you also fix these checkpatch errors ...
>>>
>>> ERROR: Macros with complex values should be enclosed in parentheses
>>> #424: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:350:
>>>
>>> ERROR: Macros with complex values should be enclosed in parentheses
>>> #456: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:382:
>> I can fix this but will still have the error as:
>>
>> CHECK: Macro argument reuse '_entry_' - possible side-effects?
>> #425: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:425:
>>
>>
>> And there is no better way to fix this.
> It's a stupid little script, feel free to ignore it.
And when I tried to add the parenthesis, it failed in compilation.
So in this case, we just need to ignore the error of

Macros with complex values should be enclosed in parentheses

^ permalink raw reply

* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: zhangfei @ 2016-11-22  9:34 UTC (permalink / raw)
  To: Arnd Bergmann
  Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
	xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
	Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
	devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2220300.Yj4lYzeH2z@wuerfel>

Hi, Arnd

On 2016年11月22日 16:50, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
>> +       [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
>> +       [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
>> +       [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
>> +       [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
>> +};
>> +
>> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
>> +       .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
>> +       .channels = hi3660_iomcu_rst,
>> +};
>> +
>> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
>> +       [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
>> +       [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
>> +       [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
>> +       [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
>> +       [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
>> +       [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
>> +       [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
>> +       [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
>> +       [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
>> +       [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
>> +       [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
>> +       [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
>> +       [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
>> +       [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
>> +       [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
>> +};
> I think you can avoid the trap of the ABI incompatibility if
> you just define those as in the binding as tuples, using #reset-cells=2.
>
> In particular for the first set, it seems really silly to redefine
> the numbers when there is just a simple integer number.

Could you clarify more, still not understand.
The number is index of the arrays, and the index will be used in dts.
The arrays lists the registers offset and bit shift.
For example:

[HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.

And Documentation/devicetree/bindings/reset/reset.txt
Required properties:
#reset-cells:   Number of cells in a reset specifier; Typically 0 for nodes
                 with a single reset output and 1 for nodes with multiple
                 reset outputs.

Thanks
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^ permalink raw reply

* Re: [PATCH v2 01/13] devicetree/bindings: display: Document common panel properties
From: Laurent Pinchart @ 2016-11-22  9:36 UTC (permalink / raw)
  To: Rob Herring
  Cc: linux-renesas-soc, Tomi Valkeinen, Laurent Pinchart, dri-devel,
	devicetree
In-Reply-To: <20161121164815.bxca4rfvifloizdh@rob-hp-laptop>

Hi Rob,

On Monday 21 Nov 2016 10:48:15 Rob Herring wrote:
> On Sat, Nov 19, 2016 at 05:28:01AM +0200, Laurent Pinchart wrote:
> > Document properties common to several display panels in a central
> > location that can be referenced by the panel device tree bindings.
> 
> Looks good. Just one comment...
> 
> [...]
> 
> > +Connectivity
> > +------------
> > +
> > +- ports: Panels receive video data through one or multiple connections.
> > While
> > +  the nature of those connections is specific to the panel type, the
> > +  connectivity is expressed in a standard fashion using ports as
> > specified in
> > +  the device graph bindings defined in
> > +  Documentation/devicetree/bindings/graph.txt.
> 
> We allow panels to either use graph binding or be a child of the display
> controller.

I knew that some display controllers use a phandle to the panel (see the 
fsl,panel and nvidia,panel properties), but I didn't know we had panels as 
children of display controller nodes. I don't think we should allow that for 
anything but DSI panels, as the DT hierarchy is based on control buses. Are 
you sure we have other panels instantiated through that mechanism ?

> Using the graph is preferred, but in the simple cases just a child node is
> sufficient. This should be described here or somewhere in this doc.

-- 
Regards,

Laurent Pinchart

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dri-devel mailing list
dri-devel@lists.freedesktop.org
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^ permalink raw reply


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