* [PATCH V3 0/2] pinctrl: tegra: Add support for IO pad control
From: Laxman Dewangan @ 2016-11-22 10:20 UTC (permalink / raw)
To: linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: mark.rutland-5wv7dgnIgG8, gnurou-Re5JQEeQqe8AvxtiuMwx3w,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, joe-6d6DIl74uiNBDgjK7y7TUQ,
jonathanh-DDmLM1+adcrQT0dZR+AlfA, Laxman Dewangan
NVIDIA Tegra124 and later SoCs support the multi-voltage level and
low power state of some of its IO pads. The IO pads can work in
the voltage of the 1.8V and 3.3V of IO power rail sources. When IO
interface are not used then IO pads can be configure in low power
state to reduce the power from that IO pads.
This series add the support of configuration of IO pad via pinctrl
framework. The io pad driver uses the tegra PMC interface.
---
This driver was sent earlier for review along with soc/tegra pmc
changes. During review, decided to first conclude in soc/tegra pmc
patches and then review this.
Thierry applied the pmc patches in the private tree
https://github.com/thierryreding/linux/tree/tegra186
and he wanted to have the patches for user of the new APIs so that
it can be pushed to mainline.
Sending the pinctrl driver. This needs Ack/reviewed from pinctrl subsystem
i.e. Linus Welleij to apply in the Thierry's T186 branch along with
PMC patches.
---
Changes from V1:
- use the regulator framework to get the IO voltage instead of table from
DT. The regulator handle is provided from DT.
Changes from V2:
- Nit fixes and variable/allocation optimisation as per review comment from
V2.
Laxman Dewangan (2):
pinctrl: tegra: Add DT binding for io pads control
pinctrl: tegra: Add driver to configure voltage and power of io pads
.../bindings/pinctrl/nvidia,tegra-io-pad.txt | 126 +++++
drivers/pinctrl/tegra/Kconfig | 12 +
drivers/pinctrl/tegra/Makefile | 1 +
drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c | 530 +++++++++++++++++++++
4 files changed, 669 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/nvidia,tegra-io-pad.txt
create mode 100644 drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c
--
2.1.4
^ permalink raw reply
* Re: [RFC PATCH net v2 2/3] dt: bindings: add ethernet phy eee-disable-advert option documentation
From: Jerome Brunet @ 2016-11-22 10:13 UTC (permalink / raw)
To: Florian Fainelli, Andrew Lunn
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
Alexandre TORGUE, Neil Armstrong, Martin Blumenstingl,
Kevin Hilman, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andre Roth,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Carlo Caione,
Giuseppe Cavallaro,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <e792c889-8725-3952-ca28-a08537d9f87a-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Mon, 2016-11-21 at 21:35 -0800, Florian Fainelli wrote:
> Le 21/11/2016 à 08:47, Andrew Lunn a écrit :
> >
> > >
> > > What I did not realize when doing this patch for the realtek
> > > driver is
> > > that there is already 6 valid modes defined in the kernel
> > >
> > > #define MDIO_EEE_100TX MDIO_AN_EEE_ADV_100TX
> > > /*
> > > 100TX EEE cap */
> > > #define MDIO_EEE_1000T MDIO_AN_EEE_ADV_1000T
> > > /*
> > > 1000T EEE cap */
> > > #define MDIO_EEE_10GT 0x0008 /* 10GT EEE
> > > cap */
> > > #define MDIO_EEE_1000KX 0x0010 /* 1000KX
> > > EEE cap
> > > */
> > > #define MDIO_EEE_10GKX4 0x0020 /* 10G KX4
> > > EEE cap
> > > */
> > > #define MDIO_EEE_10GKR 0x0040 /* 10G KR EEE
> > > cap
> > > */
> > >
> > > I took care of only 2 in the case of realtek.c since it only
> > > support
> > > MDIO_EEE_100TX and MDIO_EEE_1000T.
> > >
> > > Defining a property for each is certainly doable but it does not
> > > look
> > > very nice either. If it extends in the future, it will get even
> > > more
> > > messier, especially if you want to disable everything.
> >
> > Yes, agreed.
>
> One risk with the definition a group of advertisement capabilities
> (under the form of a bitmask for instance) to enable/disable is that
> we
> end up with Device Tree contain some kind of configuration policy as
> opposed to just flagging particular hardware features as broken.
The code proposed only allows to disable EEE advertisement (not
enable), so we should not see it used as a configuration policy in DT.
To make this more explicit, I could replace the property "eee-advert-
disable" by "eee-broken" ?
>
> Fortunately, there does not seem to be a ton of PHYs out there which
> require EEE
It is quite difficult to have the real picture here because some PHYs
have EEE disabled by default and you have to explicitly enable it.
I have no idea of the ratio between the 2 phy policies.
> to be disabled to function properly so having individual
> properties vs. bitmasks/groups is kind of speculative here.
In the particular instance of the OdroidC2, disabling EEE for GbE only
enough. However, If you have a PHY broken with, I think it is likely
that you might want to disable all (supported) EEE modes. That's reason
why I prefer bitmask. I agree both are functionally similar, this is
kind of a cosmetic debate.
>
> Another approach to solving this problem could be to register a PHY
> fixup which disables EEE at the PHY level, and which is only called
> for
> specific boards affected by this problem
> (of_machine_is_compatible()).
> This code can leave in arch/*/* when that is possible,
That something I was looking at, but we don't have these files anymore
on ARM64 (looking at your comment, you already know this)
> or it can just be
> somewhere where it is relevant, e.g; in the PHY driver for instance
> (similarly to how PCI fixups are done).
Do you prefer having board specific code inside generic driver than
having the setting living in DT? Peppe told me they also had a few
platform with similar issues. The point is that this could be useful to
other people, so it could spread a grow a bit.
I would prefer having this in the DT, but I can definitely do it the
PHY with of_machine_is_compatible() and register_fixup is this what you
prefer/want.
Cheers
Jerome
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^ permalink raw reply
* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: zhangfei @ 2016-11-22 10:02 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3166877.sQekoU5ezv@wuerfel>
On 2016年11月22日 17:42, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 5:34:05 PM CET zhangfei wrote:
>> On 2016年11月22日 16:50, Arnd Bergmann wrote:
>>> On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>>>> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
>>>> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
>>>> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
>>>> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
>>>> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
>>>> +};
>>>> +
>>>> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
>>>> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
>>>> + .channels = hi3660_iomcu_rst,
>>>> +};
>>>> +
>>>> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
>>>> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
>>>> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
>>>> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
>>>> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
>>>> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
>>>> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
>>>> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
>>>> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
>>>> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
>>>> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
>>>> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
>>>> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
>>>> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
>>>> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
>>>> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
>>>> +};
>>> I think you can avoid the trap of the ABI incompatibility if
>>> you just define those as in the binding as tuples, using #reset-cells=2.
>>>
>>> In particular for the first set, it seems really silly to redefine
>>> the numbers when there is just a simple integer number.
>> Could you clarify more, still not understand.
>> The number is index of the arrays, and the index will be used in dts.
>> The arrays lists the registers offset and bit shift.
>> For example:
>>
>> [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.
>>
>> And Documentation/devicetree/bindings/reset/reset.txt
>> Required properties:
>> #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
>> with a single reset output and 1 for nodes with multiple
>> reset outputs.
> You can easily enumerate the registers that contain reset bits here,
> so just use one cell for the register and another one for the index.
/* reset separated register offset is 0x4 */
#define HISI_RST_SEP(off, bit) \
{ .enable = REG_FIELD(off, bit, bit), \
.disable = REG_FIELD(off + 0x4, bit, bit), \
.status = REG_FIELD(off + 0x8, bit, bit), }
We not only provide the off and bit shift, but fulfill the members in
the meantime.
Thanks
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^ permalink raw reply
* [PATCH v2 2/2] ARM64: dts: meson-gxm: Add support for the Nexbox A1
From: Neil Armstrong @ 2016-11-22 10:00 UTC (permalink / raw)
To: khilman, carlo
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel,
devicetree
In-Reply-To: <20161122100046.25899-1-narmstrong@baylibre.com>
Add support for the Nexbox A1 board based on the Amlogic S912 SoC.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.txt | 1 +
arch/arm64/boot/dts/amlogic/Makefile | 1 +
.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 169 +++++++++++++++++++++
3 files changed, 171 insertions(+)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index 1144214..6ef7c52 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -45,3 +45,4 @@ Board compatible values:
- "amlogic,p231" (Meson gxl s905d)
- "amlogic,q200" (Meson gxm s912)
- "amlogic,q201" (Meson gxm s912)
+ - "nexbox,a1" (Meson gxm s912)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 7752a16..2fbb8e3 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
new file mode 100644
index 0000000..d320727
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
@@ -0,0 +1,169 @@
+/*
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+
+/ {
+ compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
+ model = "NEXBOX A1";
+
+ aliases {
+ serial0 = &uart_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&uart_ao_a_pins>;
+ pinctrl-names = "default";
+};
+
+&ir {
+ status = "okay";
+ pinctrl-0 = <&remote_input_ao_pins>;
+ pinctrl-names = "default";
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ mmc-ddr-1_8v;
+ mmc-hs200-1_8v;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+ðmac {
+ status = "okay";
+
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
+};
--
2.7.0
^ permalink raw reply related
* [PATCH v2 1/2] ARM64: dts: Add support for Meson GXM
From: Neil Armstrong @ 2016-11-22 10:00 UTC (permalink / raw)
To: khilman, carlo
Cc: Neil Armstrong, linux-amlogic, linux-arm-kernel, linux-kernel,
devicetree
In-Reply-To: <20161122100046.25899-1-narmstrong@baylibre.com>
Following the Amlogic Linux kernel, it seem the only differences
between the GXL and GXM SoCs are the CPU Clusters.
This commit renames the gxl-s905d-p23x DTSI in a common file for
S905D p23x and S912 q20x boards.
Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards
dts files since the S905D and S912 SoCs shares the same pinout
and the P23x and Q20x boards are identical.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
---
Documentation/devicetree/bindings/arm/amlogic.txt | 6 ++
arch/arm64/boot/dts/amlogic/Makefile | 2 +
...gxl-s905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} | 4 +-
.../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 3 +-
.../arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 77 ++++++++++++++
.../arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts | 58 +++++++++++
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 114 +++++++++++++++++++++
8 files changed, 264 insertions(+), 3 deletions(-)
rename arch/arm64/boot/dts/amlogic/{meson-gxl-s905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
index fffc179..1144214 100644
--- a/Documentation/devicetree/bindings/arm/amlogic.txt
+++ b/Documentation/devicetree/bindings/arm/amlogic.txt
@@ -25,6 +25,10 @@ Boards with the Amlogic Meson GXL S905D SoC shall have the following properties:
Required root node property:
compatible: "amlogic,s905d", "amlogic,meson-gxl";
+Boards with the Amlogic Meson GXM S912 SoC shall have the following properties:
+ Required root node property:
+ compatible: "amlogic,s912", "amlogic,meson-gxm";
+
Board compatible values:
- "geniatech,atv1200" (Meson6)
- "minix,neo-x8" (Meson8)
@@ -39,3 +43,5 @@ Board compatible values:
- "amlogic,p212" (Meson gxl s905x)
- "amlogic,p230" (Meson gxl s905d)
- "amlogic,p231" (Meson gxl s905d)
+ - "amlogic,q200" (Meson gxm s912)
+ - "amlogic,q201" (Meson gxm s912)
diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
index 5a64050..7752a16 100644
--- a/arch/arm64/boot/dts/amlogic/Makefile
+++ b/arch/arm64/boot/dts/amlogic/Makefile
@@ -8,6 +8,8 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-vega-s95-telos.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905x-p212.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
+dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
always := $(dtb-y)
subdir-y := $(dts-dirs)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
similarity index 97%
rename from arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
rename to arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
index 622ffbe..7a078be 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p23x.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx-p23x-q20x.dtsi
@@ -41,7 +41,9 @@
* OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "meson-gxl-s905d.dtsi"
+/* Common DTSI for same Amlogic Q200/Q201 and P230/P231 boards using either
+ * the pin-compatible S912 (GXM) or S905D (GXL) SoCs.
+ */
/ {
aliases {
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 4d082a7..f66939c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -43,7 +43,8 @@
/dts-v1/;
-#include "meson-gxl-s905d-p23x.dtsi"
+#include "meson-gxl-s905d.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p230", "amlogic,s905d", "amlogic,meson-gxl";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
index 1cc8d49..95992cf 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p231.dts
@@ -43,7 +43,8 @@
/dts-v1/;
-#include "meson-gxl-s905d-p23x.dtsi"
+#include "meson-gxl-s905d.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
/ {
compatible = "amlogic,p231", "amlogic,s905d", "amlogic,meson-gxl";
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
new file mode 100644
index 0000000..5dbc660
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
@@ -0,0 +1,77 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+
+/ {
+ compatible = "amlogic,q200", "amlogic,s912", "amlogic,meson-gxm";
+ model = "Amlogic Meson GXM (S912) Q200 Development Board";
+};
+
+/* Q200 has exclusive choice between internal or external PHY */
+ðmac {
+ pinctrl-0 = <ð_pins>;
+ pinctrl-names = "default";
+
+ /* Select external PHY by default */
+ phy-handle = <&external_phy>;
+
+ /* External PHY reset is shared with internal PHY Led signals */
+ snps,reset-gpio = <&gpio GPIOZ_14 0>;
+ snps,reset-delays-us = <0 10000 1000000>;
+ snps,reset-active-low;
+
+ /* External PHY is in RGMII */
+ phy-mode = "rgmii";
+};
+
+&external_mdio {
+ external_phy: ethernet-phy@0 {
+ compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ max-speed = <1000>;
+ };
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
new file mode 100644
index 0000000..95e11d7
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-gxm.dtsi"
+#include "meson-gx-p23x-q20x.dtsi"
+
+/ {
+ compatible = "amlogic,q201", "amlogic,s912", "amlogic,meson-gxm";
+ model = "Amlogic Meson GXM (S912) Q201 Development Board";
+};
+
+/* Q201 has only internal PHY port */
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
new file mode 100644
index 0000000..c1974bb
--- /dev/null
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
@@ -0,0 +1,114 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-gxl.dtsi"
+
+/ {
+ compatible = "amlogic,meson-gxm";
+
+ cpus {
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+ core1 {
+ cpu = <&cpu1>;
+ };
+ core2 {
+ cpu = <&cpu2>;
+ };
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+ core1 {
+ cpu = <&cpu5>;
+ };
+ core2 {
+ cpu = <&cpu6>;
+ };
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ cpu4: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x100>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu5: cpu@101 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x101>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu6: cpu@102 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x102>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+
+ cpu7: cpu@103 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x103>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ };
+ };
+};
--
2.7.0
^ permalink raw reply related
* [PATCH v2 0/2] ARM64: dts: Add support for Meson GXM
From: Neil Armstrong @ 2016-11-22 10:00 UTC (permalink / raw)
To: khilman-rdvid1DuHRBWk0Htik3J/w, carlo-KA+7E9HrN00dnm+yROfE0A
Cc: Neil Armstrong, linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
The new Amlogic GXM SoC (S912) is part of the Meson GX family and is nearly
identical to GXM but with a second Quad-A53 core cluster.
The GXM dtsi includes the GXL dtsi and the p20x dtsi is refactored in a
common p20x/q20x to support the GXM Q200 and Q201 board that uses the exact
same board layout since the S905D and S912 are pinout compatible.
The last patch adds support for the Nexbox A1 Set-Top-Box based on the S912.
Changes since v1 at [1] :
- Remove bad p200/p201 changes
- Fix cpu-map
Changes since RFC :
- Refactor the p20x/q20x dtsi into a single common file
- Add support for Nexbox A1
[1] http://lkml.kernel.org/r/20161121162905.14285-1-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org
Neil Armstrong (2):
ARM64: dts: Add support for Meson GXM
ARM64: dts: meson-gxm: Add support for the Nexbox A1
Documentation/devicetree/bindings/arm/amlogic.txt | 7 +
arch/arm64/boot/dts/amlogic/Makefile | 3 +
...gxl-s905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} | 4 +-
.../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 3 +-
.../boot/dts/amlogic/meson-gxl-s905d-p231.dts | 3 +-
.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 169 +++++++++++++++++++++
.../arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 77 ++++++++++
.../arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts | 58 +++++++
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 114 ++++++++++++++
9 files changed, 435 insertions(+), 3 deletions(-)
rename arch/arm64/boot/dts/amlogic/{meson-gxl-s905d-p23x.dtsi => meson-gx-p23x-q20x.dtsi} (97%)
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-s912-q201.dts
create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
--
2.7.0
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^ permalink raw reply
* Re: [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: Arnd Bergmann @ 2016-11-22 9:55 UTC (permalink / raw)
To: zhangfei
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <0dcef3c7-7406-0728-5a18-c277bb8915ad-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tuesday, November 22, 2016 5:46:22 PM CET zhangfei wrote:
> On 2016年11月22日 16:49, Arnd Bergmann wrote:
> > On Tuesday, November 22, 2016 3:49:20 PM CET Zhangfei Gao wrote:
> >> -#define PERIPH_RSTDIS0_MMC0 0x000
> >> -#define PERIPH_RSTDIS0_MMC1 0x001
> >> -#define PERIPH_RSTDIS0_MMC2 0x002
> >> -#define PERIPH_RSTDIS0_NANDC 0x003
> >> -#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
> >> -#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
> >> -#define PERIPH_RSTDIS0_USBOTG 0x006
> >> -#define PERIPH_RSTDIS0_USBOTG_32K 0x007
> >> -#define PERIPH_RSTDIS1_HIFI 0x100
> >> -#define PERIPH_RSTDIS1_DIGACODEC 0x105
> >> +/* reset in sysctrl */
> >> +#define PERIPH_RSTDIS0_MMC0 0
> >> +#define PERIPH_RSTDIS0_MMC1 1
> >> +#define PERIPH_RSTDIS0_MMC2 2
> >> +#define PERIPH_RSTDIS0_NANDC 3
> >> +#define PERIPH_RSTDIS0_USBOTG_BUS 4
> >> +#define PERIPH_RSTDIS0_POR_PICOPHY 5
> >> +#define PERIPH_RSTDIS0_USBOTG 6
> >> +#define PERIPH_RSTDIS0_USBOTG_32K 7
> >> +#define PERIPH_RSTDIS1_HIFI 8
> > You can't redefined the binding here, this is part of the ABI.
> > You can however add new numbers as long as the old ones keep
> > working.
> The methods are different.
> The original define is offset | bit_shift, and driver has to parse
> offset and bit shift.
> The new define is just index of array, which is defined in the reset-xxx.c
I understand that, what I mean is you have to find a way to let the new
driver still support the old binding, you can't change it.
Arnd
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^ permalink raw reply
* Re: [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: zhangfei @ 2016-11-22 9:46 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3837594.jmpXXfpk9Q@wuerfel>
On 2016年11月22日 16:49, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 3:49:20 PM CET Zhangfei Gao wrote:
>> -#define PERIPH_RSTDIS0_MMC0 0x000
>> -#define PERIPH_RSTDIS0_MMC1 0x001
>> -#define PERIPH_RSTDIS0_MMC2 0x002
>> -#define PERIPH_RSTDIS0_NANDC 0x003
>> -#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
>> -#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
>> -#define PERIPH_RSTDIS0_USBOTG 0x006
>> -#define PERIPH_RSTDIS0_USBOTG_32K 0x007
>> -#define PERIPH_RSTDIS1_HIFI 0x100
>> -#define PERIPH_RSTDIS1_DIGACODEC 0x105
>> +/* reset in sysctrl */
>> +#define PERIPH_RSTDIS0_MMC0 0
>> +#define PERIPH_RSTDIS0_MMC1 1
>> +#define PERIPH_RSTDIS0_MMC2 2
>> +#define PERIPH_RSTDIS0_NANDC 3
>> +#define PERIPH_RSTDIS0_USBOTG_BUS 4
>> +#define PERIPH_RSTDIS0_POR_PICOPHY 5
>> +#define PERIPH_RSTDIS0_USBOTG 6
>> +#define PERIPH_RSTDIS0_USBOTG_32K 7
>> +#define PERIPH_RSTDIS1_HIFI 8
> You can't redefined the binding here, this is part of the ABI.
> You can however add new numbers as long as the old ones keep
> working.
The methods are different.
The original define is offset | bit_shift, and driver has to parse
offset and bit shift.
The new define is just index of array, which is defined in the reset-xxx.c
Thanks
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^ permalink raw reply
* Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Joe Perches @ 2016-11-22 9:45 UTC (permalink / raw)
To: Laxman Dewangan, Jon Hunter, linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
swarren-3lzwWm7+Weoh9ZMKESR00Q,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w
Cc: gnurou-Re5JQEeQqe8AvxtiuMwx3w,
yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-tegra-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <5833FE99.2020004-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
On Tue, 2016-11-22 at 13:45 +0530, Laxman Dewangan wrote:
> On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
> > On 09/11/16 13:06, Laxman Dewangan wrote:
> > + _entry_(32, "uart", UART, true, "vddio-uart"), \
> > + _entry_(33, "usb0", USB0, true, NULL), \
> > + _entry_(34, "usb1", USB1, true, NULL), \
> > + _entry_(35, "usb2", USB2, true, NULL), \
> > + _entry_(36, "usb3", USB3, true, NULL), \
> > + _entry_(37, "usb-bias", USB_BIAS, true, NULL)
> > Can you also fix these checkpatch errors ...
> >
> > ERROR: Macros with complex values should be enclosed in parentheses
> > #424: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:350:
> >
> > ERROR: Macros with complex values should be enclosed in parentheses
> > #456: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:382:
>
> I can fix this but will still have the error as:
>
> CHECK: Macro argument reuse '_entry_' - possible side-effects?
> #425: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:425:
>
>
> And there is no better way to fix this.
It's a stupid little script, feel free to ignore it.
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^ permalink raw reply
* [PATCH 2/4] arm64: dts: rockchip: Arch counter doesn't tick in system suspend
From: Daniel Lezcano @ 2016-11-22 9:44 UTC (permalink / raw)
To: tglx-hfZtesqFncYOwBW4kG4KsQ
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Brian Norris, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Heiko Stuebner,
Douglas Anderson, Caesar Wang, Shawn Lin, Xing Zheng, Jianqun Xu,
Elaine Zhang, David Wu,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM64 PORT AARCH64 ARCHITECTURE,
open list:ARM/Rock
In-Reply-To: <1479807866-6957-1-git-send-email-daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
The "arm,no-tick-in-suspend" property was introduced to note
implementations where the system counter does not quite follow the ARM
specification that it "must be implemented in an always-on power
domain".
Particularly, RK3399's counter stops ticking when we switch from the
24MHz clock to the 32KHz clock in low-power suspend, so let's mark it as
such.
Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..d85b651 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -174,6 +174,7 @@
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
+ arm,no-tick-in-suspend;
};
xin24m: xin24m {
--
2.7.4
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^ permalink raw reply related
* [PATCH 1/4] clocksource/drivers/arm_arch_timer: Don't assume clock runs in suspend
From: Daniel Lezcano @ 2016-11-22 9:44 UTC (permalink / raw)
To: tglx-hfZtesqFncYOwBW4kG4KsQ
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA, Brian Norris, Marc Zyngier,
Rob Herring, Mark Rutland, Will Deacon, Douglas Anderson,
Scott Wood,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM ARCHITECTED TIMER DRIVER
In-Reply-To: <20161122094300.GA2017@mai>
From: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
The ARM specifies that the system counter "must be implemented in an
always-on power domain," and so we try to use the counter as a source of
timekeeping across suspend/resume. Unfortunately, some SoCs (e.g.,
Rockchip's RK3399) do not keep the counter ticking properly when
switched from their high-power clock to the lower-power clock used in
system suspend. Support this quirk by adding a new device tree property.
Signed-off-by: Brian Norris <briannorris-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Reviewed-by: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Acked-by: Marc Zyngier <marc.zyngier-5wv7dgnIgG8@public.gmane.org>
Signed-off-by: Daniel Lezcano <daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
Documentation/devicetree/bindings/arm/arch_timer.txt | 5 +++++
drivers/clocksource/arm_arch_timer.c | 9 ++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/arch_timer.txt b/Documentation/devicetree/bindings/arm/arch_timer.txt
index ef5fbe9..ad440a2 100644
--- a/Documentation/devicetree/bindings/arm/arch_timer.txt
+++ b/Documentation/devicetree/bindings/arm/arch_timer.txt
@@ -38,6 +38,11 @@ to deliver its interrupts via SPIs.
architecturally-defined reset values. Only supported for 32-bit
systems which follow the ARMv7 architected reset values.
+- arm,no-tick-in-suspend : The main counter does not tick when the system is in
+ low-power system suspend on some SoCs. This behavior does not match the
+ Architecture Reference Manual's specification that the system counter "must
+ be implemented in an always-on power domain."
+
Example:
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 73c487d..a2503db 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -81,6 +81,7 @@ static struct clock_event_device __percpu *arch_timer_evt;
static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
static bool arch_timer_c3stop;
static bool arch_timer_mem_use_virtual;
+static bool arch_counter_suspend_stop;
static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
@@ -576,7 +577,7 @@ static struct clocksource clocksource_counter = {
.rating = 400,
.read = arch_counter_read,
.mask = CLOCKSOURCE_MASK(56),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP,
+ .flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
static struct cyclecounter cyclecounter = {
@@ -616,6 +617,8 @@ static void __init arch_counter_register(unsigned type)
arch_timer_read_counter = arch_counter_get_cntvct_mem;
}
+ if (!arch_counter_suspend_stop)
+ clocksource_counter.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
start_count = arch_timer_read_counter();
clocksource_register_hz(&clocksource_counter, arch_timer_rate);
cyclecounter.mult = clocksource_counter.mult;
@@ -907,6 +910,10 @@ static int __init arch_timer_of_init(struct device_node *np)
of_property_read_bool(np, "arm,cpu-registers-not-fw-configured"))
arch_timer_uses_ppi = PHYS_SECURE_PPI;
+ /* On some systems, the counter stops ticking when in suspend. */
+ arch_counter_suspend_stop = of_property_read_bool(np,
+ "arm,no-tick-in-suspend");
+
return arch_timer_init();
}
CLOCKSOURCE_OF_DECLARE(armv7_arch_timer, "arm,armv7-timer", arch_timer_of_init);
--
2.7.4
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^ permalink raw reply related
* [PATCH] ARM: dts: da850: specify max width for display node
From: Bartosz Golaszewski @ 2016-11-22 9:42 UTC (permalink / raw)
To: Kevin Hilman, Michael Turquette, Sekhar Nori, Rob Herring,
Frank Rowand, Mark Rutland, Peter Ujfalusi, Russell King
Cc: linux-devicetree, LKML, linux-drm, Bartosz Golaszewski,
Tomi Valkeinen, Jyri Sarha, arm-soc, Laurent Pinchart
It has been determined that the highest resolution supported correctly
by LCDC rev1 is 800x600 on da850 due to memory bandwidth constraints.
Set the max_width property in da850.dtsi to 800.
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
---
arch/arm/boot/dts/da850.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 36066fa..0876238 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -441,6 +441,7 @@
compatible = "ti,da850-tilcdc";
reg = <0x213000 0x1000>;
interrupts = <52>;
+ max-width = <800>;
status = "disabled";
};
};
--
2.9.3
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related
* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: Arnd Bergmann @ 2016-11-22 9:42 UTC (permalink / raw)
To: zhangfei
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <d6e602c0-70e9-0309-86b5-bfd006d86028-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tuesday, November 22, 2016 5:34:05 PM CET zhangfei wrote:
> On 2016年11月22日 16:50, Arnd Bergmann wrote:
> > On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
> >> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
> >> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
> >> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
> >> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
> >> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
> >> +};
> >> +
> >> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
> >> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
> >> + .channels = hi3660_iomcu_rst,
> >> +};
> >> +
> >> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
> >> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
> >> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
> >> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
> >> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
> >> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
> >> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
> >> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
> >> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
> >> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
> >> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
> >> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
> >> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
> >> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
> >> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
> >> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
> >> +};
> > I think you can avoid the trap of the ABI incompatibility if
> > you just define those as in the binding as tuples, using #reset-cells=2.
> >
> > In particular for the first set, it seems really silly to redefine
> > the numbers when there is just a simple integer number.
>
> Could you clarify more, still not understand.
> The number is index of the arrays, and the index will be used in dts.
> The arrays lists the registers offset and bit shift.
> For example:
>
> [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.
>
> And Documentation/devicetree/bindings/reset/reset.txt
> Required properties:
> #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
> with a single reset output and 1 for nodes with multiple
> reset outputs.
You can easily enumerate the registers that contain reset bits here,
so just use one cell for the register and another one for the index.
Arnd
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^ permalink raw reply
* Re: [PATCH 1/2] ARM64: dts: Add support for Meson GXM
From: Neil Armstrong @ 2016-11-22 9:41 UTC (permalink / raw)
To: Kevin Hilman
Cc: carlo, linux-amlogic, linux-kernel, linux-arm-kernel, devicetree
In-Reply-To: <m2oa181jtd.fsf@baylibre.com>
On 11/22/2016 12:42 AM, Kevin Hilman wrote:
> Neil,
>
> Neil Armstrong <narmstrong@baylibre.com> writes:
>
>> Following the Amlogic Linux kernel, it seem the only differences
>> between the GXL and GXM SoCs are the CPU Clusters.
>>
>> This commit renames the gxl-s905d-p23x DTSI in a common file for
>> S905D p20x and S912 q20x boards.
>
> s/p20x/p23x/ ??
>
>> Then adds a meson-gxm dtsi and reproduce the P23x to Q20x boards
>> dts files since the S905D and S912 SoCs shares the same pinout
>> and the P23x and Q20x boards are identical.
>>
>> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
>
> I had to drop this as it breaks the network on (at least) gxbb-p200, but...
>
> [...]
>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
>> index 03e3d76..17bb77c 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
>> @@ -56,3 +56,22 @@
>> pinctrl-0 = <&i2c_b_pins>;
>> pinctrl-names = "default";
>> };
>> +
>> +ðmac {
>> + status = "okay";
>> + pinctrl-0 = <ð_rgmii_pins>;
>> + pinctrl-names = "default";
>> +
>> + phy-handle = <ð_phy0>;
>> +
>> + mdio {
>> + compatible = "snps,dwmac-mdio";
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + eth_phy0: ethernet-phy@0 {
>> + reg = <0>;
>> + realtek,disable-eee-1000t;
>> + };
>> + };
>> +};
>
> ... backing out this change makes it work again.
>
> This change also looks suspicious as it's using the proposed disable-eee
> properties, which I don't think have been merged yet.
>
>> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
>> index 39bb037..5608c51 100644
>> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
>> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts
>> @@ -50,3 +50,10 @@
>> compatible = "amlogic,p201", "amlogic,meson-gxbb";
>> model = "Amlogic Meson GXBB P201 Development Board";
>> };
>> +
>> +ðmac {
>> + status = "okay";
>> + pinctrl-0 = <ð_rmii_pins>;
>> + pinctrl-names = "default";
>> + phy-mode = "rmii";
>> +};
>
> This also doesn't look releveant to the GXL/GXM changes being introduced
> in this patch.
>
> Could you separate out any GXBB-related changes into a separate patch
> (if they are in fact needed) and re-spin this?
>
> Thanks,
>
> Kevin
>
Sorry leftover for another work...
Will cleanup for v2.
Neil
^ permalink raw reply
* Re: [PATCH 1/6] reset: hisilicon: add reset core
From: Arnd Bergmann @ 2016-11-22 9:41 UTC (permalink / raw)
To: zhangfei
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <0084ef53-c0e6-51e8-afa5-07264dfce529-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tuesday, November 22, 2016 5:22:42 PM CET zhangfei wrote:
> Hi, Arnd
>
> On 2016年11月22日 16:45, Arnd Bergmann wrote:
> > On Tuesday, November 22, 2016 3:49:16 PM CET Zhangfei Gao wrote:
> >> @@ -1,8 +1,8 @@
> >> obj-y += core.o
> >> -obj-y += hisilicon/
> >> obj-$(CONFIG_ARCH_STI) += sti/
> >> obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
> >> obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
> >> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
> >> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
> >> obj-$(CONFIG_RESET_MESON) += reset-meson.o
> >> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> > Please leave the obj-y line, otherwise the COMPILE_TEST variant won't work.
>
> COMPILE_TEST is added in drivers/reset/hisilicon/Kconfig
> like
> config COMMON_RESET_HI3660
> tristate "Hi3660 Reset Driver"
> depends on ARCH_HISI || COMPILE_TEST
>
> The reason not using "obj-y" here is that reset.c will be compiled unconditionally.
>
> drivers/reset/hisilicon/Makefile
> obj-y += reset.o
Yes, that line has to change as well then, to only build it when one
of the hardware specific drivers is enabled.
Arnd
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^ permalink raw reply
* Re: [PATCH v2 01/13] devicetree/bindings: display: Document common panel properties
From: Laurent Pinchart @ 2016-11-22 9:36 UTC (permalink / raw)
To: Rob Herring
Cc: linux-renesas-soc, Tomi Valkeinen, Laurent Pinchart, dri-devel,
devicetree
In-Reply-To: <20161121164815.bxca4rfvifloizdh@rob-hp-laptop>
Hi Rob,
On Monday 21 Nov 2016 10:48:15 Rob Herring wrote:
> On Sat, Nov 19, 2016 at 05:28:01AM +0200, Laurent Pinchart wrote:
> > Document properties common to several display panels in a central
> > location that can be referenced by the panel device tree bindings.
>
> Looks good. Just one comment...
>
> [...]
>
> > +Connectivity
> > +------------
> > +
> > +- ports: Panels receive video data through one or multiple connections.
> > While
> > + the nature of those connections is specific to the panel type, the
> > + connectivity is expressed in a standard fashion using ports as
> > specified in
> > + the device graph bindings defined in
> > + Documentation/devicetree/bindings/graph.txt.
>
> We allow panels to either use graph binding or be a child of the display
> controller.
I knew that some display controllers use a phandle to the panel (see the
fsl,panel and nvidia,panel properties), but I didn't know we had panels as
children of display controller nodes. I don't think we should allow that for
anything but DSI panels, as the DT hierarchy is based on control buses. Are
you sure we have other panels instantiated through that mechanism ?
> Using the graph is preferred, but in the simple cases just a child node is
> sufficient. This should be described here or somewhere in this doc.
--
Regards,
Laurent Pinchart
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^ permalink raw reply
* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: zhangfei @ 2016-11-22 9:34 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <2220300.Yj4lYzeH2z@wuerfel>
Hi, Arnd
On 2016年11月22日 16:50, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
>> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
>> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
>> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
>> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
>> +};
>> +
>> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
>> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
>> + .channels = hi3660_iomcu_rst,
>> +};
>> +
>> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
>> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
>> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
>> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
>> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
>> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
>> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
>> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
>> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
>> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
>> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
>> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
>> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
>> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
>> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
>> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
>> +};
> I think you can avoid the trap of the ABI incompatibility if
> you just define those as in the binding as tuples, using #reset-cells=2.
>
> In particular for the first set, it seems really silly to redefine
> the numbers when there is just a simple integer number.
Could you clarify more, still not understand.
The number is index of the arrays, and the index will be used in dts.
The arrays lists the registers offset and bit shift.
For example:
[HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.
And Documentation/devicetree/bindings/reset/reset.txt
Required properties:
#reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
with a single reset output and 1 for nodes with multiple
reset outputs.
Thanks
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^ permalink raw reply
* Re: [PATCH V2 2/2] pinctrl: tegra: Add driver to configure voltage and power of io pads
From: Laxman Dewangan @ 2016-11-22 9:32 UTC (permalink / raw)
To: Joe Perches, Jon Hunter, linus.walleij, robh+dt, mark.rutland,
swarren, thierry.reding
Cc: gnurou, yamada.masahiro, linux-gpio, devicetree, linux-tegra,
linux-kernel
In-Reply-To: <1479807957.1942.9.camel@perches.com>
On Tuesday 22 November 2016 03:15 PM, Joe Perches wrote:
> On Tue, 2016-11-22 at 13:45 +0530, Laxman Dewangan wrote:
>> On Tuesday 22 November 2016 02:31 AM, Jon Hunter wrote:
>>> On 09/11/16 13:06, Laxman Dewangan wrote:
>>> + _entry_(32, "uart", UART, true, "vddio-uart"), \
>>> + _entry_(33, "usb0", USB0, true, NULL), \
>>> + _entry_(34, "usb1", USB1, true, NULL), \
>>> + _entry_(35, "usb2", USB2, true, NULL), \
>>> + _entry_(36, "usb3", USB3, true, NULL), \
>>> + _entry_(37, "usb-bias", USB_BIAS, true, NULL)
>>> Can you also fix these checkpatch errors ...
>>>
>>> ERROR: Macros with complex values should be enclosed in parentheses
>>> #424: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:350:
>>>
>>> ERROR: Macros with complex values should be enclosed in parentheses
>>> #456: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:382:
>> I can fix this but will still have the error as:
>>
>> CHECK: Macro argument reuse '_entry_' - possible side-effects?
>> #425: FILE: drivers/pinctrl/tegra/pinctrl-tegra-io-pad.c:425:
>>
>>
>> And there is no better way to fix this.
> It's a stupid little script, feel free to ignore it.
And when I tried to add the parenthesis, it failed in compilation.
So in this case, we just need to ignore the error of
Macros with complex values should be enclosed in parentheses
^ permalink raw reply
* Re: [PATCH 1/6] reset: hisilicon: add reset core
From: zhangfei @ 2016-11-22 9:22 UTC (permalink / raw)
To: Arnd Bergmann
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <3993565.nedzUBZcVS@wuerfel>
Hi, Arnd
On 2016年11月22日 16:45, Arnd Bergmann wrote:
> On Tuesday, November 22, 2016 3:49:16 PM CET Zhangfei Gao wrote:
>> @@ -1,8 +1,8 @@
>> obj-y += core.o
>> -obj-y += hisilicon/
>> obj-$(CONFIG_ARCH_STI) += sti/
>> obj-$(CONFIG_RESET_ATH79) += reset-ath79.o
>> obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o
>> +obj-$(CONFIG_ARCH_HISI) += hisilicon/
>> obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
>> obj-$(CONFIG_RESET_MESON) += reset-meson.o
>> obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
> Please leave the obj-y line, otherwise the COMPILE_TEST variant won't work.
COMPILE_TEST is added in drivers/reset/hisilicon/Kconfig
like
config COMMON_RESET_HI3660
tristate "Hi3660 Reset Driver"
depends on ARCH_HISI || COMPILE_TEST
The reason not using "obj-y" here is that reset.c will be compiled unconditionally.
drivers/reset/hisilicon/Makefile
obj-y += reset.o
Thanks
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^ permalink raw reply
* RE: [PATCH V3 1/4] Documentation: pv88080: Move binding document
From: Eric Hyeung Dong Jeong @ 2016-11-22 9:20 UTC (permalink / raw)
To: Rob Herring, Eric Hyeung Dong Jeong
Cc: DEVICETREE, LINUX-KERNEL, Mark Rutland, Alexandre Courbot,
LINUX-GPIO, Lee Jones, Liam Girdwood, Linus Walleij, Mark Brown,
Support Opensource
In-Reply-To: <20161118153842.bbcmfczxvrwamlqs@rob-hp-laptop>
On Saturday, November 19, 2016 12:39 AM, Rob Herring wrote:
> On Fri, Nov 18, 2016 at 09:35:46AM +0900, Eric Jeong wrote:
> >
> > From: Eric Jeong <eric.jeong.opensource@diasemi.com>
> >
> > The change is to move pv88080 binding document from the regulator
> > directory to mfd binding directory for PV88080 PMIC MFD support.
> > And, GPIO properties are added.
> >
> >
> > Signed-off-by: Eric Jeong <eric.jeong.opensource@diasemi.com>
> >
> > ---
> > This patch applies against linux-next and next-20161117
> >
> > Hi,
> >
> > Change since PATCH V2
> > - Added property and description for gpio
> >
> > Change since PATCH V1
> > - Patch separated from PATCH V1
> >
> > Regards,
> > Eric Jeong, Dialog Semiconductor Ltd.
> >
> >
> > .../bindings/{regulator => mfd}/pv88080.txt | 16 +++++++++++++++-
> > 1 file changed, 15 insertions(+), 1 deletion(-) rename
> > Documentation/devicetree/bindings/{regulator => mfd}/pv88080.txt (79%)
> >
> > diff --git a/Documentation/devicetree/bindings/regulator/pv88080.txt
> > b/Documentation/devicetree/bindings/mfd/pv88080.txt
> > similarity index 79%
> > rename from Documentation/devicetree/bindings/regulator/pv88080.txt
> > rename to Documentation/devicetree/bindings/mfd/pv88080.txt
> > index e6e4b9c8..7e24f95 100644
> > --- a/Documentation/devicetree/bindings/regulator/pv88080.txt
> > +++ b/Documentation/devicetree/bindings/mfd/pv88080.txt
> > @@ -1,4 +1,4 @@
> > -* Powerventure Semiconductor PV88080 Voltage Regulator
> > +* Powerventure Semiconductor PV88080 PMIC
> >
> > Required properties:
> > - compatible: Must be one of the following, depending on the @@ -16,8
> > +16,15 @@ Required properties:
> > standard binding for regulators; see regulator.txt.
> > BUCK1, BUCK2, BUCK3 and HVBUCK.
> >
> > +- gpio-controller: Marks the device node as a GPIO controller.
> > +- #gpio-cells: Should be 2. See gpio.txt in this directory
> > + for a description of the cells format.
> > +
> > Optional properties:
> > +- ngpios : Number of in-use slots of available slots for GPIO.
> > + Maximum is 2.
> > - Any optional property defined in regulator.txt
> > + and gpio.txt for more information.
> >
> > Example:
> >
> > @@ -27,6 +34,13 @@ Example:
> > interrupt-parent = <&gpio>;
> > interrupts = <24 24>;
> >
> > + gpioex {
>
> gpio-controller {
>
> > + compatible = "pvs,pv88080-gpio";
>
> Is this documented?
No, It's not documented. I will update this document with the compatible string.
>
> > + gpio-controller;
> > + #gpio-cells = <2>;
> > + ngpios = <2>;
> > + };
> > +
> > regulators {
> > BUCK1 {
> > regulator-name = "buck1";
> > --
> > end-of-patch for PATCH V3
> >
^ permalink raw reply
* RE: [PATCH v3] ARM: at91/dt: add dts file for sama5d36ek CMP board
From: Wenyou.Yang-UWL1GkI3JZL3oGB3hsPCZA @ 2016-11-22 9:11 UTC (permalink / raw)
To: alexandre.belloni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
Cc: nicolas.ferre-AIFe0yeh4nAAvxtiuMwx3w,
linux-lFZ/pmaqli7XmaaqVzeoHQ, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
pawel.moll-5wv7dgnIgG8, mark.rutland-5wv7dgnIgG8,
ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <20161121140248.utlir6krokjeeobi-m++hUPXGwpdeoWH0uzbU5w@public.gmane.org>
> -----Original Message-----
> From: Alexandre Belloni [mailto:alexandre.belloni@free-electrons.com]
> Sent: 2016年11月21日 22:03
> To: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>
> Cc: Nicolas Ferre <nicolas.ferre@atmel.com>; Russell King
> <linux@arm.linux.org.uk>; Rob Herring <robh+dt@kernel.org>; Pawel Moll
> <pawel.moll@arm.com>; Mark Rutland <mark.rutland@arm.com>; Ian Campbell
> <ijc+devicetree@hellion.org.uk>; Kumar Gala <galak@codeaurora.org>; linux-
> kernel@vger.kernel.org; Wenyou Yang - A41535
> <Wenyou.Yang@microchip.com>; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH v3] ARM: at91/dt: add dts file for sama5d36ek CMP board
>
> Hi,
>
> I fixed it up this time but please use the proper subject prefix next time (ARM: dts:
> at91:).
Thank you.
I keep it in mind.
>
> On 21/11/2016 at 13:14:42 +0800, Wenyou Yang wrote :
> > The sama5d36ek CMP board is the variant of sama5d3xek board.
> > It is equipped with the low-power DDR2 SDRAM, PMIC ACT8865 and some
> > power rail. Its main purpose is used to measure the power consumption.
> > The difference of the sama5d36ek CMP dts from sama5d36ek dts is listed
> > as below.
> > 1. The USB host nodes are removed, that is, the USB host is disabled.
> > 2. The gpio_keys node is added to wake up from the sleep.
> > 3. The LCD isn't supported due to the pins for LCD are conflicted
> > with gpio_keys.
> > 4. The adc0 node support the pinctrl sleep state to fix the over
> > consumption on VDDANA.
> >
> > As said in errata, "When the USB host ports are used in high speed
> > mode (EHCI), it is not possible to suspend the ports if no device is
> > attached on each port. This leads to increased power consumption even
> > if the system is in a low power mode." That is why the the USB host is
> > disabled.
> >
> > Signed-off-by: Wenyou Yang <wenyou.yang@atmel.com>
> > ---
> >
> > Changes in v3:
> > - Use a dual license scheme for DT files.
> > - Use the proper model name and the compatible string to reflect
> > the nature of this new "CMP" board.
> > - Change name of wakeup property to "wakeup-source".
> > - Remove unnecessary comments.
> > - Remove bootargs.
> >
> > Changes in v2:
> > - Add the pinctrl sleep state for adc0 node to fix the over
> > consumption on VDDANA.
> > - Improve the commit log.
> >
> > arch/arm/boot/dts/sama5d36ek_cmp.dts | 87 ++++++++++
> > arch/arm/boot/dts/sama5d3xcm_cmp.dtsi | 201 +++++++++++++++++++++++
> > arch/arm/boot/dts/sama5d3xmb_cmp.dtsi | 301
> > ++++++++++++++++++++++++++++++++++
> > 3 files changed, 589 insertions(+)
> > create mode 100644 arch/arm/boot/dts/sama5d36ek_cmp.dts
> > create mode 100644 arch/arm/boot/dts/sama5d3xcm_cmp.dtsi
> > create mode 100644 arch/arm/boot/dts/sama5d3xmb_cmp.dtsi
> >
> Applied, thanks.
>
> --
> Alexandre Belloni, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
Best Regards,
Wenyou Yang
^ permalink raw reply
* Re: [PATCH 2/2] phy: qcom-qmp: new qmp phy driver for qcom-chipsets
From: Kishon Vijay Abraham I @ 2016-11-22 9:09 UTC (permalink / raw)
To: Vivek Gautam
Cc: robh+dt, Mark Rutland, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm
In-Reply-To: <CAFp+6iFhJ245YEuLNd0jOOLVtf=_GFaD12PdiM__-32W==WRTQ@mail.gmail.com>
Hi,
On Tuesday 22 November 2016 01:17 PM, Vivek Gautam wrote:
> Hi Kishon,
>
>
> On Thu, Nov 10, 2016 at 2:33 PM, Vivek Gautam
> <vivek.gautam@codeaurora.org> wrote:
>> Hi Kishon,
>>
>
>>>> +unsigned int msm8996_pciephy_tx_offsets[] = { 0x1000, 0x2000, 0x3000 };
>>>> +unsigned int msm8996_pciephy_rx_offsets[] = { 0x1200, 0x2200, 0x3200 };
>>>> +unsigned int msm8996_pciephy_pcs_offsets[] = { 0x1400, 0x2400, 0x3400 };
>
>>> you can have a separate reg map for each lane and all these can come from dt.
>>
>> The idea is to avoid the any child nodes for lanes. So, we have the complete
>> ioremaped region and these offsets to tx, rx and pcs blocks.
>
> I don't see benefits in using regmap for different lanes.
> Do you see benefits in replacing a bunch of readl()/writel() with
> regmap_read()/regmap_update_bits()/regmap_write() ?
By reg map, I meant register spaces allocated for different lanes.
>
> I can as well use separate 'reg' values for each lanes, and have the offsets
> come from dt. Something like below :
>
> - reg: array of offset and length of the PHY register sets.
> at index 0: offset and length of register set for PHY common
> serdes block.
> from index 1 - N: offset and length of register set for each lane,
> for N number of phy lanes (ports).
> - lane-offsets: array of offsets to tx, rx and pcs blocks for phy lanes.
>
> Example:
> pcie_phy: pciephy@34000 {
> compatible = "qcom,msm8996-qmp-pcie-phy";
> reg = <0x034000 0x48f>,
> <0x035000 5bf>,
> <0x036000 5bf>,
> <0x037000 5bf>;
> /* tx, rx, pcs */
> lane-offsets = <0x0 0x200 0x400>;
right, I meant something like this.
Thanks
Kishon
^ permalink raw reply
* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: Arnd Bergmann @ 2016-11-22 8:50 UTC (permalink / raw)
To: Zhangfei Gao
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-4-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>
> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
> +};
> +
> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
> + .channels = hi3660_iomcu_rst,
> +};
> +
> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
> +};
I think you can avoid the trap of the ABI incompatibility if
you just define those as in the binding as tuples, using #reset-cells=2.
In particular for the first set, it seems really silly to redefine
the numbers when there is just a simple integer number.
Arnd
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^ permalink raw reply
* Re: [PATCH V2 1/2] regulator: pwm: DT: Add ramp delay for exponential voltage transition
From: Laxman Dewangan @ 2016-11-22 8:50 UTC (permalink / raw)
To: Rob Herring
Cc: broonie-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Douglas Anderson,
Aleksandr Frid
In-Reply-To: <20161121161727.y6pvydowiyeyy7qs@rob-hp-laptop>
On Monday 21 November 2016 09:47 PM, Rob Herring wrote:
> On Fri, Nov 18, 2016 at 08:05:55PM +0530, Laxman Dewangan wrote:
>> Some PWM regulator has the exponential transition in voltage change as
>> opposite to fixed slew-rate linear transition on other regulators.
>> For such PWM regulators, add the property to tell that voltage change
>> is exponential and having fixed delay for any level of change.
>>
>> Signed-off-by: Laxman Dewangan <ldewangan-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>> CC: Douglas Anderson <dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
>> CC: Aleksandr Frid <afrid-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
>>
>> ---
>> This patch is continuation of discussion on patch
>> regulator: pwm: Fix regulator ramp delay for continuous mode
>> https://patchwork.kernel.org/patch/9216857/
>> where is it discussed to have separate property for PWM which has
>> exponential voltage transition.
>>
>> Changes from V1:
>> - Pass the flag to tell that voltage ramp is exponential instead of
>> providing delay.
>> ---
>> .../devicetree/bindings/regulator/pwm-regulator.txt | 12 ++++++++++++
>> 1 file changed, 12 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> index 3aeba9f..2d9ef3a 100644
>> --- a/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> +++ b/Documentation/devicetree/bindings/regulator/pwm-regulator.txt
>> @@ -54,6 +54,18 @@ Optional properties:
>> --------------------
>> - enable-gpios: GPIO to use to enable/disable the regulator
>>
>> +- voltage-ramp-exponential: Boolean, Some of PWM regulator has the exponential
>> + transition in voltage ramp as opposite to fixed
>> + slew-rate linear transition on other regulators.
>> + For such PWM regulator, presence of this property will
>> + tell that value of the regulator ramp delay provided by
>> + DT property "regulator-ramp-delay" is exponential and
>> + fixed delay for any voltage level change.
>> + If PWM regulator supports the fixed linear slew rate
>> + then this property should be absent from DT node and
>> + property "regulator-ramp-delay" is used as linear slew
>> + rate.
> Sorry, but on further thought, I don't think we should mix different
> units for the same property. Also, the fact that the ramp is exponential
> is irrelevant. You just want an absolute delay time rather than a rate,
> right? So instead, how about just "regulator-ramp-time-us". Roughly what
> you had in v1, but not PWM specific.
Can we say "regulator-settling-time-us" and make it generic i.e. part of
the regulator core instead of PWM regulator specific?
So no change for "regulator-ramp-delay".
new property "regulator-settling-time-us" for fixed settling time in any
voltage level change.
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^ permalink raw reply
* Re: [PATCH 5/6] reset: hisilicon: Use new driver reset-hi6222
From: Arnd Bergmann @ 2016-11-22 8:49 UTC (permalink / raw)
To: Zhangfei Gao
Cc: Philipp Zabel, Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479800961-6249-6-git-send-email-zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On Tuesday, November 22, 2016 3:49:20 PM CET Zhangfei Gao wrote:
>
> -#define PERIPH_RSTDIS0_MMC0 0x000
> -#define PERIPH_RSTDIS0_MMC1 0x001
> -#define PERIPH_RSTDIS0_MMC2 0x002
> -#define PERIPH_RSTDIS0_NANDC 0x003
> -#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
> -#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
> -#define PERIPH_RSTDIS0_USBOTG 0x006
> -#define PERIPH_RSTDIS0_USBOTG_32K 0x007
> -#define PERIPH_RSTDIS1_HIFI 0x100
> -#define PERIPH_RSTDIS1_DIGACODEC 0x105
> +/* reset in sysctrl */
> +#define PERIPH_RSTDIS0_MMC0 0
> +#define PERIPH_RSTDIS0_MMC1 1
> +#define PERIPH_RSTDIS0_MMC2 2
> +#define PERIPH_RSTDIS0_NANDC 3
> +#define PERIPH_RSTDIS0_USBOTG_BUS 4
> +#define PERIPH_RSTDIS0_POR_PICOPHY 5
> +#define PERIPH_RSTDIS0_USBOTG 6
> +#define PERIPH_RSTDIS0_USBOTG_32K 7
> +#define PERIPH_RSTDIS1_HIFI 8
You can't redefined the binding here, this is part of the ABI.
You can however add new numbers as long as the old ones keep
working.
Arnd
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