* Re: [RFC PATCH] ARM: dts: Add support for Turris Omnia
From: Uwe Kleine-König @ 2016-11-23 8:19 UTC (permalink / raw)
To: Tomas Hlavacek
Cc: Rob Herring, Mark Rutland, Russell King, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479859770-9375-1-git-send-email-tmshlvck-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
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Hello Tomas,
calling it v4 would be nice.
On Wed, Nov 23, 2016 at 01:09:20AM +0100, Tomas Hlavacek wrote:
> Turris Omnia board by CZ.NIC:
>
> * Marvell Armada 385 SoC
> * 1 or 2 GB DDR3
> * eMMC
> * 8 MB SPI flash (U-Boot and rescue Linux image)
> * 88E1514 PHY
> * 88E6176 Ethernet switch (not supported)
>
> Supported board revision: CZ11NIC13 (production board).
>
> Signed-off-by: Tomas Hlavacek <tmshlvck-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
As you picked my v3, you should keep my S-o-b.
> ---
> Changes since Uwe's version:
>
> - add MBUS regions (needed for Marvell CESA)
> - remove rtc disable (WFM with CZ11NIC13 = production board)
If I do
mw 0xf10184a0 0xfd4d4cfa
in the boot loader, it seems to work for me, too. You don't need that?
> - cleanup comments
>
> Unsupported peripherals:
> - MV88E7176 switch
> - SFP
> - LEDs
LEDs is not that bad IMHO, because they work. You just cannot change
their function, but they blink according to their default trigger.
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/armada-385-turris-omnia.dts | 279 ++++++++++++++++++++++++++
> 2 files changed, 280 insertions(+)
> create mode 100644 arch/arm/boot/dts/armada-385-turris-omnia.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index befcd26..f1d3b9ff 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -920,6 +920,7 @@ dtb-$(CONFIG_MACH_ARMADA_38X) += \
> armada-385-db-ap.dtb \
> armada-385-linksys-caiman.dtb \
> armada-385-linksys-cobra.dtb \
> + armada-385-turris-omnia.dtb \
> armada-388-clearfog.dtb \
> armada-388-db.dtb \
> armada-388-gp.dtb \
> diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> new file mode 100644
> index 0000000..5ef3d62
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> @@ -0,0 +1,279 @@
> +/*
> + * Device Tree file for the Turris Omnia
> + * Schematic available at https://www.turris.cz/doc/_media/rtrom01-schema.pdf
> + *
> + * Copyright (C) 2016 Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
> + * Copyright (C) 2016 Tomas Hlavacek <tmshlvkc-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without
> + * any warranty of any kind, whether express or implied.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include "armada-385.dtsi"
> +
> +/ {
> + model = "Turris Omnia";
> + compatible = "cznic,turris-omnia", "marvell,armada385", \
> + "marvell,armada380";
You don't need a \ here AFAIK.
> +
> + chosen {
> + stdout-path = &uart0;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x00000000 0x40000000>; /* 1024 MB */
> + };
> +
> + soc {
> + ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
> + MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
> + MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
> + MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
> +
> + internal-regs {
> +
> + /* USB part of the PCIe2/USB 2.0 port */
> + usb@58000 {
> + status = "okay";
> + };
> +
> + sata@a8000 {
> + status = "okay";
> + };
> +
> + sdhci@d8000 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&sdhci_pins>;
> + status = "okay";
> +
> + bus-width = <8>;
> + no-1-8-v;
> + non-removable;
> + };
> +
> + usb3@f0000 {
> + status = "okay";
> + };
> +
> + usb3@f8000 {
> + status = "okay";
> + };
> + };
> +
> + pcie-controller {
> + status = "okay";
> +
> + pcie@1,0 {
> + /* Port 0, Lane 0 */
> + status = "okay";
> + };
> +
> + pcie@2,0 {
> + /* Port 1, Lane 0 */
> + status = "okay";
> + };
> +
> + pcie@3,0 {
> + /* Port 2, Lane 0 */
> + status = "okay";
> + };
> + };
> + };
> +};
> +
> +/* Connected to 88E6176 switch, port 6 */
> +ð0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ge0_rgmii_pins>;
> + status = "okay";
> + phy-mode = "rgmii-id";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +/* Connected to 88E6176 switch, port 5 */
> +ð1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ge1_rgmii_pins>;
> + status = "okay";
> + phy-mode = "rgmii-id";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> +
> +/* WAN port */
> +ð2 {
> + status = "okay";
> + phy-mode = "sgmii";
> + phy = <&phy1>;
> +};
> +
> +&i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&i2c0_pins>;
> + status = "okay";
> +
> + i2cmux@70 {
> + compatible = "nxp,pca9547";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x70>;
> + status = "okay";
> +
> + i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + status = "okay";
> +
> + /* STM32F0 command interface at address 0x2a.
> + * STM32F0 LED interface at address 0x2b.
> + */
Should this better be:
/*
* STM32F0 command interface at address 0x2a.
* STM32F0 LED interface at address 0x2b.
*/
As is recommended for comments in .c?
> +
> + eeprom@54 {
> + compatible = "at,24c64";
> + reg = <0x54>;
> +
> + /* The EEPROM contains data for bootloader.
> + * Contents:
> + * struct omnia_eeprom {
> + * u32 magic; (=0x0341a034)
> + * u32 ramsize;
ramsize in GiB?
> + * char region[4] (=0x0);
This is for the WLAN regdomain, right?
> + * u32 crc32;
> + * };
> + */
ditto for the comment format.
> + };
> + };
> +
> + /* Channel 1: Routed to PCIe0/mSATA connector (CN7A).
> + * Channel 2: Routed to PCIe1/USB2 connector (CN61A).
> + * Channel 3: Routed to PCIe2 connector (CN62A).
> + * Channel 4: Routed to SFP+.
> + * Channel 5: ATSHA204A at address 0x64.
> + * Channel 6: Routed to user pin header CN11.
> + */
I'd like to keep the busses as Andrew already pointed out. For example
this might make it possible to use i2c-tools to read out the mac address
from the ATSHA.
> + i2c@7 {
> + /* GPIO expander for SFP+ signals */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <7>;
> +
> + wangpio: gpio@71 {
> + compatible = "nxp,pca9538";
> + reg = <0x71>;
> + interrupt-parent = <&gpio1>;
> + interrupts = <14 IRQ_TYPE_LEVEL_LOW>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> + };
> + };
> +};
> +
> +&mdio {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mdio_pins>;
> + status = "okay";
> +
> + phy1: phy@1 {
> + status = "okay";
> + compatible = "ethernet-phy-id0141.0DD1", \
> + "ethernet-phy-ieee802.3-c22";
Drop the \
> + reg = <1>;
> + /* IRQ is connected to PCA9538 pin 7. Currently it
> + * can not be utilized.
> + */
> + };
> +
> + /* Switch MV88E7176 at address 0x10. */
> +};
> +
> +&pinctrl {
> + spi0cs1_pins: spi0-pins-0cs1 {
> + marvell,pins = "mpp26";
> + marvell,function = "spi0";
> + };
Why did you drop the pcawan pinctrl?
> +};
> +
> +&spi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0_pins &spi0cs1_pins>;
Oh, this is wrong (already in my patch): this is cs0 not cs1.
> + status = "okay";
> +
> + spi-nor@0 {
> + compatible = "spansion,s25fl164k", "jedec,spi-nor";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> +
> + partition@0 {
> + reg = <0x0 0x00100000>;
> + label = "U-Boot";
> + };
> +
> + partition@1 {
> + reg = <0x00100000 0x00700000>;
> + label = "Rescue system";
> + };
> + };
> +
> + /* SPI0 + CS1 (MPP26) is routed to a pin header CN11. */
Looks strange. What about
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
Maybe also add the node for this pin to &pinctrl, but don't use it in
&spi0.pinctrl-0? This would nicely document the MPP26 part.
> +};
> +
> +&uart0 {
> + /* Pin header CN10. */
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + /* Pin header CN11. */
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "okay";
> +};
> +
Trailing new line
Best regards
Uwe
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^ permalink raw reply
* Re: [PATCH 5/7] add bindings for stm32 IIO timer drivers
From: Benjamin Gaignard @ 2016-11-23 8:17 UTC (permalink / raw)
To: Lee Jones
Cc: Lars-Peter Clausen, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Mark Rutland,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux Kernel Mailing List, Thierry Reding,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, Peter Meerwald-Stadler,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <20161122171820.GL10134-Re9dqnLqz4GzQB+pC5nmwQ@public.gmane.org>
If it is ok for you I will add "id" parameter in mfd driver and
forward it to the sub-devices drivers
to be able to distinguish the hardware blocks
2016-11-22 18:18 GMT+01:00 Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>:
> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>
>> [snip]
>> >> + "st,stm32-iio-timer5"
>> >> + "st,stm32-iio-timer6"
>> >> + "st,stm32-iio-timer7"
>> >> + "st,stm32-iio-timer8"
>> >> + "st,stm32-iio-timer9"
>> >> + "st,stm32-iio-timer10"
>> >> + "st,stm32-iio-timer11"
>> >> + "st,stm32-iio-timer12"
>> >> + "st,stm32-iio-timer13"
>> >> + "st,stm32-iio-timer14"
>> >
>> > We can't do this. This is a binding for a driver, not for the hardware.
>> >
>>
>> Unfortunately each instance for the hardware IP have little
>> differences like which triggers they could accept or size of the
>> counter register,
>> and I doesn't have value inside the hardware to distinguish them so
>> the only way I found is to use compatible.
>
> Can't you represent these as properties?
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
--
Benjamin Gaignard
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Linaro.org │ Open source software for ARM SoCs
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^ permalink raw reply
* Re: [PATCH 1/7] add binding for stm32 multifunctions timer driver
From: Benjamin Gaignard @ 2016-11-23 8:15 UTC (permalink / raw)
To: Lee Jones
Cc: robh+dt, Mark Rutland, alexandre.torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, linux-pwm, jic23,
knaack.h, Lars-Peter Clausen, Peter Meerwald-Stadler, linux-iio,
linux-arm-kernel, Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen,
Linus Walleij, Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <20161122165228.GK10134@dell.home>
2016-11-22 17:52 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Tue, 22 Nov 2016, Benjamin Gaignard wrote:
>
>> Add bindings information for stm32 timer MFD
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../devicetree/bindings/mfd/stm32-timer.txt | 53 ++++++++++++++++++++++
>> 1 file changed, 53 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-timer.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
>> new file mode 100644
>> index 0000000..3cefce1
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/stm32-timer.txt
>> @@ -0,0 +1,53 @@
>> +STM32 multifunctions timer driver
>
> "STM32 Multi-Function Timer/PWM device bindings"
>
> Doesn't this shared device have a better name?
In SoC documentation those hardware blocks are named "advanced-control
timers", "general purpose timers" or "basic timers"
"stm32-timer" name is already used for clock source driver, that why I
have prefix it with mfd
>
>> +stm32 timer MFD allow to handle at the same time pwm and IIO timer devices
>
> No need for this sentence.
>
OK
>> +Required parameters:
>> +- compatible: must be one of the follow value:
>> + "st,stm32-mfd-timer1"
>> + "st,stm32-mfd-timer2"
>> + "st,stm32-mfd-timer3"
>> + "st,stm32-mfd-timer4"
>> + "st,stm32-mfd-timer5"
>> + "st,stm32-mfd-timer6"
>> + "st,stm32-mfd-timer7"
>> + "st,stm32-mfd-timer8"
>> + "st,stm32-mfd-timer9"
>> + "st,stm32-mfd-timer10"
>> + "st,stm32-mfd-timer11"
>> + "st,stm32-mfd-timer12"
>> + "st,stm32-mfd-timer13"
>> + "st,stm32-mfd-timer14"
>
> We don't normally number devices.
>
> What's stopping you from simply doing:
>
> pwm1: pwm1@40010000 {
> compatible = "st,stm32-pwm";
> };
> pwm2: pwm1@40020000 {
> compatible = "st,stm32-pwm";
> };
> pwm3: pwm1@40030000 {
> compatible = "st,stm32-pwm";
> };
>
Because each instance of the hardware is slightly different: number of
pwm channels, triggers capabilities, etc ..
so I need to distinguish them.
Since it look to be a problem I will follow your suggestion and add a
property this driver to be able to identify each instance.
Do you think that "id" parameter (integer for 1 to 14) is acceptable ?
>> +- reg : Physical base address and length of the controller's
>> + registers.
>> +- clock-names: Set to "mfd_timer_clk".
>
Only one but I use devm_regmap_init_mmio_clk() to avoid calling
clk_{enable/disable}
everywhere in the drivers when reading/writing regsister.
devm_regmap_init_mmio_clk() find the clock by it name that why I have
put it here
In the doc this clock in named "clk_int" I will use this name.
> How many clocks are there?
>
> If only 1, you don't need this property.
>
> "mfd_timer_clk" is not the correct name.
>
> What is it called in the datasheet?
>
>> +- clocks: Phandle of the clock used by the timer module.
>
> "Phandle to the clock ..."
>
>> + For Clk properties, please refer to [1].
>> +- interrupts : Reference to the timer interrupt
>
> Reference to?
>
> See how other binding documents describe this property.
>
>> +Optional parameters:
>> +- resets : Reference to a reset controller asserting the timer
>
> As above.
>
>> +Optional subnodes:
>
> Either use ":" or " :" or "<tab>:", but keep it consistent.
>
>> +- pwm: See Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>> +- iiotimer: See Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>> +
>> +[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
>
> Use the relative paths "../clock/", "../pwm/", "../iio/".
>
OK
>> +Example:
>> + mfd_timer1: mfdtimer1@40010000 {
>
> This is not an "MFD timer". MFD is a Linuxisum.
>
>> + compatible = "st,stm32-mfd-timer1";
>
> Better description required.
>
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "mfd_timer_clk";
>> + interrupts = <27>;
>> +
>> + pwm1: pwm1@40010000 {
>> + compatible = "st,stm32-pwm1";
>> + };
>> +
>> + iiotimer1: iiotimer1@40010000 {
>> + compatible = "st,stm32-iio-timer1";
>> + };
>> + };
^ permalink raw reply
* Re: [PATCH v2 1/3] arm64: dts: add USB1-related nodes of Allwinner A64
From: Maxime Ripard @ 2016-11-23 8:08 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, Catalin Marinas, Will Deacon,
linux-kernel, Chen-Yu Tsai, Rob Herring, linux-arm-kernel
In-Reply-To: <20161122155831.8724-1-icenowy@aosc.xyz>
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On Tue, Nov 22, 2016 at 11:58:29PM +0800, Icenowy Zheng wrote:
> Allwinner A64 have two HCI USB controllers, a OTG controller and a USB
> PHY device which have two ports. One of the port is wired to both a HCI
> USB controller and the OTG controller, which is currently not supported.
> The another one is only wired to a HCI controller, and the device node of
> OHCI/EHCI controller of the port can be added now.
>
> Also the A64 USB PHY device node is also added for the HCI controllers to
> work.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes since v1:
> - Remove manual CLK_USB_OHCI0 gate, as it's dealed by ccu driver now.
> - Sort the nodes and fixed {e,o}hci1 regs.
> arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 44 +++++++++++++++++++++++++++
> 1 file changed, 44 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> index 3d70be3..2572dd6 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
> @@ -122,6 +122,50 @@
> #size-cells = <1>;
> ranges;
>
> + usbphy: phy@01c19400 {
> + compatible = "allwinner,sun50i-a64-usb-phy";
> + reg = <0x01c19400 0x14>,
> + <0x01c1b800 0x4>;
> + reg-names = "phy_ctrl",
> + "pmu1";
> + clocks = <&ccu CLK_USB_PHY0>,
> + <&ccu CLK_USB_PHY1>;
> + clock-names = "usb0_phy",
> + "usb1_phy";
> + resets = <&ccu RST_USB_PHY0>,
> + <&ccu RST_USB_PHY1>;
> + reset-names = "usb0_reset",
> + "usb1_reset";
> + status = "disabled";
> + #phy-cells = <1>;
> + };
> +
> + ohci1: usb@01c1b400 {
> + compatible = "allwinner,sun50i-a64-ohci", "generic-ohci";
> + reg = <0x01c1b400 0x100>;
> + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
> +
> + ehci1: usb@01c1b000 {
> + compatible = "allwinner,sun50i-a64-ehci", "generic-ehci";
> + reg = <0x01c1b000 0x100>;
> + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&ccu CLK_BUS_OHCI1>,
> + <&ccu CLK_BUS_EHCI1>,
> + <&ccu CLK_USB_OHCI1>;
> + resets = <&ccu RST_BUS_OHCI1>,
> + <&ccu RST_BUS_EHCI1>;
> + phys = <&usbphy 1>;
> + phy-names = "usb";
> + status = "disabled";
> + };
The nodes were inverted, also, please use "arm64: dts: allwinner:" for
your prefix in the future.
I fixed both issues and queued for 4.11.
Thanks!
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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* [RFC V2: PATCH 2/2] reset: hisilicon: add reset-hi3660
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: Philipp Zabel; +Cc: devicetree, linux-arm-kernel, Zhangfei Gao
In-Reply-To: <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org>
Add hi3660 reset driver
Reset offset & bits should be listed in dts
Like:
iomcu_rst: iomcu_rst_controller {
compatible = "hisilicon,hi3660-reset";
#reset-cells = <1>;
hisi,rst-syscon = <&iomcu>;
hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
0x20 0x10 /* 1: i2c1 */
0x20 0x20 /* 2: i2c2 */
0x20 0x8000000>; /* 3: i2c6 */
};
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
drivers/reset/hisilicon/Kconfig | 7 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset-hi3660.c | 144 +++++++++++++++++++++++++++++++++
3 files changed, 152 insertions(+)
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
index 1ff8b0c..10134dc 100644
--- a/drivers/reset/hisilicon/Kconfig
+++ b/drivers/reset/hisilicon/Kconfig
@@ -1,3 +1,10 @@
+config COMMON_RESET_HI3660
+ tristate "Hi3660 Reset Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ default ARCH_HISI
+ help
+ Build the Hisilicon Hi3660 reset driver.
+
config COMMON_RESET_HI6220
tristate "Hi6220 Reset Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
index c932f86..ab8a7bf 100644
--- a/drivers/reset/hisilicon/Makefile
+++ b/drivers/reset/hisilicon/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
+obj-$(CONFIG_COMMON_RESET_HI3660) += reset-hi3660.o
diff --git a/drivers/reset/hisilicon/reset-hi3660.c b/drivers/reset/hisilicon/reset-hi3660.c
new file mode 100644
index 0000000..3307252
--- /dev/null
+++ b/drivers/reset/hisilicon/reset-hi3660.c
@@ -0,0 +1,144 @@
+/*
+ * Copyright (c) 2016-2017 Linaro Ltd.
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset-controller.h>
+
+struct hi3660_reset_data {
+ unsigned int off;
+ unsigned int bits;
+};
+
+struct hi3660_reset_controller {
+ struct reset_controller_dev rst;
+ struct regmap *map;
+ const struct hi3660_reset_data *datas;
+};
+
+#define to_hi3660_reset_controller(_rst) \
+ container_of(_rst, struct hi3660_reset_controller, rst)
+
+static int hi3660_reset_program_hw(struct reset_controller_dev *rcdev,
+ unsigned long idx, bool assert)
+{
+ struct hi3660_reset_controller *rc = to_hi3660_reset_controller(rcdev);
+ const struct hi3660_reset_data *d;
+
+ if (idx >= rcdev->nr_resets)
+ return -EINVAL;
+
+ d = &rc->datas[idx];
+
+ if (assert)
+ return regmap_write(rc->map, d->off, d->bits);
+ else
+ return regmap_write(rc->map, d->off + 4, d->bits);
+}
+
+static int hi3660_reset_assert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hi3660_reset_program_hw(rcdev, idx, true);
+}
+
+static int hi3660_reset_deassert(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ return hi3660_reset_program_hw(rcdev, idx, false);
+}
+
+static int hi3660_reset_dev(struct reset_controller_dev *rcdev,
+ unsigned long idx)
+{
+ int err;
+
+ err = hi3660_reset_assert(rcdev, idx);
+ if (err)
+ return err;
+
+ return hi3660_reset_deassert(rcdev, idx);
+}
+
+static struct reset_control_ops hi3660_reset_ops = {
+ .reset = hi3660_reset_dev,
+ .assert = hi3660_reset_assert,
+ .deassert = hi3660_reset_deassert,
+};
+
+static int hi3660_reset_probe(struct platform_device *pdev)
+{
+ struct hi3660_reset_controller *rc;
+ struct device_node *np = pdev->dev.of_node;
+ struct device *dev = &pdev->dev;
+ struct hi3660_reset_data *datas;
+ const __be32 *list;
+ int size, nr, i;
+
+ rc = devm_kzalloc(dev, sizeof(*rc), GFP_KERNEL);
+ if (!rc)
+ return -ENOMEM;
+
+ rc->map = syscon_regmap_lookup_by_phandle(np, "hisi,rst-syscon");
+ if (IS_ERR(rc->map)) {
+ dev_err(dev, "failed to get hi3660,rst-syscon\n");
+ return PTR_ERR(rc->map);
+ }
+
+ list = of_get_property(np, "hisi,reset-bits", &size);
+ if (!list || (size / sizeof(*list)) % 2 != 0) {
+ dev_err(dev, "invalid DT reset description\n");
+ return -EINVAL;
+ }
+
+ nr = (size / sizeof(*list)) / 2;
+ datas = devm_kzalloc(dev, nr * sizeof(*datas), GFP_KERNEL);
+ if (!datas)
+ return -ENOMEM;
+
+ for (i = 0; i < nr; i++) {
+ datas[i].off = be32_to_cpup(list++);
+ datas[i].bits = be32_to_cpup(list++);
+ }
+
+ rc->rst.ops = &hi3660_reset_ops,
+ rc->rst.of_node = np;
+ rc->rst.nr_resets = nr;
+ rc->datas = datas;
+
+ return reset_controller_register(&rc->rst);
+}
+
+static const struct of_device_id hi3660_reset_match[] = {
+ { .compatible = "hisilicon,hi3660-reset", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hi3660_reset_match);
+
+static struct platform_driver hi3660_reset_driver = {
+ .probe = hi3660_reset_probe,
+ .driver = {
+ .name = "hi3660-reset",
+ .of_match_table = hi3660_reset_match,
+ },
+};
+
+static int __init hi3660_reset_init(void)
+{
+ return platform_driver_register(&hi3660_reset_driver);
+}
+arch_initcall(hi3660_reset_init);
+
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hi3660-reset");
+MODULE_DESCRIPTION("HiSilicon Hi3660 Reset Driver");
--
2.7.4
^ permalink raw reply related
* [RFC v2: PATCH 1/2] dt-bindings: Document the hi3660 reset bindings
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: Philipp Zabel; +Cc: devicetree, linux-arm-kernel, Zhangfei Gao
In-Reply-To: <1479888476-13138-1-git-send-email-zhangfei.gao@linaro.org>
Add DT bindings documentation for hi3660 SoC reset controller.
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
---
.../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
new file mode 100644
index 0000000..250daf2
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
@@ -0,0 +1,51 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi3660 SoC.
+
+Required properties:
+- compatible: should be
+ "hisilicon,hi3660-reset"
+- #reset-cells: 1, see below
+- hisi,rst-syscon: phandle of the reset's syscon.
+- hisi,reset-bits: Contains the reset control register information
+ Should contain 2 cells for each reset exposed to
+ consumers, defined as:
+ Cell #1 : offset from the syscon register base
+ Cell #2 : bits position of the control register
+
+Example:
+ iomcu: iomcu@ffd7e000 {
+ compatible = "hisilicon,hi3660-iomcu", "syscon";
+ reg = <0x0 0xffd7e000 0x0 0x1000>;
+ };
+
+ iomcu_rst: iomcu_rst_controller {
+ compatible = "hisilicon,hi3660-reset";
+ #reset-cells = <1>;
+ hisi,rst-syscon = <&iomcu>;
+ hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
+ 0x20 0x10 /* 1: i2c1 */
+ 0x20 0x20 /* 2: i2c2 */
+ 0x20 0x8000000>; /* 3: i2c6 */
+ };
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ i2c0: i2c@..... {
+ ...
+ resets = <&iomcu_rst 0>;
+ ...
+ };
+
+ i2c1: i2c@..... {
+ ...
+ resets = <&iomcu_rst 1>;
+ ...
+ };
--
2.7.4
^ permalink raw reply related
* [RFC V2:PATCH 0/2] add reset-hi3660
From: Zhangfei Gao @ 2016-11-23 8:07 UTC (permalink / raw)
To: Philipp Zabel; +Cc: devicetree, linux-arm-kernel, Zhangfei Gao
In-Reply-To: <Arnd Bergmann <arnd@arndb.de>
Considering Arnd and Philipp suggestions,
move reset register to dts as table instead of dts header in case of ABI issue
Zhangfei Gao (2):
dt-bindings: Document the hi3660 reset bindings
reset: hisilicon: add reset-hi3660
.../bindings/reset/hisilicon,hi3660-reset.txt | 51 ++++++++
drivers/reset/hisilicon/Kconfig | 7 +
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/reset-hi3660.c | 144 +++++++++++++++++++++
4 files changed, 203 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi3660-reset.txt
create mode 100644 drivers/reset/hisilicon/reset-hi3660.c
--
2.7.4
^ permalink raw reply
* Re: [PATCH] ARM: dts: sunxi: Enable UEXT related nodes for Olimex A20 SOM EVB
From: Maxime Ripard @ 2016-11-23 8:03 UTC (permalink / raw)
To: Emmanuel Vadot
Cc: mark.rutland, devicetree, linux, linux-kernel, wens, robh+dt,
linux-arm-kernel
In-Reply-To: <20161121164911.76900-1-manu@bidouilliste.com>
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On Mon, Nov 21, 2016 at 05:49:11PM +0100, Emmanuel Vadot wrote:
> UEXT are Universal EXTension connector from Olimex. They embed i2c, spi
> and uart pins along power in one connector and are found on most,
> if not all, Olimex boards.
> The Olimex A20 SOM EVB have two UEXT connector so enable the nodes found on
> those two connectors.
>
> Signed-off-by: Emmanuel Vadot <manu@bidouilliste.com>
Fixed the indentation of the spi pinctrl cells, and applied.
Please note that I'm note planning to send any new pull request, so
this will likely end up in 4.11.
Thanks!
Maxime
--
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Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 3/6] reset: hisilicon: add reset-hi3660
From: zhangfei @ 2016-11-23 8:02 UTC (permalink / raw)
To: Philipp Zabel, Arnd Bergmann
Cc: Rob Herring, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, Chen Feng, Xinliang Liu, Xia Qing,
Jiancheng Xue, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479810156.13701.1.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
Hi, Philipp
On 2016年11月22日 18:22, Philipp Zabel wrote:
> Am Dienstag, den 22.11.2016, 10:42 +0100 schrieb Arnd Bergmann:
>> On Tuesday, November 22, 2016 5:34:05 PM CET zhangfei wrote:
>>> On 2016年11月22日 16:50, Arnd Bergmann wrote:
>>>> On Tuesday, November 22, 2016 3:49:18 PM CET Zhangfei Gao wrote:
>>>>> +static const struct hisi_reset_channel_data hi3660_iomcu_rst[] = {
>>>>> + [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3),
>>>>> + [HI3660_RST_I2C1] = HISI_RST_SEP(0x20, 4),
>>>>> + [HI3660_RST_I2C2] = HISI_RST_SEP(0x20, 5),
>>>>> + [HI3660_RST_I2C6] = HISI_RST_SEP(0x20, 27),
>>>>> +};
>>>>> +
>>>>> +static struct hisi_reset_controller_data hi3660_iomcu_controller = {
>>>>> + .nr_channels = ARRAY_SIZE(hi3660_iomcu_rst),
>>>>> + .channels = hi3660_iomcu_rst,
>>>>> +};
>>>>> +
>>>>> +static const struct hisi_reset_channel_data hi3660_crgctrl_rst[] = {
>>>>> + [HI3660_RST_I2C3] = HISI_RST_SEP(0x78, 7),
>>>>> + [HI3660_RST_I2C4] = HISI_RST_SEP(0x78, 27),
>>>>> + [HI3660_RST_I2C7] = HISI_RST_SEP(0x60, 14),
>>>>> + [HI3660_RST_SD] = HISI_RST_SEP(0x90, 18),
>>>>> + [HI3660_RST_SDIO] = HISI_RST_SEP(0x90, 20),
>>>>> + [HI3660_RST_UFS] = HISI_RST_SEP(0x84, 12),
>>>>> + [HI3660_RST_UFS_ASSERT] = HISI_RST_SEP(0x84, 7),
>>>>> + [HI3660_RST_PCIE_SYS] = HISI_RST_SEP(0x84, 26),
>>>>> + [HI3660_RST_PCIE_PHY] = HISI_RST_SEP(0x84, 27),
>>>>> + [HI3660_RST_PCIE_BUS] = HISI_RST_SEP(0x84, 31),
>>>>> + [HI3660_RST_USB3OTG_PHY] = HISI_RST_SEP(0x90, 3),
>>>>> + [HI3660_RST_USB3OTG] = HISI_RST_SEP(0x90, 5),
>>>>> + [HI3660_RST_USB3OTG_32K] = HISI_RST_SEP(0x90, 6),
>>>>> + [HI3660_RST_USB3OTG_AHB] = HISI_RST_SEP(0x90, 7),
>>>>> + [HI3660_RST_USB3OTG_MUX] = HISI_RST_SEP(0x90, 8),
>>>>> +};
>>>> I think you can avoid the trap of the ABI incompatibility if
>>>> you just define those as in the binding as tuples, using #reset-cells=2.
>>>>
>>>> In particular for the first set, it seems really silly to redefine
>>>> the numbers when there is just a simple integer number.
>>> Could you clarify more, still not understand.
>>> The number is index of the arrays, and the index will be used in dts.
>>> The arrays lists the registers offset and bit shift.
>>> For example:
>>>
>>> [HI3660_RST_I2C0] = HISI_RST_SEP(0x20, 3), means register offset : 0x20, and bit shift = 3.
>>>
>>> And Documentation/devicetree/bindings/reset/reset.txt
>>> Required properties:
>>> #reset-cells: Number of cells in a reset specifier; Typically 0 for nodes
>>> with a single reset output and 1 for nodes with multiple
>>> reset outputs.
> This is just a suggestion, for reset controllers where the reset lines
> can reasonably be enumerated by a single integer. If there is a good
> reason to use more complicated bindings, more cells can be used.
> That being said, I dislike having to spread register/bit information
> throughout the device trees at the consumer/phandle sites, if the
> register/bit information absolutely has to be put into the device tree,
> I'd prefer a binding similar to ti-syscon, where it's all in one place.
Thanks for the suggestion.
Will use table in dts instead of
include/dt-bindings/reset/hisi,hi3660-resets.h
like
+ hisi,reset-bits = <0x20 0x8 /* 0: i2c0 */
+ 0x20 0x10 /* 1: i2c1 */
+ 0x20 0x20 /* 2: i2c2 */
+ 0x20 0x8000000>; /* 3: i2c6 */
To remove the potential ABI issue as pointed by Arnd.
>
>> You can easily enumerate the registers that contain reset bits here,
>> so just use one cell for the register and another one for the index.
> Changing the reset cells is an incompatible change, and this is not a
> straight forward register/bit mapping in hardware either. There are
> currently three registers involved: enable (+0x0), disable (+0x4), and
> status (+0x8). Also, what if in the future one of these reset bits have
> to be handled inverted (as just happened for hi3519)?
Discussed with Jianchen, we are only considering Kirin series now.
The inverted in hi3519 is only for some line, not the whole controller.
It is more like a bug and kirin does not have such issue.
Will send a new RFC, help take a look.
Thanks
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* Re: [PATCH 3/3] ARM: dts: sunxi: enable SDIO Wi-Fi on Orange Pi Zero
From: Maxime Ripard @ 2016-11-23 7:59 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, Vishnu Patekar, Arnd Bergmann,
Jonathan Corbet, Andre Przywara, linux-doc, Russell King,
linux-kernel, Hans de Goede, Chen-Yu Tsai, linux-arm-kernel
In-Reply-To: <20161121162421.800-3-icenowy@aosc.xyz>
[-- Attachment #1.1: Type: text/plain, Size: 2865 bytes --]
Hi,
On Tue, Nov 22, 2016 at 12:24:21AM +0800, Icenowy Zheng wrote:
> There's a Allwinner's XR819 SDIO Wi-Fi module soldered on the board of
> Orange Pi Zero, which used a dedicated regulator to power.
>
> Add the device tree node of the regulator, the enable gpio (with
> mmc-pwrseq) and the sdio controller.
>
> There's a out-of-tree driver tested to work with this device tree.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> New patch in the patchset, since a out-of-tree working xradio driver is done.
>
> If there is any problem in this patch, it can be omitted.
No particular problem with this one, however it can and should be
merged with the previous one.
Minor comments below though.
>
> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 42 ++++++++++++++++++++++++
> 1 file changed, 42 insertions(+)
>
> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> index b428e47..39cac26 100644
> --- a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> @@ -79,6 +79,24 @@
> gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> };
> };
> +
> + reg_vcc_wifi: reg_vcc_wifi {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&vcc_wifi_pin_opi0>;
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi";
> + enable-active-high;
> + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + pinctrl-names = "default";
> + pinctrl-0 = <&wifi_pwrseq_pin_opi0>;
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
> + };
> };
>
> &ehci1 {
> @@ -95,6 +113,20 @@
> status = "okay";
> };
>
> +&mmc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins_a>;
> + vmmc-supply = <®_vcc_wifi>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +};
> +
> +&mmc1_pins_a {
> + allwinner,pull = <SUN4I_PINCTRL_PULL_UP>;
This should be bias-pull-up.
> +};
> +
> &ohci1 {
> status = "okay";
> };
> @@ -104,6 +136,11 @@
> pins = "PA17";
> function = "gpio_out";
> };
> +
> + vcc_wifi_pin_opi0: vcc_wifi_pin@0 {
> + allwinner,pins = "PA20";
This should be pins
> + allwinner,function = "gpio_out";
This should be function
> + };
> };
>
> &r_pio {
> @@ -111,6 +148,11 @@
> pins = "PL10";
> function = "gpio_out";
> };
> +
> + wifi_pwrseq_pin_opi0: wifi_pwrseq_pin@0 {
> + allwinner,pins = "PL7";
> + allwinner,function = "gpio_out";
And same thing here.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Maxime Ripard @ 2016-11-23 7:57 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Mark Rutland, devicetree, Vishnu Patekar, Arnd Bergmann,
Jonathan Corbet, Andre Przywara, linux-doc, Russell King,
linux-kernel, Hans de Goede, Chen-Yu Tsai, linux-arm-kernel
In-Reply-To: <20161121162421.800-2-icenowy@aosc.xyz>
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On Tue, Nov 22, 2016 at 12:24:20AM +0800, Icenowy Zheng wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC.
>
> Add a device tree file for it.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Changes since v2:
> - Use generic pinconf binding instead of legacy allwinner pinctrl binding.
> - removed uart3, which is not accessible on Orange Pi Zero.
> - Removed sun8i-h2plus.dtsi and make Orange Pi Zero dts directly include
> sun8i-h3.dtsi.
> - Removed allwinner,sun8i-h3 compatible.
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts | 137 +++++++++++++++++++++++
Ditto, h2-plus-orangepi-zero.
> 2 files changed, 138 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 802a10d..51a1dd7 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -834,6 +834,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-sinlinx-sina33.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> + sun8i-h2plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> new file mode 100644
> index 0000000..b428e47
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h2plus-orangepi-zero.dts
> @@ -0,0 +1,137 @@
> +/*
> + * Copyright (C) 2016 Icenowy Zheng <icenowy@aosc.xyz>
> + *
> + * Based on sun8i-h3-orangepi-one.dts, which is:
> + * Copyright (C) 2016 Hans de Goede <hdegoede@redhat.com>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "Xunlong Orange Pi Zero";
> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2plus";
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&leds_opi0>, <&leds_r_opi0>;
> +
> + pwr_led {
> + label = "orangepi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "orangepi:red:status";
> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&pio {
> + leds_opi0: led_pins@0 {
> + pins = "PA17";
> + function = "gpio_out";
> + };
> +};
> +
> +&r_pio {
> + leds_r_opi0: led_pins@0 {
> + pins = "PL10";
> + function = "gpio_out";
> + };
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> +};
I'm not sure you answered me on this one. Are those exposed on the
headers? why did you put them as disabled here?
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH v2 1/3] ARM: sunxi: add support for H2+ SoC
From: Maxime Ripard @ 2016-11-23 7:54 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Jonathan Corbet, Chen-Yu Tsai, Mark Rutland, Russell King,
Hans de Goede, Vishnu Patekar, Andre Przywara, Arnd Bergmann,
linux-doc, linux-arm-kernel, linux-kernel, devicetree
In-Reply-To: <20161121162421.800-1-icenowy@aosc.xyz>
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Hi,
On Tue, Nov 22, 2016 at 12:24:19AM +0800, Icenowy Zheng wrote:
> Allwinner H2+ is a quad-core Cortex-A7 SoC.
>
> It is very like H3, that they share the same SoC ID (0x1680), and H3
> memory maps as well as drivers works well on the SoC.
>
> Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz>
> ---
> Documentation/arm/sunxi/README | 4 ++++
> Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
> arch/arm/mach-sunxi/sunxi.c | 1 +
> 3 files changed, 6 insertions(+)
>
> diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
> index cd02433..1fe4d99c 100644
> --- a/Documentation/arm/sunxi/README
> +++ b/Documentation/arm/sunxi/README
> @@ -63,6 +63,10 @@ SunXi family
> + User Manual
> http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
>
> + - Allwinner H2+ (sun8i)
> + + No document available now, but is known to be working properly with
> + H3 drivers and memory map.
> +
I'm not sure the phrasing is right here. I would prefer something like:
"No document publicly available now, but looks very similar to the H3"
> - Allwinner H3 (sun8i)
> + Datasheet
> http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
> index 4d6467c..26b35a7 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.txt
> +++ b/Documentation/devicetree/bindings/arm/sunxi.txt
> @@ -13,6 +13,7 @@ using one of the following compatible strings:
> allwinner,sun8i-a33
> allwinner,sun8i-a83t
> allwinner,sun8i-h3
> + allwinner,sun8i-h2plus
h2-plus please.
Thanks!
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* Re: [PATCH 1/3] of: base: add support to get machine compatible string
From: Sekhar Nori @ 2016-11-23 7:49 UTC (permalink / raw)
To: Sudeep Holla, Bartosz Golaszewski, Kevin Hilman,
Michael Turquette, Rob Herring, Frank Rowand, Mark Rutland,
Peter Ujfalusi, Russell King
Cc: LKML, arm-soc, linux-drm, linux-devicetree, Jyri Sarha,
Tomi Valkeinen, David Airlie, Laurent Pinchart, Robin Murphy
In-Reply-To: <fdb93150-9089-c7bb-2b0a-21ded241a647-5wv7dgnIgG8@public.gmane.org>
On Tuesday 22 November 2016 09:16 PM, Sudeep Holla wrote:
> Hi Sekhar,
>
> On 22/11/16 15:06, Sekhar Nori wrote:
>> Hi Sudeep,
>>
>> On Tuesday 22 November 2016 04:23 PM, Sudeep Holla wrote:
>>>
>>>
>>> On 22/11/16 10:41, Bartosz Golaszewski wrote:
>>>> Add a function allowing to retrieve the compatible string of the root
>>>> node of the device tree.
>>>>
>>>
>>> Rob has queued [1] and it's in -next today. You can reuse that if you
>>> are planning to target this for v4.11 or just use open coding in your
>>> driver for v4.10 and target this move for v4.11 to avoid cross tree
>>> dependencies as I already mentioned in your previous thread.
>>
>> I dont have your original patch in my mailbox, but I wonder if
>> returning a pointer to property string for a node whose reference has
>> already been released is safe to do? Probably not an issue for the root
>> node, but still feels counter-intuitive.
>>
>
> I am not sure if I understand the issue here. Are you referring a case
> where of_root is freed ?
Yes, right, thats what I was hinting at. Since you are giving up the
reference to the device node before the function returns, the user can
be left with a dangling reference.
> Also I have seen drivers today just using this pointer directly, but
> it's better to copy the string(I just saw this done in one case)
Hmm, the reference is given up before the API returns, so I doubt
copying it later is any additional benefit.
I suspect this is a theoretical issue though since root device node is
probably never freed.
Thanks,
Sekhar
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^ permalink raw reply
* [PATCH] arm64: dts: exynos: enable hs400 mode for eMMC for TM2
From: Jaehoon Chung @ 2016-11-23 7:43 UTC (permalink / raw)
To: linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, kgene-DgEjT+Ai2ygdnm+yROfE0A,
krzk-DgEjT+Ai2ygdnm+yROfE0A, cw00.choi-Sze3O3UU22JBDgjK7y7TUQ,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ, Jaehoon Chung
TM2 can support the HS400 mode, but eMMC is working as the lowest mode.
This patch added the properties for HS400 and other modes.
Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
index 88cb6c1..f21bdc2 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
+++ b/arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
@@ -701,6 +701,9 @@
&mshc_0 {
status = "okay";
num-slots = <1>;
+ mmc-hs200-1_8v;
+ mmc-hs400-1_8v;
+ cap-mmc-highspeed;
non-removable;
card-detect-delay = <200>;
samsung,dw-mshc-ciu-div = <3>;
--
2.10.1
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^ permalink raw reply related
* Re: [PATCHv0 1/1] fbdev: add Intel FPGA FRAME BUFFER driver
From: Tomi Valkeinen @ 2016-11-23 7:30 UTC (permalink / raw)
To: Ong, Hean Loong
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479287278-5192-1-git-send-email-hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
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Hi,
On 16/11/16 11:07, Ong, Hean Loong wrote:
> From: Ong Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
>
> This patch enables the display port IP driver for
> Intel Arria 10 SOCFPGA Golden Hardware
> Reference Design (GHRD).
>
> The driver requires enabling the options such as
> Coheherent Memory Allocation,
> Intel FPGA Frame Buffer, Frame Buffer Conasole
>
> Signed-off-by: Ong Hean Loong <hean.loong.ong-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
> ---
> .../devicetree/bindings/video/intelfpgavipfb.txt | 22 ++
> MAINTAINERS | 6 +
> drivers/video/fbdev/Kconfig | 15 +
> drivers/video/fbdev/Makefile | 1 +
> drivers/video/fbdev/intelfpgavipfb.c | 302 ++++++++++++++++++++
> 5 files changed, 346 insertions(+), 0 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/video/intelfpgavipfb.txt
> create mode 100644 drivers/video/fbdev/intelfpgavipfb.c
As mentioned by Rob and Alan, no new fbdev drivers please. Write a DRM
driver for this.
Tomi
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^ permalink raw reply
* [PATCH] arm/dts: ls1021a: Add dma-coherent property to usb3 node
From: Changming Huang @ 2016-11-23 7:15 UTC (permalink / raw)
To: robh+dt, mark.rutland, linux
Cc: devicetree, Rajesh Bhagat, linux-kernel, linux-arm-kernel,
Changming Huang
This sets dma ops as coherent for usb 3.0 platform device
Signed-off-by: Changming Huang <jerry.huang@nxp.com>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..81fb4d9 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ dma-coherent;
};
pcie@3400000 {
--
1.7.9.5
^ permalink raw reply related
* RE: [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Troy Jia @ 2016-11-23 7:14 UTC (permalink / raw)
To: Scott Wood, rui.zhang@intel.com, edubezval@gmail.com,
robh+dt@kernel.org, Scott Wood, shawnguo@kernel.org
Cc: devicetree@vger.kernel.org, linuxppc-dev@lists.ozlabs.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1479884833.21746.44.camel@buserror.net>
> -----Original Message-----
> From: Scott Wood [mailto:oss@buserror.net]
> Sent: Wednesday, November 23, 2016 3:07 PM
> To: Troy Jia <hongtao.jia@nxp.com>; rui.zhang@intel.com; edubezval@gmail.com;
> robh+dt@kernel.org; Scott Wood <scott.wood@nxp.com>; shawnguo@kernel.org
> Cc: devicetree@vger.kernel.org; linuxppc-dev@lists.ozlabs.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for
> T1040/T1042
>
> On Tue, 2016-10-25 at 10:15 +0800, Jia Hongtao wrote:
> > From: Hongtao Jia <hongtao.jia@nxp.com>
> >
> > Update #thermal-sensor-cells from 0 to 1 according to the new binding.
> > The sensor specifier added is the monitoring site ID, and represents
> > the "n" in TRITSRn and TRATSRn.
> >
> > Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
>
> Where can I find this new binding? As of the current linux-next I don't see anything
> in qoriq-thermal.txt about this.
Hi Rui Zhang,
As we discussed before. The time was inappropriate as merge window was about to close.
So do you have any plan for applying the binding file recently?
-Hongtao.
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^ permalink raw reply
* Re: [PATCH V3 1/2] powerpc/mpc85xx: Update TMU device tree node for T1040/T1042
From: Scott Wood @ 2016-11-23 7:07 UTC (permalink / raw)
To: Jia Hongtao, rui.zhang, edubezval, robh+dt, scott.wood, shawnguo
Cc: devicetree, linuxppc-dev, linux-kernel, linux-arm-kernel
In-Reply-To: <1477361742-589-1-git-send-email-hongtao.jia@nxp.com>
On Tue, 2016-10-25 at 10:15 +0800, Jia Hongtao wrote:
> From: Hongtao Jia <hongtao.jia@nxp.com>
>
> Update #thermal-sensor-cells from 0 to 1 according to the new binding. The
> sensor specifier added is the monitoring site ID, and represents the "n" in
> TRITSRn and TRATSRn.
>
> Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
Where can I find this new binding? As of the current linux-next I don't see
anything in qoriq-thermal.txt about this.
-Scott
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^ permalink raw reply
* Re: [PATCH v2 1/5] ARM: memory: da8xx-ddrctl: new driver
From: Sekhar Nori @ 2016-11-23 5:55 UTC (permalink / raw)
To: Frank Rowand, Bartosz Golaszewski, Kevin Hilman,
Michael Turquette, Rob Herring, Mark Rutland, Peter Ujfalusi,
Russell King
Cc: linux-devicetree, David Airlie, LKML, linux-drm, Tomi Valkeinen,
Jyri Sarha, Sudeep Holla, arm-soc, Laurent Pinchart
In-Reply-To: <58348CB8.7050304@gmail.com>
On Tuesday 22 November 2016 11:51 PM, Frank Rowand wrote:
> Please note that the compatible property might contain several strings, not just
> a single string.
So I guess the best thing to do is to use
of_property_read_string_index() and print the sting at index 0.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] arm/dts: ls1021a: Add dma-coherent property to usb3 node
From: Changming Huang @ 2016-11-23 5:49 UTC (permalink / raw)
To: linux-usb-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Changming Huang, Rajesh Bhagat
This sets dma ops as coherent for usb 3.0 platform device
Signed-off-by: Changming Huang <jerry.huang-3arQi8VN3Tc@public.gmane.org>
Signed-off-by: Rajesh Bhagat <rajesh.bhagat-3arQi8VN3Tc@public.gmane.org>
---
arch/arm/boot/dts/ls1021a.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 368e219..81fb4d9 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -627,6 +627,7 @@
dr_mode = "host";
snps,quirk-frame-length-adjustment = <0x20>;
snps,dis_rxdet_inp3_quirk;
+ dma-coherent;
};
pcie@3400000 {
--
1.7.9.5
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* Re: [PATCH 5/5] sdhci: Add quirk for delayed IRQ ACK
From: Jeremy McNicoll @ 2016-11-23 5:23 UTC (permalink / raw)
To: Jisheng Zhang
Cc: Jeremy McNicoll, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
andy.gross-QSEj5FYQhm4dnm+yROfE0A, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
robh-DgEjT+Ai2ygdnm+yROfE0A, arnd-r2nGTMty4D4,
bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
riteshh-sgV2jX0FEOL9JmXXK+q4OQ
In-Reply-To: <20161123121209.3623e14b@xhacker>
On 2016-11-22 8:12 PM, Jisheng Zhang wrote:
> On Tue, 22 Nov 2016 19:48:56 -0800 Jeremy McNicoll wrote:
>
>> On 2016-11-22 7:36 PM, Jisheng Zhang wrote:
>>> On Tue, 22 Nov 2016 17:09:48 -0800
>>> Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org> wrote:
>>>
>>>> On msm8992 it has been observed that IRQs were not getting
>>>> ACK'd correctly when clocked at speeds greater than 400KHz.
>>>>
>>>> Signed-off-by: Jeremy McNicoll <jeremymc-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
>>>> ---
>>>> drivers/mmc/host/sdhci-msm.c | 7 +++++++
>>>> drivers/mmc/host/sdhci.c | 12 ++++++++++--
>>>> drivers/mmc/host/sdhci.h | 2 ++
>>>> 3 files changed, 19 insertions(+), 2 deletions(-)
>>>>
>>>> diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
>>>> index 1fcda96..459003c 100644
>>>> --- a/drivers/mmc/host/sdhci-msm.c
>>>> +++ b/drivers/mmc/host/sdhci-msm.c
>>>> @@ -1303,6 +1303,13 @@ static int sdhci_msm_probe(struct platform_device *pdev)
>>>> CORE_VENDOR_SPEC_CAPABILITIES0);
>>>> }
>>>>
>>>> + /* Enable delayed IRQ handling workaround on 8992 */
>>>> + if (core_major == 1 && core_minor == 0x3e) {
>>>> + /* Add 40us delay in interrupt handler when operating
>>>> + * at initialization frequency of 400KHz. */
>>>> + host->quirks2 |= SDHCI_QUIRK2_SLOW_INT_CLR;
>>>> + }
>>>> +
>>>> /* Setup IRQ for handling power/voltage tasks with PMIC */
>>>> msm_host->pwr_irq = platform_get_irq_byname(pdev, "pwr_irq");
>>>> if (msm_host->pwr_irq < 0) {
>>>> diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
>>>> index 5911f98..c1aae22 100644
>>>> --- a/drivers/mmc/host/sdhci.c
>>>> +++ b/drivers/mmc/host/sdhci.c
>>>> @@ -2703,11 +2703,19 @@ static irqreturn_t sdhci_irq(int irq, void *dev_id)
>>>> result = IRQ_WAKE_THREAD;
>>>> }
>>>>
>>>> - if (intmask & SDHCI_INT_CMD_MASK)
>>>> + if (intmask & SDHCI_INT_CMD_MASK) {
>>>> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) {
>>>> + udelay(40);
>>>> + }
>>>> sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK);
>>>> + }
>>>>
>>>> - if (intmask & SDHCI_INT_DATA_MASK)
>>>> + if (intmask & SDHCI_INT_DATA_MASK) {
>>>> + if ((host->quirks2 & SDHCI_QUIRK2_SLOW_INT_CLR) && (host->clock <= 400000)) {
>>>> + udelay(40);
>>>> + }
>>>> sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK);
>>>> + }
>>>>
>>>> if (intmask & SDHCI_INT_BUS_POWER)
>>>> pr_err("%s: Card is consuming too much power!\n",
>>>> diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
>>>> index c055e24..5f8301e 100644
>>>> --- a/drivers/mmc/host/sdhci.h
>>>> +++ b/drivers/mmc/host/sdhci.h
>>>> @@ -24,6 +24,8 @@
>>>> * Controller registers
>>>> */
>>>>
>>>> +#define SDHCI_QUIRK2_SLOW_INT_CLR (1<<5)
>>>
>>> IIRC, new quirk isn't allowed now.
>>>
>>
>> Why not?
>
> IIRC, mmc subsystem will behave as a lib in the long run, so the community
> and developers call for no new quirk. For your case, we may need to handle
> the udelay in sdhci-msm.c, export sdhci_irq as a helper function?
>
Thanks for the details and suggestions. I am going to wait until the US
Thanksgiving (and cyber Monday) is over before I do any more.
-jeremy
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^ permalink raw reply
* Re: [PATCH v9 00/16] mmc: sdhci-msm: Add clk-rates, DDR, HS400 support
From: Andy Gross @ 2016-11-23 5:00 UTC (permalink / raw)
To: Ulf Hansson
Cc: Ritesh Harjani, linux-mmc, Adrian Hunter, Stephen Boyd, Shawn Lin,
devicetree@vger.kernel.org, linux-clk, David Brown,
linux-arm-msm@vger.kernel.org, Georgi Djakov, Alex Lemberg,
Mateusz Nowak, Yuliy Izrailov, Asutosh Das, David Griego,
Sahitya Tummala, Venkat Gopalakrishnan, Rajendra Nayak
In-Reply-To: <CAPDyKFrRbf0+G5K=-jsaevAGbTqhTAss2zJv3QdiyCrv0BG-zA@mail.gmail.com>
On Mon, Nov 21, 2016 at 11:06:13AM +0100, Ulf Hansson wrote:
> On 21 November 2016 at 07:37, Ritesh Harjani <riteshh@codeaurora.org> wrote:
> > Hi,
> >
> > This is v9 version of the patch series which adds support for MSM8996.
> > Adds HS400 driver support as well.
> > These are tested on internal msm8996 & db410c HW.
> >
> > The patch series is ready. Do we think we can apply these
> > patches for next now?
>
> I guess the DTS changes can be picked up by Andy, so they can go via arm-soc?
Yeah I'll pick up the DTS change and the Documentation change.
>
> Then, does the mmc changes depend on the clock changes? If so, I can
> pick them as well, but then I need an ack from Stephen....
>
> Kind regards
> Uffe
Andy
^ permalink raw reply
* [PATCH] ALSA SoC MAX98927 driver - Initial release
From: Ryan Lee @ 2016-11-23 4:57 UTC (permalink / raw)
To: lgirdwood, broonie, robh+dt, mark.rutland, perex, tiwai, arnd,
michael, oder_chiou, yesanishhere, jacob, Damien.Horsley,
bardliao, kuninori.morimoto.gx, petr, lars, nh6z, ryans.lee,
alsa-devel, devicetree, linux-kernel
Cc: Ryan Lee
Signed-off-by: Ryan Lee <ryans.lee@maximintegrated.com>
---
.../devicetree/bindings/sound/max98927.txt | 32 +
sound/soc/codecs/Kconfig | 5 +
sound/soc/codecs/Makefile | 2 +
sound/soc/codecs/max98927.c | 954 +++++++++++++++
sound/soc/codecs/max98927.h | 1253 ++++++++++++++++++++
5 files changed, 2246 insertions(+)
create mode 100755 Documentation/devicetree/bindings/sound/max98927.txt
mode change 100644 => 100755 sound/soc/codecs/Kconfig
mode change 100644 => 100755 sound/soc/codecs/Makefile
create mode 100755 sound/soc/codecs/max98927.c
create mode 100755 sound/soc/codecs/max98927.h
diff --git a/Documentation/devicetree/bindings/sound/max98927.txt b/Documentation/devicetree/bindings/sound/max98927.txt
new file mode 100755
index 0000000..ddcd332
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/max98927.txt
@@ -0,0 +1,32 @@
+max98927 audio CODEC
+
+This device supports I2C.
+
+Required properties:
+
+ - compatible : "maxim,max98927"
+
+ - vmon-slot-no : slot number used to send voltage information
+ or in inteleave mode this will be used as
+ interleave slot.
+
+ - imon-slot-no : slot number used to send current information
+
+ - interleave-mode : When using two MAX98927 in a system it is
+ possible to create ADC data that that will
+ overflow the frame size. Digital Audio Interleave
+ mode provides a means to output VMON and IMON data
+ from two devices on a single DOUT line when running
+ smaller frames sizes such as 32 BCLKS per LRCLK or
+ 48 BCLKS per LRCLK.
+
+ - reg : the I2C address of the device for I2C
+
+Example:
+
+codec: max98927@3a {
+ compatible = "maxim,max98927";
+ vmon-slot-no = <1>;
+ imon-slot-no = <0>;
+ reg = <0x3a>;
+};
diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
old mode 100644
new mode 100755
index c67667b..45f21ca
--- a/sound/soc/codecs/Kconfig
+++ b/sound/soc/codecs/Kconfig
@@ -86,6 +86,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_MAX9867 if I2C
select SND_SOC_MAX98925 if I2C
select SND_SOC_MAX98926 if I2C
+ select SND_SOC_MAX98927 if I2C
select SND_SOC_MAX9850 if I2C
select SND_SOC_MAX9860 if I2C
select SND_SOC_MAX9768 if I2C
@@ -573,6 +574,10 @@ config SND_SOC_MAX98925
config SND_SOC_MAX98926
tristate
+config SND_SOC_MAX98927
+ tristate "Maxim Integrated MAX98927 Speaker Amplifier"
+ depends on I2C
+
config SND_SOC_MAX9850
tristate
diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
old mode 100644
new mode 100755
index 958cd49..1f5fe2c
--- a/sound/soc/codecs/Makefile
+++ b/sound/soc/codecs/Makefile
@@ -82,6 +82,7 @@ snd-soc-max98371-objs := max98371.o
snd-soc-max9867-objs := max9867.o
snd-soc-max98925-objs := max98925.o
snd-soc-max98926-objs := max98926.o
+snd-soc-max98927-objs := max98927.o
snd-soc-max9850-objs := max9850.o
snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o
@@ -306,6 +307,7 @@ obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o
obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
+obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
diff --git a/sound/soc/codecs/max98927.c b/sound/soc/codecs/max98927.c
new file mode 100755
index 0000000..d85c84f
--- /dev/null
+++ b/sound/soc/codecs/max98927.c
@@ -0,0 +1,954 @@
+/*
+ * max98927.c -- MAX98927 ALSA Soc Audio driver
+ *
+ * Copyright 2013-15 Maxim Integrated Products
+ * Author: Ryan Lee <ryans.lee@maximintegrated.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/slab.h>
+#include <linux/cdev.h>
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+#include <linux/gpio.h>
+#include <linux/of_gpio.h>
+#include <sound/tlv.h>
+#include "max98927.h"
+
+static struct reg_default max98927_reg_map[] = {
+ {0x0014, 0x78},
+ {0x0015, 0xFF},
+ {0x0043, 0x04},
+ {0x0017, 0x55},
+ /* For mono driver we are just enabling one channel*/
+ {MAX98927_PCM_Rx_Enables_A, 0x03},
+ {MAX98927_PCM_Tx_HiZ_Control_A, 0xfc},
+ {MAX98927_PCM_Tx_HiZ_Control_B, 0xff},
+ {MAX98927_PCM_Tx_Channel_Sources_A, 0x01},
+ {MAX98927_PCM_Tx_Channel_Sources_B, 0x01},
+ {MAX98927_Measurement_DSP_Config, 0xf7},
+ {0x0025, 0x80},
+ {0x0026, 0x01},
+ {0x0035, 0x40},
+ {0x0036, 0x40},
+ {0x0037, 0x02},
+ {0x0039, 0x01},
+ {0x003c, 0x44},
+ {0x003d, 0x04},
+ {0x0040, 0x10},
+ {0x0042, 0x3f},
+ {0x0044, 0x00},
+ {0x0045, 0x24},
+ {0x007f, 0x06},
+ {0x0087, 0x1c},
+ {0x0089, 0x03},
+ {0x009f, 0x01},
+};
+
+void max98927_wrapper_write(struct max98927_priv *max98927,
+ unsigned int reg, unsigned int val)
+{
+ if (max98927->regmap)
+ regmap_write(max98927->regmap, reg, val);
+ if (max98927->sub_regmap)
+ regmap_write(max98927->sub_regmap, reg, val);
+}
+
+void max98927_wrap_update_bits(struct max98927_priv *max98927,
+ unsigned int reg, unsigned int mask, unsigned int val)
+{
+ if (max98927->regmap)
+ regmap_update_bits(max98927->regmap, reg, mask, val);
+ if (max98927->sub_regmap)
+ regmap_update_bits(max98927->sub_regmap, reg, mask, val);
+}
+
+static int max98927_reg_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol, unsigned int reg,
+ unsigned int mask, unsigned int shift)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ int data;
+
+ regmap_read(max98927->regmap, reg, &data);
+ ucontrol->value.integer.value[0] =
+ (data & mask) >> shift;
+ return 0;
+}
+
+static int max98927_reg_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol, unsigned int reg,
+ unsigned int mask, unsigned int shift)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ unsigned int sel = ucontrol->value.integer.value[0];
+
+ max98927_wrap_update_bits(max98927, reg, mask, sel << shift);
+ dev_dbg(codec->dev, "%s: register 0x%02X, value 0x%02X\n",
+ __func__, reg, sel);
+ return 0;
+}
+
+static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai,
+ unsigned int fmt)
+{
+ struct snd_soc_codec *codec = codec_dai->codec;
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ unsigned int invert = 0;
+
+ dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
+ switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
+ case SND_SOC_DAIFMT_CBS_CFS:
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_SLAVE);
+ break;
+ case SND_SOC_DAIFMT_CBM_CFM:
+ max98927->master = true;
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_MASTER);
+ break;
+ case SND_SOC_DAIFMT_CBS_CFM:
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_HYBRID);
+ default:
+ dev_err(codec->dev, "DAI clock mode unsupported");
+ return -EINVAL;
+ }
+
+ switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
+ case SND_SOC_DAIFMT_NB_NF:
+ break;
+ case SND_SOC_DAIFMT_IB_NF:
+ invert = MAX98927_PCM_Mode_Config_PCM_BCLKEDGE;
+ break;
+ default:
+ dev_err(codec->dev, "DAI invert mode unsupported");
+ return -EINVAL;
+ }
+
+ /* interface format */
+ switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
+ case SND_SOC_DAIFMT_I2S:
+ max98927->iface |= SND_SOC_DAIFMT_I2S;
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Mode_Config,
+ max98927->iface, max98927->iface);
+ break;
+ case SND_SOC_DAIFMT_LEFT_J:
+ max98927->iface |= SND_SOC_DAIFMT_LEFT_J;
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Mode_Config,
+ max98927->iface, max98927->iface);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ /* pcm channel configuration */
+ if (max98927->iface & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
+ max98927_wrapper_write(max98927,
+ MAX98927_PCM_Rx_Enables_A,
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH0_EN|
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH1_EN);
+ max98927_wrapper_write(max98927,
+ MAX98927_PCM_Tx_Enables_A,
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH0_EN|
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH1_EN);
+ }
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Mode_Config,
+ MAX98927_PCM_Mode_Config_PCM_BCLKEDGE, invert);
+ return 0;
+}
+
+/* codec MCLK rate in master mode */
+static const int rate_table[] = {
+ 5644800, 6000000, 6144000, 6500000,
+ 9600000, 11289600, 12000000, 12288000,
+ 13000000, 19200000,
+};
+
+static int max98927_set_clock(struct max98927_priv *max98927,
+ struct snd_pcm_hw_params *params)
+{
+ /* BCLK/LRCLK ratio calculation */
+ int blr_clk_ratio = params_channels(params) * max98927->ch_size;
+ int reg = MAX98927_PCM_Clock_setup;
+ int mask = MAX98927_PCM_Clock_setup_PCM_BSEL_Mask;
+ int value;
+
+ if (max98927->master) {
+ int i;
+ /* match rate to closest value */
+ for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
+ if (rate_table[i] >= max98927->sysclk)
+ break;
+ }
+ if (i == ARRAY_SIZE(rate_table)) {
+ pr_err("%s couldn't get the MCLK to match codec\n",
+ __func__);
+ return -EINVAL;
+ }
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
+ MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_Mask,
+ i << MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_SHIFT);
+ }
+
+ switch (blr_clk_ratio) {
+ case 32:
+ value = 2;
+ break;
+ case 48:
+ value = 3;
+ break;
+ case 64:
+ value = 4;
+ break;
+ default:
+ return -EINVAL;
+ }
+ max98927_wrap_update_bits(max98927,
+ reg, mask, value);
+ return 0;
+}
+
+static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ int sampling_rate = 0;
+
+ /* pcm mode configuration */
+ switch (snd_pcm_format_width(params_format(params))) {
+ case 16:
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Mode_Config,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_16,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_16);
+ max98927->ch_size = 16;
+ break;
+ case 24:
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Mode_Config,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_24,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_24);
+ max98927->ch_size = 24;
+ break;
+ case 32:
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Mode_Config,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_32,
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_32);
+ max98927->ch_size = 32;
+ break;
+ default:
+ pr_err("%s: format unsupported %d",
+ __func__, params_format(params));
+ goto err;
+ }
+ dev_dbg(codec->dev, "%s: format supported %d",
+ __func__, params_format(params));
+
+ /* sampling rate configuration */
+ switch (params_rate(params)) {
+ case 8000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_8000;
+ break;
+ case 11025:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_11025;
+ break;
+ case 12000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_12000;
+ break;
+ case 16000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_16000;
+ break;
+ case 22050:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_22050;
+ break;
+ case 24000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_24000;
+ break;
+ case 32000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_32000;
+ break;
+ case 44100:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_44100;
+ break;
+ case 48000:
+ sampling_rate |=
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_48000;
+ break;
+ default:
+ pr_err("%s rate %d not supported\n",
+ __func__, params_rate(params));
+ goto err;
+ }
+ /* set DAI_SR to correct LRCLK frequency */
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_1,
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_Mask, sampling_rate);
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_2,
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_Mask, sampling_rate<<4);
+ max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_2,
+ MAX98927_PCM_Sample_rate_setup_2_IVADC_SR_Mask, sampling_rate);
+ return max98927_set_clock(max98927, params);
+err:
+ return -EINVAL;
+}
+
+#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
+
+#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
+ SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
+
+static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
+ int clk_id, unsigned int freq, int dir)
+{
+ struct snd_soc_codec *codec = dai->codec;
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+
+ max98927->sysclk = freq;
+ return 0;
+}
+
+static const struct snd_soc_dai_ops max98927_dai_ops = {
+ .set_sysclk = max98927_dai_set_sysclk,
+ .set_fmt = max98927_dai_set_fmt,
+ .hw_params = max98927_dai_hw_params,
+};
+
+static void max98927_handle_pdata(struct snd_soc_codec *codec)
+{
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ struct max98927_reg_default *regInfo;
+ int cfg_size = 0;
+ int x;
+
+ if (max98927->regcfg != NULL)
+ cfg_size = max98927->regcfg_sz / sizeof(uint32_t);
+
+ if (cfg_size <= 0) {
+ dev_dbg(codec->dev,
+ "Register configuration is not required.\n");
+ return;
+ }
+
+ /* direct configuration from device tree */
+ for (x = 0; x < cfg_size; x += 3) {
+ regInfo = (struct max98927_reg_default *)&max98927->regcfg[x];
+ dev_info(codec->dev, "CH:%d, reg:0x%02x, value:0x%02x\n",
+ be32_to_cpu(regInfo->ch),
+ be32_to_cpu(regInfo->reg),
+ be32_to_cpu(regInfo->def));
+ if (be32_to_cpu(regInfo->ch) == PRI_MAX98927
+ && max98927->regmap)
+ regmap_write(max98927->regmap,
+ be32_to_cpu(regInfo->reg),
+ be32_to_cpu(regInfo->def));
+ else if (be32_to_cpu(regInfo->ch) == SEC_MAX98927
+ && max98927->sub_regmap)
+ regmap_write(max98927->sub_regmap,
+ be32_to_cpu(regInfo->reg),
+ be32_to_cpu(regInfo->def));
+ }
+}
+
+static int max98927_dac_event(struct snd_soc_dapm_widget *w,
+ struct snd_kcontrol *kcontrol, int event)
+{
+ struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+
+ switch (event) {
+ case SND_SOC_DAPM_POST_PMU:
+ max98927_wrap_update_bits(max98927,
+ MAX98927_AMP_enables, 1, 1);
+ /* enable the v and i for vi feedback */
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Measurement_enables,
+ MAX98927_Measurement_enables_IVADC_V_EN,
+ MAX98927_Measurement_enables_IVADC_V_EN);
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Measurement_enables,
+ MAX98927_Measurement_enables_IVADC_I_EN,
+ MAX98927_Measurement_enables_IVADC_I_EN);
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Global_Enable, 1, 1);
+ break;
+ case SND_SOC_DAPM_POST_PMD:
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Global_Enable, 1, 0);
+ max98927_wrap_update_bits(max98927,
+ MAX98927_AMP_enables, 1, 0);
+ /* disable the v and i for vi feedback */
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Measurement_enables,
+ MAX98927_Measurement_enables_IVADC_V_EN,
+ 0);
+ max98927_wrap_update_bits(max98927,
+ MAX98927_Measurement_enables,
+ MAX98927_Measurement_enables_IVADC_I_EN,
+ 0);
+ break;
+ default:
+ return 0;
+ }
+ return 0;
+}
+
+static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
+ SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
+ SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_AMP_enables,
+ 0, 0, max98927_dac_event,
+ SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
+ SND_SOC_DAPM_OUTPUT("BE_OUT"),
+};
+
+static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
+static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
+
+static int max98927_spk_gain_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = max98927->spk_gain;
+ dev_dbg(codec->dev, "%s: spk_gain setting returned %d\n", __func__,
+ (int) ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int max98927_spk_gain_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ unsigned int sel = ucontrol->value.integer.value[0];
+
+ if (sel < ((1 << MAX98927_Speaker_Gain_Width) - 1)) {
+ max98927_wrap_update_bits(max98927, MAX98927_Speaker_Gain,
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_Mask, sel);
+ max98927->spk_gain = sel;
+ }
+ return 0;
+}
+
+static int max98927_digital_gain_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+
+ ucontrol->value.integer.value[0] = max98927->digital_gain;
+ dev_dbg(codec->dev, "%s: spk_gain setting returned %d\n", __func__,
+ (int) ucontrol->value.integer.value[0]);
+ return 0;
+}
+
+static int max98927_digital_gain_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ unsigned int sel = ucontrol->value.integer.value[0];
+
+ if (sel < ((1 << MAX98927_AMP_VOL_WIDTH) - 1)) {
+ max98927_wrap_update_bits(max98927, MAX98927_AMP_volume_control,
+ MAX98927_AMP_volume_control_AMP_VOL_Mask, sel);
+ max98927->digital_gain = sel;
+ }
+ return 0;
+}
+
+static int max98927_boost_voltage_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol, MAX98927_Boost_Control_0,
+ MAX98927_Boost_Control_0_BST_VOUT_Mask, 0);
+}
+
+static int max98927_boost_voltage_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol, MAX98927_Boost_Control_0,
+ MAX98927_Boost_Control_0_BST_VOUT_Mask, 0);
+}
+
+static int max98927_amp_vol_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol, MAX98927_Boost_Control_0,
+ MAX98927_Boost_Control_0_BST_VOUT_Mask,
+ MAX98927_AMP_VOL_LOCATION_SHIFT);
+}
+
+static int max98927_amp_dsp_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol, MAX98927_Brownout_enables,
+ MAX98927_Brownout_enables_AMP_DSP_EN, MAX98927_BDE_DSP_SHIFT);
+}
+
+static int max98927_amp_dsp_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol, MAX98927_Brownout_enables,
+ MAX98927_Brownout_enables_AMP_DSP_EN, MAX98927_BDE_DSP_SHIFT);
+}
+
+static int max98927_ramp_switch_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol, MAX98927_AMP_DSP_Config,
+ MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS,
+ MAX98927_SPK_RMP_EN_SHIFT);
+}
+static int max98927_ramp_switch_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol, MAX98927_AMP_DSP_Config,
+ MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS,
+ MAX98927_SPK_RMP_EN_SHIFT);
+}
+
+static int max98927_dre_en_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol, MAX98927_DRE_Control,
+ MAX98927_DRE_Control_DRE_EN, 0);
+}
+static int max98927_dre_en_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol, MAX98927_DRE_Control,
+ MAX98927_DRE_Control_DRE_EN, 0);
+}
+static int max98927_amp_vol_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol,
+ MAX98927_AMP_volume_control,
+ MAX98927_AMP_volume_control_AMP_VOL_SEL,
+ MAX98927_AMP_VOL_LOCATION_SHIFT);
+}
+static int max98927_spk_src_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol,
+ MAX98927_Speaker_source_select,
+ MAX98927_Speaker_source_select_SPK_SOURCE_Mask, 0);
+}
+
+static int max98927_spk_src_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol,
+ MAX98927_Speaker_source_select,
+ MAX98927_Speaker_source_select_SPK_SOURCE_Mask, 0);
+}
+
+static int max98927_mono_out_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_get(kcontrol, ucontrol,
+ MAX98927_PCM_to_speaker_monomix_A,
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask,
+ MAX98927_PCM_to_speaker_monomix_A_SHIFT);
+}
+
+static int max98927_mono_out_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ return max98927_reg_put(kcontrol, ucontrol,
+ MAX98927_PCM_to_speaker_monomix_A,
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask,
+ MAX98927_PCM_to_speaker_monomix_A_SHIFT);
+}
+
+static bool max98927_readable_register(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case 0x0001 ... 0x0028:
+ case 0x002B ... 0x004E:
+ case 0x0051 ... 0x0055:
+ case 0x005A ... 0x0061:
+ case 0x0072 ... 0x0087:
+ case 0x00FF:
+ case 0x0100:
+ case 0x01FF:
+ return true;
+ }
+ return false;
+};
+
+static const char * const max98927_boost_voltage_text[] = {
+ "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
+ "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
+ "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
+ "9.5V", "9.625V", "9.75V", "9.875V", "10V"
+};
+
+static const char * const max98927_speaker_source_text[] = {
+ "i2s", "reserved", "tone", "pdm"
+};
+
+static const char * const max98927_monomix_output_text[] = {
+ "ch_0", "ch_1", "ch_1_2_div"
+};
+
+static const struct soc_enum max98927_enum[] = {
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_monomix_output_text),
+ max98927_monomix_output_text),
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_speaker_source_text),
+ max98927_speaker_source_text),
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_boost_voltage_text),
+ max98927_boost_voltage_text),
+};
+
+static const struct snd_kcontrol_new max98927_snd_controls[] = {
+ SOC_SINGLE_EXT_TLV("Speaker Volume", MAX98927_Speaker_Gain,
+ 0, (1<<MAX98927_Speaker_Gain_Width)-1, 0,
+ max98927_spk_gain_get, max98927_spk_gain_put,
+ max98927_spk_tlv),
+ SOC_SINGLE_EXT_TLV("Digital Gain", MAX98927_AMP_volume_control,
+ 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
+ max98927_digital_gain_get, max98927_digital_gain_put,
+ max98927_digital_tlv),
+ SOC_SINGLE_EXT("Amp DSP Enable", MAX98927_Brownout_enables,
+ MAX98927_BDE_DSP_SHIFT, 1, 0,
+ max98927_amp_dsp_get, max98927_amp_dsp_put),
+ SOC_SINGLE_EXT("Ramp Switch", MAX98927_AMP_DSP_Config,
+ MAX98927_SPK_RMP_EN_SHIFT, 1, 1,
+ max98927_ramp_switch_get, max98927_ramp_switch_put),
+ SOC_SINGLE_EXT("DRE EN", MAX98927_DRE_Control,
+ MAX98927_DRE_Control_DRE_SHIFT, 1, 0,
+ max98927_dre_en_get, max98927_dre_en_put),
+ SOC_SINGLE_EXT("Amp Volume Location", MAX98927_AMP_volume_control,
+ MAX98927_AMP_VOL_LOCATION_SHIFT, 1, 0,
+ max98927_amp_vol_get, max98927_amp_vol_put),
+
+ SOC_ENUM_EXT("Boost Output Voltage", max98927_enum[2],
+ max98927_boost_voltage_get, max98927_boost_voltage_put),
+ SOC_ENUM_EXT("Speaker Source", max98927_enum[1],
+ max98927_spk_src_get, max98927_spk_src_put),
+ SOC_ENUM_EXT("Monomix Output", max98927_enum[0],
+ max98927_mono_out_get, max98927_mono_out_put),
+};
+
+static const struct snd_soc_dapm_route max98927_audio_map[] = {
+ {"BE_OUT", NULL, "Amp Enable"},
+};
+
+static struct snd_soc_dai_driver max98927_dai[] = {
+ {
+ .name = "max98927-aif1",
+ .playback = {
+ .stream_name = "HiFi Playback",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MAX98927_RATES,
+ .formats = MAX98927_FORMATS,
+ },
+ .capture = {
+ .stream_name = "HiFi Capture",
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = MAX98927_RATES,
+ .formats = MAX98927_FORMATS,
+ },
+ .ops = &max98927_dai_ops,
+ }
+};
+
+static int max98927_probe(struct snd_soc_codec *codec)
+{
+ struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
+ int ret = 0, reg = 0, i;
+
+ max98927->codec = codec;
+ codec->control_data = max98927->regmap;
+ codec->cache_bypass = 1;
+
+ /* Software Reset */
+ max98927_wrapper_write(max98927,
+ MAX98927_Software_Reset, MAX98927_Software_Reset_RST);
+
+ /* Check Revision ID for the primary MAX98927*/
+ ret = regmap_read(max98927->regmap, MAX98927_REV_ID, ®);
+ if (ret < 0)
+ dev_err(codec->dev,
+ "Failed to read: 0x%02X\n", MAX98927_REV_ID);
+ else
+ dev_info(codec->dev,
+ "MAX98927 revisionID: 0x%02X\n", reg);
+
+ /* Check Revision ID for the secondary MAX98927*/
+ if (max98927->sub_regmap) {
+ ret = regmap_read(max98927->sub_regmap, MAX98927_REV_ID, ®);
+ if (ret < 0)
+ dev_err(codec->dev,
+ "Failed to read: 0x%02X from secodnary device\n"
+ , MAX98927_REV_ID);
+ else
+ dev_info(codec->dev,
+ "Secondary device revisionID: 0x%02X\n", reg);
+ }
+
+ /* Register initialization */
+ for (i = 0; i < sizeof(max98927_reg_map)/
+ sizeof(max98927_reg_map[0]); i++)
+ max98927_wrapper_write(max98927,
+ max98927_reg_map[i].reg,
+ max98927_reg_map[i].def);
+
+ if (max98927->regmap)
+ regmap_write(max98927->regmap,
+ MAX98927_PCM_Tx_Channel_Sources_A,
+ (max98927->i_l_slot
+ <<MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT|
+ max98927->v_l_slot)&0xFF);
+ if (max98927->sub_regmap)
+ regmap_write(max98927->sub_regmap,
+ MAX98927_PCM_Tx_Channel_Sources_A,
+ (max98927->i_r_slot
+ <<MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT|
+ max98927->v_r_slot)&0xFF);
+
+ /* Set interleave mode */
+ if (max98927->interleave_mode)
+ max98927_wrap_update_bits(max98927,
+ MAX98927_PCM_Tx_Channel_Sources_B,
+ MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask,
+ MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask);
+
+ max98927_handle_pdata(codec);
+
+ return ret;
+}
+
+static const struct snd_soc_codec_driver soc_codec_dev_max98927 = {
+ .probe = max98927_probe,
+ .dapm_routes = max98927_audio_map,
+ .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
+ .dapm_widgets = max98927_dapm_widgets,
+ .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
+ .controls = max98927_snd_controls,
+ .num_controls = ARRAY_SIZE(max98927_snd_controls),
+};
+
+static const struct regmap_config max98927_regmap = {
+ .reg_bits = 16,
+ .val_bits = 8,
+ .max_register = MAX98927_REV_ID,
+ .reg_defaults = max98927_reg_map,
+ .num_reg_defaults = ARRAY_SIZE(max98927_reg_map),
+ .readable_reg = max98927_readable_register,
+ .cache_type = REGCACHE_RBTREE,
+};
+
+static struct i2c_board_info max98927_i2c_sub_board[] = {
+ {
+ I2C_BOARD_INFO("max98927_sub", 0x39),
+ }
+};
+
+static struct i2c_driver max98927_i2c_sub_driver = {
+ .driver = {
+ .name = "max98927_sub",
+ .owner = THIS_MODULE,
+ },
+};
+
+struct i2c_client *max98927_add_sub_device(int bus_id, int slave_addr)
+{
+ struct i2c_client *i2c = NULL;
+ struct i2c_adapter *adapter;
+
+ max98927_i2c_sub_board[0].addr = slave_addr;
+
+ adapter = i2c_get_adapter(bus_id);
+ if (adapter) {
+ i2c = i2c_new_device(adapter, max98927_i2c_sub_board);
+ if (i2c)
+ i2c->dev.driver = &max98927_i2c_sub_driver.driver;
+ }
+
+ return i2c;
+}
+
+int probe_common(struct i2c_client *i2c, struct max98927_priv *max98927)
+{
+ int ret = 0, value;
+
+ if (!of_property_read_u32(i2c->dev.of_node, "vmon-l-slot", &value))
+ max98927->v_l_slot = value & 0xF;
+ else
+ max98927->v_l_slot = 0;
+ if (!of_property_read_u32(i2c->dev.of_node, "imon-l-slot", &value))
+ max98927->i_l_slot = value & 0xF;
+ else
+ max98927->i_l_slot = 1;
+ if (!of_property_read_u32(i2c->dev.of_node, "vmon-r-slot", &value))
+ max98927->v_r_slot = value & 0xF;
+ else
+ max98927->v_r_slot = 2;
+ if (!of_property_read_u32(i2c->dev.of_node, "imon-r-slot", &value))
+ max98927->i_r_slot = value & 0xF;
+ else
+ max98927->i_r_slot = 3;
+
+ ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98927,
+ max98927_dai, ARRAY_SIZE(max98927_dai));
+ if (ret < 0)
+ dev_err(&i2c->dev,
+ "Failed to register codec: %d\n", ret);
+ return ret;
+}
+
+static int max98927_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+
+ int ret = 0, value;
+ struct max98927_priv *max98927 = NULL;
+
+ max98927 = devm_kzalloc(&i2c->dev,
+ sizeof(*max98927), GFP_KERNEL);
+
+ if (!max98927) {
+ ret = -ENOMEM;
+ goto err;
+ }
+ i2c_set_clientdata(i2c, max98927);
+
+ /* update interleave mode info */
+ if (!of_property_read_u32(i2c->dev.of_node,
+ "interleave_mode", &value)) {
+ if (value > 0)
+ max98927->interleave_mode = 1;
+ else
+ max98927->interleave_mode = 0;
+ } else
+ max98927->interleave_mode = 0;
+
+ /* update direct configuration info */
+ max98927->regcfg = of_get_property(i2c->dev.of_node,
+ "maxim,regcfg", &max98927->regcfg_sz);
+
+ /* check for secondary MAX98927 */
+ ret = of_property_read_u32(i2c->dev.of_node,
+ "maxim,sub_reg", &max98927->sub_reg);
+ if (ret) {
+ dev_err(&i2c->dev, "Sub-device slave address was not found.\n");
+ max98927->sub_reg = -1;
+ }
+ ret = of_property_read_u32(i2c->dev.of_node,
+ "maxim,sub_bus", &max98927->sub_bus);
+ if (ret) {
+ dev_err(&i2c->dev, "Sub-device bus information was not found.\n");
+ max98927->sub_bus = i2c->adapter->nr;
+ }
+
+ /* regmap initialization for primary device */
+ max98927->regmap
+ = devm_regmap_init_i2c(i2c, &max98927_regmap);
+ if (IS_ERR(max98927->regmap)) {
+ ret = PTR_ERR(max98927->regmap);
+ dev_err(&i2c->dev,
+ "Failed to allocate regmap: %d\n", ret);
+ goto err;
+ }
+
+ /* regmap initialization for secondary device */
+ if (max98927->sub_reg > 0) {
+ max98927->sub_i2c = max98927_add_sub_device(max98927->sub_bus,
+ max98927->sub_reg);
+ if (IS_ERR(max98927->sub_i2c)) {
+ dev_err(&max98927->sub_i2c->dev,
+ "Second MAX98927 was not found\n");
+ ret = PTR_ERR(max98927->regmap);
+ goto err;
+ } else {
+ max98927->sub_regmap = regmap_init_i2c(
+ max98927->sub_i2c, &max98927_regmap);
+ if (IS_ERR(max98927->sub_regmap)) {
+ ret = PTR_ERR(max98927->sub_regmap);
+ dev_err(&max98927->sub_i2c->dev,
+ "Failed to allocate sub_regmap: %d\n",
+ ret);
+ goto err;
+ }
+ }
+ }
+
+ /* codec registeration */
+ ret = probe_common(i2c, max98927);
+
+ return ret;
+
+err:
+ if (max98927)
+ devm_kfree(&i2c->dev, max98927);
+ return ret;
+}
+
+static int max98927_i2c_remove(struct i2c_client *client)
+{
+ snd_soc_unregister_codec(&client->dev);
+ return 0;
+}
+
+static const struct i2c_device_id max98927_i2c_id[] = {
+ { "max98927", 0},
+ { },
+};
+
+MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
+
+static const struct of_device_id max98927_of_match[] = {
+ { .compatible = "maxim,max98927", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, max98927_of_match);
+
+static struct i2c_driver max98927_i2c_driver = {
+ .driver = {
+ .name = "max98927",
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(max98927_of_match),
+ .pm = NULL,
+ },
+ .probe = max98927_i2c_probe,
+ .remove = max98927_i2c_remove,
+ .id_table = max98927_i2c_id,
+};
+
+module_i2c_driver(max98927_i2c_driver)
+
+MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
+MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
+MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/max98927.h b/sound/soc/codecs/max98927.h
new file mode 100755
index 0000000..2305185
--- /dev/null
+++ b/sound/soc/codecs/max98927.h
@@ -0,0 +1,1253 @@
+/*
+ * max98927.c -- MAX98927 ALSA Soc Audio driver
+ *
+ * Copyright 2008-11 Wolfson Microelectronics PLC.
+ * Author: Ryan Lee <ryans.lee@maximintegrated.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+#ifndef __MAX98927_REGISTERDEFS_H
+#define __MAX98927_REGISTERDEFS_H
+#ifdef CONFIG_SND_SOC_MAXIM_DSM
+#include <sound/maxim_dsm.h>
+#endif /* CONFIG_SND_SOC_MAXIM_DSM */
+
+enum {
+ PRI_MAX98927 = 0,
+ SEC_MAX98927 = 1,
+ MAX_DEV_ID_MAX98927,
+} MAX98927deviceID;
+
+enum {
+ /*Interrupt Raw 1 (Address 0x0001)*/
+ MAX98927_Interrupt_Raw_1 = 0x0001,
+ MAX98927_Interrupt_Raw_1_BDE_ACTIVE_END_RAW = (0x1 << 0),
+ MAX98927_Interrupt_Raw_1_BDE_ACTIVE_BGN_RAW = (0x1 << 1),
+ MAX98927_Interrupt_Raw_1_BDE_LEVEL_CHANGE_RAW = (0x1 << 2),
+ MAX98927_Interrupt_Raw_1_BDE_L8_RAW = (0x1 << 3),
+ MAX98927_Interrupt_Raw_1_THERMWARN_END_RAW = (0x1 << 4),
+ MAX98927_Interrupt_Raw_1_THERMWARN_START_RAW = (0x1 << 5),
+ MAX98927_Interrupt_Raw_1_THERMSHDN_END_RAW = (0x1 << 6),
+ MAX98927_Interrupt_Raw_1_THERMSHDN_START_RAW = (0x1 << 7),
+
+ /* Interrupt Raw 2 (Address 0x0002)*/
+ MAX98927_Interrupt_Raw_2 = 0x0002,
+ MAX98927_Interrupt_Raw_2_WATCHDOGWARN_RAW = (0x1 << 0),
+ MAX98927_Interrupt_Raw_2_WATCHDOGFAIL_RAW = (0x1 << 1),
+ MAX98927_Interrupt_Raw_2_BOOSTCURRLIM_RAW = (0x1 << 2),
+ MAX98927_Interrupt_Raw_2_CLKSTOP_RAW = (0x1 << 3),
+ MAX98927_Interrupt_Raw_2_CLKSTART_RAW = (0x1 << 4),
+ MAX98927_Interrupt_Raw_2_MEASADC_END_RAW = (0x1 << 5),
+ MAX98927_Interrupt_Raw_2_PWRDN_DONE_RAW = (0x1 << 6),
+ MAX98927_Interrupt_Raw_2_PWRUP_DONE_RAW = (0x1 << 7),
+
+ /* Interrupt Raw 3 (Address 0x0003)*/
+ MAX98927_Interrupt_Raw_3 = 0x0003,
+ MAX98927_Interrupt_Raw_3_PWRUP_FAIL_RAW = (0x1 << 0),
+ MAX98927_Interrupt_Raw_3_AUTH_DONE_RAW = (0x1 << 1),
+ MAX98927_Interrupt_Raw_3_SPK_OVC_RAW = (0x1 << 2),
+ MAX98927_Interrupt_Raw_3_BST_UVLO_RAW = (0x1 << 3),
+
+ /* Interrupt State 1 (Address 0x0004)*/
+ MAX98927_Interrupt_State_1 = 0x0004,
+ MAX98927_Interrupt_State_1_BDE_ACTIVE_END_STATE = (0x1 << 0),
+ MAX98927_Interrupt_State_1_BDE_ACTIVE_BGN_STATE = (0x1 << 1),
+ MAX98927_Interrupt_State_1_BDE_LEVEL_CHANGE_STATE = (0x1 << 2),
+ MAX98927_Interrupt_State_1_BDE_L8_STATE = (0x1 << 3),
+ MAX98927_Interrupt_State_1_THERMWARN_END_STATE = (0x1 << 4),
+ MAX98927_Interrupt_State_1_THERMWARN_START_STATE = (0x1 << 5),
+ MAX98927_Interrupt_State_1_THERMSHDN_END_STATE = (0x1 << 6),
+ MAX98927_Interrupt_State_1_THERMSHDN_START_STATE = (0x1 << 7),
+
+ /* Interrupt State 2 (Address 0x0005)*/
+ MAX98927_Interrupt_State_2 = 0x0005,
+ MAX98927_Interrupt_State_2_WATCHDOGWARN_STATE = (0x1 << 0),
+ MAX98927_Interrupt_State_2_WATCHDOGFAIL_STATE = (0x1 << 1),
+ MAX98927_Interrupt_State_2_BOOSTCURRLIM_STATE = (0x1 << 2),
+ MAX98927_Interrupt_State_2_CLKSTOP_STATE = (0x1 << 3),
+ MAX98927_Interrupt_State_2_CLKSTART_STATE = (0x1 << 4),
+ MAX98927_Interrupt_State_2_MEASADC_END_STATE = (0x1 << 5),
+ MAX98927_Interrupt_State_2_PWRDN_DONE_STATE = (0x1 << 6),
+ MAX98927_Interrupt_State_2_PWRUP_DONE_STATE = (0x1 << 7),
+
+ /* Interrupt State 3 (Address 0x0006)*/
+ MAX98927_Interrupt_State_3 = 0x0006,
+ MAX98927_Interrupt_State_3_PWRUP_FAIL_STATE = (0x1 << 0),
+ MAX98927_Interrupt_State_3_AUTH_DONE_STATE = (0x1 << 1),
+ MAX98927_Interrupt_State_3_SPK_OVC_STATE = (0x1 << 2),
+ MAX98927_Interrupt_State_3_BST_UVLO_STATE = (0x1 << 3),
+
+ /* Interrupt Flag 1 (Address 0x0007)*/
+ MAX98927_Interrupt_Flag_1 = 0x0007,
+ MAX98927_Interrupt_Flag_1_BDE_ACTIVE_END_FLAG = (0x1 << 0),
+ MAX98927_Interrupt_Flag_1_BDE_ACTIVE_BGN_FLAG = (0x1 << 1),
+ MAX98927_Interrupt_Flag_1_BDE_LEVEL_CHANGE_FLAG = (0x1 << 2),
+ MAX98927_Interrupt_Flag_1_BDE_L8_FLAG = (0x1 << 3),
+ MAX98927_Interrupt_Flag_1_THERMWARN_END_FLAG = (0x1 << 4),
+ MAX98927_Interrupt_Flag_1_THERMWARN_START_FLAG = (0x1 << 5),
+ MAX98927_Interrupt_Flag_1_THERMSHDN_END_FLAG = (0x1 << 6),
+ MAX98927_Interrupt_Flag_1_THERMSHDN_START_FLAG = (0x1 << 7),
+
+ /* Interrupt Flag 2 (Address 0x0008)*/
+ MAX98927_Interrupt_Flag_2 = 0x0008,
+ MAX98927_Interrupt_Flag_2_WATCHDOGWARN_FLAG = (0x1 << 0),
+ MAX98927_Interrupt_Flag_2_WATCHDOGFAIL_FLAG = (0x1 << 1),
+ MAX98927_Interrupt_Flag_2_BOOSTCURRLIM_FLAG = (0x1 << 2),
+ MAX98927_Interrupt_Flag_2_CLKSTOP_FLAG = (0x1 << 3),
+ MAX98927_Interrupt_Flag_2_CLKSTART_FLAG = (0x1 << 4),
+ MAX98927_Interrupt_Flag_2_MEASADC_END_FLAG = (0x1 << 5),
+ MAX98927_Interrupt_Flag_2_PWRDN_DONE_FLAG = (0x1 << 6),
+ MAX98927_Interrupt_Flag_2_PWRUP_DONE_FLAG = (0x1 << 7),
+
+ /* Interrupt Flag 3 (Address 0x0009)*/
+ MAX98927_Interrupt_Flag_3 = 0x0009,
+ MAX98927_Interrupt_Flag_3_PWRUP_FAIL_FLAG = (0x1 << 0),
+ MAX98927_Interrupt_Flag_3_AUTH_DONE_FLAG = (0x1 << 1),
+ MAX98927_Interrupt_Flag_3_SPK_OVC_FLAG = (0x1 << 2),
+ MAX98927_Interrupt_Flag_3_BST_UVLO_FLAG = (0x1 << 3),
+
+ /* Interrupt Enable 1 (Address 0x000a)*/
+ MAX98927_Interrupt_Enable_1 = 0x000a,
+ MAX98927_Interrupt_Enable_1_BDE_ACTIVE_END_EN = (0x1 << 0),
+ MAX98927_Interrupt_Enable_1_BDE_ACTIVE_BGN_EN = (0x1 << 1),
+ MAX98927_Interrupt_Enable_1_BDE_LEVEL_CHANGE_EN = (0x1 << 2),
+ MAX98927_Interrupt_Enable_1_BDE_L8_EN = (0x1 << 3),
+ MAX98927_Interrupt_Enable_1_THERMWARN_END_EN = (0x1 << 4),
+ MAX98927_Interrupt_Enable_1_THERMWARN_START_EN = (0x1 << 5),
+ MAX98927_Interrupt_Enable_1_THERMSHDN_END_EN = (0x1 << 6),
+ MAX98927_Interrupt_Enable_1_THERMSHDN_START_EN = (0x1 << 7),
+
+ /* Interrupt Enable 2 (Address 0x000b)*/
+ MAX98927_Interrupt_Enable_2 = 0x000b,
+ MAX98927_Interrupt_Enable_2_WATCHDOGWARN_EN = (0x1 << 0),
+ MAX98927_Interrupt_Enable_2_WATCHDOGFAIL_EN = (0x1 << 1),
+ MAX98927_Interrupt_Enable_2_BOOSTCURRLIM_EN = (0x1 << 2),
+ MAX98927_Interrupt_Enable_2_CLKSTOP_EN = (0x1 << 3),
+ MAX98927_Interrupt_Enable_2_CLKSTART_EN = (0x1 << 4),
+ MAX98927_Interrupt_Enable_2_MEASADC_END_EN = (0x1 << 5),
+ MAX98927_Interrupt_Enable_2_PWRDN_DONE_EN = (0x1 << 6),
+ MAX98927_Interrupt_Enable_2_PWRUP_DONE_EN = (0x1 << 7),
+
+ /* Interrupt Enable 3 (Address 0x000c)*/
+ MAX98927_Interrupt_Enable_3 = 0x000c,
+ MAX98927_Interrupt_Enable_3_PWRUP_FAIL_EN = (0x1 << 0),
+ MAX98927_Interrupt_Enable_3_AUTH_DONE_EN = (0x1 << 1),
+ MAX98927_Interrupt_Enable_3_SPK_OVC_EN = (0x1 << 2),
+ MAX98927_Interrupt_Enable_3_BST_UVLO_EN = (0x1 << 3),
+
+ /* Interrupt Flag Clear 1 (Address 0x000d)*/
+ MAX98927_Interrupt_Flag_Clear_1 = 0x000d,
+ MAX98927_Interrupt_Flag_Clear_1_BDE_ACTIVE_END_CLR = (0x1 << 0),
+ MAX98927_Interrupt_Flag_Clear_1_BDE_ACTIVE_BGN_CLR = (0x1 << 1),
+ MAX98927_Interrupt_Flag_Clear_1_BDE_LEVEL_CHANGE_CLR = (0x1 << 2),
+ MAX98927_Interrupt_Flag_Clear_1_BDE_L8_CLR = (0x1 << 3),
+ MAX98927_Interrupt_Flag_Clear_1_THERMWARN_END_CLR = (0x1 << 4),
+ MAX98927_Interrupt_Flag_Clear_1_THERMWARN_START_CLR = (0x1 << 5),
+ MAX98927_Interrupt_Flag_Clear_1_THERMSHDN_END_CLR = (0x1 << 6),
+ MAX98927_Interrupt_Flag_Clear_1_THERMSHDN_START_CLR = (0x1 << 7),
+
+ /* Interrupt Flag Clear 2 (Address 0x000e)*/
+ MAX98927_Interrupt_Flag_Clear_2 = 0x000e,
+ MAX98927_Interrupt_Flag_Clear_2_WATCHDOGWARN_CLR = (0x1 << 0),
+ MAX98927_Interrupt_Flag_Clear_2_WATCHDOGFAIL_CLR = (0x1 << 1),
+ MAX98927_Interrupt_Flag_Clear_2_BOOSTCURRLIM_CLR = (0x1 << 2),
+ MAX98927_Interrupt_Flag_Clear_2_CLKSTOP_CLR = (0x1 << 3),
+ MAX98927_Interrupt_Flag_Clear_2_CLKSTART_CLR = (0x1 << 4),
+ MAX98927_Interrupt_Flag_Clear_2_MEASADC_END_CLR = (0x1 << 5),
+ MAX98927_Interrupt_Flag_Clear_2_PWRDN_DONE_CLR = (0x1 << 6),
+ MAX98927_Interrupt_Flag_Clear_2_PWRUP_DONE_CLR = (0x1 << 7),
+
+ /* Interrupt Flag Clear 3 (Address 0x000f)*/
+ MAX98927_Interrupt_Flag_Clear_3 = 0x000f,
+ MAX98927_Interrupt_Flag_Clear_3_PWRUP_FAIL_CLR = (0x1 << 0),
+ MAX98927_Interrupt_Flag_Clear_3_AUTH_DONE_CLR = (0x1 << 1),
+ MAX98927_Interrupt_Flag_Clear_3_SPK_OVC_CLR = (0x1 << 2),
+ MAX98927_Interrupt_Flag_Clear_3_BST_UVLO_CLR = (0x1 << 3),
+
+ /* IRQ Control (Address 0x0010)*/
+ MAX98927_IRQ_Control = 0x0010,
+ MAX98927_IRQ_Control_IRQ_EN = (0x1 << 0),
+ MAX98927_IRQ_Control_IRQ_POL = (0x1 << 1),
+ MAX98927_IRQ_Control_IRQ_MODE = (0x1 << 2),
+
+ /* Clock monitor enable (Address 0x0011)*/
+ MAX98927_Clock_monitor_enable = 0x0011,
+ MAX98927_Clock_monitor_enable_CMON_ENA = (0x1 << 0),
+ MAX98927_Clock_monitor_enable_CMON_AUTORESTART_ENA = (0x1 << 1),
+
+ /* Watchdog Control (Address 0x0012)*/
+ MAX98927_Watchdog_Control = 0x0012,
+ MAX98927_Watchdog_Control_WDT_ENA = (0x1 << 0),
+ MAX98927_Watchdog_Control_WDT_MODE = (0x1 << 1),
+ MAX98927_Watchdog_Control_WDT_TO_SEL_Mask = (0x3 << 2),
+ MAX98927_Watchdog_Control_WDT_TO_SEL_5 = (0x0 << 2),
+ MAX98927_Watchdog_Control_WDT_TO_SEL_10 = (0x1 << 2),
+ MAX98927_Watchdog_Control_WDT_TO_SEL_35 = (0x2 << 2),
+ MAX98927_Watchdog_Control_WDT_TO_SEL_50 = (0x3 << 2),
+ MAX98927_Watchdog_Control_WDT_HW_SOURCE = (0x1 << 4),
+
+ /* Watchdog SW Reset (Address 0x0013)*/
+ MAX98927_Watchdog_SW_Reset = 0x0013,
+ MAX98927_Watchdog_SW_Reset_WDT_SW_RST_Mask = (0xff << 0),
+
+ /* Meas ADC Thermal Warning Threshhold (Address 0x0014)*/
+ MAX98927_Meas_ADC_TW_Threshhold = 0x0014,
+ MAX98927_Meas_ADC_TW_Threshhold_MEAS_ADC_WARN_THRESH_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Thermal Shutdown Threshhold (Address 0x0015)*/
+ MAX98927_Meas_ADC_TS_Threshhold = 0x0015,
+ MAX98927_Meas_ADC_TS_Threshhold_MEAS_ADC_SHDN_THRESH_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Thermal Hysteresis (Address 0x0016)*/
+ MAX98927_Meas_ADC_Thermal_Hysteresis = 0x0016,
+ MAX98927_Meas_ADC_TH_MEAS_ADC_THERM_HYST_Mask = (0x1f << 0),
+
+ /* Pin Config (Address 0x0017)*/
+ MAX98927_Pin_Config = 0x0017,
+ MAX98927_Pin_Config_DOUT_DRV_Mask = (0x3 << 0),
+ MAX98927_Pin_Config_DOUT_DRV_01 = (0x0 << 0),
+ MAX98927_Pin_Config_DOUT_DRV_11 = (0x2 << 0),
+ MAX98927_Pin_Config_BCLK_DRV_Mask = (0x3 << 2),
+ MAX98927_Pin_Config_BCLK_DRV_01 = (0x0 << 2),
+ MAX98927_Pin_Config_BCLK_DRV_11 = (0x2 << 2),
+ MAX98927_Pin_Config_LRCLK_DRV_Mask = (0x3 << 4),
+ MAX98927_Pin_Config_LRCLK_DRV_01 = (0x0 << 4),
+ MAX98927_Pin_Config_LRCLK_DRV_11 = (0x2 << 4),
+ MAX98927_Pin_Config_ICC_DRV_Mask = (0x3 << 6),
+ MAX98927_Pin_Config_ICC_DRV_01 = (0x0 << 6),
+ MAX98927_Pin_Config_ICC_DRV_11 = (0x2 << 6),
+
+ /* PCM Rx Enables A (Address 0x0018)*/
+ MAX98927_PCM_Rx_Enables_A = 0x0018,
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH0_EN = (0x1 << 0),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH1_EN = (0x1 << 1),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH2_EN = (0x1 << 2),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH3_EN = (0x1 << 3),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH4_EN = (0x1 << 4),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH5_EN = (0x1 << 5),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH6_EN = (0x1 << 6),
+ MAX98927_PCM_Rx_Enables_A_PCM_RX_CH7_EN = (0x1 << 7),
+
+ /* PCM Rx Enables B (Address 0x0019)*/
+ MAX98927_PCM_Rx_Enables_B = 0x0019,
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH8_EN = (0x1 << 0),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH9_EN = (0x1 << 1),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH10_EN = (0x1 << 2),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH11_EN = (0x1 << 3),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH12_EN = (0x1 << 4),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH13_EN = (0x1 << 5),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH14_EN = (0x1 << 6),
+ MAX98927_PCM_Rx_Enables_B_PCM_RX_CH15_EN = (0x1 << 7),
+
+ /* PCM Tx Enables A (Address 0x001a)*/
+ MAX98927_PCM_Tx_Enables_A = 0x001a,
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH0_EN = (0x1 << 0),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH1_EN = (0x1 << 1),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH2_EN = (0x1 << 2),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH3_EN = (0x1 << 3),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH4_EN = (0x1 << 4),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH5_EN = (0x1 << 5),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH6_EN = (0x1 << 6),
+ MAX98927_PCM_Tx_Enables_A_PCM_TX_CH7_EN = (0x1 << 7),
+
+ /* PCM Tx Enables B (Address 0x001b)*/
+ MAX98927_PCM_Tx_Enables_B = 0x001b,
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH8_EN = (0x1 << 0),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH9_EN = (0x1 << 1),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH10_EN = (0x1 << 2),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH11_EN = (0x1 << 3),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH12_EN = (0x1 << 4),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH13_EN = (0x1 << 5),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH14_EN = (0x1 << 6),
+ MAX98927_PCM_Tx_Enables_B_PCM_TX_CH15_EN = (0x1 << 7),
+
+ /* PCM Tx HiZ Control A (Address 0x001c)*/
+ MAX98927_PCM_Tx_HiZ_Control_A = 0x001c,
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH0_HIZ = (0x1 << 0),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH1_HIZ = (0x1 << 1),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH2_HIZ = (0x1 << 2),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH3_HIZ = (0x1 << 3),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH4_HIZ = (0x1 << 4),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH5_HIZ = (0x1 << 5),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH6_HIZ = (0x1 << 6),
+ MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH7_HIZ = (0x1 << 7),
+
+ /* PCM Tx HiZ Control B (Address 0x001d)*/
+ MAX98927_PCM_Tx_HiZ_Control_B = 0x001d,
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH8_HIZ = (0x1 << 0),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH9_HIZ = (0x1 << 1),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH10_HIZ = (0x1 << 2),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH11_HIZ = (0x1 << 3),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH12_HIZ = (0x1 << 4),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH13_HIZ = (0x1 << 5),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH14_HIZ = (0x1 << 6),
+ MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH15_HIZ = (0x1 << 7),
+
+ /* PCM Tx Channel Sources A (Address 0x001e)*/
+ MAX98927_PCM_Tx_Channel_Sources_A = 0x001e,
+ MAX98927_PCM_Tx_Channel_Sources_A_PCM_IVADC_V_DEST_Mask = (0xf << 0),
+ MAX98927_PCM_Tx_Channel_Sources_A_PCM_IVADC_I_DEST_Mask = (0xf << 4),
+
+ /* PCM Tx Channel Sources B (Address 0x001f)*/
+ MAX98927_PCM_Tx_Channel_Sources_B = 0x001f,
+ MAX98927_PCM_Tx_Channel_Sources_B_PCM_AMP_DSP_DEST_Mask = (0xf << 0),
+ MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask = (0x1 << 5),
+
+ /* PCM Mode Config (Address 0x0020)*/
+ MAX98927_PCM_Mode_Config = 0x0020,
+ MAX98927_PCM_Mode_Config_PCM_TX_EXTRA_HIZ = (0x1 << 0),
+ MAX98927_PCM_Mode_Config_PCM_CHANSEL = (0x1 << 1),
+ MAX98927_PCM_Mode_Config_PCM_BCLKEDGE = (0x1 << 2),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_Mask = (0x7 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_I2S = (0x0 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_LEFT = (0x1 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_0 = (0x3 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_1 = (0x4 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_2 = (0x5 << 3),
+ MAX98927_PCM_Mode_Config_PCM_FORMAT_ = (0x6 << 3),
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_Mask = (0x3 << 6),
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_16 = (0x1 << 6),
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_24 = (0x2 << 6),
+ MAX98927_PCM_Mode_Config_PCM_CHANSZ_32 = (0x3 << 6),
+
+ /* PCM Master Mode (Address 0x0021)*/
+ MAX98927_PCM_Master_Mode = 0x0021,
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask = (0x3 << 0),
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_SLAVE = (0x0 << 0),
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_MASTER = (0x3 << 0),
+ MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_HYBRID = (0x1 << 0),
+ MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_Mask = (0xf << 2),
+ MAX98927_PCM_Master_Mode_PCM_CLK_SOURCE = (0x1 << 6),
+
+ /* PCM Clock setup (Address 0x0022)*/
+ MAX98927_PCM_Clock_setup = 0x0022,
+ MAX98927_PCM_Clock_setup_PCM_BSEL_Mask = (0xf << 0),
+ MAX98927_PCM_Clock_setup_PCM_MSEL_Mask = (0xf << 4),
+
+ /* PCM Sample rate setup 1 (Address 0x0023)*/
+ MAX98927_PCM_Sample_rate_setup_1 = 0x0023,
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_Mask = (0xf << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_8000 = (0x0 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_11025 = (0x1 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_12000 = (0x2 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_16000 = (0x3 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_22050 = (0x4 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_24000 = (0x5 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_32000 = (0x6 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_44100 = (0x7 << 0),
+ MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_48000 = (0x8 << 0),
+
+ /* PCM Sample rate setup 1 (Address 0x0024)*/
+ MAX98927_PCM_Sample_rate_setup_2 = 0x0024,
+ MAX98927_PCM_Sample_rate_setup_2_IVADC_SR_Mask = (0xf << 0),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_Mask = (0xf << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0001 = (0x0 << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0011 = (0x2 << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0101 = (0x4 << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0111 = (0x6 << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1001 = (0x8 << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1011 = (0xa << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1101 = (0xc << 4),
+ MAX98927_PCM_Sample_rate_setup_2_SPK_SR_ = (0xf << 4),
+
+ /* PCM to speaker monomix A (Address 0x0025)*/
+ MAX98927_PCM_to_speaker_monomix_A = 0x0025,
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CH0_SOURCE_Mask = (0xf << 0),
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask = (0x3 << 6),
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_1 = (0x0 << 6),
+ MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_3 = (0x0 << 6),
+
+ /* PCM to speaker monomix B (Address 0x0026)*/
+ MAX98927_PCM_to_spkmonomix_B = 0x0026,
+ MAX98927_PCM_to_spkmonomix_B_DMONOMIX_CH1_SOURCE_Mask = (0xf << 0),
+
+ /* ICC RX Enables A (Address 0x0027)*/
+ MAX98927_ICC_RX_Enables_A = 0x0027,
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH0_EN = (0x1 << 0),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH1_EN = (0x1 << 1),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH2_EN = (0x1 << 2),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH3_EN = (0x1 << 3),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH4_EN = (0x1 << 4),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH5_EN = (0x1 << 5),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH6_EN = (0x1 << 6),
+ MAX98927_ICC_RX_Enables_A_ICC_RX_CH7_EN = (0x1 << 7),
+
+ /* ICC RX Enables B (Address 0x0028)*/
+ MAX98927_ICC_RX_Enables_B = 0x0028,
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH8_EN = (0x1 << 0),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH9_EN = (0x1 << 1),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH10_EN = (0x1 << 2),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH11_EN = (0x1 << 3),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH12_EN = (0x1 << 4),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH13_EN = (0x1 << 5),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH14_EN = (0x1 << 6),
+ MAX98927_ICC_RX_Enables_B_ICC_RX_CH15_EN = (0x1 << 7),
+
+ /* ICC TX Enables A (Address 0x002b)*/
+ MAX98927_ICC_TX_Enables_A = 0x002b,
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH0_EN = (0x1 << 0),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH1_EN = (0x1 << 1),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH2_EN = (0x1 << 2),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH3_EN = (0x1 << 3),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH4_EN = (0x1 << 4),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH5_EN = (0x1 << 5),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH6_EN = (0x1 << 6),
+ MAX98927_ICC_TX_Enables_A_ICC_TX_CH7_EN = (0x1 << 7),
+
+ /* ICC TX Enables B (Address 0x002c)*/
+ MAX98927_ICC_TX_Enables_B = 0x002c,
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH8_EN = (0x1 << 0),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH9_EN = (0x1 << 1),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH10_EN = (0x1 << 2),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH11_EN = (0x1 << 3),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH12_EN = (0x1 << 4),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH13_EN = (0x1 << 5),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH14_EN = (0x1 << 6),
+ MAX98927_ICC_TX_Enables_B_ICC_TX_CH15_EN = (0x1 << 7),
+
+ /* ICC Data Order Select (Address 0x002d)*/
+ MAX98927_ICC_Data_Order_Select = 0x002d,
+ MAX98927_ICC_Data_Order_Select_ICC_DRIVE_MODE = (0x1 << 3),
+
+ /* ICC HiZ Manual Mode (Address 0x002e)*/
+ MAX98927_ICC_HiZ_Manual_Mode = 0x002e,
+ MAX98927_ICC_HiZ_Manual_Mode_ICC_TX_HIZ_MANUAL = (0x1 << 0),
+ MAX98927_ICC_HiZ_Manual_Mode_ICC_TX_EXTRA_HIZ = (0x1 << 1),
+
+ /* ICC TX HiZ Enables A (Address 0x002f)*/
+ MAX98927_ICC_TX_HiZ_Enables_A = 0x002f,
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH0_HIZ = (0x1 << 0),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH1_HIZ = (0x1 << 1),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH2_HIZ = (0x1 << 2),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH3_HIZ = (0x1 << 3),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH4_HIZ = (0x1 << 4),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH5_HIZ = (0x1 << 5),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH6_HIZ = (0x1 << 6),
+ MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH7_HIZ = (0x1 << 7),
+
+ /* ICC TX HiZ Enables B (Address 0x0030)*/
+ MAX98927_ICC_TX_HiZ_Enables_B = 0x0030,
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH8_HIZ = (0x1 << 0),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH9_HIZ = (0x1 << 1),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH10_HIZ = (0x1 << 2),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH11_HIZ = (0x1 << 3),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH12_HIZ = (0x1 << 4),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH13_HIZ = (0x1 << 5),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH14_HIZ = (0x1 << 6),
+ MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH15_HIZ = (0x1 << 7),
+
+ /* ICC Link Enables (Address 0x0031)*/
+ MAX98927_ICC_Link_Enables = 0x0031,
+ MAX98927_ICC_Link_Enables_ICC_LINK_EN = (0x1 << 1),
+
+ /* PDM Tx Enables (Address 0x0032)*/
+ MAX98927_PDM_Tx_Enables = 0x0032,
+ MAX98927_PDM_Tx_Enables_PDM_TX_EN = (0x1 << 0),
+ MAX98927_PDM_Tx_Enables_PDM_TX_CLK_DIV2 = (0x1 << 1),
+
+ /* PDM Tx HiZ Control (Address 0x0033)*/
+ MAX98927_PDM_Tx_HiZ_Control = 0x0033,
+ MAX98927_PDM_Tx_HiZ_Control_PDM_TX_HIZ = (0x1 << 0),
+
+ /* PDM Tx Control (Address 0x0034)*/
+ MAX98927_PDM_Tx_Control = 0x0034,
+ MAX98927_PDM_Tx_Control_PDM_TX_CH0_SOURCE = (0x1 << 0),
+ MAX98927_PDM_Tx_Control_PDM_TX_CH1_SOURCE = (0x1 << 1),
+
+ /* PDM Rx Enable (Address 0x0034)*/
+ MAX98927_PDM_Rx_Enable = 0x0035,
+ MAX98927_PDM_Rx_Enable_PDM_RX_EN = (0x1 << 0),
+ MAX98927_PDM_Rx_Enable_PDM_DSP_EN = (0x1 << 1),
+ MAX98927_PDM_Rx_Enable_PDM_DITH_EN = (0x1 << 2),
+ MAX98927_PDM_Rx_Enable_PDM_RX_CH_SEL = (0x1 << 3),
+ MAX98927_PDM_Rx_Enable_PDM_FIFO_RDY_LVL_Mask = (0xf << 4),
+
+ /* AMP volume control (Address 0x0036)*/
+ MAX98927_AMP_volume_control = 0x0036,
+ MAX98927_AMP_volume_control_AMP_VOL_Mask = (0x7f << 0),
+ MAX98927_AMP_volume_control_AMP_VOL_SEL = (0x1 << 7),
+
+ /* AMP DSP Config (Address 0x0037)*/
+ MAX98927_AMP_DSP_Config = 0x0037,
+ MAX98927_AMP_DSP_Config_AMP_DCBLK_EN = (0x1 << 0),
+ MAX98927_AMP_DSP_Config_AMP_DITH_EN = (0x1 << 1),
+ MAX98927_AMP_DSP_Config_DAC_HALF_REF_CURRENT = (0x1 << 2),
+ MAX98927_AMP_DSP_Config_DAC_DOUBLE_RFB = (0x1 << 3),
+ MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS = (0x1 << 4),
+ MAX98927_AMP_DSP_Config_DAC_INVERT = (0x1 << 5),
+
+ /* Tone Generator and DC Config (Address 0x0038)*/
+ MAX98927_Tone_Generator_and_DC_Config = 0x0038,
+ MAX98927_Tone_Generator_and_DC_Config_TONE_CONFIG_Mask = (0xf << 0),
+
+ /* DRE Control (Address 0x0039)*/
+ MAX98927_DRE_Control = 0x0039,
+ MAX98927_DRE_Control_DRE_EN = (0x1 << 0),
+
+ /* AMP enables (Address 0x003a)*/
+ MAX98927_AMP_enables = 0x003a,
+ MAX98927_AMP_enables_SPK_EN = (0x1 << 0),
+
+ /* Speaker source select (Address 0x003b)*/
+ MAX98927_Speaker_source_select = 0x003b,
+ MAX98927_Speaker_source_select_SPK_SOURCE_Mask = (0x3 << 0),
+ MAX98927_Speaker_source_select_SPK_SOURCE_01 = (0x0 << 0),
+ MAX98927_Speaker_source_select_SPK_SOURCE_11 = (0x2 << 0),
+
+ /* Speaker Gain (Address 0x003c)*/
+ MAX98927_Speaker_Gain = 0x003c,
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_Mask = (0x7 << 0),
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_001 = (0x0 << 0),
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_011 = (0x2 << 0),
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_101 = (0x4 << 0),
+ MAX98927_Speaker_Gain_SPK_PCM_GAIN_111 = (0x6 << 0),
+ MAX98927_Speaker_Gain_SPK_PDM_GAIN_Mask = (0x7 << 4),
+ MAX98927_Speaker_Gain_SPK_PDM_GAIN_001 = (0x0 << 4),
+ MAX98927_Speaker_Gain_SPK_PDM_GAIN_011 = (0x2 << 4),
+ MAX98927_Speaker_Gain_SPK_PDM_GAIN_101 = (0x4 << 4),
+ MAX98927_Speaker_Gain_SPK_PDM_GAIN_111 = (0x6 << 4),
+
+ /* SSM Configuration (Address 0x003d)*/
+ MAX98927_SSM_Configuration = 0x003d,
+ MAX98927_SSM_Configuration_SSM_MOD_INDEX_Mask = (0x7 << 0),
+ MAX98927_SSM_Configuration_SSM_MOD_INDEX_001 = (0x0 << 0),
+ MAX98927_SSM_Configuration_SSM_MOD_INDEX_011 = (0x2 << 0),
+ MAX98927_SSM_Configuration_SSM_MOD_INDEX_101 = (0x4 << 0),
+ MAX98927_SSM_Configuration_SSM_MOD_INDEX_ = (0x6 << 0),
+ MAX98927_SSM_Configuration_SPK_FSW_SEL = (0x1 << 3),
+ MAX98927_SSM_Configuration_SSM_ENA = (0x1 << 7),
+
+ /* Measurement enables (Address 0x003e)*/
+ MAX98927_Measurement_enables = 0x003e,
+ MAX98927_Measurement_enables_IVADC_V_EN = (0x1 << 0),
+ MAX98927_Measurement_enables_IVADC_I_EN = (0x1 << 1),
+
+ /* Measurement DSP Config (Address 0x003f)*/
+ MAX98927_Measurement_DSP_Config = 0x003f,
+ MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_EN = (0x1 << 0),
+ MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_EN = (0x1 << 1),
+ MAX98927_Measurement_DSP_Config_MEAS_DITH_EN = (0x1 << 2),
+ MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_Mask = (0x3 << 4),
+ MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_01 = (0x0 << 4),
+ MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_11 = (0x2 << 4),
+ MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_Mask = (0x3 << 6),
+ MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_01 = (0x0 << 6),
+ MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_11 = (0x2 << 6),
+
+ /* Boost Control 0 (Address 0x0040)*/
+ MAX98927_Boost_Control_0 = 0x0040,
+ MAX98927_Boost_Control_0_BST_VOUT_Mask = (0x1f << 0),
+ MAX98927_Boost_Control_0_EXT_PVDD_EN = (0x1 << 7),
+
+ /* Boost Control 3 (Address 0x0041)*/
+ MAX98927_Boost_Control_3 = 0x0041,
+ MAX98927_Boost_Control_3_BST_SKIPLOAD_Mask = (0x3 << 0),
+ MAX98927_Boost_Control_3_BST_SKIPLOAD_01 = (0x0 << 0),
+ MAX98927_Boost_Control_3_BST_SKIPLOAD_11 = (0x2 << 0),
+ MAX98927_Boost_Control_3_BST_PHASE_Mask = (0x7 << 2),
+ MAX98927_Boost_Control_3_BST_PHASE_001 = (0x0 << 2),
+ MAX98927_Boost_Control_3_BST_PHASE_011 = (0x2 << 2),
+ MAX98927_Boost_Control_3_BST_PHASE_ = (0x1 << 2),
+ MAX98927_Boost_Control_3_BST_SLOWSTART = (0x1 << 5),
+
+ /* Boost Control 1 (Address 0x0042)*/
+ MAX98927_Boost_Control_1 = 0x0042,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Boost_Control_1_BST_ILIM_Mask = (0x3f << 0),
+
+ /* Meas ADC Config (Address 0x0043)*/
+ MAX98927_Meas_ADC_Config = 0x0043,
+ MAX98927_Meas_ADC_Config_MEAS_ADC_CH0_EN = (0x1 << 0),
+ MAX98927_Meas_ADC_Config_MEAS_ADC_CH1_EN = (0x1 << 1),
+ MAX98927_Meas_ADC_Config_MEAS_ADC_CH2_EN = (0x1 << 2),
+
+ /* Meas ADC Base Divide MSByte (Address 0x0044)*/
+ MAX98927_Meas_ADC_Base_Divide_MSByte = 0x0044,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Base_Divide_MSByte_MEAS_ADC_BASE_DIV_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Base Divide LSByte (Address 0x0045)*/
+ MAX98927_Meas_ADC_Base_Divide_LSByte = 0x0045,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Base_Divide_LSByte_MEAS_ADC_BASE_DIV_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Chan 0 Divide (Address 0x0046)*/
+ MAX98927_Meas_ADC_Chan_0_Divide = 0x0046,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_0_Divide_MEAS_ADC_CH0_DIV_Mask = (0xff << 0),
+
+ /* Meas ADC Chan 1 Divide (Address 0x0047)*/
+ MAX98927_Meas_ADC_Chan_1_Divide = 0x0047,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_1_Divide_MEAS_ADC_CH1_DIV_Mask = (0xff << 0),
+
+ /* Meas ADC Chan 2 Divide (Address 0x0048)*/
+ MAX98927_Meas_ADC_Chan_2_Divide = 0x0048,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_2_Divide_MEAS_ADC_CH2_DIV_Mask = (0xff << 0),
+
+ /* Meas ADC Chan 0 Filt Config (Address 0x0049)*/
+ MAX98927_Meas_ADC_Chan_0_Filt_Config = 0x0049,
+ MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_Mask
+ = (0x7 << 0),
+ MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_001
+ = (0x0 << 0),
+ MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_011
+ = (0x2 << 0),
+ MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_101
+ = (0x4 << 0),
+ MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_EN
+ = (0x1 << 3),
+
+ /* Meas ADC Chan 1 Filt Config (Address 0x004a)*/
+ MAX98927_Meas_ADC_Chan_1_Filt_Config = 0x004a,
+ MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_Mask
+ = (0x7 << 0),
+ MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_001
+ = (0x0 << 0),
+ MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_011
+ = (0x2 << 0),
+ MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_101
+ = (0x4 << 0),
+ MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_EN
+ = (0x1 << 3),
+
+ /* Meas ADC Chan 2 Filt Config (Address 0x004b)*/
+ MAX98927_Meas_ADC_Chan_2_Filt_Config = 0x004b,
+ MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_Mask
+ = (0x7 << 0),
+ MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_001
+ = (0x0 << 0),
+ MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_011
+ = (0x2 << 0),
+ MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_101
+ = (0x4 << 0),
+ MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_EN
+ = (0x1 << 3),
+
+ /* Meas ADC Chan 0 Readback (Address 0x004c)*/
+ MAX98927_Meas_ADC_Chan_0_Readback = 0x004c,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_0_Readback_MEAS_ADC_CH0_DATA_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Chan 1 Readback (Address 0x004d)*/
+ MAX98927_Meas_ADC_Chan_1_Readback = 0x004d,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_1_Readback_MEAS_ADC_CH1_DATA_Mask
+ = (0xff << 0),
+
+ /* Meas ADC Chan 2 Readback (Address 0x004e)*/
+ MAX98927_Meas_ADC_Chan_2_Readback = 0x004e,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Meas_ADC_Chan_2_Readback_MEAS_ADC_CH2_DATA_Mask
+ = (0xff << 0),
+
+ /* Brownout status (Address 0x0051)*/
+ MAX98927_Brownout_status = 0x0051,
+ MAX98927_Brownout_status_BDE_STATE_Mask = (0xf << 0),
+
+ /* Brownout enables (Address 0x0052)*/
+ MAX98927_Brownout_enables = 0x0052,
+ MAX98927_Brownout_enables_BDE_EN = (0x1 << 0),
+ MAX98927_Brownout_enables_BDE_AMP_EN = (0x1 << 1),
+ MAX98927_Brownout_enables_AMP_DSP_EN = (0x1 << 2),
+
+ /* Brownout level infinite hold (Address 0x0053)*/
+ MAX98927_Brownout_level_infinite_hold = 0x0053,
+ MAX98927_Brownout_level_infinite_hold_BDE_L8_INF_HLD = (0x1 << 1),
+
+ /* Brownout level infinite hold clear (Address 0x0054)*/
+ MAX98927_Brownout_level_infinite_hold_clear = 0x0054,
+ MAX98927_Brownout_level_infinite_hold_clear_BDE_L8_HLD_RLS
+ = (0x1 << 1),
+
+ /* Brownout level hold (Address 0x0055)*/
+ MAX98927_Brownout_level_hold = 0x0055,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout_level_hold_BDE_HLD_Mask = (0xff << 0),
+
+ /* Brownout level 1 threshold (Address 0x0056)*/
+ MAX98927_Brownout__level_1_threshold = 0x0056,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_1_threshold_BDE_L1_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 2 threshold (Address 0x0057)*/
+ MAX98927_Brownout__level_2_threshold = 0x0057,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_2_threshold_BDE_L2_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 3 threshold (Address 0x0058)*/
+ MAX98927_Brownout__level_3_threshold = 0x0058,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_3_threshold_BDE_L3_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 4 threshold (Address 0x0059)*/
+ MAX98927_Brownout__level_4_threshold = 0x0059,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_4_threshold_BDE_L4_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 5 threshold (Address 0x005a)*/
+ MAX98927_Brownout__level_5_threshold = 0x005a,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_5_threshold_BDE_L5_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 6 threshold (Address 0x005b)*/
+ MAX98927_Brownout__level_6_threshold = 0x005b,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_6_threshold_BDE_L6_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 7 threshold (Address 0x005c)*/
+ MAX98927_Brownout__level_7_threshold = 0x005c,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_7_threshold_BDE_L7_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout level 8 threshold (Address 0x005d)*/
+ MAX98927_Brownout__level_8_threshold = 0x005d,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_8_threshold_BDE_L8_VTHRESH_Mask = (0xff << 0),
+
+ /* Brownout threshold hysterysis (Address 0x005e)*/
+ MAX98927_Brownout_threshold_hysterysis = 0x005e,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout_threshold_hysterysis_BDE_VTHRESH_HYST_Mask
+ = (0xff << 0),
+ /* Brownout AMP limiter attack/release (Address 0x005f)*/
+ MAX98927_Brownout_AMP_limiter_attack_release = 0x005f,
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_Mask
+ = (0xf << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0001
+ = (0x0 << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0011
+ = (0x2 << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0101
+ = (0x4 << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0111
+ = (0x6 << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1001
+ = (0x8 << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1011
+ = (0xa << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1101
+ = (0xc << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1111
+ = (0xe << 0),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_Mask
+ = (0xf << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0001
+ = (0x0 << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0011
+ = (0x2 << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0101
+ = (0x4 << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0111
+ = (0x6 << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1001
+ = (0x8 << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1011
+ = (0xa << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1101
+ = (0xc << 4),
+ MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1111
+ = (0xe << 4),
+
+ /* Brownout AMP gain attack/release (Address 0x0060)*/
+ MAX98927_Brownout_AMP_gain_attack_release = 0x0060,
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_Mask
+ = (0xf << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0001
+ = (0x0 << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0011
+ = (0x2 << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0101
+ = (0x4 << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0111
+ = (0x6 << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1001
+ = (0x8 << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1011
+ = (0xa << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1101
+ = (0xc << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1111
+ = (0xe << 0),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_Mask
+ = (0xf << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0001
+ = (0x0 << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0011
+ = (0x2 << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0101
+ = (0x4 << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0111
+ = (0x6 << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1001
+ = (0x8 << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1011
+ = (0xa << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1101
+ = (0xc << 4),
+ MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1111
+ = (0xe << 4),
+
+ /* Brownout AMP1 clip mode (Address 0x0061)*/
+ MAX98927_Brownout_AMP1_clip_mode = 0x0061,
+ MAX98927_Brownout_AMP1_clip_mode_AMP_CLIP_MODE = (0x1 << 0),
+
+ /* Brownout level 1 current limit (Address 0x0062)*/
+ MAX98927_Brownout__level_1_current_limit = 0x0062,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_1_current_limit_BDE_L1_ILIM_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 1 amp 1 control 1 (Address 0x0063)*/
+ MAX98927_Brownout__level_1_amp_1_control_1 = 0x0063,
+ MAX98927_Brownout__level_1_amp_1_control_1_BDE_L1_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 1 amp 1 control 2 (Address 0x0064)*/
+ MAX98927_Brownout__level_1_amp_1_control_2 = 0x0064,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_1_amp_1_control_2_BDE_L1_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 1 amp 1 control 3 (Address 0x0065)*/
+ MAX98927_Brownout__level_1_amp_1_control_3 = 0x0065,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_1_amp_1_control_3_BDE_L1_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 2 current limit (Address 0x0066)*/
+ MAX98927_Brownout__level_2_current_limit = 0x0066,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_2_current_limit_BDE_L2_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 2 amp 1 control 1 (Address 0x0067)*/
+ MAX98927_Brownout__level_2_amp_1_control_1 = 0x0067,
+ MAX98927_Brownout__level_2_amp_1_control_1_BDE_L2_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 2 amp 1 control 2 (Address 0x0068)*/
+ MAX98927_Brownout__level_2_amp_1_control_2 = 0x0068,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_2_amp_1_control_2_BDE_L2_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 2 amp 1 control 3 (Address 0x0069)*/
+ MAX98927_Brownout__level_2_amp_1_control_3 = 0x0069,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_2_amp_1_control_3_BDE_L2_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 3 current limit (Address 0x006a)*/
+ MAX98927_Brownout__level_3_current_limit = 0x006a,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_3_current_limit_BDE_L3_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 3 amp 1 control 1 (Address 0x006b)*/
+ MAX98927_Brownout__level_3_amp_1_control_1 = 0x006b,
+ MAX98927_Brownout__level_3_amp_1_control_1_BDE_L3_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 3 amp 1 control 2 (Address 0x006c)*/
+ MAX98927_Brownout__level_3_amp_1_control_2 = 0x006c,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_3_amp_1_control_2_BDE_L3_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 3 amp 1 control 3 (Address 0x006d)*/
+ MAX98927_Brownout__level_3_amp_1_control_3 = 0x006d,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_3_amp_1_control_3_BDE_L3_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 4 current limit (Address 0x006e)*/
+ MAX98927_Brownout__level_4_current_limit = 0x006e,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_4_current_limit_BDE_L4_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 4 amp 1 control 1 (Address 0x006f)*/
+ MAX98927_Brownout__level_4_amp_1_control_1 = 0x006f,
+ MAX98927_Brownout__level_4_amp_1_control_1_BDE_L4_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 4 amp 1 control 2 (Address 0x0070)*/
+ MAX98927_Brownout__level_4_amp_1_control_2 = 0x0070,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_4_amp_1_control_2_BDE_L4_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 4 amp 1 control 3 (Address 0x0071)*/
+ MAX98927_Brownout__level_4_amp_1_control_3 = 0x0071,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_4_amp_1_control_3_BDE_L4_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 5 current limit (Address 0x0072)*/
+ MAX98927_Brownout__level_5_current_limit = 0x0072,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_5_current_limit_BDE_L5_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 5 amp 1 control 1 (Address 0x0073)*/
+ MAX98927_Brownout__level_5_amp_1_control_1 = 0x0073,
+ MAX98927_Brownout__level_5_amp_1_control_1_BDE_L5_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 5 amp 1 control 2 (Address 0x0074)*/
+ MAX98927_Brownout__level_5_amp_1_control_2 = 0x0074,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_5_amp_1_control_2_BDE_L5_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 5 amp 1 control 3 (Address 0x0075)*/
+ MAX98927_Brownout__level_5_amp_1_control_3 = 0x0075,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_5_amp_1_control_3_BDE_L5_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 6 current limit (Address 0x0076)*/
+ MAX98927_Brownout__level_6_current_limit = 0x0076,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_6_current_limit_BDE_L6_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 6 amp 1 control 1 (Address 0x0077)*/
+ MAX98927_Brownout__level_6_amp_1_control_1 = 0x0077,
+ MAX98927_Brownout__level_6_amp_1_control_1_BDE_L6_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 6 amp 1 control 2 (Address 0x0078)*/
+ MAX98927_Brownout__level_6_amp_1_control_2 = 0x0078,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_6_amp_1_control_2_BDE_L6_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 6 amp 1 control 3 (Address 0x0079)*/
+ MAX98927_Brownout__level_6_amp_1_control_3 = 0x0079,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_6_amp_1_control_3_BDE_L6_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 7 current limit (Address 0x007a)*/
+ MAX98927_Brownout__level_7_current_limit = 0x007a,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_7_current_limit_BDE_L7_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 7 amp 1 control 1 (Address 0x007b)*/
+ MAX98927_Brownout__level_7_amp_1_control_1 = 0x007b,
+ MAX98927_Brownout__level_7_amp_1_control_1_BDE_L7_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 7 amp 1 control 2 (Address 0x007c)*/
+ MAX98927_Brownout__level_7_amp_1_control_2 = 0x007c,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_7_amp_1_control_2_BDE_L7_AMP1_CLIP_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 7 amp 1 control 3 (Address 0x007d)*/
+ MAX98927_Brownout__level_7_amp_1_control_3 = 0x007d,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_7_amp_1_control_3_BDE_L7_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Brownout level 8 current limit (Address 0x007e)*/
+ MAX98927_Brownout__level_8_current_limit = 0x007e,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_8_current_limit_BDE_L8_ILIM_Mask = (0x3f << 0),
+
+ /* Brownout level 8 amp 1 control 1 (Address 0x007f)*/
+ MAX98927_Brownout__level_8_amp_1_control_1 = 0x007f,
+ MAX98927_Brownout__level_8_amp_1_control_1_BDE_L8_AMP1_LIM_Mask
+ = (0xf << 0),
+
+ /* Brownout level 8 amp 1 control 2 (Address 0x0080)*/
+ MAX98927_Brownout__lvl_8_amp_1_control_2 = 0x0080,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__lvl_8_amp_1_control_2_BDE_L8_AMP1_CLIP_Mask
+ = (0x3f << 0),
+ MAX98927_Brownout__lvl_8_amp_1_control_2_BDE_L8_AMP1_MUTE
+ = (0x1 << 7),
+
+ /* Brownout level 8 amp 1 control 3 (Address 0x0081)*/
+ MAX98927_Brownout__level_8_amp_1_control_3 = 0x0081,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Brownout__level_8_amp_1_control_3_BDE_L8_AMP1_GAIN_Mask
+ = (0x3f << 0),
+
+ /* Env Tracker Vout Headroom (Address 0x0082)*/
+ MAX98927_Env_Tracker_Vout_Headroom = 0x0082,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Env_Tracker_Vout_Head_ENV_TRACKER_BST_VOUT_HEADROOM_Mask
+ = (0x1f << 0),
+
+ /* Env Tracker Boost Vout Delay (Address 0x0083)*/
+ MAX98927_Env_Tracker_Boost_Vout_Delay = 0x0083,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Env_Tracker_Boost_V_Delay_ENV_TRACKER_BST_VOUT_DELAY_Mask
+ = (0x1f << 0),
+ MAX98927_Env_Tracker_Boost_Vout_Delay_ENV_TRACKER_BDE_MODE
+ = (0x1 << 7),
+
+ /* Env Tracker Release Rate (Address 0x0084)*/
+ MAX98927_Env_Tracker_Release_Rate = 0x0084,
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_Mask
+ = (0x7 << 0),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_001
+ = (0x0 << 0),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_011
+ = (0x2 << 0),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_101
+ = (0x4 << 0),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_111
+ = (0x6 << 0),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_PEAK_DET_LPF_BYP_EN
+ = (0x1 << 3),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_Mask
+ = (0x3 << 4),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_01
+ = (0x0 << 4),
+ MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_11
+ = (0x2 << 4),
+
+ /* Env Tracker Hold Rate (Address 0x0085)*/
+ MAX98927_Env_Tracker_Hold_Rate = 0x0085,
+ MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_Mask
+ = (0x7 << 0),
+ MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_001
+ = (0x0 << 0),
+ MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_011
+ = (0x2 << 0),
+ MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_101
+ = (0x4 << 0),
+ MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_111
+ = (0x6 << 0),
+
+ /* Env Tracker Control (Address 0x0086)*/
+ MAX98927_Env_Tracker_Control = 0x0086,
+ MAX98927_Env_Tracker_Control_ENV_TRACKER_EN = (0x1 << 0),
+
+ /* Env Tracker Boost Vout ReadBack (Address 0x0087)*/
+ MAX98927_Env_Tracker__Boost_Vout_ReadBack = 0x0087,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Env_Tracker__Boost_Vout_RB_ENV_TRACKER_BST_VOUT_RD_Mask
+ = (0x1f << 0),
+
+ /* Advanced Settings (Address 0x0089)*/
+ MAX98927_Advanced_Settings = 0x0089,
+ MAX98927_Advanced_Settings_DAC_HALF_FIR = (0x1 << 0),
+ MAX98927_Advanced_Settings_PDM_MOD_SEL = (0x1 << 1),
+ MAX98927_Advanced_Settings_ISOCH_EN = (0x1 << 2),
+
+ /* DAC Test 1 (Address 0x009f)*/
+ MAX98927_DAC_Test_1 = 0x009f,
+ MAX98927_DAC_Test_1_DAC_PCM_TIMING = (0x1 << 0),
+ MAX98927_DAC_Test_1_DAC_HALFI_AMP = (0x1 << 1),
+ MAX98927_DAC_Test_1_DAC_LONG_HOLD = (0x1 << 3),
+ MAX98927_DAC_Test_1_DAC_DISABLE_CHOP = (0x1 << 4),
+ MAX98927_DAC_Test_1_DAC_TM = (0x1 << 5),
+ MAX98927_DAC_Test_1_DAC_INVERT_DACCLK = (0x1 << 6),
+
+ /* Authentication key 0 (Address 0x00ea)*/
+ MAX98927_Authentication_key_0 = 0x00ea,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_key_0_AUTH_KEY_Mask = (0xff << 0),
+
+ /* Authentication key 1 (Address 0x00eb)*/
+ MAX98927_Authentication_key_1 = 0x00eb,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_key_1_AUTH_KEY_Mask = (0xff << 0),
+
+ /* Authentication key 2 (Address 0x00ec)*/
+ MAX98927_Authentication_key_2 = 0x00ec,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_key_2_AUTH_KEY_Mask = (0xff << 0),
+
+ /* Authentication key 3 (Address 0x00ed)*/
+ MAX98927_Authentication_key_3 = 0x00ed,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_key_3_AUTH_KEY_Mask = (0xff << 0),
+
+ /* Authentication enable (Address 0x00ee)*/
+ MAX98927_Authentication_enable = 0x00ee,
+ MAX98927_Authentication_enable_AUTH_EN = (0x1 << 0),
+
+ /* Authentication result 0 (Address 0x00ef)*/
+ MAX98927_Authentication_result_0 = 0x00ef,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_0_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 1 (Address 0x00f0)*/
+ MAX98927_Authentication_result_1 = 0x00f0,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_1_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 2 (Address 0x00f1)*/
+ MAX98927_Authentication_result_2 = 0x00f1,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_2_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 3 (Address 0x00f2)*/
+ MAX98927_Authentication_result_3 = 0x00f2,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_3_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 4 (Address 0x00f3)*/
+ MAX98927_Authentication_result_4 = 0x00f3,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_4_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 5 (Address 0x00f4)*/
+ MAX98927_Authentication_result_5 = 0x00f4,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_5_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 6 (Address 0x00f5)*/
+ MAX98927_Authentication_result_6 = 0x00f5,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_6_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 7 (Address 0x00f6)*/
+ MAX98927_Authentication_result_7 = 0x00f6,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_7_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 8 (Address 0x00f7)*/
+ MAX98927_Authentication_result_8 = 0x00f7,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_8_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 9 (Address 0x00f8)*/
+ MAX98927_Authentication_result_9 = 0x00f8,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_9_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 10 (Address 0x00f9)*/
+ MAX98927_Authentication_result_10 = 0x00f9,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_10_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 11 (Address 0x00fa)*/
+ MAX98927_Authentication_result_11 = 0x00fa,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_11_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 12 (Address 0x00fb)*/
+ MAX98927_Authentication_result_12 = 0x00fb,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_12_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 13 (Address 0x00fc)*/
+ MAX98927_Authentication_result_13 = 0x00fc,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_13_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 14 (Address 0x00fd)*/
+ MAX98927_Authentication_result_14 = 0x00fd,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_14_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Authentication result 15 (Address 0x00fe)*/
+ MAX98927_Authentication_result_15 = 0x00fe,
+ /*#BYHAND width >= 5:*/
+ MAX98927_Authentication_result_15_AUTH_RESULT_Mask = (0xff << 0),
+
+ /* Global Enable (Address 0x00ff)*/
+ MAX98927_Global_Enable = 0x00ff,
+ MAX98927_Global_Enable_EN = (0x1 << 0),
+ /* Software Reset (Address 0x0100)*/
+ MAX98927_Software_Reset = 0x0100,
+ MAX98927_Software_Reset_RST = (0x1 << 0),
+
+ /* REV ID (Address 0x01ff)*/
+ MAX98927_REV_ID = 0x01ff,
+ /*#BYHAND width >= 5:*/
+ MAX98927_REV_ID_REV_ID_Mask = (0xff << 0),
+} MAX98927Registers;
+
+struct max98927_reg_default {
+ unsigned int ch;
+ unsigned int reg;
+ unsigned int def;
+};
+struct max98927_priv {
+ struct regmap *regmap;
+ struct regmap *sub_regmap;
+ struct snd_soc_codec *codec;
+ struct max98927_pdata *pdata;
+ const uint32_t *regcfg;
+ uint32_t regcfg_sz;
+ unsigned int spk_gain;
+ unsigned int sysclk;
+ unsigned int v_l_slot;
+ unsigned int i_l_slot;
+ unsigned int v_r_slot;
+ unsigned int i_r_slot;
+ bool interleave_mode;
+ unsigned int ch_size;
+ unsigned int rate;
+ unsigned int iface;
+ unsigned int master;
+ unsigned int thres_hyste;
+ unsigned int level5_hold;
+ unsigned int level6_hold;
+ unsigned int level7_hold;
+ unsigned int level8_hold;
+ unsigned int amp_limit;
+ unsigned int amp_limit_rel;
+ unsigned int amp1_level;
+ unsigned int amp2_level;
+ unsigned int amp3_level;
+ unsigned int amp1_level8;
+ unsigned int amp2_level8;
+ unsigned int amp3_level8;
+ unsigned int amp1_level7;
+ unsigned int amp2_level7;
+ unsigned int amp3_level7;
+ unsigned int amp1_level6;
+ unsigned int amp2_level6;
+ unsigned int amp3_level6;
+ unsigned int amp1_level5;
+ unsigned int amp2_level5;
+ unsigned int amp3_level5;
+ unsigned int digital_gain;
+ unsigned int pdm_gain;
+ unsigned int level_hold;
+ struct i2c_client *sub_i2c;
+ int sub_reg;
+ int sub_bus;
+};
+
+#define MAX98927_GLOBAL_SHIFT 0
+#define M98927_DAI_MSEL_SHIFT 4
+#define M98927_DAI_BSEL_SHIFT 0
+#define M98927_DAI_BSEL_32 (2 << M98927_DAI_BSEL_SHIFT)
+#define M98927_DAI_BSEL_48 (3 << M98927_DAI_BSEL_SHIFT)
+#define M98927_DAI_BSEL_64 (4 << M98927_DAI_BSEL_SHIFT)
+#define M98927_DAI_MSEL_32 (2 << M98927_DAI_MSEL_SHIFT)
+#define M98927_DAI_MSEL_48 (3 << M98927_DAI_MSEL_SHIFT)
+#define M98927_DAI_MSEL_64 (4 << M98927_DAI_MSEL_SHIFT)
+#define MAX98927_Speaker_Gain_Width 3
+#define MAX98927_SPK_RMP_EN_SHIFT 4
+#define MAX98927_PDM_GAIN_SHIFT 4
+#define MAX98927_pdm_Gain_Width 3
+#define MAX98927_AMP_VOL_WIDTH 7
+#define MAX98927_AMP_VOL_LOCATION_SHIFT 7
+#define MAX98927_PDM_Rx_Enable_PDM_CH_SHIFT 3
+#define MAX98927_PCM_to_speaker_monomix_A_SHIFT 6
+#define MAX98927_PCM_Sample_rate_setup_2_DIG_IF_SR_48000 (0x8 << 4)
+#define MAX98927_PCM_FORMAT_DSP_A (0x3 << 3)
+#define MAX98927_DRE_Control_DRE_SHIFT 0x1
+#define MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_SHIFT (2)
+#define MAX98927_Brownout_AMP_limiter_attack_release_shift 4
+#define MAX98927_BDE_DSP_SHIFT 2
+#define MAX98927_Speaker_Gain_SPK_PDM_GAIN_SHIFT (4)
+#define MAX98927_BDE_AMP_SHIFT (1)
+#define MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT (4)
+#endif
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v3 2/2] DW DMAC: add multi-block property to device tree
From: Vinod Koul @ 2016-11-23 4:15 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Eugeniy Paltsev, devicetree, robh+dt, mark.rutland, linux-kernel,
dmaengine, linux-snps-arc
In-Reply-To: <1479497593.22212.45.camel@linux.intel.com>
On Fri, Nov 18, 2016 at 09:33:13PM +0200, Andy Shevchenko wrote:
> > @@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
> > (dwc_params >> DWC_PARAMS_MBLK_EN &
> > 0x1) == 0;
> > } else {
> > dwc->block_size = pdata->block_size;
> > - dwc->nollp = pdata->is_nollp;
> > + dwc->nollp = pdata->multi_block[i];
>
> You missed the point. You assign positive value to negative variable.
> It's a bug. Have you tested this? How?
>
> In case of positive property you have to update DTS. By the way, I'm
> pretty sure that spare13xx boards has auto configuration enabled, though
> it has to be checked with vendor (I assume you may have fast response
> from them).
Yeah why are we not using auto configuration here would be the first
question..
--
~Vinod
^ permalink raw reply
* Re: [PATCH v4 3/3] dmaengine: sun6i: share the dma driver with sun50i
From: Vinod Koul @ 2016-11-23 4:12 UTC (permalink / raw)
To: Hao Zhang
Cc: mark.rutland, devicetree, catalin.marinas, will.deacon,
linux-kernel, wens, robh+dt, dmaengine, maxime.ripard,
dan.j.williams, linux-arm-kernel
In-Reply-To: <1479638740-20520-4-git-send-email-hao5781286@gmail.com>
On Sun, Nov 20, 2016 at 06:45:40PM +0800, Hao Zhang wrote:
> Changes the limited buswith to 8 bytes,and add
> the test in sun6i_dma_config function
>
> Accroding to sun6i dma driver, i think ,if the client
^^^^^^^^
typo and other grammatical mistakes here..
> doesn't configure the address width with dmaengine_slave_config
> function, it would use the default width. So we can add the test
> in sun6i_dma_config function called by dmaengine_slave_config,
> and test the configuration whether is support for the device.
>
> Signed-off-by: Hao Zhang <hao5781286@gmail.com>
> ---
> drivers/dma/sun6i-dma.c | 33 ++++++++++++++++++++++++++++++++-
> 1 file changed, 32 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index a235878..f7c90b6 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -250,7 +250,7 @@ static inline s8 convert_burst(u32 maxburst)
> static inline s8 convert_buswidth(enum dma_slave_buswidth addr_width)
> {
> if ((addr_width < DMA_SLAVE_BUSWIDTH_1_BYTE) ||
> - (addr_width > DMA_SLAVE_BUSWIDTH_4_BYTES))
> + (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES))
> return -EINVAL;
>
> return addr_width >> 1;
> @@ -758,6 +758,18 @@ static int sun6i_dma_config(struct dma_chan *chan,
> {
> struct sun6i_vchan *vchan = to_sun6i_vchan(chan);
>
> + if ((BIT(config->src_addr_width) | chan->device->src_addr_widths) !=
> + chan->device->src_addr_widths) {
First I dont like coding style here
Second, this is not driver specific, should be move to core..
--
~Vinod
^ permalink raw reply
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