* Re: [PATCH] ARM: dts: imx6q-cm-fx6: enable S/PDIF support
From: Fabio Estevam @ 2016-11-23 23:01 UTC (permalink / raw)
To: Christopher Spinrath
Cc: Mark Rutland, devicetree@vger.kernel.org,
Russell King - ARM Linux, robh+dt@kernel.org, Igor Grinberg,
Sascha Hauer, Fabio Estevam, Shawn Guo,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <5da612fbab7a4064993790702550fa77@rwthex-s1-b.rwth-ad.de>
On Tue, Nov 22, 2016 at 10:07 PM, <christopher.spinrath@rwth-aachen.de> wrote:
> From: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
>
> Enable the S/PDIF transceiver present on the cm-fx6 module.
>
> Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* Re: [PATCH v4 1/2] Documentation: dt: reset: Add TI SCI reset binding
From: Rob Herring @ 2016-11-23 23:01 UTC (permalink / raw)
To: Andrew F. Davis
Cc: Nishanth Menon, Mark Rutland, devicetree, linux-kernel,
Tero Kristo, Philipp Zabel, Santosh Shilimkar, linux-arm-kernel
In-Reply-To: <20161121213052.8684-2-afd@ti.com>
On Mon, Nov 21, 2016 at 03:30:51PM -0600, Andrew F. Davis wrote:
> Add TI SCI reset controller binding. This describes the DT binding
> details for a reset controller node providing reset management services
> to hardware blocks (reset consumers) using the Texas Instrument's System
> Control Interface (TI SCI) protocol to communicate to a system controller
> block present on the SoC.
>
> Signed-off-by: Andrew F. Davis <afd@ti.com>
> [s-anna@ti.com: revise the binding format]
> Signed-off-by: Suman Anna <s-anna@ti.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
> ---
> .../devicetree/bindings/reset/ti,sci-reset.txt | 66 ++++++++++++++++++++++
> MAINTAINERS | 2 +
> include/dt-bindings/reset/k2g.h | 22 ++++++++
> 3 files changed, 90 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/ti,sci-reset.txt
> create mode 100644 include/dt-bindings/reset/k2g.h
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 2/2] Add support for the Nexbox A1 board based on the Amlogic S912 SoC.
From: Rob Herring @ 2016-11-23 22:52 UTC (permalink / raw)
To: Neil Armstrong
Cc: khilman-rdvid1DuHRBWk0Htik3J/w, carlo-KA+7E9HrN00dnm+yROfE0A,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161121162905.14285-3-narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On Mon, Nov 21, 2016 at 05:29:05PM +0100, Neil Armstrong wrote:
> Signed-off-by: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> ---
> Documentation/devicetree/bindings/arm/amlogic.txt | 1 +
> arch/arm64/boot/dts/amlogic/Makefile | 1 +
> .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 169 +++++++++++++++++++++
> 3 files changed, 171 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
A few nits below, otherwise:
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> diff --git a/Documentation/devicetree/bindings/arm/amlogic.txt b/Documentation/devicetree/bindings/arm/amlogic.txt
> index 1144214..6ef7c52 100644
> --- a/Documentation/devicetree/bindings/arm/amlogic.txt
> +++ b/Documentation/devicetree/bindings/arm/amlogic.txt
> @@ -45,3 +45,4 @@ Board compatible values:
> - "amlogic,p231" (Meson gxl s905d)
> - "amlogic,q200" (Meson gxm s912)
> - "amlogic,q201" (Meson gxm s912)
> + - "nexbox,a1" (Meson gxm s912)
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile b/arch/arm64/boot/dts/amlogic/Makefile
> index 7752a16..2fbb8e3 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p230.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxl-s905d-p231.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q200.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxm-s912-q201.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-gxm-nexbox-a1.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
> new file mode 100644
> index 0000000..d320727
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts
> @@ -0,0 +1,169 @@
> +/*
> + * Copyright (c) 2016 BayLibre, SAS.
> + * Author: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> + *
> + * Copyright (c) 2016 Endless Computers, Inc.
> + * Author: Carlo Caione <carlo-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-gxm.dtsi"
> +
> +/ {
> + compatible = "nexbox,a1", "amlogic,s912", "amlogic,meson-gxm";
> + model = "NEXBOX A1";
> +
> + aliases {
> + serial0 = &uart_AO;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x0 0x0 0x80000000>;
> + };
> +
> + vddio_boot: regulator-vddio_boot {
Don't use '_' in node names.
> + compatible = "regulator-fixed";
> + regulator-name = "VDDIO_BOOT";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <1800000>;
> + };
> +
> + vddao_3v3: regulator-vddao_3v3 {
ditto
> + compatible = "regulator-fixed";
> + regulator-name = "VDDAO_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + vcc_3v3: regulator-vcc_3v3 {
ditto
> + compatible = "regulator-fixed";
> + regulator-name = "VCC_3V3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + emmc_pwrseq: emmc-pwrseq {
> + compatible = "mmc-pwrseq-emmc";
> + reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +/* This UART is brought out to the DB9 connector */
> +&uart_AO {
> + status = "okay";
> + pinctrl-0 = <&uart_ao_a_pins>;
> + pinctrl-names = "default";
> +};
> +
> +&ir {
> + status = "okay";
> + pinctrl-0 = <&remote_input_ao_pins>;
> + pinctrl-names = "default";
> +};
> +
> +/* SD card */
> +&sd_emmc_b {
> + status = "okay";
> + pinctrl-0 = <&sdcard_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <4>;
> + cap-sd-highspeed;
> + max-frequency = <100000000>;
> + disable-wp;
> +
> + cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>;
> + cd-inverted;
> +
> + vmmc-supply = <&vddao_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +};
> +
> +/* eMMC */
> +&sd_emmc_c {
> + status = "okay";
> + pinctrl-0 = <&emmc_pins>;
> + pinctrl-names = "default";
> +
> + bus-width = <8>;
> + cap-sd-highspeed;
> + cap-mmc-highspeed;
> + max-frequency = <200000000>;
> + non-removable;
> + disable-wp;
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> +
> + mmc-pwrseq = <&emmc_pwrseq>;
> + vmmc-supply = <&vcc_3v3>;
> + vqmmc-supply = <&vddio_boot>;
> +};
> +
> +ðmac {
> + status = "okay";
> +
> + pinctrl-0 = <ð_pins>;
> + pinctrl-names = "default";
> +
> + /* Select external PHY by default */
> + phy-handle = <&external_phy>;
> +
> + snps,reset-gpio = <&gpio GPIOZ_14 0>;
> + snps,reset-delays-us = <0 10000 1000000>;
> + snps,reset-active-low;
> +
> + /* External PHY is in RGMII */
> + phy-mode = "rgmii";
> +};
> +
> +&external_mdio {
> + external_phy: ethernet-phy@0 {
> + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22";
> + reg = <0>;
> + max-speed = <1000>;
> + };
> +};
> --
> 2.7.0
>
> --
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^ permalink raw reply
* Re: [PATCH v2] ARM: dts: da850: add the mstpri and ddrctl nodes
From: David Lechner @ 2016-11-23 22:48 UTC (permalink / raw)
To: Kevin Hilman
Cc: Bartosz Golaszewski, Michael Turquette, Sekhar Nori, Rob Herring,
Frank Rowand, Mark Rutland, Peter Ujfalusi, Russell King,
linux-devicetree, David Airlie, LKML, linux-drm, Tomi Valkeinen,
Jyri Sarha, arm-soc, Laurent Pinchart
In-Reply-To: <m2bmx5x1y2.fsf-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On 11/23/2016 04:32 PM, Kevin Hilman wrote:
> David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org> writes:
>
>> On 11/23/2016 04:27 AM, Bartosz Golaszewski wrote:
>>> 2016-11-22 23:23 GMT+01:00 David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>:
>>>> On 11/15/2016 05:00 AM, Bartosz Golaszewski wrote:
>>>>>
>>>>> Add the nodes for the MSTPRI configuration and DDR2/mDDR memory
>>>>> controller drivers to da850.dtsi.
>>>>>
>>>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>>>>> ---
>>>>> v1 -> v2:
>>>>> - moved the priority controller node above the cfgchip node
>>>>> - renamed added nodes to better reflect their purpose
>>>>>
>>>>> arch/arm/boot/dts/da850.dtsi | 8 ++++++++
>>>>> 1 file changed, 8 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>>>>> index 1bb1f6d..412eec6 100644
>>>>> --- a/arch/arm/boot/dts/da850.dtsi
>>>>> +++ b/arch/arm/boot/dts/da850.dtsi
>>>>> @@ -210,6 +210,10 @@
>>>>> };
>>>>>
>>>>> };
>>>>> + prictrl: priority-controller@14110 {
>>>>> + compatible = "ti,da850-mstpri";
>>>>> + reg = <0x14110 0x0c>;
>>>>
>>>>
>>>> I think we should add status = "disabled"; here and let boards opt in.
>>>>
>>>>> + };
>>>>> cfgchip: chip-controller@1417c {
>>>>> compatible = "ti,da830-cfgchip", "syscon",
>>>>> "simple-mfd";
>>>>> reg = <0x1417c 0x14>;
>>>>> @@ -451,4 +455,8 @@
>>>>> 1 0 0x68000000 0x00008000>;
>>>>> status = "disabled";
>>>>> };
>>>>> + memctrl: memory-controller@b0000000 {
>>>>> + compatible = "ti,da850-ddr-controller";
>>>>> + reg = <0xb0000000 0xe8>;
>>>>
>>>>
>>>> same here. status = "disabled";
>>>>
>>>>> + };
>>>>> };
>>>>>
>>>
>>> Hi David,
>>>
>>> I did that initially[1][2] and it was rejected by Kevin[3] and Laurent[4].
>>>
>>> FYI this patch has already been queued by Sekhar.
>>
>> Thanks. I did not see those threads.
>>
>> FYI to maintainers, having these enabled by default causes error
>> messages in the kernel log for other boards that are not supported by
>> the drivers.
>
> Then the driver is too noisy and should be cleaned up.
>
>> Since there is only one board that is supported and soon
>> to be 2 that are not, I would rather have this disabled by default to
>> avoid the error messages.
>
> IMO, what exactly are the error messages? Sounds like the driver is
> being too verbose, and calling things errors that are not really errors.
It is just one line per driver.
dev_err(dev, "no master priorities defined for this board\n");
and
dev_err(dev, "no settings defined for this board\n");
Since "ti,da850-lcdk" is the only board supported in these drivers, all
other boards will see these error messages.
Also, these modules will be loaded and taking up memory on boards that
don't use them. This not really a big deal and they can be explicitly
disabled, so maybe it was not worth mentioning.
>
> Kevin
>
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^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: tomas.hlavacek @ 2016-11-23 22:45 UTC (permalink / raw)
To: Andrew Lunn
Cc: Mark Rutland, marex, Jason Cooper, Uwe Kleine-König,
devicetree, Rob Herring, Gregory Clement, linux-arm-kernel,
Sebastian Hesselbarth
In-Reply-To: <20161123145916.GL14947@lunn.ch>
Hi Andrew!
On Wed, Nov 23, 2016 at 3:59 PM, Andrew Lunn <andrew@lunn.ch> wrote:
>> >CZ11NIC12 is indicated on my board.
>>
>> :-( Well, this board version has wrongly matched length of some
>> differential pairs, IRQ from 88E1514 is connected differently, there
>> are slight differences in power supplies and (if I am not mistaken)
>> something changed in RTC support circuitry. It looks like a huge
>> mistake on our side.
>
> Hi Tomas
>
> Would these problems also explain why the Ethernet links to the switch
> don't work? Maybe the differential pairs?
I do not think so. The ethernet links to the switch are RGMII, not
differential pairs. Differential pair is used only for the eth2 to link
either SFP+ or 88E1514 (via a high-speed switch that selects one or
another). So the problems with differential pairs affect only WAN
interface.
>
>
>> It seems that libphy is probed before pca9538 and we end up with:
>> [ 4.217550] libphy: orion_mdio_bus: probed
>> [ 4.221777] irq: no irq domain found for
>> /soc/internal-regs/i2c@11000/i2cmux@70/i2c@7/gpio@71 !
>>
>> Any clue where to look in order to defer probing libphy or at least
>> orion_mdio_bus?
>
> I think there is a known phylib problem here. Somewhere in the call
> chain there is a void function, so the EPROBE_DEFFER gets
> discarded. But i could be remembering this wrongly.
Oh yes, I thought that and I tried to find exactly this type of problem
yesterday, but I didn't succeed. But I think that we agreed that we are
going to stick with PHY polling rather then experimenting with
unreliable IRQ over the GPIO expander, so we can leave this unresolved.
I will look into the I2C mux concerns, fix the remaining comments
regarding my version and test RTC more extensively - Uwe's board is
still not ticking, mine does, so we have to rule out that it is a
common problem.
Tomas
^ permalink raw reply
* Re: [PATCH 3/3] ARM: dts: da850: Add node for pullup/pulldown pinconf
From: Kevin Hilman @ 2016-11-23 22:33 UTC (permalink / raw)
To: David Lechner
Cc: Sekhar Nori, Linus Walleij, Rob Herring, Mark Rutland, linux-gpio,
devicetree, linux-kernel, linux-arm-kernel, Axel Haslam,
Alexandre Bailon, Bartosz Gołaszewski
In-Reply-To: <06bc8517-8c33-85a1-9d5a-29042c7281db@lechnology.com>
David Lechner <david@lechnology.com> writes:
> On 11/23/2016 05:12 AM, Sekhar Nori wrote:
>> On Wednesday 23 November 2016 08:59 AM, David Lechner wrote:
>>> This SoC has a separate pin controller for configuring pullup/pulldown
>>> bias on groups of pins.
>>>
>>> Signed-off-by: David Lechner <david@lechnology.com>
>>> ---
>>> arch/arm/boot/dts/da850.dtsi | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>>> index 8945815..1c0224c 100644
>>> --- a/arch/arm/boot/dts/da850.dtsi
>>> +++ b/arch/arm/boot/dts/da850.dtsi
>>> @@ -210,6 +210,11 @@
>>> };
>>>
>>> };
>>> + pinconf: pin-controller@22c00c {
>>> + compatible = "ti,da850-pupd";
>>> + reg = <0x22c00c 0x8>;
>>> + status = "disabled";
>>> + };
>>
>> Can you please place this below the i2c1 node. I am trying to keep the
>> nodes sorted by unit address. I know thats broken in many places today,
>> but lets add the new ones where they should eventually end up.
>
> I can do this, but it seems that the predominant sorting pattern here
> is to keep subsystems together (e.g. all i2c are together, all uart
> are together, etc.)
>
> Would a separate patch to sort everything by unit address to get this
> cleaned up be acceptable?
No thanks. That kind of thing is the needless churn that gets us flamed.
Kevin
^ permalink raw reply
* Re: [PATCH v2] ARM: dts: da850: add the mstpri and ddrctl nodes
From: Kevin Hilman @ 2016-11-23 22:32 UTC (permalink / raw)
To: David Lechner
Cc: Mark Rutland, linux-devicetree, Tomi Valkeinen, Michael Turquette,
Sekhar Nori, Russell King, linux-drm, LKML, Peter Ujfalusi,
Bartosz Golaszewski, Rob Herring, Jyri Sarha, Frank Rowand,
arm-soc, Laurent Pinchart
In-Reply-To: <5e647eb0-2f8a-b46b-2048-7616bfb54ad7@lechnology.com>
David Lechner <david@lechnology.com> writes:
> On 11/23/2016 04:27 AM, Bartosz Golaszewski wrote:
>> 2016-11-22 23:23 GMT+01:00 David Lechner <david@lechnology.com>:
>>> On 11/15/2016 05:00 AM, Bartosz Golaszewski wrote:
>>>>
>>>> Add the nodes for the MSTPRI configuration and DDR2/mDDR memory
>>>> controller drivers to da850.dtsi.
>>>>
>>>> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
>>>> ---
>>>> v1 -> v2:
>>>> - moved the priority controller node above the cfgchip node
>>>> - renamed added nodes to better reflect their purpose
>>>>
>>>> arch/arm/boot/dts/da850.dtsi | 8 ++++++++
>>>> 1 file changed, 8 insertions(+)
>>>>
>>>> diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
>>>> index 1bb1f6d..412eec6 100644
>>>> --- a/arch/arm/boot/dts/da850.dtsi
>>>> +++ b/arch/arm/boot/dts/da850.dtsi
>>>> @@ -210,6 +210,10 @@
>>>> };
>>>>
>>>> };
>>>> + prictrl: priority-controller@14110 {
>>>> + compatible = "ti,da850-mstpri";
>>>> + reg = <0x14110 0x0c>;
>>>
>>>
>>> I think we should add status = "disabled"; here and let boards opt in.
>>>
>>>> + };
>>>> cfgchip: chip-controller@1417c {
>>>> compatible = "ti,da830-cfgchip", "syscon",
>>>> "simple-mfd";
>>>> reg = <0x1417c 0x14>;
>>>> @@ -451,4 +455,8 @@
>>>> 1 0 0x68000000 0x00008000>;
>>>> status = "disabled";
>>>> };
>>>> + memctrl: memory-controller@b0000000 {
>>>> + compatible = "ti,da850-ddr-controller";
>>>> + reg = <0xb0000000 0xe8>;
>>>
>>>
>>> same here. status = "disabled";
>>>
>>>> + };
>>>> };
>>>>
>>
>> Hi David,
>>
>> I did that initially[1][2] and it was rejected by Kevin[3] and Laurent[4].
>>
>> FYI this patch has already been queued by Sekhar.
>
> Thanks. I did not see those threads.
>
> FYI to maintainers, having these enabled by default causes error
> messages in the kernel log for other boards that are not supported by
> the drivers.
Then the driver is too noisy and should be cleaned up.
> Since there is only one board that is supported and soon
> to be 2 that are not, I would rather have this disabled by default to
> avoid the error messages.
IMO, what exactly are the error messages? Sounds like the driver is
being too verbose, and calling things errors that are not really errors.
Kevin
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^ permalink raw reply
* Re: [PATCH v2 2/3] drm/bridge: Add ti-tfp410 DVI transmitter driver
From: Rob Herring @ 2016-11-23 22:30 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Jyri Sarha, dri-devel,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, David Airlie,
Daniel Vetter, Tomi Valkeinen, Rob Clark, Bartosz Golaszewski,
Kevin Hilman, Benoit Cousson
In-Reply-To: <1829466.vPTafcVR8L@avalon>
On Thu, Nov 17, 2016 at 3:45 AM, Laurent Pinchart
<laurent.pinchart-ryLnwIuWjnjg/C1BVhZhaw@public.gmane.org> wrote:
> Hi Jyri,
>
> On Wednesday 16 Nov 2016 16:39:28 Jyri Sarha wrote:
>> On 11/16/16 15:33, Rob Herring wrote:
>> >> +Optional properties
>> >>
>> >>> + - reg: I2C address. If and only if present the driver node
>
> I assume you meant device node, not driver node ?
>
>> >>> + should be placed into the i2c controller node where the
>> >>> + tfp410 i2c is connected to (the current implementation does
>> >>> + not yet support this).
>> >
>> > So this chip can work without programming I guess?
>>
>> Yes. Just powering it up is enough for most application.
>>
>> > reg should only be not present if I2C is not connected in the design. It
>> > can't be a function of what the driver supports. In otherwords, you
>> > can't be moving this node around based on when you add I2C control.
>>
>> Ok, I'll try to implement a dummy i2c driver at the same time too. I can
>> not test anything related to it because I do not have a piece of HW with
>> tfp410 i2c wires connected, but it should not matter as long as I am
>> able to probe it as a i2c client.
>
> I think that Rob's point was that whether the current implementation supports
> this or not is irrelevant from a DT bindings point of view. It should not be
> mentioned in the bindings document.
Right. Now, whether the h/w has I2C wires connected or not is relevant
to the binding doc. So the doc just needs some rewording, a dummy
driver isn't needed.
Rob
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^ permalink raw reply
* Re: [PATCH 1/2] PM / Domains: Introduce domain-performance-state binding
From: Kevin Hilman @ 2016-11-23 22:30 UTC (permalink / raw)
To: Vincent Guittot
Cc: Viresh Kumar, Rob Herring, Rafael Wysocki,
linaro-kernel@lists.linaro.org, linux-pm@vger.kernel.org,
linux-kernel, Mark Rutland, Ulf Hansson, Lina Iyer,
devicetree@vger.kernel.org, Stephen Boyd, Nayak Rajendra
In-Reply-To: <CAKfTPtBMro7+UruF0-E26TJPu6pEAvkjF9V7SKriNBm5q+K9+A@mail.gmail.com>
Vincent Guittot <vincent.guittot@linaro.org> writes:
> On 23 November 2016 at 16:51, Kevin Hilman <khilman@baylibre.com> wrote:
>> Vincent Guittot <vincent.guittot@linaro.org> writes:
>>
>>> On 22 November 2016 at 19:12, Kevin Hilman <khilman@baylibre.com> wrote:
>>>> Viresh Kumar <viresh.kumar@linaro.org> writes:
>>>>
>>>>> On 21-11-16, 09:07, Rob Herring wrote:
>>>>>> On Fri, Nov 18, 2016 at 02:53:12PM +0530, Viresh Kumar wrote:
>>>>>> > Some platforms have the capability to configure the performance state of
>>>>>> > their Power Domains. The performance levels are represented by positive
>>>>>> > integer values, a lower value represents lower performance state.
>>>>>> >
>>>>>> > The power-domains until now were only concentrating on the idle state
>>>>>> > management of the device and this needs to change in order to reuse the
>>>>>> > infrastructure of power domains for active state management.
>>>>>> >
>>>>>> > This patch introduces a new optional property for the consumers of the
>>>>>> > power-domains: domain-performance-state.
>>>>>> >
>>>>>> > If the consumers don't need the capability of switching to different
>>>>>> > domain performance states at runtime, then they can simply define their
>>>>>> > required domain performance state in their node directly. Otherwise the
>>>>>> > consumers can define their requirements with help of other
>>>>>> > infrastructure, for example the OPP table.
>>>>>> >
>>>>>> > Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
>>>>>> > ---
>>>>>> > Documentation/devicetree/bindings/power/power_domain.txt | 6 ++++++
>>>>>> > 1 file changed, 6 insertions(+)
>>>>>> >
>>>>>> > diff --git a/Documentation/devicetree/bindings/power/power_domain.txt b/Documentation/devicetree/bindings/power/power_domain.txt
>>>>>> > index e1650364b296..db42eacf8b5c 100644
>>>>>> > --- a/Documentation/devicetree/bindings/power/power_domain.txt
>>>>>> > +++ b/Documentation/devicetree/bindings/power/power_domain.txt
>>>>>> > @@ -106,6 +106,12 @@ domain provided by the 'parent' power controller.
>>>>>> > - power-domains : A phandle and PM domain specifier as defined by bindings of
>>>>>> > the power controller specified by phandle.
>>>>>> >
>>>>>> > +Optional properties:
>>>>>> > +- domain-performance-state: A positive integer value representing the minimum
>>>>>> > + performance level (of the parent domain) required by the consumer for its
>>>>>> > + working. The integer value '1' represents the lowest performance level and the
>>>>>> > + highest value represents the highest performance level.
>>>>>>
>>>>>> How does one come up with the range of values?
>>>>>
>>>>> Why would we need a range here? The value here represents the minimum 'state'
>>>>> and the assumption is that everything above that level would be fine. So the
>>>>> range is automatically: domain-performance-state -> MAX.
>>>>>
>>>>>> It seems like you are
>>>>>> just making up numbers. Couldn't the domain performance level be an OPP
>>>>>> in the sense that it is a collection of clock frequencies and voltage
>>>>>> settings?
>>>>>
>>>>> The clock is going to be handled by the device itself (at least for the case we
>>>>> have today) and the performance-state lies with the power-domain which is
>>>>> configured separately. If the performance level includes both clk and voltage,
>>>>> then why would we need to show the clock rates in the DT ? Wouldn't a
>>>>> performance level be enough in such cases?
>>>>
>>>> I think the question is: what does the performance-level of a domain
>>>> actually mean? Or, what are the units?
>>>>
>>>> Depending on the SoC, there's probably a few things this could mean. It
>>>> might mean is that an underlying bus/interconnect can be configured to
>>>> guarantee a specific bandwidth or throughput. That in turn might mean
>>>> that that bus/interconnect might have to be set at a specific
>>>> frequency/voltage.
>>>>
>>>> In your case, IIUC, you're just passing some magic value to some
>>>> firmware running on a micro-controller, but under the hood that uC is
>>>> probably configuring a frequency/voltage someplace.
>>>
>>> In the case described by Viresh, it's only about setting the voltage
>>> of a power domain that is shared between different devices. these
>>> devices wants to run at different frequency (set by the devices) but
>>> we have to select a Volateg value that will match with the constraint
>>> of all devices (in this case the highest voltage)
>>
>> Then, at least for this use case, we're talking about voltage, not some
>> unspecified units.
>>
>> But that makes me wonder, this performance state sounds like something
>> that is changing dynamically at runtime, so why do you want to describe
>> this statically in DT?
>>
>> This sounds to me like the job of the genpd. When any device in the
>> domain does its pm_runtime_get(), the domain could check the device
>> frequency and see if it needs to change the domain voltage in order for
>> that device to operate at that frequency. When the device goes away
>> (using pm_runtime_put()) the domain can check again if it could lower
>> the voltage and still meet the requirements of the remaining devices.
>
> That's only part of the job. The device can change its frequency and
> as a result ask for a new voltage index while it is already running
That's fine. Use clock notifiers, or better use QoS (with notifiers) so
that the genpd knows when any of those change.
Kevin
^ permalink raw reply
* Re: [PATCH] of: Fix issue where code would fall through to error case.
From: Rob Herring @ 2016-11-23 21:58 UTC (permalink / raw)
To: Moritz Fischer
Cc: Frank Rowand, Moritz Fischer, linux-kernel@vger.kernel.org,
Pantelis Antoniou, moritz, devicetree@vger.kernel.org
In-Reply-To: <CAJYdmeNnKtecshe3QSZCPnwEuNUFAW9cUsNS-Z1Chw7OPUJ2jQ@mail.gmail.com>
On Thu, Nov 17, 2016 at 6:10 PM, Moritz Fischer
<moritz.fischer.private@gmail.com> wrote:
> On Thu, Nov 17, 2016 at 4:02 PM, Frank Rowand <frowand.list@gmail.com> wrote:
>> On 11/17/16 15:40, Frank Rowand wrote:
>>> On 11/17/16 15:25, Moritz Fischer wrote:
>>>> No longer fall through into the error case that prints out
>>>> an error if no error (err = 0) occurred.
>>>>
>>>> Fixes d9181b20a83(of: Add back an error message, restructured)
>>>> Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
>>>> ---
>>>> drivers/of/resolver.c | 6 +++++-
>>>> 1 file changed, 5 insertions(+), 1 deletion(-)
>>>>
>>>> diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
>>>> index 783bd09..785076d 100644
>>>> --- a/drivers/of/resolver.c
>>>> +++ b/drivers/of/resolver.c
>>>> @@ -358,9 +358,13 @@ int of_resolve_phandles(struct device_node *overlay)
>>>>
>>>> err = update_usages_of_a_phandle_reference(overlay, prop, phandle);
>>>> if (err)
>>>> - break;
>>>> + goto err_out;
>>>> }
>>>>
>>>> + of_node_put(tree_symbols);
>>>> +
>>>> + return 0;
>>>> +
>>>> err_out:
>>>> pr_err("overlay phandle fixup failed: %d\n", err);
>>>> out:
>>>
>>> Thanks for catching that.
>>>
>>> Rob, please apply.
>>>
>>> Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
>>>
>>> -Frank
>>
>> On second thought, isn't the common pattern when clean up is needed for
>> both the no-error path and the error path something like:
>>
>>
>> out:
>> of_node_put(tree_symbols);
>> return err;
>>
>> err_out:
>> pr_err("overlay phandle fixup failed: %d\n", err);
>> goto out;
>> }
>>
>>
>> I don't have a strong opinion, whatever Rob wants to take is fine with me.
>
> Same here. I tried to avoid the jumping back part, but if that's the
> common pattern,
> I can submit a v2 doing that instead.
Both are ugly. Just do:
if (err)
pr_err(...);
Rob
^ permalink raw reply
* Re: [PATCH] drivers/of: Export phandle iterators
From: Rob Herring @ 2016-11-23 21:49 UTC (permalink / raw)
To: Robin Murphy
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Frank Rowand
In-Reply-To: <a1fa1157cab10f2a6f319d431d355cef79b91820.1479927866.git.robin.murphy-5wv7dgnIgG8@public.gmane.org>
On Wed, Nov 23, 2016 at 1:06 PM, Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org> wrote:
> Modular drivers may want to use of_for_each_phandle() - export its
> constituent functions.
Do you have a user?
Rob
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^ permalink raw reply
* Re: [PATCH] ALSA SoC MAX98927 driver - Initial release
From: Michael Trimarchi @ 2016-11-23 19:20 UTC (permalink / raw)
To: Ryan Lee
Cc: Liam Girdwood, Mark Brown, Rob Herring, Mark Rutland,
Jaroslav Kysela, Takashi Iwai, Arnd Bergmann, Oder Chiou,
yesanishhere-Re5JQEeQqe8AvxtiuMwx3w, Jacob Siverskog,
Damien.Horsley-1AXoQHu6uovQT0dZR+AlfA, Bard Liao,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
petr-Qh/3xLP0EvwAvxtiuMwx3w, Lars-Peter Clausen, nh6z-fFIq/eER6g8,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, LKML
In-Reply-To: <1479877026-5172-1-git-send-email-RyanS.Lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
Hi
On Wed, Nov 23, 2016 at 5:57 AM, Ryan Lee <RyanS.Lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org> wrote:
> Signed-off-by: Ryan Lee <ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
> ---
> .../devicetree/bindings/sound/max98927.txt | 32 +
> sound/soc/codecs/Kconfig | 5 +
> sound/soc/codecs/Makefile | 2 +
> sound/soc/codecs/max98927.c | 954 +++++++++++++++
> sound/soc/codecs/max98927.h | 1253 ++++++++++++++++++++
> 5 files changed, 2246 insertions(+)
> create mode 100755 Documentation/devicetree/bindings/sound/max98927.txt
> mode change 100644 => 100755 sound/soc/codecs/Kconfig
> mode change 100644 => 100755 sound/soc/codecs/Makefile
> create mode 100755 sound/soc/codecs/max98927.c
> create mode 100755 sound/soc/codecs/max98927.h
>
> diff --git a/Documentation/devicetree/bindings/sound/max98927.txt b/Documentation/devicetree/bindings/sound/max98927.txt
> new file mode 100755
> index 0000000..ddcd332
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/sound/max98927.txt
> @@ -0,0 +1,32 @@
> +max98927 audio CODEC
> +
> +This device supports I2C.
> +
> +Required properties:
> +
> + - compatible : "maxim,max98927"
> +
> + - vmon-slot-no : slot number used to send voltage information
> + or in inteleave mode this will be used as
> + interleave slot.
> +
> + - imon-slot-no : slot number used to send current information
> +
> + - interleave-mode : When using two MAX98927 in a system it is
> + possible to create ADC data that that will
> + overflow the frame size. Digital Audio Interleave
> + mode provides a means to output VMON and IMON data
> + from two devices on a single DOUT line when running
> + smaller frames sizes such as 32 BCLKS per LRCLK or
> + 48 BCLKS per LRCLK.
> +
> + - reg : the I2C address of the device for I2C
> +
> +Example:
> +
> +codec: max98927@3a {
> + compatible = "maxim,max98927";
> + vmon-slot-no = <1>;
> + imon-slot-no = <0>;
> + reg = <0x3a>;
> +};
> diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig
> old mode 100644
> new mode 100755
> index c67667b..45f21ca
> --- a/sound/soc/codecs/Kconfig
> +++ b/sound/soc/codecs/Kconfig
> @@ -86,6 +86,7 @@ config SND_SOC_ALL_CODECS
> select SND_SOC_MAX9867 if I2C
> select SND_SOC_MAX98925 if I2C
> select SND_SOC_MAX98926 if I2C
> + select SND_SOC_MAX98927 if I2C
> select SND_SOC_MAX9850 if I2C
> select SND_SOC_MAX9860 if I2C
> select SND_SOC_MAX9768 if I2C
> @@ -573,6 +574,10 @@ config SND_SOC_MAX98925
> config SND_SOC_MAX98926
> tristate
>
> +config SND_SOC_MAX98927
> + tristate "Maxim Integrated MAX98927 Speaker Amplifier"
> + depends on I2C
> +
> config SND_SOC_MAX9850
> tristate
>
> diff --git a/sound/soc/codecs/Makefile b/sound/soc/codecs/Makefile
> old mode 100644
> new mode 100755
> index 958cd49..1f5fe2c
> --- a/sound/soc/codecs/Makefile
> +++ b/sound/soc/codecs/Makefile
> @@ -82,6 +82,7 @@ snd-soc-max98371-objs := max98371.o
> snd-soc-max9867-objs := max9867.o
> snd-soc-max98925-objs := max98925.o
> snd-soc-max98926-objs := max98926.o
> +snd-soc-max98927-objs := max98927.o
> snd-soc-max9850-objs := max9850.o
> snd-soc-max9860-objs := max9860.o
> snd-soc-mc13783-objs := mc13783.o
> @@ -306,6 +307,7 @@ obj-$(CONFIG_SND_SOC_MAX98357A) += snd-soc-max98357a.o
> obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
> obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
> obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
> +obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o
> obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
> obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
> obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o
> diff --git a/sound/soc/codecs/max98927.c b/sound/soc/codecs/max98927.c
> new file mode 100755
> index 0000000..d85c84f
> --- /dev/null
> +++ b/sound/soc/codecs/max98927.c
> @@ -0,0 +1,954 @@
> +/*
> + * max98927.c -- MAX98927 ALSA Soc Audio driver
> + *
> + * Copyright 2013-15 Maxim Integrated Products
> + * Author: Ryan Lee <ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/slab.h>
> +#include <linux/cdev.h>
> +#include <sound/pcm.h>
> +#include <sound/pcm_params.h>
> +#include <sound/soc.h>
> +#include <linux/gpio.h>
> +#include <linux/of_gpio.h>
> +#include <sound/tlv.h>
> +#include "max98927.h"
> +
> +static struct reg_default max98927_reg_map[] = {
> + {0x0014, 0x78},
> + {0x0015, 0xFF},
> + {0x0043, 0x04},
> + {0x0017, 0x55},
> + /* For mono driver we are just enabling one channel*/
> + {MAX98927_PCM_Rx_Enables_A, 0x03},
> + {MAX98927_PCM_Tx_HiZ_Control_A, 0xfc},
> + {MAX98927_PCM_Tx_HiZ_Control_B, 0xff},
> + {MAX98927_PCM_Tx_Channel_Sources_A, 0x01},
> + {MAX98927_PCM_Tx_Channel_Sources_B, 0x01},
> + {MAX98927_Measurement_DSP_Config, 0xf7},
What about not use camel case
> + {0x0025, 0x80},
> + {0x0026, 0x01},
> + {0x0035, 0x40},
> + {0x0036, 0x40},
> + {0x0037, 0x02},
> + {0x0039, 0x01},
> + {0x003c, 0x44},
> + {0x003d, 0x04},
> + {0x0040, 0x10},
> + {0x0042, 0x3f},
> + {0x0044, 0x00},
> + {0x0045, 0x24},
> + {0x007f, 0x06},
> + {0x0087, 0x1c},
> + {0x0089, 0x03},
> + {0x009f, 0x01},
> +};
> +
> +void max98927_wrapper_write(struct max98927_priv *max98927,
> + unsigned int reg, unsigned int val)
> +{
> + if (max98927->regmap)
> + regmap_write(max98927->regmap, reg, val);
> + if (max98927->sub_regmap)
> + regmap_write(max98927->sub_regmap, reg, val);
> +}
> +
> +void max98927_wrap_update_bits(struct max98927_priv *max98927,
> + unsigned int reg, unsigned int mask, unsigned int val)
> +{
> + if (max98927->regmap)
> + regmap_update_bits(max98927->regmap, reg, mask, val);
> + if (max98927->sub_regmap)
> + regmap_update_bits(max98927->sub_regmap, reg, mask, val);
> +}
> +
> +static int max98927_reg_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol, unsigned int reg,
> + unsigned int mask, unsigned int shift)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + int data;
> +
> + regmap_read(max98927->regmap, reg, &data);
> + ucontrol->value.integer.value[0] =
> + (data & mask) >> shift;
> + return 0;
> +}
> +
> +static int max98927_reg_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol, unsigned int reg,
> + unsigned int mask, unsigned int shift)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + unsigned int sel = ucontrol->value.integer.value[0];
> +
> + max98927_wrap_update_bits(max98927, reg, mask, sel << shift);
> + dev_dbg(codec->dev, "%s: register 0x%02X, value 0x%02X\n",
> + __func__, reg, sel);
> + return 0;
> +}
> +
> +static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai,
> + unsigned int fmt)
> +{
> + struct snd_soc_codec *codec = codec_dai->codec;
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + unsigned int invert = 0;
> +
> + dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
> + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> + case SND_SOC_DAIFMT_CBS_CFS:
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_SLAVE);
> + break;
> + case SND_SOC_DAIFMT_CBM_CFM:
> + max98927->master = true;
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_MASTER);
> + break;
> + case SND_SOC_DAIFMT_CBS_CFM:
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_HYBRID);
> + default:
> + dev_err(codec->dev, "DAI clock mode unsupported");
> + return -EINVAL;
> + }
Please fill up the mask variable and apply in one round after the switch.
> +
> + switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
> + case SND_SOC_DAIFMT_NB_NF:
> + break;
> + case SND_SOC_DAIFMT_IB_NF:
> + invert = MAX98927_PCM_Mode_Config_PCM_BCLKEDGE;
> + break;
> + default:
> + dev_err(codec->dev, "DAI invert mode unsupported");
> + return -EINVAL;
> + }
> +
> + /* interface format */
> + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> + case SND_SOC_DAIFMT_I2S:
> + max98927->iface |= SND_SOC_DAIFMT_I2S;
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Mode_Config,
> + max98927->iface, max98927->iface);
> + break;
> + case SND_SOC_DAIFMT_LEFT_J:
> + max98927->iface |= SND_SOC_DAIFMT_LEFT_J;
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Mode_Config,
> + max98927->iface, max98927->iface);
> + break;
> + default:
> + return -EINVAL;
> + }
> +
Same here
> + /* pcm channel configuration */
> + if (max98927->iface & (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_LEFT_J)) {
> + max98927_wrapper_write(max98927,
> + MAX98927_PCM_Rx_Enables_A,
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH0_EN|
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH1_EN);
> + max98927_wrapper_write(max98927,
> + MAX98927_PCM_Tx_Enables_A,
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH0_EN|
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH1_EN);
> + }
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Mode_Config,
> + MAX98927_PCM_Mode_Config_PCM_BCLKEDGE, invert);
> + return 0;
> +}
> +
> +/* codec MCLK rate in master mode */
> +static const int rate_table[] = {
> + 5644800, 6000000, 6144000, 6500000,
> + 9600000, 11289600, 12000000, 12288000,
> + 13000000, 19200000,
> +};
> +
> +static int max98927_set_clock(struct max98927_priv *max98927,
> + struct snd_pcm_hw_params *params)
> +{
> + /* BCLK/LRCLK ratio calculation */
> + int blr_clk_ratio = params_channels(params) * max98927->ch_size;
> + int reg = MAX98927_PCM_Clock_setup;
> + int mask = MAX98927_PCM_Clock_setup_PCM_BSEL_Mask;
> + int value;
> +
> + if (max98927->master) {
> + int i;
> + /* match rate to closest value */
> + for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
> + if (rate_table[i] >= max98927->sysclk)
> + break;
> + }
> + if (i == ARRAY_SIZE(rate_table)) {
> + pr_err("%s couldn't get the MCLK to match codec\n",
> + __func__);
> + return -EINVAL;
> + }
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Master_Mode,
> + MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_Mask,
> + i << MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_SHIFT);
> + }
some code style here
> +
> + switch (blr_clk_ratio) {
> + case 32:
> + value = 2;
> + break;
> + case 48:
> + value = 3;
> + break;
> + case 64:
> + value = 4;
> + break;
> + default:
> + return -EINVAL;
> + }
> + max98927_wrap_update_bits(max98927,
> + reg, mask, value);
> + return 0;
> +}
> +
ditto
> +static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_codec *codec = dai->codec;
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + int sampling_rate = 0;
> +
> + /* pcm mode configuration */
> + switch (snd_pcm_format_width(params_format(params))) {
> + case 16:
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Mode_Config,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_16,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_16);
> + max98927->ch_size = 16;
> + break;
> + case 24:
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Mode_Config,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_24,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_24);
> + max98927->ch_size = 24;
> + break;
> + case 32:
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Mode_Config,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_32,
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_32);
> + max98927->ch_size = 32;
> + break;
> + default:
> + pr_err("%s: format unsupported %d",
> + __func__, params_format(params));
> + goto err;
> + }
Move update bits after switch. Can you update a new version?
Michael
> + dev_dbg(codec->dev, "%s: format supported %d",
> + __func__, params_format(params));
> +
> + /* sampling rate configuration */
> + switch (params_rate(params)) {
> + case 8000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_8000;
> + break;
> + case 11025:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_11025;
> + break;
> + case 12000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_12000;
> + break;
> + case 16000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_16000;
> + break;
> + case 22050:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_22050;
> + break;
> + case 24000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_24000;
> + break;
> + case 32000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_32000;
> + break;
> + case 44100:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_44100;
> + break;
> + case 48000:
> + sampling_rate |=
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_48000;
> + break;
> + default:
> + pr_err("%s rate %d not supported\n",
> + __func__, params_rate(params));
> + goto err;
> + }
> + /* set DAI_SR to correct LRCLK frequency */
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_1,
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_Mask, sampling_rate);
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_2,
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_Mask, sampling_rate<<4);
> + max98927_wrap_update_bits(max98927, MAX98927_PCM_Sample_rate_setup_2,
> + MAX98927_PCM_Sample_rate_setup_2_IVADC_SR_Mask, sampling_rate);
> + return max98927_set_clock(max98927, params);
> +err:
> + return -EINVAL;
> +}
> +
> +#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
> +
> +#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
> + SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
> +
> +static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
> + int clk_id, unsigned int freq, int dir)
> +{
> + struct snd_soc_codec *codec = dai->codec;
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> +
> + max98927->sysclk = freq;
> + return 0;
> +}
> +
> +static const struct snd_soc_dai_ops max98927_dai_ops = {
> + .set_sysclk = max98927_dai_set_sysclk,
> + .set_fmt = max98927_dai_set_fmt,
> + .hw_params = max98927_dai_hw_params,
> +};
> +
> +static void max98927_handle_pdata(struct snd_soc_codec *codec)
> +{
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + struct max98927_reg_default *regInfo;
> + int cfg_size = 0;
> + int x;
> +
> + if (max98927->regcfg != NULL)
> + cfg_size = max98927->regcfg_sz / sizeof(uint32_t);
> +
> + if (cfg_size <= 0) {
> + dev_dbg(codec->dev,
> + "Register configuration is not required.\n");
> + return;
> + }
> +
> + /* direct configuration from device tree */
> + for (x = 0; x < cfg_size; x += 3) {
> + regInfo = (struct max98927_reg_default *)&max98927->regcfg[x];
> + dev_info(codec->dev, "CH:%d, reg:0x%02x, value:0x%02x\n",
> + be32_to_cpu(regInfo->ch),
> + be32_to_cpu(regInfo->reg),
> + be32_to_cpu(regInfo->def));
> + if (be32_to_cpu(regInfo->ch) == PRI_MAX98927
> + && max98927->regmap)
> + regmap_write(max98927->regmap,
> + be32_to_cpu(regInfo->reg),
> + be32_to_cpu(regInfo->def));
> + else if (be32_to_cpu(regInfo->ch) == SEC_MAX98927
> + && max98927->sub_regmap)
> + regmap_write(max98927->sub_regmap,
> + be32_to_cpu(regInfo->reg),
> + be32_to_cpu(regInfo->def));
> + }
> +}
> +
> +static int max98927_dac_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol, int event)
> +{
> + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> +
> + switch (event) {
> + case SND_SOC_DAPM_POST_PMU:
> + max98927_wrap_update_bits(max98927,
> + MAX98927_AMP_enables, 1, 1);
> + /* enable the v and i for vi feedback */
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Measurement_enables,
> + MAX98927_Measurement_enables_IVADC_V_EN,
> + MAX98927_Measurement_enables_IVADC_V_EN);
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Measurement_enables,
> + MAX98927_Measurement_enables_IVADC_I_EN,
> + MAX98927_Measurement_enables_IVADC_I_EN);
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Global_Enable, 1, 1);
> + break;
> + case SND_SOC_DAPM_POST_PMD:
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Global_Enable, 1, 0);
> + max98927_wrap_update_bits(max98927,
> + MAX98927_AMP_enables, 1, 0);
> + /* disable the v and i for vi feedback */
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Measurement_enables,
> + MAX98927_Measurement_enables_IVADC_V_EN,
> + 0);
> + max98927_wrap_update_bits(max98927,
> + MAX98927_Measurement_enables,
> + MAX98927_Measurement_enables_IVADC_I_EN,
> + 0);
> + break;
> + default:
> + return 0;
> + }
> + return 0;
> +}
> +
> +static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
> + SND_SOC_DAPM_AIF_IN("DAI_OUT", "HiFi Playback", 0, SND_SOC_NOPM, 0, 0),
> + SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_AMP_enables,
> + 0, 0, max98927_dac_event,
> + SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
> + SND_SOC_DAPM_OUTPUT("BE_OUT"),
> +};
> +
> +static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
> +static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
> +
> +static int max98927_spk_gain_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> +
> + ucontrol->value.integer.value[0] = max98927->spk_gain;
> + dev_dbg(codec->dev, "%s: spk_gain setting returned %d\n", __func__,
> + (int) ucontrol->value.integer.value[0]);
> + return 0;
> +}
> +
> +static int max98927_spk_gain_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + unsigned int sel = ucontrol->value.integer.value[0];
> +
> + if (sel < ((1 << MAX98927_Speaker_Gain_Width) - 1)) {
> + max98927_wrap_update_bits(max98927, MAX98927_Speaker_Gain,
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_Mask, sel);
> + max98927->spk_gain = sel;
> + }
> + return 0;
> +}
> +
> +static int max98927_digital_gain_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> +
> + ucontrol->value.integer.value[0] = max98927->digital_gain;
> + dev_dbg(codec->dev, "%s: spk_gain setting returned %d\n", __func__,
> + (int) ucontrol->value.integer.value[0]);
> + return 0;
> +}
> +
> +static int max98927_digital_gain_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + unsigned int sel = ucontrol->value.integer.value[0];
> +
> + if (sel < ((1 << MAX98927_AMP_VOL_WIDTH) - 1)) {
> + max98927_wrap_update_bits(max98927, MAX98927_AMP_volume_control,
> + MAX98927_AMP_volume_control_AMP_VOL_Mask, sel);
> + max98927->digital_gain = sel;
> + }
> + return 0;
> +}
> +
> +static int max98927_boost_voltage_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol, MAX98927_Boost_Control_0,
> + MAX98927_Boost_Control_0_BST_VOUT_Mask, 0);
> +}
> +
> +static int max98927_boost_voltage_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol, MAX98927_Boost_Control_0,
> + MAX98927_Boost_Control_0_BST_VOUT_Mask, 0);
> +}
> +
> +static int max98927_amp_vol_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol, MAX98927_Boost_Control_0,
> + MAX98927_Boost_Control_0_BST_VOUT_Mask,
> + MAX98927_AMP_VOL_LOCATION_SHIFT);
> +}
> +
> +static int max98927_amp_dsp_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol, MAX98927_Brownout_enables,
> + MAX98927_Brownout_enables_AMP_DSP_EN, MAX98927_BDE_DSP_SHIFT);
> +}
> +
> +static int max98927_amp_dsp_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol, MAX98927_Brownout_enables,
> + MAX98927_Brownout_enables_AMP_DSP_EN, MAX98927_BDE_DSP_SHIFT);
> +}
> +
> +static int max98927_ramp_switch_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol, MAX98927_AMP_DSP_Config,
> + MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS,
> + MAX98927_SPK_RMP_EN_SHIFT);
> +}
> +static int max98927_ramp_switch_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol, MAX98927_AMP_DSP_Config,
> + MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS,
> + MAX98927_SPK_RMP_EN_SHIFT);
> +}
> +
> +static int max98927_dre_en_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol, MAX98927_DRE_Control,
> + MAX98927_DRE_Control_DRE_EN, 0);
> +}
> +static int max98927_dre_en_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol, MAX98927_DRE_Control,
> + MAX98927_DRE_Control_DRE_EN, 0);
> +}
> +static int max98927_amp_vol_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol,
> + MAX98927_AMP_volume_control,
> + MAX98927_AMP_volume_control_AMP_VOL_SEL,
> + MAX98927_AMP_VOL_LOCATION_SHIFT);
> +}
> +static int max98927_spk_src_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol,
> + MAX98927_Speaker_source_select,
> + MAX98927_Speaker_source_select_SPK_SOURCE_Mask, 0);
> +}
> +
> +static int max98927_spk_src_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol,
> + MAX98927_Speaker_source_select,
> + MAX98927_Speaker_source_select_SPK_SOURCE_Mask, 0);
> +}
> +
> +static int max98927_mono_out_get(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_get(kcontrol, ucontrol,
> + MAX98927_PCM_to_speaker_monomix_A,
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask,
> + MAX98927_PCM_to_speaker_monomix_A_SHIFT);
> +}
> +
> +static int max98927_mono_out_put(struct snd_kcontrol *kcontrol,
> + struct snd_ctl_elem_value *ucontrol)
> +{
> + return max98927_reg_put(kcontrol, ucontrol,
> + MAX98927_PCM_to_speaker_monomix_A,
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask,
> + MAX98927_PCM_to_speaker_monomix_A_SHIFT);
> +}
> +
> +static bool max98927_readable_register(struct device *dev, unsigned int reg)
> +{
> + switch (reg) {
> + case 0x0001 ... 0x0028:
> + case 0x002B ... 0x004E:
> + case 0x0051 ... 0x0055:
> + case 0x005A ... 0x0061:
> + case 0x0072 ... 0x0087:
> + case 0x00FF:
> + case 0x0100:
> + case 0x01FF:
> + return true;
> + }
> + return false;
> +};
> +
> +static const char * const max98927_boost_voltage_text[] = {
> + "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
> + "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
> + "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
> + "9.5V", "9.625V", "9.75V", "9.875V", "10V"
> +};
> +
> +static const char * const max98927_speaker_source_text[] = {
> + "i2s", "reserved", "tone", "pdm"
> +};
> +
> +static const char * const max98927_monomix_output_text[] = {
> + "ch_0", "ch_1", "ch_1_2_div"
> +};
> +
> +static const struct soc_enum max98927_enum[] = {
> + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_monomix_output_text),
> + max98927_monomix_output_text),
> + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_speaker_source_text),
> + max98927_speaker_source_text),
> + SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(max98927_boost_voltage_text),
> + max98927_boost_voltage_text),
> +};
> +
> +static const struct snd_kcontrol_new max98927_snd_controls[] = {
> + SOC_SINGLE_EXT_TLV("Speaker Volume", MAX98927_Speaker_Gain,
> + 0, (1<<MAX98927_Speaker_Gain_Width)-1, 0,
> + max98927_spk_gain_get, max98927_spk_gain_put,
> + max98927_spk_tlv),
> + SOC_SINGLE_EXT_TLV("Digital Gain", MAX98927_AMP_volume_control,
> + 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
> + max98927_digital_gain_get, max98927_digital_gain_put,
> + max98927_digital_tlv),
> + SOC_SINGLE_EXT("Amp DSP Enable", MAX98927_Brownout_enables,
> + MAX98927_BDE_DSP_SHIFT, 1, 0,
> + max98927_amp_dsp_get, max98927_amp_dsp_put),
> + SOC_SINGLE_EXT("Ramp Switch", MAX98927_AMP_DSP_Config,
> + MAX98927_SPK_RMP_EN_SHIFT, 1, 1,
> + max98927_ramp_switch_get, max98927_ramp_switch_put),
> + SOC_SINGLE_EXT("DRE EN", MAX98927_DRE_Control,
> + MAX98927_DRE_Control_DRE_SHIFT, 1, 0,
> + max98927_dre_en_get, max98927_dre_en_put),
> + SOC_SINGLE_EXT("Amp Volume Location", MAX98927_AMP_volume_control,
> + MAX98927_AMP_VOL_LOCATION_SHIFT, 1, 0,
> + max98927_amp_vol_get, max98927_amp_vol_put),
> +
> + SOC_ENUM_EXT("Boost Output Voltage", max98927_enum[2],
> + max98927_boost_voltage_get, max98927_boost_voltage_put),
> + SOC_ENUM_EXT("Speaker Source", max98927_enum[1],
> + max98927_spk_src_get, max98927_spk_src_put),
> + SOC_ENUM_EXT("Monomix Output", max98927_enum[0],
> + max98927_mono_out_get, max98927_mono_out_put),
> +};
> +
> +static const struct snd_soc_dapm_route max98927_audio_map[] = {
> + {"BE_OUT", NULL, "Amp Enable"},
> +};
> +
> +static struct snd_soc_dai_driver max98927_dai[] = {
> + {
> + .name = "max98927-aif1",
> + .playback = {
> + .stream_name = "HiFi Playback",
> + .channels_min = 1,
> + .channels_max = 2,
> + .rates = MAX98927_RATES,
> + .formats = MAX98927_FORMATS,
> + },
> + .capture = {
> + .stream_name = "HiFi Capture",
> + .channels_min = 1,
> + .channels_max = 2,
> + .rates = MAX98927_RATES,
> + .formats = MAX98927_FORMATS,
> + },
> + .ops = &max98927_dai_ops,
> + }
> +};
> +
> +static int max98927_probe(struct snd_soc_codec *codec)
> +{
> + struct max98927_priv *max98927 = snd_soc_codec_get_drvdata(codec);
> + int ret = 0, reg = 0, i;
> +
> + max98927->codec = codec;
> + codec->control_data = max98927->regmap;
> + codec->cache_bypass = 1;
> +
> + /* Software Reset */
> + max98927_wrapper_write(max98927,
> + MAX98927_Software_Reset, MAX98927_Software_Reset_RST);
> +
> + /* Check Revision ID for the primary MAX98927*/
> + ret = regmap_read(max98927->regmap, MAX98927_REV_ID, ®);
> + if (ret < 0)
> + dev_err(codec->dev,
> + "Failed to read: 0x%02X\n", MAX98927_REV_ID);
> + else
> + dev_info(codec->dev,
> + "MAX98927 revisionID: 0x%02X\n", reg);
> +
> + /* Check Revision ID for the secondary MAX98927*/
> + if (max98927->sub_regmap) {
> + ret = regmap_read(max98927->sub_regmap, MAX98927_REV_ID, ®);
> + if (ret < 0)
> + dev_err(codec->dev,
> + "Failed to read: 0x%02X from secodnary device\n"
> + , MAX98927_REV_ID);
> + else
> + dev_info(codec->dev,
> + "Secondary device revisionID: 0x%02X\n", reg);
> + }
> +
> + /* Register initialization */
> + for (i = 0; i < sizeof(max98927_reg_map)/
> + sizeof(max98927_reg_map[0]); i++)
> + max98927_wrapper_write(max98927,
> + max98927_reg_map[i].reg,
> + max98927_reg_map[i].def);
> +
> + if (max98927->regmap)
> + regmap_write(max98927->regmap,
> + MAX98927_PCM_Tx_Channel_Sources_A,
> + (max98927->i_l_slot
> + <<MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT|
> + max98927->v_l_slot)&0xFF);
> + if (max98927->sub_regmap)
> + regmap_write(max98927->sub_regmap,
> + MAX98927_PCM_Tx_Channel_Sources_A,
> + (max98927->i_r_slot
> + <<MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT|
> + max98927->v_r_slot)&0xFF);
> +
> + /* Set interleave mode */
> + if (max98927->interleave_mode)
> + max98927_wrap_update_bits(max98927,
> + MAX98927_PCM_Tx_Channel_Sources_B,
> + MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask,
> + MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask);
> +
> + max98927_handle_pdata(codec);
> +
> + return ret;
> +}
> +
> +static const struct snd_soc_codec_driver soc_codec_dev_max98927 = {
> + .probe = max98927_probe,
> + .dapm_routes = max98927_audio_map,
> + .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
> + .dapm_widgets = max98927_dapm_widgets,
> + .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
> + .controls = max98927_snd_controls,
> + .num_controls = ARRAY_SIZE(max98927_snd_controls),
> +};
> +
> +static const struct regmap_config max98927_regmap = {
> + .reg_bits = 16,
> + .val_bits = 8,
> + .max_register = MAX98927_REV_ID,
> + .reg_defaults = max98927_reg_map,
> + .num_reg_defaults = ARRAY_SIZE(max98927_reg_map),
> + .readable_reg = max98927_readable_register,
> + .cache_type = REGCACHE_RBTREE,
> +};
> +
> +static struct i2c_board_info max98927_i2c_sub_board[] = {
> + {
> + I2C_BOARD_INFO("max98927_sub", 0x39),
> + }
> +};
> +
> +static struct i2c_driver max98927_i2c_sub_driver = {
> + .driver = {
> + .name = "max98927_sub",
> + .owner = THIS_MODULE,
> + },
> +};
> +
> +struct i2c_client *max98927_add_sub_device(int bus_id, int slave_addr)
> +{
> + struct i2c_client *i2c = NULL;
> + struct i2c_adapter *adapter;
> +
> + max98927_i2c_sub_board[0].addr = slave_addr;
> +
> + adapter = i2c_get_adapter(bus_id);
> + if (adapter) {
> + i2c = i2c_new_device(adapter, max98927_i2c_sub_board);
> + if (i2c)
> + i2c->dev.driver = &max98927_i2c_sub_driver.driver;
> + }
> +
> + return i2c;
> +}
> +
> +int probe_common(struct i2c_client *i2c, struct max98927_priv *max98927)
> +{
> + int ret = 0, value;
> +
> + if (!of_property_read_u32(i2c->dev.of_node, "vmon-l-slot", &value))
> + max98927->v_l_slot = value & 0xF;
> + else
> + max98927->v_l_slot = 0;
> + if (!of_property_read_u32(i2c->dev.of_node, "imon-l-slot", &value))
> + max98927->i_l_slot = value & 0xF;
> + else
> + max98927->i_l_slot = 1;
> + if (!of_property_read_u32(i2c->dev.of_node, "vmon-r-slot", &value))
> + max98927->v_r_slot = value & 0xF;
> + else
> + max98927->v_r_slot = 2;
> + if (!of_property_read_u32(i2c->dev.of_node, "imon-r-slot", &value))
> + max98927->i_r_slot = value & 0xF;
> + else
> + max98927->i_r_slot = 3;
> +
> + ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98927,
> + max98927_dai, ARRAY_SIZE(max98927_dai));
> + if (ret < 0)
> + dev_err(&i2c->dev,
> + "Failed to register codec: %d\n", ret);
> + return ret;
> +}
> +
> +static int max98927_i2c_probe(struct i2c_client *i2c,
> + const struct i2c_device_id *id)
> +{
> +
> + int ret = 0, value;
> + struct max98927_priv *max98927 = NULL;
> +
> + max98927 = devm_kzalloc(&i2c->dev,
> + sizeof(*max98927), GFP_KERNEL);
> +
> + if (!max98927) {
> + ret = -ENOMEM;
> + goto err;
> + }
> + i2c_set_clientdata(i2c, max98927);
> +
> + /* update interleave mode info */
> + if (!of_property_read_u32(i2c->dev.of_node,
> + "interleave_mode", &value)) {
> + if (value > 0)
> + max98927->interleave_mode = 1;
> + else
> + max98927->interleave_mode = 0;
> + } else
> + max98927->interleave_mode = 0;
> +
> + /* update direct configuration info */
> + max98927->regcfg = of_get_property(i2c->dev.of_node,
> + "maxim,regcfg", &max98927->regcfg_sz);
> +
> + /* check for secondary MAX98927 */
> + ret = of_property_read_u32(i2c->dev.of_node,
> + "maxim,sub_reg", &max98927->sub_reg);
> + if (ret) {
> + dev_err(&i2c->dev, "Sub-device slave address was not found.\n");
> + max98927->sub_reg = -1;
> + }
> + ret = of_property_read_u32(i2c->dev.of_node,
> + "maxim,sub_bus", &max98927->sub_bus);
> + if (ret) {
> + dev_err(&i2c->dev, "Sub-device bus information was not found.\n");
> + max98927->sub_bus = i2c->adapter->nr;
> + }
> +
> + /* regmap initialization for primary device */
> + max98927->regmap
> + = devm_regmap_init_i2c(i2c, &max98927_regmap);
> + if (IS_ERR(max98927->regmap)) {
> + ret = PTR_ERR(max98927->regmap);
> + dev_err(&i2c->dev,
> + "Failed to allocate regmap: %d\n", ret);
> + goto err;
> + }
> +
> + /* regmap initialization for secondary device */
> + if (max98927->sub_reg > 0) {
> + max98927->sub_i2c = max98927_add_sub_device(max98927->sub_bus,
> + max98927->sub_reg);
> + if (IS_ERR(max98927->sub_i2c)) {
> + dev_err(&max98927->sub_i2c->dev,
> + "Second MAX98927 was not found\n");
> + ret = PTR_ERR(max98927->regmap);
> + goto err;
> + } else {
> + max98927->sub_regmap = regmap_init_i2c(
> + max98927->sub_i2c, &max98927_regmap);
> + if (IS_ERR(max98927->sub_regmap)) {
> + ret = PTR_ERR(max98927->sub_regmap);
> + dev_err(&max98927->sub_i2c->dev,
> + "Failed to allocate sub_regmap: %d\n",
> + ret);
> + goto err;
> + }
> + }
> + }
> +
> + /* codec registeration */
> + ret = probe_common(i2c, max98927);
> +
> + return ret;
> +
> +err:
> + if (max98927)
> + devm_kfree(&i2c->dev, max98927);
> + return ret;
> +}
> +
> +static int max98927_i2c_remove(struct i2c_client *client)
> +{
> + snd_soc_unregister_codec(&client->dev);
> + return 0;
> +}
> +
> +static const struct i2c_device_id max98927_i2c_id[] = {
> + { "max98927", 0},
> + { },
> +};
> +
> +MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
> +
> +static const struct of_device_id max98927_of_match[] = {
> + { .compatible = "maxim,max98927", },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, max98927_of_match);
> +
> +static struct i2c_driver max98927_i2c_driver = {
> + .driver = {
> + .name = "max98927",
> + .owner = THIS_MODULE,
> + .of_match_table = of_match_ptr(max98927_of_match),
> + .pm = NULL,
> + },
> + .probe = max98927_i2c_probe,
> + .remove = max98927_i2c_remove,
> + .id_table = max98927_i2c_id,
> +};
> +
> +module_i2c_driver(max98927_i2c_driver)
> +
> +MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
> +MODULE_AUTHOR("Ryan Lee <ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>");
> +MODULE_LICENSE("GPL");
> diff --git a/sound/soc/codecs/max98927.h b/sound/soc/codecs/max98927.h
> new file mode 100755
> index 0000000..2305185
> --- /dev/null
> +++ b/sound/soc/codecs/max98927.h
> @@ -0,0 +1,1253 @@
> +/*
> + * max98927.c -- MAX98927 ALSA Soc Audio driver
> + *
> + * Copyright 2008-11 Wolfson Microelectronics PLC.
> + * Author: Ryan Lee <ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the
> + * Free Software Foundation; either version 2 of the License, or (at your
> + * option) any later version.
> + *
> + */
> +#ifndef __MAX98927_REGISTERDEFS_H
> +#define __MAX98927_REGISTERDEFS_H
> +#ifdef CONFIG_SND_SOC_MAXIM_DSM
> +#include <sound/maxim_dsm.h>
> +#endif /* CONFIG_SND_SOC_MAXIM_DSM */
> +
> +enum {
> + PRI_MAX98927 = 0,
> + SEC_MAX98927 = 1,
> + MAX_DEV_ID_MAX98927,
> +} MAX98927deviceID;
> +
> +enum {
> + /*Interrupt Raw 1 (Address 0x0001)*/
> + MAX98927_Interrupt_Raw_1 = 0x0001,
> + MAX98927_Interrupt_Raw_1_BDE_ACTIVE_END_RAW = (0x1 << 0),
> + MAX98927_Interrupt_Raw_1_BDE_ACTIVE_BGN_RAW = (0x1 << 1),
> + MAX98927_Interrupt_Raw_1_BDE_LEVEL_CHANGE_RAW = (0x1 << 2),
> + MAX98927_Interrupt_Raw_1_BDE_L8_RAW = (0x1 << 3),
> + MAX98927_Interrupt_Raw_1_THERMWARN_END_RAW = (0x1 << 4),
> + MAX98927_Interrupt_Raw_1_THERMWARN_START_RAW = (0x1 << 5),
> + MAX98927_Interrupt_Raw_1_THERMSHDN_END_RAW = (0x1 << 6),
> + MAX98927_Interrupt_Raw_1_THERMSHDN_START_RAW = (0x1 << 7),
> +
> + /* Interrupt Raw 2 (Address 0x0002)*/
> + MAX98927_Interrupt_Raw_2 = 0x0002,
> + MAX98927_Interrupt_Raw_2_WATCHDOGWARN_RAW = (0x1 << 0),
> + MAX98927_Interrupt_Raw_2_WATCHDOGFAIL_RAW = (0x1 << 1),
> + MAX98927_Interrupt_Raw_2_BOOSTCURRLIM_RAW = (0x1 << 2),
> + MAX98927_Interrupt_Raw_2_CLKSTOP_RAW = (0x1 << 3),
> + MAX98927_Interrupt_Raw_2_CLKSTART_RAW = (0x1 << 4),
> + MAX98927_Interrupt_Raw_2_MEASADC_END_RAW = (0x1 << 5),
> + MAX98927_Interrupt_Raw_2_PWRDN_DONE_RAW = (0x1 << 6),
> + MAX98927_Interrupt_Raw_2_PWRUP_DONE_RAW = (0x1 << 7),
> +
> + /* Interrupt Raw 3 (Address 0x0003)*/
> + MAX98927_Interrupt_Raw_3 = 0x0003,
> + MAX98927_Interrupt_Raw_3_PWRUP_FAIL_RAW = (0x1 << 0),
> + MAX98927_Interrupt_Raw_3_AUTH_DONE_RAW = (0x1 << 1),
> + MAX98927_Interrupt_Raw_3_SPK_OVC_RAW = (0x1 << 2),
> + MAX98927_Interrupt_Raw_3_BST_UVLO_RAW = (0x1 << 3),
> +
> + /* Interrupt State 1 (Address 0x0004)*/
> + MAX98927_Interrupt_State_1 = 0x0004,
> + MAX98927_Interrupt_State_1_BDE_ACTIVE_END_STATE = (0x1 << 0),
> + MAX98927_Interrupt_State_1_BDE_ACTIVE_BGN_STATE = (0x1 << 1),
> + MAX98927_Interrupt_State_1_BDE_LEVEL_CHANGE_STATE = (0x1 << 2),
> + MAX98927_Interrupt_State_1_BDE_L8_STATE = (0x1 << 3),
> + MAX98927_Interrupt_State_1_THERMWARN_END_STATE = (0x1 << 4),
> + MAX98927_Interrupt_State_1_THERMWARN_START_STATE = (0x1 << 5),
> + MAX98927_Interrupt_State_1_THERMSHDN_END_STATE = (0x1 << 6),
> + MAX98927_Interrupt_State_1_THERMSHDN_START_STATE = (0x1 << 7),
> +
> + /* Interrupt State 2 (Address 0x0005)*/
> + MAX98927_Interrupt_State_2 = 0x0005,
> + MAX98927_Interrupt_State_2_WATCHDOGWARN_STATE = (0x1 << 0),
> + MAX98927_Interrupt_State_2_WATCHDOGFAIL_STATE = (0x1 << 1),
> + MAX98927_Interrupt_State_2_BOOSTCURRLIM_STATE = (0x1 << 2),
> + MAX98927_Interrupt_State_2_CLKSTOP_STATE = (0x1 << 3),
> + MAX98927_Interrupt_State_2_CLKSTART_STATE = (0x1 << 4),
> + MAX98927_Interrupt_State_2_MEASADC_END_STATE = (0x1 << 5),
> + MAX98927_Interrupt_State_2_PWRDN_DONE_STATE = (0x1 << 6),
> + MAX98927_Interrupt_State_2_PWRUP_DONE_STATE = (0x1 << 7),
> +
> + /* Interrupt State 3 (Address 0x0006)*/
> + MAX98927_Interrupt_State_3 = 0x0006,
> + MAX98927_Interrupt_State_3_PWRUP_FAIL_STATE = (0x1 << 0),
> + MAX98927_Interrupt_State_3_AUTH_DONE_STATE = (0x1 << 1),
> + MAX98927_Interrupt_State_3_SPK_OVC_STATE = (0x1 << 2),
> + MAX98927_Interrupt_State_3_BST_UVLO_STATE = (0x1 << 3),
> +
> + /* Interrupt Flag 1 (Address 0x0007)*/
> + MAX98927_Interrupt_Flag_1 = 0x0007,
> + MAX98927_Interrupt_Flag_1_BDE_ACTIVE_END_FLAG = (0x1 << 0),
> + MAX98927_Interrupt_Flag_1_BDE_ACTIVE_BGN_FLAG = (0x1 << 1),
> + MAX98927_Interrupt_Flag_1_BDE_LEVEL_CHANGE_FLAG = (0x1 << 2),
> + MAX98927_Interrupt_Flag_1_BDE_L8_FLAG = (0x1 << 3),
> + MAX98927_Interrupt_Flag_1_THERMWARN_END_FLAG = (0x1 << 4),
> + MAX98927_Interrupt_Flag_1_THERMWARN_START_FLAG = (0x1 << 5),
> + MAX98927_Interrupt_Flag_1_THERMSHDN_END_FLAG = (0x1 << 6),
> + MAX98927_Interrupt_Flag_1_THERMSHDN_START_FLAG = (0x1 << 7),
> +
> + /* Interrupt Flag 2 (Address 0x0008)*/
> + MAX98927_Interrupt_Flag_2 = 0x0008,
> + MAX98927_Interrupt_Flag_2_WATCHDOGWARN_FLAG = (0x1 << 0),
> + MAX98927_Interrupt_Flag_2_WATCHDOGFAIL_FLAG = (0x1 << 1),
> + MAX98927_Interrupt_Flag_2_BOOSTCURRLIM_FLAG = (0x1 << 2),
> + MAX98927_Interrupt_Flag_2_CLKSTOP_FLAG = (0x1 << 3),
> + MAX98927_Interrupt_Flag_2_CLKSTART_FLAG = (0x1 << 4),
> + MAX98927_Interrupt_Flag_2_MEASADC_END_FLAG = (0x1 << 5),
> + MAX98927_Interrupt_Flag_2_PWRDN_DONE_FLAG = (0x1 << 6),
> + MAX98927_Interrupt_Flag_2_PWRUP_DONE_FLAG = (0x1 << 7),
> +
> + /* Interrupt Flag 3 (Address 0x0009)*/
> + MAX98927_Interrupt_Flag_3 = 0x0009,
> + MAX98927_Interrupt_Flag_3_PWRUP_FAIL_FLAG = (0x1 << 0),
> + MAX98927_Interrupt_Flag_3_AUTH_DONE_FLAG = (0x1 << 1),
> + MAX98927_Interrupt_Flag_3_SPK_OVC_FLAG = (0x1 << 2),
> + MAX98927_Interrupt_Flag_3_BST_UVLO_FLAG = (0x1 << 3),
> +
> + /* Interrupt Enable 1 (Address 0x000a)*/
> + MAX98927_Interrupt_Enable_1 = 0x000a,
> + MAX98927_Interrupt_Enable_1_BDE_ACTIVE_END_EN = (0x1 << 0),
> + MAX98927_Interrupt_Enable_1_BDE_ACTIVE_BGN_EN = (0x1 << 1),
> + MAX98927_Interrupt_Enable_1_BDE_LEVEL_CHANGE_EN = (0x1 << 2),
> + MAX98927_Interrupt_Enable_1_BDE_L8_EN = (0x1 << 3),
> + MAX98927_Interrupt_Enable_1_THERMWARN_END_EN = (0x1 << 4),
> + MAX98927_Interrupt_Enable_1_THERMWARN_START_EN = (0x1 << 5),
> + MAX98927_Interrupt_Enable_1_THERMSHDN_END_EN = (0x1 << 6),
> + MAX98927_Interrupt_Enable_1_THERMSHDN_START_EN = (0x1 << 7),
> +
> + /* Interrupt Enable 2 (Address 0x000b)*/
> + MAX98927_Interrupt_Enable_2 = 0x000b,
> + MAX98927_Interrupt_Enable_2_WATCHDOGWARN_EN = (0x1 << 0),
> + MAX98927_Interrupt_Enable_2_WATCHDOGFAIL_EN = (0x1 << 1),
> + MAX98927_Interrupt_Enable_2_BOOSTCURRLIM_EN = (0x1 << 2),
> + MAX98927_Interrupt_Enable_2_CLKSTOP_EN = (0x1 << 3),
> + MAX98927_Interrupt_Enable_2_CLKSTART_EN = (0x1 << 4),
> + MAX98927_Interrupt_Enable_2_MEASADC_END_EN = (0x1 << 5),
> + MAX98927_Interrupt_Enable_2_PWRDN_DONE_EN = (0x1 << 6),
> + MAX98927_Interrupt_Enable_2_PWRUP_DONE_EN = (0x1 << 7),
> +
> + /* Interrupt Enable 3 (Address 0x000c)*/
> + MAX98927_Interrupt_Enable_3 = 0x000c,
> + MAX98927_Interrupt_Enable_3_PWRUP_FAIL_EN = (0x1 << 0),
> + MAX98927_Interrupt_Enable_3_AUTH_DONE_EN = (0x1 << 1),
> + MAX98927_Interrupt_Enable_3_SPK_OVC_EN = (0x1 << 2),
> + MAX98927_Interrupt_Enable_3_BST_UVLO_EN = (0x1 << 3),
> +
> + /* Interrupt Flag Clear 1 (Address 0x000d)*/
> + MAX98927_Interrupt_Flag_Clear_1 = 0x000d,
> + MAX98927_Interrupt_Flag_Clear_1_BDE_ACTIVE_END_CLR = (0x1 << 0),
> + MAX98927_Interrupt_Flag_Clear_1_BDE_ACTIVE_BGN_CLR = (0x1 << 1),
> + MAX98927_Interrupt_Flag_Clear_1_BDE_LEVEL_CHANGE_CLR = (0x1 << 2),
> + MAX98927_Interrupt_Flag_Clear_1_BDE_L8_CLR = (0x1 << 3),
> + MAX98927_Interrupt_Flag_Clear_1_THERMWARN_END_CLR = (0x1 << 4),
> + MAX98927_Interrupt_Flag_Clear_1_THERMWARN_START_CLR = (0x1 << 5),
> + MAX98927_Interrupt_Flag_Clear_1_THERMSHDN_END_CLR = (0x1 << 6),
> + MAX98927_Interrupt_Flag_Clear_1_THERMSHDN_START_CLR = (0x1 << 7),
> +
> + /* Interrupt Flag Clear 2 (Address 0x000e)*/
> + MAX98927_Interrupt_Flag_Clear_2 = 0x000e,
> + MAX98927_Interrupt_Flag_Clear_2_WATCHDOGWARN_CLR = (0x1 << 0),
> + MAX98927_Interrupt_Flag_Clear_2_WATCHDOGFAIL_CLR = (0x1 << 1),
> + MAX98927_Interrupt_Flag_Clear_2_BOOSTCURRLIM_CLR = (0x1 << 2),
> + MAX98927_Interrupt_Flag_Clear_2_CLKSTOP_CLR = (0x1 << 3),
> + MAX98927_Interrupt_Flag_Clear_2_CLKSTART_CLR = (0x1 << 4),
> + MAX98927_Interrupt_Flag_Clear_2_MEASADC_END_CLR = (0x1 << 5),
> + MAX98927_Interrupt_Flag_Clear_2_PWRDN_DONE_CLR = (0x1 << 6),
> + MAX98927_Interrupt_Flag_Clear_2_PWRUP_DONE_CLR = (0x1 << 7),
> +
> + /* Interrupt Flag Clear 3 (Address 0x000f)*/
> + MAX98927_Interrupt_Flag_Clear_3 = 0x000f,
> + MAX98927_Interrupt_Flag_Clear_3_PWRUP_FAIL_CLR = (0x1 << 0),
> + MAX98927_Interrupt_Flag_Clear_3_AUTH_DONE_CLR = (0x1 << 1),
> + MAX98927_Interrupt_Flag_Clear_3_SPK_OVC_CLR = (0x1 << 2),
> + MAX98927_Interrupt_Flag_Clear_3_BST_UVLO_CLR = (0x1 << 3),
> +
> + /* IRQ Control (Address 0x0010)*/
> + MAX98927_IRQ_Control = 0x0010,
> + MAX98927_IRQ_Control_IRQ_EN = (0x1 << 0),
> + MAX98927_IRQ_Control_IRQ_POL = (0x1 << 1),
> + MAX98927_IRQ_Control_IRQ_MODE = (0x1 << 2),
> +
> + /* Clock monitor enable (Address 0x0011)*/
> + MAX98927_Clock_monitor_enable = 0x0011,
> + MAX98927_Clock_monitor_enable_CMON_ENA = (0x1 << 0),
> + MAX98927_Clock_monitor_enable_CMON_AUTORESTART_ENA = (0x1 << 1),
> +
> + /* Watchdog Control (Address 0x0012)*/
> + MAX98927_Watchdog_Control = 0x0012,
> + MAX98927_Watchdog_Control_WDT_ENA = (0x1 << 0),
> + MAX98927_Watchdog_Control_WDT_MODE = (0x1 << 1),
> + MAX98927_Watchdog_Control_WDT_TO_SEL_Mask = (0x3 << 2),
> + MAX98927_Watchdog_Control_WDT_TO_SEL_5 = (0x0 << 2),
> + MAX98927_Watchdog_Control_WDT_TO_SEL_10 = (0x1 << 2),
> + MAX98927_Watchdog_Control_WDT_TO_SEL_35 = (0x2 << 2),
> + MAX98927_Watchdog_Control_WDT_TO_SEL_50 = (0x3 << 2),
> + MAX98927_Watchdog_Control_WDT_HW_SOURCE = (0x1 << 4),
> +
> + /* Watchdog SW Reset (Address 0x0013)*/
> + MAX98927_Watchdog_SW_Reset = 0x0013,
> + MAX98927_Watchdog_SW_Reset_WDT_SW_RST_Mask = (0xff << 0),
> +
> + /* Meas ADC Thermal Warning Threshhold (Address 0x0014)*/
> + MAX98927_Meas_ADC_TW_Threshhold = 0x0014,
> + MAX98927_Meas_ADC_TW_Threshhold_MEAS_ADC_WARN_THRESH_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Thermal Shutdown Threshhold (Address 0x0015)*/
> + MAX98927_Meas_ADC_TS_Threshhold = 0x0015,
> + MAX98927_Meas_ADC_TS_Threshhold_MEAS_ADC_SHDN_THRESH_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Thermal Hysteresis (Address 0x0016)*/
> + MAX98927_Meas_ADC_Thermal_Hysteresis = 0x0016,
> + MAX98927_Meas_ADC_TH_MEAS_ADC_THERM_HYST_Mask = (0x1f << 0),
> +
> + /* Pin Config (Address 0x0017)*/
> + MAX98927_Pin_Config = 0x0017,
> + MAX98927_Pin_Config_DOUT_DRV_Mask = (0x3 << 0),
> + MAX98927_Pin_Config_DOUT_DRV_01 = (0x0 << 0),
> + MAX98927_Pin_Config_DOUT_DRV_11 = (0x2 << 0),
> + MAX98927_Pin_Config_BCLK_DRV_Mask = (0x3 << 2),
> + MAX98927_Pin_Config_BCLK_DRV_01 = (0x0 << 2),
> + MAX98927_Pin_Config_BCLK_DRV_11 = (0x2 << 2),
> + MAX98927_Pin_Config_LRCLK_DRV_Mask = (0x3 << 4),
> + MAX98927_Pin_Config_LRCLK_DRV_01 = (0x0 << 4),
> + MAX98927_Pin_Config_LRCLK_DRV_11 = (0x2 << 4),
> + MAX98927_Pin_Config_ICC_DRV_Mask = (0x3 << 6),
> + MAX98927_Pin_Config_ICC_DRV_01 = (0x0 << 6),
> + MAX98927_Pin_Config_ICC_DRV_11 = (0x2 << 6),
> +
> + /* PCM Rx Enables A (Address 0x0018)*/
> + MAX98927_PCM_Rx_Enables_A = 0x0018,
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH0_EN = (0x1 << 0),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH1_EN = (0x1 << 1),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH2_EN = (0x1 << 2),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH3_EN = (0x1 << 3),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH4_EN = (0x1 << 4),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH5_EN = (0x1 << 5),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH6_EN = (0x1 << 6),
> + MAX98927_PCM_Rx_Enables_A_PCM_RX_CH7_EN = (0x1 << 7),
> +
> + /* PCM Rx Enables B (Address 0x0019)*/
> + MAX98927_PCM_Rx_Enables_B = 0x0019,
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH8_EN = (0x1 << 0),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH9_EN = (0x1 << 1),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH10_EN = (0x1 << 2),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH11_EN = (0x1 << 3),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH12_EN = (0x1 << 4),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH13_EN = (0x1 << 5),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH14_EN = (0x1 << 6),
> + MAX98927_PCM_Rx_Enables_B_PCM_RX_CH15_EN = (0x1 << 7),
> +
> + /* PCM Tx Enables A (Address 0x001a)*/
> + MAX98927_PCM_Tx_Enables_A = 0x001a,
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH0_EN = (0x1 << 0),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH1_EN = (0x1 << 1),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH2_EN = (0x1 << 2),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH3_EN = (0x1 << 3),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH4_EN = (0x1 << 4),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH5_EN = (0x1 << 5),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH6_EN = (0x1 << 6),
> + MAX98927_PCM_Tx_Enables_A_PCM_TX_CH7_EN = (0x1 << 7),
> +
> + /* PCM Tx Enables B (Address 0x001b)*/
> + MAX98927_PCM_Tx_Enables_B = 0x001b,
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH8_EN = (0x1 << 0),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH9_EN = (0x1 << 1),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH10_EN = (0x1 << 2),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH11_EN = (0x1 << 3),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH12_EN = (0x1 << 4),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH13_EN = (0x1 << 5),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH14_EN = (0x1 << 6),
> + MAX98927_PCM_Tx_Enables_B_PCM_TX_CH15_EN = (0x1 << 7),
> +
> + /* PCM Tx HiZ Control A (Address 0x001c)*/
> + MAX98927_PCM_Tx_HiZ_Control_A = 0x001c,
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH0_HIZ = (0x1 << 0),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH1_HIZ = (0x1 << 1),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH2_HIZ = (0x1 << 2),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH3_HIZ = (0x1 << 3),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH4_HIZ = (0x1 << 4),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH5_HIZ = (0x1 << 5),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH6_HIZ = (0x1 << 6),
> + MAX98927_PCM_Tx_HiZ_Control_A_PCM_TX_CH7_HIZ = (0x1 << 7),
> +
> + /* PCM Tx HiZ Control B (Address 0x001d)*/
> + MAX98927_PCM_Tx_HiZ_Control_B = 0x001d,
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH8_HIZ = (0x1 << 0),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH9_HIZ = (0x1 << 1),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH10_HIZ = (0x1 << 2),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH11_HIZ = (0x1 << 3),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH12_HIZ = (0x1 << 4),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH13_HIZ = (0x1 << 5),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH14_HIZ = (0x1 << 6),
> + MAX98927_PCM_Tx_HiZ_Control_B_PCM_TX_CH15_HIZ = (0x1 << 7),
> +
> + /* PCM Tx Channel Sources A (Address 0x001e)*/
> + MAX98927_PCM_Tx_Channel_Sources_A = 0x001e,
> + MAX98927_PCM_Tx_Channel_Sources_A_PCM_IVADC_V_DEST_Mask = (0xf << 0),
> + MAX98927_PCM_Tx_Channel_Sources_A_PCM_IVADC_I_DEST_Mask = (0xf << 4),
> +
> + /* PCM Tx Channel Sources B (Address 0x001f)*/
> + MAX98927_PCM_Tx_Channel_Sources_B = 0x001f,
> + MAX98927_PCM_Tx_Channel_Sources_B_PCM_AMP_DSP_DEST_Mask = (0xf << 0),
> + MAX98927_PCM_Tx_Channel_Src_INTERLEAVE_Mask = (0x1 << 5),
> +
> + /* PCM Mode Config (Address 0x0020)*/
> + MAX98927_PCM_Mode_Config = 0x0020,
> + MAX98927_PCM_Mode_Config_PCM_TX_EXTRA_HIZ = (0x1 << 0),
> + MAX98927_PCM_Mode_Config_PCM_CHANSEL = (0x1 << 1),
> + MAX98927_PCM_Mode_Config_PCM_BCLKEDGE = (0x1 << 2),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_Mask = (0x7 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_I2S = (0x0 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_LEFT = (0x1 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_0 = (0x3 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_1 = (0x4 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_TDM_2 = (0x5 << 3),
> + MAX98927_PCM_Mode_Config_PCM_FORMAT_ = (0x6 << 3),
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_Mask = (0x3 << 6),
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_16 = (0x1 << 6),
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_24 = (0x2 << 6),
> + MAX98927_PCM_Mode_Config_PCM_CHANSZ_32 = (0x3 << 6),
> +
> + /* PCM Master Mode (Address 0x0021)*/
> + MAX98927_PCM_Master_Mode = 0x0021,
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_Mask = (0x3 << 0),
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_SLAVE = (0x0 << 0),
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_MASTER = (0x3 << 0),
> + MAX98927_PCM_Master_Mode_PCM_MSTR_MODE_HYBRID = (0x1 << 0),
> + MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_Mask = (0xf << 2),
> + MAX98927_PCM_Master_Mode_PCM_CLK_SOURCE = (0x1 << 6),
> +
> + /* PCM Clock setup (Address 0x0022)*/
> + MAX98927_PCM_Clock_setup = 0x0022,
> + MAX98927_PCM_Clock_setup_PCM_BSEL_Mask = (0xf << 0),
> + MAX98927_PCM_Clock_setup_PCM_MSEL_Mask = (0xf << 4),
> +
> + /* PCM Sample rate setup 1 (Address 0x0023)*/
> + MAX98927_PCM_Sample_rate_setup_1 = 0x0023,
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_Mask = (0xf << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_8000 = (0x0 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_11025 = (0x1 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_12000 = (0x2 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_16000 = (0x3 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_22050 = (0x4 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_24000 = (0x5 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_32000 = (0x6 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_44100 = (0x7 << 0),
> + MAX98927_PCM_Sample_rate_setup_1_DIG_IF_SR_48000 = (0x8 << 0),
> +
> + /* PCM Sample rate setup 1 (Address 0x0024)*/
> + MAX98927_PCM_Sample_rate_setup_2 = 0x0024,
> + MAX98927_PCM_Sample_rate_setup_2_IVADC_SR_Mask = (0xf << 0),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_Mask = (0xf << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0001 = (0x0 << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0011 = (0x2 << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0101 = (0x4 << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_0111 = (0x6 << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1001 = (0x8 << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1011 = (0xa << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_1101 = (0xc << 4),
> + MAX98927_PCM_Sample_rate_setup_2_SPK_SR_ = (0xf << 4),
> +
> + /* PCM to speaker monomix A (Address 0x0025)*/
> + MAX98927_PCM_to_speaker_monomix_A = 0x0025,
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CH0_SOURCE_Mask = (0xf << 0),
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_Mask = (0x3 << 6),
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_1 = (0x0 << 6),
> + MAX98927_PCM_to_spkmonomix_A_DMONOMIX_CFG_3 = (0x0 << 6),
> +
> + /* PCM to speaker monomix B (Address 0x0026)*/
> + MAX98927_PCM_to_spkmonomix_B = 0x0026,
> + MAX98927_PCM_to_spkmonomix_B_DMONOMIX_CH1_SOURCE_Mask = (0xf << 0),
> +
> + /* ICC RX Enables A (Address 0x0027)*/
> + MAX98927_ICC_RX_Enables_A = 0x0027,
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH0_EN = (0x1 << 0),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH1_EN = (0x1 << 1),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH2_EN = (0x1 << 2),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH3_EN = (0x1 << 3),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH4_EN = (0x1 << 4),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH5_EN = (0x1 << 5),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH6_EN = (0x1 << 6),
> + MAX98927_ICC_RX_Enables_A_ICC_RX_CH7_EN = (0x1 << 7),
> +
> + /* ICC RX Enables B (Address 0x0028)*/
> + MAX98927_ICC_RX_Enables_B = 0x0028,
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH8_EN = (0x1 << 0),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH9_EN = (0x1 << 1),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH10_EN = (0x1 << 2),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH11_EN = (0x1 << 3),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH12_EN = (0x1 << 4),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH13_EN = (0x1 << 5),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH14_EN = (0x1 << 6),
> + MAX98927_ICC_RX_Enables_B_ICC_RX_CH15_EN = (0x1 << 7),
> +
> + /* ICC TX Enables A (Address 0x002b)*/
> + MAX98927_ICC_TX_Enables_A = 0x002b,
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH0_EN = (0x1 << 0),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH1_EN = (0x1 << 1),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH2_EN = (0x1 << 2),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH3_EN = (0x1 << 3),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH4_EN = (0x1 << 4),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH5_EN = (0x1 << 5),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH6_EN = (0x1 << 6),
> + MAX98927_ICC_TX_Enables_A_ICC_TX_CH7_EN = (0x1 << 7),
> +
> + /* ICC TX Enables B (Address 0x002c)*/
> + MAX98927_ICC_TX_Enables_B = 0x002c,
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH8_EN = (0x1 << 0),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH9_EN = (0x1 << 1),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH10_EN = (0x1 << 2),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH11_EN = (0x1 << 3),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH12_EN = (0x1 << 4),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH13_EN = (0x1 << 5),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH14_EN = (0x1 << 6),
> + MAX98927_ICC_TX_Enables_B_ICC_TX_CH15_EN = (0x1 << 7),
> +
> + /* ICC Data Order Select (Address 0x002d)*/
> + MAX98927_ICC_Data_Order_Select = 0x002d,
> + MAX98927_ICC_Data_Order_Select_ICC_DRIVE_MODE = (0x1 << 3),
> +
> + /* ICC HiZ Manual Mode (Address 0x002e)*/
> + MAX98927_ICC_HiZ_Manual_Mode = 0x002e,
> + MAX98927_ICC_HiZ_Manual_Mode_ICC_TX_HIZ_MANUAL = (0x1 << 0),
> + MAX98927_ICC_HiZ_Manual_Mode_ICC_TX_EXTRA_HIZ = (0x1 << 1),
> +
> + /* ICC TX HiZ Enables A (Address 0x002f)*/
> + MAX98927_ICC_TX_HiZ_Enables_A = 0x002f,
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH0_HIZ = (0x1 << 0),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH1_HIZ = (0x1 << 1),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH2_HIZ = (0x1 << 2),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH3_HIZ = (0x1 << 3),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH4_HIZ = (0x1 << 4),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH5_HIZ = (0x1 << 5),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH6_HIZ = (0x1 << 6),
> + MAX98927_ICC_TX_HiZ_Enables_A_ICC_TX_CH7_HIZ = (0x1 << 7),
> +
> + /* ICC TX HiZ Enables B (Address 0x0030)*/
> + MAX98927_ICC_TX_HiZ_Enables_B = 0x0030,
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH8_HIZ = (0x1 << 0),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH9_HIZ = (0x1 << 1),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH10_HIZ = (0x1 << 2),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH11_HIZ = (0x1 << 3),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH12_HIZ = (0x1 << 4),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH13_HIZ = (0x1 << 5),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH14_HIZ = (0x1 << 6),
> + MAX98927_ICC_TX_HiZ_Enables_B_ICC_TX_CH15_HIZ = (0x1 << 7),
> +
> + /* ICC Link Enables (Address 0x0031)*/
> + MAX98927_ICC_Link_Enables = 0x0031,
> + MAX98927_ICC_Link_Enables_ICC_LINK_EN = (0x1 << 1),
> +
> + /* PDM Tx Enables (Address 0x0032)*/
> + MAX98927_PDM_Tx_Enables = 0x0032,
> + MAX98927_PDM_Tx_Enables_PDM_TX_EN = (0x1 << 0),
> + MAX98927_PDM_Tx_Enables_PDM_TX_CLK_DIV2 = (0x1 << 1),
> +
> + /* PDM Tx HiZ Control (Address 0x0033)*/
> + MAX98927_PDM_Tx_HiZ_Control = 0x0033,
> + MAX98927_PDM_Tx_HiZ_Control_PDM_TX_HIZ = (0x1 << 0),
> +
> + /* PDM Tx Control (Address 0x0034)*/
> + MAX98927_PDM_Tx_Control = 0x0034,
> + MAX98927_PDM_Tx_Control_PDM_TX_CH0_SOURCE = (0x1 << 0),
> + MAX98927_PDM_Tx_Control_PDM_TX_CH1_SOURCE = (0x1 << 1),
> +
> + /* PDM Rx Enable (Address 0x0034)*/
> + MAX98927_PDM_Rx_Enable = 0x0035,
> + MAX98927_PDM_Rx_Enable_PDM_RX_EN = (0x1 << 0),
> + MAX98927_PDM_Rx_Enable_PDM_DSP_EN = (0x1 << 1),
> + MAX98927_PDM_Rx_Enable_PDM_DITH_EN = (0x1 << 2),
> + MAX98927_PDM_Rx_Enable_PDM_RX_CH_SEL = (0x1 << 3),
> + MAX98927_PDM_Rx_Enable_PDM_FIFO_RDY_LVL_Mask = (0xf << 4),
> +
> + /* AMP volume control (Address 0x0036)*/
> + MAX98927_AMP_volume_control = 0x0036,
> + MAX98927_AMP_volume_control_AMP_VOL_Mask = (0x7f << 0),
> + MAX98927_AMP_volume_control_AMP_VOL_SEL = (0x1 << 7),
> +
> + /* AMP DSP Config (Address 0x0037)*/
> + MAX98927_AMP_DSP_Config = 0x0037,
> + MAX98927_AMP_DSP_Config_AMP_DCBLK_EN = (0x1 << 0),
> + MAX98927_AMP_DSP_Config_AMP_DITH_EN = (0x1 << 1),
> + MAX98927_AMP_DSP_Config_DAC_HALF_REF_CURRENT = (0x1 << 2),
> + MAX98927_AMP_DSP_Config_DAC_DOUBLE_RFB = (0x1 << 3),
> + MAX98927_AMP_DSP_Config_AMP_VOL_RMP_BYPASS = (0x1 << 4),
> + MAX98927_AMP_DSP_Config_DAC_INVERT = (0x1 << 5),
> +
> + /* Tone Generator and DC Config (Address 0x0038)*/
> + MAX98927_Tone_Generator_and_DC_Config = 0x0038,
> + MAX98927_Tone_Generator_and_DC_Config_TONE_CONFIG_Mask = (0xf << 0),
> +
> + /* DRE Control (Address 0x0039)*/
> + MAX98927_DRE_Control = 0x0039,
> + MAX98927_DRE_Control_DRE_EN = (0x1 << 0),
> +
> + /* AMP enables (Address 0x003a)*/
> + MAX98927_AMP_enables = 0x003a,
> + MAX98927_AMP_enables_SPK_EN = (0x1 << 0),
> +
> + /* Speaker source select (Address 0x003b)*/
> + MAX98927_Speaker_source_select = 0x003b,
> + MAX98927_Speaker_source_select_SPK_SOURCE_Mask = (0x3 << 0),
> + MAX98927_Speaker_source_select_SPK_SOURCE_01 = (0x0 << 0),
> + MAX98927_Speaker_source_select_SPK_SOURCE_11 = (0x2 << 0),
> +
> + /* Speaker Gain (Address 0x003c)*/
> + MAX98927_Speaker_Gain = 0x003c,
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_Mask = (0x7 << 0),
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_001 = (0x0 << 0),
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_011 = (0x2 << 0),
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_101 = (0x4 << 0),
> + MAX98927_Speaker_Gain_SPK_PCM_GAIN_111 = (0x6 << 0),
> + MAX98927_Speaker_Gain_SPK_PDM_GAIN_Mask = (0x7 << 4),
> + MAX98927_Speaker_Gain_SPK_PDM_GAIN_001 = (0x0 << 4),
> + MAX98927_Speaker_Gain_SPK_PDM_GAIN_011 = (0x2 << 4),
> + MAX98927_Speaker_Gain_SPK_PDM_GAIN_101 = (0x4 << 4),
> + MAX98927_Speaker_Gain_SPK_PDM_GAIN_111 = (0x6 << 4),
> +
> + /* SSM Configuration (Address 0x003d)*/
> + MAX98927_SSM_Configuration = 0x003d,
> + MAX98927_SSM_Configuration_SSM_MOD_INDEX_Mask = (0x7 << 0),
> + MAX98927_SSM_Configuration_SSM_MOD_INDEX_001 = (0x0 << 0),
> + MAX98927_SSM_Configuration_SSM_MOD_INDEX_011 = (0x2 << 0),
> + MAX98927_SSM_Configuration_SSM_MOD_INDEX_101 = (0x4 << 0),
> + MAX98927_SSM_Configuration_SSM_MOD_INDEX_ = (0x6 << 0),
> + MAX98927_SSM_Configuration_SPK_FSW_SEL = (0x1 << 3),
> + MAX98927_SSM_Configuration_SSM_ENA = (0x1 << 7),
> +
> + /* Measurement enables (Address 0x003e)*/
> + MAX98927_Measurement_enables = 0x003e,
> + MAX98927_Measurement_enables_IVADC_V_EN = (0x1 << 0),
> + MAX98927_Measurement_enables_IVADC_I_EN = (0x1 << 1),
> +
> + /* Measurement DSP Config (Address 0x003f)*/
> + MAX98927_Measurement_DSP_Config = 0x003f,
> + MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_EN = (0x1 << 0),
> + MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_EN = (0x1 << 1),
> + MAX98927_Measurement_DSP_Config_MEAS_DITH_EN = (0x1 << 2),
> + MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_Mask = (0x3 << 4),
> + MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_01 = (0x0 << 4),
> + MAX98927_Measurement_DSP_Config_MEAS_V_DCBLK_11 = (0x2 << 4),
> + MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_Mask = (0x3 << 6),
> + MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_01 = (0x0 << 6),
> + MAX98927_Measurement_DSP_Config_MEAS_I_DCBLK_11 = (0x2 << 6),
> +
> + /* Boost Control 0 (Address 0x0040)*/
> + MAX98927_Boost_Control_0 = 0x0040,
> + MAX98927_Boost_Control_0_BST_VOUT_Mask = (0x1f << 0),
> + MAX98927_Boost_Control_0_EXT_PVDD_EN = (0x1 << 7),
> +
> + /* Boost Control 3 (Address 0x0041)*/
> + MAX98927_Boost_Control_3 = 0x0041,
> + MAX98927_Boost_Control_3_BST_SKIPLOAD_Mask = (0x3 << 0),
> + MAX98927_Boost_Control_3_BST_SKIPLOAD_01 = (0x0 << 0),
> + MAX98927_Boost_Control_3_BST_SKIPLOAD_11 = (0x2 << 0),
> + MAX98927_Boost_Control_3_BST_PHASE_Mask = (0x7 << 2),
> + MAX98927_Boost_Control_3_BST_PHASE_001 = (0x0 << 2),
> + MAX98927_Boost_Control_3_BST_PHASE_011 = (0x2 << 2),
> + MAX98927_Boost_Control_3_BST_PHASE_ = (0x1 << 2),
> + MAX98927_Boost_Control_3_BST_SLOWSTART = (0x1 << 5),
> +
> + /* Boost Control 1 (Address 0x0042)*/
> + MAX98927_Boost_Control_1 = 0x0042,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Boost_Control_1_BST_ILIM_Mask = (0x3f << 0),
> +
> + /* Meas ADC Config (Address 0x0043)*/
> + MAX98927_Meas_ADC_Config = 0x0043,
> + MAX98927_Meas_ADC_Config_MEAS_ADC_CH0_EN = (0x1 << 0),
> + MAX98927_Meas_ADC_Config_MEAS_ADC_CH1_EN = (0x1 << 1),
> + MAX98927_Meas_ADC_Config_MEAS_ADC_CH2_EN = (0x1 << 2),
> +
> + /* Meas ADC Base Divide MSByte (Address 0x0044)*/
> + MAX98927_Meas_ADC_Base_Divide_MSByte = 0x0044,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Base_Divide_MSByte_MEAS_ADC_BASE_DIV_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Base Divide LSByte (Address 0x0045)*/
> + MAX98927_Meas_ADC_Base_Divide_LSByte = 0x0045,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Base_Divide_LSByte_MEAS_ADC_BASE_DIV_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Chan 0 Divide (Address 0x0046)*/
> + MAX98927_Meas_ADC_Chan_0_Divide = 0x0046,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_0_Divide_MEAS_ADC_CH0_DIV_Mask = (0xff << 0),
> +
> + /* Meas ADC Chan 1 Divide (Address 0x0047)*/
> + MAX98927_Meas_ADC_Chan_1_Divide = 0x0047,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_1_Divide_MEAS_ADC_CH1_DIV_Mask = (0xff << 0),
> +
> + /* Meas ADC Chan 2 Divide (Address 0x0048)*/
> + MAX98927_Meas_ADC_Chan_2_Divide = 0x0048,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_2_Divide_MEAS_ADC_CH2_DIV_Mask = (0xff << 0),
> +
> + /* Meas ADC Chan 0 Filt Config (Address 0x0049)*/
> + MAX98927_Meas_ADC_Chan_0_Filt_Config = 0x0049,
> + MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_Mask
> + = (0x7 << 0),
> + MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_001
> + = (0x0 << 0),
> + MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_011
> + = (0x2 << 0),
> + MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_AVG_101
> + = (0x4 << 0),
> + MAX98927_Meas_ADC_Chan_0_Filt_Config_MEAS_ADC_CH0_FILT_EN
> + = (0x1 << 3),
> +
> + /* Meas ADC Chan 1 Filt Config (Address 0x004a)*/
> + MAX98927_Meas_ADC_Chan_1_Filt_Config = 0x004a,
> + MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_Mask
> + = (0x7 << 0),
> + MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_001
> + = (0x0 << 0),
> + MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_011
> + = (0x2 << 0),
> + MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_AVG_101
> + = (0x4 << 0),
> + MAX98927_Meas_ADC_Chan_1_Filt_Config_MEAS_ADC_CH1_FILT_EN
> + = (0x1 << 3),
> +
> + /* Meas ADC Chan 2 Filt Config (Address 0x004b)*/
> + MAX98927_Meas_ADC_Chan_2_Filt_Config = 0x004b,
> + MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_Mask
> + = (0x7 << 0),
> + MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_001
> + = (0x0 << 0),
> + MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_011
> + = (0x2 << 0),
> + MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_AVG_101
> + = (0x4 << 0),
> + MAX98927_Meas_ADC_Chan_2_Filt_Config_MEAS_ADC_CH2_FILT_EN
> + = (0x1 << 3),
> +
> + /* Meas ADC Chan 0 Readback (Address 0x004c)*/
> + MAX98927_Meas_ADC_Chan_0_Readback = 0x004c,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_0_Readback_MEAS_ADC_CH0_DATA_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Chan 1 Readback (Address 0x004d)*/
> + MAX98927_Meas_ADC_Chan_1_Readback = 0x004d,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_1_Readback_MEAS_ADC_CH1_DATA_Mask
> + = (0xff << 0),
> +
> + /* Meas ADC Chan 2 Readback (Address 0x004e)*/
> + MAX98927_Meas_ADC_Chan_2_Readback = 0x004e,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Meas_ADC_Chan_2_Readback_MEAS_ADC_CH2_DATA_Mask
> + = (0xff << 0),
> +
> + /* Brownout status (Address 0x0051)*/
> + MAX98927_Brownout_status = 0x0051,
> + MAX98927_Brownout_status_BDE_STATE_Mask = (0xf << 0),
> +
> + /* Brownout enables (Address 0x0052)*/
> + MAX98927_Brownout_enables = 0x0052,
> + MAX98927_Brownout_enables_BDE_EN = (0x1 << 0),
> + MAX98927_Brownout_enables_BDE_AMP_EN = (0x1 << 1),
> + MAX98927_Brownout_enables_AMP_DSP_EN = (0x1 << 2),
> +
> + /* Brownout level infinite hold (Address 0x0053)*/
> + MAX98927_Brownout_level_infinite_hold = 0x0053,
> + MAX98927_Brownout_level_infinite_hold_BDE_L8_INF_HLD = (0x1 << 1),
> +
> + /* Brownout level infinite hold clear (Address 0x0054)*/
> + MAX98927_Brownout_level_infinite_hold_clear = 0x0054,
> + MAX98927_Brownout_level_infinite_hold_clear_BDE_L8_HLD_RLS
> + = (0x1 << 1),
> +
> + /* Brownout level hold (Address 0x0055)*/
> + MAX98927_Brownout_level_hold = 0x0055,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout_level_hold_BDE_HLD_Mask = (0xff << 0),
> +
> + /* Brownout level 1 threshold (Address 0x0056)*/
> + MAX98927_Brownout__level_1_threshold = 0x0056,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_1_threshold_BDE_L1_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 2 threshold (Address 0x0057)*/
> + MAX98927_Brownout__level_2_threshold = 0x0057,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_2_threshold_BDE_L2_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 3 threshold (Address 0x0058)*/
> + MAX98927_Brownout__level_3_threshold = 0x0058,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_3_threshold_BDE_L3_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 4 threshold (Address 0x0059)*/
> + MAX98927_Brownout__level_4_threshold = 0x0059,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_4_threshold_BDE_L4_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 5 threshold (Address 0x005a)*/
> + MAX98927_Brownout__level_5_threshold = 0x005a,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_5_threshold_BDE_L5_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 6 threshold (Address 0x005b)*/
> + MAX98927_Brownout__level_6_threshold = 0x005b,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_6_threshold_BDE_L6_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 7 threshold (Address 0x005c)*/
> + MAX98927_Brownout__level_7_threshold = 0x005c,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_7_threshold_BDE_L7_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout level 8 threshold (Address 0x005d)*/
> + MAX98927_Brownout__level_8_threshold = 0x005d,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_8_threshold_BDE_L8_VTHRESH_Mask = (0xff << 0),
> +
> + /* Brownout threshold hysterysis (Address 0x005e)*/
> + MAX98927_Brownout_threshold_hysterysis = 0x005e,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout_threshold_hysterysis_BDE_VTHRESH_HYST_Mask
> + = (0xff << 0),
> + /* Brownout AMP limiter attack/release (Address 0x005f)*/
> + MAX98927_Brownout_AMP_limiter_attack_release = 0x005f,
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_Mask
> + = (0xf << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0001
> + = (0x0 << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0011
> + = (0x2 << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0101
> + = (0x4 << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_0111
> + = (0x6 << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1001
> + = (0x8 << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1011
> + = (0xa << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1101
> + = (0xc << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_RLS_1111
> + = (0xe << 0),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_Mask
> + = (0xf << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0001
> + = (0x0 << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0011
> + = (0x2 << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0101
> + = (0x4 << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_0111
> + = (0x6 << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1001
> + = (0x8 << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1011
> + = (0xa << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1101
> + = (0xc << 4),
> + MAX98927_Brownout_AMP_limiter_attack_release_AMP_LIM_ATK_1111
> + = (0xe << 4),
> +
> + /* Brownout AMP gain attack/release (Address 0x0060)*/
> + MAX98927_Brownout_AMP_gain_attack_release = 0x0060,
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_Mask
> + = (0xf << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0001
> + = (0x0 << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0011
> + = (0x2 << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0101
> + = (0x4 << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_0111
> + = (0x6 << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1001
> + = (0x8 << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1011
> + = (0xa << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1101
> + = (0xc << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_RLS_1111
> + = (0xe << 0),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_Mask
> + = (0xf << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0001
> + = (0x0 << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0011
> + = (0x2 << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0101
> + = (0x4 << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_0111
> + = (0x6 << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1001
> + = (0x8 << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1011
> + = (0xa << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1101
> + = (0xc << 4),
> + MAX98927_Brownout_AMP_gain_attack_release_AMP_GAIN_ATK_1111
> + = (0xe << 4),
> +
> + /* Brownout AMP1 clip mode (Address 0x0061)*/
> + MAX98927_Brownout_AMP1_clip_mode = 0x0061,
> + MAX98927_Brownout_AMP1_clip_mode_AMP_CLIP_MODE = (0x1 << 0),
> +
> + /* Brownout level 1 current limit (Address 0x0062)*/
> + MAX98927_Brownout__level_1_current_limit = 0x0062,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_1_current_limit_BDE_L1_ILIM_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 1 amp 1 control 1 (Address 0x0063)*/
> + MAX98927_Brownout__level_1_amp_1_control_1 = 0x0063,
> + MAX98927_Brownout__level_1_amp_1_control_1_BDE_L1_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 1 amp 1 control 2 (Address 0x0064)*/
> + MAX98927_Brownout__level_1_amp_1_control_2 = 0x0064,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_1_amp_1_control_2_BDE_L1_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 1 amp 1 control 3 (Address 0x0065)*/
> + MAX98927_Brownout__level_1_amp_1_control_3 = 0x0065,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_1_amp_1_control_3_BDE_L1_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 2 current limit (Address 0x0066)*/
> + MAX98927_Brownout__level_2_current_limit = 0x0066,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_2_current_limit_BDE_L2_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 2 amp 1 control 1 (Address 0x0067)*/
> + MAX98927_Brownout__level_2_amp_1_control_1 = 0x0067,
> + MAX98927_Brownout__level_2_amp_1_control_1_BDE_L2_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 2 amp 1 control 2 (Address 0x0068)*/
> + MAX98927_Brownout__level_2_amp_1_control_2 = 0x0068,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_2_amp_1_control_2_BDE_L2_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 2 amp 1 control 3 (Address 0x0069)*/
> + MAX98927_Brownout__level_2_amp_1_control_3 = 0x0069,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_2_amp_1_control_3_BDE_L2_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 3 current limit (Address 0x006a)*/
> + MAX98927_Brownout__level_3_current_limit = 0x006a,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_3_current_limit_BDE_L3_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 3 amp 1 control 1 (Address 0x006b)*/
> + MAX98927_Brownout__level_3_amp_1_control_1 = 0x006b,
> + MAX98927_Brownout__level_3_amp_1_control_1_BDE_L3_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 3 amp 1 control 2 (Address 0x006c)*/
> + MAX98927_Brownout__level_3_amp_1_control_2 = 0x006c,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_3_amp_1_control_2_BDE_L3_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 3 amp 1 control 3 (Address 0x006d)*/
> + MAX98927_Brownout__level_3_amp_1_control_3 = 0x006d,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_3_amp_1_control_3_BDE_L3_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 4 current limit (Address 0x006e)*/
> + MAX98927_Brownout__level_4_current_limit = 0x006e,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_4_current_limit_BDE_L4_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 4 amp 1 control 1 (Address 0x006f)*/
> + MAX98927_Brownout__level_4_amp_1_control_1 = 0x006f,
> + MAX98927_Brownout__level_4_amp_1_control_1_BDE_L4_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 4 amp 1 control 2 (Address 0x0070)*/
> + MAX98927_Brownout__level_4_amp_1_control_2 = 0x0070,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_4_amp_1_control_2_BDE_L4_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 4 amp 1 control 3 (Address 0x0071)*/
> + MAX98927_Brownout__level_4_amp_1_control_3 = 0x0071,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_4_amp_1_control_3_BDE_L4_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 5 current limit (Address 0x0072)*/
> + MAX98927_Brownout__level_5_current_limit = 0x0072,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_5_current_limit_BDE_L5_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 5 amp 1 control 1 (Address 0x0073)*/
> + MAX98927_Brownout__level_5_amp_1_control_1 = 0x0073,
> + MAX98927_Brownout__level_5_amp_1_control_1_BDE_L5_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 5 amp 1 control 2 (Address 0x0074)*/
> + MAX98927_Brownout__level_5_amp_1_control_2 = 0x0074,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_5_amp_1_control_2_BDE_L5_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 5 amp 1 control 3 (Address 0x0075)*/
> + MAX98927_Brownout__level_5_amp_1_control_3 = 0x0075,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_5_amp_1_control_3_BDE_L5_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 6 current limit (Address 0x0076)*/
> + MAX98927_Brownout__level_6_current_limit = 0x0076,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_6_current_limit_BDE_L6_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 6 amp 1 control 1 (Address 0x0077)*/
> + MAX98927_Brownout__level_6_amp_1_control_1 = 0x0077,
> + MAX98927_Brownout__level_6_amp_1_control_1_BDE_L6_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 6 amp 1 control 2 (Address 0x0078)*/
> + MAX98927_Brownout__level_6_amp_1_control_2 = 0x0078,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_6_amp_1_control_2_BDE_L6_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 6 amp 1 control 3 (Address 0x0079)*/
> + MAX98927_Brownout__level_6_amp_1_control_3 = 0x0079,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_6_amp_1_control_3_BDE_L6_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 7 current limit (Address 0x007a)*/
> + MAX98927_Brownout__level_7_current_limit = 0x007a,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_7_current_limit_BDE_L7_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 7 amp 1 control 1 (Address 0x007b)*/
> + MAX98927_Brownout__level_7_amp_1_control_1 = 0x007b,
> + MAX98927_Brownout__level_7_amp_1_control_1_BDE_L7_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 7 amp 1 control 2 (Address 0x007c)*/
> + MAX98927_Brownout__level_7_amp_1_control_2 = 0x007c,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_7_amp_1_control_2_BDE_L7_AMP1_CLIP_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 7 amp 1 control 3 (Address 0x007d)*/
> + MAX98927_Brownout__level_7_amp_1_control_3 = 0x007d,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_7_amp_1_control_3_BDE_L7_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Brownout level 8 current limit (Address 0x007e)*/
> + MAX98927_Brownout__level_8_current_limit = 0x007e,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_8_current_limit_BDE_L8_ILIM_Mask = (0x3f << 0),
> +
> + /* Brownout level 8 amp 1 control 1 (Address 0x007f)*/
> + MAX98927_Brownout__level_8_amp_1_control_1 = 0x007f,
> + MAX98927_Brownout__level_8_amp_1_control_1_BDE_L8_AMP1_LIM_Mask
> + = (0xf << 0),
> +
> + /* Brownout level 8 amp 1 control 2 (Address 0x0080)*/
> + MAX98927_Brownout__lvl_8_amp_1_control_2 = 0x0080,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__lvl_8_amp_1_control_2_BDE_L8_AMP1_CLIP_Mask
> + = (0x3f << 0),
> + MAX98927_Brownout__lvl_8_amp_1_control_2_BDE_L8_AMP1_MUTE
> + = (0x1 << 7),
> +
> + /* Brownout level 8 amp 1 control 3 (Address 0x0081)*/
> + MAX98927_Brownout__level_8_amp_1_control_3 = 0x0081,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Brownout__level_8_amp_1_control_3_BDE_L8_AMP1_GAIN_Mask
> + = (0x3f << 0),
> +
> + /* Env Tracker Vout Headroom (Address 0x0082)*/
> + MAX98927_Env_Tracker_Vout_Headroom = 0x0082,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Env_Tracker_Vout_Head_ENV_TRACKER_BST_VOUT_HEADROOM_Mask
> + = (0x1f << 0),
> +
> + /* Env Tracker Boost Vout Delay (Address 0x0083)*/
> + MAX98927_Env_Tracker_Boost_Vout_Delay = 0x0083,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Env_Tracker_Boost_V_Delay_ENV_TRACKER_BST_VOUT_DELAY_Mask
> + = (0x1f << 0),
> + MAX98927_Env_Tracker_Boost_Vout_Delay_ENV_TRACKER_BDE_MODE
> + = (0x1 << 7),
> +
> + /* Env Tracker Release Rate (Address 0x0084)*/
> + MAX98927_Env_Tracker_Release_Rate = 0x0084,
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_Mask
> + = (0x7 << 0),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_001
> + = (0x0 << 0),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_011
> + = (0x2 << 0),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_101
> + = (0x4 << 0),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_111
> + = (0x6 << 0),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_PEAK_DET_LPF_BYP_EN
> + = (0x1 << 3),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_Mask
> + = (0x3 << 4),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_01
> + = (0x0 << 4),
> + MAX98927_Env_Tracker_Release_Rate_ENV_TRACKER_RLS_RATE_SCALE_11
> + = (0x2 << 4),
> +
> + /* Env Tracker Hold Rate (Address 0x0085)*/
> + MAX98927_Env_Tracker_Hold_Rate = 0x0085,
> + MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_Mask
> + = (0x7 << 0),
> + MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_001
> + = (0x0 << 0),
> + MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_011
> + = (0x2 << 0),
> + MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_101
> + = (0x4 << 0),
> + MAX98927_Env_Tracker_Hold_Rate_ENV_TRACKER_HOLD_RATE_111
> + = (0x6 << 0),
> +
> + /* Env Tracker Control (Address 0x0086)*/
> + MAX98927_Env_Tracker_Control = 0x0086,
> + MAX98927_Env_Tracker_Control_ENV_TRACKER_EN = (0x1 << 0),
> +
> + /* Env Tracker Boost Vout ReadBack (Address 0x0087)*/
> + MAX98927_Env_Tracker__Boost_Vout_ReadBack = 0x0087,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Env_Tracker__Boost_Vout_RB_ENV_TRACKER_BST_VOUT_RD_Mask
> + = (0x1f << 0),
> +
> + /* Advanced Settings (Address 0x0089)*/
> + MAX98927_Advanced_Settings = 0x0089,
> + MAX98927_Advanced_Settings_DAC_HALF_FIR = (0x1 << 0),
> + MAX98927_Advanced_Settings_PDM_MOD_SEL = (0x1 << 1),
> + MAX98927_Advanced_Settings_ISOCH_EN = (0x1 << 2),
> +
> + /* DAC Test 1 (Address 0x009f)*/
> + MAX98927_DAC_Test_1 = 0x009f,
> + MAX98927_DAC_Test_1_DAC_PCM_TIMING = (0x1 << 0),
> + MAX98927_DAC_Test_1_DAC_HALFI_AMP = (0x1 << 1),
> + MAX98927_DAC_Test_1_DAC_LONG_HOLD = (0x1 << 3),
> + MAX98927_DAC_Test_1_DAC_DISABLE_CHOP = (0x1 << 4),
> + MAX98927_DAC_Test_1_DAC_TM = (0x1 << 5),
> + MAX98927_DAC_Test_1_DAC_INVERT_DACCLK = (0x1 << 6),
> +
> + /* Authentication key 0 (Address 0x00ea)*/
> + MAX98927_Authentication_key_0 = 0x00ea,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_key_0_AUTH_KEY_Mask = (0xff << 0),
> +
> + /* Authentication key 1 (Address 0x00eb)*/
> + MAX98927_Authentication_key_1 = 0x00eb,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_key_1_AUTH_KEY_Mask = (0xff << 0),
> +
> + /* Authentication key 2 (Address 0x00ec)*/
> + MAX98927_Authentication_key_2 = 0x00ec,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_key_2_AUTH_KEY_Mask = (0xff << 0),
> +
> + /* Authentication key 3 (Address 0x00ed)*/
> + MAX98927_Authentication_key_3 = 0x00ed,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_key_3_AUTH_KEY_Mask = (0xff << 0),
> +
> + /* Authentication enable (Address 0x00ee)*/
> + MAX98927_Authentication_enable = 0x00ee,
> + MAX98927_Authentication_enable_AUTH_EN = (0x1 << 0),
> +
> + /* Authentication result 0 (Address 0x00ef)*/
> + MAX98927_Authentication_result_0 = 0x00ef,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_0_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 1 (Address 0x00f0)*/
> + MAX98927_Authentication_result_1 = 0x00f0,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_1_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 2 (Address 0x00f1)*/
> + MAX98927_Authentication_result_2 = 0x00f1,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_2_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 3 (Address 0x00f2)*/
> + MAX98927_Authentication_result_3 = 0x00f2,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_3_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 4 (Address 0x00f3)*/
> + MAX98927_Authentication_result_4 = 0x00f3,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_4_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 5 (Address 0x00f4)*/
> + MAX98927_Authentication_result_5 = 0x00f4,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_5_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 6 (Address 0x00f5)*/
> + MAX98927_Authentication_result_6 = 0x00f5,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_6_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 7 (Address 0x00f6)*/
> + MAX98927_Authentication_result_7 = 0x00f6,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_7_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 8 (Address 0x00f7)*/
> + MAX98927_Authentication_result_8 = 0x00f7,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_8_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 9 (Address 0x00f8)*/
> + MAX98927_Authentication_result_9 = 0x00f8,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_9_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 10 (Address 0x00f9)*/
> + MAX98927_Authentication_result_10 = 0x00f9,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_10_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 11 (Address 0x00fa)*/
> + MAX98927_Authentication_result_11 = 0x00fa,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_11_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 12 (Address 0x00fb)*/
> + MAX98927_Authentication_result_12 = 0x00fb,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_12_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 13 (Address 0x00fc)*/
> + MAX98927_Authentication_result_13 = 0x00fc,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_13_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 14 (Address 0x00fd)*/
> + MAX98927_Authentication_result_14 = 0x00fd,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_14_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Authentication result 15 (Address 0x00fe)*/
> + MAX98927_Authentication_result_15 = 0x00fe,
> + /*#BYHAND width >= 5:*/
> + MAX98927_Authentication_result_15_AUTH_RESULT_Mask = (0xff << 0),
> +
> + /* Global Enable (Address 0x00ff)*/
> + MAX98927_Global_Enable = 0x00ff,
> + MAX98927_Global_Enable_EN = (0x1 << 0),
> + /* Software Reset (Address 0x0100)*/
> + MAX98927_Software_Reset = 0x0100,
> + MAX98927_Software_Reset_RST = (0x1 << 0),
> +
> + /* REV ID (Address 0x01ff)*/
> + MAX98927_REV_ID = 0x01ff,
> + /*#BYHAND width >= 5:*/
> + MAX98927_REV_ID_REV_ID_Mask = (0xff << 0),
> +} MAX98927Registers;
> +
> +struct max98927_reg_default {
> + unsigned int ch;
> + unsigned int reg;
> + unsigned int def;
> +};
> +struct max98927_priv {
> + struct regmap *regmap;
> + struct regmap *sub_regmap;
> + struct snd_soc_codec *codec;
> + struct max98927_pdata *pdata;
> + const uint32_t *regcfg;
> + uint32_t regcfg_sz;
> + unsigned int spk_gain;
> + unsigned int sysclk;
> + unsigned int v_l_slot;
> + unsigned int i_l_slot;
> + unsigned int v_r_slot;
> + unsigned int i_r_slot;
> + bool interleave_mode;
> + unsigned int ch_size;
> + unsigned int rate;
> + unsigned int iface;
> + unsigned int master;
> + unsigned int thres_hyste;
> + unsigned int level5_hold;
> + unsigned int level6_hold;
> + unsigned int level7_hold;
> + unsigned int level8_hold;
> + unsigned int amp_limit;
> + unsigned int amp_limit_rel;
> + unsigned int amp1_level;
> + unsigned int amp2_level;
> + unsigned int amp3_level;
> + unsigned int amp1_level8;
> + unsigned int amp2_level8;
> + unsigned int amp3_level8;
> + unsigned int amp1_level7;
> + unsigned int amp2_level7;
> + unsigned int amp3_level7;
> + unsigned int amp1_level6;
> + unsigned int amp2_level6;
> + unsigned int amp3_level6;
> + unsigned int amp1_level5;
> + unsigned int amp2_level5;
> + unsigned int amp3_level5;
> + unsigned int digital_gain;
> + unsigned int pdm_gain;
> + unsigned int level_hold;
> + struct i2c_client *sub_i2c;
> + int sub_reg;
> + int sub_bus;
> +};
> +
> +#define MAX98927_GLOBAL_SHIFT 0
> +#define M98927_DAI_MSEL_SHIFT 4
> +#define M98927_DAI_BSEL_SHIFT 0
> +#define M98927_DAI_BSEL_32 (2 << M98927_DAI_BSEL_SHIFT)
> +#define M98927_DAI_BSEL_48 (3 << M98927_DAI_BSEL_SHIFT)
> +#define M98927_DAI_BSEL_64 (4 << M98927_DAI_BSEL_SHIFT)
> +#define M98927_DAI_MSEL_32 (2 << M98927_DAI_MSEL_SHIFT)
> +#define M98927_DAI_MSEL_48 (3 << M98927_DAI_MSEL_SHIFT)
> +#define M98927_DAI_MSEL_64 (4 << M98927_DAI_MSEL_SHIFT)
> +#define MAX98927_Speaker_Gain_Width 3
> +#define MAX98927_SPK_RMP_EN_SHIFT 4
> +#define MAX98927_PDM_GAIN_SHIFT 4
> +#define MAX98927_pdm_Gain_Width 3
> +#define MAX98927_AMP_VOL_WIDTH 7
> +#define MAX98927_AMP_VOL_LOCATION_SHIFT 7
> +#define MAX98927_PDM_Rx_Enable_PDM_CH_SHIFT 3
> +#define MAX98927_PCM_to_speaker_monomix_A_SHIFT 6
> +#define MAX98927_PCM_Sample_rate_setup_2_DIG_IF_SR_48000 (0x8 << 4)
> +#define MAX98927_PCM_FORMAT_DSP_A (0x3 << 3)
> +#define MAX98927_DRE_Control_DRE_SHIFT 0x1
> +#define MAX98927_PCM_Master_Mode_PCM_MCLK_RATE_SHIFT (2)
> +#define MAX98927_Brownout_AMP_limiter_attack_release_shift 4
> +#define MAX98927_BDE_DSP_SHIFT 2
> +#define MAX98927_Speaker_Gain_SPK_PDM_GAIN_SHIFT (4)
> +#define MAX98927_BDE_AMP_SHIFT (1)
> +#define MAX98927_PCM_Tx_Ch_Sources_A_I_SHIFT (4)
> +#endif
> --
> 1.9.1
>
--
| Michael Nazzareno Trimarchi Amarula Solutions BV |
| COO - Founder Cruquiuskade 47 |
| +31(0)851119172 Amsterdam 1018 AM NL |
| [`as] http://www.amarulasolutions.com |
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [alsa-devel] [PATCH v2] clkdev: add devm_of_clk_get()
From: Stephen Boyd @ 2016-11-23 19:10 UTC (permalink / raw)
To: Kuninori Morimoto
Cc: Michael Turquette, Rob Herring, Russell King, Mark Brown,
Linux-ALSA, Linux-DT, Linux-Kernel, linux-clk, Linux-ARM
In-Reply-To: <8737isvwc6.wl%kuninori.morimoto.gx@renesas.com>
On 11/16, Kuninori Morimoto wrote:
>
> Hi Rob, Michael, Russell
>
>
> What is the conclusion of this patch ?
> We shouldn't add devm_of_clk_get() ? or can I continue ?
>
> The problem of current [devm_]clk_get() handles *dev only,
> but I need to get clocks from DT node, not dev
>
> sound_soc {
> ...
> cpu {
> ...
> => clocks = <&xxx>;
> };
> codec {
> ...
> => clocks = <&xxx>;
> };
> };
>
I've seen bindings that have the 'clocks' property at the top
level and the appropriate 'clock-names' property to relate the
clocks to a subnode.
sound_soc {
clocks = <&xxx>, <&xxx>;
clock-names = "cpu", "codec";
...
cpu {
...
};
codec {
...
};
};
Then the subnodes call clk_get() with the top level device and
the name of their node and things match up. I suppose this
binding is finalized though, so we can't really do that?
I see that the gpio framework has a similar design called
devm_get_gpiod_from_child(), so how about we add a
devm_get_clk_from_child() API? That would more closely match the
intent here, which is to restrict the clk_get() operation to
child nodes of the device passed as the first argument.
struct clk *devm_get_clk_from_child(struct device *dev,
const char *con_id,
struct device_node *child);
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* [PATCH] drivers/of: Export phandle iterators
From: Robin Murphy @ 2016-11-23 19:06 UTC (permalink / raw)
To: devicetree, linux-kernel; +Cc: Rob Herring, Frank Rowand
Modular drivers may want to use of_for_each_phandle() - export its
constituent functions.
CC: Rob Herring <robh+dt@kernel.org>
CC: Frank Rowand <frowand.list@gmail.com>
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
---
drivers/of/base.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/of/base.c b/drivers/of/base.c
index a0bccb54a9bd..92e35fe0189a 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -1563,6 +1563,7 @@ int of_phandle_iterator_init(struct of_phandle_iterator *it,
return 0;
}
+EXPORT_SYMBOL_GPL(of_phandle_iterator_init);
int of_phandle_iterator_next(struct of_phandle_iterator *it)
{
@@ -1632,6 +1633,7 @@ int of_phandle_iterator_next(struct of_phandle_iterator *it)
return -EINVAL;
}
+EXPORT_SYMBOL_GPL(of_phandle_iterator_next);
int of_phandle_iterator_args(struct of_phandle_iterator *it,
uint32_t *args,
@@ -1649,6 +1651,7 @@ int of_phandle_iterator_args(struct of_phandle_iterator *it,
return count;
}
+EXPORT_SYMBOL_GPL(of_phandle_iterator_args);
static int __of_parse_phandle_with_args(const struct device_node *np,
const char *list_name,
--
2.10.2.dirty
^ permalink raw reply related
* Re: [PATCH v9 02/16] clk: qcom: Move all sdcc rcgs to use clk_rcg2_floor_ops
From: Stephen Boyd @ 2016-11-23 19:00 UTC (permalink / raw)
To: Ritesh Harjani
Cc: ulf.hansson, linux-mmc, adrian.hunter, andy.gross, shawn.lin,
devicetree, linux-clk, david.brown, linux-arm-msm, georgi.djakov,
alex.lemberg, mateusz.nowak, Yuliy.Izrailov, asutoshd,
david.griego, stummala, venkatg, rnayak, pramod.gurav, jeremymc
In-Reply-To: <1479710246-26676-3-git-send-email-riteshh@codeaurora.org>
On 11/21, Ritesh Harjani wrote:
> From: Rajendra Nayak <rnayak@codeaurora.org>
>
> The sdcc driver for msm8996/msm8916/msm8974/msm8994 and apq8084
> expects a clk_set_rate() on the sdcc rcg clk to set
> a floor value of supported clk rate closest to the requested
> rate, by looking up the frequency table.
> So move all the sdcc rcgs on all these platforms to use the
> newly introduced clk_rcg2_floor_ops
>
> Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
> Signed-off-by: Ritesh Harjani <riteshh@codeaurora.org>
> Signed-off-by: Jeremy McNicoll <jeremymc@redhat.com>
> ---
Applied to clk-next
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH v9 01/16] clk: qcom: Add rcg ops to return floor value closest to the requested rate
From: Stephen Boyd @ 2016-11-23 19:00 UTC (permalink / raw)
To: Ritesh Harjani
Cc: ulf.hansson-QSEj5FYQhm4dnm+yROfE0A,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
adrian.hunter-ral2JQCrhuEAvxtiuMwx3w,
andy.gross-QSEj5FYQhm4dnm+yROfE0A,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
david.brown-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
georgi.djakov-QSEj5FYQhm4dnm+yROfE0A,
alex.lemberg-XdAiOPVOjttBDgjK7y7TUQ,
mateusz.nowak-ral2JQCrhuEAvxtiuMwx3w,
Yuliy.Izrailov-XdAiOPVOjttBDgjK7y7TUQ,
asutoshd-sgV2jX0FEOL9JmXXK+q4OQ,
david.griego-QSEj5FYQhm4dnm+yROfE0A,
stummala-sgV2jX0FEOL9JmXXK+q4OQ, venkatg-sgV2jX0FEOL9JmXXK+q4OQ,
rnayak-sgV2jX0FEOL9JmXXK+q4OQ,
pramod.gurav-QSEj5FYQhm4dnm+yROfE0A,
jeremymc-H+wXaHxf7aLQT0dZR+AlfA
In-Reply-To: <1479710246-26676-2-git-send-email-riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On 11/21, Ritesh Harjani wrote:
> From: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
>
> The default behaviour with clk_rcg2_ops is for the
> clk_round_rate()/clk_set_rate() to return/set a ceil clock
> rate closest to the requested rate by looking up the corresponding
> frequency table.
> However, we do have some instances (mainly sdcc on various platforms)
> of clients expecting a clk_set_rate() to set a floor value instead.
> Add a new clk_rcg2_floor_ops to handle this for such specific
> rcg instances
>
> Signed-off-by: Rajendra Nayak <rnayak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> Signed-off-by: Ritesh Harjani <riteshh-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
Applied to clk-next
--
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^ permalink raw reply
* Re: [PATCH] ALSA SoC MAX98927 driver - Initial release
From: kbuild test robot @ 2016-11-23 18:56 UTC (permalink / raw)
To: Ryan Lee
Cc: kbuild-all-JC7UmRfGjtg, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
arnd-r2nGTMty4D4, michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
oder_chiou-Rasf1IRRPZFBDgjK7y7TUQ,
yesanishhere-Re5JQEeQqe8AvxtiuMwx3w,
jacob-EZCvousvhKUZux3j3Bed6dkegs52MxvZ,
Damien.Horsley-1AXoQHu6uovQT0dZR+AlfA,
bardliao-Rasf1IRRPZFBDgjK7y7TUQ,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
petr-Qh/3xLP0EvwAvxtiuMwx3w, lars-Qo5EllUWu/uELgA04lAiVw,
nh6z-fFIq/eER6g8, ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479877026-5172-1-git-send-email-RyanS.Lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 3732 bytes --]
Hi Ryan,
[auto build test WARNING on asoc/for-next]
[also build test WARNING on v4.9-rc6 next-20161123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ryan-Lee/ALSA-SoC-MAX98927-driver-Initial-release/20161124-004840
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
config: tile-allyesconfig (attached as .config)
compiler: tilegx-linux-gcc (GCC) 4.6.2
reproduce:
wget https://git.kernel.org/cgit/linux/kernel/git/wfg/lkp-tests.git/plain/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=tile
All warnings (new ones prefixed by >>):
sound/soc/codecs/max98927.c:755:2: error: unknown field 'dapm_routes' specified in initializer
>> sound/soc/codecs/max98927.c:755:2: warning: initialization from incompatible pointer type [enabled by default]
sound/soc/codecs/max98927.c:755:2: warning: (near initialization for 'soc_codec_dev_max98927.remove') [enabled by default]
sound/soc/codecs/max98927.c:756:2: error: unknown field 'num_dapm_routes' specified in initializer
>> sound/soc/codecs/max98927.c:756:21: warning: initialization makes pointer from integer without a cast [enabled by default]
sound/soc/codecs/max98927.c:756:21: warning: (near initialization for 'soc_codec_dev_max98927.suspend') [enabled by default]
sound/soc/codecs/max98927.c:757:2: error: unknown field 'dapm_widgets' specified in initializer
sound/soc/codecs/max98927.c:757:2: warning: initialization from incompatible pointer type [enabled by default]
sound/soc/codecs/max98927.c:757:2: warning: (near initialization for 'soc_codec_dev_max98927.resume') [enabled by default]
sound/soc/codecs/max98927.c:758:2: error: unknown field 'num_dapm_widgets' specified in initializer
sound/soc/codecs/max98927.c:758:22: warning: missing braces around initializer [-Wmissing-braces]
sound/soc/codecs/max98927.c:758:22: warning: (near initialization for 'soc_codec_dev_max98927.component_driver') [-Wmissing-braces]
sound/soc/codecs/max98927.c:758:22: warning: initialization makes pointer from integer without a cast [enabled by default]
sound/soc/codecs/max98927.c:758:22: warning: (near initialization for 'soc_codec_dev_max98927.component_driver.name') [enabled by default]
sound/soc/codecs/max98927.c:759:2: error: unknown field 'controls' specified in initializer
sound/soc/codecs/max98927.c:759:2: warning: initialization from incompatible pointer type [enabled by default]
sound/soc/codecs/max98927.c:759:2: warning: (near initialization for 'soc_codec_dev_max98927.set_sysclk') [enabled by default]
sound/soc/codecs/max98927.c:760:2: error: unknown field 'num_controls' specified in initializer
sound/soc/codecs/max98927.c:760:18: warning: initialization makes pointer from integer without a cast [enabled by default]
sound/soc/codecs/max98927.c:760:18: warning: (near initialization for 'soc_codec_dev_max98927.set_pll') [enabled by default]
vim +755 sound/soc/codecs/max98927.c
749
750 return ret;
751 }
752
753 static const struct snd_soc_codec_driver soc_codec_dev_max98927 = {
754 .probe = max98927_probe,
> 755 .dapm_routes = max98927_audio_map,
> 756 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
757 .dapm_widgets = max98927_dapm_widgets,
758 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
759 .controls = max98927_snd_controls,
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 46522 bytes --]
^ permalink raw reply
* [PATCH v4 2/2] DW DMAC: add multi-block property to device tree
From: Eugeniy Paltsev @ 2016-11-23 18:37 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, linux-snps-arc, arnd, vinod.koul, linux-kernel,
robh+dt, dmaengine, andriy.shevchenko, Eugeniy Paltsev
In-Reply-To: <1479926268-29050-1-git-send-email-Eugeniy.Paltsev@synopsys.com>
Several versions of DW DMAC have multi block transfers hardware
support. Hardware support of multi block transfers is disabled
by default if we use DT to configure DMAC and software emulation
of multi block transfers used instead.
Add multi-block property, so it is possible to enable hardware
multi block transfers (if present) via DT.
Switch from per device is_nollp variable to multi_block array
to be able enable/disable multi block transfers separately per
channel.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
Also:
Update DT documentation.
Update existing platform data.
Documentation/devicetree/bindings/dma/snps-dma.txt | 3 +++
drivers/dma/dw/core.c | 2 +-
drivers/dma/dw/platform.c | 5 +++++
drivers/tty/serial/8250/8250_lpss.c | 2 +-
include/linux/platform_data/dma-dw.h | 4 ++--
5 files changed, 12 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/snps-dma.txt b/Documentation/devicetree/bindings/dma/snps-dma.txt
index 0f55832..0c6256d 100644
--- a/Documentation/devicetree/bindings/dma/snps-dma.txt
+++ b/Documentation/devicetree/bindings/dma/snps-dma.txt
@@ -27,6 +27,9 @@ Optional properties:
that services interrupts for this device
- is_private: The device channels should be marked as private and not for by the
general purpose DMA channel allocator. False if not passed.
+- multi-block: Multi block transfers supported by hardware per AHB master.
+ Array property with one cell per master. 0 (default): not supported,
+ 1: supported.
Example:
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index c2c0a61..e5adf5d 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -1569,7 +1569,7 @@ int dw_dma_probe(struct dw_dma_chip *chip)
(dwc_params >> DWC_PARAMS_MBLK_EN & 0x1) == 0;
} else {
dwc->block_size = pdata->block_size;
- dwc->nollp = pdata->is_nollp;
+ dwc->nollp = !pdata->multi_block[i];
}
}
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index aa7a5c1..b262fd3 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -152,6 +152,11 @@ dw_dma_parse_dt(struct platform_device *pdev)
pdata->data_width[tmp] = BIT(arr[tmp] & 0x07);
}
+ if (!of_property_read_u32_array(np, "multi-block", arr, nr_masters)) {
+ for (tmp = 0; tmp < nr_masters; tmp++)
+ pdata->multi_block[tmp] = arr[tmp];
+ }
+
return pdata;
}
#else
diff --git a/drivers/tty/serial/8250/8250_lpss.c b/drivers/tty/serial/8250/8250_lpss.c
index f607946..58cbb30 100644
--- a/drivers/tty/serial/8250/8250_lpss.c
+++ b/drivers/tty/serial/8250/8250_lpss.c
@@ -157,12 +157,12 @@ static int byt_serial_setup(struct lpss8250 *lpss, struct uart_port *port)
static const struct dw_dma_platform_data qrk_serial_dma_pdata = {
.nr_channels = 2,
.is_private = true,
- .is_nollp = true,
.chan_allocation_order = CHAN_ALLOCATION_ASCENDING,
.chan_priority = CHAN_PRIORITY_ASCENDING,
.block_size = 4095,
.nr_masters = 1,
.data_width = {4},
+ .multi_block = {0},
};
static void qrk_serial_setup_dma(struct lpss8250 *lpss, struct uart_port *port)
diff --git a/include/linux/platform_data/dma-dw.h b/include/linux/platform_data/dma-dw.h
index 5f0e11e..0773bb4 100644
--- a/include/linux/platform_data/dma-dw.h
+++ b/include/linux/platform_data/dma-dw.h
@@ -40,19 +40,18 @@ struct dw_dma_slave {
* @is_private: The device channels should be marked as private and not for
* by the general purpose DMA channel allocator.
* @is_memcpy: The device channels do support memory-to-memory transfers.
- * @is_nollp: The device channels does not support multi block transfers.
* @chan_allocation_order: Allocate channels starting from 0 or 7
* @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
* @block_size: Maximum block size supported by the controller
* @nr_masters: Number of AHB masters supported by the controller
* @data_width: Maximum data width supported by hardware per AHB master
* (in bytes, power of 2)
+ * @multi_block: Multi block transfers supported by hardware per AHB master.
*/
struct dw_dma_platform_data {
unsigned int nr_channels;
bool is_private;
bool is_memcpy;
- bool is_nollp;
#define CHAN_ALLOCATION_ASCENDING 0 /* zero to seven */
#define CHAN_ALLOCATION_DESCENDING 1 /* seven to zero */
unsigned char chan_allocation_order;
@@ -62,6 +61,7 @@ struct dw_dma_platform_data {
unsigned int block_size;
unsigned char nr_masters;
unsigned char data_width[DW_DMA_MAX_NR_MASTERS];
+ unsigned char multi_block[DW_DMA_MAX_NR_MASTERS];
};
#endif /* _PLATFORM_DATA_DMA_DW_H */
--
2.5.5
^ permalink raw reply related
* [PATCH v4 1/2] DW DMAC: enable memory-to-memory transfers support
From: Eugeniy Paltsev @ 2016-11-23 18:37 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA,
vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
linux-snps-arc-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Eugeniy Paltsev
In-Reply-To: <1479926268-29050-1-git-send-email-Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
All known devices, which use DT for configuration, support
memory-to-memory transfers. So enable it by default, if we read
configuration from DT.
Acked-by: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev-HKixBCOQz3hWk0Htik3J/w@public.gmane.org>
---
drivers/dma/dw/platform.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/dma/dw/platform.c b/drivers/dma/dw/platform.c
index 5bda0eb..aa7a5c1 100644
--- a/drivers/dma/dw/platform.c
+++ b/drivers/dma/dw/platform.c
@@ -129,6 +129,12 @@ dw_dma_parse_dt(struct platform_device *pdev)
if (of_property_read_bool(np, "is_private"))
pdata->is_private = true;
+ /*
+ * All known devices, which use DT for configuration, support
+ * memory-to-memory transfers. So enable it by default.
+ */
+ pdata->is_memcpy = true;
+
if (!of_property_read_u32(np, "chan_allocation_order", &tmp))
pdata->chan_allocation_order = (unsigned char)tmp;
--
2.5.5
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^ permalink raw reply related
* [PATCH v4 0/2] DW DMAC: update device tree
From: Eugeniy Paltsev @ 2016-11-23 18:37 UTC (permalink / raw)
To: devicetree
Cc: mark.rutland, linux-snps-arc, arnd, vinod.koul, linux-kernel,
robh+dt, dmaengine, andriy.shevchenko, Eugeniy Paltsev
It wasn't possible to enable some features like
memory-to-memory transfers or multi block transfers via DT.
It is fixed by these patches.
Changes for v4:
* Fix setting inverted value to "dwc->nollp". My fault - I
tested with wrong DTS, so DMAC was configured from autoconfig
instead of device tree. Pointed by Andy Shevchenko.
* Update "multi-block" diescription in documentation to be more
clear. Pointed by Arnd Bergmann.
Changes for v3:
* Update existing platform data.
We don't need to update existing DTS because default logic
wasn't change: we don't set "is_nollp" if we read
configuration from DT before. And we don't set it now if
"multi-block" property doesn't exist in DTS.
Changes for v2:
* I thought about is_memcpy DT property: all known devices, which
use DT for configuration, support memory-to-memory transfers.
So we don't need to read it from DT. So enable it by default,
if we read configuration from DT.
* Use "multi-block" instead of "hw-llp" name to be more clear.
* Move adding DT property and adding documentation for this
property to one patch.
Eugeniy Paltsev (2):
DW DMAC: enable memory-to-memory transfers support
DW DMAC: add multi-block property to device tree
Documentation/devicetree/bindings/dma/snps-dma.txt | 3 +++
drivers/dma/dw/core.c | 2 +-
drivers/dma/dw/platform.c | 11 +++++++++++
drivers/tty/serial/8250/8250_lpss.c | 2 +-
include/linux/platform_data/dma-dw.h | 4 ++--
5 files changed, 18 insertions(+), 4 deletions(-)
--
2.5.5
^ permalink raw reply
* Re: [PATCH RFC] ARM: dts: add support for Turris Omnia
From: Uwe Kleine-König @ 2016-11-23 18:36 UTC (permalink / raw)
To: Andrew Lunn, tomas.hlavacek-x+rMaJPWets
Cc: Mark Rutland, marex-ynQEQJNshbs, Jason Cooper,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Gregory Clement,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
In-Reply-To: <20161123145916.GL14947-g2DYL2Zd6BY@public.gmane.org>
[-- Attachment #1.1: Type: text/plain, Size: 964 bytes --]
Hello Andrew,
On 11/23/2016 03:59 PM, Andrew Lunn wrote:
>>> CZ11NIC12 is indicated on my board.
>>
>> :-( Well, this board version has wrongly matched length of some
>> differential pairs, IRQ from 88E1514 is connected differently, there
>> are slight differences in power supplies and (if I am not mistaken)
>> something changed in RTC support circuitry. It looks like a huge
>> mistake on our side.
>
> Hi Tomas
>
> Would these problems also explain why the Ethernet links to the switch
> don't work? Maybe the differential pairs?
no this is not the problem. When booting the OpenWRT based system I can
communicate with the device via the switch. (Didn't test deeply, but my
Laptop got a dhcp lease from the Turris Omnia and I can ping it.) But
this convinces me, that the hardware is good enough.
If you have any ideas what I can try to make the switch work or help to
diagnose the problem, just let me know.
Best regards
Uwe
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 488 bytes --]
^ permalink raw reply
* Re: [PATCH 6/6] pinctrl: mt8173: set GPIO16 to usb iddig mode
From: Matthias Brugger @ 2016-11-23 18:32 UTC (permalink / raw)
To: Hongzhou Yang, chunfeng yun
Cc: Linus Walleij, Maoguang Meng, Yingjoe Chen, Greg Kroah-Hartman,
Felipe Balbi, Mathias Nyman, Alan Stern, Rob Herring,
Mark Rutland, Ian Campbell, Sergei Shtylyov, Pawel Moll,
Kumar Gala, Sascha Hauer, Biao Huang, linux-usb@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel
In-Reply-To: <1463021701.25171.5.camel@mussux00>
Hi Hongzhou,
On 12/05/16 04:55, Hongzhou Yang wrote:
> On Wed, 2016-05-11 at 19:09 -0700, Hongzhou Yang wrote:
>> On Thu, 2016-05-12 at 09:41 +0800, chunfeng yun wrote:
>>> Hi,
>>>
>>> On Wed, 2016-05-11 at 11:32 -0700, Hongzhou Yang wrote:
>>>> On Wed, 2016-05-11 at 13:56 +0200, Linus Walleij wrote:
>>>>> On Tue, May 10, 2016 at 10:23 AM, Chunfeng Yun
>>>>> <chunfeng.yun@mediatek.com> wrote:
>>>>>
>>>>>> the default mode of GPIO16 pin is gpio, when set EINT16 to
>>>>>> IRQ_TYPE_LEVEL_HIGH, no interrupt is triggered, it can be
>>>>>> fixed when set its default mode as usb iddig.
>>>>>>
>>>>>> Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
>>>>>
>>>>
>>>> Chunfeng, GPIO16 can be used as EINT16 mode, but the pinmux should be 0.
>>>> If you want to set its default mode to iddig, you should set it in dts.
>>>>
>>> I set it in DTS, but it didn't work, because when usb driver requested
>>> IRQ, pinmux was switched back to default mode set by
>>> MTK_EINT_FUNCTION().
>>>
>>
>> After confirmed, there are something wrong with data sheet and pinmux
>> table, and GPIO16 can only receive interrupt by mode 1. So
>>
>> Acked-by: Hongzhou Yang <hongzhou.yang@mediatek.com>
>>
>
> Linus,
>
> We find there are some other pins still have the same problem, so please
> hold on it. Sorry for so much noise.
>
Did you made any progress on this? I didn't see any patch on the mailing
list.
Regards,
Matthias
^ permalink raw reply
* Re: [PATCH v2 1/5] ARM: memory: da8xx-ddrctl: new driver
From: Frank Rowand @ 2016-11-23 18:23 UTC (permalink / raw)
To: Sekhar Nori, Bartosz Golaszewski, Kevin Hilman, Michael Turquette,
Rob Herring, Mark Rutland, Peter Ujfalusi, Russell King
Cc: LKML, arm-soc, linux-drm, linux-devicetree, Jyri Sarha,
Tomi Valkeinen, David Airlie, Laurent Pinchart, Sudeep Holla
In-Reply-To: <5835DC2D.5080606-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On 11/23/16 10:13, Frank Rowand wrote:
> On 11/22/16 21:55, Sekhar Nori wrote:
>> On Tuesday 22 November 2016 11:51 PM, Frank Rowand wrote:
>>> Please note that the compatible property might contain several strings, not just
>>> a single string.
>>
>> So I guess the best thing to do is to use
>> of_property_read_string_index() and print the sting at index 0.
>>
>> Thanks,
>> Sekhar
>
> If you want to print just one compatible value, you could use that method.
>
> To give all of the information needed to understand the problem, the error
> message would need to include all of the strings contained in the compatible
> property and all of the .board values in the da8xx_ddrctl_board_confs[] array
> (currently only one entry, but coded to allow additional entries in the
> future).
>
> It is hard to justify an error message that complex.
>
> I would just print an error that no match was found.
>
> -Frank
I just needed to read some more emails. I see this approach was taken
in the "[PATCH v4 0/2] da8xx: fix section mismatch in new drivers"
series.
-Frank
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^ permalink raw reply
* [PATCH] fix platform_no_drv_owner.cocci warnings
From: kbuild test robot @ 2016-11-23 18:13 UTC (permalink / raw)
To: Ryan Lee
Cc: kbuild-all, lgirdwood, broonie, robh+dt, mark.rutland, perex,
tiwai, arnd, michael, oder_chiou, yesanishhere, jacob,
Damien.Horsley, bardliao, kuninori.morimoto.gx, petr, lars, nh6z,
ryans.lee, alsa-devel, devicetree, linux-kernel
In-Reply-To: <1479877026-5172-1-git-send-email-RyanS.Lee@maximintegrated.com>
sound/soc/codecs/max98927.c:941:3-8: No need to set .owner here. The core will do it.
Remove .owner field if calls are used which set it automatically
Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci
CC: Ryan Lee <RyanS.Lee@maximintegrated.com>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
---
max98927.c | 1 -
1 file changed, 1 deletion(-)
--- a/sound/soc/codecs/max98927.c
+++ b/sound/soc/codecs/max98927.c
@@ -938,7 +938,6 @@ MODULE_DEVICE_TABLE(of, max98927_of_matc
static struct i2c_driver max98927_i2c_driver = {
.driver = {
.name = "max98927",
- .owner = THIS_MODULE,
.of_match_table = of_match_ptr(max98927_of_match),
.pm = NULL,
},
^ permalink raw reply
* Re: [PATCH] ALSA SoC MAX98927 driver - Initial release
From: kbuild test robot @ 2016-11-23 18:13 UTC (permalink / raw)
To: Ryan Lee
Cc: kbuild-all-JC7UmRfGjtg, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, perex-/Fr2/VpizcU, tiwai-IBi9RG/b67k,
arnd-r2nGTMty4D4, michael-dyjBcgdgk7Pe9wHmmfpqLFaTQe2KTcn/,
oder_chiou-Rasf1IRRPZFBDgjK7y7TUQ,
yesanishhere-Re5JQEeQqe8AvxtiuMwx3w,
jacob-EZCvousvhKUZux3j3Bed6dkegs52MxvZ,
Damien.Horsley-1AXoQHu6uovQT0dZR+AlfA,
bardliao-Rasf1IRRPZFBDgjK7y7TUQ,
kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ,
petr-Qh/3xLP0EvwAvxtiuMwx3w, lars-Qo5EllUWu/uELgA04lAiVw,
nh6z-fFIq/eER6g8, ryans.lee-zxKO94PEStzToO697jQleEEOCMrvLtNR,
alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1479877026-5172-1-git-send-email-RyanS.Lee-zxKO94PEStzToO697jQleEEOCMrvLtNR@public.gmane.org>
Hi Ryan,
[auto build test WARNING on asoc/for-next]
[also build test WARNING on v4.9-rc6 next-20161123]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ryan-Lee/ALSA-SoC-MAX98927-driver-Initial-release/20161124-004840
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
coccinelle warnings: (new ones prefixed by >>)
>> sound/soc/codecs/max98927.c:941:3-8: No need to set .owner here. The core will do it.
Please review and possibly fold the followup patch.
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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