* [PATCH] ARM: dts: vf610-zii-dev-rev-b: Add missing newline
From: Andreas Färber @ 2016-11-27 19:54 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Andreas Färber, Andrew Lunn, David S . Miller, Shawn Guo,
Sascha Hauer, Stefan Agner, Rob Herring, Mark Rutland,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
Found while reviewing Marvell dsa bindings usage.
Fixes: f283745b3caf ("arm: vf610: zii devel b: Add support for switch interrupts")
Cc: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
Cc: David S. Miller <davem-fT/PcQaiUtIeIZ0/mPfg9Q@public.gmane.org>
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
arch/arm/boot/dts/vf610-zii-dev-rev-b.dts | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
index 7ea617e47fe4..958b4c42d320 100644
--- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
+++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts
@@ -153,7 +153,8 @@
switch0phy1: switch1phy0@1 {
reg = <1>;
interrupt-parent = <&switch0>;
- interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; };
+ interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+ };
switch0phy2: switch1phy0@2 {
reg = <2>;
interrupt-parent = <&switch0>;
--
2.6.6
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* Re: [PATCH v5 2/2] ARM: dts: add support for Turris Omnia
From: Andreas Färber @ 2016-11-27 19:39 UTC (permalink / raw)
To: Uwe Kleine-König, Gregory Clement
Cc: Mark Rutland, Andrew Lunn, Jason Cooper,
devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek, Rob Herring,
Bedřicha Košatu,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth
In-Reply-To: <71af60f5-b657-cab4-32a8-00a604fc656e-l3A5Bk7waGM@public.gmane.org>
Am 27.11.2016 um 20:22 schrieb Andreas Färber:
> Am 25.11.2016 um 15:26 schrieb Uwe Kleine-König:
>> diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
>> new file mode 100644
>> index 000000000000..bcc10c285889
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> [...]
>> + chosen {
>> + stdout-path = &uart0;
>> + };
>
> I notice that the other 38x boards (and thus my previous Omnia .dts) use
> "serial0:115200n8". Can we really rely on the driver defaults here?
Answering my own question: No, with the mvebu/dt .dts I do not get any
serial output. Patch sent.
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* [PATCH] ARM: dts: mvebu: Fix armada-385-turris-omnia stdout-path
From: Andreas Färber @ 2016-11-27 19:37 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Uwe Kleine-König, Michal Hrusecki, Tomas Hlavacek,
Bedřicha Košatu, Andreas Färber, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Rob Herring,
Mark Rutland, Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <71af60f5-b657-cab4-32a8-00a604fc656e-l3A5Bk7waGM@public.gmane.org>
Specify the baudrate.
Fixes: 26ca8b52d6e1 ("ARM: dts: add support for Turris Omnia")
Cc: Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
arch/arm/boot/dts/armada-385-turris-omnia.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
index f53cb8b73610..2eff012287d4 100644
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -52,7 +52,7 @@
compatible = "cznic,turris-omnia", "marvell,armada385", "marvell,armada380";
chosen {
- stdout-path = &uart0;
+ stdout-path = "serial0:115200n8";
};
memory {
--
2.6.6
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^ permalink raw reply related
* Re: [PATCH v5 2/2] ARM: dts: add support for Turris Omnia
From: Andreas Färber @ 2016-11-27 19:22 UTC (permalink / raw)
To: Uwe Kleine-König, Gregory Clement
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Bedřicha Košatu
In-Reply-To: <20161125142658.21690-3-uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
Am 25.11.2016 um 15:26 schrieb Uwe Kleine-König:
> diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
> new file mode 100644
> index 000000000000..bcc10c285889
> --- /dev/null
> +++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
[...]
> + chosen {
> + stdout-path = &uart0;
> + };
I notice that the other 38x boards (and thus my previous Omnia .dts) use
"serial0:115200n8". Can we really rely on the driver defaults here?
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* Re: [PATCH] ARM: dts: mvebu: Add Armada 38x labels and clean up Turris Omnia
From: Andreas Färber @ 2016-11-27 18:57 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Uwe Kleine-König, Michal Hrusecki, Tomas Hlavacek,
Bedřicha Košatu, Jason Cooper, Andrew Lunn,
Gregory Clement, Sebastian Hesselbarth, Rob Herring, Mark Rutland,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1480272700-28888-1-git-send-email-afaerber-l3A5Bk7waGM@public.gmane.org>
Am 27.11.2016 um 19:51 schrieb Andreas Färber:
> To more consistently reference nodes by label, add labels for sata,
> usb2, sdhci and usb3 nodes.
s/usb2/usb/ to be fully correct.
>
> Convert all other 38x boards for consistency. Add labels for nfc and rtc.
>
> Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
> ---
> arch/arm/boot/dts/armada-385-db-ap.dts | 334 +++++++------
> arch/arm/boot/dts/armada-385-linksys-caiman.dts | 98 ++--
> arch/arm/boot/dts/armada-385-linksys-cobra.dts | 98 ++--
> arch/arm/boot/dts/armada-385-linksys.dtsi | 294 ++++++-----
> arch/arm/boot/dts/armada-385-turris-omnia.dts | 97 ++--
> arch/arm/boot/dts/armada-385.dtsi | 20 +-
> arch/arm/boot/dts/armada-388-clearfog.dts | 550 ++++++++++-----------
> arch/arm/boot/dts/armada-388-db.dts | 236 ++++-----
> arch/arm/boot/dts/armada-388-gp.dts | 403 ++++++++-------
> arch/arm/boot/dts/armada-388-rd.dts | 115 +++--
> arch/arm/boot/dts/armada-388.dtsi | 19 +-
> .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 111 ++---
> arch/arm/boot/dts/armada-38x.dtsi | 16 +-
> 13 files changed, 1170 insertions(+), 1221 deletions(-)
[...]
> diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
> index 564fa59..1a7fc5d 100644
> --- a/arch/arm/boot/dts/armada-388.dtsi
> +++ b/arch/arm/boot/dts/armada-388.dtsi
> @@ -50,21 +50,8 @@
> model = "Marvell Armada 388 family SoC";
> compatible = "marvell,armada388", "marvell,armada385",
> "marvell,armada380";
> +};
>
> - soc {
> - internal-regs {
> - pinctrl@18000 {
> - compatible = "marvell,mv88f6828-pinctrl";
> - };
> -
> - sata@e0000 {
> - compatible = "marvell,armada-380-ahci";
> - reg = <0xe0000 0x2000>;
> - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> - clocks = <&gateclk 30>;
> - status = "disabled";
> - };
Note that this sata node is redundant with armada-38x.dtsi by my
reading, therefore dropped.
> -
> - };
> - };
> +&pinctrl {
> + compatible = "marvell,mv88f6828-pinctrl";
> };
Regards,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* [PATCH] ARM: dts: mvebu: Add Armada 38x labels and clean up Turris Omnia
From: Andreas Färber @ 2016-11-27 18:51 UTC (permalink / raw)
To: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Uwe Kleine-König, Michal Hrusecki, Tomas Hlavacek,
Bedřicha Košatu, Andreas Färber, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Rob Herring,
Mark Rutland, Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1fc18002-0144-8300-1888-09f456860ef0-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
To more consistently reference nodes by label, add labels for sata,
usb2, sdhci and usb3 nodes.
Convert all other 38x boards for consistency. Add labels for nfc and rtc.
Signed-off-by: Andreas Färber <afaerber-l3A5Bk7waGM@public.gmane.org>
---
arch/arm/boot/dts/armada-385-db-ap.dts | 334 +++++++------
arch/arm/boot/dts/armada-385-linksys-caiman.dts | 98 ++--
arch/arm/boot/dts/armada-385-linksys-cobra.dts | 98 ++--
arch/arm/boot/dts/armada-385-linksys.dtsi | 294 ++++++-----
arch/arm/boot/dts/armada-385-turris-omnia.dts | 97 ++--
arch/arm/boot/dts/armada-385.dtsi | 20 +-
arch/arm/boot/dts/armada-388-clearfog.dts | 550 ++++++++++-----------
arch/arm/boot/dts/armada-388-db.dts | 236 ++++-----
arch/arm/boot/dts/armada-388-gp.dts | 403 ++++++++-------
arch/arm/boot/dts/armada-388-rd.dts | 115 +++--
arch/arm/boot/dts/armada-388.dtsi | 19 +-
.../arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 111 ++---
arch/arm/boot/dts/armada-38x.dtsi | 16 +-
13 files changed, 1170 insertions(+), 1221 deletions(-)
diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts b/arch/arm/boot/dts/armada-385-db-ap.dts
index db5b9f6..9b67716 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -63,174 +63,6 @@
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
-
- internal-regs {
- i2c0: i2c@11000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- /*
- * This bus is wired to two EEPROM
- * sockets, one of which holding the
- * board ID used by the bootloader.
- * Erasing this EEPROM's content will
- * brick the board.
- * Use this bus with caution.
- */
- };
-
- mdio@72004 {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
-
- phy0: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy1: ethernet-phy@4 {
- reg = <4>;
- };
-
- phy2: ethernet-phy@6 {
- reg = <6>;
- };
- };
-
- /* UART0 is exposed through the JP8 connector */
- uart0: serial@12000 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
- };
-
- /*
- * UART1 is exposed through a FTDI chip
- * wired to the mini-USB connector
- */
- uart1: serial@12100 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins>;
- status = "okay";
- };
-
- pinctrl@18000 {
- xhci0_vbus_pins: xhci0-vbus-pins {
- marvell,pins = "mpp44";
- marvell,function = "gpio";
- };
- };
-
- /* CON3 */
- ethernet@30000 {
- status = "okay";
- phy = <&phy2>;
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <1>;
- bm,pool-short = <3>;
- };
-
- /* CON2 */
- ethernet@34000 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
- };
-
- usb@58000 {
- status = "okay";
- };
-
- /* CON4 */
- ethernet@70000 {
- pinctrl-names = "default";
-
- /*
- * The Reference Clock 0 is used to
- * provide a clock to the PHY
- */
- pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <3>;
- };
-
- bm@c8000 {
- status = "okay";
- };
-
- nfc: flash@d0000 {
- status = "okay";
- num-cs = <1>;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0x00000000 0x00800000>;
- read-only;
- };
-
- partition@800000 {
- label = "uImage";
- reg = <0x00800000 0x00400000>;
- read-only;
- };
-
- partition@c00000 {
- label = "Root";
- reg = <0x00c00000 0x3f400000>;
- };
- };
- };
-
- usb3@f0000 {
- status = "okay";
- usb-phy = <&usb3_phy>;
- };
- };
-
- bm-bppi {
- status = "okay";
- };
-
- pcie-controller {
- status = "okay";
-
- /*
- * The three PCIe units are accessible through
- * standard mini-PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
-
- pcie@3,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- };
};
usb3_phy: usb3_phy {
@@ -250,6 +82,150 @@
};
};
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+&ehci {
+ status = "okay";
+};
+
+/* CON4 */
+ð0 {
+ pinctrl-names = "default";
+
+ /*
+ * The Reference Clock 0 is used to
+ * provide a clock to the PHY
+ */
+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <3>;
+};
+
+/* CON3 */
+ð1 {
+ status = "okay";
+ phy = <&phy2>;
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <1>;
+ bm,pool-short = <3>;
+};
+
+/* CON2 */
+ð2 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <3>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ /*
+ * This bus is wired to two EEPROM
+ * sockets, one of which holding the
+ * board ID used by the bootloader.
+ * Erasing this EEPROM's content will
+ * brick the board.
+ * Use this bus with caution.
+ */
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy@4 {
+ reg = <4>;
+ };
+
+ phy2: ethernet-phy@6 {
+ reg = <6>;
+ };
+};
+
+&nfc {
+ status = "okay";
+ num-cs = <1>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0x00000000 0x00800000>;
+ read-only;
+ };
+
+ partition@800000 {
+ label = "uImage";
+ reg = <0x00800000 0x00400000>;
+ read-only;
+ };
+
+ partition@c00000 {
+ label = "Root";
+ reg = <0x00c00000 0x3f400000>;
+ };
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+/*
+ * The three PCIe units are accessible through
+ * standard mini-PCIe slots on the board.
+ */
+&pcie1 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&pcie2 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+&pcie3 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+};
+
+&pinctrl {
+ xhci0_vbus_pins: xhci0-vbus-pins {
+ marvell,pins = "mpp44";
+ marvell,function = "gpio";
+ };
+};
+
&spi1 {
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins>;
@@ -263,3 +239,25 @@
spi-max-frequency = <54000000>;
};
};
+
+/* UART0 is exposed through the JP8 connector */
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+/*
+ * UART1 is exposed through a FTDI chip
+ * wired to the mini-USB connector
+ */
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+ usb-phy = <&usb3_phy>;
+};
diff --git a/arch/arm/boot/dts/armada-385-linksys-caiman.dts b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
index f3cee91..7869fec 100644
--- a/arch/arm/boot/dts/armada-385-linksys-caiman.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-caiman.dts
@@ -44,71 +44,59 @@
model = "Linksys WRT1200AC";
compatible = "linksys,caiman", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+};
- soc {
- internal-regs{
- i2c@11000 {
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan_amber@0 {
- label = "caiman:amber:wan";
- reg = <0x0>;
- };
+&pca9635 {
+ wan_amber@0 {
+ label = "caiman:amber:wan";
+ reg = <0x0>;
+ };
- wan_white@1 {
- label = "caiman:white:wan";
- reg = <0x1>;
- };
+ wan_white@1 {
+ label = "caiman:white:wan";
+ reg = <0x1>;
+ };
- wlan_2g@2 {
- label = "caiman:white:wlan_2g";
- reg = <0x2>;
- };
+ wlan_2g@2 {
+ label = "caiman:white:wlan_2g";
+ reg = <0x2>;
+ };
- wlan_5g@3 {
- label = "caiman:white:wlan_5g";
- reg = <0x3>;
- };
+ wlan_5g@3 {
+ label = "caiman:white:wlan_5g";
+ reg = <0x3>;
+ };
- usb2@5 {
- label = "caiman:white:usb2";
- reg = <0x5>;
- };
+ usb2@5 {
+ label = "caiman:white:usb2";
+ reg = <0x5>;
+ };
- usb3_1@6 {
- label = "caiman:white:usb3_1";
- reg = <0x6>;
- };
+ usb3_1@6 {
+ label = "caiman:white:usb3_1";
+ reg = <0x6>;
+ };
- usb3_2@7 {
- label = "caiman:white:usb3_2";
- reg = <0x7>;
- };
+ usb3_2@7 {
+ label = "caiman:white:usb3_2";
+ reg = <0x7>;
+ };
- wps_white@8 {
- label = "caiman:white:wps";
- reg = <0x8>;
- };
+ wps_white@8 {
+ label = "caiman:white:wps";
+ reg = <0x8>;
+ };
- wps_amber@9 {
- label = "caiman:amber:wps";
- reg = <0x9>;
- };
- };
- };
- };
+ wps_amber@9 {
+ label = "caiman:amber:wps";
+ reg = <0x9>;
};
+};
- gpio-leds {
- power {
- label = "caiman:white:power";
- };
+&power_led {
+ label = "caiman:white:power";
+};
- sata {
- label = "caiman:white:sata";
- };
- };
+&sata_led {
+ label = "caiman:white:sata";
};
diff --git a/arch/arm/boot/dts/armada-385-linksys-cobra.dts b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
index 1110718..94cdc09 100644
--- a/arch/arm/boot/dts/armada-385-linksys-cobra.dts
+++ b/arch/arm/boot/dts/armada-385-linksys-cobra.dts
@@ -44,71 +44,59 @@
model = "Linksys WRT1900ACv2";
compatible = "linksys,cobra", "linksys,armada385", "marvell,armada385",
"marvell,armada380";
+};
- soc {
- internal-regs{
- i2c@11000 {
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
-
- wan_amber@0 {
- label = "cobra:amber:wan";
- reg = <0x0>;
- };
+&pca9635 {
+ wan_amber@0 {
+ label = "cobra:amber:wan";
+ reg = <0x0>;
+ };
- wan_white@1 {
- label = "cobra:white:wan";
- reg = <0x1>;
- };
+ wan_white@1 {
+ label = "cobra:white:wan";
+ reg = <0x1>;
+ };
- wlan_2g@2 {
- label = "cobra:white:wlan_2g";
- reg = <0x2>;
- };
+ wlan_2g@2 {
+ label = "cobra:white:wlan_2g";
+ reg = <0x2>;
+ };
- wlan_5g@3 {
- label = "cobra:white:wlan_5g";
- reg = <0x3>;
- };
+ wlan_5g@3 {
+ label = "cobra:white:wlan_5g";
+ reg = <0x3>;
+ };
- usb2@5 {
- label = "cobra:white:usb2";
- reg = <0x5>;
- };
+ usb2@5 {
+ label = "cobra:white:usb2";
+ reg = <0x5>;
+ };
- usb3_1@6 {
- label = "cobra:white:usb3_1";
- reg = <0x6>;
- };
+ usb3_1@6 {
+ label = "cobra:white:usb3_1";
+ reg = <0x6>;
+ };
- usb3_2@7 {
- label = "cobra:white:usb3_2";
- reg = <0x7>;
- };
+ usb3_2@7 {
+ label = "cobra:white:usb3_2";
+ reg = <0x7>;
+ };
- wps_white@8 {
- label = "cobra:white:wps";
- reg = <0x8>;
- };
+ wps_white@8 {
+ label = "cobra:white:wps";
+ reg = <0x8>;
+ };
- wps_amber@9 {
- label = "cobra:amber:wps";
- reg = <0x9>;
- };
- };
- };
- };
+ wps_amber@9 {
+ label = "cobra:amber:wps";
+ reg = <0x9>;
};
+};
- gpio-leds {
- power {
- label = "cobra:white:power";
- };
+&power_led {
+ label = "cobra:white:power";
+};
- sata {
- label = "cobra:white:sata";
- };
- };
+&sata_led {
+ label = "cobra:white:sata";
};
diff --git a/arch/arm/boot/dts/armada-385-linksys.dtsi b/arch/arm/boot/dts/armada-385-linksys.dtsi
index 8f0e508..67341e4 100644
--- a/arch/arm/boot/dts/armada-385-linksys.dtsi
+++ b/arch/arm/boot/dts/armada-385-linksys.dtsi
@@ -60,152 +60,6 @@
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
-
- internal-regs {
- i2c@11000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
-
- tmp421@4c {
- compatible = "ti,tmp421";
- reg = <0x4c>;
- };
-
- pca9635@68 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "nxp,pca9635";
- reg = <0x68>;
- };
- };
-
- /* J10: VCC, NC, RX, NC, TX, GND */
- serial@12000 {
- status = "okay";
- };
-
- ethernet@70000 {
- status = "okay";
- phy-mode = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- status = "okay";
- phy-mode = "sgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- mdio {
- status = "okay";
- };
-
- sata@a8000 {
- status = "okay";
- };
-
- /* USB part of the eSATA/USB 2.0 port */
- usb@58000 {
- status = "okay";
- };
-
- usb3@f8000 {
- status = "okay";
- usb-phy = <&usb3_phy>;
- };
-
- flash@d0000 {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
-
- partition@0 {
- label = "u-boot";
- reg = <0x0000000 0x200000>; /* 2MB */
- read-only;
- };
-
- partition@100000 {
- label = "u_env";
- reg = <0x200000 0x40000>; /* 256KB */
- };
-
- partition@140000 {
- label = "s_env";
- reg = <0x240000 0x40000>; /* 256KB */
- };
-
- partition@900000 {
- label = "devinfo";
- reg = <0x900000 0x100000>; /* 1MB */
- read-only;
- };
-
- /* kernel1 overlaps with rootfs1 by design */
- partition@a00000 {
- label = "kernel1";
- reg = <0xa00000 0x2800000>; /* 40MB */
- };
-
- partition@1000000 {
- label = "rootfs1";
- reg = <0x1000000 0x2200000>; /* 34MB */
- };
-
- /* kernel2 overlaps with rootfs2 by design */
- partition@3200000 {
- label = "kernel2";
- reg = <0x3200000 0x2800000>; /* 40MB */
- };
-
- partition@3800000 {
- label = "rootfs2";
- reg = <0x3800000 0x2200000>; /* 34MB */
- };
-
- /*
- * 38MB, last MB is for the BBT, not writable
- */
- partition@5a00000 {
- label = "syscfg";
- reg = <0x5a00000 0x2600000>;
- };
-
- /*
- * Unused area between "s_env" and "devinfo".
- * Moved here because otherwise the renumbered
- * partitions would break the bootloader
- * supplied bootargs
- */
- partition@180000 {
- label = "unused_area";
- reg = <0x280000 0x680000>; /* 6.5MB */
- };
- };
- };
-
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Marvell 88W8864, 5GHz-only */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Marvell 88W8864, 2GHz-only */
- status = "okay";
- };
- };
};
usb3_phy: usb3_phy {
@@ -249,12 +103,12 @@
pinctrl-0 = <&power_led_pin &sata_led_pin>;
pinctrl-names = "default";
- power {
+ power_led: power {
gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
default-state = "on";
};
- sata {
+ sata_led: sata {
gpios = <&gpio1 22 GPIO_ACTIVE_LOW>;
default-state = "off";
};
@@ -306,6 +160,140 @@
};
};
+&ahci0 {
+ status = "okay";
+};
+
+/* USB part of the eSATA/USB 2.0 port */
+&ehci {
+ status = "okay";
+};
+
+ð0 {
+ status = "okay";
+ phy-mode = "rgmii-id";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+ð2 {
+ status = "okay";
+ phy-mode = "sgmii";
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+
+ tmp421@4c {
+ compatible = "ti,tmp421";
+ reg = <0x4c>;
+ };
+
+ pca9635: pca9635@68 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "nxp,pca9635";
+ reg = <0x68>;
+ };
+};
+
+&mdio {
+ status = "okay";
+};
+
+&nfc {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+
+ partition@0 {
+ label = "u-boot";
+ reg = <0x0000000 0x200000>; /* 2MB */
+ read-only;
+ };
+
+ partition@100000 {
+ label = "u_env";
+ reg = <0x200000 0x40000>; /* 256KB */
+ };
+
+ partition@140000 {
+ label = "s_env";
+ reg = <0x240000 0x40000>; /* 256KB */
+ };
+
+ partition@900000 {
+ label = "devinfo";
+ reg = <0x900000 0x100000>; /* 1MB */
+ read-only;
+ };
+
+ /* kernel1 overlaps with rootfs1 by design */
+ partition@a00000 {
+ label = "kernel1";
+ reg = <0xa00000 0x2800000>; /* 40MB */
+ };
+
+ partition@1000000 {
+ label = "rootfs1";
+ reg = <0x1000000 0x2200000>; /* 34MB */
+ };
+
+ /* kernel2 overlaps with rootfs2 by design */
+ partition@3200000 {
+ label = "kernel2";
+ reg = <0x3200000 0x2800000>; /* 40MB */
+ };
+
+ partition@3800000 {
+ label = "rootfs2";
+ reg = <0x3800000 0x2200000>; /* 34MB */
+ };
+
+ /*
+ * 38MB, last MB is for the BBT, not writable
+ */
+ partition@5a00000 {
+ label = "syscfg";
+ reg = <0x5a00000 0x2600000>;
+ };
+
+ /*
+ * Unused area between "s_env" and "devinfo".
+ * Moved here because otherwise the renumbered
+ * partitions would break the bootloader
+ * supplied bootargs
+ */
+ partition@180000 {
+ label = "unused_area";
+ reg = <0x280000 0x680000>; /* 6.5MB */
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+&pcie1 {
+ /* Marvell 88W8864, 5GHz-only */
+ status = "okay";
+};
+
+&pcie2 {
+ /* Marvell 88W8864, 2GHz-only */
+ status = "okay";
+};
+
&pinctrl {
keys_pin: keys-pin {
marvell,pins = "mpp24", "mpp29";
@@ -331,3 +319,13 @@
&spi0 {
status = "disabled";
};
+
+/* J10: VCC, NC, RX, NC, TX, GND */
+&uart0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+ usb-phy = <&usb3_phy>;
+};
diff --git a/arch/arm/boot/dts/armada-385-turris-omnia.dts b/arch/arm/boot/dts/armada-385-turris-omnia.dts
index ab49acb..f53cb8b 100644
--- a/arch/arm/boot/dts/armada-385-turris-omnia.dts
+++ b/arch/arm/boot/dts/armada-385-turris-omnia.dts
@@ -65,56 +65,17 @@
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+ };
+};
- internal-regs {
-
- /* USB part of the PCIe2/USB 2.0 port */
- usb@58000 {
- status = "okay";
- };
-
- sata@a8000 {
- status = "okay";
- };
-
- sdhci@d8000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhci_pins>;
- status = "okay";
-
- bus-width = <8>;
- no-1-8-v;
- non-removable;
- };
-
- usb3@f0000 {
- status = "okay";
- };
-
- usb3@f8000 {
- status = "okay";
- };
- };
-
- pcie-controller {
- status = "okay";
-
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
+/* PCIe0/mSATA port */
+&ahci0 {
+ status = "okay";
+};
- pcie@3,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- };
- };
+/* USB part of the PCIe2/USB 2.0 port */
+&ehci {
+ status = "okay";
};
/* Connected to 88E6176 switch, port 6 */
@@ -276,6 +237,25 @@
/* Switch MV88E7176 at address 0x10 */
};
+&pcie {
+ status = "okay";
+};
+
+&pcie1 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&pcie2 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+&pcie3 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+};
+
&pinctrl {
pcawan_pins: pcawan-pins {
marvell,pins = "mpp46";
@@ -293,6 +273,17 @@
};
};
+/* eMMC */
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ status = "okay";
+
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
@@ -338,3 +329,13 @@
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
+
+/* front USB port */
+&xhci0 {
+ status = "okay";
+};
+
+/* rear USB port */
+&xhci1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-385.dtsi b/arch/arm/boot/dts/armada-385.dtsi
index 8e67d2c..d3cd60c 100644
--- a/arch/arm/boot/dts/armada-385.dtsi
+++ b/arch/arm/boot/dts/armada-385.dtsi
@@ -70,13 +70,7 @@
};
soc {
- internal-regs {
- pinctrl@18000 {
- compatible = "marvell,mv88f6820-pinctrl";
- };
- };
-
- pcie-controller {
+ pcie: pcie-controller {
compatible = "marvell,armada-370-pcie";
status = "disabled";
device_type = "pci";
@@ -106,7 +100,7 @@
* configured in x4 by the bootloader, then
* pcie@4,0 is not available.
*/
- pcie@1,0 {
+ pcie1: pcie@1,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
reg = <0x0800 0 0 0 0>;
@@ -124,7 +118,7 @@
};
/* x1 port */
- pcie@2,0 {
+ pcie2: pcie@2,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
reg = <0x1000 0 0 0 0>;
@@ -142,7 +136,7 @@
};
/* x1 port */
- pcie@3,0 {
+ pcie3: pcie@3,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
reg = <0x1800 0 0 0 0>;
@@ -163,7 +157,7 @@
* x1 port only available when pcie@1,0 is
* configured as a x1 port
*/
- pcie@4,0 {
+ pcie4: pcie@4,0 {
device_type = "pci";
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
reg = <0x2000 0 0 0 0>;
@@ -182,3 +176,7 @@
};
};
};
+
+&pinctrl {
+ compatible = "marvell,mv88f6820-pinctrl";
+};
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
index 71ce201..98c622e 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -74,282 +74,6 @@
regulator-always-on;
};
- soc {
- internal-regs {
- ethernet@30000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <1>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- ethernet@34000 {
- phy-mode = "sgmii";
- buffer-manager = <&bm>;
- bm,pool-long = <3>;
- bm,pool-short = <1>;
- status = "okay";
-
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- i2c@11000 {
- /* Is there anything on this? */
- clock-frequency = <100000>;
- pinctrl-0 = <&i2c0_pins>;
- pinctrl-names = "default";
- status = "okay";
-
- /*
- * PCA9655 GPIO expander, up to 1MHz clock.
- * 0-CON3 CLKREQ#
- * 1-CON3 PERST#
- * 2-CON2 PERST#
- * 3-CON3 W_DISABLE
- * 4-CON2 CLKREQ#
- * 5-USB3 overcurrent
- * 6-USB3 power
- * 7-CON2 W_DISABLE
- * 8-JP4 P1
- * 9-JP4 P4
- * 10-JP4 P5
- * 11-m.2 DEVSLP
- * 12-SFP_LOS
- * 13-SFP_TX_FAULT
- * 14-SFP_TX_DISABLE
- * 15-SFP_MOD_DEF0
- */
- expander0: gpio-expander@20 {
- /*
- * This is how it should be:
- * compatible = "onnn,pca9655",
- * "nxp,pca9555";
- * but you can't do this because of
- * the way I2C works.
- */
- compatible = "nxp,pca9555";
- gpio-controller;
- #gpio-cells = <2>;
- reg = <0x20>;
-
- pcie1_0_clkreq {
- gpio-hog;
- gpios = <0 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie1.0-clkreq";
- };
- pcie1_0_w_disable {
- gpio-hog;
- gpios = <3 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie1.0-w-disable";
- };
- pcie2_0_clkreq {
- gpio-hog;
- gpios = <4 GPIO_ACTIVE_LOW>;
- input;
- line-name = "pcie2.0-clkreq";
- };
- pcie2_0_w_disable {
- gpio-hog;
- gpios = <7 GPIO_ACTIVE_LOW>;
- output-low;
- line-name = "pcie2.0-w-disable";
- };
- usb3_ilimit {
- gpio-hog;
- gpios = <5 GPIO_ACTIVE_LOW>;
- input;
- line-name = "usb3-current-limit";
- };
- usb3_power {
- gpio-hog;
- gpios = <6 GPIO_ACTIVE_HIGH>;
- output-high;
- line-name = "usb3-power";
- };
- m2_devslp {
- gpio-hog;
- gpios = <11 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "m.2 devslp";
- };
- sfp_los {
- /* SFP loss of signal */
- gpio-hog;
- gpios = <12 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-los";
- };
- sfp_tx_fault {
- /* SFP laser fault */
- gpio-hog;
- gpios = <13 GPIO_ACTIVE_HIGH>;
- input;
- line-name = "sfp-tx-fault";
- };
- sfp_tx_disable {
- /* SFP transmit disable */
- gpio-hog;
- gpios = <14 GPIO_ACTIVE_HIGH>;
- output-low;
- line-name = "sfp-tx-disable";
- };
- sfp_mod_def0 {
- /* SFP module present */
- gpio-hog;
- gpios = <15 GPIO_ACTIVE_LOW>;
- input;
- line-name = "sfp-mod-def0";
- };
- };
-
- /* The MCP3021 is 100kHz clock only */
- mikrobus_adc: mcp3021@4c {
- compatible = "microchip,mcp3021";
- reg = <0x4c>;
- };
-
- /* Also something at 0x64 */
- };
-
- i2c@11100 {
- /*
- * Routed to SFP, mikrobus, and PCIe.
- * SFP limits this to 100kHz, and requires
- * an AT24C01A/02/04 with address pins tied
- * low, which takes addresses 0x50 and 0x51.
- * Mikrobus doesn't specify beyond an I2C
- * bus being present.
- * PCIe uses ARP to assign addresses, or
- * 0x63-0x64.
- */
- clock-frequency = <100000>;
- pinctrl-0 = <&clearfog_i2c1_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- pinctrl@18000 {
- clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
- marvell,pins = "mpp46";
- marvell,function = "ref";
- };
- clearfog_dsa0_pins: clearfog-dsa0-pins {
- marvell,pins = "mpp23", "mpp41";
- marvell,function = "gpio";
- };
- clearfog_i2c1_pins: i2c1-pins {
- /* SFP, PCIe, mSATA, mikrobus */
- marvell,pins = "mpp26", "mpp27";
- marvell,function = "i2c1";
- };
- clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
- marvell,pins = "mpp20";
- marvell,function = "gpio";
- };
- clearfog_sdhci_pins: clearfog-sdhci-pins {
- marvell,pins = "mpp21", "mpp28",
- "mpp37", "mpp38",
- "mpp39", "mpp40";
- marvell,function = "sd0";
- };
- clearfog_spi1_cs_pins: spi1-cs-pins {
- marvell,pins = "mpp55";
- marvell,function = "spi1";
- };
- mikro_pins: mikro-pins {
- /* int: mpp22 rst: mpp29 */
- marvell,pins = "mpp22", "mpp29";
- marvell,function = "gpio";
- };
- mikro_spi_pins: mikro-spi-pins {
- marvell,pins = "mpp43";
- marvell,function = "spi1";
- };
- mikro_uart_pins: mikro-uart-pins {
- marvell,pins = "mpp24", "mpp25";
- marvell,function = "ua1";
- };
- rear_button_pins: rear-button-pins {
- marvell,pins = "mpp34";
- marvell,function = "gpio";
- };
- };
-
- sata@a8000 {
- /* pinctrl? */
- status = "okay";
- };
-
- sata@e0000 {
- /* pinctrl? */
- status = "okay";
- };
-
- sdhci@d8000 {
- bus-width = <4>;
- cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
- no-1-8-v;
- pinctrl-0 = <&clearfog_sdhci_pins
- &clearfog_sdhci_cd_pins>;
- pinctrl-names = "default";
- status = "okay";
- vmmc = <®_3p3v>;
- wp-inverted;
- };
-
- serial@12100 {
- /* mikrobus uart */
- pinctrl-0 = <&mikro_uart_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
-
- usb@58000 {
- /* CON3, nearest power. */
- status = "okay";
- };
-
- usb3@f0000 {
- /* CON2, nearest CPU, USB2 only. */
- status = "okay";
- };
-
- usb3@f8000 {
- /* CON7 */
- status = "okay";
- };
- };
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * the mini-PCIe connectors on the board.
- */
- pcie@2,0 {
- /* Port 1, Lane 0. CON3, nearest power. */
- reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- pcie@3,0 {
- /* Port 2, Lane 0. CON2, nearest CPU. */
- reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
- status = "okay";
- };
- };
- };
-
dsa@0 {
compatible = "marvell,dsa";
dsa,ethernet = <ð1>;
@@ -421,6 +145,263 @@
};
};
+&ahci0 {
+ /* pinctrl? */
+ status = "okay";
+};
+
+&ahci1 {
+ /* pinctrl? */
+ status = "okay";
+};
+
+&ehci {
+ /* CON3, nearest power. */
+ status = "okay";
+};
+
+ð1 {
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <1>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+ð2 {
+ phy-mode = "sgmii";
+ buffer-manager = <&bm>;
+ bm,pool-long = <3>;
+ bm,pool-short = <1>;
+ status = "okay";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+};
+
+&i2c0 {
+ /* Is there anything on this? */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&i2c0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+
+ /*
+ * PCA9655 GPIO expander, up to 1MHz clock.
+ * 0-CON3 CLKREQ#
+ * 1-CON3 PERST#
+ * 2-CON2 PERST#
+ * 3-CON3 W_DISABLE
+ * 4-CON2 CLKREQ#
+ * 5-USB3 overcurrent
+ * 6-USB3 power
+ * 7-CON2 W_DISABLE
+ * 8-JP4 P1
+ * 9-JP4 P4
+ * 10-JP4 P5
+ * 11-m.2 DEVSLP
+ * 12-SFP_LOS
+ * 13-SFP_TX_FAULT
+ * 14-SFP_TX_DISABLE
+ * 15-SFP_MOD_DEF0
+ */
+ expander0: gpio-expander@20 {
+ /*
+ * This is how it should be:
+ * compatible = "onnn,pca9655",
+ * "nxp,pca9555";
+ * but you can't do this because of
+ * the way I2C works.
+ */
+ compatible = "nxp,pca9555";
+ gpio-controller;
+ #gpio-cells = <2>;
+ reg = <0x20>;
+
+ pcie1_0_clkreq {
+ gpio-hog;
+ gpios = <0 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie1.0-clkreq";
+ };
+ pcie1_0_w_disable {
+ gpio-hog;
+ gpios = <3 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie1.0-w-disable";
+ };
+ pcie2_0_clkreq {
+ gpio-hog;
+ gpios = <4 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "pcie2.0-clkreq";
+ };
+ pcie2_0_w_disable {
+ gpio-hog;
+ gpios = <7 GPIO_ACTIVE_LOW>;
+ output-low;
+ line-name = "pcie2.0-w-disable";
+ };
+ usb3_ilimit {
+ gpio-hog;
+ gpios = <5 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "usb3-current-limit";
+ };
+ usb3_power {
+ gpio-hog;
+ gpios = <6 GPIO_ACTIVE_HIGH>;
+ output-high;
+ line-name = "usb3-power";
+ };
+ m2_devslp {
+ gpio-hog;
+ gpios = <11 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "m.2 devslp";
+ };
+ sfp_los {
+ /* SFP loss of signal */
+ gpio-hog;
+ gpios = <12 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-los";
+ };
+ sfp_tx_fault {
+ /* SFP laser fault */
+ gpio-hog;
+ gpios = <13 GPIO_ACTIVE_HIGH>;
+ input;
+ line-name = "sfp-tx-fault";
+ };
+ sfp_tx_disable {
+ /* SFP transmit disable */
+ gpio-hog;
+ gpios = <14 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "sfp-tx-disable";
+ };
+ sfp_mod_def0 {
+ /* SFP module present */
+ gpio-hog;
+ gpios = <15 GPIO_ACTIVE_LOW>;
+ input;
+ line-name = "sfp-mod-def0";
+ };
+ };
+
+ /* The MCP3021 is 100kHz clock only */
+ mikrobus_adc: mcp3021@4c {
+ compatible = "microchip,mcp3021";
+ reg = <0x4c>;
+ };
+
+ /* Also something at 0x64 */
+};
+
+&i2c1 {
+ /*
+ * Routed to SFP, mikrobus, and PCIe.
+ * SFP limits this to 100kHz, and requires
+ * an AT24C01A/02/04 with address pins tied
+ * low, which takes addresses 0x50 and 0x51.
+ * Mikrobus doesn't specify beyond an I2C
+ * bus being present.
+ * PCIe uses ARP to assign addresses, or
+ * 0x63-0x64.
+ */
+ clock-frequency = <100000>;
+ pinctrl-0 = <&clearfog_i2c1_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&pcie {
+ status = "okay";
+};
+
+/*
+ * The two PCIe units are accessible through
+ * the mini-PCIe connectors on the board.
+ */
+&pcie2 {
+ /* Port 1, Lane 0. CON3, nearest power. */
+ reset-gpios = <&expander0 1 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pcie3 {
+ /* Port 2, Lane 0. CON2, nearest CPU. */
+ reset-gpios = <&expander0 2 GPIO_ACTIVE_LOW>;
+ status = "okay";
+};
+
+&pinctrl {
+ clearfog_dsa0_clk_pins: clearfog-dsa0-clk-pins {
+ marvell,pins = "mpp46";
+ marvell,function = "ref";
+ };
+ clearfog_dsa0_pins: clearfog-dsa0-pins {
+ marvell,pins = "mpp23", "mpp41";
+ marvell,function = "gpio";
+ };
+ clearfog_i2c1_pins: i2c1-pins {
+ /* SFP, PCIe, mSATA, mikrobus */
+ marvell,pins = "mpp26", "mpp27";
+ marvell,function = "i2c1";
+ };
+ clearfog_sdhci_cd_pins: clearfog-sdhci-cd-pins {
+ marvell,pins = "mpp20";
+ marvell,function = "gpio";
+ };
+ clearfog_sdhci_pins: clearfog-sdhci-pins {
+ marvell,pins = "mpp21", "mpp28",
+ "mpp37", "mpp38",
+ "mpp39", "mpp40";
+ marvell,function = "sd0";
+ };
+ clearfog_spi1_cs_pins: spi1-cs-pins {
+ marvell,pins = "mpp55";
+ marvell,function = "spi1";
+ };
+ mikro_pins: mikro-pins {
+ /* int: mpp22 rst: mpp29 */
+ marvell,pins = "mpp22", "mpp29";
+ marvell,function = "gpio";
+ };
+ mikro_spi_pins: mikro-spi-pins {
+ marvell,pins = "mpp43";
+ marvell,function = "spi1";
+ };
+ mikro_uart_pins: mikro-uart-pins {
+ marvell,pins = "mpp24", "mpp25";
+ marvell,function = "ua1";
+ };
+ rear_button_pins: rear-button-pins {
+ marvell,pins = "mpp34";
+ marvell,function = "gpio";
+ };
+};
+
+&sdhci {
+ bus-width = <4>;
+ cd-gpios = <&gpio0 20 GPIO_ACTIVE_LOW>;
+ no-1-8-v;
+ pinctrl-0 = <&clearfog_sdhci_pins
+ &clearfog_sdhci_cd_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+ vmmc = <®_3p3v>;
+ wp-inverted;
+};
+
&spi1 {
/*
* We don't seem to have the W25Q32 on the
@@ -444,3 +425,20 @@
status = "disabled";
};
};
+
+&uart1 {
+ /* mikrobus uart */
+ pinctrl-0 = <&mikro_uart_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&xhci0 {
+ /* CON2, nearest CPU, USB2 only. */
+ status = "okay";
+};
+
+&xhci1 {
+ /* CON7 */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-388-db.dts b/arch/arm/boot/dts/armada-388-db.dts
index de26c76..b676bf1 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -68,128 +68,117 @@
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+ };
+};
+
+&ahci0 {
+ status = "okay";
+};
+
+&ahci1 {
+ status = "okay";
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+&ehci {
+ status = "ok";
+};
+
+ð0 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+};
+
+ð1 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <3>;
+};
+
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&i2c1 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
- internal-regs {
- i2c@11000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- i2c@11100 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- serial@12000 {
- status = "okay";
- };
-
- ethernet@30000 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
- };
-
- usb@58000 {
- status = "ok";
- };
-
- ethernet@70000 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- };
-
- mdio@72004 {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
- sata@a8000 {
- status = "okay";
- };
-
- sata@e0000 {
- status = "okay";
- };
-
- bm@c8000 {
- status = "okay";
- };
-
- flash@d0000 {
- status = "okay";
- num-cs = <1>;
- marvell,nand-keep-config;
- marvell,nand-enable-arbiter;
- nand-on-flash-bbt;
- nand-ecc-strength = <4>;
- nand-ecc-step-size = <512>;
-
- partition@0 {
- label = "U-Boot";
- reg = <0 0x800000>;
- };
- partition@800000 {
- label = "Linux";
- reg = <0x800000 0x800000>;
- };
- partition@1000000 {
- label = "Filesystem";
- reg = <0x1000000 0x3f000000>;
- };
- };
-
- sdhci@d8000 {
- broken-cd;
- wp-inverted;
- bus-width = <8>;
- status = "okay";
- no-1-8-v;
- };
-
- usb3@f0000 {
- status = "okay";
- };
-
- usb3@f8000 {
- status = "okay";
- };
- };
-
- bm-bppi {
- status = "okay";
- };
-
- pcie-controller {
- status = "okay";
- /*
- * The two PCIe units are accessible through
- * standard PCIe slots on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- };
+ phy1: ethernet-phy@1 {
+ reg = <1>;
};
};
+&nfc {
+ status = "okay";
+ num-cs = <1>;
+ marvell,nand-keep-config;
+ marvell,nand-enable-arbiter;
+ nand-on-flash-bbt;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partition@0 {
+ label = "U-Boot";
+ reg = <0 0x800000>;
+ };
+ partition@800000 {
+ label = "Linux";
+ reg = <0x800000 0x800000>;
+ };
+ partition@1000000 {
+ label = "Filesystem";
+ reg = <0x1000000 0x3f000000>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+/*
+ * The two PCIe units are accessible through
+ * standard PCIe slots on the board.
+ */
+&pcie1 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&pcie2 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+
+&sdhci {
+ broken-cd;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+ no-1-8-v;
+};
+
&spi0 {
status = "okay";
@@ -202,3 +191,14 @@
};
};
+&uart0 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-388-gp.dts b/arch/arm/boot/dts/armada-388-gp.dts
index 895fa6c..89dd124 100644
--- a/arch/arm/boot/dts/armada-388-gp.dts
+++ b/arch/arm/boot/dts/armada-388-gp.dts
@@ -63,208 +63,6 @@
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
- internal-regs {
- i2c@11000 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c0_pins>;
- status = "okay";
- clock-frequency = <100000>;
-
- expander0: pca9555@20 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- pinctrl-0 = <&pca0_pins>;
- interrupt-parent = <&gpio0>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x20>;
- };
-
- expander1: pca9555@21 {
- compatible = "nxp,pca9555";
- pinctrl-names = "default";
- interrupt-parent = <&gpio0>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- reg = <0x21>;
- };
-
- eeprom@57 {
- compatible = "atmel,24c64";
- reg = <0x57>;
- };
- };
-
- serial@12000 {
- /*
- * Exported on the micro USB connector CON16
- * through an FTDI
- */
-
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
- };
-
- /* GE1 CON15 */
- ethernet@30000 {
- pinctrl-names = "default";
- pinctrl-0 = <&ge1_rgmii_pins>;
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <2>;
- bm,pool-short = <3>;
- };
-
- /* CON4 */
- usb@58000 {
- vcc-supply = <®_usb2_0_vbus>;
- status = "okay";
- };
-
- /* GE0 CON1 */
- ethernet@70000 {
- pinctrl-names = "default";
- /*
- * The Reference Clock 0 is used to provide a
- * clock to the PHY
- */
- pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- };
-
-
- mdio@72004 {
- pinctrl-names = "default";
- pinctrl-0 = <&mdio_pins>;
-
- phy0: ethernet-phy@1 {
- reg = <1>;
- };
-
- phy1: ethernet-phy@0 {
- reg = <0>;
- };
- };
-
- sata@a8000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata0: sata-port@0 {
- reg = <0>;
- target-supply = <®_5v_sata0>;
- };
-
- sata1: sata-port@1 {
- reg = <1>;
- target-supply = <®_5v_sata1>;
- };
- };
-
- bm@c8000 {
- status = "okay";
- };
-
- sata@e0000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
- status = "okay";
- #address-cells = <1>;
- #size-cells = <0>;
-
- sata2: sata-port@0 {
- reg = <0>;
- target-supply = <®_5v_sata2>;
- };
-
- sata3: sata-port@1 {
- reg = <1>;
- target-supply = <®_5v_sata3>;
- };
- };
-
- sdhci@d8000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhci_pins>;
- no-1-8-v;
- /*
- * A388-GP board v1.5 and higher replace
- * hitherto card detection method based on GPIO
- * with the one using DAT3 pin. As they are
- * incompatible, software-based polling is
- * enabled with 'broken-cd' property. For boards
- * older than v1.5 it can be replaced with:
- * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
- * whereas for the newer ones following can be
- * used instead:
- * 'dat3-cd;'
- * 'cd-inverted;'
- */
- broken-cd;
- wp-inverted;
- bus-width = <8>;
- status = "okay";
- };
-
- /* CON5 */
- usb3@f0000 {
- usb-phy = <&usb2_1_phy>;
- status = "okay";
- };
-
- /* CON7 */
- usb3@f8000 {
- usb-phy = <&usb3_phy>;
- status = "okay";
- };
- };
-
- bm-bppi {
- status = "okay";
- };
-
- pcie-controller {
- status = "okay";
- /*
- * One PCIe units is accessible through
- * standard PCIe slot on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
-
- /*
- * The two other PCIe units are accessible
- * through mini PCIe slot on the board.
- */
- pcie@2,0 {
- /* Port 1, Lane 0 */
- status = "okay";
- };
- pcie@3,0 {
- /* Port 2, Lane 0 */
- status = "okay";
- };
- };
-
gpio-fan {
compatible = "gpio-fan";
gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
@@ -412,6 +210,161 @@
};
};
+&ahci0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata0: sata-port@0 {
+ reg = <0>;
+ target-supply = <®_5v_sata0>;
+ };
+
+ sata1: sata-port@1 {
+ reg = <1>;
+ target-supply = <®_5v_sata1>;
+ };
+};
+
+&ahci1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
+ status = "okay";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sata2: sata-port@0 {
+ reg = <0>;
+ target-supply = <®_5v_sata2>;
+ };
+
+ sata3: sata-port@1 {
+ reg = <1>;
+ target-supply = <®_5v_sata3>;
+ };
+};
+
+&bm {
+ status = "okay";
+};
+
+&bm_bppi {
+ status = "okay";
+};
+
+/* CON4 */
+&ehci {
+ vcc-supply = <®_usb2_0_vbus>;
+ status = "okay";
+};
+
+/* GE0 CON1 */
+ð0 {
+ pinctrl-names = "default";
+ /*
+ * The Reference Clock 0 is used to provide a
+ * clock to the PHY
+ */
+ pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+};
+
+/* GE1 CON15 */
+ð1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&ge1_rgmii_pins>;
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <2>;
+ bm,pool-short = <3>;
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pins>;
+ status = "okay";
+ clock-frequency = <100000>;
+
+ expander0: pca9555@20 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pca0_pins>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x20>;
+ };
+
+ expander1: pca9555@21 {
+ compatible = "nxp,pca9555";
+ pinctrl-names = "default";
+ interrupt-parent = <&gpio0>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ reg = <0x21>;
+ };
+
+ eeprom@57 {
+ compatible = "atmel,24c64";
+ reg = <0x57>;
+ };
+};
+
+&mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio_pins>;
+
+ phy0: ethernet-phy@1 {
+ reg = <1>;
+ };
+
+ phy1: ethernet-phy@0 {
+ reg = <0>;
+ };
+};
+
+&pcie {
+ status = "okay";
+};
+
+/*
+ * One PCIe units is accessible through
+ * standard PCIe slot on the board.
+ */
+&pcie1 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+/*
+ * The two other PCIe units are accessible
+ * through mini PCIe slot on the board.
+ */
+&pcie2 {
+ /* Port 1, Lane 0 */
+ status = "okay";
+};
+
+&pcie3 {
+ /* Port 2, Lane 0 */
+ status = "okay";
+};
+
&pinctrl {
pca0_pins: pca0_pins {
marvell,pins = "mpp18";
@@ -419,6 +372,29 @@
};
};
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ no-1-8-v;
+ /*
+ * A388-GP board v1.5 and higher replace
+ * hitherto card detection method based on GPIO
+ * with the one using DAT3 pin. As they are
+ * incompatible, software-based polling is
+ * enabled with 'broken-cd' property. For boards
+ * older than v1.5 it can be replaced with:
+ * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
+ * whereas for the newer ones following can be
+ * used instead:
+ * 'dat3-cd;'
+ * 'cd-inverted;'
+ */
+ broken-cd;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+};
+
&spi0 {
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
@@ -433,3 +409,26 @@
m25p,fast-read;
};
};
+
+&uart0 {
+ /*
+ * Exported on the micro USB connector CON16
+ * through an FTDI
+ */
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+/* CON5 */
+&xhci0 {
+ usb-phy = <&usb2_1_phy>;
+ status = "okay";
+};
+
+/* CON7 */
+&xhci1 {
+ usb-phy = <&usb3_phy>;
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-388-rd.dts b/arch/arm/boot/dts/armada-388-rd.dts
index dd3462dd..60c9065 100644
--- a/arch/arm/boot/dts/armada-388-rd.dts
+++ b/arch/arm/boot/dts/armada-388-rd.dts
@@ -68,69 +68,59 @@
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000>;
+ };
+};
+
+ð0 {
+ status = "okay";
+ phy = <&phy1>;
+ phy-mode = "rgmii-id";
+};
+
+ð1 {
+ status = "okay";
+ phy = <&phy0>;
+ phy-mode = "rgmii-id";
+};
- internal-regs {
- i2c@11000 {
- status = "okay";
- clock-frequency = <100000>;
- };
-
- sdhci@d8000 {
- pinctrl-names = "default";
- pinctrl-0 = <&sdhci_pins>;
- broken-cd;
- no-1-8-v;
- wp-inverted;
- bus-width = <8>;
- status = "okay";
- };
-
- serial@12000 {
- status = "okay";
- };
-
- ethernet@30000 {
- status = "okay";
- phy = <&phy0>;
- phy-mode = "rgmii-id";
- };
-
- ethernet@70000 {
- status = "okay";
- phy = <&phy1>;
- phy-mode = "rgmii-id";
- };
-
-
- mdio@72004 {
- phy0: ethernet-phy@0 {
- reg = <0>;
- };
-
- phy1: ethernet-phy@1 {
- reg = <1>;
- };
- };
-
- usb3@f0000 {
- status = "okay";
- };
- };
-
- pcie-controller {
- status = "okay";
- /*
- * One PCIe units is accessible through
- * standard PCIe slot on the board.
- */
- pcie@1,0 {
- /* Port 0, Lane 0 */
- status = "okay";
- };
- };
+&i2c0 {
+ status = "okay";
+ clock-frequency = <100000>;
+};
+
+&mdio {
+ phy0: ethernet-phy@0 {
+ reg = <0>;
+ };
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
};
};
+&pcie {
+ status = "okay";
+};
+
+/*
+ * One PCIe units is accessible through
+ * standard PCIe slot on the board.
+ */
+&pcie1 {
+ /* Port 0, Lane 0 */
+ status = "okay";
+};
+
+&sdhci {
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdhci_pins>;
+ broken-cd;
+ no-1-8-v;
+ wp-inverted;
+ bus-width = <8>;
+ status = "okay";
+};
+
&spi0 {
status = "okay";
@@ -143,3 +133,10 @@
};
};
+&uart0 {
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/armada-388.dtsi b/arch/arm/boot/dts/armada-388.dtsi
index 564fa59..1a7fc5d 100644
--- a/arch/arm/boot/dts/armada-388.dtsi
+++ b/arch/arm/boot/dts/armada-388.dtsi
@@ -50,21 +50,8 @@
model = "Marvell Armada 388 family SoC";
compatible = "marvell,armada388", "marvell,armada385",
"marvell,armada380";
+};
- soc {
- internal-regs {
- pinctrl@18000 {
- compatible = "marvell,mv88f6828-pinctrl";
- };
-
- sata@e0000 {
- compatible = "marvell,armada-380-ahci";
- reg = <0xe0000 0x2000>;
- interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gateclk 30>;
- status = "disabled";
- };
-
- };
- };
+&pinctrl {
+ compatible = "marvell,mv88f6828-pinctrl";
};
diff --git a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
index 8c98422..b97eae3 100644
--- a/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
+++ b/arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi
@@ -60,69 +60,66 @@
MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
+ };
+};
- internal-regs {
- ethernet@70000 {
- pinctrl-0 = <&ge0_rgmii_pins>;
- pinctrl-names = "default";
- phy = <&phy_dedicated>;
- phy-mode = "rgmii-id";
- buffer-manager = <&bm>;
- bm,pool-long = <0>;
- bm,pool-short = <1>;
- status = "okay";
- };
-
- mdio@72004 {
- /*
- * Add the phy clock here, so the phy can be
- * accessed to read its IDs prior to binding
- * with the driver.
- */
- pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
- pinctrl-names = "default";
+&bm {
+ status = "okay";
+};
- phy_dedicated: ethernet-phy@0 {
- /*
- * Annoyingly, the marvell phy driver
- * configures the LED register, rather
- * than preserving reset-loaded setting.
- * We undo that rubbish here.
- */
- marvell,reg-init = <3 16 0 0x101e>;
- reg = <0>;
- };
- };
+&bm_bppi {
+ status = "okay";
+};
- pinctrl@18000 {
- microsom_phy_clk_pins: microsom-phy-clk-pins {
- marvell,pins = "mpp45";
- marvell,function = "ref";
- };
- };
+ð0 {
+ pinctrl-0 = <&ge0_rgmii_pins>;
+ pinctrl-names = "default";
+ phy = <&phy_dedicated>;
+ phy-mode = "rgmii-id";
+ buffer-manager = <&bm>;
+ bm,pool-long = <0>;
+ bm,pool-short = <1>;
+ status = "okay";
+};
- rtc@a3800 {
- /*
- * If the rtc doesn't work, run "date reset"
- * twice in u-boot.
- */
- status = "okay";
- };
+&mdio {
+ /*
+ * Add the phy clock here, so the phy can be
+ * accessed to read its IDs prior to binding
+ * with the driver.
+ */
+ pinctrl-0 = <&mdio_pins µsom_phy_clk_pins>;
+ pinctrl-names = "default";
- serial@12000 {
- pinctrl-0 = <&uart0_pins>;
- pinctrl-names = "default";
- status = "okay";
- };
+ phy_dedicated: ethernet-phy@0 {
+ /*
+ * Annoyingly, the marvell phy driver
+ * configures the LED register, rather
+ * than preserving reset-loaded setting.
+ * We undo that rubbish here.
+ */
+ marvell,reg-init = <3 16 0 0x101e>;
+ reg = <0>;
+ };
+};
- bm@c8000 {
- status = "okay";
- };
- };
+&pinctrl {
+ microsom_phy_clk_pins: microsom-phy-clk-pins {
+ marvell,pins = "mpp45";
+ marvell,function = "ref";
+ };
+};
- bm-bppi {
- status = "okay";
- };
+&rtc {
+ /*
+ * If the rtc doesn't work, run "date reset"
+ * twice in u-boot.
+ */
+ status = "okay";
+};
- };
+&uart0 {
+ pinctrl-0 = <&uart0_pins>;
+ pinctrl-names = "default";
+ status = "okay";
};
diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi
index 7450e9f..25303b1 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -451,7 +451,7 @@
status = "disabled";
};
- usb@58000 {
+ ehci: usb@58000 {
compatible = "marvell,orion-ehci";
reg = <0x58000 0x500>;
interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
@@ -522,14 +522,14 @@
marvell,crypto-sram-size = <0x800>;
};
- rtc@a3800 {
+ rtc: rtc@a3800 {
compatible = "marvell,armada-380-rtc";
reg = <0xa3800 0x20>, <0x184a0 0x0c>;
reg-names = "rtc", "rtc-soc";
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
};
- sata@a8000 {
+ ahci0: sata@a8000 {
compatible = "marvell,armada-380-ahci";
reg = <0xa8000 0x2000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
@@ -545,7 +545,7 @@
status = "disabled";
};
- sata@e0000 {
+ ahci1: sata@e0000 {
compatible = "marvell,armada-380-ahci";
reg = <0xe0000 0x2000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
@@ -567,7 +567,7 @@
status = "okay";
};
- flash@d0000 {
+ nfc: flash@d0000 {
compatible = "marvell,armada370-nand";
reg = <0xd0000 0x54>;
#address-cells = <1>;
@@ -577,7 +577,7 @@
status = "disabled";
};
- sdhci@d8000 {
+ sdhci: sdhci@d8000 {
compatible = "marvell,armada-380-sdhci";
reg-names = "sdhci", "mbus", "conf-sdio3";
reg = <0xd8000 0x1000>,
@@ -589,7 +589,7 @@
status = "disabled";
};
- usb3@f0000 {
+ xhci0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
@@ -597,7 +597,7 @@
status = "disabled";
};
- usb3@f8000 {
+ xhci1: usb3@f8000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
--
2.6.6
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^ permalink raw reply related
* Re: [PATCH 2/2] usb: ohci: s3c2410: allow probing from device tree
From: Krzysztof Kozlowski @ 2016-11-27 16:36 UTC (permalink / raw)
To: Sergio Prado
Cc: mark.rutland, devicetree, linux-samsung-soc, gregkh, linux-usb,
linux-kernel, krzk, javier, robh+dt, stern, kgene,
linux-arm-kernel
In-Reply-To: <1480085249-25014-3-git-send-email-sergio.prado@e-labworks.com>
On Fri, Nov 25, 2016 at 12:47:29PM -0200, Sergio Prado wrote:
> Allows configuring Samsung's s3c2410 USB OHCI controller using a
> devicetree.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> ---
> drivers/usb/host/ohci-s3c2410.c | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
> index 7a1919ca543a..d8e03a801f2e 100644
> --- a/drivers/usb/host/ohci-s3c2410.c
> +++ b/drivers/usb/host/ohci-s3c2410.c
> @@ -457,6 +457,13 @@ static int ohci_hcd_s3c2410_drv_resume(struct device *dev)
> .resume = ohci_hcd_s3c2410_drv_resume,
> };
>
> +static const struct of_device_id ohci_hcd_s3c2410_dt_ids[] = {
> + { .compatible = "samsung,s3c2410-ohci" },
> + { /* sentinel */ }
> +};
> +
A nit, usually MODULE_DEVICE_TABLE comes right after the table, without
a blank line.
Beside that:
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
> +MODULE_DEVICE_TABLE(of, ohci_hcd_s3c2410_dt_ids);
> +
> static struct platform_driver ohci_hcd_s3c2410_driver = {
> .probe = ohci_hcd_s3c2410_drv_probe,
> .remove = ohci_hcd_s3c2410_drv_remove,
> @@ -464,6 +471,7 @@ static int ohci_hcd_s3c2410_drv_resume(struct device *dev)
> .driver = {
> .name = "s3c2410-ohci",
> .pm = &ohci_hcd_s3c2410_pm_ops,
> + .of_match_table = ohci_hcd_s3c2410_dt_ids,
> },
> };
>
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH 1/2] dt-bindings: usb: add DT binding for s3c2410 USB OHCI controller
From: Krzysztof Kozlowski @ 2016-11-27 16:32 UTC (permalink / raw)
To: Sergio Prado
Cc: gregkh, robh+dt, mark.rutland, stern, kgene, krzk, javier,
linux-usb, devicetree, linux-kernel, linux-arm-kernel,
linux-samsung-soc
In-Reply-To: <1480085249-25014-2-git-send-email-sergio.prado@e-labworks.com>
On Fri, Nov 25, 2016 at 12:47:28PM -0200, Sergio Prado wrote:
> Adds the device tree bindings description for Samsung S3C2410 and
> compatible USB OHCI controller.
>
> Signed-off-by: Sergio Prado <sergio.prado@e-labworks.com>
> ---
> .../devicetree/bindings/usb/s3c2410-usb.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/usb/s3c2410-usb.txt
>
> diff --git a/Documentation/devicetree/bindings/usb/s3c2410-usb.txt b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt
> new file mode 100644
> index 000000000000..e45b38ce2986
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/usb/s3c2410-usb.txt
> @@ -0,0 +1,22 @@
> +Samsung S3C2410 and compatible SoC USB controller
> +
> +OHCI
> +
> +Required properties:
> + - compatible: should be "samsung,s3c2410-ohci" for USB host controller
> + - reg: address and lenght of the controller memory mapped region
s/lenght/length/
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Best regards,
Krzysztof
> + - interrupts: interrupt number for the USB OHCI controller
> + - clocks: Should reference the bus and host clocks
> + - clock-names: Should contain two strings
> + "usb-bus-host" for the USB bus clock
> + "usb-host" for the USB host clock
> +
> +Example:
> +
> +usb0: ohci@49000000 {
> + compatible = "samsung,s3c2410-ohci";
> + reg = <0x49000000 0x100>;
> + interrupts = <0 0 26 3>;
> + clocks = <&clocks UCLK>, <&clocks HCLK_USBH>;
> + clock-names = "usb-bus-host", "usb-host";
> +};
> --
> 1.9.1
>
^ permalink raw reply
* Re: [PATCH 00/39] mtd: nand: denali: 2nd round of Denali NAND IP patch bomb
From: Boris Brezillon @ 2016-11-27 16:31 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Marek Vasut, Brian Norris,
Richard Weinberger, David Woodhouse, Cyrille Pitchen, Rob Herring,
Mark Rutland
In-Reply-To: <1480183585-592-1-git-send-email-yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
On Sun, 27 Nov 2016 03:05:46 +0900
Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> As I said in the 1st round series, I am tackling on this driver
> to use it for my SoCs.
>
> The previous series was just cosmetic things, but this series
> includes *real* changes.
>
> After some more cleanups, I will start to add changes that
> are really necessary.
> One of the biggest problems I want to solve is a bunch of
> hard-coded parameters that prevent me from using this driver for
> my SoCs.
>
> I will introduce capability flags that are associated with DT
> compatible and make platform-dependent parameters overridable.
>
> I still have lots of reworks to get done (so probably 3rd round
> series will come), but I hope it is getting better and
> I am showing a big picture now.
>
I still need to carefully review some of those patches, but I must
admit I like some of the cleanups/rework you're doing here.
Thanks for all your work.
Boris
>
>
> Masahiro Yamada (39):
> mtd: nand: allow to set only one of ECC size and ECC strength from DT
> mtd: nand: denali: remove unused CONFIG option and macros
> mtd: nand: denali: remove redundant define of BANK(x)
> mtd: nand: denali: remove more unused struct members
> mtd: nand: denali: fix comment of denali_nand_info::flash_mem
> mtd: nand: denali: fix write_oob_data() function
> mtd: nand: denali: transfer OOB only when oob_required is set
> mtd: nand: denali: introduce capability flag
> mtd: nand: denali: fix erased page check code
> mtd: nand: denali: remove redundant if conditional of erased_check
> mtd: nand: denali: increment ecc_stats.failed by one per error
> mtd: nand: denali: return 0 for uncorrectable ECC error
> mtd: nand: denali: increment ecc_stats->corrected
> mtd: nand: denali: replace uint{8/16/32}_t with u{8/16/32}
> mtd: nand: denali: improve readability of handle_ecc()
> mtd: nand: denali: rename handle_ecc() to denali_sw_ecc_fixup()
> mtd: nand: denali: support HW_ECC_FIXUP capability
> mtd: nand: denali: move denali_read_page_raw() above
> denali_read_page()
> mtd: nand: denali: perform erased check against raw transferred page
> mtd: nand: denali_dt: enable HW_ECC_FIXUP capability for DT platform
> mtd: nand: denali: support 64bit capable DMA engine
> mtd: nand: denali_dt: remove dma-mask DT property
> mtd: nand: denali_dt: use pdev instead of ofdev for platform_device
> mtd: nand: denali: add NEW_N_BANKS_FORMAT capability
> mtd: nand: denali: use nand_chip to hold frequently accessed data
> mtd: nand: denali: call nand_set_flash_node() to set DT node
> mtd: nand: denali: do not set mtd->name
> mtd: nand: denali: move multi NAND fixup code to a helper function
> mtd: nand: denali: refactor multi NAND fixup code in more generic way
> mtd: nand: denali: set DEVICES_CONNECTED 1 if not set
> mtd: nand: denali: remove meaningless writes to read-only registers
> mtd: nand: denali: remove unnecessary writes to ECC_CORRECTION
> mtd: nand: denali: support 1024 byte ECC step size
> mtd: nand: denali: fix the condition for 15 bit ECC strength
> mtd: nand: denali: calculate ecc.strength and ecc.bytes generically
> mtd: nand: denali: allow to use SoC-specific ECC strength
> mtd: nand: denali: support "nand-ecc-strength" DT property
> mtd: nand: denali: remove Toshiba, Hynix specific fixup code
> mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants
>
> .../devicetree/bindings/mtd/denali-nand.txt | 19 +-
> drivers/mtd/nand/Kconfig | 11 -
> drivers/mtd/nand/denali.c | 740 ++++++++++++---------
> drivers/mtd/nand/denali.h | 84 +--
> drivers/mtd/nand/denali_dt.c | 95 ++-
> drivers/mtd/nand/denali_pci.c | 2 +
> drivers/mtd/nand/nand_base.c | 6 -
> 7 files changed, 515 insertions(+), 442 deletions(-)
>
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^ permalink raw reply
* Re: [PATCH v5 2/2] ARM: dts: add support for Turris Omnia
From: Andreas Färber @ 2016-11-27 16:20 UTC (permalink / raw)
To: Andrew Lunn
Cc: Gregory CLEMENT, Uwe Kleine-König, Mark Rutland,
Jason Cooper, devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek,
Rob Herring, Bed??icha Ko??atu,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth, Michal Hrusecky
In-Reply-To: <20161127160731.GD4574-g2DYL2Zd6BY@public.gmane.org>
Hi,
Am 27.11.2016 um 17:07 schrieb Andrew Lunn:
>> @Uwe: Note that I had already told CZ.NIC's Michal ~two weeks ago that I
>> have a WIP .dts for the Omnia - looks like no one knows what the other
>> is doing.
>
> Hi Andreas
>
> Did you post to the list? Comment on the earlier versions of the
> patches? The list is the please to coordinate these activities.
No, it was not yet fully working (only WAN NIC) and I don't have a habit
of spamming the list with RFCs. Also I was away the last two weekends.
I would've expected to get CC'ed for review though, since CZ.NIC
should've been aware of my work.
https://lists.opensuse.org/opensuse-arm/2016-11/msg00005.html
Cheers,
Andreas
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* Re: [PATCH v5 2/2] ARM: dts: add support for Turris Omnia
From: Andrew Lunn @ 2016-11-27 16:07 UTC (permalink / raw)
To: Andreas Färber
Cc: Gregory CLEMENT, Uwe Kleine-König, Mark Rutland,
Jason Cooper, devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek,
Rob Herring, Bed??icha Ko??atu,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth, Michal Hrusecky
In-Reply-To: <a7f47999-ec83-6cc8-8119-0087dee17bac-l3A5Bk7waGM@public.gmane.org>
> @Uwe: Note that I had already told CZ.NIC's Michal ~two weeks ago that I
> have a WIP .dts for the Omnia - looks like no one knows what the other
> is doing.
Hi Andreas
Did you post to the list? Comment on the earlier versions of the
patches? The list is the please to coordinate these activities.
Andrew
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^ permalink raw reply
* Re: [PATCH v5 2/2] ARM: dts: add support for Turris Omnia
From: Andreas Färber @ 2016-11-27 16:00 UTC (permalink / raw)
To: Gregory CLEMENT, Uwe Kleine-König
Cc: Mark Rutland, Andrew Lunn, Jason Cooper,
devicetree-u79uwXL29TY76Z2rM5mHXA, Tomas Hlavacek, Rob Herring,
Bedřicha Košatu,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Sebastian Hesselbarth, Michal Hrusecky
In-Reply-To: <87lgw7ilg9.fsf-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Am 25.11.2016 um 17:16 schrieb Gregory CLEMENT:
> On ven., nov. 25 2016, Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org> wrote:
>> This machine is an open hardware router by cz.nic driven by a
>> Marvell Armada 385.
>>
>> Signed-off-by: Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
>
> Applied on mvebu/dt with few changes:
[...]
>> +&spi0 {
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&spi0_pins &spi0cs0_pins>;
>> + status = "okay";
>> +
>> + spi-nor@0 {
>> + compatible = "spansion,s25fl164k", "jedec,spi-nor";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> + reg = <0>;
>> + spi-max-frequency = <40000000>;
>> +
>
> +
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> it is mandatory since v4.4 to use this pattern for partitions.
>
>
>> + partition@0 {
>> + reg = <0x0 0x00100000>;
>> + label = "U-Boot";
>> + };
>> +
>> + partition@1 {
> @0x100000
> We should use the reg value here ^
The unit name should be without 0x though. In your tree you seem to have
it correctly.
@Uwe: Note that I had already told CZ.NIC's Michal ~two weeks ago that I
have a WIP .dts for the Omnia - looks like no one knows what the other
is doing. :( My branch includes cleanups for 385 .dtsi and bug fixes for
the switch that I am not seeing in your series:
https://github.com/afaerber/linux/commits/omnia-next
I am still looking into phy backtraces when the network interfaces go down.
@Gregory: Can we please follow up with cleaning up these ugly
internal-regs and pcie-controller nodes for consistency?
Regards,
Andreas
>> + reg = <0x00100000 0x00700000>;
>> + label = "Rescue system";
>> + };
>
> + };
--
SUSE Linux GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany
GF: Felix Imendörffer, Jane Smithard, Graham Norton
HRB 21284 (AG Nürnberg)
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^ permalink raw reply
* Re: [PATCH v2 5/7] IIO: add bindings for stm32 IIO timer driver
From: Jonathan Cameron @ 2016-11-27 15:51 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: Lee Jones, robh+dt-DgEjT+Ai2ygdnm+yROfE0A, Mark Rutland,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
Linux Kernel Mailing List, Thierry Reding,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, knaack.h-Mmb7MZpHnFY,
Lars-Peter Clausen, Peter Meerwald-Stadler,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <CA+M3ks6LC5M3B01nRWh-bO79OOE11QcsypDXGpFAPzZ7Goc=Fw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 27/11/16 15:45, Benjamin Gaignard wrote:
> 2016-11-27 15:25 GMT+01:00 Jonathan Cameron <jic23-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
>> On 24/11/16 15:14, Benjamin Gaignard wrote:
>>> Define bindings for stm32 IIO timer
>>>
>>> version 2:
>>> - only keep one compatible
>>> - add DT parameters to set lists of the triggers:
>>> one list describe the triggers created by the device
>>> another one give the triggers accepted by the device
>>>
>>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
>>> ---
>>> .../bindings/iio/timer/stm32-iio-timer.txt | 41 ++++++++++++++++++++++
>>> 1 file changed, 41 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>>> new file mode 100644
>>> index 0000000..840b417
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>>> @@ -0,0 +1,41 @@
>>> +timer IIO trigger bindings for STM32
>>> +
>>> +Must be a sub-node of STM32 general purpose timer driver
>> Add a cross reference...
>
> I will add it in v3
>
>>> +
>>> +Required parameters:
>>> +- compatible: must be "st,stm32-iio-timer"
>> st,stm32-adc-timer or something like that.
>
> I would prefer use st,stm32-timer-trigger because triggers can be used
> for multiple other devices (dac, adc, timers)
>
>>> +- interrupts: Interrupt for this device
>>> + See ../interrupt-controller/st,stm32-exti.txt
>>> +
>>> +Optional parameters:
>>> +- st,input-triggers-names: List of the possible input triggers for
>>> + the device
>>> +- st,output-triggers-names: List of the possible output triggers for
>>> + the device
>> What are input / output triggers?
>
> each hardware block can be the source of triggers (output triggers) or customer
> of some other trigger (input triggers).That what I have tried to
> describe in those two
> parameters
So this is really about using one timer as a prescaler for another?
I'd be tempted in the first instance to drop that functionality and just
describe the ones that drive the device sampling.
It's complex to describe and there is enough complexity in here already
to keep things busy for a while!
>
>>> +
>>> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-iio-timer.h
>>> +
>>> +Example:
>>> + gptimer1: gptimer1@40010000 {
>>> + compatible = "st,stm32-gptimer";
>>> + reg = <0x40010000 0x400>;
>>> + clocks = <&rcc 0 160>;
>>> + clock-names = "clk_int";
>>> +
>>> + pwm1@0 {
>>> + compatible = "st,stm32-pwm";
>>> + st,pwm-num-chan = <4>;
>>> + st,breakinput;
>>> + st,complementary;
>>> + };
>>> +
>>> + iiotimer1@0 {
>>> + compatible = "st,stm32-iio-timer";
>>> + interrupts = <27>;
>>> + st,input-triggers-names = TIM5_TRGO,
>>> + TIM2_TRGO,
>>> + TIM4_TRGO,
>>> + TIM3_TRGO;
>>> + st,output-triggers-names = TIM1_TRGO;
>>> + };
>>> + };
>>>
>>
> --
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>
^ permalink raw reply
* Re: [PATCH v8 3/8] drivers:input:tsc2007: add iio interface to read external ADC input and temperature
From: H. Nikolaus Schaller @ 2016-11-27 15:47 UTC (permalink / raw)
To: Jonathan Cameron, Dmitry Torokhov
Cc: Jonathan Cameron, Sebastian Reichel, Mark Rutland,
Benoît Cousson, Tony Lindgren, Russell King, Arnd Bergmann,
Michael Welling, Mika Penttilä, Javier Martinez Canillas,
Igor Grinberg, Andrew F. Davis, Mark Brown, Rob Herring,
Alexander Stein, Eric Engestrom, Hans de Goede,
Benjamin Tissoires
In-Reply-To: <8d3fc752-e69c-f568-4f71-4f1768a3fffe@kernel.org>
Hi Jonathan,
> Am 27.11.2016 um 12:02 schrieb Jonathan Cameron <jic23@kernel.org>:
>
> On 24/11/16 18:05, H. Nikolaus Schaller wrote:
>>
>>> Am 24.11.2016 um 18:38 schrieb Jonathan Cameron <jic23@jic23.retrosnub.co.uk>:
>>>
>>>
>>>
>>> On 22 November 2016 14:02:30 GMT+00:00, "H. Nikolaus Schaller" <hns@goldelico.com> wrote:
>>>> The tsc2007 chip not only has a resistive touch screen controller but
>>>> also an external AUX adc imput which can be used for an ambient
>>>> light sensor, battery voltage monitoring or any general purpose.
>>>>
>>>> Additionally it can measure the chip temperature.
>>>>
>>>> This extension provides an iio interface for these adc channels.
>>>>
>>>> Since it is not wasting much resources and is very straightforward,
>>>> we simply provide all other adc channels as optional iio interfaces
>>>> as weel. This can be used for debugging or special applications.
>>>>
>>>> This patch also splits the tsc2007 driver in several source files:
>>>> tsc2007.h -- constants, structs and stubs
>>>> tsc2007_core.c -- functional parts of the original driver
>>>> tsc2007_iio.c -- the optional iio stuff
>>>>
>>>> Makefile magic allows to conditionally link the iio stuff
>>>> if CONFIG_IIO=y or =m in a way that it works with
>>>> CONFIG_TOUCHSCREEN_TSC2007=m.
>>>>
>>>> Signed-off-by: H. Nikolaus Schaller <hns@goldelico.com>
>>>> Reviewed-by: Jonathan Cameron <jic23@kernel.org>
>>>> ---
>>>> drivers/input/touchscreen/Makefile | 7 +
>>>> drivers/input/touchscreen/tsc2007.h | 116
>>>> ++++++++++++++++
>>>> .../touchscreen/{tsc2007.c => tsc2007_core.c} | 95 +++----------
>>>> drivers/input/touchscreen/tsc2007_iio.c | 150
>>>> +++++++++++++++++++++
>>>> 4 files changed, 294 insertions(+), 74 deletions(-)
>>>> create mode 100644 drivers/input/touchscreen/tsc2007.h
>>>> rename drivers/input/touchscreen/{tsc2007.c => tsc2007_core.c} (86%)
>>>> create mode 100644 drivers/input/touchscreen/tsc2007_iio.c
>>>>
>>>> diff --git a/drivers/input/touchscreen/Makefile
>>>> b/drivers/input/touchscreen/Makefile
>>>> index 81b8645..3be0d19 100644
>>>> --- a/drivers/input/touchscreen/Makefile
>>>> +++ b/drivers/input/touchscreen/Makefile
>>>> @@ -80,6 +80,13 @@ obj-$(CONFIG_TOUCHSCREEN_TSC_SERIO) += tsc40.o
>>>> obj-$(CONFIG_TOUCHSCREEN_TSC200X_CORE) += tsc200x-core.o
>>>> obj-$(CONFIG_TOUCHSCREEN_TSC2004) += tsc2004.o
>>>> obj-$(CONFIG_TOUCHSCREEN_TSC2005) += tsc2005.o
>>>> +tsc2007-y := tsc2007_core.o
>>>> +ifeq ($(CONFIG_IIO),y)
>>>> +tsc2007-y += tsc2007_iio.o
>>>> +endif
>>>> +ifeq ($(CONFIG_IIO),m)
>>>> +tsc2007-y += tsc2007_iio.o
>>>
>>> Not tsc2007-m ?
>>>
>>> I don't follow how this works!
>>
>> I guess tsc2007-y is an internal collector variable name
>> for multiple .o components. Sort of a "library" object.
>>
>> While
>>
>> obj-y += tsc2007.o adds it to the kernel
>> obj-m += tsc2007.o adds it to the modules
>>
>> I am not sure if my explanation is correct but it appears
>> to work that way.
>>
>> Anyways what shall we do? If CONFIG_TOUCHSCREEN_TSC2007=y
>> and IIO=m we have a problem that we need dynamic binding.
> Yes, we just need to block that particular combination. Only build in the IIO support
> if it is also built in. That's way I thought we'd want to add it tsc2007-m which would
> only be used if tsc2007 as a whole was built as a module.
Yes, that is what one could expect.
> Otherwise it would be ignored (I think!)
>
> I'm not seeing this structure anywhere else in kernel
It is also not described in that way:
http://lxr.free-electrons.com/source/Documentation/kbuild/modules.txt#L146
it only talks about obj-m and <module_name>-y but not <module_name>-m
> - hence cc'd Yann and the Kbuild list
> to see if they can offer some advices.
Thanks!
BTW, the other tsc2007 and ads7846 patches could already be merged (if there
are no more changes needed) since this one only depends on the result of applying
all others before.
>
> As a quick summary, we are looking to add IIO support to this driver in the following circumstances.
>
> IIO and this driver are modules. (ideally handling the dependencies nicely)
> IIO and this driver are both built in.
>
> Problem case is driver built in and IIO as a module.
>
> Jonathan
>>
>>>> +endif
>>>> obj-$(CONFIG_TOUCHSCREEN_TSC2007) += tsc2007.o
>>>> obj-$(CONFIG_TOUCHSCREEN_UCB1400) += ucb1400_ts.o
>>>> obj-$(CONFIG_TOUCHSCREEN_WACOM_W8001) += wacom_w8001.o
>>>> diff --git a/drivers/input/touchscreen/tsc2007.h
>>>> b/drivers/input/touchscreen/tsc2007.h
>>>> new file mode 100644
>>>> index 0000000..c25932f
>>>> --- /dev/null
>>>> +++ b/drivers/input/touchscreen/tsc2007.h
>>>> @@ -0,0 +1,116 @@
>>>> +/*
>>>> + * Copyright (c) 2008 MtekVision Co., Ltd.
>>>> + * Kwangwoo Lee <kwlee@mtekvision.com>
>>>> + *
>>>> + * Using code from:
>>>> + * - ads7846.c
>>>> + * Copyright (c) 2005 David Brownell
>>>> + * Copyright (c) 2006 Nokia Corporation
>>>> + * - corgi_ts.c
>>>> + * Copyright (C) 2004-2005 Richard Purdie
>>>> + * - omap_ts.[hc], ads7846.h, ts_osk.c
>>>> + * Copyright (C) 2002 MontaVista Software
>>>> + * Copyright (C) 2004 Texas Instruments
>>>> + * Copyright (C) 2005 Dirk Behme
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> + */
>>>> +
>>>> +#include <linux/input/touchscreen.h>
>>>> +
>>>> +#define TSC2007_MEASURE_TEMP0 (0x0 << 4)
>>>> +#define TSC2007_MEASURE_AUX (0x2 << 4)
>>>> +#define TSC2007_MEASURE_TEMP1 (0x4 << 4)
>>>> +#define TSC2007_ACTIVATE_XN (0x8 << 4)
>>>> +#define TSC2007_ACTIVATE_YN (0x9 << 4)
>>>> +#define TSC2007_ACTIVATE_YP_XN (0xa << 4)
>>>> +#define TSC2007_SETUP (0xb << 4)
>>>> +#define TSC2007_MEASURE_X (0xc << 4)
>>>> +#define TSC2007_MEASURE_Y (0xd << 4)
>>>> +#define TSC2007_MEASURE_Z1 (0xe << 4)
>>>> +#define TSC2007_MEASURE_Z2 (0xf << 4)
>>>> +
>>>> +#define TSC2007_POWER_OFF_IRQ_EN (0x0 << 2)
>>>> +#define TSC2007_ADC_ON_IRQ_DIS0 (0x1 << 2)
>>>> +#define TSC2007_ADC_OFF_IRQ_EN (0x2 << 2)
>>>> +#define TSC2007_ADC_ON_IRQ_DIS1 (0x3 << 2)
>>>> +
>>>> +#define TSC2007_12BIT (0x0 << 1)
>>>> +#define TSC2007_8BIT (0x1 << 1)
>>>> +
>>>> +#define MAX_12BIT ((1 << 12) - 1)
>>>> +
>>>> +#define ADC_ON_12BIT (TSC2007_12BIT | TSC2007_ADC_ON_IRQ_DIS0)
>>>> +
>>>> +#define READ_Y (ADC_ON_12BIT | TSC2007_MEASURE_Y)
>>>> +#define READ_Z1 (ADC_ON_12BIT | TSC2007_MEASURE_Z1)
>>>> +#define READ_Z2 (ADC_ON_12BIT | TSC2007_MEASURE_Z2)
>>>> +#define READ_X (ADC_ON_12BIT | TSC2007_MEASURE_X)
>>>> +#define PWRDOWN (TSC2007_12BIT | TSC2007_POWER_OFF_IRQ_EN)
>>>> +
>>>> +struct ts_event {
>>>> + u16 x;
>>>> + u16 y;
>>>> + u16 z1, z2;
>>>> +};
>>>> +
>>>> +struct tsc2007 {
>>>> + struct input_dev *input;
>>>> + char phys[32];
>>>> +
>>>> + struct i2c_client *client;
>>>> +
>>>> + u16 model;
>>>> + u16 x_plate_ohms;
>>>> +
>>>> + struct touchscreen_properties prop;
>>>> +
>>>> + bool report_resistance;
>>>> + u16 min_x;
>>>> + u16 min_y;
>>>> + u16 max_x;
>>>> + u16 max_y;
>>>> + u16 max_rt;
>>>> + unsigned long poll_period; /* in jiffies */
>>>> + int fuzzx;
>>>> + int fuzzy;
>>>> + int fuzzz;
>>>> +
>>>> + unsigned int gpio;
>>>> + int irq;
>>>> +
>>>> + wait_queue_head_t wait;
>>>> + bool stopped;
>>>> + bool pendown;
>>>> +
>>>> + int (*get_pendown_state)(struct device *);
>>>> + void (*clear_penirq)(void);
>>>> +
>>>> + struct mutex mlock;
>>>> + struct iio_dev *iio_dev; /* optional */
>>>> +};
>>>> +
>>>> +int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd);
>>>> +u32 tsc2007_calculate_resistance(struct tsc2007 *tsc,
>>>> + struct ts_event *tc);
>>>> +bool tsc2007_is_pen_down(struct tsc2007 *ts);
>>>> +
>>>> +#if IS_ENABLED(CONFIG_IIO)
>>>> +
>>>> +/* defined in tsc2007_iio.c */
>>>> +int tsc2007_iio_configure(struct tsc2007 *ts);
>>>> +void tsc2007_iio_unconfigure(struct tsc2007 *ts);
>>>> +
>>>> +#else /* CONFIG_IIO */
>>>> +
>>>> +static inline int tsc2007_iio_configure(struct tsc2007 *ts)
>>>> +{
>>>> + return 0;
>>>> +}
>>>> +static inline void tsc2007_iio_unconfigure(struct tsc2007 *ts)
>>>> +{
>>>> +}
>>>> +
>>>> +#endif /* CONFIG_IIO */
>>>> diff --git a/drivers/input/touchscreen/tsc2007.c
>>>> b/drivers/input/touchscreen/tsc2007_core.c
>>>> similarity index 86%
>>>> rename from drivers/input/touchscreen/tsc2007.c
>>>> rename to drivers/input/touchscreen/tsc2007_core.c
>>>> index 76b462b..812ded8 100644
>>>> --- a/drivers/input/touchscreen/tsc2007.c
>>>> +++ b/drivers/input/touchscreen/tsc2007_core.c
>>>> @@ -27,79 +27,11 @@
>>>> #include <linux/i2c.h>
>>>> #include <linux/i2c/tsc2007.h>
>>>> #include <linux/of_device.h>
>>>> -#include <linux/of.h>
>>>> #include <linux/of_gpio.h>
>>>> -#include <linux/input/touchscreen.h>
>>>> -
>>>> -#define TSC2007_MEASURE_TEMP0 (0x0 << 4)
>>>> -#define TSC2007_MEASURE_AUX (0x2 << 4)
>>>> -#define TSC2007_MEASURE_TEMP1 (0x4 << 4)
>>>> -#define TSC2007_ACTIVATE_XN (0x8 << 4)
>>>> -#define TSC2007_ACTIVATE_YN (0x9 << 4)
>>>> -#define TSC2007_ACTIVATE_YP_XN (0xa << 4)
>>>> -#define TSC2007_SETUP (0xb << 4)
>>>> -#define TSC2007_MEASURE_X (0xc << 4)
>>>> -#define TSC2007_MEASURE_Y (0xd << 4)
>>>> -#define TSC2007_MEASURE_Z1 (0xe << 4)
>>>> -#define TSC2007_MEASURE_Z2 (0xf << 4)
>>>> -
>>>> -#define TSC2007_POWER_OFF_IRQ_EN (0x0 << 2)
>>>> -#define TSC2007_ADC_ON_IRQ_DIS0 (0x1 << 2)
>>>> -#define TSC2007_ADC_OFF_IRQ_EN (0x2 << 2)
>>>> -#define TSC2007_ADC_ON_IRQ_DIS1 (0x3 << 2)
>>>> -
>>>> -#define TSC2007_12BIT (0x0 << 1)
>>>> -#define TSC2007_8BIT (0x1 << 1)
>>>> -
>>>> -#define MAX_12BIT ((1 << 12) - 1)
>>>> -
>>>> -#define ADC_ON_12BIT (TSC2007_12BIT | TSC2007_ADC_ON_IRQ_DIS0)
>>>> -
>>>> -#define READ_Y (ADC_ON_12BIT | TSC2007_MEASURE_Y)
>>>> -#define READ_Z1 (ADC_ON_12BIT | TSC2007_MEASURE_Z1)
>>>> -#define READ_Z2 (ADC_ON_12BIT | TSC2007_MEASURE_Z2)
>>>> -#define READ_X (ADC_ON_12BIT | TSC2007_MEASURE_X)
>>>> -#define PWRDOWN (TSC2007_12BIT | TSC2007_POWER_OFF_IRQ_EN)
>>>> -
>>>> -struct ts_event {
>>>> - u16 x;
>>>> - u16 y;
>>>> - u16 z1, z2;
>>>> -};
>>>> -
>>>> -struct tsc2007 {
>>>> - struct input_dev *input;
>>>> - char phys[32];
>>>> -
>>>> - struct i2c_client *client;
>>>> -
>>>> - u16 model;
>>>> - u16 x_plate_ohms;
>>>> -
>>>> - struct touchscreen_properties prop;
>>>> -
>>>> - bool report_resistance;
>>>> - u16 min_x;
>>>> - u16 min_y;
>>>> - u16 max_x;
>>>> - u16 max_y;
>>>> - u16 max_rt;
>>>> - unsigned long poll_period; /* in jiffies */
>>>> - int fuzzx;
>>>> - int fuzzy;
>>>> - int fuzzz;
>>>> -
>>>> - unsigned gpio;
>>>> - int irq;
>>>> -
>>>> - wait_queue_head_t wait;
>>>> - bool stopped;
>>>> +#include "tsc2007.h"
>>>>
>>>> - int (*get_pendown_state)(struct device *);
>>>> - void (*clear_penirq)(void);
>>>> -};
>>>>
>>>> -static inline int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd)
>>>> +int tsc2007_xfer(struct tsc2007 *tsc, u8 cmd)
>>>> {
>>>> s32 data;
>>>> u16 val;
>>>> @@ -137,7 +69,7 @@ static void tsc2007_read_values(struct tsc2007 *tsc,
>>>> struct ts_event *tc)
>>>> tsc2007_xfer(tsc, PWRDOWN);
>>>> }
>>>>
>>>> -static u32 tsc2007_calculate_resistance(struct tsc2007 *tsc,
>>>> +u32 tsc2007_calculate_resistance(struct tsc2007 *tsc,
>>>> struct ts_event *tc)
>>>> {
>>>> u32 rt = 0;
>>>> @@ -158,7 +90,7 @@ static u32 tsc2007_calculate_resistance(struct
>>>> tsc2007 *tsc,
>>>> return rt;
>>>> }
>>>>
>>>> -static bool tsc2007_is_pen_down(struct tsc2007 *ts)
>>>> +bool tsc2007_is_pen_down(struct tsc2007 *ts)
>>>> {
>>>> /*
>>>> * NOTE: We can't rely on the pressure to determine the pen down
>>>> @@ -191,7 +123,10 @@ static irqreturn_t tsc2007_soft_irq(int irq, void
>>>> *handle)
>>>> while (!ts->stopped && tsc2007_is_pen_down(ts)) {
>>>>
>>>> /* pen is down, continue with the measurement */
>>>> +
>>>> + mutex_lock(&ts->mlock);
>>>> tsc2007_read_values(ts, &tc);
>>>> + mutex_unlock(&ts->mlock);
>>>>
>>>> rt = tsc2007_calculate_resistance(ts, &tc);
>>>>
>>>> @@ -441,7 +376,8 @@ static void tsc2007_call_exit_platform_hw(void
>>>> *data)
>>>> static int tsc2007_probe(struct i2c_client *client,
>>>> const struct i2c_device_id *id)
>>>> {
>>>> - const struct tsc2007_platform_data *pdata =
>>>> dev_get_platdata(&client->dev);
>>>> + const struct tsc2007_platform_data *pdata =
>>>> + dev_get_platdata(&client->dev);
>>>> struct tsc2007 *ts;
>>>> struct input_dev *input_dev;
>>>> int err;
>>>> @@ -463,7 +399,9 @@ static int tsc2007_probe(struct i2c_client *client,
>>>> ts->client = client;
>>>> ts->irq = client->irq;
>>>> ts->input = input_dev;
>>>> +
>>>> init_waitqueue_head(&ts->wait);
>>>> + mutex_init(&ts->mlock);
>>>>
>>>> snprintf(ts->phys, sizeof(ts->phys),
>>>> "%s/input0", dev_name(&client->dev));
>>>> @@ -534,7 +472,7 @@ static int tsc2007_probe(struct i2c_client *client,
>>>> if (err < 0) {
>>>> dev_err(&client->dev,
>>>> "Failed to setup chip: %d\n", err);
>>>> - return err; /* usually, chip does not respond */
>>>> + return err; /* chip does not respond */
>>>> }
>>>>
>>>> err = input_register_device(input_dev);
>>>> @@ -544,6 +482,14 @@ static int tsc2007_probe(struct i2c_client
>>>> *client,
>>>> return err;
>>>> }
>>>>
>>>> + return tsc2007_iio_configure(ts);
>>>> +}
>>>> +
>>>> +static int tsc2007_remove(struct i2c_client *client)
>>>> +{
>>>> + struct tsc2007 *ts = i2c_get_clientdata(client);
>>>> +
>>>> + tsc2007_iio_unconfigure(ts);
>>>> return 0;
>>>> }
>>>>
>>>> @@ -569,6 +515,7 @@ static struct i2c_driver tsc2007_driver = {
>>>> },
>>>> .id_table = tsc2007_idtable,
>>>> .probe = tsc2007_probe,
>>>> + .remove = tsc2007_remove,
>>>> };
>>>>
>>>> module_i2c_driver(tsc2007_driver);
>>>> diff --git a/drivers/input/touchscreen/tsc2007_iio.c
>>>> b/drivers/input/touchscreen/tsc2007_iio.c
>>>> new file mode 100644
>>>> index 0000000..ed79944
>>>> --- /dev/null
>>>> +++ b/drivers/input/touchscreen/tsc2007_iio.c
>>>> @@ -0,0 +1,150 @@
>>>> +/*
>>>> + * Copyright (c) 2016 Golden Delicious Comp. GmbH&Co. KG
>>>> + * Nikolaus Schaller <hns@goldelico.com>
>>>> + *
>>>> + * This program is free software; you can redistribute it and/or
>>>> modify
>>>> + * it under the terms of the GNU General Public License version 2 as
>>>> + * published by the Free Software Foundation.
>>>> + */
>>>> +
>>>> +#include <linux/i2c.h>
>>>> +#include <linux/iio/iio.h>
>>>> +#include "tsc2007.h"
>>>> +
>>>> +struct tsc2007_iio {
>>>> + struct tsc2007 *ts;
>>>> +};
>>>> +
>>>> +#define TSC2007_CHAN_IIO(_chan, _name, _type, _chan_info) \
>>>> +{ \
>>>> + .datasheet_name = _name, \
>>>> + .type = _type, \
>>>> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>>>> + BIT(_chan_info), \
>>>> + .indexed = 1, \
>>>> + .channel = _chan, \
>>>> +}
>>>> +
>>>> +static const struct iio_chan_spec tsc2007_iio_channel[] = {
>>>> + TSC2007_CHAN_IIO(0, "x", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(1, "y", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(2, "z1", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(3, "z2", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(4, "adc", IIO_VOLTAGE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(5, "rt", IIO_VOLTAGE, IIO_CHAN_INFO_RAW), /* Ohms?
>>>> */
>>>> + TSC2007_CHAN_IIO(6, "pen", IIO_PRESSURE, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(7, "temp0", IIO_TEMP, IIO_CHAN_INFO_RAW),
>>>> + TSC2007_CHAN_IIO(8, "temp1", IIO_TEMP, IIO_CHAN_INFO_RAW),
>>>> +};
>>>> +
>>>> +static int tsc2007_read_raw(struct iio_dev *indio_dev,
>>>> + struct iio_chan_spec const *chan, int *val, int *val2, long mask)
>>>> +{
>>>> + struct tsc2007_iio *iio = iio_priv(indio_dev);
>>>> + struct tsc2007 *tsc = iio->ts;
>>>> + int adc_chan = chan->channel;
>>>> + int ret = 0;
>>>> +
>>>> + if (adc_chan >= ARRAY_SIZE(tsc2007_iio_channel))
>>>> + return -EINVAL;
>>>> +
>>>> + if (mask != IIO_CHAN_INFO_RAW)
>>>> + return -EINVAL;
>>>> +
>>>> + mutex_lock(&tsc->mlock);
>>>> +
>>>> + switch (chan->channel) {
>>>> + case 0:
>>>> + *val = tsc2007_xfer(tsc, READ_X);
>>>> + break;
>>>> + case 1:
>>>> + *val = tsc2007_xfer(tsc, READ_Y);
>>>> + break;
>>>> + case 2:
>>>> + *val = tsc2007_xfer(tsc, READ_Z1);
>>>> + break;
>>>> + case 3:
>>>> + *val = tsc2007_xfer(tsc, READ_Z2);
>>>> + break;
>>>> + case 4:
>>>> + *val = tsc2007_xfer(tsc, (ADC_ON_12BIT | TSC2007_MEASURE_AUX));
>>>> + break;
>>>> + case 5: {
>>>> + struct ts_event tc;
>>>> +
>>>> + tc.x = tsc2007_xfer(tsc, READ_X);
>>>> + tc.z1 = tsc2007_xfer(tsc, READ_Z1);
>>>> + tc.z2 = tsc2007_xfer(tsc, READ_Z2);
>>>> + *val = tsc2007_calculate_resistance(tsc, &tc);
>>>> + break;
>>>> + }
>>>> + case 6:
>>>> + *val = tsc2007_is_pen_down(tsc);
>>>> + break;
>>>> + case 7:
>>>> + *val = tsc2007_xfer(tsc,
>>>> + (ADC_ON_12BIT | TSC2007_MEASURE_TEMP0));
>>>> + break;
>>>> + case 8:
>>>> + *val = tsc2007_xfer(tsc,
>>>> + (ADC_ON_12BIT | TSC2007_MEASURE_TEMP1));
>>>> + break;
>>>> + }
>>>> +
>>>> + /* Prepare for next touch reading - power down ADC, enable PENIRQ */
>>>> + tsc2007_xfer(tsc, PWRDOWN);
>>>> +
>>>> + mutex_unlock(&tsc->mlock);
>>>> +
>>>> + ret = IIO_VAL_INT;
>>>> +
>>>> + return ret;
>>>> +}
>>>> +
>>>> +static const struct iio_info tsc2007_iio_info = {
>>>> + .read_raw = tsc2007_read_raw,
>>>> + .driver_module = THIS_MODULE,
>>>> +};
>>>> +
>>>> +int tsc2007_iio_configure(struct tsc2007 *ts)
>>>> +{
>>>> + int err;
>>>> + struct iio_dev *indio_dev;
>>>> + struct tsc2007_iio *iio;
>>>> +
>>>> + indio_dev = devm_iio_device_alloc(&ts->client->dev,
>>>> + sizeof(struct tsc2007_iio));
>>>> + if (!indio_dev) {
>>>> + dev_err(&ts->client->dev, "iio_device_alloc failed\n");
>>>> + return -ENOMEM;
>>>> + }
>>>> +
>>>> + iio = iio_priv(indio_dev);
>>>> + iio->ts = ts;
>>>> + ts->iio_dev = (void *) indio_dev;
>>>> +
>>>> + indio_dev->name = "tsc2007";
>>>> + indio_dev->dev.parent = &ts->client->dev;
>>>> + indio_dev->info = &tsc2007_iio_info;
>>>> + indio_dev->modes = INDIO_DIRECT_MODE;
>>>> + indio_dev->channels = tsc2007_iio_channel;
>>>> + indio_dev->num_channels = ARRAY_SIZE(tsc2007_iio_channel);
>>>> +
>>>> + err = iio_device_register(indio_dev);
>>>> + if (err < 0) {
>>>> + dev_err(&ts->client->dev, "iio_device_register() failed: %d\n",
>>>> + err);
>>>> + return err;
>>>> + }
>>>> +
>>>> + return 0;
>>>> +}
>>>> +EXPORT_SYMBOL(tsc2007_iio_configure);
>>>> +
>>>> +void tsc2007_iio_unconfigure(struct tsc2007 *ts)
>>>> +{
>>>> + struct iio_dev *indio_dev = ts->iio_dev;
>>>> +
>>>> + iio_device_unregister(indio_dev);
>>>> +}
>>>> +EXPORT_SYMBOL(tsc2007_iio_unconfigure);
>>>
>>> --
>>> Sent from my Android device with K-9 Mail. Please excuse my brevity.
>>
>
BR,
Nikolaus
^ permalink raw reply
* Re: [PATCH v2 5/7] IIO: add bindings for stm32 IIO timer driver
From: Benjamin Gaignard @ 2016-11-27 15:45 UTC (permalink / raw)
To: Jonathan Cameron
Cc: Lee Jones, robh+dt, Mark Rutland, alexandre.torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, linux-pwm, knaack.h,
Lars-Peter Clausen, Peter Meerwald-Stadler, linux-iio,
linux-arm-kernel, Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen,
Linus Walleij, Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <b2002a81-49fe-af2a-f13a-9f09831aa530@kernel.org>
2016-11-27 15:25 GMT+01:00 Jonathan Cameron <jic23@kernel.org>:
> On 24/11/16 15:14, Benjamin Gaignard wrote:
>> Define bindings for stm32 IIO timer
>>
>> version 2:
>> - only keep one compatible
>> - add DT parameters to set lists of the triggers:
>> one list describe the triggers created by the device
>> another one give the triggers accepted by the device
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../bindings/iio/timer/stm32-iio-timer.txt | 41 ++++++++++++++++++++++
>> 1 file changed, 41 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>> new file mode 100644
>> index 0000000..840b417
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>> @@ -0,0 +1,41 @@
>> +timer IIO trigger bindings for STM32
>> +
>> +Must be a sub-node of STM32 general purpose timer driver
> Add a cross reference...
I will add it in v3
>> +
>> +Required parameters:
>> +- compatible: must be "st,stm32-iio-timer"
> st,stm32-adc-timer or something like that.
I would prefer use st,stm32-timer-trigger because triggers can be used
for multiple other devices (dac, adc, timers)
>> +- interrupts: Interrupt for this device
>> + See ../interrupt-controller/st,stm32-exti.txt
>> +
>> +Optional parameters:
>> +- st,input-triggers-names: List of the possible input triggers for
>> + the device
>> +- st,output-triggers-names: List of the possible output triggers for
>> + the device
> What are input / output triggers?
each hardware block can be the source of triggers (output triggers) or customer
of some other trigger (input triggers).That what I have tried to
describe in those two
parameters
>> +
>> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-iio-timer.h
>> +
>> +Example:
>> + gptimer1: gptimer1@40010000 {
>> + compatible = "st,stm32-gptimer";
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "clk_int";
>> +
>> + pwm1@0 {
>> + compatible = "st,stm32-pwm";
>> + st,pwm-num-chan = <4>;
>> + st,breakinput;
>> + st,complementary;
>> + };
>> +
>> + iiotimer1@0 {
>> + compatible = "st,stm32-iio-timer";
>> + interrupts = <27>;
>> + st,input-triggers-names = TIM5_TRGO,
>> + TIM2_TRGO,
>> + TIM4_TRGO,
>> + TIM3_TRGO;
>> + st,output-triggers-names = TIM1_TRGO;
>> + };
>> + };
>>
>
^ permalink raw reply
* Re: [PATCH v2 6/7] IIO: add STM32 IIO timer driver
From: Jonathan Cameron @ 2016-11-27 15:42 UTC (permalink / raw)
To: Benjamin Gaignard, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1480000463-9625-7-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
I delved into the datasheet after trying to figure this out, so I think
I now sort of understand your intent, but please do answer the questions
inline.
On 24/11/16 15:14, Benjamin Gaignard wrote:
> Timers IPs can be used to generate triggers for other IPs like
> DAC, ADC or other timers.
> Each trigger may result of timer internals signals like counter enable,
> reset or edge, this configuration could be done through "master_mode"
> device attribute.
>
> A timer device could be triggered by other timers, we use the trigger
> name and is_stm32_iio_timer_trigger() function to distinguish them
> and configure IP input switch.
The presence of an IIO device in here was a suprise.. What is it actually for?
I think this needs some examples of usage to make it clear what the aim is.
I was basically expecting to see a driver instantiating one iio trigger
per timer that can act as a trigger. Those would each have sampling frequency
controls and basica enable / disable.
I'm seeing something much more complex here so additional explanation is
needed.
>
> Timer may also decide on which event (edge, level) they could
> be activated by a trigger, this configuration is done by writing in
> "slave_mode" device attribute.
Really? Sounds like magic numbers in sysfs which is never a good idea.
Please document those attributes / or break them up into elements that
don't require magic numbers.
>
> Since triggers could also be used by DAC or ADC their names are defined
> in include/dt-bindings/iio/timer/st,stm32-iio-timer.h so those IPs will be able
> to configure themselves in valid_trigger function
>
> Trigger have a "sampling_frequency" attribute which allow to configure
> timer sampling frequency without using pwm interface
>
> version 2:
> - keep only one compatible
Hmm. I'm not sure I like this as such. We are actually dealing with lots
of instances of a hardware block with only a small amount of shared
infrastrcuture (which is classic mfd teritory). So to my mind we
should have a separate device for each.
> - use st,input-triggers-names and st,output-triggers-names
> to know which triggers are accepted and/or create by the device
I'm not following why we have this cascade setup?
These are triggers, not devices in the IIO context. We need some detailed
description of why you have it setup like this. This would include the
ABI with examples of how you are using it.
Basically I don't currently understand what you are doing :(
Thanks,
Jonathan
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/iio/Kconfig | 2 +-
> drivers/iio/Makefile | 1 +
> drivers/iio/timer/Kconfig | 15 +
> drivers/iio/timer/Makefile | 1 +
> drivers/iio/timer/stm32-iio-timer.c | 448 +++++++++++++++++++++
> drivers/iio/trigger/Kconfig | 1 -
> include/dt-bindings/iio/timer/st,stm32-iio-timer.h | 23 ++
> include/linux/iio/timer/stm32-iio-timers.h | 16 +
> 8 files changed, 505 insertions(+), 2 deletions(-)
> create mode 100644 drivers/iio/timer/Kconfig
> create mode 100644 drivers/iio/timer/Makefile
> create mode 100644 drivers/iio/timer/stm32-iio-timer.c
> create mode 100644 include/dt-bindings/iio/timer/st,stm32-iio-timer.h
> create mode 100644 include/linux/iio/timer/stm32-iio-timers.h
>
> diff --git a/drivers/iio/Kconfig b/drivers/iio/Kconfig
> index 6743b18..2de2a80 100644
> --- a/drivers/iio/Kconfig
> +++ b/drivers/iio/Kconfig
> @@ -90,5 +90,5 @@ source "drivers/iio/potentiometer/Kconfig"
> source "drivers/iio/pressure/Kconfig"
> source "drivers/iio/proximity/Kconfig"
> source "drivers/iio/temperature/Kconfig"
> -
> +source "drivers/iio/timer/Kconfig"
> endif # IIO
> diff --git a/drivers/iio/Makefile b/drivers/iio/Makefile
> index 87e4c43..b797c08 100644
> --- a/drivers/iio/Makefile
> +++ b/drivers/iio/Makefile
> @@ -32,4 +32,5 @@ obj-y += potentiometer/
> obj-y += pressure/
> obj-y += proximity/
> obj-y += temperature/
> +obj-y += timer/
> obj-y += trigger/
> diff --git a/drivers/iio/timer/Kconfig b/drivers/iio/timer/Kconfig
> new file mode 100644
> index 0000000..7a73bc6
> --- /dev/null
> +++ b/drivers/iio/timer/Kconfig
> @@ -0,0 +1,15 @@
> +#
> +# Timers drivers
> +
> +menu "Timers"
> +
> +config IIO_STM32_TIMER
> + tristate "stm32 iio timer"
> + depends on ARCH_STM32
> + depends on OF
> + select IIO_TRIGGERED_EVENT
> + select MFD_STM32_GP_TIMER
> + help
> + Select this option to enable stm32 timers hardware IPs
> +
> +endmenu
> diff --git a/drivers/iio/timer/Makefile b/drivers/iio/timer/Makefile
> new file mode 100644
> index 0000000..a360c9f
> --- /dev/null
> +++ b/drivers/iio/timer/Makefile
> @@ -0,0 +1 @@
> +obj-$(CONFIG_IIO_STM32_TIMER) += stm32-iio-timer.o
> diff --git a/drivers/iio/timer/stm32-iio-timer.c b/drivers/iio/timer/stm32-iio-timer.c
> new file mode 100644
> index 0000000..35f2687
> --- /dev/null
> +++ b/drivers/iio/timer/stm32-iio-timer.c
> @@ -0,0 +1,448 @@
> +/*
> + * stm32-iio-timer.c
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/iio/iio.h>
> +#include <linux/iio/sysfs.h>
> +#include <linux/iio/timer/stm32-iio-timers.h>
> +#include <linux/iio/trigger.h>
> +#include <linux/iio/triggered_event.h>
> +#include <linux/interrupt.h>
> +#include <linux/mfd/stm32-gptimer.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +
> +#define DRIVER_NAME "stm32-iio-timer"
> +
> +struct stm32_iio_timer_dev {
> + struct device *dev;
> + struct regmap *regmap;
> + struct clk *clk;
> + int irq;
> + bool own_timer;
> + unsigned int sampling_frequency;
> + struct iio_trigger *active_trigger;
> +};
> +
> +static ssize_t _store_frequency(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_trigger_get_drvdata(trig);
> + unsigned int freq;
> + int ret;
> +
> + ret = kstrtouint(buf, 10, &freq);
> + if (ret)
> + return ret;
> +
> + stm32->sampling_frequency = freq;
> +
> + return len;
> +}
> +
> +static ssize_t _read_frequency(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct iio_trigger *trig = to_iio_trigger(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_trigger_get_drvdata(trig);
> + unsigned long long freq = stm32->sampling_frequency;
> + u32 psc, arr, cr1;
> +
> + regmap_read(stm32->regmap, TIM_CR1, &cr1);
> + regmap_read(stm32->regmap, TIM_PSC, &psc);
> + regmap_read(stm32->regmap, TIM_ARR, &arr);
> +
> + if (psc && arr && (cr1 & TIM_CR1_CEN)) {
> + freq = (unsigned long long)clk_get_rate(stm32->clk);
> + do_div(freq, psc);
> + do_div(freq, arr);
> + }
> +
> + return sprintf(buf, "%d\n", (unsigned int)freq);
> +}
> +
> +static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
> + _read_frequency,
> + _store_frequency);
> +
> +static struct attribute *stm32_trigger_attrs[] = {
> + &iio_dev_attr_sampling_frequency.dev_attr.attr,
> + NULL,
> +};
> +
> +static const struct attribute_group stm32_trigger_attr_group = {
> + .attrs = stm32_trigger_attrs,
> +};
> +
> +static const struct attribute_group *stm32_trigger_attr_groups[] = {
> + &stm32_trigger_attr_group,
> + NULL,
> +};
> +
> +static
> +ssize_t _show_master_mode(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_priv(indio_dev);
> + u32 cr2;
> +
> + regmap_read(stm32->regmap, TIM_CR2, &cr2);
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", (cr2 >> 4) & 0x7);
> +}
> +
> +static
> +ssize_t _store_master_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_priv(indio_dev);
> + u8 mode;
> + int ret;
> +
> + ret = kstrtou8(buf, 10, &mode);
> + if (ret)
> + return ret;
> +
> + if (mode > 0x7)
> + return -EINVAL;
> +
> + regmap_update_bits(stm32->regmap, TIM_CR2, TIM_CR2_MMS, mode << 4);
> +
> + return len;
> +}
> +
> +static IIO_DEVICE_ATTR(master_mode, S_IRUGO | S_IWUSR,
> + _show_master_mode,
> + _store_master_mode,
> + 0);
> +
> +static
> +ssize_t _show_slave_mode(struct device *dev,
> + struct device_attribute *attr, char *buf)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_priv(indio_dev);
> + u32 smcr;
> +
> + regmap_read(stm32->regmap, TIM_SMCR, &smcr);
> +
> + return snprintf(buf, PAGE_SIZE, "%d\n", smcr & 0x3);
> +}
> +
> +static
> +ssize_t _store_slave_mode(struct device *dev,
> + struct device_attribute *attr,
> + const char *buf, size_t len)
> +{
> + struct iio_dev *indio_dev = dev_to_iio_dev(dev);
> + struct stm32_iio_timer_dev *stm32 = iio_priv(indio_dev);
> + u8 mode;
> + int ret;
> +
> + ret = kstrtou8(buf, 10, &mode);
> + if (ret)
> + return ret;
> +
> + if (mode > 0x7)
> + return -EINVAL;
How is something called slave mode going to be fed a number between 0 and 7?
Rule of thumb is no magic numbers in sysfs and right now this is looking
rather cryptic to say the least!
> +
> + regmap_update_bits(stm32->regmap, TIM_SMCR, TIM_SMCR_SMS, mode);
> +
> + return len;
> +}
> +
> +static IIO_DEVICE_ATTR(slave_mode, S_IRUGO | S_IWUSR,
There is an iritating move (in terms of noise it's generating) to use values
directly instead fo these defines. Still if you don't fix it here I'll only
get a patch 'fixing' it soon after...
> + _show_slave_mode,
> + _store_slave_mode,
> + 0);
> +
> +static struct attribute *stm32_timer_attrs[] = {
> + &iio_dev_attr_master_mode.dev_attr.attr,
> + &iio_dev_attr_slave_mode.dev_attr.attr,
New ABI so must be documented under Documentation/ABI/testing/sysfs-bus-iio-*
> + NULL,
> +};
> +
> +static const struct attribute_group stm32_timer_attr_group = {
> + .attrs = stm32_timer_attrs,
> +};
> +
> +static int stm32_timer_start(struct stm32_iio_timer_dev *stm32)
> +{
> + unsigned long long prd, div;
> + int prescaler = 0;
> + u32 max_arr = 0xFFFF, cr1;
> +
> + if (stm32->sampling_frequency == 0)
> + return 0;
> +
> + /* Period and prescaler values depends of clock rate */
> + div = (unsigned long long)clk_get_rate(stm32->clk);
> +
> + do_div(div, stm32->sampling_frequency);
> +
> + prd = div;
> +
> + while (div > max_arr) {
> + prescaler++;
> + div = prd;
> + do_div(div, (prescaler + 1));
> + }
> + prd = div;
> +
> + if (prescaler > MAX_TIM_PSC) {
> + dev_err(stm32->dev, "prescaler exceeds the maximum value\n");
> + return -EINVAL;
> + }
> +
> + /* Check that we own the timer */
> + regmap_read(stm32->regmap, TIM_CR1, &cr1);
> + if ((cr1 & TIM_CR1_CEN) && !stm32->own_timer)
> + return -EBUSY;
> +
> + if (!stm32->own_timer) {
> + stm32->own_timer = true;
> + clk_enable(stm32->clk);
> + }
> +
> + regmap_write(stm32->regmap, TIM_PSC, prescaler);
> + regmap_write(stm32->regmap, TIM_ARR, prd - 1);
> + regmap_update_bits(stm32->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
> +
> + /* Force master mode to update mode */
> + regmap_update_bits(stm32->regmap, TIM_CR2, TIM_CR2_MMS, 0x20);
> +
> + /* Make sure that registers are updated */
> + regmap_update_bits(stm32->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
> +
> + /* Enable interrupt */
> + regmap_write(stm32->regmap, TIM_SR, 0);
> + regmap_update_bits(stm32->regmap, TIM_DIER, TIM_DIER_UIE, TIM_DIER_UIE);
> +
> + /* Enable controller */
> + regmap_update_bits(stm32->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
> +
> + return 0;
> +}
> +
> +static int stm32_timer_stop(struct stm32_iio_timer_dev *stm32)
> +{
> + if (!stm32->own_timer)
> + return 0;
> +
> + /* Stop timer */
> + regmap_update_bits(stm32->regmap, TIM_DIER, TIM_DIER_UIE, 0);
> + regmap_update_bits(stm32->regmap, TIM_CR1, TIM_CR1_CEN, 0);
> + regmap_write(stm32->regmap, TIM_PSC, 0);
> + regmap_write(stm32->regmap, TIM_ARR, 0);
> +
> + clk_disable(stm32->clk);
> +
> + stm32->own_timer = false;
> + stm32->active_trigger = NULL;
> +
> + return 0;
> +}
> +
> +static int stm32_set_trigger_state(struct iio_trigger *trig, bool state)
> +{
> + struct stm32_iio_timer_dev *stm32 = iio_trigger_get_drvdata(trig);
> +
> + stm32->active_trigger = trig;
> +
> + if (state)
> + return stm32_timer_start(stm32);
> + else
> + return stm32_timer_stop(stm32);
> +}
> +
> +static irqreturn_t stm32_timer_irq_handler(int irq, void *private)
> +{
> + struct stm32_iio_timer_dev *stm32 = private;
> + u32 sr;
> +
> + regmap_read(stm32->regmap, TIM_SR, &sr);
> + regmap_write(stm32->regmap, TIM_SR, 0);
> +
> + if ((sr & TIM_SR_UIF) && stm32->active_trigger)
> + iio_trigger_poll(stm32->active_trigger);
This is acting like a trigger cascading off another trigger?
Normally this interrupt handler would be directly associated with the
trigger hardware - in this case the timer.
> +
> + return IRQ_HANDLED;
> +}
> +
> +static const struct iio_trigger_ops timer_trigger_ops = {
> + .owner = THIS_MODULE,
> + .set_trigger_state = stm32_set_trigger_state,
> +};
> +
> +static int stm32_setup_iio_triggers(struct stm32_iio_timer_dev *stm32)
> +{
> + int ret;
> + struct property *p;
> + const char *cur = NULL;
> +
> + p = of_find_property(stm32->dev->of_node,
> + "st,output-triggers-names", NULL);
> +
> + while ((cur = of_prop_next_string(p, cur)) != NULL) {
> + struct iio_trigger *trig;
> +
> + trig = devm_iio_trigger_alloc(stm32->dev, "%s", cur);
> + if (!trig)
> + return -ENOMEM;
> +
> + trig->dev.parent = stm32->dev->parent;
> + trig->ops = &timer_trigger_ops;
> + trig->dev.groups = stm32_trigger_attr_groups;
> + iio_trigger_set_drvdata(trig, stm32);
> +
> + ret = devm_iio_trigger_register(stm32->dev, trig);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +/**
> + * is_stm32_iio_timer_trigger
> + * @trig: trigger to be checked
> + *
> + * return true if the trigger is a valid stm32 iio timer trigger
> + * either return false
> + */
> +bool is_stm32_iio_timer_trigger(struct iio_trigger *trig)
> +{
> + return (trig->ops == &timer_trigger_ops);
> +}
> +EXPORT_SYMBOL(is_stm32_iio_timer_trigger);
> +
> +static int stm32_validate_trigger(struct iio_dev *indio_dev,
> + struct iio_trigger *trig)
> +{
> + struct stm32_iio_timer_dev *dev = iio_priv(indio_dev);
> + int ret;
> +
> + if (!is_stm32_iio_timer_trigger(trig))
> + return -EINVAL;
> +
> + ret = of_property_match_string(dev->dev->of_node,
> + "st,input-triggers-names",
> + trig->name);
> +
> + if (ret < 0)
> + return ret;
> +
> + regmap_update_bits(dev->regmap, TIM_SMCR, TIM_SMCR_TS, ret << 4);
> +
> + return 0;
> +}
> +
> +static const struct iio_info stm32_trigger_info = {
> + .driver_module = THIS_MODULE,
> + .validate_trigger = stm32_validate_trigger,
> + .attrs = &stm32_timer_attr_group,
> +};
> +
> +static struct stm32_iio_timer_dev *stm32_setup_iio_device(struct device *dev)
> +{
> + struct iio_dev *indio_dev;
> + int ret;
> +
> + indio_dev = devm_iio_device_alloc(dev, sizeof(struct stm32_iio_timer_dev));
> + if (!indio_dev)
> + return NULL;
This is 'unusual'. Why does a trigger driver need an iio_dev at all?
> +
> + indio_dev->name = dev_name(dev);
> + indio_dev->dev.parent = dev;
> + indio_dev->info = &stm32_trigger_info;
> + indio_dev->modes = INDIO_EVENT_TRIGGERED;
> + indio_dev->num_channels = 0;
> + indio_dev->dev.of_node = dev->of_node;
> +
> + ret = iio_triggered_event_setup(indio_dev,
> + NULL,
> + stm32_timer_irq_handler);
So the iio_dev exists to provide the ability to fire this interrupt from
another trigger? Why do you want to do this?
> + if (ret)
> + return NULL;
> +
> + ret = devm_iio_device_register(dev, indio_dev);
> + if (ret) {
> + iio_triggered_event_cleanup(indio_dev);
> + return NULL;
> + }
> +
> + return iio_priv(indio_dev);
> +}
> +
> +static int stm32_iio_timer_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_iio_timer_dev *stm32;
> + struct stm32_gptimer_dev *mfd = dev_get_drvdata(pdev->dev.parent);
> + int ret;
> +
> + stm32 = stm32_setup_iio_device(dev);
> + if (!stm32)
> + return -ENOMEM;
> +
> + stm32->dev = dev;
> + stm32->regmap = mfd->regmap;
> + stm32->clk = mfd->clk;
> +
> + stm32->irq = platform_get_irq(pdev, 0);
> + if (stm32->irq < 0)
> + return -EINVAL;
> +
> + ret = devm_request_irq(stm32->dev, stm32->irq,
> + stm32_timer_irq_handler, IRQF_SHARED,
> + "iiotimer_event", stm32);
> + if (ret)
> + return ret;
> +
> + ret = stm32_setup_iio_triggers(stm32);
> + if (ret)
> + return ret;
> +
> + platform_set_drvdata(pdev, stm32);
> +
> + return 0;
> +}
> +
> +static int stm32_iio_timer_remove(struct platform_device *pdev)
> +{
> + struct stm32_iio_timer_dev *stm32 = platform_get_drvdata(pdev);
> +
> + iio_triggered_event_cleanup((struct iio_dev *)stm32);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id stm32_trig_of_match[] = {
> + {
> + .compatible = "st,stm32-iio-timer",
> + },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
> +
> +static struct platform_driver stm32_iio_timer_driver = {
> + .probe = stm32_iio_timer_probe,
> + .remove = stm32_iio_timer_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = stm32_trig_of_match,
> + },
> +};
> +module_platform_driver(stm32_iio_timer_driver);
> +
> +MODULE_ALIAS("platform:" DRIVER_NAME);
> +MODULE_DESCRIPTION("STMicroelectronics STM32 iio timer driver");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/iio/trigger/Kconfig b/drivers/iio/trigger/Kconfig
> index 809b2e7..f2af4fe 100644
> --- a/drivers/iio/trigger/Kconfig
> +++ b/drivers/iio/trigger/Kconfig
> @@ -46,5 +46,4 @@ config IIO_SYSFS_TRIGGER
>
> To compile this driver as a module, choose M here: the
> module will be called iio-trig-sysfs.
> -
Clear this out...
> endmenu
> diff --git a/include/dt-bindings/iio/timer/st,stm32-iio-timer.h b/include/dt-bindings/iio/timer/st,stm32-iio-timer.h
> new file mode 100644
> index 0000000..d39bf16
> --- /dev/null
> +++ b/include/dt-bindings/iio/timer/st,stm32-iio-timer.h
> @@ -0,0 +1,23 @@
> +/*
> + * st,stm32-iio-timer.h
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _DT_BINDINGS_IIO_TIMER_H_
> +#define _DT_BINDINGS_IIO_TIMER_H_
> +
> +#define TIM1_TRGO "tim1_trgo"
> +#define TIM2_TRGO "tim2_trgo"
> +#define TIM3_TRGO "tim3_trgo"
> +#define TIM4_TRGO "tim4_trgo"
> +#define TIM5_TRGO "tim5_trgo"
> +#define TIM6_TRGO "tim6_trgo"
> +#define TIM7_TRGO "tim7_trgo"
> +#define TIM8_TRGO "tim8_trgo"
> +#define TIM9_TRGO "tim9_trgo"
> +#define TIM12_TRGO "tim12_trgo"
> +
> +#endif
> diff --git a/include/linux/iio/timer/stm32-iio-timers.h b/include/linux/iio/timer/stm32-iio-timers.h
> new file mode 100644
> index 0000000..5d1b86c
> --- /dev/null
> +++ b/include/linux/iio/timer/stm32-iio-timers.h
> @@ -0,0 +1,16 @@
> +/*
> + * stm32-iio-timers.h
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#ifndef _STM32_IIO_TIMERS_H_
> +#define _STM32_IIO_TIMERS_H_
> +
> +#include <dt-bindings/iio/timer/st,stm32-iio-timer.h>
> +
> +bool is_stm32_iio_timer_trigger(struct iio_trigger *trig);
> +
> +#endif
>
^ permalink raw reply
* Re: [PATCH v2 1/7] MFD: add bindings for stm32 general purpose timer driver
From: Jonathan Cameron @ 2016-11-27 15:41 UTC (permalink / raw)
To: Benjamin Gaignard, lee.jones, robh+dt, mark.rutland,
alexandre.torgue, devicetree, linux-kernel, thierry.reding,
linux-pwm, knaack.h, lars, pmeerw, linux-iio, linux-arm-kernel
Cc: fabrice.gasnier, gerald.baeza, arnaud.pouliquen, linus.walleij,
linaro-kernel, Benjamin Gaignard
In-Reply-To: <2b751c4a-3038-4220-05d8-d745c51a3691@kernel.org>
On 27/11/16 14:10, Jonathan Cameron wrote:
> On 24/11/16 15:14, Benjamin Gaignard wrote:
>> Add bindings information for stm32 general purpose timer
>>
>> version 2:
>> - rename stm32-mfd-timer to stm32-gptimer
>> - only keep one compatible string
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../bindings/mfd/stm32-general-purpose-timer.txt | 43 ++++++++++++++++++++++
>> 1 file changed, 43 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
>>
>> diff --git a/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
>> new file mode 100644
>> index 0000000..2f10e67
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
>> @@ -0,0 +1,43 @@
>> +STM32 general purpose timer driver
>> +
>> +Required parameters:
>> +- compatible: must be "st,stm32-gptimer"
>> +
>> +- reg: Physical base address and length of the controller's
>> + registers.
>> +- clock-names: Set to "clk_int".
>> +- clocks: Phandle to the clock used by the timer module.
>> + For Clk properties, please refer to ../clock/clock-bindings.txt
>> +
>> +Optional parameters:
>> +- resets: Phandle to the parent reset controller.
>> + See ..reset/st,stm32-rcc.txt
>> +
>> +Optional subnodes:
>> +- pwm: See ../pwm/pwm-stm32.txt
>> +- iiotimer: See ../iio/timer/stm32-iio-timer.txt
> Naming issue here. Can't mention IIO as that's a linux subsystem and all
> bindings must be independent of OS.
>
> Perhaps adc-trigger-timer?
>> +
>> +Example:
>> + gptimer1: gptimer1@40010000 {
>> + compatible = "st,stm32-gptimer";
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "clk_int";
>> +
>> + pwm1@0 {
>> + compatible = "st,stm32-pwm";
>> + st,pwm-num-chan = <4>;
>> + st,breakinput;
>> + st,complementary;
>> + };
>> +
>> + iiotimer1@0 {
>> + compatible = "st,stm32-iio-timer";
> Again, avoid the use of iio in here (same issue you had with mfd in the previous
> version).
>> + interrupts = <27>;
>> + st,input-triggers-names = TIM5_TRGO,
> Docs for these should be introduced before they are used in an example.
> Same for the PWM ones above. Expand the detail fo the example as you add
> the other elements.
I've just dived into the datasheet for these timers.
http://www.st.com/content/ccc/resource/technical/document/reference_manual/3d/6d/5a/66/b4/99/40/d4/DM00031020.pdf/files/DM00031020.pdf/jcr:content/translations/en.DM00031020.pdf
I think you need a binding that describes the capabilities of each of the timers
explicitly. Down to the level of whether there is a repetition counter or not.
Each should exists as a separate entity in device tree.
They then have an existence as timers separate to the description of what they
are used for.
Here the only way we are saying they exist is by their use which doesn't feel
right to me.
So I think you need to move back to what you had in the first place. The key
thing is that ever timer needs describing fully. They are different enough
that for example the datasheet doesn't even try to describe them in one section.
(it has 4 separate chapters covering different sets of these hardware blocks).
The naming isn't really based on index, we are talking different hardware
that the datasheet authors have decided not to give different names to!
If they'd called them
advanced timers
generic timers
basic timers
really basic timers meant for driving the DAC (6 and 7)
We'd all have been quite happy with different compatible strings giving away
what they can do.
What you have here is far too specific to what you are trying to do with them
right now.
These things are separately capable of timing capture (which is I guess where
the IIO device later comes in).
So my expectation is that we end up potentially instantiating:
1) An MFD to handle the shared elements of the timers.
2) Up to 12ish timers each with separate existence as a device in the driver model
and in device tree.
(nasty corner cases here are using timers as perscalers for other timers - I'd be
tempted to leave that for now)
Note that each of these devices has a different register set I think? Any shared
bits are handled via the mfd above (if we even need that MFD which I'm starting
to doubt looking at the datasheet).
3) Up to N pwms again with there own existence in the device model. These don't
do much other than wrap the timer and stick it in output mode.
4) Up to N iio triggers - this is basically using the timer as a periodic interrupt
(though without the interrupt having visibility to the kernel) which fires off
sampling on associated ADCs.
5) Up to N iio capture devices for all channels that support timing capture.
Note there is also hardware encoder capture support in these which should be
correctly handled as well. This comes back to an ancient discussion on the
TI ecap units which have similar capabilities (driver never went anywhere but
I think that was because the author left TI).
Certainly for the IIO devices these should no be bound up into one instance
as you have done here.
Anyhow, I fear that right now this discussion is missing the key ingredient
that the hardware is horrendously variable in it's capabilities and really
is 4-5 different types of hardware that just happen to share a few bits of
their offsets in their register maps.
So after all that I'm almost more confused than I was at the start!
Jonathan
>> + TIM2_TRGO,
>> + TIM4_TRGO,
>> + TIM3_TRGO;
>> + st,output-triggers-names = TIM1_TRGO;
>> + };
>> + };
>>
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-iio" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
>
^ permalink raw reply
* Re: [PATCH 00/39] mtd: nand: denali: 2nd round of Denali NAND IP patch bomb
From: Boris Brezillon @ 2016-11-27 15:04 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Marek Vasut, Brian Norris,
Richard Weinberger, David Woodhouse, Cyrille Pitchen, Rob Herring,
Mark Rutland, Andy Shevchenko
In-Reply-To: <1480183585-592-1-git-send-email-yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
+Andy
Hi Masahiro,
On Sun, 27 Nov 2016 03:05:46 +0900
Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> As I said in the 1st round series, I am tackling on this driver
> to use it for my SoCs.
>
> The previous series was just cosmetic things, but this series
> includes *real* changes.
>
> After some more cleanups, I will start to add changes that
> are really necessary.
> One of the biggest problems I want to solve is a bunch of
> hard-coded parameters that prevent me from using this driver for
> my SoCs.
>
> I will introduce capability flags that are associated with DT
> compatible and make platform-dependent parameters overridable.
>
> I still have lots of reworks to get done (so probably 3rd round
> series will come), but I hope it is getting better and
> I am showing a big picture now.
>
Thanks for posting this 2nd round of patches, I know have a clearer
view of what you're trying to achieve.
Could you be a bit more specific about the remaining rework (your 3rd
round)?
Also, if you don't mind, I'd like to have reviews and testing from intel
users before applying the series. Can you Cc Andy (and possibly other
intel maintainers) for the next round.
Thanks,
Boris
>
>
> Masahiro Yamada (39):
> mtd: nand: allow to set only one of ECC size and ECC strength from DT
> mtd: nand: denali: remove unused CONFIG option and macros
> mtd: nand: denali: remove redundant define of BANK(x)
> mtd: nand: denali: remove more unused struct members
> mtd: nand: denali: fix comment of denali_nand_info::flash_mem
> mtd: nand: denali: fix write_oob_data() function
> mtd: nand: denali: transfer OOB only when oob_required is set
> mtd: nand: denali: introduce capability flag
> mtd: nand: denali: fix erased page check code
> mtd: nand: denali: remove redundant if conditional of erased_check
> mtd: nand: denali: increment ecc_stats.failed by one per error
> mtd: nand: denali: return 0 for uncorrectable ECC error
> mtd: nand: denali: increment ecc_stats->corrected
> mtd: nand: denali: replace uint{8/16/32}_t with u{8/16/32}
> mtd: nand: denali: improve readability of handle_ecc()
> mtd: nand: denali: rename handle_ecc() to denali_sw_ecc_fixup()
> mtd: nand: denali: support HW_ECC_FIXUP capability
> mtd: nand: denali: move denali_read_page_raw() above
> denali_read_page()
> mtd: nand: denali: perform erased check against raw transferred page
> mtd: nand: denali_dt: enable HW_ECC_FIXUP capability for DT platform
> mtd: nand: denali: support 64bit capable DMA engine
> mtd: nand: denali_dt: remove dma-mask DT property
> mtd: nand: denali_dt: use pdev instead of ofdev for platform_device
> mtd: nand: denali: add NEW_N_BANKS_FORMAT capability
> mtd: nand: denali: use nand_chip to hold frequently accessed data
> mtd: nand: denali: call nand_set_flash_node() to set DT node
> mtd: nand: denali: do not set mtd->name
> mtd: nand: denali: move multi NAND fixup code to a helper function
> mtd: nand: denali: refactor multi NAND fixup code in more generic way
> mtd: nand: denali: set DEVICES_CONNECTED 1 if not set
> mtd: nand: denali: remove meaningless writes to read-only registers
> mtd: nand: denali: remove unnecessary writes to ECC_CORRECTION
> mtd: nand: denali: support 1024 byte ECC step size
> mtd: nand: denali: fix the condition for 15 bit ECC strength
> mtd: nand: denali: calculate ecc.strength and ecc.bytes generically
> mtd: nand: denali: allow to use SoC-specific ECC strength
> mtd: nand: denali: support "nand-ecc-strength" DT property
> mtd: nand: denali: remove Toshiba, Hynix specific fixup code
> mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants
>
> .../devicetree/bindings/mtd/denali-nand.txt | 19 +-
> drivers/mtd/nand/Kconfig | 11 -
> drivers/mtd/nand/denali.c | 740 ++++++++++++---------
> drivers/mtd/nand/denali.h | 84 +--
> drivers/mtd/nand/denali_dt.c | 95 ++-
> drivers/mtd/nand/denali_pci.c | 2 +
> drivers/mtd/nand/nand_base.c | 6 -
> 7 files changed, 515 insertions(+), 442 deletions(-)
>
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^ permalink raw reply
* Re: [PATCH v2 5/7] IIO: add bindings for stm32 IIO timer driver
From: Jonathan Cameron @ 2016-11-27 14:25 UTC (permalink / raw)
To: Benjamin Gaignard, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1480000463-9625-6-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On 24/11/16 15:14, Benjamin Gaignard wrote:
> Define bindings for stm32 IIO timer
>
> version 2:
> - only keep one compatible
> - add DT parameters to set lists of the triggers:
> one list describe the triggers created by the device
> another one give the triggers accepted by the device
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> .../bindings/iio/timer/stm32-iio-timer.txt | 41 ++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
> new file mode 100644
> index 0000000..840b417
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-iio-timer.txt
> @@ -0,0 +1,41 @@
> +timer IIO trigger bindings for STM32
> +
> +Must be a sub-node of STM32 general purpose timer driver
Add a cross reference...
> +
> +Required parameters:
> +- compatible: must be "st,stm32-iio-timer"
st,stm32-adc-timer or something like that.
> +- interrupts: Interrupt for this device
> + See ../interrupt-controller/st,stm32-exti.txt
> +
> +Optional parameters:
> +- st,input-triggers-names: List of the possible input triggers for
> + the device
> +- st,output-triggers-names: List of the possible output triggers for
> + the device
What are input / output triggers?
> +
> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-iio-timer.h
> +
> +Example:
> + gptimer1: gptimer1@40010000 {
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm1@0 {
> + compatible = "st,stm32-pwm";
> + st,pwm-num-chan = <4>;
> + st,breakinput;
> + st,complementary;
> + };
> +
> + iiotimer1@0 {
> + compatible = "st,stm32-iio-timer";
> + interrupts = <27>;
> + st,input-triggers-names = TIM5_TRGO,
> + TIM2_TRGO,
> + TIM4_TRGO,
> + TIM3_TRGO;
> + st,output-triggers-names = TIM1_TRGO;
> + };
> + };
>
^ permalink raw reply
* Re: [PATCH v2 3/7] PWM: add pwm-stm32 DT bindings
From: Jonathan Cameron @ 2016-11-27 14:19 UTC (permalink / raw)
To: Benjamin Gaignard, lee.jones, robh+dt, mark.rutland,
alexandre.torgue, devicetree, linux-kernel, thierry.reding,
linux-pwm, knaack.h, lars, pmeerw, linux-iio, linux-arm-kernel
Cc: fabrice.gasnier, gerald.baeza, arnaud.pouliquen, linus.walleij,
linaro-kernel, Benjamin Gaignard
In-Reply-To: <1480000463-9625-4-git-send-email-benjamin.gaignard@st.com>
On 24/11/16 15:14, Benjamin Gaignard wrote:
> Define bindings for pwm-stm32
>
> version 2:
> - use parameters instead of compatible of handle the hardware configuration
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
> ---
> .../devicetree/bindings/pwm/pwm-stm32.txt | 37 ++++++++++++++++++++++
> 1 file changed, 37 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> new file mode 100644
> index 0000000..36263f0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> @@ -0,0 +1,37 @@
> +STMicroelectronics PWM driver bindings for STM32
> +
> +Must be a sub-node of STM32 general purpose timer driver
> +
> +Required parameters:
> +- compatible: Must be "st,stm32-pwm"
> +- pinctrl-names: Set to "default".
> +- pinctrl-0: List of phandles pointing to pin configuration nodes
> + for PWM module.
> + For Pinctrl properties, please refer to [1].
> +
> +Optional parameters:
> +- st,breakinput: Set if the hardware have break input capabilities
> +- st,breakinput-polarity: Set break input polarity. Default is 0
> + The value define the active polarity:
> + - 0 (active LOW)
> + - 1 (active HIGH)
> +- st,pwm-num-chan: Number of available PWM channels. Default is 0.
> +- st,32bits-counter: Set if the hardware have a 32 bits counter
> +- st,complementary: Set if the hardware have complementary output channels
> +
> +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
> +
> +Example:
> + gptimer1: gptimer1@40010000 {
Given the example includes chunks for the other binding, make sure to have
explicit cross references in the document.
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm1@0 {
> + compatible = "st,stm32-pwm";
> + st,pwm-num-chan = <4>;
> + st,breakinput;
> + st,complementary;
> + };
> + };
>
^ permalink raw reply
* Re: [PATCH v2 1/7] MFD: add bindings for stm32 general purpose timer driver
From: Jonathan Cameron @ 2016-11-27 14:10 UTC (permalink / raw)
To: Benjamin Gaignard, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1480000463-9625-2-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On 24/11/16 15:14, Benjamin Gaignard wrote:
> Add bindings information for stm32 general purpose timer
>
> version 2:
> - rename stm32-mfd-timer to stm32-gptimer
> - only keep one compatible string
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> .../bindings/mfd/stm32-general-purpose-timer.txt | 43 ++++++++++++++++++++++
> 1 file changed, 43 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
>
> diff --git a/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
> new file mode 100644
> index 0000000..2f10e67
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/stm32-general-purpose-timer.txt
> @@ -0,0 +1,43 @@
> +STM32 general purpose timer driver
> +
> +Required parameters:
> +- compatible: must be "st,stm32-gptimer"
> +
> +- reg: Physical base address and length of the controller's
> + registers.
> +- clock-names: Set to "clk_int".
> +- clocks: Phandle to the clock used by the timer module.
> + For Clk properties, please refer to ../clock/clock-bindings.txt
> +
> +Optional parameters:
> +- resets: Phandle to the parent reset controller.
> + See ..reset/st,stm32-rcc.txt
> +
> +Optional subnodes:
> +- pwm: See ../pwm/pwm-stm32.txt
> +- iiotimer: See ../iio/timer/stm32-iio-timer.txt
Naming issue here. Can't mention IIO as that's a linux subsystem and all
bindings must be independent of OS.
Perhaps adc-trigger-timer?
> +
> +Example:
> + gptimer1: gptimer1@40010000 {
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm1@0 {
> + compatible = "st,stm32-pwm";
> + st,pwm-num-chan = <4>;
> + st,breakinput;
> + st,complementary;
> + };
> +
> + iiotimer1@0 {
> + compatible = "st,stm32-iio-timer";
Again, avoid the use of iio in here (same issue you had with mfd in the previous
version).
> + interrupts = <27>;
> + st,input-triggers-names = TIM5_TRGO,
Docs for these should be introduced before they are used in an example.
Same for the PWM ones above. Expand the detail fo the example as you add
the other elements.
> + TIM2_TRGO,
> + TIM4_TRGO,
> + TIM3_TRGO;
> + st,output-triggers-names = TIM1_TRGO;
> + };
> + };
>
^ permalink raw reply
* Re: [PATCH 2/2] input: touchscreen: sample averaging for imx6ul_tsc
From: Fabio Estevam @ 2016-11-27 12:39 UTC (permalink / raw)
To: Guy Shapiro
Cc: Fabio Estevam, Mark Rutland, devicetree@vger.kernel.org,
Haibo Chen, Dmitry Torokhov, robh+dt@kernel.org, linux-input,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1480232698-23075-2-git-send-email-guy.shapiro@mobi-wize.com>
On Sun, Nov 27, 2016 at 5:44 AM, Guy Shapiro <guy.shapiro@mobi-wize.com> wrote:
> The i.MX6UL internal touchscreen controller contains an option to
> average upon samples. This feature reduces noise from the produced
> touch locations.
>
> This patch adds sample averaging support to the imx6ul_tsc device
> driver.
>
> Signed-off-by: Guy Shapiro <guy.shapiro@mobi-wize.com>
Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com>
^ permalink raw reply
* Re: [PATCH 1/2] Documentation: sample averaging for imx6ul_tsc
From: Fabio Estevam @ 2016-11-27 12:38 UTC (permalink / raw)
To: Guy Shapiro
Cc: Dmitry Torokhov, Fabio Estevam, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Haibo Chen,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org,
linux-input-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
In-Reply-To: <1480232698-23075-1-git-send-email-guy.shapiro-2HKgp+mgmS5l57MIdRCFDg@public.gmane.org>
On Sun, Nov 27, 2016 at 5:44 AM, Guy Shapiro <guy.shapiro-2HKgp+mgmS5l57MIdRCFDg@public.gmane.org> wrote:
> The i.MX6UL internal touchscreen controller contains an option to
> average upon samples. This feature reduces noise from the produced
> touch locations.
>
> This patch introduces a new device tree optional property for this
> feature. It provides control over the amount of averaged samples per
> touch event.
>
> The property was inspired by a similar property on the
> "brcm,iproc-touchscreen" binding.
>
> Signed-off-by: Guy Shapiro <guy.shapiro-2HKgp+mgmS5l57MIdRCFDg@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v3 0/7] mux controller abstraction and iio/i2c muxes
From: Jonathan Cameron @ 2016-11-27 12:00 UTC (permalink / raw)
To: Peter Rosin, Lars-Peter Clausen, linux-kernel
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Hartmut Knaack,
Peter Meerwald-Stadler, Jonathan Corbet, Arnd Bergmann,
Greg Kroah-Hartman, linux-i2c, devicetree, linux-iio, linux-doc
In-Reply-To: <3870654b-8cf5-30cb-74cd-c5fb1559adba@axentia.se>
On 23/11/16 11:47, Peter Rosin wrote:
> On 2016-11-22 21:58, Lars-Peter Clausen wrote:
>> On 11/21/2016 02:17 PM, Peter Rosin wrote:
>> [...]
>>> I have a piece of hardware that is using the same 3 GPIO pins
>>> to control four 8-way muxes. Three of them control ADC lines
>>> to an ADS1015 chip with an iio driver, and the last one
>>> controls the SDA line of an i2c bus. We have some deployed
>>> code to handle this, but you do not want to see it or ever
>>> hear about it. I'm not sure why I even mention it. Anyway,
>>> the situation has nagged me to no end for quite some time.
>>>
>>> So, after first getting more intimate with the i2c muxing code
>>> and later discovering the drivers/iio/inkern.c file and
>>> writing a couple of drivers making use of it, I came up with
>>> what I think is an acceptable solution; add a generic mux
>>> controller driver (and subsystem) that is shared between all
>>> instances, and combine that with an iio mux driver and a new
>>> generic i2c mux driver. The new i2c mux I called "simple"
>>> since it is only hooking the i2c muxing and the new mux
>>> controller (much like the alsa simple card driver does for ASoC).
>>
>> While abstracting this properly is all nice and good and the way it should
>> be done, but it also adds a lot of complexity and the devicetree adds a lot
>> of restrictions on what can actually be represented.
>
> This is a characterization without any specifics. But is the
> characterization true? You have two complaints, complexity
> and restrictions with bindings.
>
>> There is a certain point where the fabric on a PCB becomes so complex that
>> it deserves to be a device on its own (like the audio fabric drivers).
>> Especially when the hardware is built with a certain application in mind and
>> the driver is supposed to impose policy which reflects this application. The
>> latter can often not properly be described with the primitives the
>> devicetree can offer.
>>
>> And I think your setup is very borderline what can be done in a declarative
>> way only and it adds a lot of complexity over a more imperative solution in
>> form of a driver. I think it is worth investigating about having a driver
>> that is specific to your fabric and handles the interdependencies of the
>> discrete components.
>
> So, there are three "new" concepts:
>
> 1. Sticking a mux in front of an AD-converter. That's not all that
> novel, nor complex. Quite the opposite, I'd say. In fact, I find it
> a bit amazing that there is no in-kernel support for it.
As ever first person who needs it and has the skills to write it gets to do it ;)
Congratulations Peter ;)
>
> 2. Reusing the same GPIO-pins to drive different muxes. There are
> obviously chips that work this way (as Jonathan pointed out) and
> these will at some point get used in Linux devices. I guess they
> already are used, but that people handle them in userspace. Or
> something? If this is complex, which I question, it will still need
> support at some point. At least that's what I believe.
>
> 3. Using the same GPIO pins to mux things handled by different
> subsystems. Right, this is a bit crazy, and I'd rather not have this
> requirement, but this HW is what it is so I'll need to handle it in
> some way. It is also what stops me from falling back to a userspace
> solution, which is probably connected to why #1 and #2 is not supported
> by the kernel; everybody probably does muxing in userspace. Which is
> not necessarily a good idea, nor how it's supposed to be done...
>
> So, the only thing that's out of the ordinary (as I see it), is #3.
> The question that then needs an answer is how the in-kernel solution
> for #1 and #2 would look if we do not consider #3.
>
> And I claim that the desired solution to #1 and #2 is pretty close
> to my proposal.
>
> A. You do not want mux-controller drivers in every subsystem that
> needs them.
Agreed.
>
> B. You do not want every mux-consumer to know the specifics of how to
> operate every kind of mux; there are muxes that are not controlled
> with GPIO pins...
>
> C. When you implement muxing in a subsystem, there will in some cases
> be a need to handle parallel muxing, where there is a need to share
> mux-controllers.
>
> It just feels right to separate out the mux-controller and refer to
> it from where a mux is needed. It solves #1 and #2. And, of course,
> as a bonus #3 is also solved. But my bias is obvious.
>
> And that leads us to the restrictions with the bindings. And the same
> thing happens; the solution for #2 also solves #3.
>
> So how do you refer to a mux-controller from where it's needed? My
> first proposal used a dt phandle, for the second round I put them in
> the parent node. It would be super if it was possible for the mux-
> consumer to create the mux-controller device from the same dt
> node that is already bound to the mux-consumer. The problem is that
> the mux-consumer should not hard-code which mux-controller device it
> should create. The best I can think of is some kind of 'mux-compatible'
> attribute, that works like the standard 'compatible' attribute. That
> would simplify the bindings for the normal case (#1) where the mux-
> controller isn't shared (#2 and #3). Maybe it's possible to fix this
> issue somehow? I simply don't know?
As Lars stated, it's marginal. The question is not at what point do we
'have to' bother with a fabric driver, but rather at what point does it
make a our lives easier.
Take you nastiest mux case described earlier.
The ideal would be to represent the ADC and 3 muxes as (approximately) a
single ADC to userspace that just happens to have somewhere near 23 inputs.
To do that in device tree we need to describe
1 The adc
2 The three muxes
3 The software representation to pull all of these back into a single device.
That last part to my mind trips the balance to the point where a fabric driver
would make sense. It's not complex. Just a few lines of code tying all the
elements together without ending up with a fairly fiendish setup to describe in
device tree.
Also just wait until we have muxes stacked on muxes, with cross overs occuring.
Some of the ASoC parts can actually have effective loops if you try all the mux
combinations.
So question is do we have a 'simple case description' in device tree or force
fabric drivers everywhere? I think I'm in favour of the simple case - which handles
one of your two uses nicely. The second one to do the the recombining of channels after
the muxes, ends up looking to me like it needs a fabric driver.
Note we are only talking about bindings vs code based description here. I agree
entirely with the concept of a generic mux subsystem.
Jonathan
>
> Cheers,
> Peter
>
^ permalink raw reply
* Re: [RFC PATCH v2 5/7] iio: multiplexer: new iio category and iio-mux driver
From: Jonathan Cameron @ 2016-11-27 11:42 UTC (permalink / raw)
To: Peter Rosin, linux-kernel
Cc: Wolfram Sang, Rob Herring, Mark Rutland, Hartmut Knaack,
Lars-Peter Clausen, Peter Meerwald-Stadler, Arnd Bergmann,
Greg Kroah-Hartman, linux-i2c, devicetree, linux-iio
In-Reply-To: <365eb334-d27a-e91b-7ca7-9e10c7ede9a6@axentia.se>
On 19/11/16 22:08, Peter Rosin wrote:
> On 2016-11-19 16:49, Jonathan Cameron wrote:
>> On 17/11/16 21:48, Peter Rosin wrote:
>>> When a multiplexer changes how an iio device behaves (for example
>>> by feeding different signals to an ADC), this driver can be used
>>> create one virtual iio channel for each multiplexer state.
>>>
>>> Depends on the generic multiplexer driver.
>> I'm not really following what all the ext info stuff in here is about.
>> Could you add a little more description of that?
>
> Certainly. I have two needs for this series. The first one is simple
> when it comes to the iio part and complex because the mux is shared
> between three 8-way muxes on three of the inputs to an ADS-1015 ADC.
> The forth ADC line to the ADS-1015 is not muxed. Those three muxes
> are of course GPIO-controlled and share GPIO pins. And the GPIO
> pins also control an i2c bus that is muxed 8-ways as well. There are
> eight (possible) batteries, and we monitor voltage/current/temp with
> the 3 muxed ADC lines, and 8 chargers sit on i2c behind the i2c mux.
> I guess it felt natural for the HW designer to select battery with
> the GPIO lines, but that do not fit too well with the code as it
> is without this series...
>
> For this first need, the iio mux does not need ext_info.
>
> The second need is simple in the mux part but worse in the iio
> department. It's another 8-way mux that simply muxes an ADC line,
> so that is simple. However, the ADC line is the envelope detector
> that just got added to linux-next, and it has two ext_info
> attributes that needs to be set differently for different mux
> states. Two of the states need "invert" to be false, the rest need
> "invert" to be true. And it is also preferable to have different
> values for "compare_interval" for different mux states since the
> signals on the diffrent mux states have the different frequency
> characteristics.
>
> True, I could have the ext-info attributes go straight through
> the mux, and just start by writing values to "invert"
> and "compare_interval", and only then read a sample. But then I
> would need to lock out other users during the duration of this
> transaction. I believe that the best place to put that lock is
> in the iio mux (when it locks its control-mux) and not leave it
> to userspace to solve this in some brittle cooperative manner.
>
>> Perhaps an example of how it is used and what the resulting interface
>> looks like?
>
> The resulting interface is just a copy of the (ext_info) interface
> exposed by the parent channel (with a cache that is rewritten to
> the parent on every iio mux state change). I have plans to add code
> to not rewrite ext_info attributes that have never been changed in
> any mux state.
>
> Below I have an example file listing.
>
> device0 is a dpot (mcp4561).
> device1 is a dac (dpot-dac, wrapping the above dpot).
> device2 is an adc (envelope-detector, wrapping the above dac)
> device3 is a mux (iio-mux, wrapping the above adc)
>
> The 8-way iio-mux have no signals attached on mux states 0 and 1, which
> is why the first channel for device 3 is in_altvoltage2.
>
> Ultimately, I would like some knob to hide devices 0, 1 and 2 from
> userspace. They need/should only be visible to in-kernel users. Or
> is there such a knob already?
>
There isn't and this feeds into what Lars was suggesting with a fabric
driver. The complexity of the description in device tree is getting really
very nasty indeed, perhaps we are better off allowing for complex cases
to have a driver that directly hooks into all the relevant elements and
can do magic channel remapping etc.
That could then register the 3 muxes and acquire all the chanenls required
to build a single many channel device that hides all the complexity from userspace.
I've considered working out how to do an IIO multiplexer before in software which would
allow us to make 'fake' devices that wrap multiple physical devices. In the general
case it has always felt to complex as we'd want it to handle triggered and buffered
data flows. That brings all sorts of nasty data alignment problems with it as there
is no guarantee the devices are producing aligned data at all.
In the specific case though a driver can bundle up everything it needs to create
a pseudo device (for triggered flows we'd probably need a little magic to hold off the
trigger but that's not hard). With sysfs only access it would be simple to do but
hard to describe. Hence bringing us back to fabric drivers.
Thanks for the description. Good to understand what you are trying to handle.
Jonathan
> Cheers,
> Peter
>
> $ ls /sys/bus/iio/devices/iio\:device*
> /sys/bus/iio/devices/iio:device0:
> dev out_resistance_raw_available
> name out_resistance_scale
> of_node power
> out_resistance0_raw subsystem
> out_resistance1_raw uevent
>
> /sys/bus/iio/devices/iio:device1:
> dev out_voltage0_scale
> name power
> of_node subsystem
> out_voltage0_raw uevent
> out_voltage0_raw_available
>
> /sys/bus/iio/devices/iio:device2:
> dev name
> in_altvoltage0_compare_interval of_node
> in_altvoltage0_invert power
> in_altvoltage0_raw subsystem
> in_altvoltage0_scale uevent
>
> /sys/bus/iio/devices/iio:device3:
> dev in_altvoltage5_raw
> in_altvoltage2_compare_interval in_altvoltage5_scale
> in_altvoltage2_invert in_altvoltage6_compare_interval
> in_altvoltage2_raw in_altvoltage6_invert
> in_altvoltage2_scale in_altvoltage6_raw
> in_altvoltage3_compare_interval in_altvoltage6_scale
> in_altvoltage3_invert in_altvoltage7_compare_interval
> in_altvoltage3_raw in_altvoltage7_invert
> in_altvoltage3_scale in_altvoltage7_raw
> in_altvoltage4_compare_interval in_altvoltage7_scale
> in_altvoltage4_invert name
> in_altvoltage4_raw of_node
> in_altvoltage4_scale power
> in_altvoltage5_compare_interval subsystem
> in_altvoltage5_invert uevent
>
^ permalink raw reply
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