* Re: [PATCH] mmc: pwrseq: add support for Marvell SD8787 chip
From: Rob Herring @ 2016-11-29 14:51 UTC (permalink / raw)
To: Ulf Hansson
Cc: Matt Ranostay,
linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-mmc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Tony Lindgren,
Mark Rutland, Srinivas Kandagatla
In-Reply-To: <CAPDyKFr=TE+EuZ9rZV3ygsjBFN_mRrE2imkFa-wQs_ykM5d+cQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Nov 28, 2016 at 9:54 AM, Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> [...]
>
>>> +
>>> +Example:
>>> +
>>> + wifi_pwrseq: wifi_pwrseq {
>>> + compatible = "mmc-pwrseq-sd8787";
>>> + pwrdn-gpio = <&twl_gpio 0 GPIO_ACTIVE_LOW>;
>>> + reset-gpio = <&twl_gpio 1 GPIO_ACTIVE_LOW>;
>>> + }
>>> diff --git a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt b/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
>>> index c421aba0a5bc..08fd65d35725 100644
>>> --- a/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
>>> +++ b/Documentation/devicetree/bindings/net/wireless/marvell-sd8xxx.txt
>>> @@ -32,6 +32,9 @@ Optional properties:
>>> so that the wifi chip can wakeup host platform under certain condition.
>>> during system resume, the irq will be disabled to make sure
>>> unnecessary interrupt is not received.
>>> + - vmmc-supply: a phandle of a regulator, supplying VCC to the card
>>
>> This is why pwrseq is wrong. You have some properties in the card node
>> and some in pwrseq node. Everything should be in the card node.
>
> Put "all" in the card node, just doesn't work for MMC. Particular in
> cases when we have removable cards, as then it would be wrong to have
> a card node.
When is there a problem with removable cards? The connector is
standard and everything needed (CD, VMMC, VDDIO, etc.) is defined in
the host controller node. If that isn't sufficient, then we should
start defining a connector node.
> The mmc pwrseq DT bindings just follows the legacy approach for MMC
> and that's why the pwrseq handle is at the controller node. Yes, would
> could have done it differently, but this is the case now, so we will
> have to accept that.
We're stuck with supporting the existing cases. That doesn't mean
we're stuck with the same thing for new cases.
Rob
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^ permalink raw reply
* Re: [PATCH v3 4/4] [media] dt-bindings: add TI VPIF documentation
From: Rob Herring @ 2016-11-29 14:41 UTC (permalink / raw)
To: Kevin Hilman
Cc: linux-media-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Hans Verkuil,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Sekhar Nori,
Axel Haslam, Bartosz Gołaszewski, Alexandre Bailon,
David Lechner
In-Reply-To: <m2shqbs0eu.fsf-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On Mon, Nov 28, 2016 at 4:30 PM, Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> Hi Rob,
>
> Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> writes:
>
>> On Tue, Nov 22, 2016 at 07:52:44AM -0800, Kevin Hilman wrote:
>>> Signed-off-by: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
>>> ---
>>> .../bindings/media/ti,da850-vpif-capture.txt | 65 ++++++++++++++++++++++
>>> .../devicetree/bindings/media/ti,da850-vpif.txt | 8 +++
>>> 2 files changed, 73 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/media/ti,da850-vpif-capture.txt
>>> create mode 100644 Documentation/devicetree/bindings/media/ti,da850-vpif.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/media/ti,da850-vpif-capture.txt b/Documentation/devicetree/bindings/media/ti,da850-vpif-capture.txt
>>> new file mode 100644
>>> index 000000000000..c447ac482c1d
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/media/ti,da850-vpif-capture.txt
>>> @@ -0,0 +1,65 @@
>>> +Texas Instruments VPIF Capture
>>> +------------------------------
>>> +
>>> +The TI Video Port InterFace (VPIF) capture component is the primary
>>> +component for video capture on the DA850 family of TI DaVinci SoCs.
>>> +
>>> +TI Document number reference: SPRUH82C
>>> +
>>> +Required properties:
>>> +- compatible: must be "ti,da850-vpif-capture"
>>> +- reg: physical base address and length of the registers set for the device;
>>> +- interrupts: should contain IRQ line for the VPIF
>>> +
>>> +VPIF capture has a 16-bit parallel bus input, supporting 2 8-bit
>>> +channels or a single 16-bit channel. It should contain at least one
>>> +port child node with child 'endpoint' node. Please refer to the
>>> +bindings defined in
>>> +Documentation/devicetree/bindings/media/video-interfaces.txt.
>>> +
>>> +Example using 2 8-bit input channels, one of which is connected to an
>>> +I2C-connected TVP5147 decoder:
>>> +
>>> + vpif_capture: video-capture@0x00217000 {
>>> + reg = <0x00217000 0x1000>;
>>> + interrupts = <92>;
>>> +
>>> + port {
>>> + vpif_ch0: endpoint@0 {
>>> + reg = <0>;
>>> + bus-width = <8>;
>>> + remote-endpoint = <&composite>;
>>> + };
>>> +
>>> + vpif_ch1: endpoint@1 {
>>
>> I think probably channels here should be ports rather than endpoints.
>> AIUI, having multiple endpoints is for cases like a mux or 1 to many
>> connections. There's only one data flow, but multiple sources or sinks.
>
> Looking at this closer... , I used an endpoint because it's bascially a
> 16-bit parallel bus, that can be configured as (up to) 2 8-bit
> "channels. So, based on the video-interfaces.txt doc, I configured this
> as a single port, with (up to) 2 endpoints. That also allows me to
> connect output of the decoder directly, using the remote-endpoint
> property.
>
> So I guess I'm not fully understanding your suggestion.
NM, looks like video-interfaces.txt actually spells out this case and
defines doing it as you did.
Rob
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* [PATCH 5/5] arm64: dts: marvell: Enable spi0 on the board Armada-3720-db
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <20161129143939.3191-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
This commit enables the device node spi0 on the official development
board for the Marvell Armada 3700. It also adds sub-node for the 128Mb
SPI-NOR present on the board.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 30 ++++++++++++++++++++++++++
1 file changed, 30 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
index 1372e9a6..0c4eb98 100644
--- a/arch/arm64/boot/dts/marvell/armada-3720-db.dts
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -67,6 +67,36 @@
status = "okay";
};
+&spi0 {
+ status = "okay";
+
+ m25p80@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <108000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ partition@0 {
+ label = "bootloader";
+ reg = <0x0 0x200000>;
+ };
+ partition@200000 {
+ label = "U-boot Env";
+ reg = <0x200000 0x10000>;
+ };
+ partition@210000 {
+ label = "Linux";
+ reg = <0x210000 0xDF0000>;
+ };
+ };
+ };
+};
+
/* Exported on the micro USB connector CON32 through an FTDI */
&uart0 {
status = "okay";
--
2.9.3
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* [PATCH 4/5] arm64: dts: marvell: Add definition of SPI controller for Armada 3700
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <20161129143939.3191-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Armada 3700 SoC has an SPI Controller, this commit adds the definition
of the SPI device node at the SoC level.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
index e9bd587..84e4f57 100644
--- a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
@@ -98,6 +98,19 @@
/* 32M internal register @ 0xd000_0000 */
ranges = <0x0 0x0 0xd0000000 0x2000000>;
+ spi0: spi@10600 {
+ compatible = "marvell,armada-3700-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10600 0x5d>;
+ clocks = <&nb_periph_clk 7>;
+ clock-frequency = <200000000>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ max-frequency = <66000000>;
+ num-cs = <4>;
+ status = "disabled";
+ };
+
uart0: serial@12000 {
compatible = "marvell,armada-3700-uart";
reg = <0x12000 0x400>;
--
2.9.3
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* [PATCH 3/5] dt-bindings: spi: Add documentation for the Armada 3700 SPI Controller
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <20161129143939.3191-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
This adds the devicetree bindings documentation for the SPI controller
present in the Marvell Armada 3700 SoCs.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
.../devicetree/bindings/spi/spi-armada-3700.txt | 25 ++++++++++++++++++++++
1 file changed, 25 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-armada-3700.txt
diff --git a/Documentation/devicetree/bindings/spi/spi-armada-3700.txt b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt
new file mode 100644
index 0000000..1564aa8
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/spi-armada-3700.txt
@@ -0,0 +1,25 @@
+* Marvell Armada 3700 SPI Controller
+
+Required Properties:
+
+- compatible: should be "marvell,armada-3700-spi"
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: The interrupt number. The interrupt specifier format depends on
+ the interrupt controller and of its driver.
+- clocks: Must contain the clock source, usually from the North Bridge clocks.
+- num-cs: The number of chip selects that is supported by this SPI Controller
+- #address-cells: should be 1.
+- #size-cells: should be 0.
+
+Example:
+
+ spi0: spi@10600 {
+ compatible = "marvell,armada-3700-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10600 0x5d>;
+ clocks = <&nb_perih_clk 7>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
+ num-cs = <4>;
+ };
--
2.9.3
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* [PATCH 2/5] spi: armada-3700: Add support for the FIFO mode
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <20161129143939.3191-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
In FIFO mode, dedicated registers are used to store the instruction,
the address, the read mode and the data. Write and Read FIFO are used
to store the outcoming or incoming data. The CPU no longer has to assert
each byte. The data FIFOs are accessible via DMA or by the CPU.
This commit adds support for the FIFO mode with the CPU.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/spi/spi-armada-3700.c | 408 ++++++++++++++++++++++++++++++++++++++++--
1 file changed, 398 insertions(+), 10 deletions(-)
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
index 1e8298c..c4febe4 100644
--- a/drivers/spi/spi-armada-3700.c
+++ b/drivers/spi/spi-armada-3700.c
@@ -99,19 +99,28 @@
/* A3700_SPI_IF_TIME_REG */
#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
+/* Flags and macros for struct a3700_spi */
+#define HAS_FIFO BIT(0)
+#define A3700_INSTR_CNT 1
+#define A3700_ADDR_CNT 3
+#define A3700_DUMMY_CNT 1
+
struct a3700_spi {
struct spi_master *master;
void __iomem *base;
struct clk *clk;
unsigned int irq;
unsigned int flags;
- bool last_xfer;
+ bool xmit_data;
const u8 *tx_buf;
u8 *rx_buf;
size_t buf_len;
u8 byte_len;
u32 wait_mask;
struct completion done;
+ u32 addr_cnt;
+ u32 instr_cnt;
+ size_t hdr_cnt;
};
static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
@@ -180,12 +189,15 @@ static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
return 0;
}
-static void a3700_spi_fifo_mode_unset(struct a3700_spi *a3700_spi)
+static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi)
{
u32 val;
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
- val &= ~A3700_SPI_FIFO_MODE;
+ if (a3700_spi->flags & HAS_FIFO)
+ val |= A3700_SPI_FIFO_MODE;
+ else
+ val &= ~A3700_SPI_FIFO_MODE;
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
}
@@ -255,11 +267,30 @@ static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
a3700_spi->byte_len = len;
}
+static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi)
+{
+ int timeout = A3700_SPI_TIMEOUT;
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val |= A3700_SPI_FIFO_FLUSH;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ while (--timeout) {
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ if (!(val & A3700_SPI_FIFO_FLUSH))
+ return 0;
+ udelay(1);
+ }
+
+ return -ETIMEDOUT;
+}
+
static int a3700_spi_init(struct a3700_spi *a3700_spi)
{
struct spi_master *master = a3700_spi->master;
u32 val;
- int i;
+ int i, ret = 0;
/* Reset SPI unit */
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
@@ -278,10 +309,8 @@ static int a3700_spi_init(struct a3700_spi *a3700_spi)
for (i = 0; i < master->num_chipselect; i++)
a3700_spi_deactivate_cs(a3700_spi, i);
- a3700_spi_pin_mode_set(a3700_spi, 0);
-
- /* Be sure that FIFO mode is disabled */
- a3700_spi_fifo_mode_unset(a3700_spi);
+ /* Enable FIFO mode */
+ a3700_spi_fifo_mode_set(a3700_spi);
/* Set SPI mode */
a3700_spi_mode_set(a3700_spi, master->mode_bits);
@@ -294,7 +323,7 @@ static int a3700_spi_init(struct a3700_spi *a3700_spi)
spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
- return 0;
+ return ret;
}
static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
@@ -380,6 +409,21 @@ static bool a3700_spi_transfer_wait(struct spi_device *spi,
return a3700_spi_wait_completion(spi);
}
+static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi,
+ unsigned int bytes)
+{
+ u32 val;
+
+ if (a3700_spi->flags & HAS_FIFO) {
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT);
+ val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT;
+ val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT);
+ val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+ }
+}
+
static int a3700_spi_transfer_setup(struct spi_device *spi,
struct spi_transfer *xfer)
{
@@ -396,6 +440,8 @@ static int a3700_spi_transfer_setup(struct spi_device *spi,
/* Set byte length */
a3700_spi_bytelen_set(a3700_spi, byte_len);
+ a3700_spi_fifo_thres_set(a3700_spi, byte_len);
+
return ret;
}
@@ -456,6 +502,168 @@ static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
}
+static void a3700_spi_header_set(struct a3700_spi *a3700_spi)
+{
+ u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0;
+ u32 val = 0;
+
+ /* Clear the header registers */
+ spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0);
+ spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0);
+ spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0);
+
+ /* Set header counters */
+ if (a3700_spi->tx_buf) {
+ if (a3700_spi->buf_len <= a3700_spi->instr_cnt) {
+ instr_cnt = a3700_spi->buf_len;
+ } else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt +
+ a3700_spi->addr_cnt)) {
+ instr_cnt = a3700_spi->instr_cnt;
+ addr_cnt = a3700_spi->buf_len - instr_cnt;
+ } else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) {
+ instr_cnt = a3700_spi->instr_cnt;
+ addr_cnt = a3700_spi->addr_cnt;
+ /* Need to handle the normal write case with 1 byte
+ * data
+ */
+ if (!a3700_spi->tx_buf[instr_cnt + addr_cnt])
+ dummy_cnt = a3700_spi->buf_len - instr_cnt -
+ addr_cnt;
+ }
+ val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK)
+ << A3700_SPI_INSTR_CNT_BIT);
+ val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK)
+ << A3700_SPI_ADDR_CNT_BIT);
+ val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK)
+ << A3700_SPI_DUMMY_CNT_BIT);
+ }
+ spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val);
+
+ /* Update the buffer length to be transferred */
+ a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt);
+
+ /* Set Instruction */
+ val = 0;
+ while (instr_cnt--) {
+ val = (val << 8) | a3700_spi->tx_buf[0];
+ a3700_spi->tx_buf++;
+ }
+ spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val);
+
+ /* Set Address */
+ val = 0;
+ while (addr_cnt--) {
+ val = (val << 8) | a3700_spi->tx_buf[0];
+ a3700_spi->tx_buf++;
+ }
+ spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val);
+}
+
+static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+ return (val & A3700_SPI_WFIFO_FULL);
+}
+
+static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi)
+{
+ u32 val;
+ int i = 0;
+
+ while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) {
+ val = 0;
+ if (a3700_spi->buf_len >= 4) {
+ val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf);
+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
+
+ a3700_spi->buf_len -= 4;
+ a3700_spi->tx_buf += 4;
+ } else {
+ /*
+ * If the remained buffer length is less than 4-bytes,
+ * we should pad the write buffer with all ones. So that
+ * it avoids overwrite the unexpected bytes following
+ * the last one.
+ */
+ val = GENMASK(31, 0);
+ while (a3700_spi->buf_len) {
+ val &= ~(0xff << (8 * i));
+ val |= *a3700_spi->tx_buf++ << (8 * i);
+ i++;
+ a3700_spi->buf_len--;
+
+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG,
+ val);
+ }
+ break;
+ }
+ }
+
+ return 0;
+}
+
+static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi)
+{
+ u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+
+ return (val & A3700_SPI_RFIFO_EMPTY);
+}
+
+static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi)
+{
+ u32 val;
+
+ while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) {
+ val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
+ if (a3700_spi->buf_len >= 4) {
+ u32 data = le32_to_cpu(val);
+ memcpy(a3700_spi->rx_buf, &data, 4);
+
+ a3700_spi->buf_len -= 4;
+ a3700_spi->rx_buf += 4;
+ } else {
+ /*
+ * When remain bytes is not larger than 4, we should
+ * avoid memory overwriting and just write the left rx
+ * buffer bytes.
+ */
+ while (a3700_spi->buf_len) {
+ *a3700_spi->rx_buf = val & 0xff;
+ val >>= 8;
+
+ a3700_spi->buf_len--;
+ a3700_spi->rx_buf++;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi)
+{
+ int timeout = A3700_SPI_TIMEOUT;
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val |= A3700_SPI_XFER_STOP;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ while (--timeout) {
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ if (!(val & A3700_SPI_XFER_START))
+ break;
+ udelay(1);
+ }
+
+ a3700_spi_fifo_flush(a3700_spi);
+
+ val &= ~A3700_SPI_XFER_STOP;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+}
+
static int a3700_spi_prepare_message(struct spi_master *master,
struct spi_message *message)
{
@@ -469,12 +677,28 @@ static int a3700_spi_prepare_message(struct spi_master *master,
return 0;
}
+static int a3700_spi_prepare_fifo_message(struct spi_master *master,
+ struct spi_message *message)
+{
+ struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
+ int ret;
+
+ /* Flush the FIFOs */
+ ret = a3700_spi_fifo_flush(a3700_spi);
+ if (ret)
+ return ret;
+
+ a3700_spi_bytelen_set(a3700_spi, 4);
+
+ return 0;
+}
+
static int a3700_spi_transfer_one(struct spi_master *master,
struct spi_device *spi,
struct spi_transfer *xfer)
{
struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
- int ret = 0;
+ int ret;
ret = a3700_spi_transfer_setup(spi, xfer);
if (ret)
@@ -513,6 +737,153 @@ static int a3700_spi_transfer_one(struct spi_master *master,
return ret;
}
+static int a3700_spi_fifo_transfer_one(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
+ int ret = 0, timeout = A3700_SPI_TIMEOUT;
+ unsigned int nbits = 0;
+ u32 val;
+
+ ret = a3700_spi_transfer_setup(spi, xfer);
+ if (ret)
+ goto error;
+
+ a3700_spi->tx_buf = xfer->tx_buf;
+ a3700_spi->rx_buf = xfer->rx_buf;
+ a3700_spi->buf_len = xfer->len;
+
+ /* SPI transfer headers */
+ a3700_spi_header_set(a3700_spi);
+
+ if (xfer->tx_buf)
+ nbits = xfer->tx_nbits;
+ else if (xfer->rx_buf)
+ nbits = xfer->rx_nbits;
+
+ a3700_spi_pin_mode_set(a3700_spi, nbits);
+
+ if (xfer->rx_buf) {
+ /* Set read data length */
+ spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG,
+ a3700_spi->buf_len);
+ /* Start READ transfer */
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~A3700_SPI_RW_EN;
+ val |= A3700_SPI_XFER_START;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+ } else if (xfer->tx_buf) {
+ /* Start Write transfer */
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN);
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ /*
+ * If there are data to be written to the SPI device, xmit_data
+ * flag is set true; otherwise the instruction in SPI_INSTR does
+ * not require data to be written to the SPI device, then
+ * xmit_data flag is set false.
+ */
+ a3700_spi->xmit_data = (a3700_spi->buf_len != 0);
+ }
+
+ while (a3700_spi->buf_len) {
+ if (a3700_spi->tx_buf) {
+ /* Wait wfifo ready */
+ if (!a3700_spi_transfer_wait(spi,
+ A3700_SPI_WFIFO_RDY)) {
+ dev_err(&spi->dev,
+ "wait wfifo ready timed out\n");
+ ret = -ETIMEDOUT;
+ goto error;
+ }
+ /* Fill up the wfifo */
+ ret = a3700_spi_fifo_write(a3700_spi);
+ if (ret)
+ goto error;
+ } else if (a3700_spi->rx_buf) {
+ /* Wait rfifo ready */
+ if (!a3700_spi_transfer_wait(spi,
+ A3700_SPI_RFIFO_RDY)) {
+ dev_err(&spi->dev,
+ "wait rfifo ready timed out\n");
+ ret = -ETIMEDOUT;
+ goto error;
+ }
+ /* Drain out the rfifo */
+ ret = a3700_spi_fifo_read(a3700_spi);
+ if (ret)
+ goto error;
+ }
+ }
+
+ /*
+ * Stop a write transfer in fifo mode:
+ * - wait all the bytes in wfifo to be shifted out
+ * - set XFER_STOP bit
+ * - wait XFER_START bit clear
+ * - clear XFER_STOP bit
+ * Stop a read transfer in fifo mode:
+ * - the hardware is to reset the XFER_START bit
+ * after the number of bytes indicated in DIN_CNT
+ * register
+ * - just wait XFER_START bit clear
+ */
+ if (a3700_spi->tx_buf) {
+ if (a3700_spi->xmit_data) {
+ /*
+ * If there are data written to the SPI device, wait
+ * until SPI_WFIFO_EMPTY is 1 to wait for all data to
+ * transfer out of write FIFO.
+ */
+ if (!a3700_spi_transfer_wait(spi,
+ A3700_SPI_WFIFO_EMPTY)) {
+ dev_err(&spi->dev, "wait wfifo empty timed out\n");
+ return -ETIMEDOUT;
+ }
+ } else {
+ /*
+ * If the instruction in SPI_INSTR does not require data
+ * to be written to the SPI device, wait until SPI_RDY
+ * is 1 for the SPI interface to be in idle.
+ */
+ if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
+ dev_err(&spi->dev, "wait xfer ready timed out\n");
+ return -ETIMEDOUT;
+ }
+ }
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val |= A3700_SPI_XFER_STOP;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+ }
+
+ while (--timeout) {
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ if (!(val & A3700_SPI_XFER_START))
+ break;
+ udelay(1);
+ }
+
+ if (timeout == 0) {
+ dev_err(&spi->dev, "wait transfer start clear timed out\n");
+ ret = -ETIMEDOUT;
+ goto error;
+ }
+
+ val &= ~A3700_SPI_XFER_STOP;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+ goto out;
+
+error:
+ a3700_spi_transfer_abort_fifo(a3700_spi);
+out:
+ spi_finalize_current_transfer(master);
+
+ return ret;
+}
+
static int a3700_spi_unprepare_message(struct spi_master *master,
struct spi_message *message)
{
@@ -600,6 +971,23 @@ static int a3700_spi_probe(struct platform_device *pdev)
goto error;
}
+ if (of_device_is_compatible(of_node, "marvell,armada-3700-spi")) {
+ master->prepare_message = a3700_spi_prepare_fifo_message;
+ master->transfer_one = a3700_spi_fifo_transfer_one;
+
+ spi->flags |= HAS_FIFO;
+ spi->instr_cnt = A3700_INSTR_CNT;
+ spi->addr_cnt = A3700_ADDR_CNT;
+ spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT +
+ A3700_DUMMY_CNT;
+ master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL |
+ SPI_RX_QUAD | SPI_TX_QUAD);
+ } else {
+ master->prepare_message = a3700_spi_prepare_message;
+ master->transfer_one = a3700_spi_transfer_one;
+ master->unprepare_message = a3700_spi_unprepare_message;
+ }
+
ret = a3700_spi_init(spi);
if (ret)
goto error_clk;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH 1/5] spi: Add basic support for Armada 3700 SPI Controller
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <20161129143939.3191-1-romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
Marvell Armada 3700 SoC comprises an SPI Controller. This Controller
supports up to 4 SPI slave devices, with dedicated chip selects, supports
SPI mode 0/1/2 and 3, CPIO or Fifo mode with DMA transfers and different
SPI transfer mode (Single, Dual or Quad).
This commit adds basic driver support for CPIO mode and single SPI
transfer. In this mode, the CPU asserts cs, outputs or inputs data from
the current SPI device. Data transfers are copied by 1 or 4 bytes using
the SPI registers.
Signed-off-by: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-armada-3700.c | 659 ++++++++++++++++++++++++++++++++++++++++++
3 files changed, 667 insertions(+)
create mode 100644 drivers/spi/spi-armada-3700.c
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index b799547..6ade1ca 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -67,6 +67,13 @@ config SPI_ATH79
This enables support for the SPI controller present on the
Atheros AR71XX/AR724X/AR913X SoCs.
+config SPI_ARMADA_3700
+ tristate "Marvell Armada 3700 SPI Controller"
+ depends on ARCH_MVEBU && OF
+ help
+ This enables support for the SPI controller present on the
+ Marvell Armada 3700 SoCs.
+
config SPI_ATMEL
tristate "Atmel SPI Controller"
depends on HAS_DMA
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index aa939d9..140ca45 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_SPI_LOOPBACK_TEST) += spi-loopback-test.o
# SPI master controller drivers (bus)
obj-$(CONFIG_SPI_ALTERA) += spi-altera.o
+obj-$(CONFIG_SPI_ARMADA_3700) += spi-armada-3700.o
obj-$(CONFIG_SPI_ATMEL) += spi-atmel.o
obj-$(CONFIG_SPI_ATH79) += spi-ath79.o
obj-$(CONFIG_SPI_AU1550) += spi-au1550.o
diff --git a/drivers/spi/spi-armada-3700.c b/drivers/spi/spi-armada-3700.c
new file mode 100644
index 0000000..1e8298c
--- /dev/null
+++ b/drivers/spi/spi-armada-3700.c
@@ -0,0 +1,659 @@
+/*
+ * Marvell Armada-3700 SPI controller driver
+ *
+ * Copyright (C) 2016 Marvell Ltd.
+ *
+ * Author: Wilson Ding <dingwei-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>
+ * Author: Romain Perier <romain.perier-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/consumer.h>
+#include <linux/spi/spi.h>
+
+#define DRIVER_NAME "armada_3700_spi"
+
+#define A3700_SPI_TIMEOUT 10
+
+/* SPI Register Offest */
+#define A3700_SPI_IF_CTRL_REG 0x00
+#define A3700_SPI_IF_CFG_REG 0x04
+#define A3700_SPI_DATA_OUT_REG 0x08
+#define A3700_SPI_DATA_IN_REG 0x0C
+#define A3700_SPI_IF_INST_REG 0x10
+#define A3700_SPI_IF_ADDR_REG 0x14
+#define A3700_SPI_IF_RMODE_REG 0x18
+#define A3700_SPI_IF_HDR_CNT_REG 0x1C
+#define A3700_SPI_IF_DIN_CNT_REG 0x20
+#define A3700_SPI_IF_TIME_REG 0x24
+#define A3700_SPI_INT_STAT_REG 0x28
+#define A3700_SPI_INT_MASK_REG 0x2C
+
+/* A3700_SPI_IF_CTRL_REG */
+#define A3700_SPI_EN BIT(16)
+#define A3700_SPI_ADDR_NOT_CONFIG BIT(12)
+#define A3700_SPI_WFIFO_OVERFLOW BIT(11)
+#define A3700_SPI_WFIFO_UNDERFLOW BIT(10)
+#define A3700_SPI_RFIFO_OVERFLOW BIT(9)
+#define A3700_SPI_RFIFO_UNDERFLOW BIT(8)
+#define A3700_SPI_WFIFO_FULL BIT(7)
+#define A3700_SPI_WFIFO_EMPTY BIT(6)
+#define A3700_SPI_RFIFO_FULL BIT(5)
+#define A3700_SPI_RFIFO_EMPTY BIT(4)
+#define A3700_SPI_WFIFO_RDY BIT(3)
+#define A3700_SPI_RFIFO_RDY BIT(2)
+#define A3700_SPI_XFER_RDY BIT(1)
+#define A3700_SPI_XFER_DONE BIT(0)
+
+/* A3700_SPI_IF_CFG_REG */
+#define A3700_SPI_WFIFO_THRS BIT(28)
+#define A3700_SPI_RFIFO_THRS BIT(24)
+#define A3700_SPI_AUTO_CS BIT(20)
+#define A3700_SPI_DMA_RD_EN BIT(18)
+#define A3700_SPI_FIFO_MODE BIT(17)
+#define A3700_SPI_SRST BIT(16)
+#define A3700_SPI_XFER_START BIT(15)
+#define A3700_SPI_XFER_STOP BIT(14)
+#define A3700_SPI_INST_PIN BIT(13)
+#define A3700_SPI_ADDR_PIN BIT(12)
+#define A3700_SPI_DATA_PIN1 BIT(11)
+#define A3700_SPI_DATA_PIN0 BIT(10)
+#define A3700_SPI_FIFO_FLUSH BIT(9)
+#define A3700_SPI_RW_EN BIT(8)
+#define A3700_SPI_CLK_POL BIT(7)
+#define A3700_SPI_CLK_PHA BIT(6)
+#define A3700_SPI_BYTE_LEN BIT(5)
+#define A3700_SPI_CLK_PRESCALE BIT(0)
+#define A3700_SPI_CLK_PRESCALE_MASK (0x1f)
+
+#define A3700_SPI_WFIFO_THRS_BIT 28
+#define A3700_SPI_RFIFO_THRS_BIT 24
+#define A3700_SPI_FIFO_THRS_MASK 0x7
+
+#define A3700_SPI_DATA_PIN_MASK 0x3
+
+/* A3700_SPI_IF_HDR_CNT_REG */
+#define A3700_SPI_DUMMY_CNT_BIT 12
+#define A3700_SPI_DUMMY_CNT_MASK 0x7
+#define A3700_SPI_RMODE_CNT_BIT 8
+#define A3700_SPI_RMODE_CNT_MASK 0x3
+#define A3700_SPI_ADDR_CNT_BIT 4
+#define A3700_SPI_ADDR_CNT_MASK 0x7
+#define A3700_SPI_INSTR_CNT_BIT 0
+#define A3700_SPI_INSTR_CNT_MASK 0x3
+
+/* A3700_SPI_IF_TIME_REG */
+#define A3700_SPI_CLK_CAPT_EDGE BIT(7)
+
+struct a3700_spi {
+ struct spi_master *master;
+ void __iomem *base;
+ struct clk *clk;
+ unsigned int irq;
+ unsigned int flags;
+ bool last_xfer;
+ const u8 *tx_buf;
+ u8 *rx_buf;
+ size_t buf_len;
+ u8 byte_len;
+ u32 wait_mask;
+ struct completion done;
+};
+
+static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset)
+{
+ return readl(a3700_spi->base + offset);
+}
+
+static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data)
+{
+ writel(data, a3700_spi->base + offset);
+}
+
+static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~A3700_SPI_AUTO_CS;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+}
+
+static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+ val |= (A3700_SPI_EN << cs);
+ spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
+}
+
+static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi,
+ unsigned int cs)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+ val &= ~(A3700_SPI_EN << cs);
+ spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val);
+}
+
+static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi,
+ unsigned int pin_mode)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN);
+ val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1);
+
+ switch (pin_mode) {
+ case 1:
+ break;
+ case 2:
+ val |= A3700_SPI_DATA_PIN0;
+ break;
+ case 4:
+ val |= A3700_SPI_DATA_PIN1;
+ break;
+ default:
+ dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode);
+ return -EINVAL;
+ }
+
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ return 0;
+}
+
+static void a3700_spi_fifo_mode_unset(struct a3700_spi *a3700_spi)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~A3700_SPI_FIFO_MODE;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+}
+
+static void a3700_spi_mode_set(struct a3700_spi *a3700_spi,
+ unsigned int mode_bits)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+
+ if (mode_bits & SPI_CPOL)
+ val |= A3700_SPI_CLK_POL;
+ else
+ val &= ~A3700_SPI_CLK_POL;
+
+ if (mode_bits & SPI_CPHA)
+ val |= A3700_SPI_CLK_PHA;
+ else
+ val &= ~A3700_SPI_CLK_PHA;
+
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+}
+
+static void a3700_spi_clock_set(struct a3700_spi *a3700_spi,
+ unsigned int speed_hz, u16 mode)
+{
+ u32 val;
+ u32 prescale;
+
+ prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz);
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val = val & ~A3700_SPI_CLK_PRESCALE_MASK;
+
+ val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK);
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ if (prescale <= 2) {
+ val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG);
+ val |= A3700_SPI_CLK_CAPT_EDGE;
+ spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val);
+ }
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA);
+
+ if (mode & SPI_CPOL)
+ val |= A3700_SPI_CLK_POL;
+
+ if (mode & SPI_CPHA)
+ val |= A3700_SPI_CLK_PHA;
+
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+}
+
+static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len)
+{
+ u32 val;
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ if (len == 4)
+ val |= A3700_SPI_BYTE_LEN;
+ else
+ val &= ~A3700_SPI_BYTE_LEN;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ a3700_spi->byte_len = len;
+}
+
+static int a3700_spi_init(struct a3700_spi *a3700_spi)
+{
+ struct spi_master *master = a3700_spi->master;
+ u32 val;
+ int i;
+
+ /* Reset SPI unit */
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val |= A3700_SPI_SRST;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ for (i = 0; i < A3700_SPI_TIMEOUT; i++)
+ udelay(1);
+
+ val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG);
+ val &= ~A3700_SPI_SRST;
+ spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val);
+
+ /* Disable AUTO_CS and deactivate all chip-selects */
+ a3700_spi_auto_cs_unset(a3700_spi);
+ for (i = 0; i < master->num_chipselect; i++)
+ a3700_spi_deactivate_cs(a3700_spi, i);
+
+ a3700_spi_pin_mode_set(a3700_spi, 0);
+
+ /* Be sure that FIFO mode is disabled */
+ a3700_spi_fifo_mode_unset(a3700_spi);
+
+ /* Set SPI mode */
+ a3700_spi_mode_set(a3700_spi, master->mode_bits);
+
+ /* Reset counters */
+ spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0);
+ spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0);
+
+ /* Mask the interrupts and clear cause bits */
+ spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
+ spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U);
+
+ return 0;
+}
+
+static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id)
+{
+ struct spi_master *master = dev_id;
+ struct a3700_spi *a3700_spi;
+ u32 cause;
+
+ a3700_spi = spi_master_get_devdata(master);
+
+ /* Get interrupt causes */
+ cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG);
+
+ /* mask and acknowledge the SPI interrupts */
+ spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
+ spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause);
+
+ /* Wake up the transfer */
+ if (a3700_spi->wait_mask & cause)
+ complete(&a3700_spi->done);
+
+ return IRQ_HANDLED;
+}
+
+static bool a3700_spi_wait_completion(struct spi_device *spi)
+{
+ struct a3700_spi *a3700_spi;
+ unsigned int timeout;
+ unsigned int ctrl_reg;
+ unsigned long timeout_jiffies;
+
+ a3700_spi = spi_master_get_devdata(spi->master);
+
+ /* SPI interrupt is edge-triggered, which means an interrupt will
+ * be generated only when detecting a specific status bit changed
+ * from '0' to '1'. So when we start waiting for a interrupt, we
+ * need to check status bit in control reg first, if it is already 1,
+ * then we do not need to wait for interrupt
+ */
+ ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+ if (a3700_spi->wait_mask & ctrl_reg)
+ return true;
+
+ reinit_completion(&a3700_spi->done);
+
+ spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG,
+ a3700_spi->wait_mask);
+
+ timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT);
+ timeout = wait_for_completion_timeout(&a3700_spi->done,
+ timeout_jiffies);
+
+ a3700_spi->wait_mask = 0;
+
+ if (timeout)
+ return true;
+
+ /* there might be the case that right after we checked the
+ * status bits in this routine and before start to wait for
+ * interrupt by wait_for_completion_timeout, the interrupt
+ * happens, to avoid missing it we need to double check
+ * status bits in control reg, if it is already 1, then
+ * consider that we have the interrupt successfully and
+ * return true.
+ */
+ ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG);
+ if (a3700_spi->wait_mask & ctrl_reg)
+ return true;
+
+ spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0);
+
+ return true;
+}
+
+static bool a3700_spi_transfer_wait(struct spi_device *spi,
+ unsigned int bit_mask)
+{
+ struct a3700_spi *a3700_spi;
+
+ a3700_spi = spi_master_get_devdata(spi->master);
+ a3700_spi->wait_mask = bit_mask;
+
+ return a3700_spi_wait_completion(spi);
+}
+
+static int a3700_spi_transfer_setup(struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ struct a3700_spi *a3700_spi;
+ unsigned int byte_len;
+ int ret = 0;
+
+ a3700_spi = spi_master_get_devdata(spi->master);
+
+ a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode);
+
+ byte_len = xfer->bits_per_word >> 3;
+
+ /* Set byte length */
+ a3700_spi_bytelen_set(a3700_spi, byte_len);
+
+ return ret;
+}
+
+static int a3700_spi_read_data(struct a3700_spi *a3700_spi)
+{
+ u32 val, data;
+
+ if (a3700_spi->buf_len % a3700_spi->byte_len)
+ return -EINVAL;
+
+ /* Read bytes from data in register */
+ val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG);
+
+ if (a3700_spi->byte_len == 4)
+ data = be32_to_cpu(val);
+ else
+ data = val;
+
+ memcpy(a3700_spi->rx_buf, &data, a3700_spi->byte_len);
+
+ a3700_spi->buf_len -= a3700_spi->byte_len;
+ a3700_spi->rx_buf += a3700_spi->byte_len;
+
+ /* Request next 1 or 4 bytes data */
+ if (a3700_spi->buf_len)
+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
+
+ return 0;
+}
+
+static int a3700_spi_write_data(struct a3700_spi *a3700_spi)
+{
+ u32 val = 0;
+
+ if (a3700_spi->buf_len % a3700_spi->byte_len)
+ return -EINVAL;
+
+ /* Write bytes from data out register */
+ if (a3700_spi->byte_len == 4)
+ val = cpu_to_be32(*(u32 *)a3700_spi->tx_buf);
+ else
+ val = a3700_spi->tx_buf[0];
+
+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val);
+ a3700_spi->buf_len -= a3700_spi->byte_len;
+ a3700_spi->tx_buf += a3700_spi->byte_len;
+
+ return 0;
+}
+
+static void a3700_spi_set_cs(struct spi_device *spi, bool enable)
+{
+ struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master);
+
+ if (!enable)
+ a3700_spi_activate_cs(a3700_spi, spi->chip_select);
+ else
+ a3700_spi_deactivate_cs(a3700_spi, spi->chip_select);
+}
+
+static int a3700_spi_prepare_message(struct spi_master *master,
+ struct spi_message *message)
+{
+ struct spi_device *spi = message->spi;
+
+ if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
+ dev_err(&spi->dev, "wait transfer ready timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static int a3700_spi_transfer_one(struct spi_master *master,
+ struct spi_device *spi,
+ struct spi_transfer *xfer)
+{
+ struct a3700_spi *a3700_spi = spi_master_get_devdata(master);
+ int ret = 0;
+
+ ret = a3700_spi_transfer_setup(spi, xfer);
+ if (ret)
+ goto err;
+
+ a3700_spi->tx_buf = xfer->tx_buf;
+ a3700_spi->rx_buf = xfer->rx_buf;
+ a3700_spi->buf_len = xfer->len;
+
+ /* Start READ transfer by writing dummy data to DOUT register */
+ if (xfer->rx_buf)
+ spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, 0);
+
+ while (a3700_spi->buf_len) {
+ if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
+ dev_err(&spi->dev, "wait transfer ready timed out\n");
+ ret = -ETIMEDOUT;
+ goto err;
+ }
+
+ if (a3700_spi->tx_buf) {
+ ret = a3700_spi_write_data(a3700_spi);
+ if (ret)
+ goto err;
+ }
+
+ if (a3700_spi->rx_buf) {
+ ret = a3700_spi_read_data(a3700_spi);
+ if (ret)
+ goto err;
+ }
+ }
+
+err:
+ spi_finalize_current_transfer(master);
+ return ret;
+}
+
+static int a3700_spi_unprepare_message(struct spi_master *master,
+ struct spi_message *message)
+{
+ struct spi_device *spi = message->spi;
+
+ if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) {
+ dev_err(&spi->dev, "wait transfer ready timed out\n");
+ return -ETIMEDOUT;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id a3700_spi_dt_ids[] = {
+ { .compatible = "marvell,armada-3700-spi", .data = NULL },
+};
+
+MODULE_DEVICE_TABLE(of, a3700_spi_of_match_table);
+
+static int a3700_spi_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *of_node = dev->of_node;
+ struct resource *res;
+ struct spi_master *master;
+ struct a3700_spi *spi;
+ u32 num_cs = 0;
+ int ret = 0;
+
+ master = spi_alloc_master(dev, sizeof(*spi));
+ if (!master) {
+ dev_err(dev, "master allocation failed\n");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ if (of_property_read_u32(of_node, "num-cs", &num_cs)) {
+ dev_err(dev, "could not find num-cs\n");
+ ret = -ENXIO;
+ goto error;
+ }
+
+ master->bus_num = (pdev->id != -1) ? pdev->id : 0;
+ master->dev.of_node = of_node;
+ master->mode_bits = SPI_MODE_3;
+ master->num_chipselect = num_cs;
+ master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32);
+ master->prepare_message = a3700_spi_prepare_message;
+ master->transfer_one = a3700_spi_transfer_one;
+ master->unprepare_message = a3700_spi_unprepare_message;
+ master->set_cs = a3700_spi_set_cs;
+
+ platform_set_drvdata(pdev, master);
+
+ spi = spi_master_get_devdata(master);
+ memset(spi, 0, sizeof(struct a3700_spi));
+
+ spi->master = master;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ spi->base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(spi->base)) {
+ ret = PTR_ERR(spi->base);
+ goto error;
+ }
+
+ spi->irq = platform_get_irq(pdev, 0);
+ if (spi->irq < 0) {
+ dev_err(dev, "could not get irq: %d\n", spi->irq);
+ ret = -ENXIO;
+ goto error;
+ }
+
+ init_completion(&spi->done);
+
+ spi->clk = devm_clk_get(dev, NULL);
+ if (IS_ERR(spi->clk)) {
+ dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk));
+ goto error;
+ }
+
+ ret = clk_prepare_enable(spi->clk);
+ if (ret) {
+ dev_err(dev, "could not prepare clk: %d\n", ret);
+ goto error;
+ }
+
+ ret = a3700_spi_init(spi);
+ if (ret)
+ goto error_clk;
+
+ ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0,
+ dev_name(dev), master);
+ if (ret) {
+ dev_err(dev, "could not request IRQ: %d\n", ret);
+ goto error_clk;
+ }
+
+ ret = devm_spi_register_master(dev, master);
+ if (ret) {
+ dev_err(dev, "Failed to register master\n");
+ goto error_clk;
+ }
+
+ dev_info(dev, "Marvell Armada 3700 SPI Controller at 0x%08lx, irq %d\n",
+ (unsigned long)res->start, spi->irq);
+
+ return 0;
+
+error_clk:
+ clk_disable_unprepare(spi->clk);
+error:
+ spi_master_put(master);
+out:
+ return ret;
+}
+
+static int a3700_spi_remove(struct platform_device *pdev)
+{
+ struct spi_master *master = platform_get_drvdata(pdev);
+ struct a3700_spi *spi = spi_master_get_devdata(master);
+
+ clk_disable_unprepare(spi->clk);
+ spi_master_put(master);
+
+ return 0;
+}
+
+static struct platform_driver a3700_spi_driver = {
+ .driver = {
+ .name = DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = of_match_ptr(a3700_spi_dt_ids),
+ },
+ .probe = a3700_spi_probe,
+ .remove = a3700_spi_remove,
+};
+
+module_platform_driver(a3700_spi_driver);
+
+MODULE_DESCRIPTION("Armada-3700 SPI driver");
+MODULE_AUTHOR("Wilson Ding <dingwei-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:" DRIVER_NAME);
--
2.9.3
--
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^ permalink raw reply related
* [PATCH 0/5] Add support for the Armada 3700 SPI controller
From: Romain Perier @ 2016-11-29 14:39 UTC (permalink / raw)
To: Mark Brown, linux-spi-u79uwXL29TY76Z2rM5mHXA
Cc: Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
The Marvell Armada 3700 SoC includes an SPI controller. This controller
supports up to 4 SPI slave devices, with dedicated chip selects, CPIO or
FIFO mode with DMA or CPU transfers and different SPI transfer modes
(Standard single, Dual or Quad).
This set of patches adds a basic support for the CPIO mode, then it
enables the FIFO mode (CPU-side only, DMA not supported yet). It also
adds the required definitions of the spi nodes to the devicetree.
Romain Perier (5):
spi: Add basic support for Armada 3700 SPI Controller
spi: armada-3700: Add support for the FIFO mode
dt-bindings: spi: Add documentation for the Armada 3700 SPI Controller
arm64: dts: marvell: Add definition of SPI controller for Armada 3700
arm64: dts: marvell: Enable spi0 on the board Armada-3720-db
.../devicetree/bindings/spi/spi-armada-3700.txt | 25 +
arch/arm64/boot/dts/marvell/armada-3720-db.dts | 30 +
arch/arm64/boot/dts/marvell/armada-37xx.dtsi | 13 +
drivers/spi/Kconfig | 7 +
drivers/spi/Makefile | 1 +
drivers/spi/spi-armada-3700.c | 1047 ++++++++++++++++++++
6 files changed, 1123 insertions(+)
create mode 100644 Documentation/devicetree/bindings/spi/spi-armada-3700.txt
create mode 100644 drivers/spi/spi-armada-3700.c
--
2.9.3
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^ permalink raw reply
* Re: Re: [PATCH v7 1/8] drm: sun8i: Add a basic DRM driver for Allwinner DE2
From: Icenowy Zheng @ 2016-11-29 14:33 UTC (permalink / raw)
To: daniel-/w4YWyX8dFk@public.gmane.org, Jean-Francois Moine
Cc: Dave Airlie, Maxime Ripard, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
In-Reply-To: <20161129143051.vn6exubsirwcauag-dv86pmgwkMBes7Z6vYuT8azUEOm+Xw19@public.gmane.org>
29.11.2016, 22:30, "Daniel Vetter" <daniel-/w4YWyX8dFk@public.gmane.org>:
> On Mon, Nov 28, 2016 at 03:23:54PM +0100, Jean-Francois Moine wrote:
>> Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
>> engine, DE2.
>> This patch adds a DRM video driver for this device.
>>
>> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
>
> Scrolled around a bit, seemed all reasonable.
>
> Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
>
> Not sure a new driver for each chip is reasonable, experience says that
> long-term you want to share quite a pile of code between different hw
> platforms from the same vendor. But that's entirely up to you.
> -Daniel
The Display Engine on A83T and newer SoCs is quite new, different from
the ones on A33 and older.
It's called "DE 2.0" in the user manual of the SoCs.
>
>> ---
>> drivers/gpu/drm/Kconfig | 2 +
>> drivers/gpu/drm/Makefile | 1 +
>> drivers/gpu/drm/sun8i/Kconfig | 19 +
>> drivers/gpu/drm/sun8i/Makefile | 7 +
>> drivers/gpu/drm/sun8i/de2_crtc.c | 449 +++++++++++++++++++++++
>> drivers/gpu/drm/sun8i/de2_crtc.h | 50 +++
>> drivers/gpu/drm/sun8i/de2_drv.c | 317 ++++++++++++++++
>> drivers/gpu/drm/sun8i/de2_drv.h | 48 +++
>> drivers/gpu/drm/sun8i/de2_plane.c | 734 ++++++++++++++++++++++++++++++++++++++
>> 9 files changed, 1627 insertions(+)
>> create mode 100644 drivers/gpu/drm/sun8i/Kconfig
>> create mode 100644 drivers/gpu/drm/sun8i/Makefile
>> create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.c
>> create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.h
>> create mode 100644 drivers/gpu/drm/sun8i/de2_drv.c
>> create mode 100644 drivers/gpu/drm/sun8i/de2_drv.h
>> create mode 100644 drivers/gpu/drm/sun8i/de2_plane.c
>>
>> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
>> index 95fc041..bb1bfbc 100644
>> --- a/drivers/gpu/drm/Kconfig
>> +++ b/drivers/gpu/drm/Kconfig
>> @@ -202,6 +202,8 @@ source "drivers/gpu/drm/shmobile/Kconfig"
>>
>> source "drivers/gpu/drm/sun4i/Kconfig"
>>
>> +source "drivers/gpu/drm/sun8i/Kconfig"
>> +
>> source "drivers/gpu/drm/omapdrm/Kconfig"
>>
>> source "drivers/gpu/drm/tilcdc/Kconfig"
>> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
>> index 883f3e7..3e1eaa0 100644
>> --- a/drivers/gpu/drm/Makefile
>> +++ b/drivers/gpu/drm/Makefile
>> @@ -72,6 +72,7 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
>> obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
>> obj-y += omapdrm/
>> obj-$(CONFIG_DRM_SUN4I) += sun4i/
>> +obj-$(CONFIG_DRM_SUN8I) += sun8i/
>> obj-y += tilcdc/
>> obj-$(CONFIG_DRM_QXL) += qxl/
>> obj-$(CONFIG_DRM_BOCHS) += bochs/
>> diff --git a/drivers/gpu/drm/sun8i/Kconfig b/drivers/gpu/drm/sun8i/Kconfig
>> new file mode 100644
>> index 0000000..6940895
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/Kconfig
>> @@ -0,0 +1,19 @@
>> +#
>> +# Allwinner DE2 Video configuration
>> +#
>> +
>> +config DRM_SUN8I
>> + bool
>> +
>> +config DRM_SUN8I_DE2
>> + tristate "Support for Allwinner Video with DE2 interface"
>> + depends on DRM && OF
>> + depends on ARCH_SUNXI || COMPILE_TEST
>> + select DRM_GEM_CMA_HELPER
>> + select DRM_KMS_CMA_HELPER
>> + select DRM_KMS_HELPER
>> + select DRM_SUN8I
>> + help
>> + Choose this option if your Allwinner chipset has the DE2 interface
>> + as the A64, A83T and H3. If M is selected the module will be called
>> + sun8i-de2-drm.
>> diff --git a/drivers/gpu/drm/sun8i/Makefile b/drivers/gpu/drm/sun8i/Makefile
>> new file mode 100644
>> index 0000000..f107919
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/Makefile
>> @@ -0,0 +1,7 @@
>> +#
>> +# Makefile for Allwinner's sun8i DRM device driver
>> +#
>> +
>> +sun8i-de2-drm-objs := de2_drv.o de2_crtc.o de2_plane.o
>> +
>> +obj-$(CONFIG_DRM_SUN8I_DE2) += sun8i-de2-drm.o
>> diff --git a/drivers/gpu/drm/sun8i/de2_crtc.c b/drivers/gpu/drm/sun8i/de2_crtc.c
>> new file mode 100644
>> index 0000000..4e94ccc
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/de2_crtc.c
>> @@ -0,0 +1,449 @@
>> +/*
>> + * Allwinner DRM driver - DE2 CRTC
>> + *
>> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +
>> +#include <linux/component.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <linux/io.h>
>> +#include <linux/of_irq.h>
>> +#include <linux/of_graph.h>
>> +
>> +#include "de2_drv.h"
>> +#include "de2_crtc.h"
>> +
>> +/* I/O map */
>> +
>> +#define TCON_GCTL_REG 0x00
>> +#define TCON_GCTL_TCON_ENABLE BIT(31)
>> +#define TCON_GINT0_REG 0x04
>> +#define TCON_GINT0_TCON1_Vb_Int_En BIT(30)
>> +#define TCON_GINT0_TCON1_Vb_Int_Flag BIT(14)
>> +#define TCON_GINT0_TCON1_Vb_Line_Int_Flag BIT(12)
>> +#define TCON0_CTL_REG 0x40
>> +#define TCON0_CTL_TCON_ENABLE BIT(31)
>> +#define TCON1_CTL_REG 0x90
>> +#define TCON1_CTL_TCON_ENABLE BIT(31)
>> +#define TCON1_CTL_INTERLACE_ENABLE BIT(20)
>> +#define TCON1_CTL_Start_Delay_SHIFT 4
>> +#define TCON1_CTL_Start_Delay_MASK GENMASK(8, 4)
>> +#define TCON1_BASIC0_REG 0x94 /* XI/YI */
>> +#define TCON1_BASIC1_REG 0x98 /* LS_XO/LS_YO */
>> +#define TCON1_BASIC2_REG 0x9c /* XO/YO */
>> +#define TCON1_BASIC3_REG 0xa0 /* HT/HBP */
>> +#define TCON1_BASIC4_REG 0xa4 /* VT/VBP */
>> +#define TCON1_BASIC5_REG 0xa8 /* HSPW/VSPW */
>> +#define TCON1_PS_SYNC_REG 0xb0
>> +#define TCON1_IO_POL_REG 0xf0
>> +#define TCON1_IO_POL_IO0_inv BIT(24)
>> +#define TCON1_IO_POL_IO1_inv BIT(25)
>> +#define TCON1_IO_POL_IO2_inv BIT(26)
>> +#define TCON1_IO_TRI_REG 0xf4
>> +#define TCON_CEU_CTL_REG 0x100
>> +#define TCON_CEU_CTL_ceu_en BIT(31)
>> +#define TCON1_FILL_CTL_REG 0x300
>> +#define TCON1_FILL_START0_REG 0x304
>> +#define TCON1_FILL_END0_REG 0x308
>> +#define TCON1_FILL_DATA0_REG 0x30c
>> +
>> +#define XY(x, y) (((x) << 16) | (y))
>> +
>> +#define andl_relaxed(addr, val) \
>> + writel_relaxed(readl_relaxed(addr) & val, addr)
>> +#define orl_relaxed(addr, val) \
>> + writel_relaxed(readl_relaxed(addr) | val, addr)
>> +
>> +/* vertical blank functions */
>> +
>> +static void de2_atomic_flush(struct drm_crtc *crtc,
>> + struct drm_crtc_state *old_state)
>> +{
>> + struct drm_pending_vblank_event *event = crtc->state->event;
>> +
>> + if (event) {
>> + crtc->state->event = NULL;
>> + spin_lock_irq(&crtc->dev->event_lock);
>> + if (drm_crtc_vblank_get(crtc) == 0)
>> + drm_crtc_arm_vblank_event(crtc, event);
>> + else
>> + drm_crtc_send_vblank_event(crtc, event);
>> + spin_unlock_irq(&crtc->dev->event_lock);
>> + }
>> +}
>> +
>> +static irqreturn_t de2_lcd_irq(int irq, void *dev_id)
>> +{
>> + struct lcd *lcd = (struct lcd *) dev_id;
>> + u32 isr;
>> +
>> + isr = readl_relaxed(lcd->mmio + TCON_GINT0_REG);
>> +
>> + drm_crtc_handle_vblank(&lcd->crtc);
>> +
>> + writel_relaxed(isr &
>> + ~(TCON_GINT0_TCON1_Vb_Int_Flag |
>> + TCON_GINT0_TCON1_Vb_Line_Int_Flag),
>> + lcd->mmio + TCON_GINT0_REG);
>> +
>> + return IRQ_HANDLED;
>> +}
>> +
>> +int de2_enable_vblank(struct drm_device *drm, unsigned int crtc_ix)
>> +{
>> + struct priv *priv = drm_to_priv(drm);
>> + struct lcd *lcd = priv->lcds[crtc_ix];
>> +
>> + orl_relaxed(lcd->mmio + TCON_GINT0_REG, TCON_GINT0_TCON1_Vb_Int_En);
>> +
>> + return 0;
>> +}
>> +
>> +void de2_disable_vblank(struct drm_device *drm, unsigned int crtc_ix)
>> +{
>> + struct priv *priv = drm_to_priv(drm);
>> + struct lcd *lcd = priv->lcds[crtc_ix];
>> +
>> + andl_relaxed(lcd->mmio + TCON_GINT0_REG, ~TCON_GINT0_TCON1_Vb_Int_En);
>> +}
>> +
>> +void de2_vblank_reset(struct lcd *lcd)
>> +{
>> + drm_crtc_vblank_reset(&lcd->crtc);
>> +}
>> +
>> +/* frame functions */
>> +static int de2_crtc_set_clock(struct lcd *lcd, int rate)
>> +{
>> + struct clk *parent_clk;
>> + u32 parent_rate;
>> + int ret;
>> +
>> + /* determine and set the best rate for the parent clock (pll-video) */
>> + if ((270000 * 2) % rate == 0)
>> + parent_rate = 270000000;
>> + else if (297000 % rate == 0)
>> + parent_rate = 297000000;
>> + else
>> + return -EINVAL; /* unsupported clock */
>> +
>> + parent_clk = clk_get_parent(lcd->clk);
>> +
>> + ret = clk_set_rate(parent_clk, parent_rate);
>> + if (ret) {
>> + dev_err(lcd->dev, "set parent rate failed %d\n", ret);
>> + return ret;
>> + }
>> + ret = clk_set_rate(lcd->clk, rate * 1000);
>> + if (ret) {
>> + dev_err(lcd->dev, "set rate failed %d\n", ret);
>> + return ret;
>> + }
>> +
>> + /* enable the clock */
>> + reset_control_deassert(lcd->reset);
>> + clk_prepare_enable(lcd->bus);
>> + clk_prepare_enable(lcd->clk);
>> +
>> + return ret;
>> +}
>> +
>> +static void de2_tcon_init(struct lcd *lcd)
>> +{
>> + andl_relaxed(lcd->mmio + TCON0_CTL_REG, ~TCON0_CTL_TCON_ENABLE);
>> + andl_relaxed(lcd->mmio + TCON1_CTL_REG, ~TCON1_CTL_TCON_ENABLE);
>> + andl_relaxed(lcd->mmio + TCON_GCTL_REG, ~TCON_GCTL_TCON_ENABLE);
>> +
>> + /* disable/ack interrupts */
>> + writel_relaxed(0, lcd->mmio + TCON_GINT0_REG);
>> +}
>> +
>> +static void de2_tcon_enable(struct lcd *lcd)
>> +{
>> + struct drm_crtc *crtc = &lcd->crtc;
>> + const struct drm_display_mode *mode = &crtc->mode;
>> + int interlace = mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 1;
>> + int start_delay;
>> + u32 data;
>> +
>> + orl_relaxed(lcd->mmio + TCON_GCTL_REG, TCON_GCTL_TCON_ENABLE);
>> +
>> + data = XY(mode->hdisplay - 1, mode->vdisplay / interlace - 1);
>> + writel_relaxed(data, lcd->mmio + TCON1_BASIC0_REG);
>> + writel_relaxed(data, lcd->mmio + TCON1_BASIC1_REG);
>> + writel_relaxed(data, lcd->mmio + TCON1_BASIC2_REG);
>> + writel_relaxed(XY(mode->htotal - 1,
>> + mode->htotal - mode->hsync_start - 1),
>> + lcd->mmio + TCON1_BASIC3_REG);
>> + writel_relaxed(XY(mode->vtotal * (3 - interlace),
>> + mode->vtotal - mode->vsync_start - 1),
>> + lcd->mmio + TCON1_BASIC4_REG);
>> + writel_relaxed(XY(mode->hsync_end - mode->hsync_start - 1,
>> + mode->vsync_end - mode->vsync_start - 1),
>> + lcd->mmio + TCON1_BASIC5_REG);
>> +
>> + data = TCON1_IO_POL_IO2_inv;
>> + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
>> + data |= TCON1_IO_POL_IO0_inv;
>> + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
>> + data |= TCON1_IO_POL_IO1_inv;
>> + writel_relaxed(data, lcd->mmio + TCON1_IO_POL_REG);
>> +
>> + andl_relaxed(lcd->mmio + TCON_CEU_CTL_REG, ~TCON_CEU_CTL_ceu_en);
>> +
>> + if (interlace == 2)
>> + orl_relaxed(lcd->mmio + TCON1_CTL_REG,
>> + TCON1_CTL_INTERLACE_ENABLE);
>> + else
>> + andl_relaxed(lcd->mmio + TCON1_CTL_REG,
>> + ~TCON1_CTL_INTERLACE_ENABLE);
>> +
>> + writel_relaxed(0, lcd->mmio + TCON1_FILL_CTL_REG);
>> + writel_relaxed(mode->vtotal + 1, lcd->mmio + TCON1_FILL_START0_REG);
>> + writel_relaxed(mode->vtotal, lcd->mmio + TCON1_FILL_END0_REG);
>> + writel_relaxed(0, lcd->mmio + TCON1_FILL_DATA0_REG);
>> +
>> + start_delay = (mode->vtotal - mode->vdisplay) / interlace - 5;
>> + if (start_delay > 31)
>> + start_delay = 31;
>> + data = readl_relaxed(lcd->mmio + TCON1_CTL_REG);
>> + data &= ~TCON1_CTL_Start_Delay_MASK;
>> + data |= start_delay << TCON1_CTL_Start_Delay_SHIFT;
>> + writel_relaxed(data, lcd->mmio + TCON1_CTL_REG);
>> +
>> + orl_relaxed(lcd->mmio + TCON1_CTL_REG, TCON1_CTL_TCON_ENABLE);
>> +}
>> +
>> +static void de2_tcon_disable(struct lcd *lcd)
>> +{
>> + andl_relaxed(lcd->mmio + TCON1_CTL_REG, ~TCON1_CTL_TCON_ENABLE);
>> + andl_relaxed(lcd->mmio + TCON_GCTL_REG, ~TCON_GCTL_TCON_ENABLE);
>> +}
>> +
>> +static void de2_crtc_enable(struct drm_crtc *crtc)
>> +{
>> + struct lcd *lcd = crtc_to_lcd(crtc);
>> + struct drm_display_mode *mode = &crtc->mode;
>> +
>> + if (de2_crtc_set_clock(lcd, mode->clock) < 0)
>> + return;
>> + lcd->clk_enabled = true;
>> +
>> + /* start the TCON and the DE */
>> + de2_tcon_enable(lcd);
>> + de2_de_enable(lcd);
>> +
>> + /* turn on blanking interrupt */
>> + drm_crtc_vblank_on(crtc);
>> +}
>> +
>> +static void de2_crtc_disable(struct drm_crtc *crtc,
>> + struct drm_crtc_state *old_crtc_state)
>> +{
>> + struct lcd *lcd = crtc_to_lcd(crtc);
>> +
>> + if (!lcd->clk_enabled)
>> + return; /* already disabled */
>> + lcd->clk_enabled = false;
>> +
>> + de2_de_disable(lcd);
>> +
>> + drm_crtc_vblank_off(crtc);
>> +
>> + de2_tcon_disable(lcd);
>> +
>> + clk_disable_unprepare(lcd->clk);
>> + clk_disable_unprepare(lcd->bus);
>> + reset_control_assert(lcd->reset);
>> +}
>> +
>> +static const struct drm_crtc_funcs de2_crtc_funcs = {
>> + .destroy = drm_crtc_cleanup,
>> + .set_config = drm_atomic_helper_set_config,
>> + .page_flip = drm_atomic_helper_page_flip,
>> + .reset = drm_atomic_helper_crtc_reset,
>> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
>> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
>> +};
>> +
>> +static const struct drm_crtc_helper_funcs de2_crtc_helper_funcs = {
>> + .atomic_flush = de2_atomic_flush,
>> + .enable = de2_crtc_enable,
>> + .atomic_disable = de2_crtc_disable,
>> +};
>> +
>> +/* device init */
>> +static int de2_lcd_bind(struct device *dev, struct device *master,
>> + void *data)
>> +{
>> + struct drm_device *drm = data;
>> + struct priv *priv = drm_to_priv(drm);
>> + struct lcd *lcd = dev_get_drvdata(dev);
>> + struct drm_crtc *crtc = &lcd->crtc;
>> + int ret, i, crtc_ix;
>> +
>> + lcd->priv = priv;
>> +
>> + /* set the CRTC reference */
>> + crtc_ix = drm_crtc_index(crtc);
>> + if (crtc_ix >= ARRAY_SIZE(priv->lcds)) {
>> + dev_err(drm->dev, "Bad crtc index");
>> + return -ENOENT;
>> + }
>> + priv->lcds[crtc_ix] = lcd;
>> +
>> + /* and the mixer index (DT port index in the DE) */
>> + for (i = 0; ; i++) {
>> + struct device_node *port;
>> +
>> + port = of_parse_phandle(drm->dev->of_node, "ports", i);
>> + if (!port)
>> + break;
>> + if (port == lcd->crtc.port) {
>> + lcd->mixer = i;
>> + break;
>> + }
>> + }
>> +
>> + ret = de2_plane_init(drm, lcd);
>> + if (ret < 0)
>> + return ret;
>> +
>> + drm_crtc_helper_add(crtc, &de2_crtc_helper_funcs);
>> +
>> + return drm_crtc_init_with_planes(drm, crtc,
>> + &lcd->planes[DE2_PRIMARY_PLANE],
>> + &lcd->planes[DE2_CURSOR_PLANE],
>> + &de2_crtc_funcs, NULL);
>> +}
>> +
>> +static void de2_lcd_unbind(struct device *dev, struct device *master,
>> + void *data)
>> +{
>> + struct platform_device *pdev = to_platform_device(dev);
>> + struct lcd *lcd = platform_get_drvdata(pdev);
>> +
>> + if (lcd->priv)
>> + lcd->priv->lcds[drm_crtc_index(&lcd->crtc)] = NULL;
>> +}
>> +
>> +static const struct component_ops de2_lcd_ops = {
>> + .bind = de2_lcd_bind,
>> + .unbind = de2_lcd_unbind,
>> +};
>> +
>> +static int de2_lcd_probe(struct platform_device *pdev)
>> +{
>> + struct device *dev = &pdev->dev;
>> + struct device_node *np = dev->of_node, *tmp, *parent, *port;
>> + struct lcd *lcd;
>> + struct resource *res;
>> + int id, irq, ret;
>> +
>> + lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL);
>> + if (!lcd)
>> + return -ENOMEM;
>> +
>> + dev_set_drvdata(dev, lcd);
>> + lcd->dev = dev;
>> + lcd->mixer = id;
>> +
>> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> + if (!res) {
>> + dev_err(dev, "failed to get memory resource\n");
>> + return -EINVAL;
>> + }
>> +
>> + lcd->mmio = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(lcd->mmio)) {
>> + dev_err(dev, "failed to map registers\n");
>> + return PTR_ERR(lcd->mmio);
>> + }
>> +
>> + /* possible CRTC */
>> + parent = np;
>> + tmp = of_get_child_by_name(np, "ports");
>> + if (tmp)
>> + parent = tmp;
>> + port = of_get_child_by_name(parent, "port");
>> + of_node_put(tmp);
>> + if (!port) {
>> + dev_err(dev, "no port node\n");
>> + return -ENXIO;
>> + }
>> + lcd->crtc.port = port;
>> +
>> + lcd->bus = devm_clk_get(dev, "bus");
>> + if (IS_ERR(lcd->bus)) {
>> + dev_err(dev, "get bus clock err %d\n", (int) PTR_ERR(lcd->bus));
>> + ret = PTR_ERR(lcd->bus);
>> + goto err;
>> + }
>> +
>> + lcd->clk = devm_clk_get(dev, "clock");
>> + if (IS_ERR(lcd->clk)) {
>> + ret = PTR_ERR(lcd->clk);
>> + dev_err(dev, "get video clock err %d\n", ret);
>> + goto err;
>> + }
>> +
>> + lcd->reset = devm_reset_control_get(dev, NULL);
>> + if (IS_ERR(lcd->reset)) {
>> + ret = PTR_ERR(lcd->reset);
>> + dev_err(dev, "get reset err %d\n", ret);
>> + goto err;
>> + }
>> +
>> + irq = platform_get_irq(pdev, 0);
>> + if (irq <= 0) {
>> + dev_err(dev, "unable to get irq\n");
>> + ret = -EINVAL;
>> + goto err;
>> + }
>> +
>> + de2_tcon_init(lcd); /* stop TCON and avoid interrupts */
>> +
>> + ret = devm_request_irq(dev, irq, de2_lcd_irq, 0,
>> + dev_name(dev), lcd);
>> + if (ret < 0) {
>> + dev_err(dev, "unable to request irq %d\n", irq);
>> + goto err;
>> + }
>> +
>> + return component_add(dev, &de2_lcd_ops);
>> +
>> +err:
>> + of_node_put(lcd->crtc.port);
>> + return ret;
>> +}
>> +
>> +static int de2_lcd_remove(struct platform_device *pdev)
>> +{
>> + struct lcd *lcd = platform_get_drvdata(pdev);
>> +
>> + component_del(&pdev->dev, &de2_lcd_ops);
>> +
>> + of_node_put(lcd->crtc.port);
>> +
>> + return 0;
>> +}
>> +
>> +static const struct of_device_id de2_lcd_ids[] = {
>> + { .compatible = "allwinner,sun8i-a83t-tcon", },
>> + { }
>> +};
>> +
>> +struct platform_driver de2_lcd_platform_driver = {
>> + .probe = de2_lcd_probe,
>> + .remove = de2_lcd_remove,
>> + .driver = {
>> + .name = "sun8i-de2-tcon",
>> + .of_match_table = of_match_ptr(de2_lcd_ids),
>> + },
>> +};
>> diff --git a/drivers/gpu/drm/sun8i/de2_crtc.h b/drivers/gpu/drm/sun8i/de2_crtc.h
>> new file mode 100644
>> index 0000000..c0d34a7
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/de2_crtc.h
>> @@ -0,0 +1,50 @@
>> +#ifndef __DE2_CRTC_H__
>> +#define __DE2_CRTC_H__
>> +/*
>> + * Copyright (C) 2016 Jean-Fran??ois Moine
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +
>> +#include <drm/drm_plane_helper.h>
>> +
>> +struct clk;
>> +struct reset_control;
>> +struct priv;
>> +
>> +/* planes */
>> +#define DE2_PRIMARY_PLANE 0
>> +#define DE2_CURSOR_PLANE 1
>> +#define DE2_N_PLANES 5 /* number of planes - see plane_tb[] in de2_plane.c */
>> +
>> +struct lcd {
>> + void __iomem *mmio;
>> +
>> + struct device *dev;
>> + struct drm_crtc crtc;
>> +
>> + struct priv *priv; /* DRM/DE private data */
>> +
>> + u8 mixer; /* LCD (mixer) number */
>> + u8 delayed; /* bitmap of planes with delayed update */
>> +
>> + u8 clk_enabled; /* used for error in crtc_enable */
>> +
>> + struct clk *clk;
>> + struct clk *bus;
>> + struct reset_control *reset;
>> +
>> + struct drm_plane planes[DE2_N_PLANES];
>> +};
>> +
>> +#define crtc_to_lcd(x) container_of(x, struct lcd, crtc)
>> +
>> +/* in de2_plane.c */
>> +void de2_de_enable(struct lcd *lcd);
>> +void de2_de_disable(struct lcd *lcd);
>> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd);
>> +
>> +#endif /* __DE2_CRTC_H__ */
>> diff --git a/drivers/gpu/drm/sun8i/de2_drv.c b/drivers/gpu/drm/sun8i/de2_drv.c
>> new file mode 100644
>> index 0000000..f96babe
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/de2_drv.c
>> @@ -0,0 +1,317 @@
>> +/*
>> + * Allwinner DRM driver - DE2 DRM driver
>> + *
>> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +
>> +#include <linux/module.h>
>> +#include <linux/of_device.h>
>> +#include <drm/drm_of.h>
>> +#include <linux/component.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_fb_cma_helper.h>
>> +#include <drm/drm_gem_cma_helper.h>
>> +
>> +#include "de2_drv.h"
>> +
>> +#define DRIVER_NAME "sun8i-de2"
>> +#define DRIVER_DESC "Allwinner DRM DE2"
>> +#define DRIVER_DATE "20161101"
>> +#define DRIVER_MAJOR 1
>> +#define DRIVER_MINOR 0
>> +
>> +static const struct of_device_id de2_drm_of_match[] = {
>> + { .compatible = "allwinner,sun8i-a83t-display-engine",
>> + .data = (void *) SOC_A83T },
>> + { .compatible = "allwinner,sun8i-h3-display-engine",
>> + .data = (void *) SOC_H3 },
>> + { },
>> +};
>> +MODULE_DEVICE_TABLE(of, de2_drm_of_match);
>> +
>> +static void de2_fb_output_poll_changed(struct drm_device *drm)
>> +{
>> + struct priv *priv = drm_to_priv(drm);
>> +
>> + if (priv->fbdev)
>> + drm_fbdev_cma_hotplug_event(priv->fbdev);
>> +}
>> +
>> +static const struct drm_mode_config_funcs de2_mode_config_funcs = {
>> + .fb_create = drm_fb_cma_create,
>> + .output_poll_changed = de2_fb_output_poll_changed,
>> + .atomic_check = drm_atomic_helper_check,
>> + .atomic_commit = drm_atomic_helper_commit,
>> +};
>> +
>> +/* -- DRM operations -- */
>> +
>> +static void de2_lastclose(struct drm_device *drm)
>> +{
>> + struct priv *priv = drm_to_priv(drm);
>> +
>> + if (priv->fbdev)
>> + drm_fbdev_cma_restore_mode(priv->fbdev);
>> +}
>> +
>> +static const struct file_operations de2_fops = {
>> + .owner = THIS_MODULE,
>> + .open = drm_open,
>> + .release = drm_release,
>> + .unlocked_ioctl = drm_ioctl,
>> + .poll = drm_poll,
>> + .read = drm_read,
>> + .llseek = no_llseek,
>> + .mmap = drm_gem_cma_mmap,
>> +};
>> +
>> +static struct drm_driver de2_drm_driver = {
>> + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
>> + DRIVER_ATOMIC,
>> + .lastclose = de2_lastclose,
>> + .get_vblank_counter = drm_vblank_no_hw_counter,
>> + .enable_vblank = de2_enable_vblank,
>> + .disable_vblank = de2_disable_vblank,
>> + .gem_free_object = drm_gem_cma_free_object,
>> + .gem_vm_ops = &drm_gem_cma_vm_ops,
>> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
>> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
>> + .gem_prime_import = drm_gem_prime_import,
>> + .gem_prime_export = drm_gem_prime_export,
>> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
>> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
>> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
>> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
>> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
>> + .dumb_create = drm_gem_cma_dumb_create,
>> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
>> + .dumb_destroy = drm_gem_dumb_destroy,
>> + .fops = &de2_fops,
>> + .name = DRIVER_NAME,
>> + .desc = DRIVER_DESC,
>> + .date = DRIVER_DATE,
>> + .major = DRIVER_MAJOR,
>> + .minor = DRIVER_MINOR,
>> +};
>> +
>> +/*
>> + * Platform driver
>> + */
>> +
>> +static int de2_drm_bind(struct device *dev)
>> +{
>> + struct drm_device *drm;
>> + struct priv *priv;
>> + struct resource *res;
>> + struct lcd *lcd;
>> + int i, ret;
>> +
>> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
>> + if (!priv)
>> + return -ENOMEM;
>> +
>> + drm = &priv->drm;
>> + dev_set_drvdata(dev, drm);
>> +
>> + /* get the resources */
>> + priv->soc_type = (int) of_match_device(de2_drm_of_match, dev)->data;
>> +
>> + res = platform_get_resource(to_platform_device(dev),
>> + IORESOURCE_MEM, 0);
>> + if (!res) {
>> + dev_err(dev, "failed to get memory resource\n");
>> + ret = -EINVAL;
>> + goto out1;
>> + }
>> +
>> + priv->mmio = devm_ioremap_resource(dev, res);
>> + if (IS_ERR(priv->mmio)) {
>> + ret = PTR_ERR(priv->mmio);
>> + dev_err(dev, "failed to map registers %d\n", ret);
>> + goto out1;
>> + }
>> +
>> + priv->gate = devm_clk_get(dev, "bus");
>> + if (IS_ERR(priv->gate)) {
>> + ret = PTR_ERR(priv->gate);
>> + dev_err(dev, "bus gate err %d\n", ret);
>> + goto out1;
>> + }
>> +
>> + priv->clk = devm_clk_get(dev, "clock");
>> + if (IS_ERR(priv->clk)) {
>> + ret = PTR_ERR(priv->clk);
>> + dev_err(dev, "clock err %d\n", ret);
>> + goto out1;
>> + }
>> +
>> + priv->reset = devm_reset_control_get(dev, NULL);
>> + if (IS_ERR(priv->reset)) {
>> + ret = PTR_ERR(priv->reset);
>> + dev_err(dev, "reset err %d\n", ret);
>> + goto out1;
>> + }
>> +
>> + mutex_init(&priv->mutex); /* protect DE I/O accesses */
>> +
>> + ret = drm_dev_init(drm, &de2_drm_driver, dev);
>> + if (ret != 0) {
>> + dev_err(dev, "dev_init failed %d\n", ret);
>> + goto out1;
>> + }
>> +
>> + drm_mode_config_init(drm);
>> + drm->mode_config.min_width = 32; /* needed for cursor */
>> + drm->mode_config.min_height = 32;
>> + drm->mode_config.max_width = 1920;
>> + drm->mode_config.max_height = 1080;
>> + drm->mode_config.funcs = &de2_mode_config_funcs;
>> +
>> + drm->irq_enabled = true;
>> +
>> + /* start the subdevices */
>> + ret = component_bind_all(dev, drm);
>> + if (ret < 0)
>> + goto out2;
>> +
>> + /* initialize and disable vertical blanking on all CRTCs */
>> + ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
>> + if (ret < 0)
>> + dev_warn(dev, "vblank_init failed %d\n", ret);
>> +
>> + for (i = 0; i < ARRAY_SIZE(priv->lcds); i++) {
>> + lcd = priv->lcds[i];
>> + if (lcd)
>> + de2_vblank_reset(lcd);
>> + }
>> +
>> + drm_mode_config_reset(drm);
>> +
>> + priv->fbdev = drm_fbdev_cma_init(drm,
>> + 32, /* bpp */
>> + drm->mode_config.num_crtc,
>> + drm->mode_config.num_connector);
>> + if (IS_ERR(priv->fbdev)) {
>> + ret = PTR_ERR(priv->fbdev);
>> + priv->fbdev = NULL;
>> + goto out3;
>> + }
>> +
>> + drm_kms_helper_poll_init(drm);
>> +
>> + ret = drm_dev_register(drm, 0);
>> + if (ret < 0)
>> + goto out4;
>> +
>> + return 0;
>> +
>> +out4:
>> + drm_fbdev_cma_fini(priv->fbdev);
>> +out3:
>> + component_unbind_all(dev, drm);
>> +out2:
>> + drm_dev_unref(drm);
>> +out1:
>> + kfree(priv);
>> + return ret;
>> +}
>> +
>> +static void de2_drm_unbind(struct device *dev)
>> +{
>> + struct drm_device *drm = dev_get_drvdata(dev);
>> + struct priv *priv = drm_to_priv(drm);
>> +
>> + drm_dev_unregister(drm);
>> +
>> + drm_fbdev_cma_fini(priv->fbdev);
>> + drm_kms_helper_poll_fini(drm);
>> + drm_vblank_cleanup(drm);
>> + drm_mode_config_cleanup(drm);
>> +
>> + component_unbind_all(dev, drm);
>> +
>> + kfree(priv);
>> +}
>> +
>> +static const struct component_master_ops de2_drm_comp_ops = {
>> + .bind = de2_drm_bind,
>> + .unbind = de2_drm_unbind,
>> +};
>> +
>> +/*
>> + * drm_of_component_probe() does:
>> + * - bind of the ports (lcd-controller.port)
>> + * - bind of the remote nodes (hdmi, tve..)
>> + */
>> +static int compare_of(struct device *dev, void *data)
>> +{
>> + struct device_node *np = data;
>> +
>> + if (of_node_cmp(np->name, "port") == 0) {
>> + np = of_get_parent(np);
>> + of_node_put(np);
>> + }
>> + return dev->of_node == np;
>> +}
>> +
>> +static int de2_drm_probe(struct platform_device *pdev)
>> +{
>> + int ret;
>> +
>> + ret = drm_of_component_probe(&pdev->dev,
>> + compare_of,
>> + &de2_drm_comp_ops);
>> + if (ret == -EINVAL)
>> + ret = -ENXIO;
>> + return ret;
>> +}
>> +
>> +static int de2_drm_remove(struct platform_device *pdev)
>> +{
>> + component_master_del(&pdev->dev, &de2_drm_comp_ops);
>> +
>> + return 0;
>> +}
>> +
>> +static struct platform_driver de2_drm_platform_driver = {
>> + .probe = de2_drm_probe,
>> + .remove = de2_drm_remove,
>> + .driver = {
>> + .name = DRIVER_NAME,
>> + .of_match_table = de2_drm_of_match,
>> + },
>> +};
>> +
>> +static int __init de2_drm_init(void)
>> +{
>> + int ret;
>> +
>> + ret = platform_driver_register(&de2_lcd_platform_driver);
>> + if (ret < 0)
>> + return ret;
>> +
>> + ret = platform_driver_register(&de2_drm_platform_driver);
>> + if (ret < 0)
>> + platform_driver_unregister(&de2_lcd_platform_driver);
>> +
>> + return ret;
>> +}
>> +
>> +static void __exit de2_drm_fini(void)
>> +{
>> + platform_driver_unregister(&de2_lcd_platform_driver);
>> + platform_driver_unregister(&de2_drm_platform_driver);
>> +}
>> +
>> +module_init(de2_drm_init);
>> +module_exit(de2_drm_fini);
>> +
>> +MODULE_AUTHOR("Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>");
>> +MODULE_DESCRIPTION("Allwinner DE2 DRM Driver");
>> +MODULE_LICENSE("GPL v2");
>> diff --git a/drivers/gpu/drm/sun8i/de2_drv.h b/drivers/gpu/drm/sun8i/de2_drv.h
>> new file mode 100644
>> index 0000000..c42c30a
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/de2_drv.h
>> @@ -0,0 +1,48 @@
>> +#ifndef __DE2_DRM_H__
>> +#define __DE2_DRM_H__
>> +/*
>> + * Copyright (C) 2016 Jean-Fran??ois Moine
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +
>> +#include <drm/drmP.h>
>> +#include <linux/clk.h>
>> +#include <linux/reset.h>
>> +
>> +struct drm_fbdev_cma;
>> +struct lcd;
>> +
>> +#define N_LCDS 2
>> +
>> +struct priv {
>> + struct drm_device drm;
>> + void __iomem *mmio;
>> + struct clk *clk;
>> + struct clk *gate;
>> + struct reset_control *reset;
>> +
>> + struct mutex mutex; /* protect DE I/O access */
>> + u8 soc_type;
>> +#define SOC_A83T 0
>> +#define SOC_H3 1
>> + u8 started; /* bitmap of started mixers */
>> + u8 clean; /* bitmap of clean mixers */
>> +
>> + struct drm_fbdev_cma *fbdev;
>> +
>> + struct lcd *lcds[N_LCDS]; /* CRTCs */
>> +};
>> +
>> +#define drm_to_priv(x) container_of(x, struct priv, drm)
>> +
>> +/* in de2_crtc.c */
>> +int de2_enable_vblank(struct drm_device *drm, unsigned int crtc);
>> +void de2_disable_vblank(struct drm_device *drm, unsigned int crtc);
>> +void de2_vblank_reset(struct lcd *lcd);
>> +extern struct platform_driver de2_lcd_platform_driver;
>> +
>> +#endif /* __DE2_DRM_H__ */
>> diff --git a/drivers/gpu/drm/sun8i/de2_plane.c b/drivers/gpu/drm/sun8i/de2_plane.c
>> new file mode 100644
>> index 0000000..2fd72dc
>> --- /dev/null
>> +++ b/drivers/gpu/drm/sun8i/de2_plane.c
>> @@ -0,0 +1,734 @@
>> +/*
>> + * Allwinner DRM driver - Display Engine 2
>> + *
>> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
>> + * Adapted from the sun8iw6 and sun8iw7 disp2 drivers
>> + * Copyright (c) 2016 Allwinnertech Co., Ltd.
>> + *
>> + * This program is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of
>> + * the License, or (at your option) any later version.
>> + */
>> +
>> +#include <linux/io.h>
>> +#include <drm/drm_atomic_helper.h>
>> +#include <drm/drm_crtc_helper.h>
>> +#include <drm/drm_fb_cma_helper.h>
>> +#include <drm/drm_gem_cma_helper.h>
>> +#include <drm/drm_plane_helper.h>
>> +
>> +#include "de2_drv.h"
>> +#include "de2_crtc.h"
>> +
>> +/* DE2 I/O map */
>> +
>> +#define DE2_MOD_REG 0x0000 /* 1 bit per LCD */
>> +#define DE2_GATE_REG 0x0004
>> +#define DE2_RESET_REG 0x0008
>> +#define DE2_DIV_REG 0x000c /* 4 bits per LCD */
>> +#define DE2_SEL_REG 0x0010
>> +
>> +#define DE2_MIXER0_BASE 0x00100000 /* LCD 0 */
>> +#define DE2_MIXER1_BASE 0x00200000 /* LCD 1 */
>> +
>> +/* mixer registers (addr / mixer base) */
>> +#define MIXER_GLB_REGS 0x00000 /* global control */
>> +#define MIXER_BLD_REGS 0x01000 /* alpha blending */
>> +#define MIXER_CHAN_REGS 0x02000 /* VI/UI overlay channels */
>> +#define MIXER_CHAN_SZ 0x1000 /* size of a channel */
>> +#define MIXER_VSU_REGS 0x20000 /* VSU */
>> +#define MIXER_GSU1_REGS 0x30000 /* GSUs */
>> +#define MIXER_GSU2_REGS 0x40000
>> +#define MIXER_GSU3_REGS 0x50000
>> +#define MIXER_FCE_REGS 0xa0000 /* FCE */
>> +#define MIXER_BWS_REGS 0xa2000 /* BWS */
>> +#define MIXER_LTI_REGS 0xa4000 /* LTI */
>> +#define MIXER_PEAK_REGS 0xa6000 /* PEAK */
>> +#define MIXER_ASE_REGS 0xa8000 /* ASE */
>> +#define MIXER_FCC_REGS 0xaa000 /* FCC */
>> +#define MIXER_DCSC_REGS 0xb0000 /* DCSC/SMBL */
>> +
>> +/* global control */
>> +#define MIXER_GLB_CTL_REG 0x00
>> +#define MIXER_GLB_CTL_rt_en BIT(0)
>> +#define MIXER_GLB_CTL_finish_irq_en BIT(4)
>> +#define MIXER_GLB_CTL_rtwb_port BIT(12)
>> +#define MIXER_GLB_STATUS_REG 0x04
>> +#define MIXER_GLB_DBUFF_REG 0x08
>> +#define MIXER_GLB_SIZE_REG 0x0c
>> +
>> +/* alpha blending */
>> +#define MIXER_BLD_FCOLOR_CTL_REG 0x00
>> +#define MIXER_BLD_FCOLOR_CTL_PEN(pipe) (0x0100 << (pipe))
>> +#define MIXER_BLD_ATTR_N 4 /* number of attribute blocks */
>> +#define MIXER_BLD_ATTR_SIZE (4 * 4) /* size of an attribute block */
>> +#define MIXER_BLD_ATTRx_FCOLOR(x) (0x04 + MIXER_BLD_ATTR_SIZE * (x))
>> +#define MIXER_BLD_ATTRx_INSIZE(x) (0x08 + MIXER_BLD_ATTR_SIZE * (x))
>> +#define MIXER_BLD_ATTRx_OFFSET(x) (0x0c + MIXER_BLD_ATTR_SIZE * (x))
>> +#define MIXER_BLD_ROUTE_REG 0x80
>> +#define MIXER_BLD_ROUTE(chan, pipe) ((chan) << ((pipe) * 4))
>> +#define MIXER_BLD_PREMULTIPLY_REG 0x84
>> +#define MIXER_BLD_BKCOLOR_REG 0x88
>> +#define MIXER_BLD_OUTPUT_SIZE_REG 0x8c
>> +#define MIXER_BLD_MODEx_REG(x) (0x90 + 4 * (x)) /* x = 0..3 */
>> +#define MIXER_BLD_MODE_SRCOVER 0x03010301
>> +#define MIXER_BLD_OUT_CTL_REG 0xfc
>> +
>> +/* VI channel (channel 0) */
>> +#define VI_CFG_N 4 /* number of layers */
>> +#define VI_CFG_SIZE 0x30 /* size of a layer */
>> +#define VI_CFGx_ATTR(l) (0x00 + VI_CFG_SIZE * (l))
>> +#define VI_CFG_ATTR_en BIT(0)
>> +#define VI_CFG_ATTR_fcolor_en BIT(4)
>> +#define VI_CFG_ATTR_fmt_SHIFT 8
>> +#define VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
>> +#define VI_CFG_ATTR_ui_sel BIT(15)
>> +#define VI_CFG_ATTR_top_down BIT(23)
>> +#define VI_CFGx_SIZE(l) (0x04 + VI_CFG_SIZE * (l))
>> +#define VI_CFGx_COORD(l) (0x08 + VI_CFG_SIZE * (l))
>> +#define VI_N_PLANES 3
>> +#define VI_CFGx_PITCHy(l, p) (0x0c + VI_CFG_SIZE * (l) + 4 * (p))
>> +#define VI_CFGx_TOP_LADDRy(l, p) (0x18 + VI_CFG_SIZE * (l) + 4 * (p))
>> +#define VI_CFGx_BOT_LADDRy(l, p) (0x24 + VI_CFG_SIZE * (l) + 4 * (p))
>> +#define VI_FCOLORx(l) (0xc0 + 4 * (l))
>> +#define VI_TOP_HADDRx(p) (0xd0 + 4 * (p))
>> +#define VI_BOT_HADDRx(p) (0xdc + 4 * (p))
>> +#define VI_OVL_SIZEx(n) (0xe8 + 4 * (n))
>> +#define VI_HORI_DSx(n) (0xf0 + 4 * (n))
>> +#define VI_VERT_DSx(n) (0xf8 + 4 * (n))
>> +#define VI_SIZE 0x100
>> +
>> +/* UI channel (channels 1..3) */
>> +#define UI_CFG_N 4 /* number of layers */
>> +#define UI_CFG_SIZE (8 * 4) /* size of a layer */
>> +#define UI_CFGx_ATTR(l) (0x00 + UI_CFG_SIZE * (l))
>> +#define UI_CFG_ATTR_en BIT(0)
>> +#define UI_CFG_ATTR_alpmod_SHIFT 1
>> +#define UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1)
>> +#define UI_CFG_ATTR_fcolor_en BIT(4)
>> +#define UI_CFG_ATTR_fmt_SHIFT 8
>> +#define UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
>> +#define UI_CFG_ATTR_top_down BIT(23)
>> +#define UI_CFG_ATTR_alpha_SHIFT 24
>> +#define UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
>> +#define UI_CFGx_SIZE(l) (0x04 + UI_CFG_SIZE * (l))
>> +#define UI_CFGx_COORD(l) (0x08 + UI_CFG_SIZE * (l))
>> +#define UI_CFGx_PITCH(l) (0x0c + UI_CFG_SIZE * (l))
>> +#define UI_CFGx_TOP_LADDR(l) (0x10 + UI_CFG_SIZE * (l))
>> +#define UI_CFGx_BOT_LADDR(l) (0x14 + UI_CFG_SIZE * (l))
>> +#define UI_CFGx_FCOLOR(l) (0x18 + UI_CFG_SIZE * (l))
>> +#define UI_TOP_HADDR 0x80
>> +#define UI_BOT_HADDR 0x84
>> +#define UI_OVL_SIZE 0x88
>> +#define UI_SIZE 0x8c
>> +
>> +/* coordinates and sizes */
>> +#define XY(x, y) (((y) << 16) | (x))
>> +#define WH(w, h) ((((h) - 1) << 16) | ((w) - 1))
>> +
>> +/* UI video formats */
>> +#define DE2_FORMAT_ARGB_8888 0
>> +#define DE2_FORMAT_BGRA_8888 3
>> +#define DE2_FORMAT_XRGB_8888 4
>> +#define DE2_FORMAT_RGB_888 8
>> +#define DE2_FORMAT_BGR_888 9
>> +
>> +/* VI video formats */
>> +#define DE2_FORMAT_YUV422_I_YVYU 1 /* YVYU */
>> +#define DE2_FORMAT_YUV422_I_UYVY 2 /* UYVY */
>> +#define DE2_FORMAT_YUV422_I_YUYV 3 /* YUYV */
>> +#define DE2_FORMAT_YUV422_P 6 /* YYYY UU VV planar */
>> +#define DE2_FORMAT_YUV420_P 10 /* YYYY U V planar */
>> +
>> +/* plane formats */
>> +static const uint32_t ui_formats[] = {
>> + DRM_FORMAT_ARGB8888,
>> + DRM_FORMAT_BGRA8888,
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_RGB888,
>> + DRM_FORMAT_BGR888,
>> +};
>> +
>> +static const uint32_t vi_formats[] = {
>> + DRM_FORMAT_XRGB8888,
>> + DRM_FORMAT_YUYV,
>> + DRM_FORMAT_YVYU,
>> + DRM_FORMAT_YUV422,
>> + DRM_FORMAT_YUV420,
>> + DRM_FORMAT_UYVY,
>> + DRM_FORMAT_BGRA8888,
>> + DRM_FORMAT_RGB888,
>> + DRM_FORMAT_BGR888,
>> +};
>> +
>> +/*
>> + * plane table
>> + *
>> + * The chosen channel/layer assignment of the planes respects
>> + * the following constraints:
>> + * - the cursor must be in a channel higher than the primary channel
>> + * - there are 4 channels in the LCD 0 and only 2 channels in the LCD 1
>> + */
>> +static const struct {
>> + u8 chan;
>> + u8 layer;
>> + u8 pipe;
>> + u8 type; /* plane type */
>> + const uint32_t *formats;
>> + u8 n_formats;
>> +} plane_tb[] = {
>> + [DE2_PRIMARY_PLANE] = { /* primary plane: channel 0 (VI) */
>> + 0, 0, 0,
>> + DRM_PLANE_TYPE_PRIMARY,
>> + ui_formats, ARRAY_SIZE(ui_formats),
>> + },
>> + [DE2_CURSOR_PLANE] = { /* cursor: channel 1 (UI) */
>> + 1, 0, 1,
>> + DRM_PLANE_TYPE_CURSOR,
>> + ui_formats, ARRAY_SIZE(ui_formats),
>> + },
>> + {
>> + 0, 1, 0, /* 1st overlay: channel 0, layer 1 */
>> + DRM_PLANE_TYPE_OVERLAY,
>> + vi_formats, ARRAY_SIZE(vi_formats),
>> + },
>> + {
>> + 0, 2, 0, /* 2nd overlay: channel 0, layer 2 */
>> + DRM_PLANE_TYPE_OVERLAY,
>> + vi_formats, ARRAY_SIZE(vi_formats),
>> + },
>> + {
>> + 0, 3, 0, /* 3rd overlay: channel 0, layer 3 */
>> + DRM_PLANE_TYPE_OVERLAY,
>> + vi_formats, ARRAY_SIZE(vi_formats),
>> + },
>> +};
>> +
>> +static inline void andl_relaxed(void __iomem *addr, u32 val)
>> +{
>> + writel_relaxed(readl_relaxed(addr) & val, addr);
>> +}
>> +
>> +static inline void orl_relaxed(void __iomem *addr, u32 val)
>> +{
>> + writel_relaxed(readl_relaxed(addr) | val, addr);
>> +}
>> +
>> +/* alert the DE processor about changes in a mixer configuration */
>> +static void de2_mixer_select(struct priv *priv,
>> + int mixer,
>> + void __iomem *mixer_io)
>> +{
>> + /* select the mixer */
>> + andl_relaxed(priv->mmio + DE2_SEL_REG, ~1);
>> +
>> + /* double register switch */
>> + writel_relaxed(1, mixer_io + MIXER_GLB_REGS + MIXER_GLB_DBUFF_REG);
>> +}
>> +
>> +/*
>> + * cleanup a mixer
>> + *
>> + * This is needed only once after power on.
>> + */
>> +static void de2_mixer_cleanup(struct priv *priv, int mixer,
>> + u32 size)
>> +{
>> + void __iomem *mixer_io = priv->mmio;
>> + void __iomem *chan_io;
>> + u32 data;
>> + unsigned int i;
>> +
>> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
>> + chan_io = mixer_io + MIXER_CHAN_REGS;
>> +
>> + andl_relaxed(priv->mmio + DE2_SEL_REG, ~1);
>> + writel_relaxed(1, mixer_io + MIXER_GLB_REGS + MIXER_GLB_DBUFF_REG);
>> +
>> + writel_relaxed(MIXER_GLB_CTL_rt_en,
>> + mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
>> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_STATUS_REG);
>> +
>> + writel_relaxed(size, mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
>> +
>> + /*
>> + * clear the VI/UI channels
>> + * LCD0: 1 VI and 3 UIs
>> + * LCD1: 1 VI and 1 UI
>> + */
>> + memset_io(chan_io, 0, VI_SIZE);
>> + memset_io(chan_io + MIXER_CHAN_SZ, 0, UI_SIZE);
>> + if (mixer == 0) {
>> + memset_io(chan_io + MIXER_CHAN_SZ * 2, 0, UI_SIZE);
>> + memset_io(chan_io + MIXER_CHAN_SZ * 3, 0, UI_SIZE);
>> + }
>> +
>> + /* alpha blending */
>> + writel_relaxed(0x00000001 | /* fcolor for primary */
>> + MIXER_BLD_FCOLOR_CTL_PEN(0),
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_FCOLOR_CTL_REG);
>> + for (i = 0; i < MIXER_BLD_ATTR_N; i++) {
>> + writel_relaxed(0xff000000,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_FCOLOR(i));
>> + writel_relaxed(size,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_INSIZE(i));
>> + writel_relaxed(0,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_OFFSET(i));
>> + }
>> + writel_relaxed(0, mixer_io + MIXER_BLD_REGS + MIXER_BLD_OUT_CTL_REG);
>> +
>> + /* prepare the pipe route for the planes */
>> + data = 0;
>> + for (i = 0; i < DE2_N_PLANES; i++)
>> + data |= MIXER_BLD_ROUTE(plane_tb[i].chan, plane_tb[i].pipe);
>> + writel_relaxed(data, mixer_io + MIXER_BLD_REGS + MIXER_BLD_ROUTE_REG);
>> +
>> + writel_relaxed(0, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_PREMULTIPLY_REG);
>> + writel_relaxed(0xff000000, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_BKCOLOR_REG);
>> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_OUTPUT_SIZE_REG);
>> + writel_relaxed(MIXER_BLD_MODE_SRCOVER,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_MODEx_REG(0));
>> + writel_relaxed(MIXER_BLD_MODE_SRCOVER,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_MODEx_REG(1));
>> +
>> + /* disable the enhancements */
>> + writel_relaxed(0, mixer_io + MIXER_VSU_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_GSU1_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_GSU2_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_GSU3_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_FCE_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_BWS_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_LTI_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_PEAK_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_ASE_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_FCC_REGS);
>> + writel_relaxed(0, mixer_io + MIXER_DCSC_REGS);
>> +}
>> +
>> +/* enable a mixer */
>> +static void de2_mixer_enable(struct lcd *lcd)
>> +{
>> + struct priv *priv = lcd->priv;
>> + void __iomem *mixer_io = priv->mmio;
>> + struct drm_display_mode *mode = &lcd->crtc.mode;
>> + u32 size = WH(mode->hdisplay, mode->vdisplay);
>> + u32 data;
>> + int mixer = lcd->mixer;
>> + int i;
>> +
>> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
>> +
>> + /* if not done yet, start the DE processor */
>> + if (!priv->started) {
>> + reset_control_deassert(priv->reset);
>> + clk_prepare_enable(priv->gate);
>> + clk_prepare_enable(priv->clk);
>> + }
>> + priv->started |= 1 << mixer;
>> +
>> + /* set the A83T clock divider (500 / 2) = 250MHz */
>> + if (priv->soc_type == SOC_A83T)
>> + writel_relaxed(0x00000011, /* div = 2 for both LCDs */
>> + priv->mmio + DE2_DIV_REG);
>> +
>> + /* deassert the mixer and enable its clock */
>> + orl_relaxed(priv->mmio + DE2_RESET_REG, mixer == 0 ? 1 : 4);
>> + data = 1 << mixer; /* 1 bit / lcd */
>> + orl_relaxed(priv->mmio + DE2_GATE_REG, data);
>> + orl_relaxed(priv->mmio + DE2_MOD_REG, data);
>> +
>> + /* if not done yet, cleanup and enable */
>> + if (!(priv->clean & (1 << mixer))) {
>> + priv->clean |= 1 << mixer;
>> + de2_mixer_cleanup(priv, mixer, size);
>> + return;
>> + }
>> +
>> + /* enable */
>> + de2_mixer_select(priv, mixer, mixer_io);
>> +
>> + writel_relaxed(MIXER_GLB_CTL_rt_en,
>> + mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
>> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_STATUS_REG);
>> +
>> + /* set the size of the frame buffer */
>> + writel_relaxed(size, mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
>> + for (i = 0; i < MIXER_BLD_ATTR_N; i++)
>> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_ATTRx_INSIZE(i));
>> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_OUTPUT_SIZE_REG);
>> +
>> + writel_relaxed(mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 0,
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_OUT_CTL_REG);
>> +}
>> +
>> +/* enable a LCD (DE mixer) */
>> +void de2_de_enable(struct lcd *lcd)
>> +{
>> + mutex_lock(&lcd->priv->mutex);
>> +
>> + de2_mixer_enable(lcd);
>> +
>> + mutex_unlock(&lcd->priv->mutex);
>> +}
>> +
>> +/* disable a LCD (DE mixer) */
>> +void de2_de_disable(struct lcd *lcd)
>> +{
>> + struct priv *priv = lcd->priv;
>> + void __iomem *mixer_io = priv->mmio;
>> + int mixer = lcd->mixer;
>> + u32 data;
>> +
>> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
>> +
>> + mutex_lock(&priv->mutex);
>> +
>> + de2_mixer_select(priv, mixer, mixer_io);
>> +
>> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
>> +
>> + data = ~(1 << mixer);
>> + andl_relaxed(priv->mmio + DE2_MOD_REG, data);
>> + andl_relaxed(priv->mmio + DE2_GATE_REG, data);
>> + andl_relaxed(priv->mmio + DE2_RESET_REG, data);
>> +
>> + mutex_unlock(&priv->mutex);
>> +
>> + /* if all mixers are disabled, stop the DE */
>> + priv->started &= ~(1 << mixer);
>> + if (!priv->started) {
>> + clk_disable_unprepare(priv->clk);
>> + clk_disable_unprepare(priv->gate);
>> + reset_control_assert(priv->reset);
>> + }
>> +}
>> +
>> +static void de2_vi_update(void __iomem *chan_io,
>> + struct drm_gem_cma_object *gem,
>> + int layer,
>> + unsigned int fmt,
>> + u32 ui_sel,
>> + u32 size,
>> + u32 coord,
>> + struct drm_framebuffer *fb,
>> + u32 screen_size)
>> +{
>> + int i;
>> +
>> + writel_relaxed(VI_CFG_ATTR_en |
>> + (fmt << VI_CFG_ATTR_fmt_SHIFT) |
>> + ui_sel,
>> + chan_io + VI_CFGx_ATTR(layer));
>> + writel_relaxed(size, chan_io + VI_CFGx_SIZE(layer));
>> + writel_relaxed(coord, chan_io + VI_CFGx_COORD(layer));
>> + for (i = 0; i < VI_N_PLANES; i++) {
>> + writel_relaxed(fb->pitches[i] ? fb->pitches[i] :
>> + fb->pitches[0],
>> + chan_io + VI_CFGx_PITCHy(layer, i));
>> + writel_relaxed(gem->paddr + fb->offsets[i],
>> + chan_io + VI_CFGx_TOP_LADDRy(layer, i));
>> + }
>> + writel_relaxed(0xff000000, chan_io + VI_FCOLORx(layer));
>> + if (layer == 0) {
>> + writel_relaxed(screen_size,
>> + chan_io + VI_OVL_SIZEx(0));
>> + }
>> +}
>> +
>> +static void de2_ui_update(void __iomem *chan_io,
>> + struct drm_gem_cma_object *gem,
>> + int layer,
>> + unsigned int fmt,
>> + u32 alpha_glob,
>> + u32 size,
>> + u32 coord,
>> + struct drm_framebuffer *fb,
>> + u32 screen_size)
>> +{
>> + writel_relaxed(UI_CFG_ATTR_en |
>> + (fmt << UI_CFG_ATTR_fmt_SHIFT) |
>> + alpha_glob,
>> + chan_io + UI_CFGx_ATTR(layer));
>> + writel_relaxed(size, chan_io + UI_CFGx_SIZE(layer));
>> + writel_relaxed(coord, chan_io + UI_CFGx_COORD(layer));
>> + writel_relaxed(fb->pitches[0], chan_io + UI_CFGx_PITCH(layer));
>> + writel_relaxed(gem->paddr + fb->offsets[0],
>> + chan_io + UI_CFGx_TOP_LADDR(layer));
>> + if (layer == 0)
>> + writel_relaxed(screen_size, chan_io + UI_OVL_SIZE);
>> +}
>> +
>> +static void de2_plane_update(struct priv *priv, struct lcd *lcd,
>> + int plane_num,
>> + struct drm_plane_state *state,
>> + struct drm_plane_state *old_state)
>> +{
>> + void __iomem *mixer_io = priv->mmio;
>> + void __iomem *chan_io;
>> + struct drm_framebuffer *fb = state->fb;
>> + struct drm_gem_cma_object *gem;
>> + u32 size = WH(state->crtc_w, state->crtc_h);
>> + u32 coord, screen_size;
>> + u32 fcolor;
>> + u32 ui_sel, alpha_glob;
>> + int mixer = lcd->mixer;
>> + int chan, layer, x, y;
>> + unsigned int fmt;
>> +
>> + chan = plane_tb[plane_num].chan;
>> + layer = plane_tb[plane_num].layer;
>> +
>> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
>> + chan_io = mixer_io + MIXER_CHAN_REGS + MIXER_CHAN_SZ * chan;
>> +
>> + x = state->crtc_x >= 0 ? state->crtc_x : 0;
>> + y = state->crtc_y >= 0 ? state->crtc_y : 0;
>> + coord = XY(x, y);
>> +
>> + /* if plane update was delayed, force a full update */
>> + if (priv->lcds[drm_crtc_index(&lcd->crtc)]->delayed &
>> + (1 << plane_num)) {
>> + priv->lcds[drm_crtc_index(&lcd->crtc)]->delayed &=
>> + ~(1 << plane_num);
>> +
>> + /* handle plane move */
>> + } else if (fb == old_state->fb) {
>> + de2_mixer_select(priv, mixer, mixer_io);
>> + if (chan == 0)
>> + writel_relaxed(coord, chan_io + VI_CFGx_COORD(layer));
>> + else
>> + writel_relaxed(coord, chan_io + UI_CFGx_COORD(layer));
>> + return;
>> + }
>> +
>> + gem = drm_fb_cma_get_gem_obj(fb, 0);
>> +
>> + ui_sel = alpha_glob = 0;
>> +
>> + switch (fb->pixel_format) {
>> + case DRM_FORMAT_ARGB8888:
>> + fmt = DE2_FORMAT_ARGB_8888;
>> + ui_sel = VI_CFG_ATTR_ui_sel;
>> + break;
>> + case DRM_FORMAT_BGRA8888:
>> + fmt = DE2_FORMAT_BGRA_8888;
>> + ui_sel = VI_CFG_ATTR_ui_sel;
>> + break;
>> + case DRM_FORMAT_XRGB8888:
>> + fmt = DE2_FORMAT_XRGB_8888;
>> + ui_sel = VI_CFG_ATTR_ui_sel;
>> + alpha_glob = (1 << UI_CFG_ATTR_alpmod_SHIFT) |
>> + (0xff << UI_CFG_ATTR_alpha_SHIFT);
>> + break;
>> + case DRM_FORMAT_RGB888:
>> + fmt = DE2_FORMAT_RGB_888;
>> + ui_sel = VI_CFG_ATTR_ui_sel;
>> + break;
>> + case DRM_FORMAT_BGR888:
>> + fmt = DE2_FORMAT_BGR_888;
>> + ui_sel = VI_CFG_ATTR_ui_sel;
>> + break;
>> + case DRM_FORMAT_YUYV:
>> + fmt = DE2_FORMAT_YUV422_I_YUYV;
>> + break;
>> + case DRM_FORMAT_YVYU:
>> + fmt = DE2_FORMAT_YUV422_I_YVYU;
>> + break;
>> + case DRM_FORMAT_YUV422:
>> + fmt = DE2_FORMAT_YUV422_P;
>> + break;
>> + case DRM_FORMAT_YUV420:
>> + fmt = DE2_FORMAT_YUV420_P;
>> + break;
>> + case DRM_FORMAT_UYVY:
>> + fmt = DE2_FORMAT_YUV422_I_UYVY;
>> + break;
>> + default:
>> + pr_err("de2_plane_update: format %.4s not yet treated\n",
>> + (char *) &fb->pixel_format);
>> + return;
>> + }
>> +
>> + /* the overlay size is the one of the primary plane */
>> + screen_size = plane_num == DE2_PRIMARY_PLANE ?
>> + size :
>> + readl_relaxed(mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
>> +
>> + /* prepare pipe enable */
>> + fcolor = readl_relaxed(mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_FCOLOR_CTL_REG);
>> + fcolor |= MIXER_BLD_FCOLOR_CTL_PEN(plane_tb[plane_num].pipe);
>> +
>> + de2_mixer_select(priv, mixer, mixer_io);
>> +
>> + if (chan == 0) /* VI channel */
>> + de2_vi_update(chan_io, gem, layer, fmt, ui_sel, size, coord,
>> + fb, screen_size);
>> + else /* UI channel */
>> + de2_ui_update(chan_io, gem, layer, fmt, alpha_glob, size, coord,
>> + fb, screen_size);
>> + writel_relaxed(fcolor, mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_FCOLOR_CTL_REG);
>> +}
>> +
>> +static int vi_nb_layers(void __iomem *chan_io)
>> +{
>> + int layer, n = 0;
>> +
>> + for (layer = 0; layer < 4; layer++) {
>> + if (readl_relaxed(chan_io + VI_CFGx_ATTR(layer)) != 0)
>> + n++;
>> + }
>> +
>> + return n;
>> +}
>> +
>> +static int ui_nb_layers(void __iomem *chan_io)
>> +{
>> + int layer, n = 0;
>> +
>> + for (layer = 0; layer < 4; layer++) {
>> + if (readl_relaxed(chan_io + UI_CFGx_ATTR(layer)) != 0)
>> + n++;
>> + }
>> +
>> + return n;
>> +}
>> +
>> +static void de2_plane_disable(struct priv *priv,
>> + int mixer, int plane_num)
>> +{
>> + void __iomem *mixer_io = priv->mmio;
>> + void __iomem *chan_io;
>> + u32 fcolor;
>> + int chan, layer, n;
>> +
>> + chan = plane_tb[plane_num].chan;
>> + layer = plane_tb[plane_num].layer;
>> +
>> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
>> + chan_io = mixer_io + MIXER_CHAN_REGS + MIXER_CHAN_SZ * chan;
>> +
>> + if (chan == 0)
>> + n = vi_nb_layers(chan_io);
>> + else
>> + n = ui_nb_layers(chan_io);
>> +
>> + fcolor = readl_relaxed(mixer_io + MIXER_BLD_REGS +
>> + MIXER_BLD_FCOLOR_CTL_REG);
>> +
>> + de2_mixer_select(priv, mixer, mixer_io);
>> +
>> + if (chan == 0)
>> + writel_relaxed(0, chan_io + VI_CFGx_ATTR(layer));
>> + else
>> + writel_relaxed(0, chan_io + UI_CFGx_ATTR(layer));
>> +
>> + /* disable the pipe if no more active layer */
>> + if (n <= 1)
>> + writel_relaxed(fcolor &
>> + ~MIXER_BLD_FCOLOR_CTL_PEN(plane_tb[plane_num].pipe),
>> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_FCOLOR_CTL_REG);
>> +}
>> +
>> +static void de2_drm_plane_update(struct drm_plane *plane,
>> + struct drm_plane_state *old_state)
>> +{
>> + struct drm_plane_state *state = plane->state;
>> + struct drm_crtc *crtc = state->crtc;
>> + struct lcd *lcd = crtc_to_lcd(crtc);
>> + struct priv *priv = lcd->priv;
>> + int plane_num = plane - lcd->planes;
>> +
>> + /* if the crtc is disabled, mark update delayed */
>> + if (!(priv->started & (1 << lcd->mixer))) {
>> + lcd->delayed |= 1 << plane_num;
>> + return; /* mixer disabled */
>> + }
>> +
>> + mutex_lock(&priv->mutex);
>> +
>> + de2_plane_update(priv, lcd, plane_num, state, old_state);
>> +
>> + mutex_unlock(&priv->mutex);
>> +}
>> +
>> +static void de2_drm_plane_disable(struct drm_plane *plane,
>> + struct drm_plane_state *old_state)
>> +{
>> + struct drm_crtc *crtc = old_state->crtc;
>> + struct lcd *lcd = crtc_to_lcd(crtc);
>> + struct priv *priv = lcd->priv;
>> + int plane_num = plane - lcd->planes;
>> +
>> + if (!(priv->started & (1 << lcd->mixer)))
>> + return; /* mixer disabled */
>> +
>> + mutex_lock(&priv->mutex);
>> +
>> + de2_plane_disable(lcd->priv, lcd->mixer, plane_num);
>> +
>> + mutex_unlock(&priv->mutex);
>> +}
>> +
>> +static const struct drm_plane_helper_funcs plane_helper_funcs = {
>> + .atomic_update = de2_drm_plane_update,
>> + .atomic_disable = de2_drm_plane_disable,
>> +};
>> +
>> +static const struct drm_plane_funcs plane_funcs = {
>> + .update_plane = drm_atomic_helper_update_plane,
>> + .disable_plane = drm_atomic_helper_disable_plane,
>> + .destroy = drm_plane_cleanup,
>> + .reset = drm_atomic_helper_plane_reset,
>> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
>> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
>> +};
>> +
>> +static int de2_one_plane_init(struct drm_device *drm,
>> + struct drm_plane *plane,
>> + int possible_crtcs,
>> + int plane_num)
>> +{
>> + int ret;
>> +
>> + ret = drm_universal_plane_init(drm, plane, possible_crtcs,
>> + &plane_funcs,
>> + plane_tb[plane_num].formats,
>> + plane_tb[plane_num].n_formats,
>> + plane_tb[plane_num].type, NULL);
>> + if (ret >= 0)
>> + drm_plane_helper_add(plane, &plane_helper_funcs);
>> +
>> + return ret;
>> +}
>> +
>> +/* initialize the planes */
>> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd)
>> +{
>> + int i, n, ret, possible_crtcs = 1 << drm_crtc_index(&lcd->crtc);
>> +
>> + n = ARRAY_SIZE(plane_tb);
>> + if (n != DE2_N_PLANES) {
>> + dev_err(lcd->dev, "Bug: incorrect number of planes %d != "
>> + __stringify(DE2_N_PLANES) "\n", n);
>> + return -EINVAL;
>> + }
>> +
>> + for (i = 0; i < n; i++) {
>> + ret = de2_one_plane_init(drm, &lcd->planes[i],
>> + possible_crtcs, i);
>> + if (ret < 0) {
>> + dev_err(lcd->dev, "plane init failed %d\n", ret);
>> + break;
>> + }
>> + }
>> +
>> + return ret;
>> +}
>> --
>> 2.10.2
>
>> _______________________________________________
>> dri-devel mailing list
>> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel
>
> --
> Daniel Vetter
> Software Engineer, Intel Corporation
> http://blog.ffwll.ch
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
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^ permalink raw reply
* Re: [PATCH v7 1/8] drm: sun8i: Add a basic DRM driver for Allwinner DE2
From: Daniel Vetter @ 2016-11-29 14:30 UTC (permalink / raw)
To: Jean-Francois Moine
Cc: Dave Airlie, Maxime Ripard, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
In-Reply-To: <592a49a2d9505fc0f09b555847892fb7a4047530.1480414715.git.moinejf-GANU6spQydw@public.gmane.org>
On Mon, Nov 28, 2016 at 03:23:54PM +0100, Jean-Francois Moine wrote:
> Allwinner's recent SoCs, as A64, A83T and H3, contain a new display
> engine, DE2.
> This patch adds a DRM video driver for this device.
>
> Signed-off-by: Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
Scrolled around a bit, seemed all reasonable.
Acked-by: Daniel Vetter <daniel.vetter-/w4YWyX8dFk@public.gmane.org>
Not sure a new driver for each chip is reasonable, experience says that
long-term you want to share quite a pile of code between different hw
platforms from the same vendor. But that's entirely up to you.
-Daniel
> ---
> drivers/gpu/drm/Kconfig | 2 +
> drivers/gpu/drm/Makefile | 1 +
> drivers/gpu/drm/sun8i/Kconfig | 19 +
> drivers/gpu/drm/sun8i/Makefile | 7 +
> drivers/gpu/drm/sun8i/de2_crtc.c | 449 +++++++++++++++++++++++
> drivers/gpu/drm/sun8i/de2_crtc.h | 50 +++
> drivers/gpu/drm/sun8i/de2_drv.c | 317 ++++++++++++++++
> drivers/gpu/drm/sun8i/de2_drv.h | 48 +++
> drivers/gpu/drm/sun8i/de2_plane.c | 734 ++++++++++++++++++++++++++++++++++++++
> 9 files changed, 1627 insertions(+)
> create mode 100644 drivers/gpu/drm/sun8i/Kconfig
> create mode 100644 drivers/gpu/drm/sun8i/Makefile
> create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.c
> create mode 100644 drivers/gpu/drm/sun8i/de2_crtc.h
> create mode 100644 drivers/gpu/drm/sun8i/de2_drv.c
> create mode 100644 drivers/gpu/drm/sun8i/de2_drv.h
> create mode 100644 drivers/gpu/drm/sun8i/de2_plane.c
>
> diff --git a/drivers/gpu/drm/Kconfig b/drivers/gpu/drm/Kconfig
> index 95fc041..bb1bfbc 100644
> --- a/drivers/gpu/drm/Kconfig
> +++ b/drivers/gpu/drm/Kconfig
> @@ -202,6 +202,8 @@ source "drivers/gpu/drm/shmobile/Kconfig"
>
> source "drivers/gpu/drm/sun4i/Kconfig"
>
> +source "drivers/gpu/drm/sun8i/Kconfig"
> +
> source "drivers/gpu/drm/omapdrm/Kconfig"
>
> source "drivers/gpu/drm/tilcdc/Kconfig"
> diff --git a/drivers/gpu/drm/Makefile b/drivers/gpu/drm/Makefile
> index 883f3e7..3e1eaa0 100644
> --- a/drivers/gpu/drm/Makefile
> +++ b/drivers/gpu/drm/Makefile
> @@ -72,6 +72,7 @@ obj-$(CONFIG_DRM_RCAR_DU) += rcar-du/
> obj-$(CONFIG_DRM_SHMOBILE) +=shmobile/
> obj-y += omapdrm/
> obj-$(CONFIG_DRM_SUN4I) += sun4i/
> +obj-$(CONFIG_DRM_SUN8I) += sun8i/
> obj-y += tilcdc/
> obj-$(CONFIG_DRM_QXL) += qxl/
> obj-$(CONFIG_DRM_BOCHS) += bochs/
> diff --git a/drivers/gpu/drm/sun8i/Kconfig b/drivers/gpu/drm/sun8i/Kconfig
> new file mode 100644
> index 0000000..6940895
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/Kconfig
> @@ -0,0 +1,19 @@
> +#
> +# Allwinner DE2 Video configuration
> +#
> +
> +config DRM_SUN8I
> + bool
> +
> +config DRM_SUN8I_DE2
> + tristate "Support for Allwinner Video with DE2 interface"
> + depends on DRM && OF
> + depends on ARCH_SUNXI || COMPILE_TEST
> + select DRM_GEM_CMA_HELPER
> + select DRM_KMS_CMA_HELPER
> + select DRM_KMS_HELPER
> + select DRM_SUN8I
> + help
> + Choose this option if your Allwinner chipset has the DE2 interface
> + as the A64, A83T and H3. If M is selected the module will be called
> + sun8i-de2-drm.
> diff --git a/drivers/gpu/drm/sun8i/Makefile b/drivers/gpu/drm/sun8i/Makefile
> new file mode 100644
> index 0000000..f107919
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/Makefile
> @@ -0,0 +1,7 @@
> +#
> +# Makefile for Allwinner's sun8i DRM device driver
> +#
> +
> +sun8i-de2-drm-objs := de2_drv.o de2_crtc.o de2_plane.o
> +
> +obj-$(CONFIG_DRM_SUN8I_DE2) += sun8i-de2-drm.o
> diff --git a/drivers/gpu/drm/sun8i/de2_crtc.c b/drivers/gpu/drm/sun8i/de2_crtc.c
> new file mode 100644
> index 0000000..4e94ccc
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/de2_crtc.c
> @@ -0,0 +1,449 @@
> +/*
> + * Allwinner DRM driver - DE2 CRTC
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/component.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <linux/io.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_graph.h>
> +
> +#include "de2_drv.h"
> +#include "de2_crtc.h"
> +
> +/* I/O map */
> +
> +#define TCON_GCTL_REG 0x00
> +#define TCON_GCTL_TCON_ENABLE BIT(31)
> +#define TCON_GINT0_REG 0x04
> +#define TCON_GINT0_TCON1_Vb_Int_En BIT(30)
> +#define TCON_GINT0_TCON1_Vb_Int_Flag BIT(14)
> +#define TCON_GINT0_TCON1_Vb_Line_Int_Flag BIT(12)
> +#define TCON0_CTL_REG 0x40
> +#define TCON0_CTL_TCON_ENABLE BIT(31)
> +#define TCON1_CTL_REG 0x90
> +#define TCON1_CTL_TCON_ENABLE BIT(31)
> +#define TCON1_CTL_INTERLACE_ENABLE BIT(20)
> +#define TCON1_CTL_Start_Delay_SHIFT 4
> +#define TCON1_CTL_Start_Delay_MASK GENMASK(8, 4)
> +#define TCON1_BASIC0_REG 0x94 /* XI/YI */
> +#define TCON1_BASIC1_REG 0x98 /* LS_XO/LS_YO */
> +#define TCON1_BASIC2_REG 0x9c /* XO/YO */
> +#define TCON1_BASIC3_REG 0xa0 /* HT/HBP */
> +#define TCON1_BASIC4_REG 0xa4 /* VT/VBP */
> +#define TCON1_BASIC5_REG 0xa8 /* HSPW/VSPW */
> +#define TCON1_PS_SYNC_REG 0xb0
> +#define TCON1_IO_POL_REG 0xf0
> +#define TCON1_IO_POL_IO0_inv BIT(24)
> +#define TCON1_IO_POL_IO1_inv BIT(25)
> +#define TCON1_IO_POL_IO2_inv BIT(26)
> +#define TCON1_IO_TRI_REG 0xf4
> +#define TCON_CEU_CTL_REG 0x100
> +#define TCON_CEU_CTL_ceu_en BIT(31)
> +#define TCON1_FILL_CTL_REG 0x300
> +#define TCON1_FILL_START0_REG 0x304
> +#define TCON1_FILL_END0_REG 0x308
> +#define TCON1_FILL_DATA0_REG 0x30c
> +
> +#define XY(x, y) (((x) << 16) | (y))
> +
> +#define andl_relaxed(addr, val) \
> + writel_relaxed(readl_relaxed(addr) & val, addr)
> +#define orl_relaxed(addr, val) \
> + writel_relaxed(readl_relaxed(addr) | val, addr)
> +
> +/* vertical blank functions */
> +
> +static void de2_atomic_flush(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_state)
> +{
> + struct drm_pending_vblank_event *event = crtc->state->event;
> +
> + if (event) {
> + crtc->state->event = NULL;
> + spin_lock_irq(&crtc->dev->event_lock);
> + if (drm_crtc_vblank_get(crtc) == 0)
> + drm_crtc_arm_vblank_event(crtc, event);
> + else
> + drm_crtc_send_vblank_event(crtc, event);
> + spin_unlock_irq(&crtc->dev->event_lock);
> + }
> +}
> +
> +static irqreturn_t de2_lcd_irq(int irq, void *dev_id)
> +{
> + struct lcd *lcd = (struct lcd *) dev_id;
> + u32 isr;
> +
> + isr = readl_relaxed(lcd->mmio + TCON_GINT0_REG);
> +
> + drm_crtc_handle_vblank(&lcd->crtc);
> +
> + writel_relaxed(isr &
> + ~(TCON_GINT0_TCON1_Vb_Int_Flag |
> + TCON_GINT0_TCON1_Vb_Line_Int_Flag),
> + lcd->mmio + TCON_GINT0_REG);
> +
> + return IRQ_HANDLED;
> +}
> +
> +int de2_enable_vblank(struct drm_device *drm, unsigned int crtc_ix)
> +{
> + struct priv *priv = drm_to_priv(drm);
> + struct lcd *lcd = priv->lcds[crtc_ix];
> +
> + orl_relaxed(lcd->mmio + TCON_GINT0_REG, TCON_GINT0_TCON1_Vb_Int_En);
> +
> + return 0;
> +}
> +
> +void de2_disable_vblank(struct drm_device *drm, unsigned int crtc_ix)
> +{
> + struct priv *priv = drm_to_priv(drm);
> + struct lcd *lcd = priv->lcds[crtc_ix];
> +
> + andl_relaxed(lcd->mmio + TCON_GINT0_REG, ~TCON_GINT0_TCON1_Vb_Int_En);
> +}
> +
> +void de2_vblank_reset(struct lcd *lcd)
> +{
> + drm_crtc_vblank_reset(&lcd->crtc);
> +}
> +
> +/* frame functions */
> +static int de2_crtc_set_clock(struct lcd *lcd, int rate)
> +{
> + struct clk *parent_clk;
> + u32 parent_rate;
> + int ret;
> +
> + /* determine and set the best rate for the parent clock (pll-video) */
> + if ((270000 * 2) % rate == 0)
> + parent_rate = 270000000;
> + else if (297000 % rate == 0)
> + parent_rate = 297000000;
> + else
> + return -EINVAL; /* unsupported clock */
> +
> + parent_clk = clk_get_parent(lcd->clk);
> +
> + ret = clk_set_rate(parent_clk, parent_rate);
> + if (ret) {
> + dev_err(lcd->dev, "set parent rate failed %d\n", ret);
> + return ret;
> + }
> + ret = clk_set_rate(lcd->clk, rate * 1000);
> + if (ret) {
> + dev_err(lcd->dev, "set rate failed %d\n", ret);
> + return ret;
> + }
> +
> + /* enable the clock */
> + reset_control_deassert(lcd->reset);
> + clk_prepare_enable(lcd->bus);
> + clk_prepare_enable(lcd->clk);
> +
> + return ret;
> +}
> +
> +static void de2_tcon_init(struct lcd *lcd)
> +{
> + andl_relaxed(lcd->mmio + TCON0_CTL_REG, ~TCON0_CTL_TCON_ENABLE);
> + andl_relaxed(lcd->mmio + TCON1_CTL_REG, ~TCON1_CTL_TCON_ENABLE);
> + andl_relaxed(lcd->mmio + TCON_GCTL_REG, ~TCON_GCTL_TCON_ENABLE);
> +
> + /* disable/ack interrupts */
> + writel_relaxed(0, lcd->mmio + TCON_GINT0_REG);
> +}
> +
> +static void de2_tcon_enable(struct lcd *lcd)
> +{
> + struct drm_crtc *crtc = &lcd->crtc;
> + const struct drm_display_mode *mode = &crtc->mode;
> + int interlace = mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 1;
> + int start_delay;
> + u32 data;
> +
> + orl_relaxed(lcd->mmio + TCON_GCTL_REG, TCON_GCTL_TCON_ENABLE);
> +
> + data = XY(mode->hdisplay - 1, mode->vdisplay / interlace - 1);
> + writel_relaxed(data, lcd->mmio + TCON1_BASIC0_REG);
> + writel_relaxed(data, lcd->mmio + TCON1_BASIC1_REG);
> + writel_relaxed(data, lcd->mmio + TCON1_BASIC2_REG);
> + writel_relaxed(XY(mode->htotal - 1,
> + mode->htotal - mode->hsync_start - 1),
> + lcd->mmio + TCON1_BASIC3_REG);
> + writel_relaxed(XY(mode->vtotal * (3 - interlace),
> + mode->vtotal - mode->vsync_start - 1),
> + lcd->mmio + TCON1_BASIC4_REG);
> + writel_relaxed(XY(mode->hsync_end - mode->hsync_start - 1,
> + mode->vsync_end - mode->vsync_start - 1),
> + lcd->mmio + TCON1_BASIC5_REG);
> +
> + data = TCON1_IO_POL_IO2_inv;
> + if (mode->flags & DRM_MODE_FLAG_PVSYNC)
> + data |= TCON1_IO_POL_IO0_inv;
> + if (mode->flags & DRM_MODE_FLAG_PHSYNC)
> + data |= TCON1_IO_POL_IO1_inv;
> + writel_relaxed(data, lcd->mmio + TCON1_IO_POL_REG);
> +
> + andl_relaxed(lcd->mmio + TCON_CEU_CTL_REG, ~TCON_CEU_CTL_ceu_en);
> +
> + if (interlace == 2)
> + orl_relaxed(lcd->mmio + TCON1_CTL_REG,
> + TCON1_CTL_INTERLACE_ENABLE);
> + else
> + andl_relaxed(lcd->mmio + TCON1_CTL_REG,
> + ~TCON1_CTL_INTERLACE_ENABLE);
> +
> + writel_relaxed(0, lcd->mmio + TCON1_FILL_CTL_REG);
> + writel_relaxed(mode->vtotal + 1, lcd->mmio + TCON1_FILL_START0_REG);
> + writel_relaxed(mode->vtotal, lcd->mmio + TCON1_FILL_END0_REG);
> + writel_relaxed(0, lcd->mmio + TCON1_FILL_DATA0_REG);
> +
> + start_delay = (mode->vtotal - mode->vdisplay) / interlace - 5;
> + if (start_delay > 31)
> + start_delay = 31;
> + data = readl_relaxed(lcd->mmio + TCON1_CTL_REG);
> + data &= ~TCON1_CTL_Start_Delay_MASK;
> + data |= start_delay << TCON1_CTL_Start_Delay_SHIFT;
> + writel_relaxed(data, lcd->mmio + TCON1_CTL_REG);
> +
> + orl_relaxed(lcd->mmio + TCON1_CTL_REG, TCON1_CTL_TCON_ENABLE);
> +}
> +
> +static void de2_tcon_disable(struct lcd *lcd)
> +{
> + andl_relaxed(lcd->mmio + TCON1_CTL_REG, ~TCON1_CTL_TCON_ENABLE);
> + andl_relaxed(lcd->mmio + TCON_GCTL_REG, ~TCON_GCTL_TCON_ENABLE);
> +}
> +
> +static void de2_crtc_enable(struct drm_crtc *crtc)
> +{
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + struct drm_display_mode *mode = &crtc->mode;
> +
> + if (de2_crtc_set_clock(lcd, mode->clock) < 0)
> + return;
> + lcd->clk_enabled = true;
> +
> + /* start the TCON and the DE */
> + de2_tcon_enable(lcd);
> + de2_de_enable(lcd);
> +
> + /* turn on blanking interrupt */
> + drm_crtc_vblank_on(crtc);
> +}
> +
> +static void de2_crtc_disable(struct drm_crtc *crtc,
> + struct drm_crtc_state *old_crtc_state)
> +{
> + struct lcd *lcd = crtc_to_lcd(crtc);
> +
> + if (!lcd->clk_enabled)
> + return; /* already disabled */
> + lcd->clk_enabled = false;
> +
> + de2_de_disable(lcd);
> +
> + drm_crtc_vblank_off(crtc);
> +
> + de2_tcon_disable(lcd);
> +
> + clk_disable_unprepare(lcd->clk);
> + clk_disable_unprepare(lcd->bus);
> + reset_control_assert(lcd->reset);
> +}
> +
> +static const struct drm_crtc_funcs de2_crtc_funcs = {
> + .destroy = drm_crtc_cleanup,
> + .set_config = drm_atomic_helper_set_config,
> + .page_flip = drm_atomic_helper_page_flip,
> + .reset = drm_atomic_helper_crtc_reset,
> + .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
> +};
> +
> +static const struct drm_crtc_helper_funcs de2_crtc_helper_funcs = {
> + .atomic_flush = de2_atomic_flush,
> + .enable = de2_crtc_enable,
> + .atomic_disable = de2_crtc_disable,
> +};
> +
> +/* device init */
> +static int de2_lcd_bind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct drm_device *drm = data;
> + struct priv *priv = drm_to_priv(drm);
> + struct lcd *lcd = dev_get_drvdata(dev);
> + struct drm_crtc *crtc = &lcd->crtc;
> + int ret, i, crtc_ix;
> +
> + lcd->priv = priv;
> +
> + /* set the CRTC reference */
> + crtc_ix = drm_crtc_index(crtc);
> + if (crtc_ix >= ARRAY_SIZE(priv->lcds)) {
> + dev_err(drm->dev, "Bad crtc index");
> + return -ENOENT;
> + }
> + priv->lcds[crtc_ix] = lcd;
> +
> + /* and the mixer index (DT port index in the DE) */
> + for (i = 0; ; i++) {
> + struct device_node *port;
> +
> + port = of_parse_phandle(drm->dev->of_node, "ports", i);
> + if (!port)
> + break;
> + if (port == lcd->crtc.port) {
> + lcd->mixer = i;
> + break;
> + }
> + }
> +
> + ret = de2_plane_init(drm, lcd);
> + if (ret < 0)
> + return ret;
> +
> + drm_crtc_helper_add(crtc, &de2_crtc_helper_funcs);
> +
> + return drm_crtc_init_with_planes(drm, crtc,
> + &lcd->planes[DE2_PRIMARY_PLANE],
> + &lcd->planes[DE2_CURSOR_PLANE],
> + &de2_crtc_funcs, NULL);
> +}
> +
> +static void de2_lcd_unbind(struct device *dev, struct device *master,
> + void *data)
> +{
> + struct platform_device *pdev = to_platform_device(dev);
> + struct lcd *lcd = platform_get_drvdata(pdev);
> +
> + if (lcd->priv)
> + lcd->priv->lcds[drm_crtc_index(&lcd->crtc)] = NULL;
> +}
> +
> +static const struct component_ops de2_lcd_ops = {
> + .bind = de2_lcd_bind,
> + .unbind = de2_lcd_unbind,
> +};
> +
> +static int de2_lcd_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node, *tmp, *parent, *port;
> + struct lcd *lcd;
> + struct resource *res;
> + int id, irq, ret;
> +
> + lcd = devm_kzalloc(dev, sizeof(*lcd), GFP_KERNEL);
> + if (!lcd)
> + return -ENOMEM;
> +
> + dev_set_drvdata(dev, lcd);
> + lcd->dev = dev;
> + lcd->mixer = id;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get memory resource\n");
> + return -EINVAL;
> + }
> +
> + lcd->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(lcd->mmio)) {
> + dev_err(dev, "failed to map registers\n");
> + return PTR_ERR(lcd->mmio);
> + }
> +
> + /* possible CRTC */
> + parent = np;
> + tmp = of_get_child_by_name(np, "ports");
> + if (tmp)
> + parent = tmp;
> + port = of_get_child_by_name(parent, "port");
> + of_node_put(tmp);
> + if (!port) {
> + dev_err(dev, "no port node\n");
> + return -ENXIO;
> + }
> + lcd->crtc.port = port;
> +
> + lcd->bus = devm_clk_get(dev, "bus");
> + if (IS_ERR(lcd->bus)) {
> + dev_err(dev, "get bus clock err %d\n", (int) PTR_ERR(lcd->bus));
> + ret = PTR_ERR(lcd->bus);
> + goto err;
> + }
> +
> + lcd->clk = devm_clk_get(dev, "clock");
> + if (IS_ERR(lcd->clk)) {
> + ret = PTR_ERR(lcd->clk);
> + dev_err(dev, "get video clock err %d\n", ret);
> + goto err;
> + }
> +
> + lcd->reset = devm_reset_control_get(dev, NULL);
> + if (IS_ERR(lcd->reset)) {
> + ret = PTR_ERR(lcd->reset);
> + dev_err(dev, "get reset err %d\n", ret);
> + goto err;
> + }
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq <= 0) {
> + dev_err(dev, "unable to get irq\n");
> + ret = -EINVAL;
> + goto err;
> + }
> +
> + de2_tcon_init(lcd); /* stop TCON and avoid interrupts */
> +
> + ret = devm_request_irq(dev, irq, de2_lcd_irq, 0,
> + dev_name(dev), lcd);
> + if (ret < 0) {
> + dev_err(dev, "unable to request irq %d\n", irq);
> + goto err;
> + }
> +
> + return component_add(dev, &de2_lcd_ops);
> +
> +err:
> + of_node_put(lcd->crtc.port);
> + return ret;
> +}
> +
> +static int de2_lcd_remove(struct platform_device *pdev)
> +{
> + struct lcd *lcd = platform_get_drvdata(pdev);
> +
> + component_del(&pdev->dev, &de2_lcd_ops);
> +
> + of_node_put(lcd->crtc.port);
> +
> + return 0;
> +}
> +
> +static const struct of_device_id de2_lcd_ids[] = {
> + { .compatible = "allwinner,sun8i-a83t-tcon", },
> + { }
> +};
> +
> +struct platform_driver de2_lcd_platform_driver = {
> + .probe = de2_lcd_probe,
> + .remove = de2_lcd_remove,
> + .driver = {
> + .name = "sun8i-de2-tcon",
> + .of_match_table = of_match_ptr(de2_lcd_ids),
> + },
> +};
> diff --git a/drivers/gpu/drm/sun8i/de2_crtc.h b/drivers/gpu/drm/sun8i/de2_crtc.h
> new file mode 100644
> index 0000000..c0d34a7
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/de2_crtc.h
> @@ -0,0 +1,50 @@
> +#ifndef __DE2_CRTC_H__
> +#define __DE2_CRTC_H__
> +/*
> + * Copyright (C) 2016 Jean-Fran??ois Moine
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <drm/drm_plane_helper.h>
> +
> +struct clk;
> +struct reset_control;
> +struct priv;
> +
> +/* planes */
> +#define DE2_PRIMARY_PLANE 0
> +#define DE2_CURSOR_PLANE 1
> +#define DE2_N_PLANES 5 /* number of planes - see plane_tb[] in de2_plane.c */
> +
> +struct lcd {
> + void __iomem *mmio;
> +
> + struct device *dev;
> + struct drm_crtc crtc;
> +
> + struct priv *priv; /* DRM/DE private data */
> +
> + u8 mixer; /* LCD (mixer) number */
> + u8 delayed; /* bitmap of planes with delayed update */
> +
> + u8 clk_enabled; /* used for error in crtc_enable */
> +
> + struct clk *clk;
> + struct clk *bus;
> + struct reset_control *reset;
> +
> + struct drm_plane planes[DE2_N_PLANES];
> +};
> +
> +#define crtc_to_lcd(x) container_of(x, struct lcd, crtc)
> +
> +/* in de2_plane.c */
> +void de2_de_enable(struct lcd *lcd);
> +void de2_de_disable(struct lcd *lcd);
> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd);
> +
> +#endif /* __DE2_CRTC_H__ */
> diff --git a/drivers/gpu/drm/sun8i/de2_drv.c b/drivers/gpu/drm/sun8i/de2_drv.c
> new file mode 100644
> index 0000000..f96babe
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/de2_drv.c
> @@ -0,0 +1,317 @@
> +/*
> + * Allwinner DRM driver - DE2 DRM driver
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_device.h>
> +#include <drm/drm_of.h>
> +#include <linux/component.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +
> +#include "de2_drv.h"
> +
> +#define DRIVER_NAME "sun8i-de2"
> +#define DRIVER_DESC "Allwinner DRM DE2"
> +#define DRIVER_DATE "20161101"
> +#define DRIVER_MAJOR 1
> +#define DRIVER_MINOR 0
> +
> +static const struct of_device_id de2_drm_of_match[] = {
> + { .compatible = "allwinner,sun8i-a83t-display-engine",
> + .data = (void *) SOC_A83T },
> + { .compatible = "allwinner,sun8i-h3-display-engine",
> + .data = (void *) SOC_H3 },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, de2_drm_of_match);
> +
> +static void de2_fb_output_poll_changed(struct drm_device *drm)
> +{
> + struct priv *priv = drm_to_priv(drm);
> +
> + if (priv->fbdev)
> + drm_fbdev_cma_hotplug_event(priv->fbdev);
> +}
> +
> +static const struct drm_mode_config_funcs de2_mode_config_funcs = {
> + .fb_create = drm_fb_cma_create,
> + .output_poll_changed = de2_fb_output_poll_changed,
> + .atomic_check = drm_atomic_helper_check,
> + .atomic_commit = drm_atomic_helper_commit,
> +};
> +
> +/* -- DRM operations -- */
> +
> +static void de2_lastclose(struct drm_device *drm)
> +{
> + struct priv *priv = drm_to_priv(drm);
> +
> + if (priv->fbdev)
> + drm_fbdev_cma_restore_mode(priv->fbdev);
> +}
> +
> +static const struct file_operations de2_fops = {
> + .owner = THIS_MODULE,
> + .open = drm_open,
> + .release = drm_release,
> + .unlocked_ioctl = drm_ioctl,
> + .poll = drm_poll,
> + .read = drm_read,
> + .llseek = no_llseek,
> + .mmap = drm_gem_cma_mmap,
> +};
> +
> +static struct drm_driver de2_drm_driver = {
> + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_PRIME |
> + DRIVER_ATOMIC,
> + .lastclose = de2_lastclose,
> + .get_vblank_counter = drm_vblank_no_hw_counter,
> + .enable_vblank = de2_enable_vblank,
> + .disable_vblank = de2_disable_vblank,
> + .gem_free_object = drm_gem_cma_free_object,
> + .gem_vm_ops = &drm_gem_cma_vm_ops,
> + .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
> + .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
> + .gem_prime_import = drm_gem_prime_import,
> + .gem_prime_export = drm_gem_prime_export,
> + .gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
> + .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
> + .gem_prime_vmap = drm_gem_cma_prime_vmap,
> + .gem_prime_vunmap = drm_gem_cma_prime_vunmap,
> + .gem_prime_mmap = drm_gem_cma_prime_mmap,
> + .dumb_create = drm_gem_cma_dumb_create,
> + .dumb_map_offset = drm_gem_cma_dumb_map_offset,
> + .dumb_destroy = drm_gem_dumb_destroy,
> + .fops = &de2_fops,
> + .name = DRIVER_NAME,
> + .desc = DRIVER_DESC,
> + .date = DRIVER_DATE,
> + .major = DRIVER_MAJOR,
> + .minor = DRIVER_MINOR,
> +};
> +
> +/*
> + * Platform driver
> + */
> +
> +static int de2_drm_bind(struct device *dev)
> +{
> + struct drm_device *drm;
> + struct priv *priv;
> + struct resource *res;
> + struct lcd *lcd;
> + int i, ret;
> +
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + drm = &priv->drm;
> + dev_set_drvdata(dev, drm);
> +
> + /* get the resources */
> + priv->soc_type = (int) of_match_device(de2_drm_of_match, dev)->data;
> +
> + res = platform_get_resource(to_platform_device(dev),
> + IORESOURCE_MEM, 0);
> + if (!res) {
> + dev_err(dev, "failed to get memory resource\n");
> + ret = -EINVAL;
> + goto out1;
> + }
> +
> + priv->mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(priv->mmio)) {
> + ret = PTR_ERR(priv->mmio);
> + dev_err(dev, "failed to map registers %d\n", ret);
> + goto out1;
> + }
> +
> + priv->gate = devm_clk_get(dev, "bus");
> + if (IS_ERR(priv->gate)) {
> + ret = PTR_ERR(priv->gate);
> + dev_err(dev, "bus gate err %d\n", ret);
> + goto out1;
> + }
> +
> + priv->clk = devm_clk_get(dev, "clock");
> + if (IS_ERR(priv->clk)) {
> + ret = PTR_ERR(priv->clk);
> + dev_err(dev, "clock err %d\n", ret);
> + goto out1;
> + }
> +
> + priv->reset = devm_reset_control_get(dev, NULL);
> + if (IS_ERR(priv->reset)) {
> + ret = PTR_ERR(priv->reset);
> + dev_err(dev, "reset err %d\n", ret);
> + goto out1;
> + }
> +
> + mutex_init(&priv->mutex); /* protect DE I/O accesses */
> +
> + ret = drm_dev_init(drm, &de2_drm_driver, dev);
> + if (ret != 0) {
> + dev_err(dev, "dev_init failed %d\n", ret);
> + goto out1;
> + }
> +
> + drm_mode_config_init(drm);
> + drm->mode_config.min_width = 32; /* needed for cursor */
> + drm->mode_config.min_height = 32;
> + drm->mode_config.max_width = 1920;
> + drm->mode_config.max_height = 1080;
> + drm->mode_config.funcs = &de2_mode_config_funcs;
> +
> + drm->irq_enabled = true;
> +
> + /* start the subdevices */
> + ret = component_bind_all(dev, drm);
> + if (ret < 0)
> + goto out2;
> +
> + /* initialize and disable vertical blanking on all CRTCs */
> + ret = drm_vblank_init(drm, drm->mode_config.num_crtc);
> + if (ret < 0)
> + dev_warn(dev, "vblank_init failed %d\n", ret);
> +
> + for (i = 0; i < ARRAY_SIZE(priv->lcds); i++) {
> + lcd = priv->lcds[i];
> + if (lcd)
> + de2_vblank_reset(lcd);
> + }
> +
> + drm_mode_config_reset(drm);
> +
> + priv->fbdev = drm_fbdev_cma_init(drm,
> + 32, /* bpp */
> + drm->mode_config.num_crtc,
> + drm->mode_config.num_connector);
> + if (IS_ERR(priv->fbdev)) {
> + ret = PTR_ERR(priv->fbdev);
> + priv->fbdev = NULL;
> + goto out3;
> + }
> +
> + drm_kms_helper_poll_init(drm);
> +
> + ret = drm_dev_register(drm, 0);
> + if (ret < 0)
> + goto out4;
> +
> + return 0;
> +
> +out4:
> + drm_fbdev_cma_fini(priv->fbdev);
> +out3:
> + component_unbind_all(dev, drm);
> +out2:
> + drm_dev_unref(drm);
> +out1:
> + kfree(priv);
> + return ret;
> +}
> +
> +static void de2_drm_unbind(struct device *dev)
> +{
> + struct drm_device *drm = dev_get_drvdata(dev);
> + struct priv *priv = drm_to_priv(drm);
> +
> + drm_dev_unregister(drm);
> +
> + drm_fbdev_cma_fini(priv->fbdev);
> + drm_kms_helper_poll_fini(drm);
> + drm_vblank_cleanup(drm);
> + drm_mode_config_cleanup(drm);
> +
> + component_unbind_all(dev, drm);
> +
> + kfree(priv);
> +}
> +
> +static const struct component_master_ops de2_drm_comp_ops = {
> + .bind = de2_drm_bind,
> + .unbind = de2_drm_unbind,
> +};
> +
> +/*
> + * drm_of_component_probe() does:
> + * - bind of the ports (lcd-controller.port)
> + * - bind of the remote nodes (hdmi, tve..)
> + */
> +static int compare_of(struct device *dev, void *data)
> +{
> + struct device_node *np = data;
> +
> + if (of_node_cmp(np->name, "port") == 0) {
> + np = of_get_parent(np);
> + of_node_put(np);
> + }
> + return dev->of_node == np;
> +}
> +
> +static int de2_drm_probe(struct platform_device *pdev)
> +{
> + int ret;
> +
> + ret = drm_of_component_probe(&pdev->dev,
> + compare_of,
> + &de2_drm_comp_ops);
> + if (ret == -EINVAL)
> + ret = -ENXIO;
> + return ret;
> +}
> +
> +static int de2_drm_remove(struct platform_device *pdev)
> +{
> + component_master_del(&pdev->dev, &de2_drm_comp_ops);
> +
> + return 0;
> +}
> +
> +static struct platform_driver de2_drm_platform_driver = {
> + .probe = de2_drm_probe,
> + .remove = de2_drm_remove,
> + .driver = {
> + .name = DRIVER_NAME,
> + .of_match_table = de2_drm_of_match,
> + },
> +};
> +
> +static int __init de2_drm_init(void)
> +{
> + int ret;
> +
> + ret = platform_driver_register(&de2_lcd_platform_driver);
> + if (ret < 0)
> + return ret;
> +
> + ret = platform_driver_register(&de2_drm_platform_driver);
> + if (ret < 0)
> + platform_driver_unregister(&de2_lcd_platform_driver);
> +
> + return ret;
> +}
> +
> +static void __exit de2_drm_fini(void)
> +{
> + platform_driver_unregister(&de2_lcd_platform_driver);
> + platform_driver_unregister(&de2_drm_platform_driver);
> +}
> +
> +module_init(de2_drm_init);
> +module_exit(de2_drm_fini);
> +
> +MODULE_AUTHOR("Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>");
> +MODULE_DESCRIPTION("Allwinner DE2 DRM Driver");
> +MODULE_LICENSE("GPL v2");
> diff --git a/drivers/gpu/drm/sun8i/de2_drv.h b/drivers/gpu/drm/sun8i/de2_drv.h
> new file mode 100644
> index 0000000..c42c30a
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/de2_drv.h
> @@ -0,0 +1,48 @@
> +#ifndef __DE2_DRM_H__
> +#define __DE2_DRM_H__
> +/*
> + * Copyright (C) 2016 Jean-Fran??ois Moine
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <drm/drmP.h>
> +#include <linux/clk.h>
> +#include <linux/reset.h>
> +
> +struct drm_fbdev_cma;
> +struct lcd;
> +
> +#define N_LCDS 2
> +
> +struct priv {
> + struct drm_device drm;
> + void __iomem *mmio;
> + struct clk *clk;
> + struct clk *gate;
> + struct reset_control *reset;
> +
> + struct mutex mutex; /* protect DE I/O access */
> + u8 soc_type;
> +#define SOC_A83T 0
> +#define SOC_H3 1
> + u8 started; /* bitmap of started mixers */
> + u8 clean; /* bitmap of clean mixers */
> +
> + struct drm_fbdev_cma *fbdev;
> +
> + struct lcd *lcds[N_LCDS]; /* CRTCs */
> +};
> +
> +#define drm_to_priv(x) container_of(x, struct priv, drm)
> +
> +/* in de2_crtc.c */
> +int de2_enable_vblank(struct drm_device *drm, unsigned int crtc);
> +void de2_disable_vblank(struct drm_device *drm, unsigned int crtc);
> +void de2_vblank_reset(struct lcd *lcd);
> +extern struct platform_driver de2_lcd_platform_driver;
> +
> +#endif /* __DE2_DRM_H__ */
> diff --git a/drivers/gpu/drm/sun8i/de2_plane.c b/drivers/gpu/drm/sun8i/de2_plane.c
> new file mode 100644
> index 0000000..2fd72dc
> --- /dev/null
> +++ b/drivers/gpu/drm/sun8i/de2_plane.c
> @@ -0,0 +1,734 @@
> +/*
> + * Allwinner DRM driver - Display Engine 2
> + *
> + * Copyright (C) 2016 Jean-Francois Moine <moinejf-GANU6spQydw@public.gmane.org>
> + * Adapted from the sun8iw6 and sun8iw7 disp2 drivers
> + * Copyright (c) 2016 Allwinnertech Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of
> + * the License, or (at your option) any later version.
> + */
> +
> +#include <linux/io.h>
> +#include <drm/drm_atomic_helper.h>
> +#include <drm/drm_crtc_helper.h>
> +#include <drm/drm_fb_cma_helper.h>
> +#include <drm/drm_gem_cma_helper.h>
> +#include <drm/drm_plane_helper.h>
> +
> +#include "de2_drv.h"
> +#include "de2_crtc.h"
> +
> +/* DE2 I/O map */
> +
> +#define DE2_MOD_REG 0x0000 /* 1 bit per LCD */
> +#define DE2_GATE_REG 0x0004
> +#define DE2_RESET_REG 0x0008
> +#define DE2_DIV_REG 0x000c /* 4 bits per LCD */
> +#define DE2_SEL_REG 0x0010
> +
> +#define DE2_MIXER0_BASE 0x00100000 /* LCD 0 */
> +#define DE2_MIXER1_BASE 0x00200000 /* LCD 1 */
> +
> +/* mixer registers (addr / mixer base) */
> +#define MIXER_GLB_REGS 0x00000 /* global control */
> +#define MIXER_BLD_REGS 0x01000 /* alpha blending */
> +#define MIXER_CHAN_REGS 0x02000 /* VI/UI overlay channels */
> +#define MIXER_CHAN_SZ 0x1000 /* size of a channel */
> +#define MIXER_VSU_REGS 0x20000 /* VSU */
> +#define MIXER_GSU1_REGS 0x30000 /* GSUs */
> +#define MIXER_GSU2_REGS 0x40000
> +#define MIXER_GSU3_REGS 0x50000
> +#define MIXER_FCE_REGS 0xa0000 /* FCE */
> +#define MIXER_BWS_REGS 0xa2000 /* BWS */
> +#define MIXER_LTI_REGS 0xa4000 /* LTI */
> +#define MIXER_PEAK_REGS 0xa6000 /* PEAK */
> +#define MIXER_ASE_REGS 0xa8000 /* ASE */
> +#define MIXER_FCC_REGS 0xaa000 /* FCC */
> +#define MIXER_DCSC_REGS 0xb0000 /* DCSC/SMBL */
> +
> +/* global control */
> +#define MIXER_GLB_CTL_REG 0x00
> +#define MIXER_GLB_CTL_rt_en BIT(0)
> +#define MIXER_GLB_CTL_finish_irq_en BIT(4)
> +#define MIXER_GLB_CTL_rtwb_port BIT(12)
> +#define MIXER_GLB_STATUS_REG 0x04
> +#define MIXER_GLB_DBUFF_REG 0x08
> +#define MIXER_GLB_SIZE_REG 0x0c
> +
> +/* alpha blending */
> +#define MIXER_BLD_FCOLOR_CTL_REG 0x00
> +#define MIXER_BLD_FCOLOR_CTL_PEN(pipe) (0x0100 << (pipe))
> +#define MIXER_BLD_ATTR_N 4 /* number of attribute blocks */
> +#define MIXER_BLD_ATTR_SIZE (4 * 4) /* size of an attribute block */
> +#define MIXER_BLD_ATTRx_FCOLOR(x) (0x04 + MIXER_BLD_ATTR_SIZE * (x))
> +#define MIXER_BLD_ATTRx_INSIZE(x) (0x08 + MIXER_BLD_ATTR_SIZE * (x))
> +#define MIXER_BLD_ATTRx_OFFSET(x) (0x0c + MIXER_BLD_ATTR_SIZE * (x))
> +#define MIXER_BLD_ROUTE_REG 0x80
> +#define MIXER_BLD_ROUTE(chan, pipe) ((chan) << ((pipe) * 4))
> +#define MIXER_BLD_PREMULTIPLY_REG 0x84
> +#define MIXER_BLD_BKCOLOR_REG 0x88
> +#define MIXER_BLD_OUTPUT_SIZE_REG 0x8c
> +#define MIXER_BLD_MODEx_REG(x) (0x90 + 4 * (x)) /* x = 0..3 */
> +#define MIXER_BLD_MODE_SRCOVER 0x03010301
> +#define MIXER_BLD_OUT_CTL_REG 0xfc
> +
> +/* VI channel (channel 0) */
> +#define VI_CFG_N 4 /* number of layers */
> +#define VI_CFG_SIZE 0x30 /* size of a layer */
> +#define VI_CFGx_ATTR(l) (0x00 + VI_CFG_SIZE * (l))
> +#define VI_CFG_ATTR_en BIT(0)
> +#define VI_CFG_ATTR_fcolor_en BIT(4)
> +#define VI_CFG_ATTR_fmt_SHIFT 8
> +#define VI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
> +#define VI_CFG_ATTR_ui_sel BIT(15)
> +#define VI_CFG_ATTR_top_down BIT(23)
> +#define VI_CFGx_SIZE(l) (0x04 + VI_CFG_SIZE * (l))
> +#define VI_CFGx_COORD(l) (0x08 + VI_CFG_SIZE * (l))
> +#define VI_N_PLANES 3
> +#define VI_CFGx_PITCHy(l, p) (0x0c + VI_CFG_SIZE * (l) + 4 * (p))
> +#define VI_CFGx_TOP_LADDRy(l, p) (0x18 + VI_CFG_SIZE * (l) + 4 * (p))
> +#define VI_CFGx_BOT_LADDRy(l, p) (0x24 + VI_CFG_SIZE * (l) + 4 * (p))
> +#define VI_FCOLORx(l) (0xc0 + 4 * (l))
> +#define VI_TOP_HADDRx(p) (0xd0 + 4 * (p))
> +#define VI_BOT_HADDRx(p) (0xdc + 4 * (p))
> +#define VI_OVL_SIZEx(n) (0xe8 + 4 * (n))
> +#define VI_HORI_DSx(n) (0xf0 + 4 * (n))
> +#define VI_VERT_DSx(n) (0xf8 + 4 * (n))
> +#define VI_SIZE 0x100
> +
> +/* UI channel (channels 1..3) */
> +#define UI_CFG_N 4 /* number of layers */
> +#define UI_CFG_SIZE (8 * 4) /* size of a layer */
> +#define UI_CFGx_ATTR(l) (0x00 + UI_CFG_SIZE * (l))
> +#define UI_CFG_ATTR_en BIT(0)
> +#define UI_CFG_ATTR_alpmod_SHIFT 1
> +#define UI_CFG_ATTR_alpmod_MASK GENMASK(2, 1)
> +#define UI_CFG_ATTR_fcolor_en BIT(4)
> +#define UI_CFG_ATTR_fmt_SHIFT 8
> +#define UI_CFG_ATTR_fmt_MASK GENMASK(12, 8)
> +#define UI_CFG_ATTR_top_down BIT(23)
> +#define UI_CFG_ATTR_alpha_SHIFT 24
> +#define UI_CFG_ATTR_alpha_MASK GENMASK(31, 24)
> +#define UI_CFGx_SIZE(l) (0x04 + UI_CFG_SIZE * (l))
> +#define UI_CFGx_COORD(l) (0x08 + UI_CFG_SIZE * (l))
> +#define UI_CFGx_PITCH(l) (0x0c + UI_CFG_SIZE * (l))
> +#define UI_CFGx_TOP_LADDR(l) (0x10 + UI_CFG_SIZE * (l))
> +#define UI_CFGx_BOT_LADDR(l) (0x14 + UI_CFG_SIZE * (l))
> +#define UI_CFGx_FCOLOR(l) (0x18 + UI_CFG_SIZE * (l))
> +#define UI_TOP_HADDR 0x80
> +#define UI_BOT_HADDR 0x84
> +#define UI_OVL_SIZE 0x88
> +#define UI_SIZE 0x8c
> +
> +/* coordinates and sizes */
> +#define XY(x, y) (((y) << 16) | (x))
> +#define WH(w, h) ((((h) - 1) << 16) | ((w) - 1))
> +
> +/* UI video formats */
> +#define DE2_FORMAT_ARGB_8888 0
> +#define DE2_FORMAT_BGRA_8888 3
> +#define DE2_FORMAT_XRGB_8888 4
> +#define DE2_FORMAT_RGB_888 8
> +#define DE2_FORMAT_BGR_888 9
> +
> +/* VI video formats */
> +#define DE2_FORMAT_YUV422_I_YVYU 1 /* YVYU */
> +#define DE2_FORMAT_YUV422_I_UYVY 2 /* UYVY */
> +#define DE2_FORMAT_YUV422_I_YUYV 3 /* YUYV */
> +#define DE2_FORMAT_YUV422_P 6 /* YYYY UU VV planar */
> +#define DE2_FORMAT_YUV420_P 10 /* YYYY U V planar */
> +
> +/* plane formats */
> +static const uint32_t ui_formats[] = {
> + DRM_FORMAT_ARGB8888,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> +};
> +
> +static const uint32_t vi_formats[] = {
> + DRM_FORMAT_XRGB8888,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_YVYU,
> + DRM_FORMAT_YUV422,
> + DRM_FORMAT_YUV420,
> + DRM_FORMAT_UYVY,
> + DRM_FORMAT_BGRA8888,
> + DRM_FORMAT_RGB888,
> + DRM_FORMAT_BGR888,
> +};
> +
> +/*
> + * plane table
> + *
> + * The chosen channel/layer assignment of the planes respects
> + * the following constraints:
> + * - the cursor must be in a channel higher than the primary channel
> + * - there are 4 channels in the LCD 0 and only 2 channels in the LCD 1
> + */
> +static const struct {
> + u8 chan;
> + u8 layer;
> + u8 pipe;
> + u8 type; /* plane type */
> + const uint32_t *formats;
> + u8 n_formats;
> +} plane_tb[] = {
> + [DE2_PRIMARY_PLANE] = { /* primary plane: channel 0 (VI) */
> + 0, 0, 0,
> + DRM_PLANE_TYPE_PRIMARY,
> + ui_formats, ARRAY_SIZE(ui_formats),
> + },
> + [DE2_CURSOR_PLANE] = { /* cursor: channel 1 (UI) */
> + 1, 0, 1,
> + DRM_PLANE_TYPE_CURSOR,
> + ui_formats, ARRAY_SIZE(ui_formats),
> + },
> + {
> + 0, 1, 0, /* 1st overlay: channel 0, layer 1 */
> + DRM_PLANE_TYPE_OVERLAY,
> + vi_formats, ARRAY_SIZE(vi_formats),
> + },
> + {
> + 0, 2, 0, /* 2nd overlay: channel 0, layer 2 */
> + DRM_PLANE_TYPE_OVERLAY,
> + vi_formats, ARRAY_SIZE(vi_formats),
> + },
> + {
> + 0, 3, 0, /* 3rd overlay: channel 0, layer 3 */
> + DRM_PLANE_TYPE_OVERLAY,
> + vi_formats, ARRAY_SIZE(vi_formats),
> + },
> +};
> +
> +static inline void andl_relaxed(void __iomem *addr, u32 val)
> +{
> + writel_relaxed(readl_relaxed(addr) & val, addr);
> +}
> +
> +static inline void orl_relaxed(void __iomem *addr, u32 val)
> +{
> + writel_relaxed(readl_relaxed(addr) | val, addr);
> +}
> +
> +/* alert the DE processor about changes in a mixer configuration */
> +static void de2_mixer_select(struct priv *priv,
> + int mixer,
> + void __iomem *mixer_io)
> +{
> + /* select the mixer */
> + andl_relaxed(priv->mmio + DE2_SEL_REG, ~1);
> +
> + /* double register switch */
> + writel_relaxed(1, mixer_io + MIXER_GLB_REGS + MIXER_GLB_DBUFF_REG);
> +}
> +
> +/*
> + * cleanup a mixer
> + *
> + * This is needed only once after power on.
> + */
> +static void de2_mixer_cleanup(struct priv *priv, int mixer,
> + u32 size)
> +{
> + void __iomem *mixer_io = priv->mmio;
> + void __iomem *chan_io;
> + u32 data;
> + unsigned int i;
> +
> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
> + chan_io = mixer_io + MIXER_CHAN_REGS;
> +
> + andl_relaxed(priv->mmio + DE2_SEL_REG, ~1);
> + writel_relaxed(1, mixer_io + MIXER_GLB_REGS + MIXER_GLB_DBUFF_REG);
> +
> + writel_relaxed(MIXER_GLB_CTL_rt_en,
> + mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_STATUS_REG);
> +
> + writel_relaxed(size, mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
> +
> + /*
> + * clear the VI/UI channels
> + * LCD0: 1 VI and 3 UIs
> + * LCD1: 1 VI and 1 UI
> + */
> + memset_io(chan_io, 0, VI_SIZE);
> + memset_io(chan_io + MIXER_CHAN_SZ, 0, UI_SIZE);
> + if (mixer == 0) {
> + memset_io(chan_io + MIXER_CHAN_SZ * 2, 0, UI_SIZE);
> + memset_io(chan_io + MIXER_CHAN_SZ * 3, 0, UI_SIZE);
> + }
> +
> + /* alpha blending */
> + writel_relaxed(0x00000001 | /* fcolor for primary */
> + MIXER_BLD_FCOLOR_CTL_PEN(0),
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_FCOLOR_CTL_REG);
> + for (i = 0; i < MIXER_BLD_ATTR_N; i++) {
> + writel_relaxed(0xff000000,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_FCOLOR(i));
> + writel_relaxed(size,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_INSIZE(i));
> + writel_relaxed(0,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_ATTRx_OFFSET(i));
> + }
> + writel_relaxed(0, mixer_io + MIXER_BLD_REGS + MIXER_BLD_OUT_CTL_REG);
> +
> + /* prepare the pipe route for the planes */
> + data = 0;
> + for (i = 0; i < DE2_N_PLANES; i++)
> + data |= MIXER_BLD_ROUTE(plane_tb[i].chan, plane_tb[i].pipe);
> + writel_relaxed(data, mixer_io + MIXER_BLD_REGS + MIXER_BLD_ROUTE_REG);
> +
> + writel_relaxed(0, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_PREMULTIPLY_REG);
> + writel_relaxed(0xff000000, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_BKCOLOR_REG);
> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_OUTPUT_SIZE_REG);
> + writel_relaxed(MIXER_BLD_MODE_SRCOVER,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_MODEx_REG(0));
> + writel_relaxed(MIXER_BLD_MODE_SRCOVER,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_MODEx_REG(1));
> +
> + /* disable the enhancements */
> + writel_relaxed(0, mixer_io + MIXER_VSU_REGS);
> + writel_relaxed(0, mixer_io + MIXER_GSU1_REGS);
> + writel_relaxed(0, mixer_io + MIXER_GSU2_REGS);
> + writel_relaxed(0, mixer_io + MIXER_GSU3_REGS);
> + writel_relaxed(0, mixer_io + MIXER_FCE_REGS);
> + writel_relaxed(0, mixer_io + MIXER_BWS_REGS);
> + writel_relaxed(0, mixer_io + MIXER_LTI_REGS);
> + writel_relaxed(0, mixer_io + MIXER_PEAK_REGS);
> + writel_relaxed(0, mixer_io + MIXER_ASE_REGS);
> + writel_relaxed(0, mixer_io + MIXER_FCC_REGS);
> + writel_relaxed(0, mixer_io + MIXER_DCSC_REGS);
> +}
> +
> +/* enable a mixer */
> +static void de2_mixer_enable(struct lcd *lcd)
> +{
> + struct priv *priv = lcd->priv;
> + void __iomem *mixer_io = priv->mmio;
> + struct drm_display_mode *mode = &lcd->crtc.mode;
> + u32 size = WH(mode->hdisplay, mode->vdisplay);
> + u32 data;
> + int mixer = lcd->mixer;
> + int i;
> +
> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
> +
> + /* if not done yet, start the DE processor */
> + if (!priv->started) {
> + reset_control_deassert(priv->reset);
> + clk_prepare_enable(priv->gate);
> + clk_prepare_enable(priv->clk);
> + }
> + priv->started |= 1 << mixer;
> +
> + /* set the A83T clock divider (500 / 2) = 250MHz */
> + if (priv->soc_type == SOC_A83T)
> + writel_relaxed(0x00000011, /* div = 2 for both LCDs */
> + priv->mmio + DE2_DIV_REG);
> +
> + /* deassert the mixer and enable its clock */
> + orl_relaxed(priv->mmio + DE2_RESET_REG, mixer == 0 ? 1 : 4);
> + data = 1 << mixer; /* 1 bit / lcd */
> + orl_relaxed(priv->mmio + DE2_GATE_REG, data);
> + orl_relaxed(priv->mmio + DE2_MOD_REG, data);
> +
> + /* if not done yet, cleanup and enable */
> + if (!(priv->clean & (1 << mixer))) {
> + priv->clean |= 1 << mixer;
> + de2_mixer_cleanup(priv, mixer, size);
> + return;
> + }
> +
> + /* enable */
> + de2_mixer_select(priv, mixer, mixer_io);
> +
> + writel_relaxed(MIXER_GLB_CTL_rt_en,
> + mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_STATUS_REG);
> +
> + /* set the size of the frame buffer */
> + writel_relaxed(size, mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
> + for (i = 0; i < MIXER_BLD_ATTR_N; i++)
> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_ATTRx_INSIZE(i));
> + writel_relaxed(size, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_OUTPUT_SIZE_REG);
> +
> + writel_relaxed(mode->flags & DRM_MODE_FLAG_INTERLACE ? 2 : 0,
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_OUT_CTL_REG);
> +}
> +
> +/* enable a LCD (DE mixer) */
> +void de2_de_enable(struct lcd *lcd)
> +{
> + mutex_lock(&lcd->priv->mutex);
> +
> + de2_mixer_enable(lcd);
> +
> + mutex_unlock(&lcd->priv->mutex);
> +}
> +
> +/* disable a LCD (DE mixer) */
> +void de2_de_disable(struct lcd *lcd)
> +{
> + struct priv *priv = lcd->priv;
> + void __iomem *mixer_io = priv->mmio;
> + int mixer = lcd->mixer;
> + u32 data;
> +
> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
> +
> + mutex_lock(&priv->mutex);
> +
> + de2_mixer_select(priv, mixer, mixer_io);
> +
> + writel_relaxed(0, mixer_io + MIXER_GLB_REGS + MIXER_GLB_CTL_REG);
> +
> + data = ~(1 << mixer);
> + andl_relaxed(priv->mmio + DE2_MOD_REG, data);
> + andl_relaxed(priv->mmio + DE2_GATE_REG, data);
> + andl_relaxed(priv->mmio + DE2_RESET_REG, data);
> +
> + mutex_unlock(&priv->mutex);
> +
> + /* if all mixers are disabled, stop the DE */
> + priv->started &= ~(1 << mixer);
> + if (!priv->started) {
> + clk_disable_unprepare(priv->clk);
> + clk_disable_unprepare(priv->gate);
> + reset_control_assert(priv->reset);
> + }
> +}
> +
> +static void de2_vi_update(void __iomem *chan_io,
> + struct drm_gem_cma_object *gem,
> + int layer,
> + unsigned int fmt,
> + u32 ui_sel,
> + u32 size,
> + u32 coord,
> + struct drm_framebuffer *fb,
> + u32 screen_size)
> +{
> + int i;
> +
> + writel_relaxed(VI_CFG_ATTR_en |
> + (fmt << VI_CFG_ATTR_fmt_SHIFT) |
> + ui_sel,
> + chan_io + VI_CFGx_ATTR(layer));
> + writel_relaxed(size, chan_io + VI_CFGx_SIZE(layer));
> + writel_relaxed(coord, chan_io + VI_CFGx_COORD(layer));
> + for (i = 0; i < VI_N_PLANES; i++) {
> + writel_relaxed(fb->pitches[i] ? fb->pitches[i] :
> + fb->pitches[0],
> + chan_io + VI_CFGx_PITCHy(layer, i));
> + writel_relaxed(gem->paddr + fb->offsets[i],
> + chan_io + VI_CFGx_TOP_LADDRy(layer, i));
> + }
> + writel_relaxed(0xff000000, chan_io + VI_FCOLORx(layer));
> + if (layer == 0) {
> + writel_relaxed(screen_size,
> + chan_io + VI_OVL_SIZEx(0));
> + }
> +}
> +
> +static void de2_ui_update(void __iomem *chan_io,
> + struct drm_gem_cma_object *gem,
> + int layer,
> + unsigned int fmt,
> + u32 alpha_glob,
> + u32 size,
> + u32 coord,
> + struct drm_framebuffer *fb,
> + u32 screen_size)
> +{
> + writel_relaxed(UI_CFG_ATTR_en |
> + (fmt << UI_CFG_ATTR_fmt_SHIFT) |
> + alpha_glob,
> + chan_io + UI_CFGx_ATTR(layer));
> + writel_relaxed(size, chan_io + UI_CFGx_SIZE(layer));
> + writel_relaxed(coord, chan_io + UI_CFGx_COORD(layer));
> + writel_relaxed(fb->pitches[0], chan_io + UI_CFGx_PITCH(layer));
> + writel_relaxed(gem->paddr + fb->offsets[0],
> + chan_io + UI_CFGx_TOP_LADDR(layer));
> + if (layer == 0)
> + writel_relaxed(screen_size, chan_io + UI_OVL_SIZE);
> +}
> +
> +static void de2_plane_update(struct priv *priv, struct lcd *lcd,
> + int plane_num,
> + struct drm_plane_state *state,
> + struct drm_plane_state *old_state)
> +{
> + void __iomem *mixer_io = priv->mmio;
> + void __iomem *chan_io;
> + struct drm_framebuffer *fb = state->fb;
> + struct drm_gem_cma_object *gem;
> + u32 size = WH(state->crtc_w, state->crtc_h);
> + u32 coord, screen_size;
> + u32 fcolor;
> + u32 ui_sel, alpha_glob;
> + int mixer = lcd->mixer;
> + int chan, layer, x, y;
> + unsigned int fmt;
> +
> + chan = plane_tb[plane_num].chan;
> + layer = plane_tb[plane_num].layer;
> +
> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
> + chan_io = mixer_io + MIXER_CHAN_REGS + MIXER_CHAN_SZ * chan;
> +
> + x = state->crtc_x >= 0 ? state->crtc_x : 0;
> + y = state->crtc_y >= 0 ? state->crtc_y : 0;
> + coord = XY(x, y);
> +
> + /* if plane update was delayed, force a full update */
> + if (priv->lcds[drm_crtc_index(&lcd->crtc)]->delayed &
> + (1 << plane_num)) {
> + priv->lcds[drm_crtc_index(&lcd->crtc)]->delayed &=
> + ~(1 << plane_num);
> +
> + /* handle plane move */
> + } else if (fb == old_state->fb) {
> + de2_mixer_select(priv, mixer, mixer_io);
> + if (chan == 0)
> + writel_relaxed(coord, chan_io + VI_CFGx_COORD(layer));
> + else
> + writel_relaxed(coord, chan_io + UI_CFGx_COORD(layer));
> + return;
> + }
> +
> + gem = drm_fb_cma_get_gem_obj(fb, 0);
> +
> + ui_sel = alpha_glob = 0;
> +
> + switch (fb->pixel_format) {
> + case DRM_FORMAT_ARGB8888:
> + fmt = DE2_FORMAT_ARGB_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_BGRA8888:
> + fmt = DE2_FORMAT_BGRA_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_XRGB8888:
> + fmt = DE2_FORMAT_XRGB_8888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + alpha_glob = (1 << UI_CFG_ATTR_alpmod_SHIFT) |
> + (0xff << UI_CFG_ATTR_alpha_SHIFT);
> + break;
> + case DRM_FORMAT_RGB888:
> + fmt = DE2_FORMAT_RGB_888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_BGR888:
> + fmt = DE2_FORMAT_BGR_888;
> + ui_sel = VI_CFG_ATTR_ui_sel;
> + break;
> + case DRM_FORMAT_YUYV:
> + fmt = DE2_FORMAT_YUV422_I_YUYV;
> + break;
> + case DRM_FORMAT_YVYU:
> + fmt = DE2_FORMAT_YUV422_I_YVYU;
> + break;
> + case DRM_FORMAT_YUV422:
> + fmt = DE2_FORMAT_YUV422_P;
> + break;
> + case DRM_FORMAT_YUV420:
> + fmt = DE2_FORMAT_YUV420_P;
> + break;
> + case DRM_FORMAT_UYVY:
> + fmt = DE2_FORMAT_YUV422_I_UYVY;
> + break;
> + default:
> + pr_err("de2_plane_update: format %.4s not yet treated\n",
> + (char *) &fb->pixel_format);
> + return;
> + }
> +
> + /* the overlay size is the one of the primary plane */
> + screen_size = plane_num == DE2_PRIMARY_PLANE ?
> + size :
> + readl_relaxed(mixer_io + MIXER_GLB_REGS + MIXER_GLB_SIZE_REG);
> +
> + /* prepare pipe enable */
> + fcolor = readl_relaxed(mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_FCOLOR_CTL_REG);
> + fcolor |= MIXER_BLD_FCOLOR_CTL_PEN(plane_tb[plane_num].pipe);
> +
> + de2_mixer_select(priv, mixer, mixer_io);
> +
> + if (chan == 0) /* VI channel */
> + de2_vi_update(chan_io, gem, layer, fmt, ui_sel, size, coord,
> + fb, screen_size);
> + else /* UI channel */
> + de2_ui_update(chan_io, gem, layer, fmt, alpha_glob, size, coord,
> + fb, screen_size);
> + writel_relaxed(fcolor, mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_FCOLOR_CTL_REG);
> +}
> +
> +static int vi_nb_layers(void __iomem *chan_io)
> +{
> + int layer, n = 0;
> +
> + for (layer = 0; layer < 4; layer++) {
> + if (readl_relaxed(chan_io + VI_CFGx_ATTR(layer)) != 0)
> + n++;
> + }
> +
> + return n;
> +}
> +
> +static int ui_nb_layers(void __iomem *chan_io)
> +{
> + int layer, n = 0;
> +
> + for (layer = 0; layer < 4; layer++) {
> + if (readl_relaxed(chan_io + UI_CFGx_ATTR(layer)) != 0)
> + n++;
> + }
> +
> + return n;
> +}
> +
> +static void de2_plane_disable(struct priv *priv,
> + int mixer, int plane_num)
> +{
> + void __iomem *mixer_io = priv->mmio;
> + void __iomem *chan_io;
> + u32 fcolor;
> + int chan, layer, n;
> +
> + chan = plane_tb[plane_num].chan;
> + layer = plane_tb[plane_num].layer;
> +
> + mixer_io += (mixer == 0) ? DE2_MIXER0_BASE : DE2_MIXER1_BASE;
> + chan_io = mixer_io + MIXER_CHAN_REGS + MIXER_CHAN_SZ * chan;
> +
> + if (chan == 0)
> + n = vi_nb_layers(chan_io);
> + else
> + n = ui_nb_layers(chan_io);
> +
> + fcolor = readl_relaxed(mixer_io + MIXER_BLD_REGS +
> + MIXER_BLD_FCOLOR_CTL_REG);
> +
> + de2_mixer_select(priv, mixer, mixer_io);
> +
> + if (chan == 0)
> + writel_relaxed(0, chan_io + VI_CFGx_ATTR(layer));
> + else
> + writel_relaxed(0, chan_io + UI_CFGx_ATTR(layer));
> +
> + /* disable the pipe if no more active layer */
> + if (n <= 1)
> + writel_relaxed(fcolor &
> + ~MIXER_BLD_FCOLOR_CTL_PEN(plane_tb[plane_num].pipe),
> + mixer_io + MIXER_BLD_REGS + MIXER_BLD_FCOLOR_CTL_REG);
> +}
> +
> +static void de2_drm_plane_update(struct drm_plane *plane,
> + struct drm_plane_state *old_state)
> +{
> + struct drm_plane_state *state = plane->state;
> + struct drm_crtc *crtc = state->crtc;
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + struct priv *priv = lcd->priv;
> + int plane_num = plane - lcd->planes;
> +
> + /* if the crtc is disabled, mark update delayed */
> + if (!(priv->started & (1 << lcd->mixer))) {
> + lcd->delayed |= 1 << plane_num;
> + return; /* mixer disabled */
> + }
> +
> + mutex_lock(&priv->mutex);
> +
> + de2_plane_update(priv, lcd, plane_num, state, old_state);
> +
> + mutex_unlock(&priv->mutex);
> +}
> +
> +static void de2_drm_plane_disable(struct drm_plane *plane,
> + struct drm_plane_state *old_state)
> +{
> + struct drm_crtc *crtc = old_state->crtc;
> + struct lcd *lcd = crtc_to_lcd(crtc);
> + struct priv *priv = lcd->priv;
> + int plane_num = plane - lcd->planes;
> +
> + if (!(priv->started & (1 << lcd->mixer)))
> + return; /* mixer disabled */
> +
> + mutex_lock(&priv->mutex);
> +
> + de2_plane_disable(lcd->priv, lcd->mixer, plane_num);
> +
> + mutex_unlock(&priv->mutex);
> +}
> +
> +static const struct drm_plane_helper_funcs plane_helper_funcs = {
> + .atomic_update = de2_drm_plane_update,
> + .atomic_disable = de2_drm_plane_disable,
> +};
> +
> +static const struct drm_plane_funcs plane_funcs = {
> + .update_plane = drm_atomic_helper_update_plane,
> + .disable_plane = drm_atomic_helper_disable_plane,
> + .destroy = drm_plane_cleanup,
> + .reset = drm_atomic_helper_plane_reset,
> + .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
> + .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
> +};
> +
> +static int de2_one_plane_init(struct drm_device *drm,
> + struct drm_plane *plane,
> + int possible_crtcs,
> + int plane_num)
> +{
> + int ret;
> +
> + ret = drm_universal_plane_init(drm, plane, possible_crtcs,
> + &plane_funcs,
> + plane_tb[plane_num].formats,
> + plane_tb[plane_num].n_formats,
> + plane_tb[plane_num].type, NULL);
> + if (ret >= 0)
> + drm_plane_helper_add(plane, &plane_helper_funcs);
> +
> + return ret;
> +}
> +
> +/* initialize the planes */
> +int de2_plane_init(struct drm_device *drm, struct lcd *lcd)
> +{
> + int i, n, ret, possible_crtcs = 1 << drm_crtc_index(&lcd->crtc);
> +
> + n = ARRAY_SIZE(plane_tb);
> + if (n != DE2_N_PLANES) {
> + dev_err(lcd->dev, "Bug: incorrect number of planes %d != "
> + __stringify(DE2_N_PLANES) "\n", n);
> + return -EINVAL;
> + }
> +
> + for (i = 0; i < n; i++) {
> + ret = de2_one_plane_init(drm, &lcd->planes[i],
> + possible_crtcs, i);
> + if (ret < 0) {
> + dev_err(lcd->dev, "plane init failed %d\n", ret);
> + break;
> + }
> + }
> +
> + return ret;
> +}
> --
> 2.10.2
>
> _______________________________________________
> dri-devel mailing list
> dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
^ permalink raw reply
* [PATCH v3 13/13] clocksource/drivers/rockchip_timer: Prevent ftrace recursion
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Currently rockchip_timer can be used as a scheduler clock. We properly
marked rk_timer_sched_clock_read() as notrace but we then call another
function rk_timer_counter_read() that _wasn't_ notrace.
Having a traceable function in the sched_clock() path leads to a recursion
within ftrace and a kernel crash.
Fix this by adding an extra notrace function to keep other users of
rk_timer_counter_read() traceable.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 1af80a0..a127822 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -87,7 +87,7 @@ static void rk_timer_update_counter(u64 cycles, struct rk_timer *timer)
writel_relaxed(upper, timer->base + TIMER_LOAD_COUNT1);
}
-static u64 rk_timer_counter_read(struct rk_timer *timer)
+static u64 notrace _rk_timer_counter_read(struct rk_timer *timer)
{
u64 counter;
u32 lower;
@@ -106,6 +106,11 @@ static u64 rk_timer_counter_read(struct rk_timer *timer)
return counter;
}
+static u64 rk_timer_counter_read(struct rk_timer *timer)
+{
+ return _rk_timer_counter_read(timer);
+}
+
static void rk_timer_interrupt_clear(struct rk_timer *timer)
{
writel_relaxed(1, timer->base + TIMER_INT_STATUS);
@@ -168,7 +173,7 @@ static u64 notrace rk_timer_sched_clock_read(void)
{
struct rk_clocksource *_cs = &cs_timer;
- return ~rk_timer_counter_read(&_cs->timer);
+ return ~_rk_timer_counter_read(&_cs->timer);
}
static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
--
1.7.9.5
--
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* [PATCH v3 12/13] clocksource/drivers/rockchip_timer: implement clocksource timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The clock supplying the arm-global-timer on the rk3188 is coming from the
the cpu clock itself and thus changes its rate everytime cpufreq adjusts
the cpu frequency making this timer unsuitable as a stable clocksource.
The rk3188, rk3288 and following socs share a separate timer block already
handled by the rockchip-timer driver. Therefore adapt this driver to also
be able to act as clocksource on rk3188.
In order to test clocksource you can run following commands and check
how much time it take in real. On rk3188 it take about ~45 seconds.
Such error cannot be fixed using NTP. Haven't test clocksource
on rk3288 and onwards. Guess they can also have unstable clocksource.
cpufreq-set -f 1.6GHZ
date; sleep 60; date
In order to use the patch you need to declare two timers in the dts
file. The first timer will be initialized as clockevent provider
and the second one as clocksource. The clockevent must be from
alive subsystem as it used as backup for the local timers at sleep
time.
In order to resolve ambiguity between timers in the device tree,
it is possible to correctly number the timers using "aliases" node.
The patch does not break compatibility with older device tree files.
The older device tree files contain only one timer. The timer
will be initialized as clockevent, as expected.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 101 ++++++++++++++++++++++++++++------
1 file changed, 85 insertions(+), 16 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 6224aa9..1af80a0 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -11,6 +11,7 @@
#include <linux/clockchips.h>
#include <linux/init.h>
#include <linux/interrupt.h>
+#include <linux/sched_clock.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
@@ -42,7 +43,19 @@ struct rk_clock_event_device {
struct rk_timer timer;
};
+struct rk_clocksource {
+ struct clocksource cs;
+ struct rk_timer timer;
+};
+
+enum {
+ ROCKCHIP_CLKSRC_CLOCKEVENT = 0,
+ ROCKCHIP_CLKSRC_CLOCKSOURCE = 1,
+};
+
static struct rk_clock_event_device bc_timer;
+static struct rk_clocksource cs_timer;
+static int rk_next_clksrc = ROCKCHIP_CLKSRC_CLOCKEVENT;
static inline struct rk_clock_event_device*
rk_clock_event_device(struct clock_event_device *ce)
@@ -143,13 +156,46 @@ static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
return IRQ_HANDLED;
}
+static cycle_t rk_timer_clocksource_read(struct clocksource *cs)
+{
+ struct rk_clocksource *_cs =
+ container_of(cs, struct rk_clocksource, cs);
+
+ return ~rk_timer_counter_read(&_cs->timer);
+}
+
+static u64 notrace rk_timer_sched_clock_read(void)
+{
+ struct rk_clocksource *_cs = &cs_timer;
+
+ return ~rk_timer_counter_read(&_cs->timer);
+}
+
static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
{
- struct clock_event_device *ce = &bc_timer.ce;
- struct rk_timer *timer = &bc_timer.timer;
+ struct clock_event_device *ce = NULL;
+ struct clocksource *cs = NULL;
+ struct rk_timer *timer = NULL;
struct clk *timer_clk;
struct clk *pclk;
int ret = -EINVAL, irq;
+ int clksrc;
+
+ clksrc = rk_next_clksrc;
+ rk_next_clksrc++;
+
+ switch (clksrc) {
+ case ROCKCHIP_CLKSRC_CLOCKEVENT:
+ ce = &bc_timer.ce;
+ timer = &bc_timer.timer;
+ break;
+ case ROCKCHIP_CLKSRC_CLOCKSOURCE:
+ cs = &cs_timer.cs;
+ timer = &cs_timer.timer;
+ break;
+ default:
+ return -ENODEV;
+ }
timer->base = of_iomap(np, 0);
if (!timer->base) {
@@ -193,26 +239,49 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
goto out_irq;
}
- ce->name = TIMER_NAME;
- ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
- CLOCK_EVT_FEAT_DYNIRQ;
- ce->set_next_event = rk_timer_set_next_event;
- ce->set_state_shutdown = rk_timer_shutdown;
- ce->set_state_periodic = rk_timer_set_periodic;
- ce->irq = irq;
- ce->cpumask = cpu_possible_mask;
- ce->rating = 250;
+ if (ce) {
+ ce->name = TIMER_NAME;
+ ce->features = CLOCK_EVT_FEAT_PERIODIC |
+ CLOCK_EVT_FEAT_ONESHOT |
+ CLOCK_EVT_FEAT_DYNIRQ;
+ ce->set_next_event = rk_timer_set_next_event;
+ ce->set_state_shutdown = rk_timer_shutdown;
+ ce->set_state_periodic = rk_timer_set_periodic;
+ ce->irq = irq;
+ ce->cpumask = cpu_possible_mask;
+ ce->rating = 250;
+ }
+
+ if (cs) {
+ cs->name = TIMER_NAME;
+ cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
+ cs->mask = CLOCKSOURCE_MASK(64);
+ cs->read = rk_timer_clocksource_read;
+ cs->rating = 250;
+ }
rk_timer_interrupt_clear(timer);
rk_timer_disable(timer);
- ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
- if (ret) {
- pr_err("Failed to initialize '%s': %d\n", TIMER_NAME, ret);
- goto out_irq;
+ if (ce) {
+ ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER,
+ TIMER_NAME, ce);
+ if (ret) {
+ pr_err("Failed to initialize '%s': %d\n",
+ TIMER_NAME, ret);
+ goto out_irq;
+ }
+
+ clockevents_config_and_register(ce, timer->freq, 1, UINT_MAX);
}
- clockevents_config_and_register(ce, timer->freq, 1, UINT_MAX);
+ if (cs) {
+ rk_timer_update_counter(U64_MAX, timer);
+ rk_timer_enable(timer, 0);
+ clocksource_register_hz(cs, timer->freq);
+ sched_clock_register(rk_timer_sched_clock_read, 64,
+ timer->freq);
+ }
return 0;
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 11/13] clocksource/drivers/rockchip_timer: implement reading 64bit value from timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index c2b0454..6224aa9 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -19,6 +19,8 @@
#define TIMER_LOAD_COUNT0 0x00
#define TIMER_LOAD_COUNT1 0x04
+#define TIMER_CURRENT_VALUE0 0x08
+#define TIMER_CURRENT_VALUE1 0x0C
#define TIMER_CONTROL_REG3288 0x10
#define TIMER_CONTROL_REG3399 0x1c
#define TIMER_INT_STATUS 0x18
@@ -72,6 +74,25 @@ static void rk_timer_update_counter(u64 cycles, struct rk_timer *timer)
writel_relaxed(upper, timer->base + TIMER_LOAD_COUNT1);
}
+static u64 rk_timer_counter_read(struct rk_timer *timer)
+{
+ u64 counter;
+ u32 lower;
+ u32 upper, old_upper;
+
+ upper = readl_relaxed(timer->base + TIMER_CURRENT_VALUE1);
+ do {
+ old_upper = upper;
+ lower = readl_relaxed(timer->base + TIMER_CURRENT_VALUE0);
+ upper = readl_relaxed(timer->base + TIMER_CURRENT_VALUE1);
+ } while (upper != old_upper);
+
+ counter = upper;
+ counter <<= 32;
+ counter |= lower;
+ return counter;
+}
+
static void rk_timer_interrupt_clear(struct rk_timer *timer)
{
writel_relaxed(1, timer->base + TIMER_INT_STATUS);
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 10/13] clocksource/drivers/rockchip_timer: implement loading 64bit value into timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 10 ++++++----
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 61c3bb1..c2b0454 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -63,11 +63,13 @@ static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
}
-static void rk_timer_update_counter(unsigned long cycles,
- struct rk_timer *timer)
+static void rk_timer_update_counter(u64 cycles, struct rk_timer *timer)
{
- writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
- writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
+ u32 lower = cycles & 0xFFFFFFFF;
+ u32 upper = (cycles >> 32) & 0xFFFFFFFF;
+
+ writel_relaxed(lower, timer->base + TIMER_LOAD_COUNT0);
+ writel_relaxed(upper, timer->base + TIMER_LOAD_COUNT1);
}
static void rk_timer_interrupt_clear(struct rk_timer *timer)
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 09/13] clocksource/drivers/rockchip_timer: move TIMER_INT_UNMASK out of rk_timer_enable()
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
This allow to enable timer without enabling interrupts from it.
As that mode will be used in clocksource implementation.
This is refactoring step without functional changes.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index a17dc61..61c3bb1 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -60,8 +60,7 @@ static inline void rk_timer_disable(struct rk_timer *timer)
static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
{
- writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
- timer->ctrl);
+ writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
}
static void rk_timer_update_counter(unsigned long cycles,
@@ -83,7 +82,8 @@ static inline int rk_timer_set_next_event(unsigned long cycles,
rk_timer_disable(timer);
rk_timer_update_counter(cycles, timer);
- rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT);
+ rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
+ TIMER_INT_UNMASK);
return 0;
}
@@ -101,7 +101,7 @@ static int rk_timer_set_periodic(struct clock_event_device *ce)
rk_timer_disable(timer);
rk_timer_update_counter(timer->freq / HZ - 1, timer);
- rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING);
+ rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
return 0;
}
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 08/13] clocksource/drivers/rockchip_timer: drop unused rk_base() and rk_ctrl()
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Use of functions has been ceased by previous commit.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 10 ----------
1 file changed, 10 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index aa9ccd1..a17dc61 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -53,16 +53,6 @@ static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
return &rk_clock_event_device(ce)->timer;
}
-static inline void __iomem *rk_base(struct clock_event_device *ce)
-{
- return rk_timer(ce)->base;
-}
-
-static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
-{
- return rk_timer(ce)->ctrl;
-}
-
static inline void rk_timer_disable(struct rk_timer *timer)
{
writel_relaxed(TIMER_DISABLE, timer->ctrl);
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 07/13] clocksource/drivers/rockchip_timer: low level routines take rk_timer as parameter
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel, devicetree, linux-arm-kernel, linux-rockchip
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet@gmail.com>
Pass rk_timer instead of clock_event_device to low lever timer routines.
So that code could be reused by clocksource implementation.
This is refactoring step without functional changes.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
---
drivers/clocksource/rockchip_timer.c | 47 +++++++++++++++++++---------------
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 6d68d4c..aa9ccd1 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -63,60 +63,67 @@ static inline void __iomem *rk_ctrl(struct clock_event_device *ce)
return rk_timer(ce)->ctrl;
}
-static inline void rk_timer_disable(struct clock_event_device *ce)
+static inline void rk_timer_disable(struct rk_timer *timer)
{
- writel_relaxed(TIMER_DISABLE, rk_ctrl(ce));
+ writel_relaxed(TIMER_DISABLE, timer->ctrl);
}
-static inline void rk_timer_enable(struct clock_event_device *ce, u32 flags)
+static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
{
writel_relaxed(TIMER_ENABLE | TIMER_INT_UNMASK | flags,
- rk_ctrl(ce));
+ timer->ctrl);
}
static void rk_timer_update_counter(unsigned long cycles,
- struct clock_event_device *ce)
+ struct rk_timer *timer)
{
- writel_relaxed(cycles, rk_base(ce) + TIMER_LOAD_COUNT0);
- writel_relaxed(0, rk_base(ce) + TIMER_LOAD_COUNT1);
+ writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
+ writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
}
-static void rk_timer_interrupt_clear(struct clock_event_device *ce)
+static void rk_timer_interrupt_clear(struct rk_timer *timer)
{
- writel_relaxed(1, rk_base(ce) + TIMER_INT_STATUS);
+ writel_relaxed(1, timer->base + TIMER_INT_STATUS);
}
static inline int rk_timer_set_next_event(unsigned long cycles,
struct clock_event_device *ce)
{
- rk_timer_disable(ce);
- rk_timer_update_counter(cycles, ce);
- rk_timer_enable(ce, TIMER_MODE_USER_DEFINED_COUNT);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
+ rk_timer_update_counter(cycles, timer);
+ rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT);
return 0;
}
static int rk_timer_shutdown(struct clock_event_device *ce)
{
- rk_timer_disable(ce);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
return 0;
}
static int rk_timer_set_periodic(struct clock_event_device *ce)
{
- rk_timer_disable(ce);
- rk_timer_update_counter(rk_timer(ce)->freq / HZ - 1, ce);
- rk_timer_enable(ce, TIMER_MODE_FREE_RUNNING);
+ struct rk_timer *timer = rk_timer(ce);
+
+ rk_timer_disable(timer);
+ rk_timer_update_counter(timer->freq / HZ - 1, timer);
+ rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING);
return 0;
}
static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
{
struct clock_event_device *ce = dev_id;
+ struct rk_timer *timer = rk_timer(ce);
- rk_timer_interrupt_clear(ce);
+ rk_timer_interrupt_clear(timer);
if (clockevent_state_oneshot(ce))
- rk_timer_disable(ce);
+ rk_timer_disable(timer);
ce->event_handler(ce);
@@ -183,8 +190,8 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
ce->cpumask = cpu_possible_mask;
ce->rating = 250;
- rk_timer_interrupt_clear(ce);
- rk_timer_disable(ce);
+ rk_timer_interrupt_clear(timer);
+ rk_timer_disable(timer);
ret = request_irq(irq, rk_timer_interrupt, IRQF_TIMER, TIMER_NAME, ce);
if (ret) {
--
1.7.9.5
^ permalink raw reply related
* [PATCH v3 06/13] clocksource/drivers/rockchip_timer: split bc_timer into rk_timer and rk_clock_event_device
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The patch move ce field out of struct bc_timer into struct
rk_clock_event_device and rename struct bc_timer to struct rk_timer.
This is refactoring step without functional changes.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
drivers/clocksource/rockchip_timer.c | 33 ++++++++++++++++++++++-----------
1 file changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/clocksource/rockchip_timer.c b/drivers/clocksource/rockchip_timer.c
index 23e267a..6d68d4c 100644
--- a/drivers/clocksource/rockchip_timer.c
+++ b/drivers/clocksource/rockchip_timer.c
@@ -29,18 +29,28 @@
#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
#define TIMER_INT_UNMASK (1 << 2)
-struct bc_timer {
- struct clock_event_device ce;
+struct rk_timer {
void __iomem *base;
void __iomem *ctrl;
u32 freq;
};
-static struct bc_timer bc_timer;
+struct rk_clock_event_device {
+ struct clock_event_device ce;
+ struct rk_timer timer;
+};
+
+static struct rk_clock_event_device bc_timer;
+
+static inline struct rk_clock_event_device*
+rk_clock_event_device(struct clock_event_device *ce)
+{
+ return container_of(ce, struct rk_clock_event_device, ce);
+}
-static inline struct bc_timer *rk_timer(struct clock_event_device *ce)
+static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
{
- return container_of(ce, struct bc_timer, ce);
+ return &rk_clock_event_device(ce)->timer;
}
static inline void __iomem *rk_base(struct clock_event_device *ce)
@@ -116,16 +126,17 @@ static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
{
struct clock_event_device *ce = &bc_timer.ce;
+ struct rk_timer *timer = &bc_timer.timer;
struct clk *timer_clk;
struct clk *pclk;
int ret = -EINVAL, irq;
- bc_timer.base = of_iomap(np, 0);
- if (!bc_timer.base) {
+ timer->base = of_iomap(np, 0);
+ if (!timer->base) {
pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
return -ENXIO;
}
- bc_timer.ctrl = bc_timer.base + ctrl_reg;
+ timer->ctrl = timer->base + ctrl_reg;
pclk = of_clk_get_by_name(np, "pclk");
if (IS_ERR(pclk)) {
@@ -153,7 +164,7 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
goto out_timer_clk;
}
- bc_timer.freq = clk_get_rate(timer_clk);
+ timer->freq = clk_get_rate(timer_clk);
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
@@ -181,7 +192,7 @@ static int __init rk_timer_init(struct device_node *np, u32 ctrl_reg)
goto out_irq;
}
- clockevents_config_and_register(ce, bc_timer.freq, 1, UINT_MAX);
+ clockevents_config_and_register(ce, timer->freq, 1, UINT_MAX);
return 0;
@@ -190,7 +201,7 @@ out_irq:
out_timer_clk:
clk_disable_unprepare(pclk);
out_unmap:
- iounmap(bc_timer.base);
+ iounmap(timer->base);
return ret;
}
--
1.7.9.5
--
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* [PATCH v3 05/13] ARM: dts: rockchip: disable arm-global-timer for rk3188
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
arm-global-timer can provide clockevents, clocksource and shed_clock. But
on rk3188 platform it provide only clocksource and shed_clock. clockevents
from arm-global-timer is not used by kernel because there is another
clockevent provider with higher rating (smp-twd).
My commit from the series implement clocksource and shed_clock using
rockchip_timer. But sched clock from rk_timer is not selected by kernel
due to lower frequency than arm-global-timer, and clocksource from
rk_timer is not selected by kernel due to lower rating than
arm-global-timer. And I don't want to increase clocksource rating
because ratings greater than 300 used for high frequency clocksources.
clocksource and shed_clock is quite unstable, because their rate depends
on cpu frequency. So disable arm-global-timer and use clocksource and
sched_clock from rockchip_timer.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/rk3188.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 0dc52fe..44da3d42 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -546,6 +546,7 @@
&global_timer {
interrupts = <GIC_PPI 11 0xf04>;
+ status = "disabled";
};
&local_timer {
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 04/13] ARM: dts: rockchip: add timer entries to rk3188 dtsi
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
The patch add two timers to all rk3188 based boards.
The first timer is from alive subsystem and it act as a backup
for the local timers at sleep time. It act the same as timers
on other rockchip chips already present in kernel.
The second timer is from CPU subsystem and act as replacement
for the arm-global-timer clocksource. It run as stable frequency
24MHz.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/rk3188.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 31f81b2..0dc52fe 100644
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -106,6 +106,22 @@
};
};
+ timer3: timer@2000e000 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x2000e000 0x20>;
+ interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER3>, <&cru PCLK_TIMER3>;
+ clock-names = "timer", "pclk";
+ };
+
+ timer6: timer@200380a0 {
+ compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";
+ reg = <0x200380a0 0x20>;
+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_TIMER6>, <&cru PCLK_TIMER0>;
+ clock-names = "timer", "pclk";
+ };
+
i2s0: i2s@1011a000 {
compatible = "rockchip,rk3188-i2s", "rockchip,rk3066-i2s";
reg = <0x1011a000 0x2000>;
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 03/13] ARM: dts: rockchip: update compatible property for rk3229 timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Property set to '"rockchip,rk3229-timer", "rockchip,rk3288-timer"'
to match devicetree bindings.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/rk3229-evb.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3229-evb.dts b/arch/arm/boot/dts/rk3229-evb.dts
index b6a1203..6629769 100644
--- a/arch/arm/boot/dts/rk3229-evb.dts
+++ b/arch/arm/boot/dts/rk3229-evb.dts
@@ -88,3 +88,7 @@
&uart2 {
status = "okay";
};
+
+&timer {
+ compatible = "rockchip,rk3229-timer", "rockchip,rk3288-timer";
+};
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 02/13] ARM: dts: rockchip: update compatible property for rk3228 timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Property set to '"rockchip,rk3228-timer", "rockchip,rk3288-timer"'
to match devicetree bindings.
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/rk3228-evb.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/rk3228-evb.dts b/arch/arm/boot/dts/rk3228-evb.dts
index 904668e..38eab87 100644
--- a/arch/arm/boot/dts/rk3228-evb.dts
+++ b/arch/arm/boot/dts/rk3228-evb.dts
@@ -70,3 +70,7 @@
&uart2 {
status = "okay";
};
+
+&timer {
+ compatible = "rockchip,rk3228-timer", "rockchip,rk3288-timer";
+};
--
1.7.9.5
--
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^ permalink raw reply related
* [PATCH v3 01/13] dt-bindings: clarify compatible property for rockchip timers
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480427118-5126-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Make all properties description in form '"rockchip,<chip>-timer",
"rockchip,rk3288-timer"' for all chips found in linux kernel.
Suggested-by: Heiko Stübner <heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org>
Signed-off-by: Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
---
.../bindings/timer/rockchip,rk-timer.txt | 12 +++++++++---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt
index a41b184..16a5f45 100644
--- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt
+++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.txt
@@ -1,9 +1,15 @@
Rockchip rk timer
Required properties:
-- compatible: shall be one of:
- "rockchip,rk3288-timer" - for rk3066, rk3036, rk3188, rk322x, rk3288, rk3368
- "rockchip,rk3399-timer" - for rk3399
+- compatible: should be:
+ "rockchip,rk3036-timer", "rockchip,rk3288-timer": for Rockchip RK3036
+ "rockchip,rk3066-timer", "rockchip,rk3288-timer": for Rockchip RK3066
+ "rockchip,rk3188-timer", "rockchip,rk3288-timer": for Rockchip RK3188
+ "rockchip,rk3228-timer", "rockchip,rk3288-timer": for Rockchip RK3228
+ "rockchip,rk3229-timer", "rockchip,rk3288-timer": for Rockchip RK3229
+ "rockchip,rk3288-timer": for Rockchip RK3288
+ "rockchip,rk3368-timer", "rockchip,rk3288-timer": for Rockchip RK3368
+ "rockchip,rk3399-timer": for Rockchip RK3399
- reg: base address of the timer register starting with TIMERS CONTROL register
- interrupts: should contain the interrupts for Timer0
- clocks : must contain an entry for each entry in clock-names
--
1.7.9.5
--
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* [PATCH v3 00/13] Implement clocksource for rockchip SoC using rockchip timer
From: Alexander Kochetkov @ 2016-11-29 13:45 UTC (permalink / raw)
To: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: Thomas Gleixner, Heiko Stuebner, Mark Rutland, Rob Herring,
Russell King, Caesar Wang, Huang Tao, Daniel Lezcano,
Alexander Kochetkov
In-Reply-To: <1480343486-25539-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hello,
This patch series contain:
- devicetree bindings clarification for rockchip timers
- dts files fixes for rk3228-evb, rk3229-evb and rk3188
- implementation of clocksource for rockchip SoC
The clock supplying the arm-global-timer on the rk3188 is coming from the
the cpu clock itself and thus changes its rate everytime cpufreq adjusts
the cpu frequency making this timer unsuitable as a stable clocksource.
The rk3188, rk3288 and following socs share a separate timer block already
handled by the rockchip-timer driver. Therefore adapt this driver to also
be able to act as clocksource on rk3188.
In order to test clocksource you can run following commands and check
how much time it take in real. On rk3188 it take about ~45 seconds.
Such error cannot be fixed using NTP. Haven't test clocksource
on rk3288 and onwards. Guess they can also have unstable clocksource.
cpufreq-set -f 1.6GHZ
date; sleep 60; date
Regards,
Alexander.
Changes in v3:
added patches:
ARM: dts: rockchip: disable arm-global-timer for rk3188
clocksource/drivers/rockchip_timer: Prevent ftrace recursion
This is try 3. Please discard all v1 patches:
devicetree:
https://patchwork.ozlabs.org/patch/699019/
https://patchwork.ozlabs.org/patch/699020/
kernel:
https://patchwork.kernel.org/patch/9443975/
https://patchwork.kernel.org/patch/9443971/
https://patchwork.kernel.org/patch/9443959/
https://patchwork.kernel.org/patch/9443963/
https://patchwork.kernel.org/patch/9443979/
https://patchwork.kernel.org/patch/9443989/
https://patchwork.kernel.org/patch/9443987/
https://patchwork.kernel.org/patch/9443977/
https://patchwork.kernel.org/patch/9443991/
Old thread:
http://lists.infradead.org/pipermail/linux-rockchip/2016-November/013147.html
Alexander Kochetkov (13):
dt-bindings: clarify compatible property for rockchip timers
ARM: dts: rockchip: update compatible property for rk3228 timer
ARM: dts: rockchip: update compatible property for rk3229 timer
ARM: dts: rockchip: add timer entries to rk3188 dtsi
ARM: dts: rockchip: disable arm-global-timer for rk3188
clocksource/drivers/rockchip_timer: split bc_timer into rk_timer and
rk_clock_event_device
clocksource/drivers/rockchip_timer: low level routines take rk_timer
as parameter
clocksource/drivers/rockchip_timer: drop unused rk_base() and
rk_ctrl()
clocksource/drivers/rockchip_timer: move TIMER_INT_UNMASK out of
rk_timer_enable()
clocksource/drivers/rockchip_timer: implement loading 64bit value
into timer
clocksource/drivers/rockchip_timer: implement reading 64bit value
from timer
clocksource/drivers/rockchip_timer: implement clocksource timer
clocksource/drivers/rockchip_timer: Prevent ftrace recursion
.../bindings/timer/rockchip,rk-timer.txt | 12 +-
arch/arm/boot/dts/rk3188.dtsi | 17 ++
arch/arm/boot/dts/rk3228-evb.dts | 4 +
arch/arm/boot/dts/rk3229-evb.dts | 4 +
drivers/clocksource/rockchip_timer.c | 207 +++++++++++++++-----
5 files changed, 190 insertions(+), 54 deletions(-)
--
1.7.9.5
--
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^ permalink raw reply
* Re: [PATCH v10 3/4] dtc: Plugin and fixup support
From: Pantelis Antoniou @ 2016-11-29 13:11 UTC (permalink / raw)
To: Phil Elwell
Cc: David Gibson, Jon Loeliger, Grant Likely, Frank Rowand,
Rob Herring, Jan Luebbe, Sascha Hauer, Simon Glass, Maxime Ripard,
Thomas Petazzoni, Boris Brezillon, Antoine Tenart, Stephen Boyd,
Devicetree Compiler, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <c06f9906-6089-c145-3b36-c410d88c786d-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org>
Hi Phil,
> On Nov 29, 2016, at 15:11 , Phil Elwell <phil-FnsA7b+Nu9XbIbC87yuRow@public.gmane.org> wrote:
>
> On 29/11/2016 13:08, Pantelis Antoniou wrote:
>> There’s no difference; you can cpp -IFOO_VALUE=foo in.dts | dtc | cat >/config/foo/dtb in a nutshell.
>>
>> And have foo-property = FOO_VALUE; in in.dts.
> In a boot loader?
>
Ah, that why you don’t do that in the bootloader :)
Regards
— Pantelis
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