* Re: [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Chen-Yu Tsai @ 2016-12-02 16:41 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Maxime Ripard, Chen-Yu Tsai, Rob Herring, Russell King,
Andre Przywara, Hans de Goede, Arnd Bergmann, Vishnu Patekar,
linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel, linux-kernel, devicetree, linux-sunxi
In-Reply-To: <20161202150513.34691-2-icenowy-ymACFijhrKM@public.gmane.org>
Hi,
On Fri, Dec 2, 2016 at 11:05 PM, Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org> wrote:
> Orange Pi Zero is a board that came with the new Allwinner H2+ SoC and a
> SDIO Wi-Fi chip by Allwinner (XR819).
>
> Add a device tree file for it.
>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> Changes since v2:
> - Merged SDIO Wi-Fi patch into it.
> - SDIO Wi-Fi: add a ethernet1 alias to it, as it has no internal NVRAM.
> - SDIO Wi-Fi: changed pinctrl binding to generic pinconf
> - removed all gpio pinctrl nodes
> - changed h2plus to h2-plus
> Changes since v1:
> - Convert to generic pinconf bindings.
> - SDIO Wi-Fi: add patch.
>
> Some notes:
> - The uart1 and uart2 is available on the unsoldered gpio header.
> - The onboard USB connector has its Vbus directly connected to DCIN-5V (the
> power jack)
>
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 159 ++++++++++++++++++++++
> 2 files changed, 160 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 6447abc..59f6e86 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -844,6 +844,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
> sun8i-a33-sinlinx-sina33.dtb \
> sun8i-a83t-allwinner-h8homlet-v2.dtb \
> sun8i-a83t-cubietruck-plus.dtb \
> + sun8i-h2-plus-orangepi-zero.dtb \
> sun8i-h3-bananapi-m2-plus.dtb \
> sun8i-h3-nanopi-neo.dtb \
> sun8i-h3-orangepi-2.dtb \
> diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> new file mode 100644
> index 0000000..d18807f
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
> @@ -0,0 +1,159 @@
> +/*
> + * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> + *
> + * Based on sun8i-h3-orangepi-one.dts, which is:
> + * Copyright (C) 2016 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun8i-h3.dtsi"
> +#include "sunxi-common-regulators.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "Xunlong Orange Pi Zero";
> + compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus";
> +
> + aliases {
> + serial0 = &uart0;
> + /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
> + ethernet1 = &xr819;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> +
> + pwr_led {
> + label = "orangepi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "orangepi:red:status";
> + gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + reg_vcc_wifi: reg_vcc_wifi {
> + compatible = "regulator-fixed";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-name = "vcc-wifi";
> + enable-active-high;
> + gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
> + };
> +
> + wifi_pwrseq: wifi_pwrseq {
> + compatible = "mmc-pwrseq-simple";
> + reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>;
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
> + status = "okay";
> +};
> +
> +&mmc1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc1_pins_a>;
> + vmmc-supply = <®_vcc_wifi>;
> + mmc-pwrseq = <&wifi_pwrseq>;
> + bus-width = <4>;
> + non-removable;
> + status = "okay";
> +
> + /*
> + * Explicitly define the sdio device, so that we can add an ethernet
> + * alias for it (which e.g. makes u-boot set a mac-address).
> + */
> + xr819: sdio_wifi@1 {
> + reg = <1>;
> + };
> +};
> +
> +&mmc1_pins_a {
> + bias-pull-up;
This is already set in h3.dtsi
> +};
> +
> +&ohci1 {
> + status = "okay";
> +};
> +
> +&uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_pins_a>;
> + status = "okay";
> +};
> +
> +&uart1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_pins>;
> + status = "disabled";
> +};
> +
> +&uart2 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2_pins>;
> + status = "disabled";
> +};
> +
> +&usbphy {
> + /* USB VBUS is always on */
I think this comment could use a little work.
AFAIK this board doesn't have an actual USB port.
It's just the D+/D- pins on the pin header, along
with the board-wide 5V, also on the pin header.
ChenYu
> + status = "okay";
> +};
> --
> 2.10.2
>
> --
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^ permalink raw reply
* Re: [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Chen-Yu Tsai @ 2016-12-02 16:37 UTC (permalink / raw)
To: Andre Przywara
Cc: Mark Rutland, devicetree@vger.kernel.org, Vishnu Patekar,
Arnd Bergmann, Jonathan Corbet, linux-doc@vger.kernel.org,
Russell King, linux-kernel@vger.kernel.org, Hans de Goede,
Chen-Yu Tsai, Icenowy Zheng, Maxime Ripard,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <324c8820-aeea-3fad-0e02-1bdb8f675677@arm.com>
On Sat, Dec 3, 2016 at 12:10 AM, Andre Przywara <andre.przywara@arm.com> wrote:
> Hi,
>
> On 02/12/16 14:32, Icenowy Zheng wrote:
>>
>>
>> 02.12.2016, 22:30, "Hans de Goede" <hdegoede@redhat.com>:
>>> Hi,
>>>
>>> On 02-12-16 15:22, Icenowy Zheng wrote:
>>>> 01.12.2016, 17:36, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>>>> On Mon, Nov 28, 2016 at 12:29:07AM +0000, André Przywara wrote:
>>>>>> > Something more interesting happened.
>>>>>> >
>>>>>> > Xunlong made a add-on board for Orange Pi Zero, which exposes the
>>>>>> > two USB Controllers exported at expansion bus as USB Type-A
>>>>>> > connectors.
>>>>>> >
>>>>>> > Also it exposes a analog A/V jack and a microphone.
>>>>>> >
>>>>>> > Should I enable {e,o}hci{2.3} in the device tree?
>>>>>>
>>>>>> Actually we should do this regardless of this extension board. The USB
>>>>>> pins are not multiplexed and are exposed on user accessible pins (just
>>>>>> not soldered, but that's a detail), so I think they qualify for DT
>>>>>> enablement. And even if a user can't use them, it doesn't hurt to have
>>>>>> them (since they are not multiplexed).
>>>>>
>>>>> My main concern about this is that we'll leave regulators enabled by
>>>>> default, for a minority of users. And that minority will prevent to do
>>>>> a proper power management when the times come since we'll have to keep
>>>>> that behaviour forever.
>>>>
>>>> I think these users can add a 'fdt set /xxx/xxx status "disabled" ' .
>>>
>>> I don't think that will be necessary I'm pretty sure these extra usb
>>> ports do not have a regulator for the Vbus, they just hook directly
>>> to the 5V rail, can someone with a schematic check ?
>>
>> We seems to have still no schematics for the add-on board.
>
> From looking at the picture of that expansion board on the Aliexpress
> page and chasing the tracks, there is clearly no voltage regulator on
> there, it's just passive components. The 5V pin from the headers is
> routed forth and back between the two layers via some vias directly to
> the 5V pins of the USB sockets.
>
>> But something is sure is that there's no any regulator-related pins
>> on the add-on pinout. There's only USB DM and DP pins.
>>
>> So the Vbus must be directly connected to +5V.
>
> So yes, it is.
>
> But I think the question is moot anyways, since we don't provide DT
> support for that add-on board at that point anyways.
> One could imagine another board, though, which has regulators switched
> by GPIOs, but that would be their problem and they would have regulators
> specified in their specific DT snippet, then.
>
> So to summarize:
> - For that specific Orange Pi Zero board which we discuss the DT for
> there is no regulator support for the additional USB ports. Thus nothing
> we could turn off to save power.
> - A user could just take these USB brackets with pin headers that are so
> common in PCs to connect additional USB ports to the back of the box.
> One just needs to re-sort the pins, which is a matter of a minute.
> - As long as we don't provide any easy way of handling DT changes, we
> should enable the USB ports for the sake of the users of either those
> brackets or the expansion board. Any more sophisticated USB expansion
> board with regulators would need to amend the DT anyway.
>
> Does that make sense?
Sounds good to me.
ChenYu
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^ permalink raw reply
* Re: [PATCH 39/39] mtd: nand: denali_dt: add compatible strings for UniPhier SoC variants
From: Rob Herring @ 2016-12-02 16:26 UTC (permalink / raw)
To: Masahiro Yamada
Cc: linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Linux Kernel Mailing List, Boris Brezillon, Marek Vasut,
Brian Norris, Richard Weinberger, David Woodhouse,
Cyrille Pitchen, Mark Rutland, Dinh Nguyen
In-Reply-To: <CAK7LNASJLbizHEh8mUUVDvTKiRMCSvyYtdrQzwN5tHmCV8iYOA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 1, 2016 at 8:54 PM, Masahiro Yamada
<yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org> wrote:
> Hi Rob,
> (+CC Dinh)
>
> 2016-12-02 1:05 GMT+09:00 Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>:
>> On Sun, Nov 27, 2016 at 03:06:25AM +0900, Masahiro Yamada wrote:
>>> Add two compatible strings for UniPhier SoCs. The revision register
>>> on both shows revision 5.0, but they are different hardware.
>>>
>>> Features:
>>> - DMA engine with 64 bit physical address support
>>> - 1024 byte ECC step size
>>> - 8 / 16 / 24 bit ECC strength
>>> - The n_banks format depends on SoC
>>>
>>> Signed-off-by: Masahiro Yamada <yamada.masahiro-uWyLwvC0a2jby3iVrkZq2A@public.gmane.org>
>>> ---
>>>
>>> .../devicetree/bindings/mtd/denali-nand.txt | 10 +++++--
>>> drivers/mtd/nand/denali_dt.c | 33 ++++++++++++++++++++--
>>> 2 files changed, 38 insertions(+), 5 deletions(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mtd/denali-nand.txt b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> index 51fe195..cea46e2 100644
>>> --- a/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> +++ b/Documentation/devicetree/bindings/mtd/denali-nand.txt
>>> @@ -1,13 +1,19 @@
>>> * Denali NAND controller
>>>
>>> Required properties:
>>> - - compatible : should be "denali,denali-nand-dt"
>>> + - compatible : should be one of the following:
>>> + "denali,denali-nand-dt"
>>
>> There are multiple things wrong with this string. denali,denali is
>> redundant is one.
>
> One more redundancy; "-dt" is weird because
> DT compatible should be a name of hardware.
>
>
>> It's also fairly useless as this IP has several
>> versions and numerous configuration options IIRC. This should be
>> deprecated IMO.
>
> Right. There are several customizable parameters for this IP,
> so a generic compatible string like this is probably useless.
>
> This DT binding was added by commit 30f9f2f for Altera SOCFPGA,
> A funny thing is that they upstreamed DT binding, but they did not upstream
> needed changes for the Denali driver core.
> So, the mainline driver has never worked on SOCFPGA
> (or any of DT-based SoCs).
>
>
>
>>> + "denali,denali-nand-uniphier-v5a"
>>> + "denali,denali-nand-uniphier-v5b"
>>
>> Use your vendor prefix, not denali. The 2nd denali can probably be
>> dropped because it is not likely you have another kind of nand
>> controller in the SoC.
>
> Hmm, your statement implies that a vendor prefix
> belongs to an SoC vendor, not an IP vendor.
> (I was not quite sure about this.)
Right. We do have some IP vendor strings, but they are usually
fallbacks. Sometimes, I guess they are useful, but IMO over time they
prove to not be useful.
> It is unlikely to happen to have two different NAND controllers on one SoC.
> But, we used a different NAND controller for our SoC family before
> introducing the Denali IP.
> It also implies that Socionext may use a different NAND IP in the future.
> I'd like to include "denali" somewhere because it is clearly associated with
> the driver name.
> Also, this will give an idea what kind of _basic_ hardware is used,
> even though we know various parameters are customizable.
>
>
>
> (Plan A)
> "denali,socfpga-nand" (for Altera SOCFPGA variant)
> "denali,uniphier-nand-v1" (for old Socionext UniPhier family variant)
> "denali,uniphier-nand-v2" (for new Socionext UniPhier family variant)
>
> (Plan B)
> "altera,denali-nand" (for Altera SOCFPGA variant)
> "socionext,denali-nand-v5a" (for old Socionext UniPhier family variant)
> "socionext,denali-nand-v5b" (for new Socionext UniPhier family variant)
Let the Altera folks worry about their stuff. At least for soft IP in
FPGA, it's a bit of a special case. The old string can remain as bad
as it is. I simply would do "socionext,uniphier-v5b-nand" (and v5a).
The fact that it is denali is part of the documentation.
Rob
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^ permalink raw reply
* Re: [PATCH] MIPS: NI 169445 board support
From: Zubair Lutfullah Kakakhel @ 2016-12-02 16:21 UTC (permalink / raw)
To: Nathan Sullivan, ralf, mark.rutland, robh+dt
Cc: linux-mips, devicetree, linux-kernel
In-Reply-To: <1480693329-22265-1-git-send-email-nathan.sullivan@ni.com>
Hi,
On 12/02/2016 03:42 PM, Nathan Sullivan wrote:
> Support the National Instruments 169445 board.
Interesting patch.
But do you happen to have a link to a description of the board?
I couldn't find anything with a quick search.
Perhaps the public name is something else?
Thanks,
ZubairLK
>
> Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
> ---
> "gpio: mmio: add support for NI 169445 NAND GPIO" and
> "devicetree: add vendor prefix for National Instruments" are required for the
> NAND on this board to work.
>
> Documentation/devicetree/bindings/mips/ni.txt | 7 ++
> arch/mips/Kbuild.platforms | 1 +
> arch/mips/Kconfig | 26 ++++++
> arch/mips/boot/dts/Makefile | 1 +
> arch/mips/boot/dts/ni/169445.dts | 99 +++++++++++++++++++++
> arch/mips/boot/dts/ni/Makefile | 9 ++
> arch/mips/configs/ni169445_defconfig | 120 ++++++++++++++++++++++++++
> arch/mips/ni169445/169445-console.c | 38 ++++++++
> arch/mips/ni169445/169445-init.c | 39 +++++++++
> arch/mips/ni169445/169445-int.c | 34 ++++++++
> arch/mips/ni169445/169445-setup.c | 58 +++++++++++++
> arch/mips/ni169445/169445-time.c | 35 ++++++++
> arch/mips/ni169445/Makefile | 9 ++
> arch/mips/ni169445/Platform | 6 ++
> 14 files changed, 482 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
> create mode 100644 arch/mips/boot/dts/ni/169445.dts
> create mode 100644 arch/mips/boot/dts/ni/Makefile
> create mode 100644 arch/mips/configs/ni169445_defconfig
> create mode 100644 arch/mips/ni169445/169445-console.c
> create mode 100644 arch/mips/ni169445/169445-init.c
> create mode 100644 arch/mips/ni169445/169445-int.c
> create mode 100644 arch/mips/ni169445/169445-setup.c
> create mode 100644 arch/mips/ni169445/169445-time.c
> create mode 100644 arch/mips/ni169445/Makefile
> create mode 100644 arch/mips/ni169445/Platform
>
> diff --git a/Documentation/devicetree/bindings/mips/ni.txt b/Documentation/devicetree/bindings/mips/ni.txt
> new file mode 100644
> index 0000000..722bf2d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/ni.txt
> @@ -0,0 +1,7 @@
> +National Instruments MIPS platforms
> +
> +required root node properties:
> + - compatible: must be "ni,169445"
> +
> +CPU Nodes
> + - compatible: must be "mti,mips14KEc"
> diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
> index f5f1bdb..f2d7b5c 100644
> --- a/arch/mips/Kbuild.platforms
> +++ b/arch/mips/Kbuild.platforms
> @@ -20,6 +20,7 @@ platforms += loongson32
> platforms += loongson64
> platforms += mti-malta
> platforms += netlogic
> +platforms += ni169445
> platforms += paravirt
> platforms += pic32
> platforms += pistachio
> diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
> index b3c5bde..d24d11f 100644
> --- a/arch/mips/Kconfig
> +++ b/arch/mips/Kconfig
> @@ -574,6 +574,32 @@ config NXP_STB225
> help
> Support for NXP Semiconductors STB225 Development Board.
>
> +config NI_169445
> + bool "NI 169445 board"
> + select ARCH_WANT_OPTIONAL_GPIOLIB
> + select BOOT_ELF32
> + select BOOT_RAW
> + select BUILTIN_DTB
> + select CEVT_R4K
> + select CSRC_R4K
> + select CPU_MIPSR2_IRQ_VI
> + select CPU_MIPSR2_IRQ_EI
> + select DMA_NONCOHERENT
> + select IRQ_MIPS_CPU
> + select LIBFDT
> + select MIPS_MSC
> + select SYS_HAS_CPU_MIPS32_R1
> + select SYS_HAS_CPU_MIPS32_R2
> + select SYS_HAS_EARLY_PRINTK
> + select SYS_SUPPORTS_32BIT_KERNEL
> + select SYS_SUPPORTS_LITTLE_ENDIAN
> + select USE_OF
> + select COMMON_CLK
> + help
> + This enables support for the National Instruments 169445A
> + board.
> +
> +
> config PMC_MSP
> bool "PMC-Sierra MSP chipsets"
> select CEVT_R4K
> diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
> index fc7a0a9..65a0ad8 100644
> --- a/arch/mips/boot/dts/Makefile
> +++ b/arch/mips/boot/dts/Makefile
> @@ -3,6 +3,7 @@ dts-dirs += cavium-octeon
> dts-dirs += ingenic
> dts-dirs += lantiq
> dts-dirs += mti
> +dts-dirs += ni
> dts-dirs += netlogic
> dts-dirs += pic32
> dts-dirs += qca
> diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
> new file mode 100644
> index 0000000..a2b49f9
> --- /dev/null
> +++ b/arch/mips/boot/dts/ni/169445.dts
> @@ -0,0 +1,99 @@
> +/dts-v1/;
> +
> +/ {
> + #address-cells = <1>;
> + #size-cells = <1>;
> + compatible = "ni,169445";
> +
> + cpus {
> + mips-hpt-frequency = <25000000>;
> +
> + cpu@0 {
> + compatible = "mti,mips14KEc";
> + };
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x0 0x08000000>;
> + };
> +
> + clocks {
> + baseclk: baseclock {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <50000000>;
> + };
> + };
> +
> + cpu_intc: cpu_intc {
> + #address-cells = <0>;
> + compatible = "mti,cpu-interrupt-controller";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + };
> +
> + ahb@0 {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + gpio1: nand-gpio-out@1f300010 {
> + compatible = "ni,169445-nand-gpio";
> + reg = <0x1f300010 0x4>;
> + reg-names = "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <5>;
> + };
> +
> + gpio2: nand-gpio-in@1f300014 {
> + compatible = "ni,169445-nand-gpio";
> + reg = <0x1f300014 0x4>;
> + reg-names = "dat";
> + gpio-controller;
> + #gpio-cells = <2>;
> + ngpios = <1>;
> + };
> +
> + nand@1f300000 {
> + compatible = "gpio-control-nand";
> + nand-on-flash-bbt;
> + nand-ecc-mode = "soft_bch";
> + nand-ecc-step-size = <512>;
> + nand-ecc-strength = <4>;
> + reg = <0x1f300000 4>;
> + gpios = <&gpio2 0 0>, /* rdy */
> + <&gpio1 1 0>, /* nce */
> + <&gpio1 2 0>, /* ale */
> + <&gpio1 3 0>, /* cle */
> + <&gpio1 4 0>; /* nwp */
> + };
> +
> + serial@1f380000 {
> + compatible = "ns16550a";
> + reg = <0x1f380000 0x1000>;
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <6>;
> + clocks = <&baseclk>;
> + reg-shift = <0>;
> + };
> +
> + ethernet@1f340000 {
> + compatible = "snps,dwc-qos-ethernet-4.10";
> + interrupt-parent = <&cpu_intc>;
> + interrupts = <5>;
> + reg = <0x1f340000 0x2000>;
> + clock-names = "apb_pclk", "phy_ref_clk";
> + clocks = <&baseclk>, <&baseclk>;
> +
> + phy-mode = "rgmii";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> +};
> diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
> new file mode 100644
> index 0000000..5291c18
> --- /dev/null
> +++ b/arch/mips/boot/dts/ni/Makefile
> @@ -0,0 +1,9 @@
> +dtb-$(CONFIG_NI_169445) += 169445.dtb
> +
> +obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
> +
> +# Force kbuild to make empty built-in.o if necessary
> +obj- += dummy.o
> +
> +always := $(dtb-y)
> +clean-files := *.dtb *.dtb.S
> diff --git a/arch/mips/configs/ni169445_defconfig b/arch/mips/configs/ni169445_defconfig
> new file mode 100644
> index 0000000..e5a34df
> --- /dev/null
> +++ b/arch/mips/configs/ni169445_defconfig
> @@ -0,0 +1,120 @@
> +CONFIG_NI_169445=y
> +CONFIG_CPU_MIPS32_R2=y
> +CONFIG_HZ_100=y
> +CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
> +# CONFIG_SWAP is not set
> +CONFIG_SYSVIPC=y
> +CONFIG_HZ_PERIODIC=y
> +CONFIG_NO_HZ=y
> +CONFIG_HIGH_RES_TIMERS=y
> +CONFIG_IKCONFIG=y
> +CONFIG_IKCONFIG_PROC=y
> +CONFIG_LOG_BUF_SHIFT=15
> +CONFIG_BLK_DEV_INITRD=y
> +# CONFIG_RD_GZIP is not set
> +# CONFIG_RD_LZMA is not set
> +# CONFIG_RD_XZ is not set
> +# CONFIG_RD_LZO is not set
> +# CONFIG_RD_LZ4 is not set
> +# CONFIG_SHMEM is not set
> +CONFIG_EMBEDDED=y
> +CONFIG_SLAB=y
> +CONFIG_PROFILING=y
> +# CONFIG_LBDAF is not set
> +# CONFIG_BLK_DEV_BSG is not set
> +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
> +# CONFIG_SUSPEND is not set
> +CONFIG_NET=y
> +CONFIG_PACKET=y
> +CONFIG_UNIX=y
> +CONFIG_INET=y
> +# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET_XFRM_MODE_TUNNEL is not set
> +# CONFIG_INET_XFRM_MODE_BEET is not set
> +# CONFIG_INET_DIAG is not set
> +# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
> +# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
> +CONFIG_NETFILTER=y
> +CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
> +CONFIG_IP_NF_IPTABLES=y
> +CONFIG_IP_NF_FILTER=y
> +CONFIG_IP6_NF_IPTABLES=y
> +CONFIG_IP6_NF_FILTER=y
> +# CONFIG_WIRELESS is not set
> +CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
> +CONFIG_DEVTMPFS=y
> +CONFIG_DEVTMPFS_MOUNT=y
> +CONFIG_MTD=y
> +CONFIG_MTD_CMDLINE_PARTS=y
> +CONFIG_MTD_BLOCK_RO=y
> +CONFIG_MTD_NAND=y
> +CONFIG_MTD_NAND_ECC_BCH=y
> +CONFIG_MTD_NAND_GPIO=y
> +CONFIG_MTD_UBI=y
> +CONFIG_MTD_UBI_BLOCK=y
> +CONFIG_NETDEVICES=y
> +# CONFIG_NET_VENDOR_AMAZON is not set
> +# CONFIG_NET_VENDOR_ARC is not set
> +# CONFIG_NET_CADENCE is not set
> +# CONFIG_NET_VENDOR_BROADCOM is not set
> +# CONFIG_NET_VENDOR_EZCHIP is not set
> +# CONFIG_NET_VENDOR_INTEL is not set
> +# CONFIG_NET_VENDOR_MARVELL is not set
> +# CONFIG_NET_VENDOR_MICREL is not set
> +# CONFIG_NET_VENDOR_NATSEMI is not set
> +# CONFIG_NET_VENDOR_NETRONOME is not set
> +# CONFIG_NET_VENDOR_QUALCOMM is not set
> +# CONFIG_NET_VENDOR_RENESAS is not set
> +# CONFIG_NET_VENDOR_ROCKER is not set
> +# CONFIG_NET_VENDOR_SAMSUNG is not set
> +# CONFIG_NET_VENDOR_SEEQ is not set
> +# CONFIG_NET_VENDOR_SMSC is not set
> +# CONFIG_NET_VENDOR_STMICRO is not set
> +CONFIG_SYNOPSYS_DWC_ETH_QOS=y
> +# CONFIG_NET_VENDOR_VIA is not set
> +# CONFIG_NET_VENDOR_WIZNET is not set
> +# CONFIG_NET_VENDOR_XILINX is not set
> +# CONFIG_WLAN is not set
> +# CONFIG_INPUT_MOUSEDEV is not set
> +# CONFIG_INPUT_KEYBOARD is not set
> +# CONFIG_INPUT_MOUSE is not set
> +# CONFIG_SERIO is not set
> +# CONFIG_CONSOLE_TRANSLATIONS is not set
> +CONFIG_VT_HW_CONSOLE_BINDING=y
> +CONFIG_LEGACY_PTY_COUNT=32
> +CONFIG_SERIAL_8250=y
> +# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
> +CONFIG_SERIAL_8250_CONSOLE=y
> +CONFIG_SERIAL_8250_NR_UARTS=2
> +CONFIG_SERIAL_8250_RUNTIME_UARTS=2
> +CONFIG_SERIAL_OF_PLATFORM=y
> +# CONFIG_HW_RANDOM is not set
> +CONFIG_GPIOLIB=y
> +CONFIG_GPIO_SYSFS=y
> +CONFIG_GPIO_GENERIC_PLATFORM=y
> +# CONFIG_HWMON is not set
> +# CONFIG_VGA_CONSOLE is not set
> +# CONFIG_HID is not set
> +# CONFIG_USB_SUPPORT is not set
> +# CONFIG_MIPS_PLATFORM_DEVICES is not set
> +# CONFIG_IOMMU_SUPPORT is not set
> +CONFIG_UBIFS_FS=y
> +CONFIG_UBIFS_FS_ADVANCED_COMPR=y
> +# CONFIG_UBIFS_FS_ZLIB is not set
> +CONFIG_SQUASHFS=y
> +# CONFIG_SQUASHFS_ZLIB is not set
> +CONFIG_SQUASHFS_LZO=y
> +CONFIG_SQUASHFS_XZ=y
> +# CONFIG_NETWORK_FILESYSTEMS is not set
> +# CONFIG_FTRACE is not set
> +CONFIG_CRYPTO_CBC=y
> +CONFIG_CRYPTO_ECB=y
> +CONFIG_CRYPTO_CRC32C=y
> +CONFIG_CRYPTO_ARC4=y
> +# CONFIG_CRYPTO_HW is not set
> +# CONFIG_XZ_DEC_X86 is not set
> +# CONFIG_XZ_DEC_POWERPC is not set
> +# CONFIG_XZ_DEC_IA64 is not set
> +# CONFIG_XZ_DEC_ARM is not set
> +# CONFIG_XZ_DEC_ARMTHUMB is not set
> +# CONFIG_XZ_DEC_SPARC is not set
> diff --git a/arch/mips/ni169445/169445-console.c b/arch/mips/ni169445/169445-console.c
> new file mode 100644
> index 0000000..f07e48b
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-console.c
> @@ -0,0 +1,38 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/console.h>
> +#include <linux/serial_reg.h>
> +#include <linux/io.h>
> +
> +#define NI_UART0_REGS_BASE ((unsigned char __iomem *)0xbf380000)
> +
> +static inline unsigned char serial_in(int offset)
> +{
> + return __raw_readb(NI_UART0_REGS_BASE + offset);
> +}
> +
> +static inline void serial_out(int offset, char value)
> +{
> + __raw_writeb(value, NI_UART0_REGS_BASE + offset);
> +}
> +
> +int prom_putchar(char c)
> +{
> + while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
> + ;
> +
> + serial_out(UART_TX, c);
> +
> + return 1;
> +}
> diff --git a/arch/mips/ni169445/169445-init.c b/arch/mips/ni169445/169445-init.c
> new file mode 100644
> index 0000000..5c7ff5e
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-init.c
> @@ -0,0 +1,39 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/initrd.h>
> +#include <linux/io.h>
> +
> +#include <asm/bootinfo.h>
> +#include <asm/cacheflush.h>
> +#include <asm/traps.h>
> +#include <asm/mips-boards/generic.h>
> +#include <asm/fw/fw.h>
> +
> +void __init prom_init(void)
> +{
> + fw_init_cmdline();
> +
> +#ifdef CONFIG_BLK_DEV_INITRD
> + /* Read the initrd address from the firmware environment */
> + initrd_start = fw_getenvl("initrd_start");
> + if (initrd_start) {
> + initrd_start = KSEG0ADDR(initrd_start);
> + initrd_end = initrd_start + fw_getenvl("initrd_size");
> + }
> +#endif
> +}
> +
> +void __init prom_free_prom_memory(void)
> +{
> +}
> diff --git a/arch/mips/ni169445/169445-int.c b/arch/mips/ni169445/169445-int.c
> new file mode 100644
> index 0000000..83caf79
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-int.c
> @@ -0,0 +1,34 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/irq.h>
> +#include <linux/of_irq.h>
> +#include <linux/irqchip/mips-gic.h>
> +#include <linux/io.h>
> +
> +#include <asm/irq_cpu.h>
> +#include <asm/setup.h>
> +
> +static const struct of_device_id of_irq_ids[] __initconst = {
> + {
> + .compatible = "mti,cpu-interrupt-controller",
> + .data = mips_cpu_irq_of_init
> + },
> + {},
> +};
> +
> +void __init arch_init_irq(void)
> +{
> + of_irq_init(of_irq_ids);
> +}
> +
> diff --git a/arch/mips/ni169445/169445-setup.c b/arch/mips/ni169445/169445-setup.c
> new file mode 100644
> index 0000000..80a5c91
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-setup.c
> @@ -0,0 +1,58 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +#include <linux/init.h>
> +#include <linux/clk-provider.h>
> +#include <linux/libfdt.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_fdt.h>
> +
> +#include <asm/prom.h>
> +#include <asm/fw/fw.h>
> +
> +#include <asm/mips-boards/generic.h>
> +
> +const char *get_system_type(void)
> +{
> + return "NI 169445 FPGA";
> +}
> +
> +void __init plat_mem_setup(void)
> +{
> + /*
> + * Load the builtin devicetree. This causes the chosen node to be
> + * parsed resulting in our memory appearing
> + */
> + __dt_setup_arch(__dtb_start);
> +}
> +
> +void __init device_tree_init(void)
> +{
> + if (!initial_boot_params)
> + return;
> +
> + unflatten_and_copy_device_tree();
> +}
> +
> +static int __init customize_machine(void)
> +{
> + of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
> + return 0;
> +}
> +arch_initcall(customize_machine);
> +
> +static int __init plat_dev_init(void)
> +{
> + of_clk_init(NULL);
> + return 0;
> +}
> +device_initcall(plat_dev_init);
> diff --git a/arch/mips/ni169445/169445-time.c b/arch/mips/ni169445/169445-time.c
> new file mode 100644
> index 0000000..3d2499e
> --- /dev/null
> +++ b/arch/mips/ni169445/169445-time.c
> @@ -0,0 +1,35 @@
> +/* Copyright 2016 National Instruments Corporation
> + *
> + * This program is free software; you can redistribute it and/or modify it
> + * under the terms of the GNU General Public License as published by the Free
> + * Software Foundation; either version 2 of the License, or (at your option)
> + * any later version.
> + *
> + * This program is distributed in the hope that it will be useful, but WITHOUT
> + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
> + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
> + * more details.
> + */
> +
> +#include <linux/init.h>
> +#include <linux/of.h>
> +
> +#include <asm/time.h>
> +
> +void __init plat_time_init(void)
> +{
> + struct device_node *np;
> + u32 freq;
> +
> + np = of_find_node_by_name(NULL, "cpus");
> + if (!np)
> + panic("missing 'cpus' DT node");
> + if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
> + panic("missing 'mips-hpt-frequency' property");
> + of_node_put(np);
> +
> + mips_hpt_frequency = freq;
> +
> + /* IRQs will not work until the timer has been set at least once */
> + write_c0_count(0);
> +}
> diff --git a/arch/mips/ni169445/Makefile b/arch/mips/ni169445/Makefile
> new file mode 100644
> index 0000000..f3a0c8c
> --- /dev/null
> +++ b/arch/mips/ni169445/Makefile
> @@ -0,0 +1,9 @@
> +#
> +#
> +obj-y := 169445-init.o \
> + 169445-int.o 169445-setup.o \
> + 169445-time.o
> +
> +obj-$(CONFIG_EARLY_PRINTK) += 169445-console.o
> +
> +CFLAGS_169445-setup.o = -I$(src)/../../../scripts/dtc/libfdt
> diff --git a/arch/mips/ni169445/Platform b/arch/mips/ni169445/Platform
> new file mode 100644
> index 0000000..9380312
> --- /dev/null
> +++ b/arch/mips/ni169445/Platform
> @@ -0,0 +1,6 @@
> +#
> +# National Instruments 169445 FPGA board
> +#
> +platform-$(CONFIG_NI_169445) += ni169445/
> +load-$(CONFIG_NI_169445) += 0xffffffff80002000
> +all-$(CONFIG_NI_169445) := $(COMPRESSION_FNAME).srec
>
^ permalink raw reply
* Re: [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Andre Przywara @ 2016-12-02 16:10 UTC (permalink / raw)
To: Icenowy Zheng, Hans de Goede, Maxime Ripard
Cc: Mark Rutland, devicetree@vger.kernel.org, Vishnu Patekar,
Arnd Bergmann, Jonathan Corbet, linux-doc@vger.kernel.org,
Russell King, linux-kernel@vger.kernel.org, Chen-Yu Tsai,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <11535601480689127@web2g.yandex.ru>
Hi,
On 02/12/16 14:32, Icenowy Zheng wrote:
>
>
> 02.12.2016, 22:30, "Hans de Goede" <hdegoede@redhat.com>:
>> Hi,
>>
>> On 02-12-16 15:22, Icenowy Zheng wrote:
>>> 01.12.2016, 17:36, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>>> On Mon, Nov 28, 2016 at 12:29:07AM +0000, André Przywara wrote:
>>>>> > Something more interesting happened.
>>>>> >
>>>>> > Xunlong made a add-on board for Orange Pi Zero, which exposes the
>>>>> > two USB Controllers exported at expansion bus as USB Type-A
>>>>> > connectors.
>>>>> >
>>>>> > Also it exposes a analog A/V jack and a microphone.
>>>>> >
>>>>> > Should I enable {e,o}hci{2.3} in the device tree?
>>>>>
>>>>> Actually we should do this regardless of this extension board. The USB
>>>>> pins are not multiplexed and are exposed on user accessible pins (just
>>>>> not soldered, but that's a detail), so I think they qualify for DT
>>>>> enablement. And even if a user can't use them, it doesn't hurt to have
>>>>> them (since they are not multiplexed).
>>>>
>>>> My main concern about this is that we'll leave regulators enabled by
>>>> default, for a minority of users. And that minority will prevent to do
>>>> a proper power management when the times come since we'll have to keep
>>>> that behaviour forever.
>>>
>>> I think these users can add a 'fdt set /xxx/xxx status "disabled" ' .
>>
>> I don't think that will be necessary I'm pretty sure these extra usb
>> ports do not have a regulator for the Vbus, they just hook directly
>> to the 5V rail, can someone with a schematic check ?
>
> We seems to have still no schematics for the add-on board.
From looking at the picture of that expansion board on the Aliexpress
page and chasing the tracks, there is clearly no voltage regulator on
there, it's just passive components. The 5V pin from the headers is
routed forth and back between the two layers via some vias directly to
the 5V pins of the USB sockets.
> But something is sure is that there's no any regulator-related pins
> on the add-on pinout. There's only USB DM and DP pins.
>
> So the Vbus must be directly connected to +5V.
So yes, it is.
But I think the question is moot anyways, since we don't provide DT
support for that add-on board at that point anyways.
One could imagine another board, though, which has regulators switched
by GPIOs, but that would be their problem and they would have regulators
specified in their specific DT snippet, then.
So to summarize:
- For that specific Orange Pi Zero board which we discuss the DT for
there is no regulator support for the additional USB ports. Thus nothing
we could turn off to save power.
- A user could just take these USB brackets with pin headers that are so
common in PCs to connect additional USB ports to the back of the box.
One just needs to re-sort the pins, which is a matter of a minute.
- As long as we don't provide any easy way of handling DT changes, we
should enable the USB ports for the sake of the users of either those
brackets or the expansion board. Any more sophisticated USB expansion
board with regulators would need to amend the DT anyway.
Does that make sense?
Cheers,
Andre.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* [PATCH] MIPS: NI 169445 board support
From: Nathan Sullivan @ 2016-12-02 15:42 UTC (permalink / raw)
To: ralf, mark.rutland, robh+dt
Cc: linux-mips, devicetree, linux-kernel, Nathan Sullivan
Support the National Instruments 169445 board.
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
---
"gpio: mmio: add support for NI 169445 NAND GPIO" and
"devicetree: add vendor prefix for National Instruments" are required for the
NAND on this board to work.
Documentation/devicetree/bindings/mips/ni.txt | 7 ++
arch/mips/Kbuild.platforms | 1 +
arch/mips/Kconfig | 26 ++++++
arch/mips/boot/dts/Makefile | 1 +
arch/mips/boot/dts/ni/169445.dts | 99 +++++++++++++++++++++
arch/mips/boot/dts/ni/Makefile | 9 ++
arch/mips/configs/ni169445_defconfig | 120 ++++++++++++++++++++++++++
arch/mips/ni169445/169445-console.c | 38 ++++++++
arch/mips/ni169445/169445-init.c | 39 +++++++++
arch/mips/ni169445/169445-int.c | 34 ++++++++
arch/mips/ni169445/169445-setup.c | 58 +++++++++++++
arch/mips/ni169445/169445-time.c | 35 ++++++++
arch/mips/ni169445/Makefile | 9 ++
arch/mips/ni169445/Platform | 6 ++
14 files changed, 482 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mips/ni.txt
create mode 100644 arch/mips/boot/dts/ni/169445.dts
create mode 100644 arch/mips/boot/dts/ni/Makefile
create mode 100644 arch/mips/configs/ni169445_defconfig
create mode 100644 arch/mips/ni169445/169445-console.c
create mode 100644 arch/mips/ni169445/169445-init.c
create mode 100644 arch/mips/ni169445/169445-int.c
create mode 100644 arch/mips/ni169445/169445-setup.c
create mode 100644 arch/mips/ni169445/169445-time.c
create mode 100644 arch/mips/ni169445/Makefile
create mode 100644 arch/mips/ni169445/Platform
diff --git a/Documentation/devicetree/bindings/mips/ni.txt b/Documentation/devicetree/bindings/mips/ni.txt
new file mode 100644
index 0000000..722bf2d
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/ni.txt
@@ -0,0 +1,7 @@
+National Instruments MIPS platforms
+
+required root node properties:
+ - compatible: must be "ni,169445"
+
+CPU Nodes
+ - compatible: must be "mti,mips14KEc"
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index f5f1bdb..f2d7b5c 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -20,6 +20,7 @@ platforms += loongson32
platforms += loongson64
platforms += mti-malta
platforms += netlogic
+platforms += ni169445
platforms += paravirt
platforms += pic32
platforms += pistachio
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b3c5bde..d24d11f 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -574,6 +574,32 @@ config NXP_STB225
help
Support for NXP Semiconductors STB225 Development Board.
+config NI_169445
+ bool "NI 169445 board"
+ select ARCH_WANT_OPTIONAL_GPIOLIB
+ select BOOT_ELF32
+ select BOOT_RAW
+ select BUILTIN_DTB
+ select CEVT_R4K
+ select CSRC_R4K
+ select CPU_MIPSR2_IRQ_VI
+ select CPU_MIPSR2_IRQ_EI
+ select DMA_NONCOHERENT
+ select IRQ_MIPS_CPU
+ select LIBFDT
+ select MIPS_MSC
+ select SYS_HAS_CPU_MIPS32_R1
+ select SYS_HAS_CPU_MIPS32_R2
+ select SYS_HAS_EARLY_PRINTK
+ select SYS_SUPPORTS_32BIT_KERNEL
+ select SYS_SUPPORTS_LITTLE_ENDIAN
+ select USE_OF
+ select COMMON_CLK
+ help
+ This enables support for the National Instruments 169445A
+ board.
+
+
config PMC_MSP
bool "PMC-Sierra MSP chipsets"
select CEVT_R4K
diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile
index fc7a0a9..65a0ad8 100644
--- a/arch/mips/boot/dts/Makefile
+++ b/arch/mips/boot/dts/Makefile
@@ -3,6 +3,7 @@ dts-dirs += cavium-octeon
dts-dirs += ingenic
dts-dirs += lantiq
dts-dirs += mti
+dts-dirs += ni
dts-dirs += netlogic
dts-dirs += pic32
dts-dirs += qca
diff --git a/arch/mips/boot/dts/ni/169445.dts b/arch/mips/boot/dts/ni/169445.dts
new file mode 100644
index 0000000..a2b49f9
--- /dev/null
+++ b/arch/mips/boot/dts/ni/169445.dts
@@ -0,0 +1,99 @@
+/dts-v1/;
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "ni,169445";
+
+ cpus {
+ mips-hpt-frequency = <25000000>;
+
+ cpu@0 {
+ compatible = "mti,mips14KEc";
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x0 0x08000000>;
+ };
+
+ clocks {
+ baseclk: baseclock {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <50000000>;
+ };
+ };
+
+ cpu_intc: cpu_intc {
+ #address-cells = <0>;
+ compatible = "mti,cpu-interrupt-controller";
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+
+ ahb@0 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ gpio1: nand-gpio-out@1f300010 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x1f300010 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <5>;
+ };
+
+ gpio2: nand-gpio-in@1f300014 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x1f300014 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <1>;
+ };
+
+ nand@1f300000 {
+ compatible = "gpio-control-nand";
+ nand-on-flash-bbt;
+ nand-ecc-mode = "soft_bch";
+ nand-ecc-step-size = <512>;
+ nand-ecc-strength = <4>;
+ reg = <0x1f300000 4>;
+ gpios = <&gpio2 0 0>, /* rdy */
+ <&gpio1 1 0>, /* nce */
+ <&gpio1 2 0>, /* ale */
+ <&gpio1 3 0>, /* cle */
+ <&gpio1 4 0>; /* nwp */
+ };
+
+ serial@1f380000 {
+ compatible = "ns16550a";
+ reg = <0x1f380000 0x1000>;
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <6>;
+ clocks = <&baseclk>;
+ reg-shift = <0>;
+ };
+
+ ethernet@1f340000 {
+ compatible = "snps,dwc-qos-ethernet-4.10";
+ interrupt-parent = <&cpu_intc>;
+ interrupts = <5>;
+ reg = <0x1f340000 0x2000>;
+ clock-names = "apb_pclk", "phy_ref_clk";
+ clocks = <&baseclk>, <&baseclk>;
+
+ phy-mode = "rgmii";
+
+ fixed-link {
+ speed = <1000>;
+ full-duplex;
+ };
+ };
+ };
+};
diff --git a/arch/mips/boot/dts/ni/Makefile b/arch/mips/boot/dts/ni/Makefile
new file mode 100644
index 0000000..5291c18
--- /dev/null
+++ b/arch/mips/boot/dts/ni/Makefile
@@ -0,0 +1,9 @@
+dtb-$(CONFIG_NI_169445) += 169445.dtb
+
+obj-y += $(patsubst %.dtb, %.dtb.o, $(dtb-y))
+
+# Force kbuild to make empty built-in.o if necessary
+obj- += dummy.o
+
+always := $(dtb-y)
+clean-files := *.dtb *.dtb.S
diff --git a/arch/mips/configs/ni169445_defconfig b/arch/mips/configs/ni169445_defconfig
new file mode 100644
index 0000000..e5a34df
--- /dev/null
+++ b/arch/mips/configs/ni169445_defconfig
@@ -0,0 +1,120 @@
+CONFIG_NI_169445=y
+CONFIG_CPU_MIPS32_R2=y
+CONFIG_HZ_100=y
+CONFIG_MIPS_CMDLINE_FROM_BOOTLOADER=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_HZ_PERIODIC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_LOG_BUF_SHIFT=15
+CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_GZIP is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_SHMEM is not set
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_PROFILING=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_SUSPEND is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+CONFIG_NETFILTER=y
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP6_NF_IPTABLES=y
+CONFIG_IP6_NF_FILTER=y
+# CONFIG_WIRELESS is not set
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK_RO=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_GPIO=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_AMAZON is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_EZCHIP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NETRONOME is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_RENESAS is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+CONFIG_SYNOPSYS_DWC_ETH_QOS=y
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_NET_VENDOR_XILINX is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_LEGACY_PTY_COUNT=32
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=2
+CONFIG_SERIAL_8250_RUNTIME_UARTS=2
+CONFIG_SERIAL_OF_PLATFORM=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+# CONFIG_HID is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_MIPS_PLATFORM_DEVICES is not set
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_UBIFS_FS=y
+CONFIG_UBIFS_FS_ADVANCED_COMPR=y
+# CONFIG_UBIFS_FS_ZLIB is not set
+CONFIG_SQUASHFS=y
+# CONFIG_SQUASHFS_ZLIB is not set
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+# CONFIG_NETWORK_FILESYSTEMS is not set
+# CONFIG_FTRACE is not set
+CONFIG_CRYPTO_CBC=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_ARC4=y
+# CONFIG_CRYPTO_HW is not set
+# CONFIG_XZ_DEC_X86 is not set
+# CONFIG_XZ_DEC_POWERPC is not set
+# CONFIG_XZ_DEC_IA64 is not set
+# CONFIG_XZ_DEC_ARM is not set
+# CONFIG_XZ_DEC_ARMTHUMB is not set
+# CONFIG_XZ_DEC_SPARC is not set
diff --git a/arch/mips/ni169445/169445-console.c b/arch/mips/ni169445/169445-console.c
new file mode 100644
index 0000000..f07e48b
--- /dev/null
+++ b/arch/mips/ni169445/169445-console.c
@@ -0,0 +1,38 @@
+/* Copyright 2016 National Instruments Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+#include <linux/init.h>
+#include <linux/console.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+
+#define NI_UART0_REGS_BASE ((unsigned char __iomem *)0xbf380000)
+
+static inline unsigned char serial_in(int offset)
+{
+ return __raw_readb(NI_UART0_REGS_BASE + offset);
+}
+
+static inline void serial_out(int offset, char value)
+{
+ __raw_writeb(value, NI_UART0_REGS_BASE + offset);
+}
+
+int prom_putchar(char c)
+{
+ while ((serial_in(UART_LSR) & UART_LSR_THRE) == 0)
+ ;
+
+ serial_out(UART_TX, c);
+
+ return 1;
+}
diff --git a/arch/mips/ni169445/169445-init.c b/arch/mips/ni169445/169445-init.c
new file mode 100644
index 0000000..5c7ff5e
--- /dev/null
+++ b/arch/mips/ni169445/169445-init.c
@@ -0,0 +1,39 @@
+/* Copyright 2016 National Instruments Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+#include <linux/init.h>
+#include <linux/initrd.h>
+#include <linux/io.h>
+
+#include <asm/bootinfo.h>
+#include <asm/cacheflush.h>
+#include <asm/traps.h>
+#include <asm/mips-boards/generic.h>
+#include <asm/fw/fw.h>
+
+void __init prom_init(void)
+{
+ fw_init_cmdline();
+
+#ifdef CONFIG_BLK_DEV_INITRD
+ /* Read the initrd address from the firmware environment */
+ initrd_start = fw_getenvl("initrd_start");
+ if (initrd_start) {
+ initrd_start = KSEG0ADDR(initrd_start);
+ initrd_end = initrd_start + fw_getenvl("initrd_size");
+ }
+#endif
+}
+
+void __init prom_free_prom_memory(void)
+{
+}
diff --git a/arch/mips/ni169445/169445-int.c b/arch/mips/ni169445/169445-int.c
new file mode 100644
index 0000000..83caf79
--- /dev/null
+++ b/arch/mips/ni169445/169445-int.c
@@ -0,0 +1,34 @@
+/* Copyright 2016 National Instruments Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/of_irq.h>
+#include <linux/irqchip/mips-gic.h>
+#include <linux/io.h>
+
+#include <asm/irq_cpu.h>
+#include <asm/setup.h>
+
+static const struct of_device_id of_irq_ids[] __initconst = {
+ {
+ .compatible = "mti,cpu-interrupt-controller",
+ .data = mips_cpu_irq_of_init
+ },
+ {},
+};
+
+void __init arch_init_irq(void)
+{
+ of_irq_init(of_irq_ids);
+}
+
diff --git a/arch/mips/ni169445/169445-setup.c b/arch/mips/ni169445/169445-setup.c
new file mode 100644
index 0000000..80a5c91
--- /dev/null
+++ b/arch/mips/ni169445/169445-setup.c
@@ -0,0 +1,58 @@
+/* Copyright 2016 National Instruments Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+#include <linux/init.h>
+#include <linux/clk-provider.h>
+#include <linux/libfdt.h>
+#include <linux/of_platform.h>
+#include <linux/of_fdt.h>
+
+#include <asm/prom.h>
+#include <asm/fw/fw.h>
+
+#include <asm/mips-boards/generic.h>
+
+const char *get_system_type(void)
+{
+ return "NI 169445 FPGA";
+}
+
+void __init plat_mem_setup(void)
+{
+ /*
+ * Load the builtin devicetree. This causes the chosen node to be
+ * parsed resulting in our memory appearing
+ */
+ __dt_setup_arch(__dtb_start);
+}
+
+void __init device_tree_init(void)
+{
+ if (!initial_boot_params)
+ return;
+
+ unflatten_and_copy_device_tree();
+}
+
+static int __init customize_machine(void)
+{
+ of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ return 0;
+}
+arch_initcall(customize_machine);
+
+static int __init plat_dev_init(void)
+{
+ of_clk_init(NULL);
+ return 0;
+}
+device_initcall(plat_dev_init);
diff --git a/arch/mips/ni169445/169445-time.c b/arch/mips/ni169445/169445-time.c
new file mode 100644
index 0000000..3d2499e
--- /dev/null
+++ b/arch/mips/ni169445/169445-time.c
@@ -0,0 +1,35 @@
+/* Copyright 2016 National Instruments Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/init.h>
+#include <linux/of.h>
+
+#include <asm/time.h>
+
+void __init plat_time_init(void)
+{
+ struct device_node *np;
+ u32 freq;
+
+ np = of_find_node_by_name(NULL, "cpus");
+ if (!np)
+ panic("missing 'cpus' DT node");
+ if (of_property_read_u32(np, "mips-hpt-frequency", &freq) < 0)
+ panic("missing 'mips-hpt-frequency' property");
+ of_node_put(np);
+
+ mips_hpt_frequency = freq;
+
+ /* IRQs will not work until the timer has been set at least once */
+ write_c0_count(0);
+}
diff --git a/arch/mips/ni169445/Makefile b/arch/mips/ni169445/Makefile
new file mode 100644
index 0000000..f3a0c8c
--- /dev/null
+++ b/arch/mips/ni169445/Makefile
@@ -0,0 +1,9 @@
+#
+#
+obj-y := 169445-init.o \
+ 169445-int.o 169445-setup.o \
+ 169445-time.o
+
+obj-$(CONFIG_EARLY_PRINTK) += 169445-console.o
+
+CFLAGS_169445-setup.o = -I$(src)/../../../scripts/dtc/libfdt
diff --git a/arch/mips/ni169445/Platform b/arch/mips/ni169445/Platform
new file mode 100644
index 0000000..9380312
--- /dev/null
+++ b/arch/mips/ni169445/Platform
@@ -0,0 +1,6 @@
+#
+# National Instruments 169445 FPGA board
+#
+platform-$(CONFIG_NI_169445) += ni169445/
+load-$(CONFIG_NI_169445) += 0xffffffff80002000
+all-$(CONFIG_NI_169445) := $(COMPRESSION_FNAME).srec
--
2.1.4
^ permalink raw reply related
* [PATCH] gpio: mmio: add support for NI 169445 NAND GPIO
From: Nathan Sullivan @ 2016-12-02 15:37 UTC (permalink / raw)
To: linus.walleij, gnurou, robh+dt, mark.rutland
Cc: devicetree, linux-kernel, linux-gpio, Nathan Sullivan
The GPIO-based NAND controller on National Instruments 169445 hardware
exposes a set of simple lines for the control signals.
Signed-off-by: Nathan Sullivan <nathan.sullivan@ni.com>
---
"devicetree: add vendor prefix for National Instruments" added the ni vendor prefix.
This patch is needed for "MIPS: NI 169445 board support", so that GPIO NAND can work.
.../bindings/gpio/ni,169445-nand-gpio.txt | 36 ++++++++++++++++++++++
drivers/gpio/gpio-mmio.c | 1 +
2 files changed, 37 insertions(+)
create mode 100644 Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
diff --git a/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
new file mode 100644
index 0000000..ca2c14f
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/ni,169445-nand-gpio.txt
@@ -0,0 +1,36 @@
+Bindings for the National Instruments 169445 GPIO NAND controller
+
+The 169445 GPIO NAND controller has two memory mapped GPIO registers, one
+for input (the ready signal) and one for output (control signals). It is
+intended to be used with the GPIO NAND driver.
+
+Required properties:
+ - compatible: should be "ni,169445-nand-gpio"
+ - reg-names: must contain
+ "dat" - data register
+ - reg: address + size pairs describing the GPIO register sets;
+ order must correspond with the order of entries in reg-names
+ - #gpio-cells: must be set to 2. The first cell is the pin number and
+ the second cell is used to specify the gpio polarity:
+ 0 = active high
+ 1 = active low
+ - gpio-controller: Marks the device node as a gpio controller.
+
+Examples:
+ gpio1: nand-gpio-out@1f300010 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x1f300010 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <5>;
+ };
+
+ gpio2: nand-gpio-in@1f300014 {
+ compatible = "ni,169445-nand-gpio";
+ reg = <0x1f300014 0x4>;
+ reg-names = "dat";
+ gpio-controller;
+ #gpio-cells = <2>;
+ ngpios = <1>;
+ };
diff --git a/drivers/gpio/gpio-mmio.c b/drivers/gpio/gpio-mmio.c
index d7d03ad..f7da40e 100644
--- a/drivers/gpio/gpio-mmio.c
+++ b/drivers/gpio/gpio-mmio.c
@@ -575,6 +575,7 @@ static void __iomem *bgpio_map(struct platform_device *pdev,
static const struct of_device_id bgpio_of_match[] = {
{ .compatible = "brcm,bcm6345-gpio" },
{ .compatible = "wd,mbl-gpio" },
+ { .compatible = "ni,169445-nand-gpio" },
{ }
};
MODULE_DEVICE_TABLE(of, bgpio_of_match);
--
2.1.4
^ permalink raw reply related
* [PATCH] devicetree: add vendor prefix for National Instruments
From: Nathan Sullivan @ 2016-12-02 15:31 UTC (permalink / raw)
To: mark.rutland-5wv7dgnIgG8, robh+dt-DgEjT+Ai2ygdnm+yROfE0A
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Nathan Sullivan
Signed-off-by: Nathan Sullivan <nathan.sullivan-acOepvfBmUk@public.gmane.org>
---
This is required by "gpio: mmio: add support for NI 169445 NAND GPIO"
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index f0a48ea..d37df5f 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -187,6 +187,7 @@ netgear NETGEAR
netlogic Broadcom Corporation (formerly NetLogic Microsystems)
netxeon Shenzhen Netxeon Technology CO., LTD
newhaven Newhaven Display International
+ni National Instruments
nintendo Nintendo
nokia Nokia
nuvoton Nuvoton Technology Corporation
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/2] arm: dts: sun8i: reuse the uart1 node of iNet D978 rev2 board
From: Icenowy Zheng @ 2016-12-02 15:19 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Hans de Goede
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In-Reply-To: <20161202151913.38892-1-icenowy-ymACFijhrKM@public.gmane.org>
As a uart1 node is added into sun8i-reference-design-tablet.dtsi, simply
use it in iNet D978 rev2 device tree.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
index fb46655..7335461 100644
--- a/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
+++ b/arch/arm/boot/dts/sun8i-a33-inet-d978-rev2.dts
@@ -49,15 +49,6 @@
model = "INet-D978 Rev 02";
compatible = "primux,inet-d978-rev2", "allwinner,sun8i-a33";
- aliases {
- serial0 = &uart1;
- };
-
- chosen {
- /* Delete debug UART as serial0 is the UART for bluetooth */
- /delete-property/stdout-path;
- };
-
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
@@ -96,13 +87,6 @@
};
};
-&r_uart {
- status = "disabled";
-};
-
&uart1 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart1_pins_a>,
- <&uart1_pins_cts_rts_a>;
status = "okay";
};
--
2.10.2
^ permalink raw reply related
* [PATCH 1/2] arm: dts: sun8i: add uart1 node to reference design tablet
From: Icenowy Zheng @ 2016-12-02 15:19 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Hans de Goede
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In the A23/A33 tablet reference design, the UART1 at PG is used to
connect to the UART-connected bluetooth.
Add a disabled uart1 node for it in the reference design tablet dtsi,
contains the pinctrl info.
If a tablet uses the UART bluetooth, simply set the status of this node
to "okay".
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
index 08cd001..2d9cf0d 100644
--- a/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
+++ b/arch/arm/boot/dts/sun8i-reference-design-tablet.dtsi
@@ -46,6 +46,7 @@
/ {
aliases {
serial0 = &r_uart;
+ serial1 = &uart1;
};
backlight: backlight {
@@ -223,6 +224,13 @@
vcc-lcd-supply = <®_dc1sw>;
};
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins_a>,
+ <&uart1_pins_cts_rts_a>;
+ status = "disabled";
+};
+
&usb_otg {
dr_mode = "otg";
status = "okay";
--
2.10.2
^ permalink raw reply related
* [PATCH v3 -next 2/2] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Icenowy Zheng @ 2016-12-02 15:05 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring, Russell King,
Andre Przywara, Hans de Goede, Arnd Bergmann, Vishnu Patekar
Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
In-Reply-To: <20161202150513.34691-1-icenowy-ymACFijhrKM@public.gmane.org>
Orange Pi Zero is a board that came with the new Allwinner H2+ SoC and a
SDIO Wi-Fi chip by Allwinner (XR819).
Add a device tree file for it.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes since v2:
- Merged SDIO Wi-Fi patch into it.
- SDIO Wi-Fi: add a ethernet1 alias to it, as it has no internal NVRAM.
- SDIO Wi-Fi: changed pinctrl binding to generic pinconf
- removed all gpio pinctrl nodes
- changed h2plus to h2-plus
Changes since v1:
- Convert to generic pinconf bindings.
- SDIO Wi-Fi: add patch.
Some notes:
- The uart1 and uart2 is available on the unsoldered gpio header.
- The onboard USB connector has its Vbus directly connected to DCIN-5V (the
power jack)
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 159 ++++++++++++++++++++++
2 files changed, 160 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 6447abc..59f6e86 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -844,6 +844,7 @@ dtb-$(CONFIG_MACH_SUN8I) += \
sun8i-a33-sinlinx-sina33.dtb \
sun8i-a83t-allwinner-h8homlet-v2.dtb \
sun8i-a83t-cubietruck-plus.dtb \
+ sun8i-h2-plus-orangepi-zero.dtb \
sun8i-h3-bananapi-m2-plus.dtb \
sun8i-h3-nanopi-neo.dtb \
sun8i-h3-orangepi-2.dtb \
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
new file mode 100644
index 0000000..d18807f
--- /dev/null
+++ b/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
@@ -0,0 +1,159 @@
+/*
+ * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
+ *
+ * Based on sun8i-h3-orangepi-one.dts, which is:
+ * Copyright (C) 2016 Hans de Goede <hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "sun8i-h3.dtsi"
+#include "sunxi-common-regulators.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/pinctrl/sun4i-a10.h>
+
+/ {
+ model = "Xunlong Orange Pi Zero";
+ compatible = "xunlong,orangepi-zero", "allwinner,sun8i-h2-plus";
+
+ aliases {
+ serial0 = &uart0;
+ /* ethernet0 is the H3 emac, defined in sun8i-h3.dtsi */
+ ethernet1 = &xr819;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ pwr_led {
+ label = "orangepi:green:pwr";
+ gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
+ default-state = "on";
+ };
+
+ status_led {
+ label = "orangepi:red:status";
+ gpios = <&pio 0 17 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ reg_vcc_wifi: reg_vcc_wifi {
+ compatible = "regulator-fixed";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc-wifi";
+ enable-active-high;
+ gpio = <&pio 0 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ wifi_pwrseq: wifi_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&r_pio 0 7 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&ehci1 {
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_a>;
+ vmmc-supply = <®_vcc3v3>;
+ bus-width = <4>;
+ cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
+ cd-inverted;
+ status = "okay";
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_a>;
+ vmmc-supply = <®_vcc_wifi>;
+ mmc-pwrseq = <&wifi_pwrseq>;
+ bus-width = <4>;
+ non-removable;
+ status = "okay";
+
+ /*
+ * Explicitly define the sdio device, so that we can add an ethernet
+ * alias for it (which e.g. makes u-boot set a mac-address).
+ */
+ xr819: sdio_wifi@1 {
+ reg = <1>;
+ };
+};
+
+&mmc1_pins_a {
+ bias-pull-up;
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins_a>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1_pins>;
+ status = "disabled";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart2_pins>;
+ status = "disabled";
+};
+
+&usbphy {
+ /* USB VBUS is always on */
+ status = "okay";
+};
--
2.10.2
^ permalink raw reply related
* [PATCH v3 -next 1/2] ARM: sunxi: add support for H2+ SoC
From: Icenowy Zheng @ 2016-12-02 15:05 UTC (permalink / raw)
To: Maxime Ripard, Chen-Yu Tsai, Rob Herring, Russell King,
Andre Przywara, Hans de Goede, Arnd Bergmann, Vishnu Patekar
Cc: linux-doc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Icenowy Zheng
Allwinner H2+ is a quad-core Cortex-A7 SoC.
It is very like H3, that they share the same SoC ID (0x1680), and H3
memory maps as well as drivers works well on the SoC.
Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
---
Changes since v2:
- Changed compatible from allwinner,sun8i-h2plus to allwinner,sun8i-h2-plus.
Documentation/arm/sunxi/README | 4 ++++
Documentation/devicetree/bindings/arm/sunxi.txt | 1 +
arch/arm/mach-sunxi/sunxi.c | 1 +
3 files changed, 6 insertions(+)
diff --git a/Documentation/arm/sunxi/README b/Documentation/arm/sunxi/README
index cd02433..1fe4d99c 100644
--- a/Documentation/arm/sunxi/README
+++ b/Documentation/arm/sunxi/README
@@ -63,6 +63,10 @@ SunXi family
+ User Manual
http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
+ - Allwinner H2+ (sun8i)
+ + No document available now, but is known to be working properly with
+ H3 drivers and memory map.
+
- Allwinner H3 (sun8i)
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
diff --git a/Documentation/devicetree/bindings/arm/sunxi.txt b/Documentation/devicetree/bindings/arm/sunxi.txt
index 4d6467c..59b143f 100644
--- a/Documentation/devicetree/bindings/arm/sunxi.txt
+++ b/Documentation/devicetree/bindings/arm/sunxi.txt
@@ -13,6 +13,7 @@ using one of the following compatible strings:
allwinner,sun8i-a33
allwinner,sun8i-a83t
allwinner,sun8i-h3
+ allwinner,sun8i-h2-plus
allwinner,sun9i-a80
allwinner,sun50i-a64
nextthing,gr8
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 2e2bde2..320d2af 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -63,6 +63,7 @@ static const char * const sun8i_board_dt_compat[] = {
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
"allwinner,sun8i-a83t",
+ "allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
NULL,
};
--
2.10.2
^ permalink raw reply related
* Re: [PATCH v4 i2c/for-next] i2c: rcar: Add per-Generation fallback bindings
From: Geert Uytterhoeven @ 2016-12-02 14:59 UTC (permalink / raw)
To: Simon Horman
Cc: Wolfram Sang, Magnus Damm, Linux I2C, Linux-Renesas, Rob Herring,
devicetree@vger.kernel.org
In-Reply-To: <1480688736-7175-1-git-send-email-horms+renesas@verge.net.au>
On Fri, Dec 2, 2016 at 3:25 PM, Simon Horman <horms+renesas@verge.net.au> wrote:
> In the case of Renesas R-Car hardware we know that there are generations of
> SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the
> relationship between IP blocks might be. For example, I believe that
> r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
> descendant of the former or vice versa.
>
> We can, however, by examining the documentation and behaviour of the
> hardware at run-time observe that the current driver implementation appears
> to be compatible with the IP blocks on SoCs within a given generation.
>
> For the above reasons and convenience when enabling new SoCs a
> per-generation fallback compatibility string scheme is being adopted for
> drivers for Renesas SoCs.
>
> Also:
> * Deprecate renesas,i2c-rcar. It seems poorly named as it is only
> compatible with R-Car Gen 1. It also appears unused in mainline.
> * Add some text to describe per-SoC bindings
>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> --- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
> +++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
> + "renesas,i2c-r8a7779" if the device is a part of a R8A7797 SoC.
R8A7779
Sorry for not noticing before.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH v2 2/3 pci/next] PCI: rcar: Use gen2 fallback compatibility last
From: Geert Uytterhoeven @ 2016-12-02 14:53 UTC (permalink / raw)
To: Simon Horman
Cc: Bjorn Helgaas, Phil Edworthy, Magnus Damm, linux-pci,
Linux-Renesas, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1480675020-26346-3-git-send-email-horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
On Fri, Dec 2, 2016 at 11:36 AM, Simon Horman
<horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org> wrote:
> Fallback compatibility strings should be used only if more specific ones
> are matched and the order of compatibility strings in the corresponding
> struct of_device_id should implement this.
>
> This does not have a run-time effect as current all relevant compatibility
> strings result in the same initialisation.
>
> Signed-off-by: Simon Horman <horms+renesas-/R6kz+dDXgpPR4JQBCEnsQ@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH] of: fix the error message handling
From: Gary Bisson @ 2016-12-02 14:50 UTC (permalink / raw)
To: pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Gary Bisson
The previous patch to add back an error message didn't take the
successful case into account. This results in the following trace
showing when a symbol is properly resolved:
OF: resolver: overlay phandle fixup failed: 0
So remove the 'err_out' label and test 'err' value in the 'out' label
before printing the error message.
Signed-off-by: Gary Bisson <gary.bisson-Q5RJGjKts06CY9SHAMCTRUEOCMrvLtNR@public.gmane.org>
---
Hi all,
While experimenting with dt-overlays on linux-next I've realized that
a new trace was showing up:
OF: resolver: overlay phandle fixup failed: 0
This patch should fix it in a simple way.
Regards,
Gary
---
drivers/of/resolver.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
index 783bd09..034a61c 100644
--- a/drivers/of/resolver.c
+++ b/drivers/of/resolver.c
@@ -298,12 +298,12 @@ int of_resolve_phandles(struct device_node *overlay)
if (!overlay) {
pr_err("null overlay\n");
err = -EINVAL;
- goto err_out;
+ goto out;
}
if (!of_node_check_flag(overlay, OF_DETACHED)) {
pr_err("overlay not detached\n");
err = -EINVAL;
- goto err_out;
+ goto out;
}
phandle_delta = live_tree_max_phandle() + 1;
@@ -315,7 +315,7 @@ int of_resolve_phandles(struct device_node *overlay)
err = adjust_local_phandle_references(local_fixups, overlay, phandle_delta);
if (err)
- goto err_out;
+ goto out;
overlay_fixups = NULL;
@@ -333,7 +333,7 @@ int of_resolve_phandles(struct device_node *overlay)
if (!tree_symbols) {
pr_err("no symbols in root of device tree.\n");
err = -EINVAL;
- goto err_out;
+ goto out;
}
for_each_property_of_node(overlay_fixups, prop) {
@@ -345,12 +345,12 @@ int of_resolve_phandles(struct device_node *overlay)
err = of_property_read_string(tree_symbols,
prop->name, &refpath);
if (err)
- goto err_out;
+ goto out;
refnode = of_find_node_by_path(refpath);
if (!refnode) {
err = -ENOENT;
- goto err_out;
+ goto out;
}
phandle = refnode->phandle;
@@ -361,9 +361,10 @@ int of_resolve_phandles(struct device_node *overlay)
break;
}
-err_out:
- pr_err("overlay phandle fixup failed: %d\n", err);
out:
+ if (err)
+ pr_err("overlay phandle fixup failed: %d\n", err);
+
of_node_put(tree_symbols);
return err;
--
2.9.3
--
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^ permalink raw reply related
* [PATCH 3/3] nvmem: imx-ocotp: Fix wrong register size
From: Daniel Schultz @ 2016-12-02 14:45 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel, fabio.estevam, devicetree, linux-arm-kernel
In-Reply-To: <1480689949-17957-1-git-send-email-d.schultz@phytec.de>
All i.MX6 SoCs have an OCOTP Controller with 4kbit fuses. The i.MX6SL is
an exception and has only 2kbit fuses.
In the TRM for the i.MX6DQ (IMX6QDRM - Rev 2, 06/2014) the fuses size is
described in chapter 46.1.1 with:
"32-bit word restricted program and read to 4Kbits of eFuse OTP(512x8)."
In the TRM for the i.MX6SL (IMX6SLRM - Rev 2, 06/2015) the fuses size is
described in chapter 34.1.1 with:
"32-bit word restricted program and read to 2 kbit of eFuse OTP(128x8)."
Since the Freescale Linux kernel OCOTP driver works with a fuses size of
2 kbit for the i.MX6SL, it looks like the TRM is wrong and the formula
to calculate the correct fuses size has to be 256x8.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
drivers/nvmem/imx-ocotp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index d2f78d3..8482c53 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -72,7 +72,7 @@ static int imx_ocotp_read(void *context, unsigned int offset,
static const struct of_device_id imx_ocotp_dt_ids[] = {
{ .compatible = "fsl,imx6q-ocotp", (void *)128 },
{ .compatible = "fsl,imx6ul-ocotp", (void *)128 },
- { .compatible = "fsl,imx6sl-ocotp", (void *)32 },
+ { .compatible = "fsl,imx6sl-ocotp", (void *)64 },
{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
{ },
};
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] ARM: dts: imx6ul: Add OCOTP node
From: Daniel Schultz @ 2016-12-02 14:45 UTC (permalink / raw)
To: srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A,
maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1480689949-17957-1-git-send-email-d.schultz-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
This device node adds OCOTP for the i.MX6UL SoC.
Signed-off-by: Daniel Schultz <d.schultz-guT5V/WYfQezQB+pC5nmwQ@public.gmane.org>
---
arch/arm/boot/dts/imx6ul.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index c5c05fd..ee53795 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -849,6 +849,12 @@
reg = <0x021b0000 0x4000>;
};
+ ocotp: ocotp@021bc000 {
+ compatible = "fsl,imx6ul-ocotp";
+ reg = <0x021bc000 0x4000>;
+ clocks = <&clks IMX6UL_CLK_OCOTP>;
+ };
+
lcdif: lcdif@021c8000 {
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
reg = <0x021c8000 0x4000>;
--
1.9.1
--
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^ permalink raw reply related
* [PATCH 1/3] nvmem: imx-ocotp: Add support for i.MX6UL
From: Daniel Schultz @ 2016-12-02 14:45 UTC (permalink / raw)
To: srinivas.kandagatla, maxime.ripard, robh+dt, mark.rutland,
shawnguo, kernel, fabio.estevam, devicetree, linux-arm-kernel
This patch adds OCOTP support for the i.MX6UL SoC.
Signed-off-by: Daniel Schultz <d.schultz@phytec.de>
---
Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 5 +++--
drivers/nvmem/imx-ocotp.c | 1 +
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
index 383d588..fcb1a48 100644
--- a/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
+++ b/Documentation/devicetree/bindings/nvmem/imx-ocotp.txt
@@ -1,13 +1,14 @@
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
This binding represents the on-chip eFuse OTP controller found on
-i.MX6Q/D, i.MX6DL/S, i.MX6SL, and i.MX6SX SoCs.
+i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX and i.MX6UL SoCs.
Required properties:
- compatible: should be one of
"fsl,imx6q-ocotp" (i.MX6Q/D/DL/S),
"fsl,imx6sl-ocotp" (i.MX6SL), or
- "fsl,imx6sx-ocotp" (i.MX6SX), followed by "syscon".
+ "fsl,imx6sx-ocotp" (i.MX6SX), or
+ "fsl,imx6ul-ocotp" (i.MX6UL), followed by "syscon".
- reg: Should contain the register base and length.
- clocks: Should contain a phandle pointing to the gated peripheral clock.
diff --git a/drivers/nvmem/imx-ocotp.c b/drivers/nvmem/imx-ocotp.c
index ac27b9b..d2f78d3 100644
--- a/drivers/nvmem/imx-ocotp.c
+++ b/drivers/nvmem/imx-ocotp.c
@@ -71,6 +71,7 @@ static int imx_ocotp_read(void *context, unsigned int offset,
static const struct of_device_id imx_ocotp_dt_ids[] = {
{ .compatible = "fsl,imx6q-ocotp", (void *)128 },
+ { .compatible = "fsl,imx6ul-ocotp", (void *)128 },
{ .compatible = "fsl,imx6sl-ocotp", (void *)32 },
{ .compatible = "fsl,imx6sx-ocotp", (void *)128 },
{ },
--
1.9.1
^ permalink raw reply related
* [PATCH] ARM: dts: imx6q-utilite-pro: enable 2nd display pipeline
From: christopher.spinrath-vA1bhqPz9FBZXbeN9DUtxg @ 2016-12-02 14:37 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
grinberg-UTxiZqZC01RS1MOuV/RT9w, fabio.estevam-3arQi8VN3Tc,
christopher.spinrath-vA1bhqPz9FBZXbeN9DUtxg,
p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
From: Christopher Spinrath <christopher.spinrath-vA1bhqPz9FBZXbeN9DUtxg@public.gmane.org>
Apart from the already enabled Designware HDMI port, the Utilite Pro
has a second display pipeline which has the following shape:
IPU1 DI0 --> Parallel display --> tfp410 rgb24 to DVI encoder
--> HDMI connector.
Enable support for it.
In addition, since this pipeline is hardwired to IPU1, sever the link
between IPU1 and the SoC-internal Designware HDMI encoder forcing the
latter to be connected to IPU2 instead of IPU1. Otherwise, it is not
possible to drive both displays at high resolution due to the bandwidth
limitations of a single IPU.
Signed-off-by: Christopher Spinrath <christopher.spinrath-vA1bhqPz9FBZXbeN9DUtxg@public.gmane.org>
---
Hi all,
the removal of the link between IPU1 and the Designware HDMI encoder is the
result of a discussion I had with Philipp Zabel:
https://lists.freedesktop.org/archives/dri-devel/2016-November/125399.html .
Altough it is not possible to connect anything else to IPU1 on the Utilite, this
approach has at least one disadvantage: if the resolution is low enough such
that a single IPU can handle both displays then muxing both displays to IPU1
would reduce the power consumption.
However, IMHO omitting the link IPU1 <--> DW HDMI is still the preferrable
solution since I'm not aware of any OS/driver that is capable of switching IPUs
or can handle the bandwidth limitation in a sane way. In particular, Linux is
unusable when both displays are supposed to be driven at high resolution and
both muxing options for the DW HDMI are available (this is not a userspace
issue; the system becomes almost unresponsive as soon as the kernel sets the
initial resolution).
Cheers,
Christopher
P.S.: this patch depends on the tfp410 bridge driver which has recently been
merged into drm-next.
arch/arm/boot/dts/imx6q-utilite-pro.dts | 115 ++++++++++++++++++++++++++++++++
1 file changed, 115 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-utilite-pro.dts b/arch/arm/boot/dts/imx6q-utilite-pro.dts
index 2200994..69bdd82 100644
--- a/arch/arm/boot/dts/imx6q-utilite-pro.dts
+++ b/arch/arm/boot/dts/imx6q-utilite-pro.dts
@@ -59,6 +59,33 @@
rtc1 = &snvs_rtc;
};
+ encoder {
+ compatible = "ti,tfp410";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ tfp410_in: endpoint {
+ remote-endpoint = <¶llel_display_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ tfp410_out: endpoint {
+ remote-endpoint = <&hdmi_connector_in>;
+ };
+ };
+ };
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -72,6 +99,19 @@
};
};
+ hdmi-connector {
+ compatible = "hdmi-connector";
+
+ type = "a";
+ ddc-i2c-bus = <&i2c_dvi_ddc>;
+
+ port {
+ hdmi_connector_in: endpoint {
+ remote-endpoint = <&tfp410_out>;
+ };
+ };
+ };
+
i2cmux {
compatible = "i2c-mux-gpio";
pinctrl-names = "default";
@@ -105,8 +145,46 @@
#size-cells = <0>;
};
};
+
+ parallel-display {
+ compatible = "fsl,imx-parallel-display";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1>;
+
+ interface-pix-fmt = "rgb24";
+
+ port@0 {
+ reg = <0>;
+
+ parallel_display_in: endpoint {
+ remote-endpoint = <&ipu1_di0_disp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ parallel_display_out: endpoint {
+ remote-endpoint = <&tfp410_in>;
+ };
+ };
+ };
};
+/*
+ * A single IPU is not able to drive both display interfaces available on the
+ * Utilite Pro at high resolution due to its bandwidth limitation. Since the
+ * tfp410 encoder is wired up to IPU1, sever the link between IPU1 and the
+ * SoC-internal Designware HDMI encoder forcing the latter to be connected to
+ * IPU2 instead of IPU1.
+ */
+/delete-node/&ipu1_di0_hdmi;
+/delete-node/&hdmi_mux_0;
+/delete-node/&ipu1_di1_hdmi;
+/delete-node/&hdmi_mux_1;
+
&hdmi {
ddc-i2c-bus = <&i2c2>;
status = "okay";
@@ -151,6 +229,39 @@
>;
};
+ pinctrl_ipu1: ipu1grp {
+ fsl,pins = <
+ MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x38
+ MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x38
+ MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x38
+ MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x38
+ MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x38
+ MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x38
+ MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x38
+ MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x38
+ MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x38
+ MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x38
+ MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x38
+ MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x38
+ MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x38
+ MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x38
+ MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x38
+ MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x38
+ MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x38
+ MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x38
+ MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x38
+ MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x38
+ MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x38
+ MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x38
+ MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x38
+ MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x38
+ MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x38
+ MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x38
+ MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x38
+ MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x38
+ >;
+ };
+
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6QDL_PAD_GPIO_7__UART2_TX_DATA 0x1b0b1
@@ -194,6 +305,10 @@
};
};
+&ipu1_di0_disp0 {
+ remote-endpoint = <¶llel_display_in>;
+};
+
&pcie {
pcie@0,0 {
reg = <0x000000 0 0 0 0>;
--
2.10.2
--
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^ permalink raw reply related
* Re: [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Icenowy Zheng @ 2016-12-02 14:32 UTC (permalink / raw)
To: Hans de Goede, Maxime Ripard, André Przywara
Cc: Mark Rutland, devicetree@vger.kernel.org, Vishnu Patekar,
Arnd Bergmann, Jonathan Corbet, linux-doc@vger.kernel.org,
Russell King, linux-kernel@vger.kernel.org, Chen-Yu Tsai,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <efb30303-b9bb-7a7c-4478-af485991dd86@redhat.com>
02.12.2016, 22:30, "Hans de Goede" <hdegoede@redhat.com>:
> Hi,
>
> On 02-12-16 15:22, Icenowy Zheng wrote:
>> 01.12.2016, 17:36, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>>> On Mon, Nov 28, 2016 at 12:29:07AM +0000, André Przywara wrote:
>>>> > Something more interesting happened.
>>>> >
>>>> > Xunlong made a add-on board for Orange Pi Zero, which exposes the
>>>> > two USB Controllers exported at expansion bus as USB Type-A
>>>> > connectors.
>>>> >
>>>> > Also it exposes a analog A/V jack and a microphone.
>>>> >
>>>> > Should I enable {e,o}hci{2.3} in the device tree?
>>>>
>>>> Actually we should do this regardless of this extension board. The USB
>>>> pins are not multiplexed and are exposed on user accessible pins (just
>>>> not soldered, but that's a detail), so I think they qualify for DT
>>>> enablement. And even if a user can't use them, it doesn't hurt to have
>>>> them (since they are not multiplexed).
>>>
>>> My main concern about this is that we'll leave regulators enabled by
>>> default, for a minority of users. And that minority will prevent to do
>>> a proper power management when the times come since we'll have to keep
>>> that behaviour forever.
>>
>> I think these users can add a 'fdt set /xxx/xxx status "disabled" ' .
>
> I don't think that will be necessary I'm pretty sure these extra usb
> ports do not have a regulator for the Vbus, they just hook directly
> to the 5V rail, can someone with a schematic check ?
We seems to have still no schematics for the add-on board.
But something is sure is that there's no any regulator-related pins
on the add-on pinout. There's only USB DM and DP pins.
So the Vbus must be directly connected to +5V.
>
> Regards,
>
> Hans
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v2 2/3] ARM: dts: sunxi: add support for Orange Pi Zero board
From: Hans de Goede @ 2016-12-02 14:30 UTC (permalink / raw)
To: Icenowy Zheng, Maxime Ripard, André Przywara
Cc: Mark Rutland, devicetree@vger.kernel.org, Vishnu Patekar,
Arnd Bergmann, Jonathan Corbet, linux-doc@vger.kernel.org,
Russell King, linux-kernel@vger.kernel.org, Chen-Yu Tsai,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <11498641480688550@web2g.yandex.ru>
Hi,
On 02-12-16 15:22, Icenowy Zheng wrote:
>
>
> 01.12.2016, 17:36, "Maxime Ripard" <maxime.ripard@free-electrons.com>:
>> On Mon, Nov 28, 2016 at 12:29:07AM +0000, André Przywara wrote:
>>> > Something more interesting happened.
>>> >
>>> > Xunlong made a add-on board for Orange Pi Zero, which exposes the
>>> > two USB Controllers exported at expansion bus as USB Type-A
>>> > connectors.
>>> >
>>> > Also it exposes a analog A/V jack and a microphone.
>>> >
>>> > Should I enable {e,o}hci{2.3} in the device tree?
>>>
>>> Actually we should do this regardless of this extension board. The USB
>>> pins are not multiplexed and are exposed on user accessible pins (just
>>> not soldered, but that's a detail), so I think they qualify for DT
>>> enablement. And even if a user can't use them, it doesn't hurt to have
>>> them (since they are not multiplexed).
>>
>> My main concern about this is that we'll leave regulators enabled by
>> default, for a minority of users. And that minority will prevent to do
>> a proper power management when the times come since we'll have to keep
>> that behaviour forever.
>
> I think these users can add a 'fdt set /xxx/xxx status "disabled" ' .
I don't think that will be necessary I'm pretty sure these extra usb
ports do not have a regulator for the Vbus, they just hook directly
to the 5V rail, can someone with a schematic check ?
Regards,
Hans
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply
* Re: [PATCH v3 2/7] MFD: add stm32 general purpose timer driver
From: Lee Jones @ 2016-12-02 14:29 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1480673842-20804-3-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
> This hardware block could at used at same time for PWM generation
> and IIO timer for other IPs like DAC, ADC or other timers.
> PWM and IIO timer configuration are mixed in the same registers
> so we need a multi fonction driver to be able to share those registers.
>
> version 2:
> - rename driver "stm32-gptimer" to be align with SoC documentation
> - only keep one compatible
> - use of_platform_populate() instead of devm_mfd_add_devices()
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> drivers/mfd/Kconfig | 10 ++++++
> drivers/mfd/Makefile | 2 ++
> drivers/mfd/stm32-gptimer.c | 73 +++++++++++++++++++++++++++++++++++++++
> include/linux/mfd/stm32-gptimer.h | 62 +++++++++++++++++++++++++++++++++
> 4 files changed, 147 insertions(+)
> create mode 100644 drivers/mfd/stm32-gptimer.c
> create mode 100644 include/linux/mfd/stm32-gptimer.h
>
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index c6df644..e75abcb 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -1607,6 +1607,15 @@ config MFD_STW481X
> in various ST Microelectronics and ST-Ericsson embedded
> Nomadik series.
>
> +config MFD_STM32_GP_TIMER
> + tristate "Support for STM32 General Purpose Timer"
> + select MFD_CORE
> + select REGMAP
> + depends on ARCH_STM32
> + depends on OF
"|| COMPILE_TEST"?
> + help
> + Select this option to enable stm32 general purpose timer
I can see that. Tell us more about the device and what it does.
s/stm32/STM32/
> menu "Multimedia Capabilities Port drivers"
> depends on ARCH_SA1100
>
> @@ -1644,4 +1653,5 @@ config MFD_VEXPRESS_SYSREG
> on the ARM Ltd. Versatile Express board.
>
> endmenu
> +
Please remove this change. It has nothing to do with the set.
> endif
> diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
> index 9834e66..86353b9 100644
> --- a/drivers/mfd/Makefile
> +++ b/drivers/mfd/Makefile
> @@ -211,3 +211,5 @@ obj-$(CONFIG_INTEL_SOC_PMIC) += intel-soc-pmic.o
> obj-$(CONFIG_MFD_MT6397) += mt6397-core.o
>
> obj-$(CONFIG_MFD_ALTERA_A10SR) += altera-a10sr.o
> +
> +obj-$(CONFIG_MFD_STM32_GP_TIMER) += stm32-gptimer.o
> diff --git a/drivers/mfd/stm32-gptimer.c b/drivers/mfd/stm32-gptimer.c
> new file mode 100644
> index 0000000..54fb95c
> --- /dev/null
> +++ b/drivers/mfd/stm32-gptimer.c
> @@ -0,0 +1,73 @@
> +/*
> + * stm32-gptimer.c
Swap this out for a description.
> + * Copyright (C) STMicroelectronics 2016
'\n'
> + * Author: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
> +
> +#include <linux/module.h>
> +#include <linux/of_platform.h>
> +#include <linux/reset.h>
> +
> +#include <linux/mfd/stm32-gptimer.h>
> +
> +static const struct regmap_config stm32_gptimer_regmap_cfg = {
> + .reg_bits = 32,
> + .val_bits = 32,
> + .reg_stride = sizeof(u32),
> + .max_register = 0x400,
> + .fast_io = true,
> +};
> +
> +static int stm32_gptimer_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct stm32_gptimer_dev *mfd;
s/mfd/ddata/
> + struct resource *res;
> + void __iomem *mmio;
> +
> + mfd = devm_kzalloc(dev, sizeof(*mfd), GFP_KERNEL);
> + if (!mfd)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + if (!res)
> + return -ENOMEM;
> +
Remove this 3 lines.
devm_ioremap_resource() does the checking and error printing for you.
> + mmio = devm_ioremap_resource(dev, res);
> + if (IS_ERR(mmio))
> + return PTR_ERR(mmio);
> +
> + mfd->regmap = devm_regmap_init_mmio_clk(dev, "clk_int", mmio,
> + &stm32_gptimer_regmap_cfg);
> + if (IS_ERR(mfd->regmap))
> + return PTR_ERR(mfd->regmap);
> +
> + mfd->clk = devm_clk_get(dev, NULL);
> + if (IS_ERR(mfd->clk))
> + return PTR_ERR(mfd->clk);
> +
> + platform_set_drvdata(pdev, mfd);
> +
> + return of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
> +}
> +
> +static const struct of_device_id stm32_gptimer_of_match[] = {
> + {
> + .compatible = "st,stm32-gptimer",
> + },
One line:
{ .compatible = "st,stm32-gptimer" },
> +};
> +MODULE_DEVICE_TABLE(of, stm32_gptimer_of_match);
> +
> +static struct platform_driver stm32_gptimer_driver = {
> + .probe = stm32_gptimer_probe,
> + .driver = {
> + .name = "stm32-gptimer",
> + .of_match_table = stm32_gptimer_of_match,
> + },
Remove tabs before the '='s.
> +module_platform_driver(stm32_gptimer_driver);
> +
> +MODULE_DESCRIPTION("STMicroelectronics STM32 general purpose timer");
"General Purpose Timer"
> +MODULE_LICENSE("GPL");
"GPL v2"
> diff --git a/include/linux/mfd/stm32-gptimer.h b/include/linux/mfd/stm32-gptimer.h
> new file mode 100644
> index 0000000..f8c92de
> --- /dev/null
> +++ b/include/linux/mfd/stm32-gptimer.h
> @@ -0,0 +1,62 @@
> +/*
> + * stm32-gptimer.h
> + *
> + * Copyright (C) STMicroelectronics 2016
> + * Author: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org> for STMicroelectronics.
> + * License terms: GNU General Public License (GPL), version 2
> + */
Same comments as before.
> +#ifndef _LINUX_STM32_GPTIMER_H_
> +#define _LINUX_STM32_GPTIMER_H_
> +
> +#include <linux/clk.h>
> +#include <linux/regmap.h>
> +
> +#define TIM_CR1 0x00 /* Control Register 1 */
> +#define TIM_CR2 0x04 /* Control Register 2 */
> +#define TIM_SMCR 0x08 /* Slave mode control reg */
> +#define TIM_DIER 0x0C /* DMA/interrupt register */
> +#define TIM_SR 0x10 /* Status register */
> +#define TIM_EGR 0x14 /* Event Generation Reg */
> +#define TIM_CCMR1 0x18 /* Capt/Comp 1 Mode Reg */
> +#define TIM_CCMR2 0x1C /* Capt/Comp 2 Mode Reg */
> +#define TIM_CCER 0x20 /* Capt/Comp Enable Reg */
> +#define TIM_PSC 0x28 /* Prescaler */
> +#define TIM_ARR 0x2c /* Auto-Reload Register */
> +#define TIM_CCR1 0x34 /* Capt/Comp Register 1 */
> +#define TIM_CCR2 0x38 /* Capt/Comp Register 2 */
> +#define TIM_CCR3 0x3C /* Capt/Comp Register 3 */
> +#define TIM_CCR4 0x40 /* Capt/Comp Register 4 */
> +#define TIM_BDTR 0x44 /* Break and Dead-Time Reg */
> +
> +#define TIM_CR1_CEN BIT(0) /* Counter Enable */
> +#define TIM_CR1_ARPE BIT(7) /* Auto-reload Preload Ena */
> +#define TIM_CR2_MMS (BIT(4) | BIT(5) | BIT(6)) /* Master mode selection */
> +#define TIM_SMCR_SMS (BIT(0) | BIT(1) | BIT(2)) /* Slave mode selection */
> +#define TIM_SMCR_TS (BIT(4) | BIT(5) | BIT(6)) /* Trigger selection */
> +#define TIM_DIER_UIE BIT(0) /* Update interrupt */
> +#define TIM_SR_UIF BIT(0) /* Update interrupt flag */
> +#define TIM_EGR_UG BIT(0) /* Update Generation */
> +#define TIM_CCMR_PE BIT(3) /* Channel Preload Enable */
> +#define TIM_CCMR_M1 (BIT(6) | BIT(5)) /* Channel PWM Mode 1 */
> +#define TIM_CCER_CC1E BIT(0) /* Capt/Comp 1 out Ena */
> +#define TIM_CCER_CC1P BIT(1) /* Capt/Comp 1 Polarity */
> +#define TIM_CCER_CC1NE BIT(2) /* Capt/Comp 1N out Ena */
> +#define TIM_CCER_CC1NP BIT(3) /* Capt/Comp 1N Polarity */
> +#define TIM_CCER_CCXE (BIT(0) | BIT(4) | BIT(8) | BIT(12))
> +#define TIM_BDTR_BKE BIT(12) /* Break input enable */
> +#define TIM_BDTR_BKP BIT(13) /* Break input polarity */
> +#define TIM_BDTR_AOE BIT(14) /* Automatic Output Enable */
> +#define TIM_BDTR_MOE BIT(15) /* Main Output Enable */
> +
> +#define MAX_TIM_PSC 0xFFFF
> +
> +struct stm32_gptimer_dev {
Drop the "_dev" or replace with ddata.
> + /* Device data */
No need for this.
> + struct clk *clk;
> +
> + /* Registers mapping */
No need for this.
> + struct regmap *regmap;
> +};
> +
> +#endif
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
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^ permalink raw reply
* [PATCH v4 i2c/for-next] i2c: rcar: Add per-Generation fallback bindings
From: Simon Horman @ 2016-12-02 14:25 UTC (permalink / raw)
To: Wolfram Sang
Cc: Magnus Damm, linux-i2c, linux-renesas-soc, Rob Herring,
devicetree, Simon Horman
In the case of Renesas R-Car hardware we know that there are generations of
SoCs, e.g. Gen 2 and Gen 3. But beyond that it's not clear what the
relationship between IP blocks might be. For example, I believe that
r8a7790 is older than r8a7791 but that doesn't imply that the latter is a
descendant of the former or vice versa.
We can, however, by examining the documentation and behaviour of the
hardware at run-time observe that the current driver implementation appears
to be compatible with the IP blocks on SoCs within a given generation.
For the above reasons and convenience when enabling new SoCs a
per-generation fallback compatibility string scheme is being adopted for
drivers for Renesas SoCs.
Also:
* Deprecate renesas,i2c-rcar. It seems poorly named as it is only
compatible with R-Car Gen 1. It also appears unused in mainline.
* Add some text to describe per-SoC bindings
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
v4
* Correct grammar in changelog
v3
* Consistently use renesas,<family>-<module> for new compat strings
* Drop RFC designation
v2
* Include accidently omitted i2c-rcar.c portion of patch
---
Documentation/devicetree/bindings/i2c/i2c-rcar.txt | 32 ++++++++++++++--------
drivers/i2c/busses/i2c-rcar.c | 5 +++-
2 files changed, 24 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
index 239632a0d709..50c378ccb8e7 100644
--- a/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
+++ b/Documentation/devicetree/bindings/i2c/i2c-rcar.txt
@@ -1,17 +1,25 @@
I2C for R-Car platforms
Required properties:
-- compatible: Must be one of
- "renesas,i2c-rcar"
- "renesas,i2c-r8a7778"
- "renesas,i2c-r8a7779"
- "renesas,i2c-r8a7790"
- "renesas,i2c-r8a7791"
- "renesas,i2c-r8a7792"
- "renesas,i2c-r8a7793"
- "renesas,i2c-r8a7794"
- "renesas,i2c-r8a7795"
- "renesas,i2c-r8a7796"
+- compatible:
+ "renesas,i2c-r8a7778" if the device is a part of a R8A7778 SoC.
+ "renesas,i2c-r8a7779" if the device is a part of a R8A7797 SoC.
+ "renesas,i2c-r8a7790" if the device is a part of a R8A7790 SoC.
+ "renesas,i2c-r8a7791" if the device is a part of a R8A7791 SoC.
+ "renesas,i2c-r8a7792" if the device is a part of a R8A7792 SoC.
+ "renesas,i2c-r8a7793" if the device is a part of a R8A7793 SoC.
+ "renesas,i2c-r8a7794" if the device is a part of a R8A7794 SoC.
+ "renesas,i2c-r8a7795" if the device is a part of a R8A7795 SoC.
+ "renesas,i2c-r8a7796" if the device is a part of a R8A7796 SoC.
+ "renesas,rcar-gen1-i2c" for a generic R-Car Gen1 compatible device.
+ "renesas,rcar-gen2-i2c" for a generic R-Car Gen2 compatible device.
+ "renesas,rcar-gen3-i2c" for a generic R-Car Gen3 compatible device.
+ "renesas,i2c-rcar" (deprecated)
+
+ When compatible with the generic version, nodes must list the
+ SoC-specific version corresponding to the platform first followed
+ by the generic version.
+
- reg: physical base address of the controller and length of memory mapped
region.
- interrupts: interrupt specifier.
@@ -33,7 +41,7 @@ Examples :
i2c0: i2c@e6508000 {
#address-cells = <1>;
#size-cells = <0>;
- compatible = "renesas,i2c-r8a7791";
+ compatible = "renesas,i2c-r8a7791", "renesas,rcar-gen2-i2c";
reg = <0 0xe6508000 0 0x40>;
interrupts = <0 287 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_I2C0>;
diff --git a/drivers/i2c/busses/i2c-rcar.c b/drivers/i2c/busses/i2c-rcar.c
index 726615e54f2a..622def6b43e2 100644
--- a/drivers/i2c/busses/i2c-rcar.c
+++ b/drivers/i2c/busses/i2c-rcar.c
@@ -793,7 +793,6 @@ static const struct i2c_algorithm rcar_i2c_algo = {
};
static const struct of_device_id rcar_i2c_dt_ids[] = {
- { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
{ .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
@@ -803,6 +802,10 @@ static const struct of_device_id rcar_i2c_dt_ids[] = {
{ .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
{ .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
{ .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
+ { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, // Deprecated
+ { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
+ { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
+ { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
{},
};
MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
--
2.7.0.rc3.207.g0ac5344
^ permalink raw reply related
* Re: [PATCH v3 5/7] IIO: add bindings for stm32 timer trigger driver
From: Benjamin Gaignard @ 2016-12-02 14:23 UTC (permalink / raw)
To: Lee Jones
Cc: robh+dt, Mark Rutland, alexandre.torgue, devicetree,
Linux Kernel Mailing List, Thierry Reding, linux-pwm,
Jonathan Cameron, knaack.h, Lars-Peter Clausen,
Peter Meerwald-Stadler, linux-iio, linux-arm-kernel,
Fabrice Gasnier, Gerald Baeza, Arnaud Pouliquen, Linus Walleij,
Linaro Kernel Mailman List, Benjamin Gaignard
In-Reply-To: <20161202135904.GN2683@dell>
2016-12-02 14:59 GMT+01:00 Lee Jones <lee.jones@linaro.org>:
> On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
>
>> Define bindings for stm32 timer trigger
>>
>> version 3:
>> - change file name
>> - add cross reference with mfd bindings
>>
>> version 2:
>> - only keep one compatible
>> - add DT parameters to set lists of the triggers:
>> one list describe the triggers created by the device
>> another one give the triggers accepted by the device
>>
>> Signed-off-by: Benjamin Gaignard <benjamin.gaignard@st.com>
>> ---
>> .../bindings/iio/timer/stm32-timer-trigger.txt | 39 ++++++++++++++++++++++
>> 1 file changed, 39 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>>
>> diff --git a/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> new file mode 100644
>> index 0000000..858816d
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/iio/timer/stm32-timer-trigger.txt
>> @@ -0,0 +1,39 @@
>> +timer trigger bindings for STM32
>> +
>> +Must be a sub-node of STM32 general purpose timer driver
>> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
>> +
>> +Required parameters:
>> +- compatible: must be "st,stm32-iio-timer"
>> +- interrupts: Interrupt for this device
>> + See ../interrupt-controller/st,stm32-exti.txt
>> +
>> +Optional parameters:
>> +- st,input-triggers-names: List of the possible input triggers for
>> + the device
>> +- st,output-triggers-names: List of the possible output triggers for
>> + the device
>> +
>> +Possible triggers are defined in include/dt-bindings/iio/timer/st,stm32-timer-trigger.h
>> +
>> +Example:
>> + gptimer1: gptimer1@40010000 {
>> + compatible = "st,stm32-gptimer";
>> + reg = <0x40010000 0x400>;
>> + clocks = <&rcc 0 160>;
>> + clock-names = "clk_int";
>> +
>> + timer1@0 {
>> + compatible = "st,stm32-timer-trigger";
>> + interrupts = <27>;
>> + st,input-triggers-names = TIM5_TRGO,
>> + TIM2_TRGO,
>> + TIM4_TRGO,
>> + TIM3_TRGO;
>> + st,output-triggers-names = TIM1_TRGO,
>> + TIM1_CH1,
>> + TIM1_CH2,
>> + TIM1_CH3,
>> + TIM1_CH4;
>
> I see why you've done it like this now ... because it makes things
> easier for you in the driver, since the IIO subsystem matches on names
> such as these.
>
> BUT, this is a Linux-implementation-ism. Just use pairs of integers
> and create the Linux-ism strings in the driver.
The goal is not to make things easier in driver but to be able to share
the triggers names with other drivers like DAC or ADC.
If each driver have to create it own triggers names it will more difficult
to keep them coherent than it they share the same definitions
>
>> + };
>> + };
>
> --
> Lee Jones
> Linaro STMicroelectronics Landing Team Lead
> Linaro.org │ Open source software for ARM SoCs
> Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
* Re: [PATCH v3 3/7] PWM: add pwm-stm32 DT bindings
From: Lee Jones @ 2016-12-02 14:23 UTC (permalink / raw)
To: Benjamin Gaignard
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
alexandre.torgue-qxv4g6HH51o, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thierry.reding-Re5JQEeQqe8AvxtiuMwx3w,
linux-pwm-u79uwXL29TY76Z2rM5mHXA, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
fabrice.gasnier-qxv4g6HH51o, gerald.baeza-qxv4g6HH51o,
arnaud.pouliquen-qxv4g6HH51o,
linus.walleij-QSEj5FYQhm4dnm+yROfE0A,
linaro-kernel-cunTk1MwBs8s++Sfvej+rw, Benjamin Gaignard
In-Reply-To: <1480673842-20804-4-git-send-email-benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
On Fri, 02 Dec 2016, Benjamin Gaignard wrote:
> Define bindings for pwm-stm32
>
> version 2:
> - use parameters instead of compatible of handle the hardware configuration
>
> Signed-off-by: Benjamin Gaignard <benjamin.gaignard-qxv4g6HH51o@public.gmane.org>
> ---
> .../devicetree/bindings/pwm/pwm-stm32.txt | 38 ++++++++++++++++++++++
> 1 file changed, 38 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/pwm-stm32.txt
>
> diff --git a/Documentation/devicetree/bindings/pwm/pwm-stm32.txt b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> new file mode 100644
> index 0000000..575b9fb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pwm/pwm-stm32.txt
> @@ -0,0 +1,38 @@
> +STMicroelectronics PWM driver bindings for STM32
> +
> +Must be a sub-node of STM32 general purpose timer driver
> +Parent node properties are describe in ../mfd/stm32-general-purpose-timer.txt
> +
> +Required parameters:
> +- compatible: Must be "st,stm32-pwm"
> +- pinctrl-names: Set to "default".
> +- pinctrl-0: List of phandles pointing to pin configuration nodes
> + for PWM module.
> + For Pinctrl properties, please refer to [1].
> +
> +Optional parameters:
> +- st,breakinput: Set if the hardware have break input capabilities
> +- st,breakinput-polarity: Set break input polarity. Default is 0
> + The value define the active polarity:
> + - 0 (active LOW)
> + - 1 (active HIGH)
> +- st,breakinput-polarity-high
Then assume the default if the property is not present.
> +- st,pwm-num-chan: Number of available PWM channels. Default is 0.
What's the point in having a PWM device with no channels?
Best to make this a compulsory property.
> +- st,32bits-counter: Set if the hardware have a 32 bits counter
> +- st,complementary: Set if the hardware have complementary output channels
> +
> +[1] Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
Use relative path.
../pinctrl/pinctrl-bindings.txt
> +Example:
> + gptimer1: gptimer1@40010000 {
> + compatible = "st,stm32-gptimer";
> + reg = <0x40010000 0x400>;
> + clocks = <&rcc 0 160>;
> + clock-names = "clk_int";
> +
> + pwm1@0 {
Don't number the node name.
pwm@xx
> + compatible = "st,stm32-pwm";
> + st,pwm-num-chan = <4>;
> + st,breakinput;
> + st,complementary;
> + };
> + };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply
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