* [PATCH 2/2] arm64:dt:ls1012a: Add TMU device tree support for LS1012A
From: Jia Hongtao @ 2016-12-08 3:28 UTC (permalink / raw)
To: shawnguo, rui.zhang, edubezval, robh+dt, scott.wood
Cc: hongtao.jia, devicetree, linux-kernel, linux-arm-kernel
In-Reply-To: <1481167706-44234-1-git-send-email-hongtao.jia@nxp.com>
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
Depend on patch "[v3] arm64: Add DTS support for FSL's LS1012A SoC".
https://patchwork.kernel.org/patch/9462399/
arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 76 ++++++++++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 92e64f3..bc694b4 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -43,6 +43,7 @@
*/
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
compatible = "fsl,ls1012a";
@@ -127,6 +128,81 @@
#clock-cells = <2>;
clocks = <&sysclk>;
};
+ tmu: tmu@1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 0>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
i2c0: i2c@2180000 {
compatible = "fsl,vf610-i2c";
--
2.1.0.27.g96db324
^ permalink raw reply related
* [PATCH 1/2] arm64:dt:ls1046a: Add TMU device tree support for LS1046A
From: Jia Hongtao @ 2016-12-08 3:28 UTC (permalink / raw)
To: shawnguo, rui.zhang, edubezval, robh+dt, scott.wood
Cc: hongtao.jia, devicetree, linux-kernel, linux-arm-kernel
Also add nodes and properties for thermal management support.
Signed-off-by: Jia Hongtao <hongtao.jia@nxp.com>
---
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 79 ++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 38806ca..40604e9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -45,6 +45,8 @@
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/thermal/thermal.h>
+
/ {
compatible = "fsl,ls1046a";
@@ -67,6 +69,7 @@
clocks = <&clockgen 1 0>;
next-level-cache = <&l2>;
cpu-idle-states = <&CPU_PH20>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -279,6 +282,82 @@
clocks = <&sysclk>;
};
+ tmu: tmu@1f00000 {
+ compatible = "fsl,qoriq-tmu";
+ reg = <0x0 0x1f00000 0x0 0x10000>;
+ interrupts = <0 33 0x4>;
+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>;
+ fsl,tmu-calibration = <0x00000000 0x00000026
+ 0x00000001 0x0000002d
+ 0x00000002 0x00000032
+ 0x00000003 0x00000039
+ 0x00000004 0x0000003f
+ 0x00000005 0x00000046
+ 0x00000006 0x0000004d
+ 0x00000007 0x00000054
+ 0x00000008 0x0000005a
+ 0x00000009 0x00000061
+ 0x0000000a 0x0000006a
+ 0x0000000b 0x00000071
+
+ 0x00010000 0x00000025
+ 0x00010001 0x0000002c
+ 0x00010002 0x00000035
+ 0x00010003 0x0000003d
+ 0x00010004 0x00000045
+ 0x00010005 0x0000004e
+ 0x00010006 0x00000057
+ 0x00010007 0x00000061
+ 0x00010008 0x0000006b
+ 0x00010009 0x00000076
+
+ 0x00020000 0x00000029
+ 0x00020001 0x00000033
+ 0x00020002 0x0000003d
+ 0x00020003 0x00000049
+ 0x00020004 0x00000056
+ 0x00020005 0x00000061
+ 0x00020006 0x0000006d
+
+ 0x00030000 0x00000021
+ 0x00030001 0x0000002a
+ 0x00030002 0x0000003c
+ 0x00030003 0x0000004e>;
+ big-endian;
+ #thermal-sensor-cells = <1>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <1000>;
+ polling-delay = <5000>;
+
+ thermal-sensors = <&tmu 3>;
+
+ trips {
+ cpu_alert: cpu-alert {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+ cpu_crit: cpu-crit {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert>;
+ cooling-device =
+ <&cpu0 THERMAL_NO_LIMIT
+ THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
dspi: dspi@2100000 {
compatible = "fsl,ls1021a-v1.0-dspi";
#address-cells = <1>;
--
2.1.0.27.g96db324
^ permalink raw reply related
* [RESEND-PATCH] ARM: EXYNOS: remove smp hook from machine descriptor
From: Pankaj Dubey @ 2016-12-08 3:02 UTC (permalink / raw)
To: linux-samsung-soc, linux-arm-kernel, devicetree
Cc: arnd, krzk, kgene, javier, thomas.ab, Pankaj Dubey
Use CPU_METHOD_OF_DECLARE() for smp_ops instead of using it
via machine descriptor.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
---
Resending as I missed to include samsung mailing list.
arch/arm/boot/dts/exynos3250.dtsi | 1 +
arch/arm/boot/dts/exynos4210.dtsi | 1 +
arch/arm/boot/dts/exynos4212.dtsi | 1 +
arch/arm/boot/dts/exynos4412.dtsi | 1 +
arch/arm/boot/dts/exynos5250.dtsi | 1 +
arch/arm/boot/dts/exynos5260.dtsi | 1 +
arch/arm/boot/dts/exynos5410.dtsi | 1 +
arch/arm/boot/dts/exynos5420-cpus.dtsi | 1 +
arch/arm/boot/dts/exynos5422-cpus.dtsi | 1 +
arch/arm/boot/dts/exynos5440.dtsi | 1 +
arch/arm/mach-exynos/common.h | 2 --
arch/arm/mach-exynos/exynos.c | 1 -
arch/arm/mach-exynos/platsmp.c | 2 ++
13 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi
index ba17ee1..f28f669 100644
--- a/arch/arm/boot/dts/exynos3250.dtsi
+++ b/arch/arm/boot/dts/exynos3250.dtsi
@@ -53,6 +53,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi
index 7f3a18c..6dfd98d 100644
--- a/arch/arm/boot/dts/exynos4210.dtsi
+++ b/arch/arm/boot/dts/exynos4210.dtsi
@@ -35,6 +35,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@900 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi
index 5389011..3e8982e 100644
--- a/arch/arm/boot/dts/exynos4212.dtsi
+++ b/arch/arm/boot/dts/exynos4212.dtsi
@@ -25,6 +25,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@A00 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi
index 40beede..faf2fb8 100644
--- a/arch/arm/boot/dts/exynos4412.dtsi
+++ b/arch/arm/boot/dts/exynos4412.dtsi
@@ -25,6 +25,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@A00 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index b6d7444..580897c 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -52,6 +52,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi
index 5818718..1af6e76 100644
--- a/arch/arm/boot/dts/exynos5260.dtsi
+++ b/arch/arm/boot/dts/exynos5260.dtsi
@@ -32,6 +32,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi
index 2b6adaf..b092cdc 100644
--- a/arch/arm/boot/dts/exynos5410.dtsi
+++ b/arch/arm/boot/dts/exynos5410.dtsi
@@ -33,6 +33,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index 5c052d7..a587704 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -24,6 +24,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index bf3c6f1..7fcdfd0 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -23,6 +23,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu0: cpu@100 {
device_type = "cpu";
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..0a958e8 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -50,6 +50,7 @@
cpus {
#address-cells = <1>;
#size-cells = <0>;
+ enable-method = "samsung,exynos-smp";
cpu@0 {
device_type = "cpu";
diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h
index fb12d11..051e1ab 100644
--- a/arch/arm/mach-exynos/common.h
+++ b/arch/arm/mach-exynos/common.h
@@ -143,8 +143,6 @@ static inline void exynos_pm_init(void) {}
extern void exynos_cpu_resume(void);
extern void exynos_cpu_resume_ns(void);
-extern const struct smp_operations exynos_smp_ops;
-
extern void exynos_cpu_power_down(int cpu);
extern void exynos_cpu_power_up(int cpu);
extern int exynos_cpu_power_state(int cpu);
diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c
index fa08ef9..f0a766e 100644
--- a/arch/arm/mach-exynos/exynos.c
+++ b/arch/arm/mach-exynos/exynos.c
@@ -211,7 +211,6 @@ DT_MACHINE_START(EXYNOS_DT, "SAMSUNG EXYNOS (Flattened Device Tree)")
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
.l2c_aux_val = 0x3c400001,
.l2c_aux_mask = 0xc20fffff,
- .smp = smp_ops(exynos_smp_ops),
.map_io = exynos_init_io,
.init_early = exynos_firmware_init,
.init_irq = exynos_init_irq,
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 94405c7..43eec10 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -474,3 +474,5 @@ const struct smp_operations exynos_smp_ops __initconst = {
.cpu_die = exynos_cpu_die,
#endif
};
+
+CPU_METHOD_OF_DECLARE(exynos_smp, "samsung,exynos-smp", &exynos_smp_ops);
--
2.7.4
^ permalink raw reply related
* Re: [PATCH v3 4/4] pinctrl: aspeed: Fix kerneldoc return descriptions
From: Joel Stanley @ 2016-12-08 2:20 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Rob Herring, Mark Rutland,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161206031152.3004-5-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 6, 2016 at 1:41 PM, Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> wrote:
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
Acked-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> ---
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 1/4] pinctrl: aspeed: Read and write bits in LPC and GFX controllers
From: Joel Stanley @ 2016-12-08 2:19 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Rob Herring, Mark Rutland, linux-gpio, devicetree,
linux-kernel
In-Reply-To: <20161206031152.3004-2-andrew@aj.id.au>
On Tue, Dec 6, 2016 at 1:41 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
>
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
(I think I've reviewed these on the openbmc list; feel free to keep my
reviewed-by tag when that's happened).
We might need to split the bindings update and the code changes into
separate patches so they can go via their respective trees.
Cheers,
Joel
> ---
> .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 50 ++++++-
> drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 48 ++++--
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 161 +++++++++++++--------
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++--
> 5 files changed, 214 insertions(+), 95 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> index 2ad18c4ea55c..115b0cce6c1c 100644
> --- a/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt
> @@ -4,12 +4,19 @@ Aspeed Pin Controllers
> The Aspeed SoCs vary in functionality inside a generation but have a common mux
> device register layout.
>
> -Required properties:
> -- compatible : Should be any one of the following:
> - "aspeed,ast2400-pinctrl"
> - "aspeed,g4-pinctrl"
> - "aspeed,ast2500-pinctrl"
> - "aspeed,g5-pinctrl"
> +Required properties for g4:
> +- compatible : Should be any one of the following:
> + "aspeed,ast2400-pinctrl"
> + "aspeed,g4-pinctrl"
> +
> +Required properties for g5:
> +- compatible : Should be any one of the following:
> + "aspeed,ast2500-pinctrl"
> + "aspeed,g5-pinctrl"
> +
> +- aspeed,external-nodes: A cell of phandles to external controller nodes:
> + 0: compatible with "aspeed,ast2500-gfx", "syscon"
> + 1: compatible with "aspeed,ast2500-lpchc", "syscon"
>
> The pin controller node should be a child of a syscon node with the required
> property:
> @@ -47,7 +54,7 @@ RGMII1 RGMII2 RMII1 RMII2 SD1 SPI1 SPI1DEBUG SPI1PASSTHRU TIMER4 TIMER5 TIMER6
> TIMER7 TIMER8 VGABIOSROM
>
>
> -Examples:
> +g4 Example:
>
> syscon: scu@1e6e2000 {
> compatible = "syscon", "simple-mfd";
> @@ -63,5 +70,34 @@ syscon: scu@1e6e2000 {
> };
> };
>
> +g5 Example:
> +
> +apb {
> + gfx: display@1e6e6000 {
> + compatible = "aspeed,ast2500-gfx", "syscon";
> + reg = <0x1e6e6000 0x1000>;
> + };
> +
> + lpchc: lpchc@1e7890a0 {
> + compatible = "aspeed,ast2500-lpchc", "syscon";
> + reg = <0x1e7890a0 0xc4>;
> + };
> +
> + syscon: scu@1e6e2000 {
> + compatible = "syscon", "simple-mfd";
> + reg = <0x1e6e2000 0x1a8>;
> +
> + pinctrl: pinctrl {
> + compatible = "aspeed,g5-pinctrl";
> + aspeed,external-nodes = <&gfx, &lpchc>;
> +
> + pinctrl_i2c3_default: i2c3_default {
> + function = "I2C3";
> + groups = "I2C3";
> + };
> + };
> + };
> +};
> +
> Please refer to pinctrl-bindings.txt in this directory for details of the
> common pinctrl bindings used by client devices.
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> index a21b071ff290..558bd102416c 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c
> @@ -292,7 +292,7 @@ SSSF_PIN_DECL(U18, GPIOG7, FLWP, SIG_DESC_SET(SCU84, 7));
> #define UART6_DESC SIG_DESC_SET(SCU90, 7)
> #define ROM16_DESC SIG_DESC_SET(SCU90, 6)
> #define FLASH_WIDE SIG_DESC_SET(HW_STRAP1, 4)
> -#define BOOT_SRC_NOR { HW_STRAP1, GENMASK(1, 0), 0, 0 }
> +#define BOOT_SRC_NOR { ASPEED_IP_SCU, HW_STRAP1, GENMASK(1, 0), 0, 0 }
>
> #define A8 56
> SIG_EXPR_DECL(ROMD8, ROM16, ROM16_DESC);
> @@ -418,9 +418,9 @@ FUNC_GROUP_DECL(I2C8, G5, F3);
> #define U1 88
> SSSF_PIN_DECL(U1, GPIOL0, NCTS1, SIG_DESC_SET(SCU84, 16));
>
> -#define VPI18_DESC { SCU90, GENMASK(5, 4), 1, 0 }
> -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
> -#define VPI30_DESC { SCU90, GENMASK(5, 4), 3, 0 }
> +#define VPI18_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
> +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
> +#define VPI30_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
>
> #define T5 89
> #define T5_DESC SIG_DESC_SET(SCU84, 17)
> @@ -641,11 +641,11 @@ SSSF_PIN_DECL(Y22, GPIOR2, ROMCS3, SIG_DESC_SET(SCU88, 26));
> #define U19 139
> SSSF_PIN_DECL(U19, GPIOR3, ROMCS4, SIG_DESC_SET(SCU88, 27));
>
> -#define VPOOFF0_DESC { SCU94, GENMASK(1, 0), 0, 0 }
> -#define VPO12_DESC { SCU94, GENMASK(1, 0), 1, 0 }
> -#define VPO24_DESC { SCU94, GENMASK(1, 0), 2, 0 }
> -#define VPOOFF1_DESC { SCU94, GENMASK(1, 0), 3, 0 }
> -#define VPO_OFF_12 { SCU94, 0x2, 0, 0 }
> +#define VPOOFF0_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
> +#define VPO12_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 1, 0 }
> +#define VPO24_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 2, 0 }
> +#define VPOOFF1_DESC { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 3, 0 }
> +#define VPO_OFF_12 { ASPEED_IP_SCU, SCU94, 0x2, 0, 0 }
> #define VPO_24_OFF SIG_DESC_SET(SCU94, 1)
>
> #define V21 140
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> index 87b46390b695..c5c9a1b6fa1c 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c
> @@ -10,6 +10,7 @@
> #include <linux/init.h>
> #include <linux/io.h>
> #include <linux/kernel.h>
> +#include <linux/mfd/syscon.h>
> #include <linux/mutex.h>
> #include <linux/of.h>
> #include <linux/platform_device.h>
> @@ -26,8 +27,8 @@
>
> #define ASPEED_G5_NR_PINS 228
>
> -#define COND1 { SCU90, BIT(6), 0, 0 }
> -#define COND2 { SCU94, GENMASK(1, 0), 0, 0 }
> +#define COND1 { ASPEED_IP_SCU, SCU90, BIT(6), 0, 0 }
> +#define COND2 { ASPEED_IP_SCU, SCU94, GENMASK(1, 0), 0, 0 }
>
> #define B14 0
> SSSF_PIN_DECL(B14, GPIOA0, MAC1LINK, SIG_DESC_SET(SCU80, 0));
> @@ -186,9 +187,12 @@ MS_PIN_DECL(C20, GPIOE1, NDCD3, GPIE0OUT);
>
> FUNC_GROUP_DECL(GPIE0, B20, C20);
>
> -#define SPI1_DESC { HW_STRAP1, GENMASK(13, 12), 1, 0 }
> -#define SPI1DEBUG_DESC { HW_STRAP1, GENMASK(13, 12), 2, 0 }
> -#define SPI1PASSTHRU_DESC { HW_STRAP1, GENMASK(13, 12), 3, 0 }
> +#define SPI1_DESC \
> + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 1, 0 }
> +#define SPI1DEBUG_DESC \
> + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 2, 0 }
> +#define SPI1PASSTHRU_DESC \
> + { ASPEED_IP_SCU, HW_STRAP1, GENMASK(13, 12), 3, 0 }
>
> #define C18 64
> SIG_EXPR_DECL(SYSCS, SPI1DEBUG, COND1, SPI1DEBUG_DESC);
> @@ -325,10 +329,11 @@ SS_PIN_DECL(R1, GPIOK7, SDA8);
>
> FUNC_GROUP_DECL(I2C8, P2, R1);
>
> -#define VPIOFF0_DESC { SCU90, GENMASK(5, 4), 0, 0 }
> -#define VPIOFF1_DESC { SCU90, GENMASK(5, 4), 1, 0 }
> -#define VPI24_DESC { SCU90, GENMASK(5, 4), 2, 0 }
> -#define VPIRSVD_DESC { SCU90, GENMASK(5, 4), 3, 0 }
> +#define VPIOFF0_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 0, 0 }
> +#define VPIOFF1_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 1, 0 }
> +#define VPI24_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 2, 0 }
> +#define VPIRSVD_DESC { ASPEED_IP_SCU, SCU90, GENMASK(5, 4), 3, 0 }
> +
>
> #define V2 104
> #define V2_DESC SIG_DESC_SET(SCU88, 0)
> @@ -848,10 +853,35 @@ static struct pinctrl_desc aspeed_g5_pinctrl_desc = {
> static int aspeed_g5_pinctrl_probe(struct platform_device *pdev)
> {
> int i;
> + struct regmap *map;
> + struct device_node *node;
>
> for (i = 0; i < ARRAY_SIZE(aspeed_g5_pins); i++)
> aspeed_g5_pins[i].number = i;
>
> + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 0);
> + map = syscon_node_to_regmap(node);
> + of_node_put(node);
> + if (IS_ERR(map)) {
> + dev_warn(&pdev->dev, "No GFX phandle found, some mux configurations may fail\n");
> + map = NULL;
> + }
> + aspeed_g5_pinctrl_data.maps[ASPEED_IP_GFX] = map;
> +
> + node = of_parse_phandle(pdev->dev.of_node, "aspeed,external-nodes", 1);
> + if (node) {
> + map = syscon_node_to_regmap(node->parent);
> + if (IS_ERR(map)) {
> + dev_warn(&pdev->dev, "LHC parent is not a syscon, some mux configurations may fail\n");
> + map = NULL;
> + }
> + } else {
> + dev_warn(&pdev->dev, "No LHC phandle found, some mux configurations may fail\n");
> + map = NULL;
> + }
> + of_node_put(node);
> + aspeed_g5_pinctrl_data.maps[ASPEED_IP_LPC] = map;
> +
> return aspeed_pinctrl_probe(pdev, &aspeed_g5_pinctrl_desc,
> &aspeed_g5_pinctrl_data);
> }
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> index 49aeba912531..782c5c97f853 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c
> @@ -14,6 +14,12 @@
> #include "../core.h"
> #include "pinctrl-aspeed.h"
>
> +static const char *const aspeed_pinmux_ips[] = {
> + [ASPEED_IP_SCU] = "SCU",
> + [ASPEED_IP_GFX] = "GFX",
> + [ASPEED_IP_LPC] = "LPC",
> +};
> +
> int aspeed_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
> {
> struct aspeed_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
> @@ -78,7 +84,8 @@ int aspeed_pinmux_get_fn_groups(struct pinctrl_dev *pctldev,
> static inline void aspeed_sig_desc_print_val(
> const struct aspeed_sig_desc *desc, bool enable, u32 rv)
> {
> - pr_debug("SCU%x[0x%08x]=0x%x, got 0x%x from 0x%08x\n", desc->reg,
> + pr_debug("Want %s%X[0x%08X]=0x%X, got 0x%X from 0x%08X\n",
> + aspeed_pinmux_ips[desc->ip], desc->reg,
> desc->mask, enable ? desc->enable : desc->disable,
> (rv & desc->mask) >> __ffs(desc->mask), rv);
> }
> @@ -88,10 +95,11 @@ static inline void aspeed_sig_desc_print_val(
> *
> * @desc: The signal descriptor of interest
> * @enabled: True to query the enabled state, false to query disabled state
> - * @regmap: The SCU regmap instance
> + * @regmap: The IP block's regmap instance
> *
> - * @return True if the descriptor's bitfield is configured to the state
> - * selected by @enabled, false otherwise
> + * @return 1 if the descriptor's bitfield is configured to the state
> + * selected by @enabled, 0 if not, and less than zero if an unrecoverable
> + * failure occurred
> *
> * Evaluation of descriptor state is non-trivial in that it is not a binary
> * outcome: The bitfields can be greater than one bit in size and thus can take
> @@ -99,14 +107,19 @@ static inline void aspeed_sig_desc_print_val(
> * descriptor (typically this means a different function to the one of interest
> * is enabled). Thus we must explicitly test for either condition as required.
> */
> -static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> +static int aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> bool enabled, struct regmap *map)
> {
> + int ret;
> unsigned int raw;
> u32 want;
>
> - if (regmap_read(map, desc->reg, &raw) < 0)
> - return false;
> + if (!map)
> + return -ENODEV;
> +
> + ret = regmap_read(map, desc->reg, &raw);
> + if (ret)
> + return ret;
>
> aspeed_sig_desc_print_val(desc, enabled, raw);
> want = enabled ? desc->enable : desc->disable;
> @@ -119,10 +132,10 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> *
> * @expr: An expression controlling the signal for a mux function on a pin
> * @enabled: True to query the enabled state, false to query disabled state
> - * @regmap: The SCU regmap instance
> + * @maps: The list of regmap instances
> *
> - * @return True if the expression composed by @enabled evaluates true, false
> - * otherwise
> + * @return 1 if the expression composed by @enabled evaluates true, 0 if not,
> + * and less than zero if an unrecoverable failure occurred.
> *
> * A mux function is enabled or disabled if the function's signal expression
> * for each pin in the function's pin group evaluates true for the desired
> @@ -135,19 +148,21 @@ static bool aspeed_sig_desc_eval(const struct aspeed_sig_desc *desc,
> * neither the enabled nor disabled state. Thus we must explicitly test for
> * either condition as required.
> */
> -static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
> - bool enabled, struct regmap *map)
> +static int aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
> + bool enabled, struct regmap * const *maps)
> {
> int i;
> + int ret;
>
> for (i = 0; i < expr->ndescs; i++) {
> const struct aspeed_sig_desc *desc = &expr->descs[i];
>
> - if (!aspeed_sig_desc_eval(desc, enabled, map))
> - return false;
> + ret = aspeed_sig_desc_eval(desc, enabled, maps[desc->ip]);
> + if (ret <= 0)
> + return ret;
> }
>
> - return true;
> + return 1;
> }
>
> /**
> @@ -158,19 +173,24 @@ static bool aspeed_sig_expr_eval(const struct aspeed_sig_expr *expr,
> * configured
> * @enable: true to enable an function's signal through a pin's signal
> * expression, false to disable the function's signal
> - * @map: The SCU's regmap instance for pinmux register access.
> + * @maps: The list of regmap instances for pinmux register access.
> *
> - * @return true if the expression is configured as requested, false otherwise
> + * @return 0 if the expression is configured as requested and a negative error
> + * code otherwise
> */
> -static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
> - bool enable, struct regmap *map)
> +static int aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
> + bool enable, struct regmap * const *maps)
> {
> + int ret;
> int i;
>
> for (i = 0; i < expr->ndescs; i++) {
> - bool ret;
> const struct aspeed_sig_desc *desc = &expr->descs[i];
> u32 pattern = enable ? desc->enable : desc->disable;
> + u32 val = (pattern << __ffs(desc->mask));
> +
> + if (!maps[desc->ip])
> + return -ENODEV;
>
> /*
> * Strap registers are configured in hardware or by early-boot
> @@ -179,64 +199,79 @@ static bool aspeed_sig_expr_set(const struct aspeed_sig_expr *expr,
> * deconfigured and is the reason we re-evaluate after writing
> * all descriptor bits.
> */
> - if (desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2)
> + if ((desc->reg == HW_STRAP1 || desc->reg == HW_STRAP2) &&
> + desc->ip == ASPEED_IP_SCU)
> continue;
>
> - ret = regmap_update_bits(map, desc->reg, desc->mask,
> - pattern << __ffs(desc->mask)) == 0;
> + ret = regmap_update_bits(maps[desc->ip], desc->reg,
> + desc->mask, val);
>
> - if (!ret)
> + if (ret)
> return ret;
> }
>
> - return aspeed_sig_expr_eval(expr, enable, map);
> + ret = aspeed_sig_expr_eval(expr, enable, maps);
> + if (ret < 0)
> + return ret;
> +
> + if (!ret)
> + return -EPERM;
> +
> + return 0;
> }
>
> -static bool aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
> - struct regmap *map)
> +static int aspeed_sig_expr_enable(const struct aspeed_sig_expr *expr,
> + struct regmap * const *maps)
> {
> - if (aspeed_sig_expr_eval(expr, true, map))
> - return true;
> + int ret;
> +
> + ret = aspeed_sig_expr_eval(expr, true, maps);
> + if (ret < 0)
> + return ret;
>
> - return aspeed_sig_expr_set(expr, true, map);
> + if (!ret)
> + return aspeed_sig_expr_set(expr, true, maps);
> +
> + return 0;
> }
>
> -static bool aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
> - struct regmap *map)
> +static int aspeed_sig_expr_disable(const struct aspeed_sig_expr *expr,
> + struct regmap * const *maps)
> {
> - if (!aspeed_sig_expr_eval(expr, true, map))
> - return true;
> + int ret;
> +
> + ret = aspeed_sig_expr_eval(expr, true, maps);
> + if (ret < 0)
> + return ret;
> +
> + if (ret)
> + return aspeed_sig_expr_set(expr, false, maps);
>
> - return aspeed_sig_expr_set(expr, false, map);
> + return 0;
> }
>
> /**
> * Disable a signal on a pin by disabling all provided signal expressions.
> *
> * @exprs: The list of signal expressions (from a priority level on a pin)
> - * @map: The SCU's regmap instance for pinmux register access.
> + * @maps: The list of regmap instances for pinmux register access.
> *
> - * @return true if all expressions in the list are successfully disabled, false
> - * otherwise
> + * @return 0 if all expressions are disabled, otherwise a negative error code
> */
> -static bool aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
> - struct regmap *map)
> +static int aspeed_disable_sig(const struct aspeed_sig_expr **exprs,
> + struct regmap * const *maps)
> {
> - bool disabled = true;
> + int ret = 0;
>
> if (!exprs)
> return true;
>
> - while (*exprs) {
> - bool ret;
> -
> - ret = aspeed_sig_expr_disable(*exprs, map);
> - disabled = disabled && ret;
> -
> + while (*exprs && !ret) {
> + ret = aspeed_sig_expr_disable(*exprs, maps);
> exprs++;
> }
>
> - return disabled;
> + return ret;
> }
>
> /**
> @@ -330,6 +365,7 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
> unsigned int group)
> {
> int i;
> + int ret;
> const struct aspeed_pinctrl_data *pdata =
> pinctrl_dev_get_drvdata(pctldev);
> const struct aspeed_pin_group *pgroup = &pdata->groups[group];
> @@ -343,6 +379,8 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
> const struct aspeed_sig_expr **funcs;
> const struct aspeed_sig_expr ***prios;
>
> + pr_debug("Muxing pin %d for %s\n", pin, pfunc->name);
> +
> if (!pdesc)
> return -EINVAL;
>
> @@ -358,8 +396,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
> if (expr)
> break;
>
> - if (!aspeed_disable_sig(funcs, pdata->map))
> - return -EPERM;
> + ret = aspeed_disable_sig(funcs, pdata->maps);
> + if (ret)
> + return ret;
>
> prios++;
> }
> @@ -377,8 +416,9 @@ int aspeed_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned int function,
> return -ENXIO;
> }
>
> - if (!aspeed_sig_expr_enable(expr, pdata->map))
> - return -EPERM;
> + ret = aspeed_sig_expr_enable(expr, pdata->maps);
> + if (ret)
> + return ret;
> }
>
> return 0;
> @@ -414,6 +454,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
> struct pinctrl_gpio_range *range,
> unsigned int offset)
> {
> + int ret;
> const struct aspeed_pinctrl_data *pdata =
> pinctrl_dev_get_drvdata(pctldev);
> const struct aspeed_pin_desc *pdesc = pdata->pins[offset].drv_data;
> @@ -432,8 +473,9 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
> if (aspeed_gpio_in_exprs(funcs))
> break;
>
> - if (!aspeed_disable_sig(funcs, pdata->map))
> - return -EPERM;
> + ret = aspeed_disable_sig(funcs, pdata->maps);
> + if (ret)
> + return ret;
>
> prios++;
> }
> @@ -462,10 +504,7 @@ int aspeed_gpio_request_enable(struct pinctrl_dev *pctldev,
> * If GPIO is not the lowest priority signal type, assume there is only
> * one expression defined to enable the GPIO function
> */
> - if (!aspeed_sig_expr_enable(expr, pdata->map))
> - return -EPERM;
> -
> - return 0;
> + return aspeed_sig_expr_enable(expr, pdata->maps);
> }
>
> int aspeed_pinctrl_probe(struct platform_device *pdev,
> @@ -481,10 +520,10 @@ int aspeed_pinctrl_probe(struct platform_device *pdev,
> return -ENODEV;
> }
>
> - pdata->map = syscon_node_to_regmap(parent->of_node);
> - if (IS_ERR(pdata->map)) {
> + pdata->maps[ASPEED_IP_SCU] = syscon_node_to_regmap(parent->of_node);
> + if (IS_ERR(pdata->maps[ASPEED_IP_SCU])) {
> dev_err(&pdev->dev, "No regmap for syscon pincontroller parent\n");
> - return PTR_ERR(pdata->map);
> + return PTR_ERR(pdata->maps[ASPEED_IP_SCU]);
> }
>
> pctl = pinctrl_register(pdesc, &pdev->dev, pdata);
> diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> index 3e72ef8c54bf..0e93cbf2ff33 100644
> --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h
> @@ -232,6 +232,11 @@
> * group.
> */
>
> +#define ASPEED_IP_SCU 0
> +#define ASPEED_IP_GFX 1
> +#define ASPEED_IP_LPC 2
> +#define ASPEED_NR_PINMUX_IPS 3
> +
> /*
> * The "Multi-function Pins Mapping and Control" table in the SoC datasheet
> * references registers by the device/offset mnemonic. The register macros
> @@ -261,7 +266,9 @@
> * A signal descriptor, which describes the register, bits and the
> * enable/disable values that should be compared or written.
> *
> - * @reg: The register offset from base in bytes
> + * @ip: The IP block identifier, used as an index into the regmap array in
> + * struct aspeed_pinctrl_data
> + * @reg: The register offset with respect to the base address of the IP block
> * @mask: The mask to apply to the register. The lowest set bit of the mask is
> * used to derive the shift value.
> * @enable: The value that enables the function. Value should be in the LSBs,
> @@ -270,6 +277,7 @@
> * LSBs, not at the position of the mask.
> */
> struct aspeed_sig_desc {
> + unsigned int ip;
> unsigned int reg;
> u32 mask;
> u32 enable;
> @@ -313,24 +321,30 @@ struct aspeed_pin_desc {
>
> /* Macro hell */
>
> +#define SIG_DESC_IP_BIT(ip, reg, idx, val) \
> + { ip, reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
> +
> /**
> - * Short-hand macro for describing a configuration enabled by the state of one
> - * bit. The disable value is derived.
> + * Short-hand macro for describing an SCU descriptor enabled by the state of
> + * one bit. The disable value is derived.
> *
> * @reg: The signal's associated register, offset from base
> * @idx: The signal's bit index in the register
> * @val: The value (0 or 1) that enables the function
> */
> #define SIG_DESC_BIT(reg, idx, val) \
> - { reg, BIT_MASK(idx), val, (((val) + 1) & 1) }
> + SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, val)
> +
> +#define SIG_DESC_IP_SET(ip, reg, idx) SIG_DESC_IP_BIT(ip, reg, idx, 1)
>
> /**
> - * A further short-hand macro describing a configuration enabled with a set bit.
> + * A further short-hand macro expanding to an SCU descriptor enabled by a set
> + * bit.
> *
> - * @reg: The configuration's associated register, offset from base
> - * @idx: The configuration's bit index in the register
> + * @reg: The register, offset from base
> + * @idx: The bit index in the register
> */
> -#define SIG_DESC_SET(reg, idx) SIG_DESC_BIT(reg, idx, 1)
> +#define SIG_DESC_SET(reg, idx) SIG_DESC_IP_BIT(ASPEED_IP_SCU, reg, idx, 1)
>
> #define SIG_DESC_LIST_SYM(sig, func) sig_descs_ ## sig ## _ ## func
> #define SIG_DESC_LIST_DECL(sig, func, ...) \
> @@ -500,7 +514,7 @@ struct aspeed_pin_desc {
> MS_PIN_DECL_(pin, SIG_EXPR_LIST_PTR(gpio))
>
> struct aspeed_pinctrl_data {
> - struct regmap *map;
> + struct regmap *maps[ASPEED_NR_PINMUX_IPS];
>
> const struct pinctrl_pin_desc *pins;
> const unsigned int npins;
> --
> 2.9.3
>
^ permalink raw reply
* Re: [PATCH v3 4/6] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
From: Joel Stanley @ 2016-12-08 2:12 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Lee Jones, Rob Herring, Mark Rutland, Linus Walleij,
Corey Minyard, Cédric Le Goater,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161206025321.1792-5-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org> wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> on bits in both the System Control Unit and the LPC Host Controller.
>
> The Aspeed LPC Host Controller is described as a child node of the
> LPC host-range syscon device for arbitration of access by the host
> controller and pinmux drivers.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 22 ++++++++++++++++++++++
> 1 file changed, 22 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> index a97131aba446..9de318ef72da 100644
> --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
> @@ -109,3 +109,25 @@ lpc: lpc@1e789000 {
> };
> };
>
> +Host Node Children
> +==================
> +
> +LPC Host Controller
> +-------------------
> +
> +The Aspeed LPC Host Controller configures the Low Pin Count (LPC) bus behaviour
> +between the host and the baseboard management controller. The registers exist
> +in the "host" portion of the Aspeed LPC controller, which must be the parent of
> +the LPC host controller node.
> +
> +Required properties:
> +- compatible: "aspeed,ast2500-lhc";
Can you remind me why this binding doesn't cover the ast2400?
Cheers,
Joel
> +- reg: contains offset/length value of the LHC memory
> + region.
> +
> +Example:
> +
> +lhc: lhc@20 {
> + compatible = "aspeed,ast2500-lhc";
> + reg = <0x20 0x24 0x48 0x8>;
> +};
> --
> 2.9.3
>
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^ permalink raw reply
* Re: [PATCH v3 3/6] mfd: dt: Add Aspeed Low Pin Count Controller bindings
From: Joel Stanley @ 2016-12-08 2:07 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Lee Jones, Rob Herring, Mark Rutland, Linus Walleij,
Corey Minyard, Cédric Le Goater, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20161206025321.1792-4-andrew@aj.id.au>
On Tue, Dec 6, 2016 at 1:23 PM, Andrew Jeffery <andrew@aj.id.au> wrote:
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
> ---
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 111 +++++++++++++++++++++
> 1 file changed, 111 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
^ permalink raw reply
* Re: [PATCH v5 01/14] Documentation: of: add type property
From: Kuninori Morimoto @ 2016-12-08 1:57 UTC (permalink / raw)
To: Rob Herring
Cc: Mark Brown, Linux-ALSA, Liam Girdwood, Simon, Laurent, Guennadi,
Grant Likely, Frank Rowand, Linux-DT, Linux-Kernel
In-Reply-To: <20161201162631.6jtubjiap7w7y3pd@rob-hp-laptop>
Hi Rob
> > From: Kuninori Morimoto <kuninori.morimoto.gx-zM6kxYcvzFBBDgjK7y7TUQ@public.gmane.org>
> >
> > OF graph indicates each devices connection. But it doesn't support type
> > of each port. For example HDMI case, it has video port and sound port
> > in one device node.
> > In this case, current driver can't handle each port correctly.
> > This patch enables to use type property on OF graph.
>
> I still don't think this is necessary. Simply define which port number
> is which for each HDMI chip.
>
> If this is necessary, then the types, video and sound, are too generic.
About this, if OF-graph can have "query" function to each port,
I can remove this "type" property from DT, and driver can answer
each port feature.
But is this OK approach ?
Best regards
---
Kuninori Morimoto
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^ permalink raw reply
* Re: [PATCH v7 0/5] Add intial support to DW MMC host on ZTE SoC
From: Jun Nie @ 2016-12-08 1:28 UTC (permalink / raw)
To: Rob Herring, mark.rutland-5wv7dgnIgG8, Shawn Guo, xie.baoyou,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: Ulf Hansson, Jaehoon Chung, Jason Liu,
chen.chaokai-Th6q7B73Y6EnDS1+zs4M5A,
lai.binz-Th6q7B73Y6EnDS1+zs4M5A, linux-mmc, Jun Nie
In-Reply-To: <1480904976-7081-1-git-send-email-jun.nie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
2016-12-05 10:29 GMT+08:00 Jun Nie <jun.nie-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>:
> Add intial support to DW MMC host on ZTE SoC. It include platform
> specific wrapper driver and workarounds for fifo quirk.
>
> Patches are prepared based on latest dw mmc runtime change:
> https://github.com/jh80chung/dw-mmc.git for-ulf
>
> Changes vs version 6:
> - Resolve confilict when rebase to latest dw-mmc.git for-ulf branch.
> - Add Shawn Lin's review tag.
>
> Changes vs version 5:
> - Add clock delay lock status check to save CPU cycle in timing tuning CMD.
>
> Changes vs version 4:
> - Fix missing empty dts compatible element in the end of compatible array.
>
> Changes vs version 3:
> - Fix brace error in document.
>
> Changes vs version 2:
> - Change dt property fifo-addr to data-addr and fifo-watermark-quirk to
> fifo-watermark-aligned.
> - Polish ZX MMC driver on minor coding style issues.
>
> Changes vs version 1:
> - Change fifo-addr-override to fifo-addr and remove its workaround tag in comments.
> - Remove ZX DW MMC driver reset cap in driver, which can be added in dt nodes.
>
> Jun Nie (5):
> mmc: dt-bindings: add ZTE ZX296718 MMC bindings
> mmc: zx: Initial support for ZX mmc controller
> Documentation: synopsys-dw-mshc: add binding for fifo quirks
> mmc: dw: Add fifo address property
> mmc: dw: Add fifo watermark alignment property
>
> .../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 ++
> .../devicetree/bindings/mmc/zx-dw-mshc.txt | 34 +++
> drivers/mmc/host/Kconfig | 9 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-zx.c | 242 +++++++++++++++++++++
> drivers/mmc/host/dw_mmc-zx.h | 31 +++
> drivers/mmc/host/dw_mmc.c | 17 +-
> include/linux/mmc/dw_mmc.h | 5 +
> 8 files changed, 349 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
> create mode 100644 drivers/mmc/host/dw_mmc-zx.c
> create mode 100644 drivers/mmc/host/dw_mmc-zx.h
>
> --
> 1.9.1
>
Hi Rob & Mark,
Could you help act DT patches in this set?
Thank you!
Jun
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^ permalink raw reply
* [PATCH 12/12] gpu: ipu-v3: Add smfc and ic client devices
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Adds IPU client devices for the SMFC and IC task units.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
drivers/gpu/ipu-v3/ipu-common.c | 87 +++++++++++++++++++++++++++++++++++++++--
include/video/imx-ipu-v3.h | 3 ++
2 files changed, 87 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index b6ca36b..729581d 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1161,18 +1161,77 @@ static struct ipu_platform_reg client_reg[] = {
.pdata = {
.type = IPU_CSI,
.csi = 0,
- .dma[0] = IPUV3_CHANNEL_CSI0,
- .dma[1] = -EINVAL,
+ .dma[0] = -EINVAL,
},
.name = "imx-ipuv3-csi",
}, {
.pdata = {
.type = IPU_CSI,
.csi = 1,
+ .dma[0] = -EINVAL,
+ },
+ .name = "imx-ipuv3-csi",
+ }, {
+ .pdata = {
+ .type = IPU_SMFC,
+ .smfc = 0,
+ .dma[0] = IPUV3_CHANNEL_CSI0,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-smfc",
+ }, {
+ .pdata = {
+ .type = IPU_SMFC,
+ .smfc = 1,
.dma[0] = IPUV3_CHANNEL_CSI1,
.dma[1] = -EINVAL,
},
- .name = "imx-ipuv3-csi",
+ .name = "imx-ipuv3-smfc",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_ENCODER,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PRP_ENC_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_VIEWFINDER,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PRP_VF_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 0,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 1,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
+ }, {
+ .pdata = {
+ .type = IPU_IC,
+ .ic_task = IC_TASK_POST_PROCESSOR,
+ .ic = 2,
+ .dma[0] = IPUV3_CHANNEL_IC_PP_MEM,
+ .dma[1] = -EINVAL,
+ },
+ .name = "imx-ipuv3-ic",
}, {
.pdata = {
.type = IPU_DI,
@@ -1213,6 +1272,28 @@ of_get_ipu_client_node(struct ipu_soc *ipu, struct ipu_platform_reg *reg)
"ipu%d_csi", ipu->id + 1);
client_id = reg->pdata.csi;
break;
+ case IPU_SMFC:
+ snprintf(node_name, sizeof(node_name), "ipu%d_smfc",
+ ipu->id + 1);
+ client_id = reg->pdata.smfc;
+ break;
+ case IPU_IC:
+ switch (reg->pdata.ic_task) {
+ case IC_TASK_ENCODER:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_prpenc", ipu->id + 1);
+ break;
+ case IC_TASK_VIEWFINDER:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_prpvf", ipu->id + 1);
+ break;
+ case IC_TASK_POST_PROCESSOR:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_ic_pp", ipu->id + 1);
+ break;
+ }
+ client_id = reg->pdata.ic;
+ break;
case IPU_DI:
snprintf(node_name, sizeof(node_name),
"ipu%d_di", ipu->id + 1);
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 7709af7..4e70ca4 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -418,6 +418,9 @@ int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
struct ipu_client_platformdata {
enum ipu_unit_type type;
int csi;
+ int smfc;
+ int ic_task;
+ int ic;
int di;
int dc;
int dp;
--
2.7.4
^ permalink raw reply related
* [PATCH 11/12] gpu: ipu-v3: lookup ipu client nodes by name
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
tomi.valkeinen-l0cyMroinI0, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
To allow for IPU clients containing multiple ports, they are no longer
a single port node name, but have a name of the format
"ipu<id>_<unit>". So we can no longer use of_graph_get_port_by_id()
to lookup the client node.
Create the function of_get_ipu_client_node() that looks up the client
node by node name and unit id. The ipu_unit_type enumeration is added
to the client_reg[] entries to compose the node names.
Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
drivers/gpu/ipu-v3/ipu-common.c | 55 +++++++++++++++++++++++++++++++++++------
1 file changed, 47 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/ipu-v3/ipu-common.c b/drivers/gpu/ipu-v3/ipu-common.c
index 97218af..b6ca36b 100644
--- a/drivers/gpu/ipu-v3/ipu-common.c
+++ b/drivers/gpu/ipu-v3/ipu-common.c
@@ -1159,6 +1159,7 @@ struct ipu_platform_reg {
static struct ipu_platform_reg client_reg[] = {
{
.pdata = {
+ .type = IPU_CSI,
.csi = 0,
.dma[0] = IPUV3_CHANNEL_CSI0,
.dma[1] = -EINVAL,
@@ -1166,6 +1167,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-csi",
}, {
.pdata = {
+ .type = IPU_CSI,
.csi = 1,
.dma[0] = IPUV3_CHANNEL_CSI1,
.dma[1] = -EINVAL,
@@ -1173,6 +1175,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-csi",
}, {
.pdata = {
+ .type = IPU_DI,
.di = 0,
.dc = 5,
.dp = IPU_DP_FLOW_SYNC_BG,
@@ -1182,6 +1185,7 @@ static struct ipu_platform_reg client_reg[] = {
.name = "imx-ipuv3-crtc",
}, {
.pdata = {
+ .type = IPU_DI,
.di = 1,
.dc = 1,
.dp = -EINVAL,
@@ -1195,6 +1199,46 @@ static struct ipu_platform_reg client_reg[] = {
static DEFINE_MUTEX(ipu_client_id_mutex);
static int ipu_client_id;
+static struct device_node *
+of_get_ipu_client_node(struct ipu_soc *ipu, struct ipu_platform_reg *reg)
+{
+ struct device *dev = ipu->dev;
+ struct device_node *client;
+ char node_name[32];
+ u32 id, client_id = 0;
+
+ switch (reg->pdata.type) {
+ case IPU_CSI:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_csi", ipu->id + 1);
+ client_id = reg->pdata.csi;
+ break;
+ case IPU_DI:
+ snprintf(node_name, sizeof(node_name),
+ "ipu%d_di", ipu->id + 1);
+ client_id = reg->pdata.di;
+ break;
+ default:
+ client = NULL;
+ goto out;
+ }
+
+ for_each_child_of_node(dev->of_node, client) {
+ if (client->name &&
+ (of_node_cmp(client->name, node_name) == 0)) {
+ of_property_read_u32(client, "reg", &id);
+ if (id == client_id)
+ break;
+ }
+ }
+out:
+ if (!client)
+ dev_info(dev, "no %s%d node in %s, not using %s%d\n",
+ node_name, client_id, dev->of_node->full_name,
+ node_name, client_id);
+ return client;
+}
+
static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
{
struct device *dev = ipu->dev;
@@ -1211,15 +1255,10 @@ static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
struct platform_device *pdev;
struct device_node *of_node;
- /* Associate subdevice with the corresponding port node */
- of_node = of_graph_get_port_by_id(dev->of_node, i);
- if (!of_node) {
- dev_info(dev,
- "no port@%d node in %s, not using %s%d\n",
- i, dev->of_node->full_name,
- (i / 2) ? "DI" : "CSI", i % 2);
+ /* Associate subdevice with the corresponding client node */
+ of_node = of_get_ipu_client_node(ipu, reg);
+ if (!of_node)
continue;
- }
pdev = platform_device_alloc(reg->name, id++);
if (!pdev) {
--
2.7.4
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^ permalink raw reply related
* [PATCH 10/12] gpu: ipu-v3: Add ipu_unit_type enumeration
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Adds an enumeration of the major IPUv3 subunits. Provide that info
in struct ipu_client_platformdata to more easily determine the IPU
client type.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
include/video/imx-ipu-v3.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/include/video/imx-ipu-v3.h b/include/video/imx-ipu-v3.h
index 53cd07c..7709af7 100644
--- a/include/video/imx-ipu-v3.h
+++ b/include/video/imx-ipu-v3.h
@@ -28,6 +28,23 @@ enum ipuv3_type {
IPUV3H,
};
+/*
+ * Enumeration of the major IPU subunits
+ */
+enum ipu_unit_type {
+ IPU_IDMAC = 0,
+ IPU_CM,
+ IPU_CSI,
+ IPU_SMFC,
+ IPU_IC,
+ IPU_VDI,
+ IPU_IRT,
+ IPU_DC,
+ IPU_DI,
+ IPU_DP,
+ IPU_DMFC,
+};
+
#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
/*
@@ -399,6 +416,7 @@ int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
bool hflip, bool vflip);
struct ipu_client_platformdata {
+ enum ipu_unit_type type;
int csi;
int di;
int dc;
--
2.7.4
^ permalink raw reply related
* [PATCH 09/12] ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
tomi.valkeinen-l0cyMroinI0, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Enables the ADV7180 decoder sensor. The ADV7180 connects to the
parallel-bus mux input on ipu1_csi0_mux.
On the sabreauto, two analog video inputs are routed to the ADV7180,
composite on Ain1, and composite on Ain3. Those inputs are defined
via inputs and input-names under the ADV7180 node. The ADV7180 power
pin is via max7310_b port expander.
Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 62 ++++++++++++++++++++++++++++++++
1 file changed, 62 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index d74882a..9222026 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -147,10 +147,48 @@
gpio-controller;
#gpio-cells = <2>;
};
+
+ camera: adv7180@21 {
+ compatible = "adi,adv7180";
+ reg = <0x21>;
+ powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
+ interrupt-parent = <&gpio1>;
+ interrupts = <27 0x8>;
+ inputs = <0x00 0x02>;
+ input-names = "ADV7180 Composite on Ain1",
+ "ADV7180 Composite on Ain3";
+
+ port {
+ adv7180_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ };
+ };
+ };
};
};
};
+&ipu1_smfc0 {
+ fim {
+ enable = <1>;
+ };
+};
+
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
+ bus-width = <8>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&clks {
assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
<&clks IMX6QDL_PLL4_BYPASS>,
@@ -451,6 +489,30 @@
>;
};
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
+ MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
+ MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
+ MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
+ MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
+ MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
+ MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
+ MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 08/12] ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
tomi.valkeinen-l0cyMroinI0, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Add pinctrl groups for both GPT input capture channels.
Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 944a4fa..d74882a 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -457,6 +457,18 @@
>;
};
+ pinctrl_gpt_input_capture0: gptinputcapture0grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x80000000
+ >;
+ };
+
+ pinctrl_gpt_input_capture1: gptinputcapture1grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x80000000
+ >;
+ };
+
pinctrl_spdif: spdifgrp {
fsl,pins = <
MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 07/12] ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
tomi.valkeinen-l0cyMroinI0, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
The reset pin to the port expander chip (MAX7310) is controlled by a gpio,
so define a reset-gpios property to control it. There are three MAX7310's
on the SabreAuto CPU card (max7310_[abc]), but all use the same pin for
their reset. Since all can't acquire the same pin, assign it to max7310_b,
that chip is needed by more functions (usb and adv7180).
Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 043d20c..944a4fa 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -136,6 +136,9 @@
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_max7310>;
+ reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
max7310_c: gpio@34 {
@@ -442,6 +445,12 @@
>;
};
+ pinctrl_max7310: max7310grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 06/12] ARM: dts: imx6-sabreauto: create i2cmux for i2c3
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
The sabreauto uses a steering pin to select between the SDA signal on
i2c3 bus, and a data-in pin for an SPI NOR chip. Use i2cmux to control
this steering pin. Idle state of the i2cmux selects SPI NOR. This is not
a classic way to use i2cmux, since one side of the mux selects something
other than an i2c bus, but it works and is probably the cleanest
solution. Note that if one thread is attempting to access SPI NOR while
another thread is accessing i2c3, the SPI NOR access will fail since the
i2cmux has selected the SDA pin rather than SPI NOR data-in. This couldn't
be avoided in any case, the board is not designed to allow concurrent
i2c3 and SPI NOR functions (and the default device-tree does not enable
SPI NOR anyway).
Devices hanging off i2c3 should now be defined under i2cmux, so
that the steering pin can be properly controlled to access those
devices. The port expanders (MAX7310) are thus moved into i2cmux.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 65 +++++++++++++++++++++-----------
1 file changed, 44 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index e000e6f..043d20c 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -108,6 +108,44 @@
default-brightness-level = <7>;
status = "okay";
};
+
+ i2cmux {
+ compatible = "i2c-mux-gpio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3mux>;
+ mux-gpios = <&gpio5 4 0>;
+ i2c-parent = <&i2c3>;
+ idle-state = <0>;
+
+ i2c@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ max7310_a: gpio@30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio@32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_c: gpio@34 {
+ compatible = "maxim,max7310";
+ reg = <0x34>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+ };
};
&clks {
@@ -291,27 +329,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
status = "okay";
-
- max7310_a: gpio@30 {
- compatible = "maxim,max7310";
- reg = <0x30>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_b: gpio@32 {
- compatible = "maxim,max7310";
- reg = <0x32>;
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- max7310_c: gpio@34 {
- compatible = "maxim,max7310";
- reg = <0x34>;
- gpio-controller;
- #gpio-cells = <2>;
- };
};
&iomuxc {
@@ -419,6 +436,12 @@
>;
};
+ pinctrl_i2c3mux: i2c3muxgrp {
+ fsl,pins = <
+ MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x80000000
+ >;
+ };
+
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
--
2.7.4
^ permalink raw reply related
* [PATCH 05/12] ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo-DgEjT+Ai2ygdnm+yROfE0A, kernel-bIcnvbaLZ9MEGnE8C9+IrQ,
fabio.estevam-3arQi8VN3Tc, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, linux-I+IVW8TIWO2tmTQ+vhA3Yw,
tomi.valkeinen-l0cyMroinI0, p.zabel-bIcnvbaLZ9MEGnE8C9+IrQ
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-fbdev-u79uwXL29TY76Z2rM5mHXA,
dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Until the OV5652 sensor module compatible with the SabreSD becomes
available for testing, the ov5642 node is currently disabled.
Signed-off-by: Steve Longerbeam <steve_longerbeam-nmGgyN9QBj3QT0dZR+AlfA@public.gmane.org>
---
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6q-sabresd.dts | 5 ++
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++++++++++++++++++++++++++++-
3 files changed, 123 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabresd.dts b/arch/arm/boot/dts/imx6dl-sabresd.dts
index 1e45f2f..6cf7a50 100644
--- a/arch/arm/boot/dts/imx6dl-sabresd.dts
+++ b/arch/arm/boot/dts/imx6dl-sabresd.dts
@@ -15,3 +15,8 @@
model = "Freescale i.MX6 DualLite SABRE Smart Device Board";
compatible = "fsl,imx6dl-sabresd", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabresd.dts b/arch/arm/boot/dts/imx6q-sabresd.dts
index 9cbdfe7..8c1d7ad 100644
--- a/arch/arm/boot/dts/imx6q-sabresd.dts
+++ b/arch/arm/boot/dts/imx6q-sabresd.dts
@@ -23,3 +23,8 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 8e9e0d9..e36e1e7 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -10,6 +10,7 @@
* http://www.gnu.org/copyleft/gpl.html
*/
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -146,6 +147,33 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vsync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -214,7 +242,33 @@
0x8014 /* 4:FN_DMICCDAT */
0x0000 /* 5:Default */
>;
- };
+ };
+
+ camera: ov5642@3c {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ reg = <0x3c>;
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* SD1_DAT0 */
+ reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* SD1_DAT1 */
+ status = "disabled";
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
};
&i2c2 {
@@ -322,6 +376,34 @@
};
};
};
+
+ mipi_camera: ov5640@3c {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ reg = <0x3c>;
+ clocks = <&clks IMX6QDL_CLK_CKO>;
+ clock-names = "xclk";
+ xclk = <24000000>;
+ DOVDD-supply = <&vgen4_reg>; /* 1.8v */
+ AVDD-supply = <&vgen5_reg>; /* 2.8v, rev C board is VGEN3
+ rev B board is VGEN5 */
+ DVDD-supply = <&vgen2_reg>; /* 1.5v*/
+ pwdn-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; /* SD1_DAT2 */
+ reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* SD1_CLK */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -426,6 +508,36 @@
>;
};
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT2__GPIO1_IO19 0x80000000
+ MX6QDL_PAD_SD1_CLK__GPIO1_IO20 0x80000000
+ >;
+ };
+
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_SD1_DAT1__GPIO1_IO17 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ >;
+ };
+
pinctrl_pcie: pciegrp {
fsl,pins = <
MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b0
--
2.7.4
--
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^ permalink raw reply related
* [PATCH 04/12] ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: devicetree, linux-fbdev, Steve Longerbeam, linux-kernel,
dri-devel, linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Enables the OV5642 parallel-bus sensor, and the OV5640 MIPI CSI-2 sensor.
Both hang off the same i2c2 bus, so they require different (and non-
default) i2c slave addresses.
The OV5642 connects to the parallel-bus mux input port on ipu1_csi0_mux.
The OV5640 connects to the input port on the MIPI CSI-2 receiver on
mipi_csi. It is set to transmit over MIPI virtual channel 1.
Note there is a pin conflict with GPIO6. This pin functions as a power
input pin to the OV5642, but ENET uses it as the h/w workaround for
erratum ERR006687, to wake-up the ARM cores on normal RX and TX packet
done events (see 6261c4c8). So workaround 6261c4c8 is reverted here to
support the OV5642, and the "fsl,err006687-workaround-present" boolean
also must be removed. The result is that the CPUidle driver will no longer
allow entering the deep idle states on the sabrelite.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 ++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 ++
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 ++++++++++++++++++++++++++++++-
3 files changed, 129 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-sabrelite.dts b/arch/arm/boot/dts/imx6dl-sabrelite.dts
index 0f06ca5..fec2524 100644
--- a/arch/arm/boot/dts/imx6dl-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6dl-sabrelite.dts
@@ -48,3 +48,8 @@
model = "Freescale i.MX6 DualLite SABRE Lite Board";
compatible = "fsl,imx6dl-sabrelite", "fsl,imx6dl";
};
+
+&ipu1_csi1_from_ipu1_csi1_mux {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
diff --git a/arch/arm/boot/dts/imx6q-sabrelite.dts b/arch/arm/boot/dts/imx6q-sabrelite.dts
index 66d10d8..9e2d26d 100644
--- a/arch/arm/boot/dts/imx6q-sabrelite.dts
+++ b/arch/arm/boot/dts/imx6q-sabrelite.dts
@@ -52,3 +52,9 @@
&sata {
status = "okay";
};
+
+&ipu1_csi1_from_mipi_vc1 {
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 81dd6cd..d7fcb1a2 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -39,6 +39,8 @@
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
+
+#include <dt-bindings/clock/imx6qdl-clock.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
@@ -96,6 +98,15 @@
};
};
+ mipi_xclk: mipi_xclk {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <22000000>;
+ clock-output-names = "mipi_pwm3";
+ pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
+ status = "okay";
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -220,6 +231,22 @@
};
};
+&ipu1_csi0_from_ipu1_csi0_mux {
+ bus-width = <8>;
+ data-shift = <12>; /* Lines 19:12 used */
+ hsync-active = <1>;
+ vync-active = <1>;
+};
+
+&ipu1_csi0_mux_from_parallel_sensor {
+ remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
+};
+
+&ipu1_csi0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ipu1_csi0>;
+};
+
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
@@ -271,9 +298,6 @@
txd1-skew-ps = <0>;
txd2-skew-ps = <0>;
txd3-skew-ps = <0>;
- interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
- <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
- fsl,err006687-workaround-present;
status = "okay";
};
@@ -302,6 +326,52 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c2>;
status = "okay";
+
+ camera: ov5642@42 {
+ compatible = "ovti,ov5642";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5642>;
+ clocks = <&clks IMX6QDL_CLK_CKO2>;
+ clock-names = "xclk";
+ reg = <0x42>;
+ xclk = <24000000>;
+ reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
+ pwdn-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
+ gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
+
+ port {
+ ov5642_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
+ bus-width = <8>;
+ hsync-active = <1>;
+ vsync-active = <1>;
+ };
+ };
+ };
+
+ mipi_camera: ov5640@40 {
+ compatible = "ovti,ov5640_mipi";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ov5640>;
+ clocks = <&mipi_xclk>;
+ clock-names = "xclk";
+ reg = <0x40>;
+ xclk = <22000000>;
+ reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
+ pwdn-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
+
+ port {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov5640_to_mipi_csi: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&mipi_csi_from_mipi_sensor>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+ };
+ };
+ };
};
&i2c3 {
@@ -374,7 +444,6 @@
MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
/* Phy reset */
MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
- MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
>;
};
@@ -449,6 +518,39 @@
>;
};
+ pinctrl_ov5642: ov5642grp {
+ fsl,pins = <
+ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000
+ MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x80000000
+ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000
+ MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x80000000
+ >;
+ };
+
+ pinctrl_ipu1_csi0: ipu1grp-csi0 {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
+ MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
+ MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
+ MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
+ MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
+ MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
+ MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
+ MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
+ MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
+ MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
+ MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
+ MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
+ >;
+ };
+
+ pinctrl_ov5640: ov5640grp {
+ fsl,pins = <
+ MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
+ MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
+ >;
+ };
+
pinctrl_pwm1: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
@@ -605,3 +707,15 @@
vmmc-supply = <®_3p3v>;
status = "okay";
};
+
+&mipi_csi {
+ status = "okay";
+};
+
+/* Incoming port from sensor */
+&mipi_csi_from_mipi_sensor {
+ remote-endpoint = <&ov5640_to_mipi_csi>;
+ data-lanes = <0 1>;
+ clock-lanes = <2>;
+};
+
--
2.7.4
^ permalink raw reply related
* [PATCH 03/12] ARM: dts: imx6qdl: add video capture devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
From: Philipp Zabel <p.zabel@pengutronix.de>
This patch adds the IPU subunit devices involved in video capture and
image conversion, and defines all the possible hardware connections
between them via OF graphs.
External to the IPU:
Video input multiplexers are defined that multiplex inputs from camera
sensors and the MIPI-CSI2 gasket, to the IPU CSIs.
On i.MX6Q/D two two-input multiplexers in front of IPU1 CSI0 and IPU2 CSI1
allow to select between CSI0/1 parallel input pads and the MIPI CSI-2 virtual
channels 0/3.
On i.MX6DL/S two five-input multiplexers in front of IPU1 CSI0 and IPU1 CSI1
allow to select between CSI0/1 parallel input pads and any of the four MIPI
CSI-2 virtual channels.
Internal to the IPU:
The IPU CSI, SMFC, IC-PRPENC, IC-PRPVF, and IC-PP subunits are added
as children of the IPUs, along with the hardware-supported connections
between them.
Finally, a media device node is defined. A video camera interface
and mem2mem device are defined as children of the media device.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
---
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++++++
arch/arm/boot/dts/imx6q.dtsi | 487 +++++++++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/imx6qdl.dtsi | 368 +++++++++++++++++++++++++++++++
3 files changed, 1045 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 1ade195..4bab076 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -109,6 +109,120 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>;
};
+
+ ipu1_csi0_mux: ipu1_csi0_mux@34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x07>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ipu1_csi0_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu1_csi1_mux: ipu1_csi1_mux@34 {
+ compatible = "imx-video-mux";
+ reg = <0x34 0x38>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <5>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi1_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi1_mux_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi1_mux_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ ipu1_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ ipu1_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ ipu1_csi1_mux_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -184,3 +298,79 @@
&vpu {
compatible = "fsl,imx6dl-vpu", "cnm,coda960";
};
+
+&ipu1_csi1 {
+ port@0 {
+ reg = <0>;
+ ipu1_csi1_from_ipu1_csi1_mux: endpoint {
+ remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>;
+ };
+ };
+};
+
+&mipi_csi {
+ sink-ports = <1>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+
+ mipi_vc0_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc1_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>;
+ };
+
+ mipi_vc1_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc2_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>;
+ };
+
+ mipi_vc2_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ mipi_vc3_to_ipu1_csi0_mux: endpoint@0 {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>;
+ };
+
+ mipi_vc3_to_ipu1_csi1_mux: endpoint@1 {
+ remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index 2b261ba..a0602c5 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -142,11 +142,270 @@
resets = <&src 4>;
ipu2_csi0: ipu2_csi@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_csi0_from_mipi_vc2: endpoint {
+ remote-endpoint = <&mipi_vc2_to_ipu2_csi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi0>;
+ };
+ ipu2_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu2_csi1: ipu2_csi@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_csi1_from_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_to_ipu2_csi1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_csi1>;
+ };
+ ipu2_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu2_smfc0: ipu2_smfc@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_to_smfc0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_smfc0>;
+ };
+ ipu2_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc0>;
+ };
+ ipu2_smfc0_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc0>;
+ };
+ };
+ };
+
+ ipu2_smfc1: ipu2_smfc@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_to_smfc1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_smfc1>;
+ };
+ ipu2_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_smfc1>;
+ };
+ ipu2_smfc1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_smfc1>;
+ };
+ };
+ };
+
+ ipu2_ic_prpenc: ipu2_ic_prpenc@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_ic_prpenc_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpenc>;
+ };
+ ipu2_ic_prpenc_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu2_ic_prpvf: ipu2_ic_prpvf@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu2_csi0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu2_csi1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_prpvf>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_ic_prpvf_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_from_ic_prpvf>;
+ };
+ ipu2_ic_prpvf_to_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu2_ic_pp0: ipu2_ic_pp@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_ic_pp0_from_m2m1: m2m1-endpoint {
+ remote-endpoint = <&m2m1_to_ic_pp0>;
+ };
+ ipu2_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_ic_pp0_to_m2m1: endpoint {
+ remote-endpoint = <&m2m1_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu2_ic_pp1: ipu2_ic_pp@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_ic_pp1>;
+ };
+ ipu2_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_ic_pp1_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp1>;
+ };
+ ipu2_ic_pp1_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu2_ic_pp2: ipu2_ic_pp@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port@0 {
+ reg = <0>;
+ ipu2_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_ic_pp2>;
+ };
+ ipu2_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu2_ic_pp2_to_camif2: camif2-endpoint {
+ remote-endpoint = <&camif2_from_ic_pp2>;
+ };
+ ipu2_ic_pp2_to_camif3: camif3-endpoint {
+ remote-endpoint = <&camif3_from_ic_pp2>;
+ };
+ };
};
ipu2_di0: ipu2_di@0 {
@@ -207,6 +466,73 @@
compatible = "fsl,imx-gpu-subsystem";
cores = <&gpu_2d>, <&gpu_3d>, <&gpu_vg>;
};
+
+
+ ipu1_csi0_mux: ipu1_csi0_mux@4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x80000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu1_csi0_mux_from_mipi_vc0: endpoint {
+ remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu1_csi0_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu1_csi0_mux_to_ipu1_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>;
+ };
+ };
+ };
+
+ ipu2_csi1_mux: ipu2_csi1_mux@4 {
+ compatible = "imx-video-mux";
+ reg = <0x04 0x100000>;
+ gpr = <&gpr>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+
+ port@0 {
+ reg = <0>;
+
+ ipu2_csi1_mux_from_mipi_vc3: endpoint {
+ remote-endpoint = <&mipi_vc3_to_ipu2_csi1_mux>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ ipu2_csi1_mux_from_parallel_sensor: endpoint {
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ ipu2_csi1_mux_to_ipu2_csi1: endpoint {
+ remote-endpoint = <&ipu2_csi1_from_ipu2_csi1_mux>;
+ };
+ };
+ };
};
&gpio1 {
@@ -266,6 +592,15 @@
};
};
+&ipu1_csi1 {
+ port@0 {
+ reg = <0>;
+ ipu1_csi1_from_mipi_vc1: endpoint {
+ remote-endpoint = <&mipi_vc1_to_ipu1_csi1>;
+ };
+ };
+};
+
&ldb {
clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
<&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
@@ -312,6 +647,49 @@
};
};
+&mipi_csi {
+ sink-ports = <1>;
+
+ port@0 {
+ reg = <0>;
+
+ mipi_csi_from_mipi_sensor: endpoint {
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mipi_vc0_to_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+
+ mipi_vc1_to_ipu1_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_from_mipi_vc1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+
+ mipi_vc2_to_ipu2_csi0: endpoint {
+ remote-endpoint = <&ipu2_csi0_from_mipi_vc2>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ mipi_vc3_to_ipu2_csi1_mux: endpoint {
+ remote-endpoint = <&ipu2_csi1_mux_from_mipi_vc3>;
+ };
+ };
+};
+
&mipi_dsi {
ports {
port@2 {
@@ -335,3 +713,112 @@
&vpu {
compatible = "fsl,imx6q-vpu", "cnm,coda960";
};
+
+&media0 {
+ m2m1: m2m@1 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ m2m1_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_to_m2m1>;
+ };
+ m2m1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_m2m1>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ m2m1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_from_m2m1>;
+ };
+ m2m1_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu2_ic_pp0_from_m2m1>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+
+ camif2: camif@2 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <2>;
+
+ port@0 {
+ reg = <0>;
+ camif2_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif2>;
+ };
+ camif2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif2>;
+ };
+ camif2_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif2>;
+ };
+ camif2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif2>;
+ };
+ camif2_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif2>;
+ };
+ camif2_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ camif3: camif@3 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <3>;
+
+ port@0 {
+ reg = <0>;
+ camif3_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu2_smfc0_to_camif3>;
+ };
+ camif3_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu2_smfc1_to_camif3>;
+ };
+ camif3_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu2_ic_prpenc_to_camif3>;
+ };
+ camif3_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu2_ic_prpvf_to_camif3>;
+ };
+ camif3_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu2_ic_pp1_to_camif3>;
+ };
+ camif3_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu2_ic_pp2_to_camif3>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 2465187..ea1e2f3 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1123,6 +1123,8 @@
mipi_csi: mipi@021dc000 {
compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
interrupts = <0 100 0x04>, <0 101 0x04>;
clocks = <&clks IMX6QDL_CLK_HSI_TX>,
<&clks IMX6QDL_CLK_VIDEO_27M>,
@@ -1227,11 +1229,263 @@
resets = <&src 2>;
ipu1_csi0: ipu1_csi@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_csi0_from_ipu1_csi0_mux: endpoint {
+ remote-endpoint = <&ipu1_csi0_mux_to_ipu1_csi0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_csi0_to_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi0>;
+ };
+ ipu1_csi0_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi0>;
+ };
+ };
};
ipu1_csi1: ipu1_csi@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port@1 {
+ reg = <1>;
+ ipu1_csi1_to_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpvf: prendpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_csi1>;
+ };
+ ipu1_csi1_to_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_from_csi1>;
+ };
+ };
+ };
+
+ ipu1_smfc0: ipu1_smfc@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_smfc0_from_csi0: endpoint {
+ remote-endpoint = <&ipu1_csi0_to_smfc0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_smfc0_to_ic_pp1: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_smfc0>;
+ };
+ ipu1_smfc0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc0>;
+ };
+ ipu1_smfc0_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc0>;
+ };
+ };
+ };
+
+ ipu1_smfc1: ipu1_smfc@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_smfc1_from_csi1: endpoint {
+ remote-endpoint = <&ipu1_csi1_to_smfc1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_smfc1_to_ic_pp2: pp-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_smfc1>;
+ };
+ ipu1_smfc1_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_smfc1>;
+ };
+ ipu1_smfc1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_smfc1>;
+ };
+ };
+ };
+
+ ipu1_ic_prpenc: ipu1_ic_prpenc@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_ic_prpenc_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpenc>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_ic_prpenc_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpenc>;
+ };
+ ipu1_ic_prpenc_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpenc>;
+ };
+ };
+ };
+
+ ipu1_ic_prpvf: ipu1_ic_prpvf@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_ic_prpvf_from_csi0: csi0-endpoint {
+ remote-endpoint = <&ipu1_csi0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_csi1: csi1-endpoint {
+ remote-endpoint = <&ipu1_csi1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_prpvf>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_ic_prpvf_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_from_ic_prpvf>;
+ };
+ ipu1_ic_prpvf_to_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_from_ic_prpvf>;
+ };
+ };
+ };
+
+ ipu1_ic_pp0: ipu1_ic_pp@0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_ic_pp0_from_m2m0: m2m0-endpoint {
+ remote-endpoint = <&m2m0_to_ic_pp0>;
+ };
+ ipu1_ic_pp0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_ic_pp0_to_m2m0: endpoint {
+ remote-endpoint = <&m2m0_from_ic_pp0>;
+ };
+ };
+ };
+
+ ipu1_ic_pp1: ipu1_ic_pp@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_ic_pp1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_ic_pp1>;
+ };
+ ipu1_ic_pp1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_ic_pp1_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp1>;
+ };
+ ipu1_ic_pp1_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp1>;
+ };
+ };
+ };
+
+ ipu1_ic_pp2: ipu1_ic_pp@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sink-ports = <1>;
+ reg = <2>;
+
+ port@0 {
+ reg = <0>;
+ ipu1_ic_pp2_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_ic_pp2>;
+ };
+ ipu1_ic_pp2_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_ic_pp2>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ ipu1_ic_pp2_to_camif0: camif0-endpoint {
+ remote-endpoint = <&camif0_from_ic_pp2>;
+ };
+ ipu1_ic_pp2_to_camif1: camif1-endpoint {
+ remote-endpoint = <&camif1_from_ic_pp2>;
+ };
+ };
};
ipu1_di0: ipu1_di@0 {
@@ -1284,5 +1538,119 @@
};
};
};
+
+ media0: media@0 {
+ compatible = "fsl,imx-media", "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ m2m0: m2m@0 {
+ compatible = "fsl,imx-media-mem2mem";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <2>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ m2m0_from_ic_pp0: endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_to_m2m0>;
+ };
+ m2m0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_m2m0>;
+ };
+ };
+
+ port@2 {
+ reg = <2>;
+ m2m0_to_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_from_m2m0>;
+ };
+ m2m0_to_ic_pp0: pp0-endpoint {
+ remote-endpoint = <&ipu1_ic_pp0_from_m2m0>;
+ };
+ };
+
+ port@3 {
+ reg = <3>;
+ };
+ };
+
+ camif0: camif@0 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <0>;
+
+ port@0 {
+ reg = <0>;
+ camif0_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif0>;
+ };
+ camif0_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif0>;
+ };
+ camif0_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif0>;
+ };
+ camif0_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif0>;
+ };
+ camif0_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif0>;
+ };
+ camif0_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif0>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ camif1: camif@1 {
+ compatible = "fsl,imx-media-camif";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ sink-ports = <1>;
+ reg = <1>;
+
+ port@0 {
+ reg = <0>;
+ camif1_from_smfc0: smfc0-endpoint {
+ remote-endpoint = <&ipu1_smfc0_to_camif1>;
+ };
+ camif1_from_smfc1: smfc1-endpoint {
+ remote-endpoint = <&ipu1_smfc1_to_camif1>;
+ };
+ camif1_from_ic_prpenc: prpenc-endpoint {
+ remote-endpoint = <&ipu1_ic_prpenc_to_camif1>;
+ };
+ camif1_from_ic_prpvf: prpvf-endpoint {
+ remote-endpoint = <&ipu1_ic_prpvf_to_camif1>;
+ };
+ camif1_from_ic_pp1: pp1-endpoint {
+ remote-endpoint = <&ipu1_ic_pp1_to_camif1>;
+ };
+ camif1_from_ic_pp2: pp2-endpoint {
+ remote-endpoint = <&ipu1_ic_pp2_to_camif1>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+ };
};
};
--
2.7.4
^ permalink raw reply related
* [PATCH 02/12] ARM: dts: imx6qdl: rename ipu client nodes
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
To allow for IPU client devices that are composed of more than one
port for input and output (SMFC and IC), change the nodes from being
a single port node to nodes that can contain multiple ports. Rename
the nodes to use the following format: "ipu<id>_<subunit>".
The IPUv3 driver will then need to lookup the client nodes by name
rather than by port id.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6q.dtsi | 12 ++++++------
arch/arm/boot/dts/imx6qdl.dtsi | 12 ++++++------
2 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index e9a5d0b..2b261ba 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -141,18 +141,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 4>;
- ipu2_csi0: port@0 {
+ ipu2_csi0: ipu2_csi@0 {
reg = <0>;
};
- ipu2_csi1: port@1 {
+ ipu2_csi1: ipu2_csi@1 {
reg = <1>;
};
- ipu2_di0: port@2 {
+ ipu2_di0: ipu2_di@0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu2_di0_disp0: disp0-endpoint {
};
@@ -174,10 +174,10 @@
};
};
- ipu2_di1: port@3 {
+ ipu2_di1: ipu2_di@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu2_di1_hdmi: hdmi-endpoint {
remote-endpoint = <&hdmi_mux_3>;
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e01e5d5..2465187 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1226,18 +1226,18 @@
clock-names = "bus", "di0", "di1";
resets = <&src 2>;
- ipu1_csi0: port@0 {
+ ipu1_csi0: ipu1_csi@0 {
reg = <0>;
};
- ipu1_csi1: port@1 {
+ ipu1_csi1: ipu1_csi@1 {
reg = <1>;
};
- ipu1_di0: port@2 {
+ ipu1_di0: ipu1_di@0 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <2>;
+ reg = <0>;
ipu1_di0_disp0: disp0-endpoint {
};
@@ -1259,10 +1259,10 @@
};
};
- ipu1_di1: port@3 {
+ ipu1_di1: ipu1_di@1 {
#address-cells = <1>;
#size-cells = <0>;
- reg = <3>;
+ reg = <1>;
ipu1_di1_disp1: disp1-endpoint {
};
--
2.7.4
^ permalink raw reply related
* [PATCH 01/12] ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: devicetree, linux-fbdev, Steve Longerbeam, linux-kernel,
dri-devel, linux-arm-kernel
In-Reply-To: <1481158673-15937-1-git-send-email-steve_longerbeam@mentor.com>
Add to the MIPI CSI2 receiver node: compatible string, interrupt sources,
clocks.
Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
---
arch/arm/boot/dts/imx6qdl.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index b13b0b2..e01e5d5 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1121,7 +1121,14 @@
};
mipi_csi: mipi@021dc000 {
+ compatible = "fsl,imx-mipi-csi2";
reg = <0x021dc000 0x4000>;
+ interrupts = <0 100 0x04>, <0 101 0x04>;
+ clocks = <&clks IMX6QDL_CLK_HSI_TX>,
+ <&clks IMX6QDL_CLK_VIDEO_27M>,
+ <&clks IMX6QDL_CLK_EIM_SEL>;
+ clock-names = "dphy_clk", "cfg_clk", "pix_clk";
+ status = "disabled";
};
mipi_dsi: mipi@021e0000 {
--
2.7.4
^ permalink raw reply related
* [PATCH 00/12] i.MX media devices and connections
From: Steve Longerbeam @ 2016-12-08 0:57 UTC (permalink / raw)
To: shawnguo, kernel, fabio.estevam, robh+dt, mark.rutland, linux,
tomi.valkeinen, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-fbdev,
dri-devel, Steve Longerbeam
Hi Philipp, Sascha, Shawn, et al,
I've been working for the past few months on a media driver for i.MX.
In addition to the media entities for the IPU-external units involved
with video capture (video mux and MIPI CSI-2 receiver), I've created
media entities for the IPU CSI, SMFC, and IC subunits. The IC entities
carry out scaling, CSC, horizontal/vertical flip, and rotation. In
addition, the IC-PRPVF entity carries out motion compensated
de-interlace.
The following series adds the OF device nodes and graphs that define
all the possible hardware connections supported by the i.MX involved
in video capture and image conversion.
Here are some of the pipelines defined by the OF graphs:
CSI -> IC-PRPENC
CSI -> IC-PRPVF
CSI -> IC-PRPVF -> IC-PP
CSI -> SMFC
CSI -> SMFC -> IC-PRPVF
CSI -> SMFC -> IC-PP
CSI -> SMFC -> IC-PRPVF -> IC-PP
You will notice that three IC-PP nodes are defined (ipu1_ic_pp0,
ipu1_ic_pp1, ipu1_ic_pp2, and same for ipu2). The reason for that
is that the IC-PP media entity uses the new ipu-image-conversion
API, which allows for multiple conversion contexts to be created.
Each IC-PP entity thus creates its own conversion context, and there
can be any number of IC-PP entities instantiated as needed by the OF
graph.
Camera sensor nodes are also added for the SabreAuto, SabreSD, and
SabreLite reference platforms.
The media driver is now in fairly good shape. It parses the OF graphs
to create the media pads and links. All the pipelines defined by the
OF graphs have been tested and are working. My media driver work is
at:
git@github.com:slongerbeam/mediatree.git, branch imx-media-staging-md-v2.
For an overview of the pipelines supported and usage notes for the
reference boards, you can refer to Documentation/media/v4l-drivers/imx.rst.
I realize there is collision here with the recent patch series posted by
Philipp, particularly around the video multiplexer and mipi csi-2 receiver
subdevs and OF graphs, as well as v4l2 capture drivers.
Philipp Zabel (1):
ARM: dts: imx6qdl: add video capture devices and connections
Steve Longerbeam (11):
ARM: dts: imx6qdl: Add compatible, clocks, irqs to MIPI CSI-2 node
ARM: dts: imx6qdl: rename ipu client nodes
ARM: dts: imx6-sabrelite: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
ARM: dts: imx6-sabreauto: create i2cmux for i2c3
ARM: dts: imx6-sabreauto: add reset-gpios property for max7310_b
ARM: dts: imx6-sabreauto: add pinctrl for gpt input capture
ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
gpu: ipu-v3: Add ipu_unit_type enumeration
gpu: ipu-v3: lookup ipu client nodes by name
gpu: ipu-v3: Add smfc and ic client devices
arch/arm/boot/dts/imx6dl-sabrelite.dts | 5 +
arch/arm/boot/dts/imx6dl-sabresd.dts | 5 +
arch/arm/boot/dts/imx6dl.dtsi | 190 ++++++++++++
arch/arm/boot/dts/imx6q-sabrelite.dts | 6 +
arch/arm/boot/dts/imx6q-sabresd.dts | 5 +
arch/arm/boot/dts/imx6q.dtsi | 497 ++++++++++++++++++++++++++++++-
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 148 +++++++--
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 122 +++++++-
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 114 ++++++-
arch/arm/boot/dts/imx6qdl.dtsi | 385 +++++++++++++++++++++++-
drivers/gpu/ipu-v3/ipu-common.c | 142 ++++++++-
include/video/imx-ipu-v3.h | 21 ++
12 files changed, 1593 insertions(+), 47 deletions(-)
--
2.7.4
^ permalink raw reply
* Re: [PATCH] ARM: dts: imx7d: fix LCDIF clock assignment
From: Shawn Guo @ 2016-12-08 0:54 UTC (permalink / raw)
To: Olof Johansson
Cc: Arnd Bergmann, Sascha Hauer, Stefan Agner, Mark Rutland,
devicetree, linux-kernel, robh+dt, Peter Chen, Fabio Estevam,
Liu Ying, linux-arm-kernel, Fabio Estevam
In-Reply-To: <20161207205314.GA20203@localhost>
On Wed, Dec 07, 2016 at 12:53:14PM -0800, Olof Johansson wrote:
> Applied, with the fixes line. In the future, please email arm@kernel.org too,
> it's easier to make sure we don't miss it that way.
Noted. Thanks, Olof.
Shawn
^ permalink raw reply
* Re: [PATCH 3/3] clk: keystone: Add sci-clk driver support
From: Stephen Boyd @ 2016-12-08 0:13 UTC (permalink / raw)
To: Tero Kristo
Cc: linux-clk, mturquette, ssantosh, nm, linux-arm-kernel, devicetree
In-Reply-To: <1477053961-27128-4-git-send-email-t-kristo@ti.com>
On 10/21, Tero Kristo wrote:
> diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
> index 6a8ac04..dce08a7 100644
> --- a/drivers/clk/Kconfig
> +++ b/drivers/clk/Kconfig
> @@ -169,6 +169,15 @@ config COMMON_CLK_NXP
> ---help---
> Support for clock providers on NXP platforms.
>
> +config TI_SCI_CLK
> + tristate "TI System Control Interface clock drivers"
> + depends on (TI_SCI_PROTOCOL && COMMON_CLK_KEYSTONE) || COMPILE_TEST
Given that we depend on COMMON_CLK_KEYSTONE (just for the
Makefile dependency?) this should be moved to right below the
COMMON_CLK_KEYSTONE config. And we should consider making a
Kconfig file in drivers/clk/keystone/ to hold both those configs
instead of having them at the toplevel.
> + default TI_SCI_PROTOCOL
> + ---help---
> + This adds the clock driver support over TI System Control Interface.
> + If you wish to use clock resources from the PMMC firmware, say Y.
> + Otherwise, say N.
> +
> config COMMON_CLK_PALMAS
> tristate "Clock driver for TI Palmas devices"
> depends on MFD_PALMAS
> diff --git a/drivers/clk/keystone/Makefile b/drivers/clk/keystone/Makefile
> index 0477cf6..0e7993d 100644
> --- a/drivers/clk/keystone/Makefile
> +++ b/drivers/clk/keystone/Makefile
> @@ -1 +1,2 @@
> obj-y += pll.o gate.o
> +obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o
> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
> new file mode 100644
> index 0000000..f6af5bd
> --- /dev/null
> +++ b/drivers/clk/keystone/sci-clk.c
> @@ -0,0 +1,589 @@
[...]
> +
> +/**
> + * sci_clk_recalc_rate - Get clock rate for a TI SCI clock
> + * @hw: clock to get rate for
> + * @parent_rate: parent rate provided by common clock framework, not used
> + *
> + * Gets the current clock rate of a TI SCI clock. Returns the current
> + * clock rate, or zero in failure.
> + */
> +static unsigned long sci_clk_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct sci_clk *clk = to_sci_clk(hw);
> + u64 freq;
> + int ret;
> +
> + ret = clk->provider->ops->get_freq(clk->provider->sci, clk->dev_id,
> + clk->clk_id, &freq);
> + if (ret) {
> + dev_err(clk->provider->dev,
> + "recalc-rate failed for dev=%d, clk=%d, ret=%d\n",
> + clk->dev_id, clk->clk_id, ret);
> + return 0;
> + }
> +
> + return (u32)freq;
Do we need the cast? sizeof(u32) doesn't always equal
sizeof(unsigned long).
> +
> +/**
> + * _sci_clk_get - Gets a handle for an SCI clock
> + * @provider: Handle to SCI clock provider
> + * @dev_id: device ID for the clock to register
> + * @clk_id: clock ID for the clock to register
> + *
> + * Gets a handle to an existing TI SCI hw clock, or builds a new clock
> + * entry and registers it with the common clock framework. Called from
> + * the common clock framework, when a corresponding of_clk_get call is
> + * executed, or recursively from itself when parsing parent clocks.
> + * Returns a pointer to the hw clock struct, or ERR_PTR value in failure.
> + */
> +static struct clk_hw *_sci_clk_build(struct sci_clk_provider *provider,
> + u16 dev_id, u8 clk_id)
> +{
> + struct clk_init_data init = { NULL };
> + struct sci_clk *sci_clk = NULL;
> + char *name = NULL;
> + char **parent_names = NULL;
> + int i;
> + int ret;
> +
> + sci_clk = devm_kzalloc(provider->dev, sizeof(*sci_clk), GFP_KERNEL);
> + if (!sci_clk)
> + return ERR_PTR(-ENOMEM);
> +
> + sci_clk->dev_id = dev_id;
> + sci_clk->clk_id = clk_id;
> + sci_clk->provider = provider;
> +
> + ret = provider->ops->get_num_parents(provider->sci, dev_id,
> + clk_id,
> + &init.num_parents);
> + if (ret)
> + goto err;
> +
> + name = kasprintf(GFP_KERNEL, "%s:%d:%d", dev_name(provider->dev),
> + sci_clk->dev_id, sci_clk->clk_id);
> +
> + init.name = name;
> +
> + if (init.num_parents < 2)
> + init.num_parents = 0;
This deserves a comment. Why is num_parents == 1 the same as
num_parents == 0?
> +
> + if (init.num_parents) {
> + parent_names = devm_kcalloc(provider->dev, init.num_parents,
> + sizeof(char *), GFP_KERNEL);
> +
> + if (!parent_names) {
> + ret = -ENOMEM;
> + goto err;
> + }
> +
> + for (i = 0; i < init.num_parents; i++) {
> + char *parent_name;
> +
> + parent_name = kasprintf(GFP_KERNEL, "%s:%d:%d",
> + dev_name(provider->dev),
> + sci_clk->dev_id,
> + sci_clk->clk_id + 1 + i);
> + if (!parent_name) {
> + ret = -ENOMEM;
> + goto err;
> + }
> + parent_names[i] = parent_name;
> + }
> + init.parent_names = (const char * const *)parent_names;
Does that really need a cast?
> + }
> +
> + init.ops = &sci_clk_ops;
> + sci_clk->hw.init = &init;
> +
> + ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
> + if (ret) {
> + dev_err(provider->dev, "failed clk register with %d\n", ret);
> + goto err;
> + }
> + kfree(name);
> +
> + return &sci_clk->hw;
> +
> +err:
> + if (parent_names) {
> + for (i = 0; i < init.num_parents; i++)
> + devm_kfree(provider->dev, parent_names[i]);
> +
> + devm_kfree(provider->dev, parent_names);
Shouldn't we be freeing the parent names all the time? It should
be deep copied in the framework.
> + }
> +
> + devm_kfree(provider->dev, sci_clk);
> +
> + kfree(name);
> +
> + return ERR_PTR(ret);
> +}
[..]
> +
> +static int ti_sci_init_clocks(struct sci_clk_provider *p)
> +{
> + struct sci_clk_data *data = p->clocks;
> + struct clk_hw *hw;
> + int i;
> +
> + while (data->num_clks) {
> + data->clocks = devm_kcalloc(p->dev, data->num_clks,
> + sizeof(struct sci_clk),
> + GFP_KERNEL);
> + if (!data->clocks)
> + return -ENOMEM;
> +
> + for (i = 0; i < data->num_clks; i++) {
> + hw = _sci_clk_build(p, data->dev, i);
> + if (!IS_ERR(hw)) {
> + data->clocks[i] = hw;
> + continue;
> + }
> +
> + /* Skip any holes in the clock lists */
> + if (PTR_ERR(hw) == -ENODEV)
Does this happen? I don't see where _sci_clk_build() returns
-ENODEV.
> + continue;
> +
> + return PTR_ERR(hw);
> + }
> + data++;
> + }
> +
> + return 0;
> +}
> +
> +
> +/**
> + * ti_sci_clk_probe - Probe function for the TI SCI clock driver
> + * @pdev: platform device pointer to be probed
> + *
> + * Probes the TI SCI clock device. Allocates a new clock provider
> + * and registers this to the common clock framework. Also applies
> + * any required flags to the identified clocks via clock lists
> + * supplied from DT. Returns 0 for success, negative error value
> + * for failure.
> + */
> +static int ti_sci_clk_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct device_node *np = dev->of_node;
> + struct sci_clk_provider *provider;
> + const struct ti_sci_handle *handle;
> + struct sci_clk_data *data;
> + int ret;
> +
> + data = (struct sci_clk_data *)
> + of_match_node(ti_sci_clk_of_match, np)->data;
Just use of_device_get_match_data() instead.
> +
> + handle = devm_ti_sci_get_handle(dev);
> + if (IS_ERR(handle))
> + return PTR_ERR(handle);
> +
> + provider = devm_kzalloc(dev, sizeof(*provider), GFP_KERNEL);
> + if (!provider)
> + return -ENOMEM;
> +
> + provider->clocks = data;
> +
> + provider->sci = handle;
> + provider->ops = &handle->ops.clk_ops;
> + provider->dev = dev;
> +
> + ti_sci_init_clocks(provider);
And if this fails?
> +
> + ret = of_clk_add_hw_provider(np, sci_clk_get, provider);
> + if (ret)
> + return ret;
> +
> + return 0;
Just "return of_clk_add_hw_provider()" please.
> +}
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [PATCH] PM / Domains: Fix compatible for domain idle state
From: Rafael J. Wysocki @ 2016-12-08 0:13 UTC (permalink / raw)
To: Ulf Hansson, Rob Herring, Lina Iyer
Cc: Kevin Hilman, linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
Andy Gross, Stephen Boyd,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Brendan Jackman, Lorenzo Pieralisi, Sudeep Holla, Juri Lelli,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1616414.c1s7NxTqJS-yvgW3jdyMHm1GS7QM15AGw@public.gmane.org>
On Thursday, December 01, 2016 10:21:59 PM Rafael J. Wysocki wrote:
> On Tuesday, November 29, 2016 09:47:03 AM Ulf Hansson wrote:
> > On 10 November 2016 at 20:58, Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> > > On Mon, Nov 07, 2016 at 12:14:28PM +0100, Ulf Hansson wrote:
> > >> On 3 November 2016 at 22:54, Lina Iyer <lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > >> > Re-using idle state definition provided by arm,idle-state for domain
> > >> > idle states creates a lot of confusion and limits further evolution of
> > >> > the domain idle definition. To keep things clear and simple, define a
> > >> > idle states for domain using a new compatible "domain-idle-state".
> > >> >
> > >> > Fix existing PM domains code to look for the newly defined compatible.
> > >> >
> > >> > Cc: <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>
> > >> > Cc: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > >> > Signed-off-by: Lina Iyer <lina.iyer-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > >> > ---
> > >> > .../bindings/power/domain-idle-state.txt | 33 ++++++++++++++++++++++
> > >> > .../devicetree/bindings/power/power_domain.txt | 8 +++---
> > >> > drivers/base/power/domain.c | 2 +-
> > >> > 3 files changed, 38 insertions(+), 5 deletions(-)
> > >> > create mode 100644 Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> >
> > >> > diff --git a/Documentation/devicetree/bindings/power/domain-idle-state.txt b/Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> > new file mode 100644
> > >> > index 0000000..eefc7ed
> > >> > --- /dev/null
> > >> > +++ b/Documentation/devicetree/bindings/power/domain-idle-state.txt
> > >> > @@ -0,0 +1,33 @@
> > >> > +PM Domain Idle State Node:
> > >> > +
> > >> > +A domain idle state node represents the state parameters that will be used to
> > >> > +select the state when there are no active components in the domain.
> > >> > +
> > >> > +The state node has the following parameters -
> > >> > +
> > >> > +- compatible:
> > >> > + Usage: Required
> > >> > + Value type: <string>
> > >> > + Definition: Must be "domain-idle-state".
> > >> > +
> > >> > +- entry-latency-us
> > >> > + Usage: Required
> > >> > + Value type: <prop-encoded-array>
> > >> > + Definition: u32 value representing worst case latency in
> > >> > + microseconds required to enter the idle state.
> > >> > + The exit-latency-us duration may be guaranteed
> > >> > + only after entry-latency-us has passed.
> > >>
> > >> As we anyway are going to change this, why not use an u64 and have the
> > >> value in ns instead of us?
> > >
> > > I can't imagine that you would need more resolution or range. For times
> > > less than 1us, s/w and register access times are going to dominate the
> > > time.
> > >
> > > Unless there is a real need, I'd keep alignment with the existing
> > > binding.
> >
> > Rob, are you fine with this? I thought it would be great to get this
> > in for 4.10 rc1.
>
> Rob, any objections here?
Well, no objections, so applied.
Thanks,
Rafael
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