* Re: [PATCH v4 1/2] power: supply: add sbs-charger driver
From: Nicolas Saenz Julienne @ 2016-12-21 9:30 UTC (permalink / raw)
To: Manish Badarkhe
Cc: sre-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Mark Rutland, linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAKDJKT7WWFd2FSAZ6erXF=t1aaCyR0F5px54TiHw7C4PrnKXSQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Manish, thanks for the interest.
On 20/12/16 17:54, Manish Badarkhe wrote:
> Hi Nicola
>
[...]
>
> Just some general comment, Can you add some more properties here to
> know voltage and current?
I assume you are mentioning reading current and voltage values. These
properties are not supported by the sbs-charger standard. All you can do
is set (write only) the charging current and charging voltage values.
Yet in all the boards I've worked with it's the sbs-battery compliant
chip that takes care of it.
> Also, can you add other properties present in charging status register
> like POWER_FAIL, VOLTAGE_OR,
> CURRENT_OR etc.
CURRENT_OR and VOLTAGE_OR relate to wrong values in the charging
voltage/current registers. Since the sbs-battery chip takes care of it I
don't see any use for it.
POWER_FAIL marks there is not enough voltage to charge the battery. I
don't need that information so I did nothing to integrate it. Having a
quick look at the power supply defines I don't see were it could easily fit.
> Don't know weather it is feasible to add or not and Also, let me know,
> if it is already been covered in
> some part of the code.
>
> Thanks
> Manish Badarkhe
>
Regards,
Nicolas
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* Re: [PATCH v3 net-next 3/3] arm64: dts: marvell: Add ethernet switch definition for the ESPRESSObin
From: Gregory CLEMENT @ 2016-12-21 9:41 UTC (permalink / raw)
To: Romain Perier
Cc: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, netdev, devicetree, Rob Herring,
Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel, Thomas Petazzoni, Nadav Haklai
In-Reply-To: <20161221090045.474-4-romain.perier@free-electrons.com>
Hi Romain,
On mer., déc. 21 2016, Romain Perier <romain.perier@free-electrons.com> wrote:
> This defines and enables the Marvell ethernet switch MVE886341 on the
> Marvell ESPRESSObin board.
This patch looks OK now.
Applied on mvebu/dt64-4.11
So you can remove it from you next version because I don't want this
patch will be applied through the netdev branch. Indeed I expect more
changes in this file for v4.11 and it will be easier to have the change
in a single branch to avoid the merge conflict.
Thanks,
Gregory
>
> Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
> ---
>
> Changes in v3:
> - Changed the node switch0 to be at 1
> - Removed reg=<1> from the mdio node, finally that's not required
>
> Changes in v2:
> - EXPRESSObin -> ESPRESSObin
> - phy nodes definition must contain the internal bus address after the @
>
> .../boot/dts/marvell/armada-3720-espressobin.dts | 66 ++++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> index 83178d9..12d9f65 100644
> --- a/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> +++ b/arch/arm64/boot/dts/marvell/armada-3720-espressobin.dts
> @@ -80,3 +80,69 @@
> &usb3 {
> status = "okay";
> };
> +
> +&mdio {
> + switch0: switch0@1 {
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> +
> + dsa,member = <0 0>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + label = "cpu";
> + ethernet = <ð0>;
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "wan";
> + phy-handle = <&switch0phy0>;
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan0";
> + phy-handle = <&switch0phy1>;
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan1";
> + phy-handle = <&switch0phy2>;
> + };
> +
> + };
> +
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + switch0phy0: switch0phy0@11 {
> + reg = <0x11>;
> + };
> + switch0phy1: switch0phy1@12 {
> + reg = <0x12>;
> + };
> + switch0phy2: switch0phy2@13 {
> + reg = <0x13>;
> + };
> + };
> + };
> +};
> +
> +ð0 {
> + phy-mode = "rgmii-id";
> + status = "okay";
> +
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> +};
> --
> 2.9.3
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v4 1/2] power: supply: add sbs-charger driver
From: Manish Badarkhe @ 2016-12-21 10:09 UTC (permalink / raw)
To: Nicolas Saenz Julienne
Cc: sre-DgEjT+Ai2ygdnm+yROfE0A, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
Mark Rutland, linux-pm-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <72292f5b-3f81-f097-a87e-56b58098ff2b-gbiq2sxWoaasTnJN9+BGXg@public.gmane.org>
Hi Nicolas
On Wed, Dec 21, 2016 at 3:00 PM, Nicolas Saenz Julienne
<nicolas.saenz-gbiq2sxWoaasTnJN9+BGXg@public.gmane.org> wrote:
> Hi Manish, thanks for the interest.
>
> On 20/12/16 17:54, Manish Badarkhe wrote:
>> Hi Nicola
>>
> [...]
>>
>> Just some general comment, Can you add some more properties here to
>> know voltage and current?
>
> I assume you are mentioning reading current and voltage values. These
> properties are not supported by the sbs-charger standard. All you can do
> is set (write only) the charging current and charging voltage values.
> Yet in all the boards I've worked with it's the sbs-battery compliant
> chip that takes care of it.
thanks for clarifying me.
>> Also, can you add other properties present in charging status register
>> like POWER_FAIL, VOLTAGE_OR,
>> CURRENT_OR etc.
>
> CURRENT_OR and VOLTAGE_OR relate to wrong values in the charging
> voltage/current registers. Since the sbs-battery chip takes care of it I
> don't see any use for it.
> POWER_FAIL marks there is not enough voltage to charge the battery. I
> don't need that information so I did nothing to integrate it. Having a
> quick look at the power supply defines I don't see were it could easily fit.
thanks for clarifying me.
Regards
Manish Badarkhe
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* [PATCHv2 0/3] arm64/clk: update Marvell Armada CP110 system controller driver
From: Thomas Petazzoni @ 2016-12-21 10:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, devicetree,
Rob Herring, Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala
Cc: Nadav Haklai, Hanna Hawa, Yehuda Yitschak, linux-arm-kernel,
Thomas Petazzoni
Hello,
This small set of commits updates the Marvell Armada CP110 system
controller driver, its Device Tree binding, and Device Tree
representation, to take into account three new things:
- The clock driver now handles clock n°9 (GOP) as a child of clock
n°18 (controls SD/MMC and GOP)
- The DT representation is adjusted to name clock n°18 "sd-mmc-gop"
instead of just "sd-mmc".
- The clock driver now handles clock n°5 (MG) as a child of clock n°6
(MG_CORE).
This set of commits is some preparation work to add networking support
for Marvell Armada 7K/8K.
I would expect patches 1 and 2 to be taken by the clock maintainers,
and patch 3 be taken by the Marvell EBU maintainers.
Changes since v1:
- Addition of the handling of the MG and MG_CORE clocks (n°5 and
n°6), also needed for the networking support on Marvell Aramda
7K/8K.
Thanks,
Thomas
Thomas Petazzoni (3):
dt-bindings: arm: update Armada CP110 system controller binding
clk: mvebu: adjust clock handling for the CP110 system controller
arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
.../bindings/arm/marvell/cp110-system-controller0.txt | 6 +++---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
drivers/clk/mvebu/cp110-system-controller.c | 13 +++++++++++--
4 files changed, 16 insertions(+), 7 deletions(-)
--
2.7.4
^ permalink raw reply
* [PATCHv2 1/3] dt-bindings: arm: update Armada CP110 system controller binding
From: Thomas Petazzoni @ 2016-12-21 10:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA,
Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala
Cc: Nadav Haklai, Hanna Hawa, Yehuda Yitschak,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <1482316017-22154-1-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
It turns out that in the CP110 HW block present in Marvell Armada
7K/8K SoCs, gatable clock n°18 not only controls SD/MMC, but also the
GOP block. This commit updates the Device Tree binding for this piece
of hardware accordingly.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
.../devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 30c5469..07dbb35 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -45,7 +45,7 @@ The following clocks are available:
- 1 15 SATA
- 1 16 SATA USB
- 1 17 Main
- - 1 18 SD/MMC
+ - 1 18 SD/MMC/GOP
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
- 1 22 USB3H0
- 1 23 USB3H1
@@ -65,7 +65,7 @@ Required properties:
"cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
Example:
@@ -78,6 +78,6 @@ Example:
gate-clock-output-names = "cpm-audio", "cpm-communit", "cpm-nand", "cpm-ppv2", "cpm-sdio",
"cpm-mg-domain", "cpm-mg-core", "cpm-xor1", "cpm-xor0", "cpm-gop-dp", "none",
"cpm-pcie_x10", "cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor", "cpm-sata",
- "cpm-sata-usb", "cpm-main", "cpm-sd-mmc", "none", "none", "cpm-slow-io",
+ "cpm-sata-usb", "cpm-main", "cpm-sd-mmc-gop", "none", "none", "cpm-slow-io",
"cpm-usb3h0", "cpm-usb3h1", "cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
--
2.7.4
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^ permalink raw reply related
* [PATCHv2 2/3] clk: mvebu: adjust clock handling for the CP110 system controller
From: Thomas Petazzoni @ 2016-12-21 10:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk, Jason Cooper,
Andrew Lunn, Sebastian Hesselbarth, Gregory Clement, devicetree,
Rob Herring, Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala
Cc: Nadav Haklai, Hanna Hawa, Yehuda Yitschak, linux-arm-kernel,
Thomas Petazzoni
In-Reply-To: <1482316017-22154-1-git-send-email-thomas.petazzoni@free-electrons.com>
This commit:
- makes the GOP_DP (bit 9) gatable clock a child clock of the
SD_MMC_GOP (bit 18) clock, as it should have been. The clock for bit
18 was just named SD_MMC, but since it also covers the GOP block, it
is renamed SD_MMC_GOP.
- makes the MG (bit 5) gatable clock a child clock of the MG_CORE
clock (bit 6)
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
---
drivers/clk/mvebu/cp110-system-controller.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/mvebu/cp110-system-controller.c b/drivers/clk/mvebu/cp110-system-controller.c
index f2303da..8038b93 100644
--- a/drivers/clk/mvebu/cp110-system-controller.c
+++ b/drivers/clk/mvebu/cp110-system-controller.c
@@ -64,8 +64,11 @@ enum {
#define CP110_GATE_NAND 2
#define CP110_GATE_PPV2 3
#define CP110_GATE_SDIO 4
+#define CP110_GATE_MG 5
+#define CP110_GATE_MG_CORE 6
#define CP110_GATE_XOR1 7
#define CP110_GATE_XOR0 8
+#define CP110_GATE_GOP_DP 9
#define CP110_GATE_PCIE_X1_0 11
#define CP110_GATE_PCIE_X1_1 12
#define CP110_GATE_PCIE_X4 13
@@ -73,7 +76,7 @@ enum {
#define CP110_GATE_SATA 15
#define CP110_GATE_SATA_USB 16
#define CP110_GATE_MAIN 17
-#define CP110_GATE_SDMMC 18
+#define CP110_GATE_SDMMC_GOP 18
#define CP110_GATE_SLOW_IO 21
#define CP110_GATE_USB3H0 22
#define CP110_GATE_USB3H1 23
@@ -302,6 +305,11 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
"gate-clock-output-names",
CP110_GATE_MAIN, &parent);
break;
+ case CP110_GATE_MG:
+ of_property_read_string_index(np,
+ "gate-clock-output-names",
+ CP110_GATE_MG_CORE, &parent);
+ break;
case CP110_GATE_NAND:
parent = nand_name;
break;
@@ -309,9 +317,10 @@ static int cp110_syscon_clk_probe(struct platform_device *pdev)
parent = ppv2_name;
break;
case CP110_GATE_SDIO:
+ case CP110_GATE_GOP_DP:
of_property_read_string_index(np,
"gate-clock-output-names",
- CP110_GATE_SDMMC, &parent);
+ CP110_GATE_SDMMC_GOP, &parent);
break;
case CP110_GATE_XOR1:
case CP110_GATE_XOR0:
--
2.7.4
^ permalink raw reply related
* [PATCHv2 3/3] arm64: dts: marvell: adjust name of sd-mmc-gop clock in syscon
From: Thomas Petazzoni @ 2016-12-21 10:26 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, linux-clk-u79uwXL29TY76Z2rM5mHXA,
Jason Cooper, Andrew Lunn, Sebastian Hesselbarth, Gregory Clement,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring, Ian Campbell,
Pawel Moll, Mark Rutland, Kumar Gala
Cc: Nadav Haklai, Hanna Hawa, Yehuda Yitschak,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni
In-Reply-To: <1482316017-22154-1-git-send-email-thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
This commit adjusts the names of gatable clock #18 of the Marvell Armada
CP110 system controller. This clock not only controls SD/MMC, but also
the GOP (Group Of Ports) used for networking. So the clock is renamed to
{cpm,cps}-sd-mmc-gop instead of {cpm,cps}-sd-mmc.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
---
arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi | 2 +-
arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index 602e2c2..895babc 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -74,7 +74,7 @@
"cpm-gop-dp", "none", "cpm-pcie_x10",
"cpm-pcie_x11", "cpm-pcie_x4", "cpm-pcie-xor",
"cpm-sata", "cpm-sata-usb", "cpm-main",
- "cpm-sd-mmc", "none", "none",
+ "cpm-sd-mmc-gop", "none", "none",
"cpm-slow-io", "cpm-usb3h0", "cpm-usb3h1",
"cpm-usb3dev", "cpm-eip150", "cpm-eip197";
};
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 6bf9e24..db99646 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -74,7 +74,7 @@
"cps-gop-dp", "none", "cps-pcie_x10",
"cps-pcie_x11", "cps-pcie_x4", "cps-pcie-xor",
"cps-sata", "cps-sata-usb", "cps-main",
- "cps-sd-mmc", "none", "none",
+ "cps-sd-mmc-gop", "none", "none",
"cps-slow-io", "cps-usb3h0", "cps-usb3h1",
"cps-usb3dev", "cps-eip150", "cps-eip197";
};
--
2.7.4
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^ permalink raw reply related
* [PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
From: Xing Zheng @ 2016-12-21 10:29 UTC (permalink / raw)
To: linux-rockchip
Cc: dianders, heiko, William wu, Xing Zheng, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Douglas Anderson,
Caesar Wang, Brian Norris, Shawn Lin, Jianqun Xu, Elaine Zhang,
David Wu, devicetree, linux-arm-kernel, linux-kernel
From: William wu <wulf@rock-chips.com>
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.
The u2phy clock flow like this:
---
Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs
u2phy ________________
| | |-----> UTMI_CLK ---------> | EHCI |
OSC_24M ---|---> PHY_PLL----|----|
|________^_______| |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC
|
|
GRF
---
Signed-off-by: William wu <wulf@rock-chips.com>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&u2phy0>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&u2phy0>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
status = "disabled";
};
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&u2phy1>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&u2phy1>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
status = "disabled";
};
--
2.7.4
^ permalink raw reply related
* [RESEND PATCH v2] arm64: dts: rockchip: add u2phy clock for ehci and ohci of rk3399
From: Xing Zheng @ 2016-12-21 10:41 UTC (permalink / raw)
To: heiko-4mtYJXux2i+zQB+pC5nmwQ,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
catalin.marinas-5wv7dgnIgG8, will.deacon-5wv7dgnIgG8,
dianders-F7+t8E8rja9g9hUCZPvPmw, wxt-TNX95d0MmH7DzftRWevZcw,
zhengxing-TNX95d0MmH7DzftRWevZcw,
shawn.lin-TNX95d0MmH7DzftRWevZcw,
briannorris-F7+t8E8rja9g9hUCZPvPmw, jay.xu-TNX95d0MmH7DzftRWevZcw,
zhangqing-TNX95d0MmH7DzftRWevZcw, david.wu-TNX95d0MmH7DzftRWevZcw,
wulf-TNX95d0MmH7DzftRWevZcw, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
dianders-hpIqsD4AKlfQT0dZR+AlfA,
frank.wang-TNX95d0MmH7DzftRWevZcw
In-Reply-To: <1482316182-2305-1-git-send-email-zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
From: William wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
We found that the suspend process was blocked when it run into
ehci/ohci module due to clk-480m of usb2-phy was disabled.
The root cause is that usb2-phy suspended earlier than ehci/ohci
(usb2-phy will be auto suspended if no devices plug-in). and the
clk-480m provided by it was disabled if no module used. However,
some suspend process related ehci/ohci are base on this clock,
so we should refer it into ehci/ohci driver to prevent this case.
The u2phy clock flow like this:
===
u2phy ________________
| | |-----> UTMI_CLK ---------> | EHCI |
OSC_24M ---|---> PHY_PLL----|----|
|________^_______| |-----> 480M_CLK ---|G|---> | USBPHY_480M_SRC| ----> USBPHY_480M for SoC
|
|
GRF
===
Signed-off-by: William wu <wulf-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Signed-off-by: Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
---
Changes in v2:
- update the commit message
- remove patches whic add and export the USBPHYx_480M_SRC clock IDs
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 28 ++++++++++++++++++++--------
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/rockchip/rk3399.dtsi b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
index b65c193..2ad9255 100644
--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
@@ -315,8 +315,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe380000 0x0 0x20000>;
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&u2phy0>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <&u2phy0_host>;
phy-names = "usb";
status = "disabled";
@@ -326,8 +328,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3a0000 0x0 0x20000>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>;
- clock-names = "hclk_host0", "hclk_host0_arb";
+ clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
+ <&u2phy0>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
+ phys = <&u2phy0_host>;
+ phy-names = "usb";
status = "disabled";
};
@@ -335,8 +341,10 @@
compatible = "generic-ehci";
reg = <0x0 0xfe3c0000 0x0 0x20000>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&u2phy1>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
phys = <&u2phy1_host>;
phy-names = "usb";
status = "disabled";
@@ -346,8 +354,12 @@
compatible = "generic-ohci";
reg = <0x0 0xfe3e0000 0x0 0x20000>;
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>;
- clock-names = "hclk_host1", "hclk_host1_arb";
+ clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
+ <&u2phy1>;
+ clock-names = "usbhost", "arbiter",
+ "utmi";
+ phys = <&u2phy1_host>;
+ phy-names = "usb";
status = "disabled";
};
--
2.7.4
--
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^ permalink raw reply related
* Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399
From: Xing Zheng @ 2016-12-21 10:44 UTC (permalink / raw)
To: Doug Anderson
Cc: Heiko Stuebner, Frank Wang, Brian Norris, William wu, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Caesar Wang,
Jianqun Xu, Elaine Zhang,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Dmitry Torokhov, Tao Huang, open list:ARM/Rockchip SoC...
In-Reply-To: <CAD=FV=W1BW6FSZ6MSxR6RhvtZyGsdQbz9vU_QshaQ5A65ENMCg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Heiko, Doug
在 2016年12月17日 01:28, Doug Anderson 写道:
> Hi,
>
> On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Hi Heiko, Doug,
>>
>> On 2016年12月16日 02:18, Heiko Stuebner wrote:
>>
>> Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson:
>>
>>
>> I still need to digest all of the things that were added to this
>> thread overnight, but nothing I've seen so far indicates that you need
>> the post-gated clock. AKA I still think you need to redo your patch
>> to replace:
>>
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&cru SCLK_USBPHY0_480M_SRC>;
>>
>> with:
>>
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&u2phy0>;
>>
>> Can you please comment on that?
>>
>> Also, with the change, the ehci will keep the clock (and thus the phy)
>> always
>> on. Does the phy-autosuspend even save anything now?
>>
>> In any case, could we make the clock-names entry sound nicer than
>> usbphy0_480m
>> please? bindings/usb/atmel-usb.txt calls its UTMI clock simply "usb_clk",
>> but
>> something like "utmi" should also work.
>> While at it you could also fix up the other clock names to something like
>> "host" and "arbiter" or so?.
>>
>>
>> Heiko
>>
>>
>> The usbphy related clock tress like this:
>>
>>
>> Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only
>> enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK.
>>
>> And the naming style of the "hclk_host0" keep the name "hclk_host0" on the
>> clcok tree diagram:
>>
>>
>> Therefore, could we rename the clock name like this:
>> ----
>> for usb_host0_ehci and usb_host0_ohci:
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&cru SCLK_U2PHY0>;
>> clock-names = "hclk_host0", "hclk_host0_arb",
>> "sclk_u2phy0";
>>
>> for usb_host1_ehci and usb_host1_ohci:
>> clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
>> <&cru SCLK_U2PHY1>;
>> clock-names = "hclk_host1", "hclk_host1_arb",
>> "sclk_u2phy1";
>> ----
>>
>> BTW, the "arb" is an abbreviation for arbiter.
> You don't specify what this new "SCLK_U2PHY0" ID is, so it's a little
> hard for me to know what you're intending.
>
> ...however, I still don't see any reason why you can't just use the
> solution I proposed. Specifying the clock as "<&u2phy0>" is the
> correct thing to do. The input clock to the EHCI driver is exactly
> the clock provided by the USB PHY with no gate in between (just as I
> said). There is no reason to somehow buffer it by the cru. The cru
> doesn't see this clock and has no reason to be involved.
>
> Note that there were many other comments on this thread besides mine.
> Are you planning to address any of them?
>
> -Doug
>
>
Done, and have resent the patch.
Thanks.
--
- Xing Zheng
--
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^ permalink raw reply
* Re: [alsa-devel] [PATCH v3 1/2] ASoC: cs35l35: Add support for Cirrus CS35L35 Amplifier
From: Charles Keepax @ 2016-12-21 10:53 UTC (permalink / raw)
To: Li Xu
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA, tiwai-IBi9RG/b67k,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA
In-Reply-To: <7566bac5-e4c4-49ff-91b3-bcd578cef21b-XU/xxMRwCJnfk+Ne4bZl5AC/G2K4zDHf@public.gmane.org>
On Tue, Dec 13, 2016 at 10:59:03AM -0600, Li Xu wrote:
> Add driver support for Cirrus Logic CS35L35 boosted
> speaker amplifier
>
> Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
> ---
Mostly just some minor comments.
> +struct classh_cfg {
> + /*
> + * Class H Algorithm Control Variables
> + * You can either have it done
> + * automatically or you can adjust
> + * these variables for tuning
> + *
> + * if you do not enable the internal algorithm
> + * you will get a set of mixer controls for
> + * Class H tuning
> + *
> + * Section 4.3 of the datasheet
> + */
> + /* Internal ClassH Algorithm */
Feels redundant to have this extra comment after the large comment
before it.
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/version.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/slab.h>
> +#include <linux/workqueue.h>
Do we need the workqueue header we don't seem to use any
workqueues?
> +static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol, int event)
> +{
> + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + int ret = 0;
> +
> + switch (event) {
> + case SND_SOC_DAPM_PRE_PMU:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MCLK_DIS_MASK, 0 << CS35L35_MCLK_DIS_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_DISCHG_FILT_MASK, 0 << CS35L35_DISCHG_FILT_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_PDN_ALL_MASK, 0);
> + break;
Break should be indented for kernel coding style.
> + case SND_SOC_DAPM_POST_PMD:
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_PDN_ALL_MASK, 1);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_DISCHG_FILT_MASK, 1 << CS35L35_DISCHG_FILT_SHIFT);
> +
> + ret = wait_for_completion_timeout(&cs35l35->pdn_done,
> + msecs_to_jiffies(100));
> + if (ret == 0) {
> + dev_err(codec->dev, "TIMEOUT PDN_DONE did not complete in 100ms\n");
> + ret = -ETIMEDOUT;
> + }
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MCLK_DIS_MASK, 1 << CS35L35_MCLK_DIS_SHIFT);
> + break;
Ditto.
> + default:
> + dev_err(codec->dev, "Invalid event = 0x%x\n", event);
> + ret = -EINVAL;
> + }
> + return ret;
> +}
> +
> +static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol, int event)
> +{
> + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + unsigned int reg[4];
> + int i;
> +
> + switch (event) {
> + case SND_SOC_DAPM_PRE_PMU:
> + if (cs35l35->pdata.bst_pdn_fet_on)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 0 << CS35L35_PDN_BST_FETON_SHIFT);
> + else
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_MUTE_MASK, 0 << CS35L35_AMP_MUTE_SHIFT);
> + break;
> + case SND_SOC_DAPM_POST_PMU:
> + usleep_range(5000, 5100);
> + /* If PDM mode we must use VP
> + * for Voltage control
> + */
Does this comment need to split across multiple lines?
> +static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
> +{
> + struct snd_soc_codec *codec = codec_dai->codec;
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> +
> + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> + case SND_SOC_DAIFMT_CBM_CFM:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
> + cs35l35->slave_mode = false;
> + break;
> + case SND_SOC_DAIFMT_CBS_CFS:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
> + cs35l35->slave_mode = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> + case SND_SOC_DAIFMT_I2S:
> + cs35l35->i2s_mode = true;
> + cs35l35->pdm_mode = false;
> + break;
> + case SND_SOC_DAIFMT_PDM:
> + cs35l35->pdm_mode = true;
> + cs35l35->i2s_mode = false;
Feels a bit redundant to have both of these if they are only ever
a logical inversion of each other.
> +static int cs35l35_get_clk_config(int sysclk, int srate)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
> + if (cs35l35_clk_ctl[i].sysclk == sysclk &&
> + cs35l35_clk_ctl[i].srate == srate)
> + return cs35l35_clk_ctl[i].clk_cfg;
> + }
> + return -EINVAL;
> +}
> +
> +static int cs35l35_pcm_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_codec *codec = dai->codec;
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
> + int srate = params_rate(params);
> + int ret = 0;
> + u8 sp_sclks;
> + int audin_format;
> + int errata_chk;
> +
> + int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
> +
> + if (clk_ctl < 0) {
> + dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
> + cs35l35->sysclk, srate);
> + return -EINVAL;
> + }
It would normally be slightly better to set constraints in
startup based on the SYSCLK rather than returning an error in
hw_params. This allows user-space to negotiate a rate that is
actually supported and do any sample rate conversion required.
> +
> + ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
> + CS35L35_CLK_CTL2_MASK, clk_ctl);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set port config %d\n", ret);
> + return ret;
> + }
> +
> + /* Rev A0 Errata
> + *
> + * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
> + * the Class H algorithm does not enable weak-drive operation for
> + * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
> + *
> + */
> + errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
> +
> + if (classh->classh_wk_fet_disable == 0x00 &&
> + (errata_chk == 0x01 || errata_chk == 0x03)) {
> + ret = regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DEL_MASK,
> + 0 << CS35L35_CH_WKFET_DEL_SHIFT);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set fet config %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> +/*
> + * You can pull more Monitor data from the SDOUT pin than going to SDIN
> + * Just make sure your SCLK is fast enough to fill the frame
> + */
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + switch (params_width(params)) {
> + case 8:
> + audin_format = CS35L35_SDIN_DEPTH_8;
> + break;
> + case 16:
> + audin_format = CS35L35_SDIN_DEPTH_16;
> + break;
> + case 24:
> + audin_format = CS35L35_SDIN_DEPTH_24;
> + break;
> + default:
> + dev_err(codec->dev, "Unsupported Width %d\n",
> + params_width(params));
> + }
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_DEPTH_CTL, CS35L35_AUDIN_DEPTH_MASK,
> + audin_format << CS35L35_AUDIN_DEPTH_SHIFT);
> + if (cs35l35->pdata.stereo) {
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_DEPTH_CTL, CS35L35_ADVIN_DEPTH_MASK,
> + audin_format << CS35L35_ADVIN_DEPTH_SHIFT);
> + }
> + }
> +/* We have to take the SCLK to derive num sclks
> + * to configure the CLOCK_CTL3 register correctly
> + */
> + if ((cs35l35->sclk / srate) % 4) {
> + dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n",
> + cs35l35->sclk, srate);
> + return -EINVAL;
> + }
Again here it might be slightly better to constraints in startup.
> + sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
> +
> + if (cs35l35->i2s_mode) {
> + /* Only certain ratios are supported in I2S Slave Mode */
> + if (cs35l35->slave_mode) {
> + switch (sp_sclks) {
> + case CS35L35_SP_SCLKS_32FS:
> + case CS35L35_SP_SCLKS_48FS:
> + case CS35L35_SP_SCLKS_64FS:
> + break;
> + default:
> + dev_err(codec->dev, "ratio not supported\n");
> + return -EINVAL;
> + };
> + } else {
> + /* Only certain ratios supported in I2S MASTER Mode */
> + switch (sp_sclks) {
> + case CS35L35_SP_SCLKS_32FS:
> + case CS35L35_SP_SCLKS_64FS:
> + break;
> + default:
> + dev_err(codec->dev, "ratio not supported\n");
> + return -EINVAL;
> + };
> + }
> + ret = regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLK_CTL3, CS35L35_SP_SCLKS_MASK,
> + sp_sclks << CS35L35_SP_SCLKS_SHIFT);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
> + return ret;
> + }
> + }
> + if (cs35l35->pdm_mode) {
> + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> + CS35L35_PDM_MODE_MASK, 1 << CS35L35_PDM_MODE_SHIFT);
> + } else {
> + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> + CS35L35_PDM_MODE_MASK, 0 << CS35L35_PDM_MODE_SHIFT);
> + }
This if could be combined with the one above since pdm_mode ==
!i2s_mode.
> + return ret;
> +}
> +
> +
> +static const struct snd_soc_dai_ops cs35l35_ops = {
> + .startup = cs35l35_pcm_startup,
> + .set_fmt = cs35l35_set_dai_fmt,
> + .hw_params = cs35l35_pcm_hw_params,
> + .set_sysclk = cs35l35_dai_set_sysclk,
> +};
> +
> +static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
> + .startup = cs35l35_pdm_startup,
> + .set_fmt = cs35l35_set_dai_fmt,
> + .hw_params = cs35l35_pcm_hw_params,
I would be tempted to rename the function to just
cs35l35_hw_params if it is shared between both PCM and PDM.
> + .set_sysclk = cs35l35_dai_set_sysclk,
> +};
> +
> +
> +static int cs35l35_codec_probe(struct snd_soc_codec *codec)
> +{
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
> + struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
> + int ret;
> +
> + cs35l35->codec = codec;
> +
> + /* Set Platform Data */
> + if (cs35l35->pdata.bst_vctl)
> + regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
> + CS35L35_BST_CTL_MASK, cs35l35->pdata.bst_vctl);
> +
> + if (cs35l35->pdata.bst_ipk)
> + regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
> + CS35L35_BST_IPK_MASK,
> + cs35l35->pdata.bst_ipk << CS35L35_BST_IPK_SHIFT);
I believe zero is a valid value for this field, but not the
default. Are we happy that the user can never set this value?
> +
> + if (cs35l35->pdata.gain_zc)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_GAIN_ZC_MASK,
> + cs35l35->pdata.gain_zc << CS35L35_AMP_GAIN_ZC_SHIFT);
> +
> + if (cs35l35->pdata.aud_channel)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_RXLOC_CTL,
> + CS35L35_AUD_IN_LR_MASK,
> + cs35l35->pdata.aud_channel << CS35L35_AUD_IN_LR_SHIFT);
> +
> + if (cs35l35->pdata.stereo) {
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_ADVIN_RXLOC_CTL, CS35L35_ADV_IN_LR_MASK,
> + cs35l35->pdata.adv_channel << CS35L35_ADV_IN_LR_SHIFT);
> + if (cs35l35->pdata.shared_bst)
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
> + CS35L35_CH_STEREO_MASK, 1 << CS35L35_CH_STEREO_SHIFT);
> + ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
> + ARRAY_SIZE(cs35l35_adv_controls));
> + if (ret)
> + return ret;
> + }
> +
> + if (cs35l35->pdata.sp_drv_str)
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_SP_DRV_MASK,
> + cs35l35->pdata.sp_drv_str << CS35L35_SP_DRV_SHIFT);
> +
> + if (classh->classh_algo_enable) {
> + if (classh->classh_bst_override)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_OVR_MASK,
> + classh->classh_bst_override << CS35L35_CH_BST_OVR_SHIFT);
> + if (classh->classh_bst_max_limit)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_LIM_MASK,
> + classh->classh_bst_max_limit << CS35L35_CH_BST_LIM_SHIFT);
This is a single bit, but the default bit is 1, so this code can
never change the value of the field.
> + if (classh->classh_mem_depth)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_MEM_DEPTH_MASK,
> + classh->classh_mem_depth << CS35L35_CH_MEM_DEPTH_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_headroom)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_HEADRM_CTL, CS35L35_CH_HDRM_CTL_MASK,
> + classh->classh_headroom << CS35L35_CH_HDRM_CTL_SHIFT);
> + if (classh->classh_release_rate)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_RELEASE_RATE, CS35L35_CH_REL_RATE_MASK,
> + classh->classh_release_rate << CS35L35_CH_REL_RATE_SHIFT);
> + if (classh->classh_wk_fet_disable)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DIS_MASK,
> + classh->classh_wk_fet_disable << CS35L35_CH_WKFET_DIS_SHIFT);
> + if (classh->classh_wk_fet_delay)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DEL_MASK,
> + classh->classh_wk_fet_delay << CS35L35_CH_WKFET_DEL_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_wk_fet_thld)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_THLD_MASK,
> + classh->classh_wk_fet_thld << CS35L35_CH_WKFET_THLD_SHIFT);
> + if (classh->classh_vpch_auto)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_AUTO_MASK,
> + classh->classh_vpch_auto << CS35L35_CH_VP_AUTO_SHIFT);
Again single bit with a default of 1.
> + if (classh->classh_vpch_rate)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_RATE_MASK,
> + classh->classh_vpch_rate << CS35L35_CH_VP_RATE_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_vpch_man)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_MAN_MASK,
> + classh->classh_vpch_man << CS35L35_CH_VP_MAN_SHIFT);
> + }
> +
<snip>
> +static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
> + const struct i2c_device_id *id)
> +{
> + struct cs35l35_private *cs35l35;
> + struct cs35l35_platform_data *pdata =
> + dev_get_platdata(&i2c_client->dev);
> + int i;
> + int ret;
> + unsigned int devid = 0;
> + unsigned int reg;
> +
> + cs35l35 = devm_kzalloc(&i2c_client->dev,
> + sizeof(struct cs35l35_private),
> + GFP_KERNEL);
> + if (!cs35l35) {
> + dev_err(&i2c_client->dev, "could not allocate codec\n");
> + return -ENOMEM;
> + }
> +
> + i2c_set_clientdata(i2c_client, cs35l35);
> + cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
> + if (IS_ERR(cs35l35->regmap)) {
> + ret = PTR_ERR(cs35l35->regmap);
> + dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
> + goto err;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
> + cs35l35->supplies[i].supply = cs35l35_supplies[i];
> + cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
> +
> + ret = devm_regulator_bulk_get(&i2c_client->dev,
> + cs35l35->num_supplies,
> + cs35l35->supplies);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev,
> + "Failed to request core supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + if (pdata) {
> + cs35l35->pdata = *pdata;
> + } else {
> + pdata = devm_kzalloc(&i2c_client->dev,
> + sizeof(struct cs35l35_platform_data),
> + GFP_KERNEL);
> + if (!pdata) {
> + dev_err(&i2c_client->dev,
> + "could not allocate pdata\n");
> + return -ENOMEM;
> + }
> + if (i2c_client->dev.of_node) {
> + ret = cs35l35_handle_of_data(i2c_client, pdata);
> + if (ret != 0)
> + return ret;
> +
> + }
> + cs35l35->pdata = *pdata;
> + }
> +
> + ret = regulator_bulk_enable(cs35l35->num_supplies,
> + cs35l35->supplies);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev,
> + "Failed to enable core supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + /* returning NULL can be an option if in stereo mode */
> + cs35l35->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
> + "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(cs35l35->reset_gpio))
> + return PTR_ERR(cs35l35->reset_gpio);
This should be a goto err;
> +
> + if (cs35l35->reset_gpio)
> + gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
gpiod_set_value_can_sleep does an internal NULL check on the GPIO
desc I would be tempted to just rely on that one.
> +
> + init_completion(&cs35l35->pdn_done);
> +
> + ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
> + ARRAY_SIZE(cs35l35_errata_patch));
> + if (ret < 0) {
> + dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
> + return ret;
This should be a goto err;
> + }
> +
> + ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
> + cs35l35_irq, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
> + "cs35l35", cs35l35);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
> + goto err;
> + }
> + /* initialize codec */
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®);
> +
> + devid = (reg & 0xFF) << 12;
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®);
> + devid |= (reg & 0xFF) << 4;
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®);
> + devid |= (reg & 0xF0) >> 4;
> +
> + if (devid != CS35L35_CHIP_ID) {
> + dev_err(&i2c_client->dev,
> + "CS35L35 Device ID (%X). Expected ID %X\n",
> + devid, CS35L35_CHIP_ID);
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®);
> + if (ret < 0) {
> + dev_err(&i2c_client->dev, "Get Revision ID failed\n");
> + goto err;
> + }
> +
> + dev_info(&i2c_client->dev,
> + "Cirrus Logic CS35L35 (%x), Revision: %02X\n", devid,
> + ret & 0xFF);
> +
> + /* Set the INT Masks for critical errors */
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1, CS35L35_INT1_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2, CS35L35_INT2_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3, CS35L35_INT3_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4, CS35L35_INT4_CRIT_MASK);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PWR2_PDN_MASK, CS35L35_PWR2_PDN_MASK);
> +
> + if (cs35l35->pdata.bst_pdn_fet_on)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 1 << CS35L35_PDN_BST_FETON_SHIFT);
> + else
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
> + CS35L35_PWR3_PDN_MASK, CS35L35_PWR3_PDN_MASK);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
> +
> + ret = snd_soc_register_codec(&i2c_client->dev,
> + &soc_codec_dev_cs35l35, cs35l35_dai,
> + ARRAY_SIZE(cs35l35_dai));
> + if (ret < 0) {
> + dev_err(&i2c_client->dev,
> + "%s: Register codec failed\n", __func__);
> + goto err;
> + }
> +
> +err:
> + regulator_bulk_disable(cs35l35->num_supplies,
> + cs35l35->supplies);
> + return ret;
> +}
> +
> +static int cs35l35_i2c_remove(struct i2c_client *client)
> +{
> + snd_soc_unregister_codec(&client->dev);
> + kfree(i2c_get_clientdata(client));
clientdata was allocated with devm this kfree will cause a double
free.
> + return 0;
> +}
Thanks,
Charles
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^ permalink raw reply
* [PATCH] ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage
From: Jerome Brunet @ 2016-12-21 11:31 UTC (permalink / raw)
To: Kevin Hilman, Carlo Caione, linux-amlogic, devicetree
Cc: Jerome Brunet, linux-arm-kernel, linux-kernel
OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the
MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on
the Tx path). The problem seems to come from the phy Rx path, entering the
LPI state.
Disabling EEE advertisement on the phy prevent this feature to be
negociated with the link partner and solve the issue.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
This patch is based on Linus recent master branch [0]
This patch depends on the series [1] which has been merged in this branch.
0: ba6d973f78eb ("Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net")
1: http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbrunet@baylibre.com
Fix integration of eee-broken-modes
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 238fbeacd330..d8933e9e9a5a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -147,6 +147,18 @@
status = "okay";
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
};
&ir {
--
2.7.4
^ permalink raw reply related
* Re: [PATCH 2/3] NFC: trf7970a: Add device tree option of 1.8 Volt IO voltage
From: Geoff Lansberry @ 2016-12-21 11:47 UTC (permalink / raw)
To: Mark Greer
Cc: linux-wireless, lauro.venancio, aloisio.almeida, sameo, robh+dt,
mark.rutland, netdev, devicetree, linux-kernel, justin
In-Reply-To: <20161221022347.GB5444@animalcreek.com>
Thanks Mark. Should I resubmit patches with the requested edits today, or wait a bit for more comments? What is the desired etiquette?
> On Dec 20, 2016, at 9:23 PM, Mark Greer <mgreer@animalcreek.com> wrote:
>
>> On Tue, Dec 20, 2016 at 11:16:31AM -0500, Geoff Lansberry wrote:
>> From: Geoff Lansberry <geoff@kuvee.com>
>>
>> The TRF7970A has configuration options for supporting hardware designs
>> with 1.8 Volt or 3.3 Volt IO. This commit adds a device tree option,
>> using a fixed regulator binding, for setting the io voltage to match
>> the hardware configuration. If no option is supplied it defaults to
>> 3.3 volt configuration.
>
> Sign-off ?? Same comment for you other patches.
>
> <time passes>
>
> Okay I see you have it at the end of the patch. It should be here.
> 'git commit -s' is your friend.
>
>> ---
>> .../devicetree/bindings/net/nfc/trf7970a.txt | 4 ++--
>> drivers/nfc/trf7970a.c | 28 +++++++++++++++++++++-
>> 2 files changed, 29 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> index e262ac1..b5777d8 100644
>> --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> +++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> @@ -21,9 +21,9 @@ Optional SoC Specific Properties:
>> - t5t-rmb-extra-byte-quirk: Specify that the trf7970a has the erratum
>> where an extra byte is returned by Read Multiple Block commands issued
>> to Type 5 tags.
>> +- vdd-io-supply: Regulator specifying voltage for vdd-io
>> - clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz
>>
>> -
>> Example (for ARM-based BeagleBone with TRF7970A on SPI1):
>>
>> &spi1 {
>> @@ -41,11 +41,11 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
>> <&gpio2 5 GPIO_ACTIVE_LOW>;
>> vin-supply = <&ldo3_reg>;
>> vin-voltage-override = <5000000>;
>> + vdd-io-supply = <&ldo2_reg>;
>> autosuspend-delay = <30000>;
>> irq-status-read-quirk;
>> en2-rf-quirk;
>> t5t-rmb-extra-byte-quirk;
>> - vdd_io_1v8;
>
> It was already mentioned but this shouldn't have been added in the
> previous patch so it shouldn't be here now.
>
>> clock-frequency = <27120000>;
>> status = "okay";
>> };
>> diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
>> index 4e051e9..8a88195 100644
>> --- a/drivers/nfc/trf7970a.c
>> +++ b/drivers/nfc/trf7970a.c
>
>> @@ -2062,6 +2068,7 @@ static int trf7970a_probe(struct spi_device *spi)
>> return ret;
>> }
>>
>> +
>
> Please don't add an extra blank line.
>
>> of_property_read_u32(np, "clock-frequency", &clk_freq);
>> if ((clk_freq != TRF7970A_27MHZ_CLOCK_FREQUENCY) ||
>> (clk_freq != TRF7970A_27MHZ_CLOCK_FREQUENCY)) {
>> @@ -2105,6 +2112,25 @@ static int trf7970a_probe(struct spi_device *spi)
>> if (uvolts > 4000000)
>> trf->chip_status_ctrl = TRF7970A_CHIP_STATUS_VRS5_3;
>>
>> + trf->regulator = devm_regulator_get(&spi->dev, "vdd-io");
>> + if (IS_ERR(trf->regulator)) {
>> + ret = PTR_ERR(trf->regulator);
>> + dev_err(trf->dev, "Can't get VDD_IO regulator: %d\n", ret);
>> + goto err_destroy_lock;
>> + }
>> +
>> + ret = regulator_enable(trf->regulator);
>> + if (ret) {
>> + dev_err(trf->dev, "Can't enable VDD_IO: %d\n", ret);
>> + goto err_destroy_lock;
>> + }
>> +
>> +
>
> Please don't add an extra blank line.
>
>> + if (regulator_get_voltage(trf->regulator) == 1800000) {
>> + trf->io_ctrl = TRF7970A_REG_IO_CTRL_IO_LOW;
>> + dev_dbg(trf->dev, "trf7970a config vdd_io to 1.8V\n");
>> + }
>> +
>> trf->ddev = nfc_digital_allocate_device(&trf7970a_nfc_ops,
>> TRF7970A_SUPPORTED_PROTOCOLS,
>> NFC_DIGITAL_DRV_CAPS_IN_CRC |
>> --
>> Signed-off-by: Geoff Lansberry <geoff@kuvee.com>
>
> Your 'Signed-off-by:' goes at the end of the commit description not here.
>
> Overall, I think you did the right thing (unless someone disagrees).
> Just some minor issues.
>
> Mark
> --
^ permalink raw reply
* [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, John Stultz
As per the device tree binding the apq8064 scm node requires the core
clock to be specified, so add this.
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 268bd470c865..78bf155a52f3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -303,6 +303,9 @@
firmware {
scm {
compatible = "qcom,scm-apq8064";
+
+ clocks = <&gcc CE3_CORE_CLK>;
+ clock-names = "core";
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Mark Rutland, devicetree, linux-arm-msm, linux-kernel,
Rob Herring, John Stultz, linux-soc, linux-arm-kernel
In-Reply-To: <20161221114939.19973-1-bjorn.andersson@linaro.org>
Add nodes for the Riva PIL, IRIS RF module, BT and WiFI services exposed
by the Riva firmware and the related memory reserve.
Also provides pinctrl nodes for devices enabling the riva-pil.
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 18 +++++++++
arch/arm/boot/dts/qcom-apq8064.dtsi | 69 +++++++++++++++++++++++++++++++-
2 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 6b801e7e57a2..5c023e649882 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -284,4 +284,22 @@
bias-disable = <0>;
};
};
+
+ riva_fm_pin_a: riva-fm-active {
+ pins = "gpio14", "gpio15";
+ function = "riva_fm";
+ };
+
+ riva_bt_pin_a: riva-bt-active {
+ pins = "gpio16", "gpio17";
+ function = "riva_bt";
+ };
+
+ riva_wlan_pin_a: riva-wlan-active {
+ pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
+ function = "riva_wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 78bf155a52f3..3dc7a7aa3450 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -21,6 +21,11 @@
reg = <0x80000000 0x200000>;
no-map;
};
+
+ wcnss_mem: wcnss@8f000000 {
+ reg = <0x8f000000 0x700000>;
+ no-map;
+ };
};
cpus {
@@ -179,7 +184,7 @@
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
@@ -1419,6 +1424,68 @@
};
};
};
+
+ riva: riva-pil@3204000 {
+ compatible = "qcom,riva-pil";
+
+ reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal";
+
+ memory-region = <&wcnss_mem>;
+
+ vddcx-supply = <&pm8921_s3>;
+ vddmx-supply = <&pm8921_l24>;
+ vddpx-supply = <&pm8921_s4>;
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3660";
+
+ clocks = <&cxo_board>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8921_l4>;
+ vddrfa-supply = <&pm8921_s2>;
+ vddpa-supply = <&pm8921_l10>;
+ vdddig-supply = <&pm8921_lvs2>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&l2cc 8 25>;
+ qcom,smd-edge = <6>;
+
+ label = "riva";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&riva>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
};
};
#include "qcom-apq8064-pins.dtsi"
--
2.11.0
^ permalink raw reply related
* [PATCH 3/5] ARM: dts: qcom: apq8064-sony-yuga: Enable riva-pil
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, John Stultz
In-Reply-To: <20161221114939.19973-1-bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: John Stultz <john.stultz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
index ebd675ca94b4..a34ba3555454 100644
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
@@ -390,5 +390,12 @@
pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 4/5] ARM: dts: qcom: sd600-eval: pm8921_s2 regulator properties
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161221114939.19973-1-bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add the missing properties for pm8921 smps2.
Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index 39ae2bc8cb08..b7dcab28642d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -74,6 +74,14 @@
bias-pull-down;
};
+ s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
+
s3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
--
2.11.0
--
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^ permalink raw reply related
* [PATCH 5/5] ARM: dts: qcom: sd600eval: Enable riva-pil
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20161221114939.19973-1-bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index b7dcab28642d..8fee42901a3d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -355,5 +355,12 @@
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 1/7] Documentation: DT: bindings: iio: adc: add documentation for Allwinner SoCs' GPADC driver
From: Maxime Ripard @ 2016-12-21 12:20 UTC (permalink / raw)
To: Quentin Schulz
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wens-jdAy2FN1RRM, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
stefan.mavrodiev-Re5JQEeQqe8AvxtiuMwx3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
In-Reply-To: <61dc140a-5ef1-f55d-e749-cb816a014705-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 708 bytes --]
Hi,
On Tue, Dec 20, 2016 at 04:43:58PM +0100, Quentin Schulz wrote:
> >> +
> >> +Optional properties:
> >> +(for use with thermal framework for CPU thermal throttling for example, and/or
> >> + IIO consumers)
> >> + - #thermal-sensor-cells = <0>; (see
> >> +Documentation/devicetree/bindings/thermal/thermal.txt)
> >> + - #io-channel-cells = <0>; (see
> >> +Documentation/devicetree/bindings/iio/iio-bindings.txt)
> >
> > I wouldn't list that as optional.
>
> In what sense? Do you mean you wouldn't put them here at all or you
> would require them?
I would require them.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH net-next v4 0/2] Add support for the ethernet switch on the ESPRESSObin
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Romain Perier
This set of patches adds support for the Marvell ethernet switch 88E6341.
It also add the devicetree definition of this switch to the DT board.
Romain Perier (2):
net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >=
num_of_ports
net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341/88E6141
drivers/net/dsa/mv88e6xxx/chip.c | 48 ++++++++++++++++++++++++++++++-----
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 4 ++-
2 files changed, 45 insertions(+), 7 deletions(-)
--
Note: As requested by Gregory, I have removed the patch for the DT (already merged).
2.9.3
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^ permalink raw reply
* [PATCH net-next v4 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, linux-arm-kernel, Thomas Petazzoni,
Nadav Haklai, Romain Perier
In-Reply-To: <20161221125734.1034-1-romain.perier@free-electrons.com>
Some Marvell ethernet switches have internal ethernet transceivers with
hardcoded phy addresses. These addresses can be greater than the number
of ports or its value might be different than the associated port number.
This is for example the case for MV88E6341 that has 6 ports and internal
Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14.
This commits fixes the issue by removing the condition in MDIO callbacks.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v4:
- Fixed typo in the commit log
Changes in v2:
- Added tag "Reviewed-by" by Andrew
- Fixed typo in the commit log
drivers/net/dsa/mv88e6xxx/chip.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index b5f0e1e..76d944e 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2881,9 +2881,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
u16 val;
int err;
- if (phy >= mv88e6xxx_num_ports(chip))
- return 0xffff;
-
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_phy_read(chip, phy, reg, &val);
mutex_unlock(&chip->reg_lock);
@@ -2896,9 +2893,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
struct mv88e6xxx_chip *chip = bus->priv;
int err;
- if (phy >= mv88e6xxx_num_ports(chip))
- return 0xffff;
-
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_phy_write(chip, phy, reg, val);
mutex_unlock(&chip->reg_lock);
--
2.9.3
^ permalink raw reply related
* [PATCH net-next v4 2/2] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341/88E6141
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, linux-arm-kernel, Thomas Petazzoni,
Nadav Haklai, Romain Perier
In-Reply-To: <20161221125734.1034-1-romain.perier@free-electrons.com>
The Marvell 88E6341 device is single-chip, 6-port ethernet switch with
four integrated 10/100/1000Mbps ethernet transceivers and one high speed
SerDes interfaces. It is compatible with switches of family 88E6352.
This commit adds basic support for this switch by describing its
capabilities to the driver.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v3:
- Added tag "Reviewed-by" by Andrew
Changes in v2:
- Add a dedicated data structure for the operations of the 88E6341
- Re-ordered PORT_SWITCH_ID_PROD_NUM_6341 in alphabetic order with other
macros
drivers/net/dsa/mv88e6xxx/chip.c | 42 +++++++++++++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 4 +++-
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 76d944e..5e97dc4 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3625,6 +3625,34 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6341_ops = {
+ /* MV88E6XXX_FAMILY_6352 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom16,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom16,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
+ .port_set_speed = mv88e6352_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6320_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6095_stats_get_sset_count,
+ .stats_get_strings = mv88e6095_stats_get_strings,
+ .stats_get_stats = mv88e6095_stats_get_stats,
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6350_ops = {
/* MV88E6XXX_FAMILY_6351 */
.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -4086,6 +4114,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6341] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .family = MV88E6XXX_FAMILY_6352,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+ .global1_addr = 0x1b,
+ .age_time_coeff = 15000,
+ .tag_protocol = DSA_TAG_PROTO_EDSA,
+ .flags = MV88E6XXX_FLAGS_FAMILY_6352,
+ .ops = &mv88e6341_ops,
+ },
+
[MV88E6350] = {
.prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
.family = MV88E6XXX_FAMILY_6351,
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
index af54bae..cb55fdb 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
@@ -100,6 +100,7 @@
#define PORT_SWITCH_ID_PROD_NUM_6240 0x240
#define PORT_SWITCH_ID_PROD_NUM_6290 0x290
#define PORT_SWITCH_ID_PROD_NUM_6321 0x310
+#define PORT_SWITCH_ID_PROD_NUM_6341 0x340
#define PORT_SWITCH_ID_PROD_NUM_6352 0x352
#define PORT_SWITCH_ID_PROD_NUM_6350 0x371
#define PORT_SWITCH_ID_PROD_NUM_6351 0x375
@@ -432,6 +433,7 @@ enum mv88e6xxx_model {
MV88E6290,
MV88E6320,
MV88E6321,
+ MV88E6341,
MV88E6350,
MV88E6351,
MV88E6352,
@@ -448,7 +450,7 @@ enum mv88e6xxx_family {
MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
MV88E6XXX_FAMILY_6320, /* 6320 6321 */
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
- MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
+ MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6341 6352 */
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
};
--
2.9.3
^ permalink raw reply related
* Re: [v4, 3/3] ARM: dts: vf610-zii-dev-rev-b: Remove 'fixed-link' from DSA ports
From: Nikita Yushchenko @ 2016-12-21 12:58 UTC (permalink / raw)
To: Andrey Smirnov, linux-arm-kernel
Cc: Mark Rutland, devicetree, andrew, Vivien Didelot, Russell King,
Stefan Agner, linux-kernel, Rob Herring, Sascha Hauer, Shawn Guo,
cphealy
In-Reply-To: <1482131877-6097-3-git-send-email-andrew.smirnov@gmail.com>
> Remove 'fixed-link' nodes from DSA ports since they are not needed (they
> are not limiting link's speed and the ports will be configured to their
> maximux speed as a default)
>
> Suggested-by: Andrew Lunn <andrew@lunn.ch>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
With this patch, ports connected to revB's second switch stop working.
Nikita
^ permalink raw reply
* Re: [PATCH v6] media: et8ek8: add device tree binding documentation
From: Pavel Machek @ 2016-12-21 13:20 UTC (permalink / raw)
To: Sakari Ailus
Cc: Rob Herring, ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w,
sre-DgEjT+Ai2ygdnm+yROfE0A, pali.rohar-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mchehab-JPH+aEBZ4P+UEJcrhfAQsw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220130538.GD16630-S+BSfZ9RZZmRSg0ZkenSGLdO1Tsj/99ntUK59QYPAWc@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 742 bytes --]
On Tue 2016-12-20 15:05:39, Sakari Ailus wrote:
> Hi Pavel,
>
> > +Endpoint node mandatory properties
> > +----------------------------------
> > +
> > +- remote-endpoint: A phandle to the bus receiver's endpoint node.
> > +
> > +Endpoint node optional properties
> > +----------------------------------
> > +
> > +- clock-lanes: <0>
> > +- data-lanes: <1..n>
>
> The driver makes no use of them and CCP2 only supports a single lane. I'll
> just remove these and apply it to my tree. Let's continue discussing the
> driver patch in the other thread.
Ok, thanks!
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
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^ permalink raw reply
* Re: [v4, 3/3] ARM: dts: vf610-zii-dev-rev-b: Remove 'fixed-link' from DSA ports
From: Uwe Kleine-König @ 2016-12-21 13:25 UTC (permalink / raw)
To: Nikita Yushchenko
Cc: Andrey Smirnov, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Vivien Didelot,
Russell King, Stefan Agner, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, andrew-g2DYL2Zd6BY, Sascha Hauer, Shawn Guo,
cphealy-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1482325125-15725-1-git-send-email-nikita.yoush-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Wed, Dec 21, 2016 at 03:58:45PM +0300, Nikita Yushchenko wrote:
> > Remove 'fixed-link' nodes from DSA ports since they are not needed (they
> > are not limiting link's speed and the ports will be configured to their
> > maximux speed as a default)
> >
> > Suggested-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> > Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> With this patch, ports connected to revB's second switch stop working.
This is probably because without a fixed-link node the phy-mode setting
isn't applied by the driver.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
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