* Re: [PATCH v3 net-next 0/3] Add support for the ethernet switch on the ESPRESSObin
From: David Miller @ 2016-12-21 16:10 UTC (permalink / raw)
To: romain.perier
Cc: andrew, vivien.didelot, f.fainelli, jason, sebastian.hesselbarth,
gregory.clement, netdev, devicetree, robh+dt, ijc+devicetree,
pawel.moll, mark.rutland, galak, linux-arm-kernel,
thomas.petazzoni, nadavh
In-Reply-To: <20161221090045.474-1-romain.perier@free-electrons.com>
net-next is not open, please do not submit net-next changes during this
time.
^ permalink raw reply
* Re: [PATCH v2] power: reset: add linkstation-reset driver
From: Sebastian Reichel @ 2016-12-21 15:59 UTC (permalink / raw)
To: Roger Shimizu
Cc: Rob Herring, linux-pm-u79uwXL29TY76Z2rM5mHXA, Andrew Lunn,
Ryan Tandy, Martin Michlmayr, Sylver Bruneau,
Herbert Valerio Riedel, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <CAEQ9gEnQEHdcA4ox3teOXKcrdf2AAqUMp=A6W6c7nXhk4VrKiw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 2141 bytes --]
Hi,
On Tue, Dec 20, 2016 at 02:37:39AM +0900, Roger Shimizu wrote:
> [...]
>
> >> +static void linkstation_reset(void)
> >> +{
> >> + const unsigned divisor = ((tclk + (8 * cfg->baud)) / (16 * cfg->baud));
> >> +
> >> + pr_err("%s: triggering power-off...\n", __func__);
> >> +
> >> + /* hijack UART1 and reset into sane state */
> >> + writel(0x83, UART1_REG(LCR));
> >> + writel(divisor & 0xff, UART1_REG(DLL));
> >> + writel((divisor >> 8) & 0xff, UART1_REG(DLM));
> >> + writel(cfg->magic[0], UART1_REG(LCR));
> >> + writel(cfg->magic[1], UART1_REG(IER));
> >> + writel(cfg->magic[2], UART1_REG(FCR));
> >> + writel(cfg->magic[3], UART1_REG(MCR));
> >> +
> >> + /* send the power-off command to PIC */
> >> + if(cfg->cmd[0][0] == 1 && cfg->cmd[1][0] == 0) {
> >> + /* if it's simply one-byte command, send it directly */
> >> + writel(cfg->cmd[0][1], UART1_REG(TX));
> >> + }
> >
> > I guess this optimization can be dropped and you can directly
> > call the for loop with uart1_micon_send().
>
> Same response regarding above two comments.
> The code is extensible because I want to extend in the future.
>
> Current implementation is just for Linkstation Pro / KuroBox Pro to be
> able to power-off.
> But for some other model of Linkstation, restart also need similar
> command via UART1.
>
> Just one example, Linkstation Pro is ARM based, but it was PowerPC based before.
> And the device support still exists in kernel tree:
> arch/powerpc/platforms/embedded6xx/linkstation.c
> arch/powerpc/platforms/embedded6xx/ls_uart.c
> It shows sending "C" to restart and sending "E" to power-off for
> PowerPC based Linkstation.
>
> I'm not actually interested in PowerPC based Linkstation, it's just an
> example to show the reason to be flexible.
>
> If other part is fine, may I send the v3 patch after merging
> linkstation-common.c into linkstation-reset.c?
> Thank you!
These models can just be added to qnap-poweroff, which handles
exactly this special case as far as I can see.
-- Sebastian
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH v2 pci/next] PCI: rcar: Add compatible string for r8a7796
From: Simon Horman @ 2016-12-21 15:36 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-pci, Bjorn Helgaas, Magnus Damm, Geert Uytterhoeven,
linux-renesas-soc, devicetree
In-Reply-To: <1482259026-7180-1-git-send-email-ykaneko0929@gmail.com>
On Wed, Dec 21, 2016 at 03:37:06AM +0900, Yoshihiro Kaneko wrote:
> From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
>
> This patch adds support for r8a7796.
>
> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply
* [PATCH v4 2/2] iio: adc: hx711: Add IIO driver for AVIA HX711
From: Andreas Klinger @ 2016-12-21 15:25 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, ak-n176/SwNRljddJNmlsFzeA
This is the IIO driver for AVIA HX711 ADC which ist mostly used in weighting
cells.
The protocol is quite simple and using GPIOs:
One GPIO is used as clock (SCK) while another GPIO is read (DOUT)
The raw value read from the chip is delivered.
To get a weight one needs to subtract the zero offset and scale it.
Signed-off-by: Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
---
drivers/iio/adc/Kconfig | 19 ++
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/hx711.c | 466 +++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 486 insertions(+)
create mode 100644 drivers/iio/adc/hx711.c
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 932de1f9d1e7..1dcf2ace1697 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -205,6 +205,25 @@ config HI8435
This driver can also be built as a module. If so, the module will be
called hi8435.
+config HX711
+ tristate "AVIA HX711 ADC for weight cells"
+ depends on GPIOLIB
+ help
+ If you say yes here you get support for AVIA HX711 ADC which is used
+ for weigh cells
+
+ This driver uses two GPIOs, one acts as the clock and controls the
+ channel selection and gain, the other one is used for the measurement
+ data
+
+ Currently the raw value is read from the chip and delivered.
+ To get an actual weight one needs to subtract the
+ zero offset and multiply by a scale factor.
+ This should be done in userspace.
+
+ This driver can also be built as a module. If so, the module will be
+ called hx711.
+
config INA2XX_ADC
tristate "Texas Instruments INA2xx Power Monitors IIO driver"
depends on I2C && !SENSORS_INA2XX
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index b1aa456e6af3..d46e289900ef 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_CC10001_ADC) += cc10001_adc.o
obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
obj-$(CONFIG_HI8435) += hi8435.o
+obj-$(CONFIG_HX711) += hx711.o
obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
diff --git a/drivers/iio/adc/hx711.c b/drivers/iio/adc/hx711.c
new file mode 100644
index 000000000000..f4b5f587e9c0
--- /dev/null
+++ b/drivers/iio/adc/hx711.c
@@ -0,0 +1,466 @@
+/*
+ * HX711: analog to digital converter for weight sensor module
+ *
+ * Copyright (c) 2016 Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#include <linux/err.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/property.h>
+#include <linux/slab.h>
+#include <linux/sched.h>
+#include <linux/delay.h>
+#include <linux/iio/iio.h>
+#include <linux/iio/sysfs.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regulator/consumer.h>
+
+/*
+ * gain to pulse and scale conversion
+ */
+#define HX711_CHAN_A 0 /* channel id for A */
+#define HX711_CHAN_B 1 /* channel id for B */
+
+#define HX711_GAIN_MAX 3
+
+struct hx711_gain_to_scale {
+ int gain;
+ int gain_pulse;
+ int scale;
+ int channel;
+};
+
+static struct hx711_gain_to_scale hx711_gain_to_scale[HX711_GAIN_MAX] = {
+ { 128, 1, 0, HX711_CHAN_A },
+ { 32, 2, 0, HX711_CHAN_B },
+ { 64, 3, 0, HX711_CHAN_A }
+};
+
+static int hx711_get_gain_to_pulse(int gain)
+{
+ int i;
+
+ for (i = 0; i < HX711_GAIN_MAX; i++)
+ if (hx711_gain_to_scale[i].gain == gain)
+ return hx711_gain_to_scale[i].gain_pulse;
+ return 1;
+}
+
+static int hx711_get_gain_to_scale(int gain)
+{
+ int i;
+
+ for (i = 0; i < HX711_GAIN_MAX; i++)
+ if (hx711_gain_to_scale[i].gain == gain)
+ return hx711_gain_to_scale[i].scale;
+ return 0;
+}
+
+static int hx711_get_scale_to_gain(int scale)
+{
+ int i;
+
+ for (i = 0; i < HX711_GAIN_MAX; i++)
+ if (hx711_gain_to_scale[i].scale == scale)
+ return hx711_gain_to_scale[i].gain;
+ return -EINVAL;
+}
+
+struct hx711_data {
+ struct device *dev;
+ struct gpio_desc *gpiod_pd_sck;
+ struct gpio_desc *gpiod_dout;
+ struct regulator *reg_avdd;
+ int gain_set; /* gain set on device */
+ int gain_chan_a; /* gain for channel A */
+ struct mutex lock;
+};
+
+static int hx711_read(struct hx711_data *hx711_data);
+
+static int hx711_reset(struct hx711_data *hx711_data)
+{
+ int ret;
+ int val = gpiod_get_value(hx711_data->gpiod_dout);
+
+ if (val) {
+ int i;
+
+ /*
+ * an examination with the oszilloscope indicated
+ * that the first value read after the reset is not stable
+ * if we reset too short;
+ * the shorter the reset cycle
+ * the less reliable the first value after reset is;
+ * there were no problems encountered with a value
+ * of 10 ms or higher
+ */
+ gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
+ msleep(10);
+ gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
+
+ /*
+ * a maximum reset cycle time of 56 ms was measured.
+ * we round it up to 100 ms
+ */
+ for (i = 0; i < 100; i++) {
+ val = gpiod_get_value(hx711_data->gpiod_dout);
+ if (!val)
+ break;
+ /* sleep at least 1 ms */
+ msleep(1);
+ }
+
+ /*
+ * after a reset the gain is 128 so we do a dummy read
+ * to set the gain for the next read
+ */
+ ret = hx711_read(hx711_data);
+ if (ret < 0)
+ return ret;
+ }
+
+ return val;
+}
+
+static int hx711_cycle(struct hx711_data *hx711_data)
+{
+ int val;
+
+ /*
+ * if preempted for more then 60us while PD_SCK is high:
+ * hx711 is going in reset
+ * ==> measuring is false
+ */
+ preempt_disable();
+ gpiod_set_value(hx711_data->gpiod_pd_sck, 1);
+ val = gpiod_get_value(hx711_data->gpiod_dout);
+ /*
+ * here we are not waiting for 0.2 us as suggested by the datasheet,
+ * because the oszilloscope showed in a test scenario
+ * at least 1.15 us for PD_SCK high (T3 in datasheet)
+ * and 0.56 us for PD_SCK low on TI Sitara with 800 MHz
+ */
+ gpiod_set_value(hx711_data->gpiod_pd_sck, 0);
+ preempt_enable();
+
+ return val;
+}
+
+static int hx711_read(struct hx711_data *hx711_data)
+{
+ int i, ret;
+ int value = 0;
+
+ if (hx711_reset(hx711_data)) {
+ dev_err(hx711_data->dev, "reset failed!");
+ return -EIO;
+ }
+
+ for (i = 0; i < 24; i++) {
+ value <<= 1;
+ ret = hx711_cycle(hx711_data);
+ if (ret)
+ value++;
+ }
+
+ value ^= 0x800000;
+
+ for (i = 0; i < hx711_get_gain_to_pulse(hx711_data->gain_set); i++)
+ hx711_cycle(hx711_data);
+
+ return value;
+}
+
+static int hx711_set_gain_for_channel(struct hx711_data *hx711_data, int chan)
+{
+ int ret;
+
+ if (chan == HX711_CHAN_A) {
+ if (hx711_data->gain_set == 32) {
+ hx711_data->gain_set = hx711_data->gain_chan_a;
+
+ ret = hx711_read(hx711_data);
+ if (ret < 0)
+ return ret;
+ }
+ } else {
+ if (hx711_data->gain_set != 32) {
+ hx711_data->gain_set = 32;
+
+ ret = hx711_read(hx711_data);
+ if (ret < 0)
+ return ret;
+ }
+ }
+
+ return 0;
+}
+
+static int hx711_read_raw(struct iio_dev *iio_dev,
+ const struct iio_chan_spec *chan,
+ int *val, int *val2, long mask)
+{
+ struct hx711_data *hx711_data = iio_priv(iio_dev);
+ int ret;
+
+ mutex_lock(&hx711_data->lock);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ ret = hx711_set_gain_for_channel(hx711_data, chan->channel);
+ if (ret < 0) {
+ mutex_unlock(&hx711_data->lock);
+ return ret;
+ }
+
+ *val = hx711_read(hx711_data);
+ mutex_unlock(&hx711_data->lock);
+ if (*val < 0)
+ return *val;
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SCALE:
+ *val = 0;
+ *val2 = hx711_get_gain_to_scale(hx711_data->gain_set);
+ mutex_unlock(&hx711_data->lock);
+ return IIO_VAL_INT_PLUS_NANO;
+ default:
+ mutex_unlock(&hx711_data->lock);
+ return -EINVAL;
+ }
+}
+
+static int hx711_write_raw(struct iio_dev *iio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ struct hx711_data *hx711_data = iio_priv(iio_dev);
+ int ret;
+ int gain;
+
+ switch (mask) {
+ case IIO_CHAN_INFO_SCALE:
+ /*
+ * a scale greater than 1 mV per LSB is not possible
+ * with the HX711, therefore val must be 0
+ */
+ if (val != 0)
+ return -EINVAL;
+
+ mutex_lock(&hx711_data->lock);
+
+ gain = hx711_get_scale_to_gain(val2);
+ if (gain < 0) {
+ mutex_unlock(&hx711_data->lock);
+ return gain;
+ }
+
+ if (gain != hx711_data->gain_set) {
+ hx711_data->gain_set = gain;
+ if (gain != 32)
+ hx711_data->gain_chan_a = gain;
+
+ ret = hx711_read(hx711_data);
+ if (ret < 0) {
+ mutex_unlock(&hx711_data->lock);
+ return ret;
+ }
+ }
+
+ mutex_unlock(&hx711_data->lock);
+ return 0;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int hx711_write_raw_get_fmt(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ long mask)
+{
+ return IIO_VAL_INT_PLUS_NANO;
+}
+
+static ssize_t hx711_scale_available_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "0.%09d 0.%09d 0.%09d\n",
+ hx711_gain_to_scale[0].scale,
+ hx711_gain_to_scale[2].scale,
+ hx711_gain_to_scale[1].scale);
+}
+
+static IIO_DEVICE_ATTR(scale_available, S_IRUGO,
+ hx711_scale_available_show, NULL, 0);
+
+static struct attribute *hx711_attributes[] = {
+ &iio_dev_attr_scale_available.dev_attr.attr,
+ NULL,
+};
+
+static struct attribute_group hx711_attribute_group = {
+ .attrs = hx711_attributes,
+};
+
+static const struct iio_info hx711_iio_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = hx711_read_raw,
+ .write_raw = hx711_write_raw,
+ .write_raw_get_fmt = hx711_write_raw_get_fmt,
+ .attrs = &hx711_attribute_group,
+};
+
+static const struct iio_chan_spec hx711_chan_spec[] = {
+ {
+ .type = IIO_VOLTAGE,
+ .channel = HX711_CHAN_A,
+ .indexed = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ },
+ {
+ .type = IIO_VOLTAGE,
+ .channel = HX711_CHAN_B,
+ .indexed = 1,
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
+ .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),
+ },
+};
+
+static int hx711_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct hx711_data *hx711_data;
+ struct iio_dev *iio;
+ int ret;
+ int i;
+
+ iio = devm_iio_device_alloc(dev, sizeof(struct hx711_data));
+ if (!iio) {
+ dev_err(dev, "failed to allocate IIO device\n");
+ return -ENOMEM;
+ }
+
+ hx711_data = iio_priv(iio);
+ hx711_data->dev = dev;
+
+ mutex_init(&hx711_data->lock);
+
+ /* PD_SCK stands for power down and serial clock input of HX711
+ * in the driver it is an output
+ */
+ hx711_data->gpiod_pd_sck = devm_gpiod_get(dev, "sck", GPIOD_OUT_LOW);
+ if (IS_ERR(hx711_data->gpiod_pd_sck)) {
+ dev_err(dev, "failed to get sck-gpiod: err=%ld\n",
+ PTR_ERR(hx711_data->gpiod_pd_sck));
+ return PTR_ERR(hx711_data->gpiod_pd_sck);
+ }
+
+ /* DOUT stands for serial data output of HX711
+ * for the driver it is an input
+ */
+ hx711_data->gpiod_dout = devm_gpiod_get(dev, "dout", GPIOD_IN);
+ if (IS_ERR(hx711_data->gpiod_dout)) {
+ dev_err(dev, "failed to get dout-gpiod: err=%ld\n",
+ PTR_ERR(hx711_data->gpiod_dout));
+ return PTR_ERR(hx711_data->gpiod_dout);
+ }
+
+ hx711_data->reg_avdd = devm_regulator_get(dev, "avdd");
+ if (IS_ERR(hx711_data->reg_avdd))
+ return PTR_ERR(hx711_data->reg_avdd);
+
+ ret = regulator_enable(hx711_data->reg_avdd);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * with
+ * full scale differential input range: AVDD / GAIN
+ * full scale output data: 2^24
+ * we can say:
+ * AVDD / GAIN = 2^24
+ * therefore:
+ * 1 LSB = AVDD / GAIN / 2^24
+ * AVDD is in uV, but we need 10^-9 mV
+ * approximately to fit into a 32 bit number:
+ * 1 LSB = (AVDD * 100) / GAIN / 1678 [10^-9 mV]
+ */
+ ret = regulator_get_voltage(hx711_data->reg_avdd);
+ if (ret < 0)
+ return ret;
+ /* we need 10^-9 mV */
+ ret *= 100;
+
+ for (i = 0; i < HX711_GAIN_MAX; i++)
+ hx711_gain_to_scale[i].scale =
+ ret / hx711_gain_to_scale[i].gain / 1678;
+
+ hx711_data->gain_set = 128;
+ hx711_data->gain_chan_a = 128;
+
+ platform_set_drvdata(pdev, iio);
+
+ iio->name = "hx711";
+ iio->dev.parent = &pdev->dev;
+ iio->info = &hx711_iio_info;
+ iio->modes = INDIO_DIRECT_MODE;
+ iio->channels = hx711_chan_spec;
+ iio->num_channels = ARRAY_SIZE(hx711_chan_spec);
+
+ return devm_iio_device_register(dev, iio);
+}
+
+static int hx711_remove(struct platform_device *pdev)
+{
+ struct hx711_data *hx711_data;
+ struct iio_dev *iio;
+
+ iio = platform_get_drvdata(pdev);
+ hx711_data = iio_priv(iio);
+
+ regulator_disable(hx711_data->reg_avdd);
+
+ return 0;
+}
+
+static const struct of_device_id of_hx711_match[] = {
+ { .compatible = "avia,hx711", },
+ {},
+};
+
+MODULE_DEVICE_TABLE(of, of_hx711_match);
+
+static struct platform_driver hx711_driver = {
+ .probe = hx711_probe,
+ .remove = hx711_remove,
+ .driver = {
+ .name = "hx711-gpio",
+ .of_match_table = of_hx711_match,
+ },
+};
+
+module_platform_driver(hx711_driver);
+
+MODULE_AUTHOR("Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>");
+MODULE_DESCRIPTION("HX711 bitbanging driver - ADC for weight cells");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:hx711-gpio");
+
--
2.1.4
^ permalink raw reply related
* [PATCH v4 1/2] iio: adc: hx711: Add DT binding for avia,hx711
From: Andreas Klinger @ 2016-12-21 15:24 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, ak-n176/SwNRljddJNmlsFzeA
Add DT bindings for avia,hx711
Add vendor avia to vendor list
[PATCH v3 1/2] of this patch was Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Sorry, but i had to add the regulator (avdd-supply) and therefore it
needs to be acked once again.
Signed-off-by: Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
---
.../devicetree/bindings/iio/adc/avia-hx711.txt | 18 ++++++++++++++++++
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
2 files changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
new file mode 100644
index 000000000000..b3629405f568
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
@@ -0,0 +1,18 @@
+* AVIA HX711 ADC chip for weight cells
+ Bit-banging driver
+
+Required properties:
+ - compatible: Should be "avia,hx711"
+ - sck-gpios: Definition of the GPIO for the clock
+ - dout-gpios: Definition of the GPIO for data-out
+ See Documentation/devicetree/bindings/gpio/gpio.txt
+ - avdd-supply: Definition of the regulator used as analog supply
+
+Example:
+weight@0 {
+ compatible = "avia,hx711";
+ sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
+ dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
+ avdd-suppy = <&avdd>;
+};
+
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 44ddc980b085..4696bb5c2198 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -32,6 +32,7 @@ atlas Atlas Scientific LLC
atmel Atmel Corporation
auo AU Optronics Corporation
avago Avago Technologies
+avia avia semiconductor
avic Shanghai AVIC Optoelectronics Co., Ltd.
axis Axis Communications AB
boe BOE Technology Group Co., Ltd.
--
2.1.4
^ permalink raw reply related
* [PATCH v4 0/2] iio: adc: hx711: Add IIO driver for AVIA HX711 ADC
From: Andreas Klinger @ 2016-12-21 15:24 UTC (permalink / raw)
To: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg, ak-n176/SwNRljddJNmlsFzeA
This series adds IIO driver support for the AVIA HX711 ADC which is
mostly used in weighting cells.
The first patch adds the new DT binding for which a new vendor avia
was also added.
The second patch is the simple IIO driver implemented as ADC.
The protocol is specific to this device and implemented using GPIOs.
Documentation of the chip can be found here:
https://cdn.sparkfun.com/datasheets/Sensors/ForceFlex/hx711_english.pdf
Changes in v4:
Thanks to the thorough reviews and suggestions of Jonathan and Lars-Peter
the driver was reworked to better meet the standard ABI of IIO.
* Patch 1: "iio: adc: hx711: Add DT binding for avia,hx711"
- added attribute for regulator
* Patch 2: "iio: adc: hx711: Add IIO driver for AVIA HX711"
- two read channels for physical channels A and B
- remove gain attribute and use scale as read raw
- offer scale_available attribute
- introduced regulator as analog supply; mainly needed for calculating
the scale
- simplyfied use of GPIOs
- measuring input and output with oszilloscope and revised timing behavior
- many minor changes
Changes in v3:
moved gain from devicetree to sysfs, according to comment of Lars-Peter
Thanks for reviewing and giving suggestions
* Patch 1: "iio: adc: hx711: Add DT binding for avia,hx711"
- removed property gain
* Patch 2: "iio: adc: hx711: Add IIO driver for AVIA HX711"
- removed property gain from devicetree
- added device attribute (rw) for gain
- support reading from both channels now
Changes in v2:
Lots of updates thanks to Peters review.
* Patch 1: "iio: adc: hx711: Add DT binding for avia,hx711"
- typo
- removed unneded section
* Patch 2: "iio: adc: hx711: Add IIO driver for AVIA HX711"
- updated help text in Kconfig
- removed dead code
- removed unused power management
- reduced channel spec to what is actually used
- added error handling in case reset of chip not possible
Andreas Klinger (2):
iio: adc: hx711: Add DT binding for avia,hx711
iio: adc: hx711: Add IIO driver for AVIA HX711
.../devicetree/bindings/iio/adc/avia-hx711.txt | 18 +
.../devicetree/bindings/vendor-prefixes.txt | 1 +
drivers/iio/adc/Kconfig | 19 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/hx711.c | 466 +++++++++++++++++++++
5 files changed, 505 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
create mode 100644 drivers/iio/adc/hx711.c
--
2.1.4
^ permalink raw reply
* Re: [v4, 3/3] ARM: dts: vf610-zii-dev-rev-b: Remove 'fixed-link' from DSA ports
From: Andrew Lunn @ 2016-12-21 15:22 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Nikita Yushchenko, Andrey Smirnov,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
devicetree-u79uwXL29TY76Z2rM5mHXA, Vivien Didelot, Russell King,
Stefan Agner, linux-kernel-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
Sascha Hauer, Shawn Guo, cphealy-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <20161221132519.bkkqyfk3beow7nc5-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
On Wed, Dec 21, 2016 at 02:25:19PM +0100, Uwe Kleine-König wrote:
> On Wed, Dec 21, 2016 at 03:58:45PM +0300, Nikita Yushchenko wrote:
> > > Remove 'fixed-link' nodes from DSA ports since they are not needed (they
> > > are not limiting link's speed and the ports will be configured to their
> > > maximux speed as a default)
> > >
> > > Suggested-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> > > Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> >
> > With this patch, ports connected to revB's second switch stop working.
>
> This is probably because without a fixed-link node the phy-mode setting
> isn't applied by the driver.
Yep, bad suggestion from me. If the phy-mode was not needed, then you
can drop the fixed-link. With the phy-mode, you also need the fixed
link.
Sorry for the wasted time,
Andrew
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 0/9] Implement clocksource for rockchip SoC using rockchip timer
From: Alexander Kochetkov @ 2016-12-21 14:21 UTC (permalink / raw)
To: LKML, devicetree-u79uwXL29TY76Z2rM5mHXA, LAK,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Daniel Lezcano,
Heiko Stuebner
Cc: Thomas Gleixner, Mark Rutland, Rob Herring, Russell King,
Caesar Wang, Huang Tao
In-Reply-To: <1480436092-10728-1-git-send-email-al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Hello Heiko, Daniel!
Are there any reasons why the patches [1][2] are not applied yet into kernel?
How can I help in applying patches?
Regards,
Alexander.
[1] http://lists.infradead.org/pipermail/linux-rockchip/2016-November/thread.html#13236
[PATCH v4 0/9] Implement clocksource for rockchip SoC using rockchip timer
[2] http://lists.infradead.org/pipermail/linux-rockchip/2016-December/013308.html
> 29 нояб. 2016 г., в 19:14, Alexander Kochetkov <al.kochet-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> написал(а):
>
> Hello,
>
> This patch series contain:
> - devicetree bindings clarification for rockchip timers
> - dts files fixes for rk3228-evb, rk3229-evb and rk3188
> - implementation of clocksource and sched clock for rockchip SoC
>
> The clock supplying the arm-global-timer on the rk3188 is coming from the
> the cpu clock itself and thus changes its rate everytime cpufreq adjusts
> the cpu frequency making this timer unsuitable as a stable clocksource.
>
> The rk3188, rk3288 and following socs share a separate timer block already
> handled by the rockchip-timer driver. Therefore adapt this driver to also
> be able to act as clocksource on rk3188.
>
> In order to test clocksource you can run following commands and check
> how much time it take in real. On rk3188 it take about ~45 seconds.
>
> cpufreq-set -f 1.6GHZ
> date; sleep 60; date
>
> rk3288 (and probably anything newer) is irrelevant to this patch,
> as it has the arch timer interface. This patch may be usefull
> for Cortex-A9/A5 based parts.
>
> Regards,
> Alexander.
>
> This is try 4. Please discard all v1, v2, v3 patches.
>
> Changes in v4:
> merged 7 and 8 from series 3
> merged 10, 11, 12, 13 from series 3
> fixed commit message
>
> Changes in v3:
> added patches:
> ARM: dts: rockchip: disable arm-global-timer for rk3188
> clocksource/drivers/rockchip_timer: Prevent ftrace recursion
>
> devicetree v1 patches:
> https://patchwork.ozlabs.org/patch/699019/
> https://patchwork.ozlabs.org/patch/699020/
>
> kernel v1 patches:
> https://patchwork.kernel.org/patch/9443975/
> https://patchwork.kernel.org/patch/9443971/
> https://patchwork.kernel.org/patch/9443959/
> https://patchwork.kernel.org/patch/9443963/
> https://patchwork.kernel.org/patch/9443979/
> https://patchwork.kernel.org/patch/9443989/
> https://patchwork.kernel.org/patch/9443987/
> https://patchwork.kernel.org/patch/9443977/
> https://patchwork.kernel.org/patch/9443991/
>
> Alexander Kochetkov (9):
> dt-bindings: clarify compatible property for rockchip timers
> ARM: dts: rockchip: update compatible property for rk3228 timer
> ARM: dts: rockchip: update compatible property for rk3229 timer
> ARM: dts: rockchip: add timer entries to rk3188 SoC
> ARM: dts: rockchip: disable arm-global-timer for rk3188
> clocksource/drivers/rockchip_timer: split bc_timer into rk_timer and
> rk_clock_event_device
> clocksource/drivers/rockchip_timer: low level routines take rk_timer
> as parameter
> clocksource/drivers/rockchip_timer: move TIMER_INT_UNMASK out of
> rk_timer_enable()
> clocksource/drivers/rockchip_timer: implement clocksource timer
>
> .../bindings/timer/rockchip,rk-timer.txt | 12 +-
> arch/arm/boot/dts/rk3188.dtsi | 17 ++
> arch/arm/boot/dts/rk3228-evb.dts | 4 +
> arch/arm/boot/dts/rk3229-evb.dts | 4 +
> drivers/clocksource/rockchip_timer.c | 207 +++++++++++++++-----
> 5 files changed, 190 insertions(+), 54 deletions(-)
>
> --
> 1.7.9.5
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [v4,1/3] ARM: dts: vf610-zii-dev-rev-b: Remove leftover PWM pingroup
From: Nikita Yushchenko @ 2016-12-21 13:30 UTC (permalink / raw)
To: Andrey Smirnov, linux-arm-kernel
Cc: Nikita Yushchenko, Mark Rutland, devicetree, andrew,
Vivien Didelot, Russell King, Stefan Agner, linux-kernel,
Rob Herring, Sascha Hauer, Shawn Guo, cphealy
In-Reply-To: <1482131877-6097-1-git-send-email-andrew.smirnov@gmail.com>
> Remove pwm0grp since it is:
>
> a) Not referenced anywhere in the DTS file (unlike Tower board it
> is based on, this board does not use/expose FTM0)
>
> b) Configures PTB2 and PTB3 in a way that contradicts
> pinctrl-mdio-mux
>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
Tested-by: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
^ permalink raw reply
* Re: [v4, 3/3] ARM: dts: vf610-zii-dev-rev-b: Remove 'fixed-link' from DSA ports
From: Uwe Kleine-König @ 2016-12-21 13:25 UTC (permalink / raw)
To: Nikita Yushchenko
Cc: Andrey Smirnov, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA, Vivien Didelot,
Russell King, Stefan Agner, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, andrew-g2DYL2Zd6BY, Sascha Hauer, Shawn Guo,
cphealy-Re5JQEeQqe8AvxtiuMwx3w
In-Reply-To: <1482325125-15725-1-git-send-email-nikita.yoush-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
On Wed, Dec 21, 2016 at 03:58:45PM +0300, Nikita Yushchenko wrote:
> > Remove 'fixed-link' nodes from DSA ports since they are not needed (they
> > are not limiting link's speed and the ports will be configured to their
> > maximux speed as a default)
> >
> > Suggested-by: Andrew Lunn <andrew-g2DYL2Zd6BY@public.gmane.org>
> > Signed-off-by: Andrey Smirnov <andrew.smirnov-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>
> With this patch, ports connected to revB's second switch stop working.
This is probably because without a fixed-link node the phy-mode setting
isn't applied by the driver.
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v6] media: et8ek8: add device tree binding documentation
From: Pavel Machek @ 2016-12-21 13:20 UTC (permalink / raw)
To: Sakari Ailus
Cc: Rob Herring, ivo.g.dimitrov.75-Re5JQEeQqe8AvxtiuMwx3w,
sre-DgEjT+Ai2ygdnm+yROfE0A, pali.rohar-Re5JQEeQqe8AvxtiuMwx3w,
linux-media-u79uwXL29TY76Z2rM5mHXA, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, mchehab-JPH+aEBZ4P+UEJcrhfAQsw,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220130538.GD16630-S+BSfZ9RZZmRSg0ZkenSGLdO1Tsj/99ntUK59QYPAWc@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 742 bytes --]
On Tue 2016-12-20 15:05:39, Sakari Ailus wrote:
> Hi Pavel,
>
> > +Endpoint node mandatory properties
> > +----------------------------------
> > +
> > +- remote-endpoint: A phandle to the bus receiver's endpoint node.
> > +
> > +Endpoint node optional properties
> > +----------------------------------
> > +
> > +- clock-lanes: <0>
> > +- data-lanes: <1..n>
>
> The driver makes no use of them and CCP2 only supports a single lane. I'll
> just remove these and apply it to my tree. Let's continue discussing the
> driver patch in the other thread.
Ok, thanks!
Pavel
--
(english) http://www.livejournal.com/~pavelmachek
(cesky, pictures) http://atrey.karlin.mff.cuni.cz/~pavel/picture/horses/blog.html
[-- Attachment #2: Digital signature --]
[-- Type: application/pgp-signature, Size: 181 bytes --]
^ permalink raw reply
* Re: [v4, 3/3] ARM: dts: vf610-zii-dev-rev-b: Remove 'fixed-link' from DSA ports
From: Nikita Yushchenko @ 2016-12-21 12:58 UTC (permalink / raw)
To: Andrey Smirnov, linux-arm-kernel
Cc: Mark Rutland, devicetree, andrew, Vivien Didelot, Russell King,
Stefan Agner, linux-kernel, Rob Herring, Sascha Hauer, Shawn Guo,
cphealy
In-Reply-To: <1482131877-6097-3-git-send-email-andrew.smirnov@gmail.com>
> Remove 'fixed-link' nodes from DSA ports since they are not needed (they
> are not limiting link's speed and the ports will be configured to their
> maximux speed as a default)
>
> Suggested-by: Andrew Lunn <andrew@lunn.ch>
> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
With this patch, ports connected to revB's second switch stop working.
Nikita
^ permalink raw reply
* [PATCH net-next v4 2/2] net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341/88E6141
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, linux-arm-kernel, Thomas Petazzoni,
Nadav Haklai, Romain Perier
In-Reply-To: <20161221125734.1034-1-romain.perier@free-electrons.com>
The Marvell 88E6341 device is single-chip, 6-port ethernet switch with
four integrated 10/100/1000Mbps ethernet transceivers and one high speed
SerDes interfaces. It is compatible with switches of family 88E6352.
This commit adds basic support for this switch by describing its
capabilities to the driver.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v3:
- Added tag "Reviewed-by" by Andrew
Changes in v2:
- Add a dedicated data structure for the operations of the 88E6341
- Re-ordered PORT_SWITCH_ID_PROD_NUM_6341 in alphabetic order with other
macros
drivers/net/dsa/mv88e6xxx/chip.c | 42 +++++++++++++++++++++++++++++++++++
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 4 +++-
2 files changed, 45 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index 76d944e..5e97dc4 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -3625,6 +3625,34 @@ static const struct mv88e6xxx_ops mv88e6321_ops = {
.reset = mv88e6352_g1_reset,
};
+static const struct mv88e6xxx_ops mv88e6341_ops = {
+ /* MV88E6XXX_FAMILY_6352 */
+ .get_eeprom = mv88e6xxx_g2_get_eeprom16,
+ .set_eeprom = mv88e6xxx_g2_set_eeprom16,
+ .set_switch_mac = mv88e6xxx_g2_set_switch_mac,
+ .phy_read = mv88e6xxx_g2_smi_phy_read,
+ .phy_write = mv88e6xxx_g2_smi_phy_write,
+ .port_set_link = mv88e6xxx_port_set_link,
+ .port_set_duplex = mv88e6xxx_port_set_duplex,
+ .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
+ .port_set_speed = mv88e6352_port_set_speed,
+ .port_tag_remap = mv88e6095_port_tag_remap,
+ .port_set_frame_mode = mv88e6351_port_set_frame_mode,
+ .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns,
+ .port_set_ether_type = mv88e6351_port_set_ether_type,
+ .port_jumbo_config = mv88e6165_port_jumbo_config,
+ .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
+ .port_pause_config = mv88e6097_port_pause_config,
+ .stats_snapshot = mv88e6320_g1_stats_snapshot,
+ .stats_get_sset_count = mv88e6095_stats_get_sset_count,
+ .stats_get_strings = mv88e6095_stats_get_strings,
+ .stats_get_stats = mv88e6095_stats_get_stats,
+ .g1_set_cpu_port = mv88e6095_g1_set_cpu_port,
+ .g1_set_egress_port = mv88e6095_g1_set_egress_port,
+ .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu,
+ .reset = mv88e6352_g1_reset,
+};
+
static const struct mv88e6xxx_ops mv88e6350_ops = {
/* MV88E6XXX_FAMILY_6351 */
.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
@@ -4086,6 +4114,20 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
.ops = &mv88e6321_ops,
},
+ [MV88E6341] = {
+ .prod_num = PORT_SWITCH_ID_PROD_NUM_6341,
+ .family = MV88E6XXX_FAMILY_6352,
+ .name = "Marvell 88E6341",
+ .num_databases = 4096,
+ .num_ports = 6,
+ .port_base_addr = 0x10,
+ .global1_addr = 0x1b,
+ .age_time_coeff = 15000,
+ .tag_protocol = DSA_TAG_PROTO_EDSA,
+ .flags = MV88E6XXX_FLAGS_FAMILY_6352,
+ .ops = &mv88e6341_ops,
+ },
+
[MV88E6350] = {
.prod_num = PORT_SWITCH_ID_PROD_NUM_6350,
.family = MV88E6XXX_FAMILY_6351,
diff --git a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
index af54bae..cb55fdb 100644
--- a/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
+++ b/drivers/net/dsa/mv88e6xxx/mv88e6xxx.h
@@ -100,6 +100,7 @@
#define PORT_SWITCH_ID_PROD_NUM_6240 0x240
#define PORT_SWITCH_ID_PROD_NUM_6290 0x290
#define PORT_SWITCH_ID_PROD_NUM_6321 0x310
+#define PORT_SWITCH_ID_PROD_NUM_6341 0x340
#define PORT_SWITCH_ID_PROD_NUM_6352 0x352
#define PORT_SWITCH_ID_PROD_NUM_6350 0x371
#define PORT_SWITCH_ID_PROD_NUM_6351 0x375
@@ -432,6 +433,7 @@ enum mv88e6xxx_model {
MV88E6290,
MV88E6320,
MV88E6321,
+ MV88E6341,
MV88E6350,
MV88E6351,
MV88E6352,
@@ -448,7 +450,7 @@ enum mv88e6xxx_family {
MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
MV88E6XXX_FAMILY_6320, /* 6320 6321 */
MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
- MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
+ MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6341 6352 */
MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
};
--
2.9.3
^ permalink raw reply related
* [PATCH net-next v4 1/2] net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >= num_of_ports
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev, devicetree, Rob Herring, Ian Campbell, Pawel Moll,
Mark Rutland, Kumar Gala, linux-arm-kernel, Thomas Petazzoni,
Nadav Haklai, Romain Perier
In-Reply-To: <20161221125734.1034-1-romain.perier@free-electrons.com>
Some Marvell ethernet switches have internal ethernet transceivers with
hardcoded phy addresses. These addresses can be greater than the number
of ports or its value might be different than the associated port number.
This is for example the case for MV88E6341 that has 6 ports and internal
Port 1 to Port4 PHYs mapped at SMI addresses from 0x11 to 0x14.
This commits fixes the issue by removing the condition in MDIO callbacks.
Signed-off-by: Romain Perier <romain.perier@free-electrons.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
Changes in v4:
- Fixed typo in the commit log
Changes in v2:
- Added tag "Reviewed-by" by Andrew
- Fixed typo in the commit log
drivers/net/dsa/mv88e6xxx/chip.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
index b5f0e1e..76d944e 100644
--- a/drivers/net/dsa/mv88e6xxx/chip.c
+++ b/drivers/net/dsa/mv88e6xxx/chip.c
@@ -2881,9 +2881,6 @@ static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
u16 val;
int err;
- if (phy >= mv88e6xxx_num_ports(chip))
- return 0xffff;
-
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_phy_read(chip, phy, reg, &val);
mutex_unlock(&chip->reg_lock);
@@ -2896,9 +2893,6 @@ static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
struct mv88e6xxx_chip *chip = bus->priv;
int err;
- if (phy >= mv88e6xxx_num_ports(chip))
- return 0xffff;
-
mutex_lock(&chip->reg_lock);
err = mv88e6xxx_phy_write(chip, phy, reg, val);
mutex_unlock(&chip->reg_lock);
--
2.9.3
^ permalink raw reply related
* [PATCH net-next v4 0/2] Add support for the ethernet switch on the ESPRESSObin
From: Romain Perier @ 2016-12-21 12:57 UTC (permalink / raw)
To: Andrew Lunn, Vivien Didelot, Florian Fainelli, Jason Cooper,
Sebastian Hesselbarth, Gregory Clement
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
Rob Herring, Ian Campbell, Pawel Moll, Mark Rutland, Kumar Gala,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
Thomas Petazzoni, Nadav Haklai, Romain Perier
This set of patches adds support for the Marvell ethernet switch 88E6341.
It also add the devicetree definition of this switch to the DT board.
Romain Perier (2):
net: dsa: mv88e6xxx: Don't forbid MDIO I/Os for PHY addr >=
num_of_ports
net: dsa: mv88e6xxx: Add support for ethernet switch 88E6341/88E6141
drivers/net/dsa/mv88e6xxx/chip.c | 48 ++++++++++++++++++++++++++++++-----
drivers/net/dsa/mv88e6xxx/mv88e6xxx.h | 4 ++-
2 files changed, 45 insertions(+), 7 deletions(-)
--
Note: As requested by Gregory, I have removed the patch for the DT (already merged).
2.9.3
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 1/7] Documentation: DT: bindings: iio: adc: add documentation for Allwinner SoCs' GPADC driver
From: Maxime Ripard @ 2016-12-21 12:20 UTC (permalink / raw)
To: Quentin Schulz
Cc: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
wens-jdAy2FN1RRM, lee.jones-QSEj5FYQhm4dnm+yROfE0A,
linux-I+IVW8TIWO2tmTQ+vhA3Yw,
stefan.mavrodiev-Re5JQEeQqe8AvxtiuMwx3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8
In-Reply-To: <61dc140a-5ef1-f55d-e749-cb816a014705-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 708 bytes --]
Hi,
On Tue, Dec 20, 2016 at 04:43:58PM +0100, Quentin Schulz wrote:
> >> +
> >> +Optional properties:
> >> +(for use with thermal framework for CPU thermal throttling for example, and/or
> >> + IIO consumers)
> >> + - #thermal-sensor-cells = <0>; (see
> >> +Documentation/devicetree/bindings/thermal/thermal.txt)
> >> + - #io-channel-cells = <0>; (see
> >> +Documentation/devicetree/bindings/iio/iio-bindings.txt)
> >
> > I wouldn't list that as optional.
>
> In what sense? Do you mean you wouldn't put them here at all or you
> would require them?
I would require them.
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 801 bytes --]
^ permalink raw reply
* [PATCH 5/5] ARM: dts: qcom: sd600eval: Enable riva-pil
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel
In-Reply-To: <20161221114939.19973-1-bjorn.andersson@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index b7dcab28642d..8fee42901a3d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -355,5 +355,12 @@
cd-gpios = <&tlmm_pinmux 26 GPIO_ACTIVE_HIGH>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
^ permalink raw reply related
* [PATCH 4/5] ARM: dts: qcom: sd600-eval: pm8921_s2 regulator properties
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161221114939.19973-1-bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Add the missing properties for pm8921 smps2.
Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
My SD600eval broke, so this is untested.
arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
index 39ae2bc8cb08..b7dcab28642d 100644
--- a/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-arrow-sd-600eval.dts
@@ -74,6 +74,14 @@
bias-pull-down;
};
+ s2 {
+ regulator-min-microvolt = <1300000>;
+ regulator-max-microvolt = <1300000>;
+ qcom,switch-mode-frequency = <1600000>;
+ bias-pull-down;
+ regulator-always-on;
+ };
+
s3 {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1400000>;
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 3/5] ARM: dts: qcom: apq8064-sony-yuga: Enable riva-pil
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm-u79uwXL29TY76Z2rM5mHXA,
linux-soc-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, John Stultz
In-Reply-To: <20161221114939.19973-1-bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Cc: John Stultz <john.stultz-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
---
arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
index ebd675ca94b4..a34ba3555454 100644
--- a/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
+++ b/arch/arm/boot/dts/qcom-apq8064-sony-xperia-yuga.dts
@@ -390,5 +390,12 @@
pinctrl-0 = <&sdcc3_pins>, <&sdcc3_cd_pin_a>;
};
};
+
+ riva-pil@3204000 {
+ status = "okay";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&riva_wlan_pin_a>, <&riva_bt_pin_a>, <&riva_fm_pin_a>;
+ };
};
};
--
2.11.0
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [PATCH 2/5] ARM: dts: qcom: apq8064: Add riva-pil node
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Mark Rutland, devicetree, linux-arm-msm, linux-kernel,
Rob Herring, John Stultz, linux-soc, linux-arm-kernel
In-Reply-To: <20161221114939.19973-1-bjorn.andersson@linaro.org>
Add nodes for the Riva PIL, IRIS RF module, BT and WiFI services exposed
by the Riva firmware and the related memory reserve.
Also provides pinctrl nodes for devices enabling the riva-pil.
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064-pins.dtsi | 18 +++++++++
arch/arm/boot/dts/qcom-apq8064.dtsi | 69 +++++++++++++++++++++++++++++++-
2 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
index 6b801e7e57a2..5c023e649882 100644
--- a/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064-pins.dtsi
@@ -284,4 +284,22 @@
bias-disable = <0>;
};
};
+
+ riva_fm_pin_a: riva-fm-active {
+ pins = "gpio14", "gpio15";
+ function = "riva_fm";
+ };
+
+ riva_bt_pin_a: riva-bt-active {
+ pins = "gpio16", "gpio17";
+ function = "riva_bt";
+ };
+
+ riva_wlan_pin_a: riva-wlan-active {
+ pins = "gpio64", "gpio65", "gpio66", "gpio67", "gpio68";
+ function = "riva_wlan";
+
+ drive-strength = <6>;
+ bias-pull-down;
+ };
};
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 78bf155a52f3..3dc7a7aa3450 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -21,6 +21,11 @@
reg = <0x80000000 0x200000>;
no-map;
};
+
+ wcnss_mem: wcnss@8f000000 {
+ reg = <0x8f000000 0x700000>;
+ no-map;
+ };
};
cpus {
@@ -179,7 +184,7 @@
};
clocks {
- cxo_board {
+ cxo_board: cxo_board {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <19200000>;
@@ -1419,6 +1424,68 @@
};
};
};
+
+ riva: riva-pil@3204000 {
+ compatible = "qcom,riva-pil";
+
+ reg = <0x03200800 0x1000>, <0x03202000 0x2000>, <0x03204000 0x100>;
+ reg-names = "ccu", "dxe", "pmu";
+
+ interrupts-extended = <&intc GIC_SPI 199 IRQ_TYPE_EDGE_RISING>,
+ <&wcnss_smsm 6 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog", "fatal";
+
+ memory-region = <&wcnss_mem>;
+
+ vddcx-supply = <&pm8921_s3>;
+ vddmx-supply = <&pm8921_l24>;
+ vddpx-supply = <&pm8921_s4>;
+
+ status = "disabled";
+
+ iris {
+ compatible = "qcom,wcn3660";
+
+ clocks = <&cxo_board>;
+ clock-names = "xo";
+
+ vddxo-supply = <&pm8921_l4>;
+ vddrfa-supply = <&pm8921_s2>;
+ vddpa-supply = <&pm8921_l10>;
+ vdddig-supply = <&pm8921_lvs2>;
+ };
+
+ smd-edge {
+ interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
+
+ qcom,ipc = <&l2cc 8 25>;
+ qcom,smd-edge = <6>;
+
+ label = "riva";
+
+ wcnss {
+ compatible = "qcom,wcnss";
+ qcom,smd-channels = "WCNSS_CTRL";
+
+ qcom,mmio = <&riva>;
+
+ bt {
+ compatible = "qcom,wcnss-bt";
+ };
+
+ wifi {
+ compatible = "qcom,wcnss-wlan";
+
+ interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "tx", "rx";
+
+ qcom,smem-states = <&apps_smsm 10>, <&apps_smsm 9>;
+ qcom,smem-state-names = "tx-enable", "tx-rings-empty";
+ };
+ };
+ };
+ };
};
};
#include "qcom-apq8064-pins.dtsi"
--
2.11.0
^ permalink raw reply related
* [PATCH 1/5] ARM: dts: qcom: apq8064: Add missing scm clock
From: Bjorn Andersson @ 2016-12-21 11:49 UTC (permalink / raw)
To: Andy Gross, David Brown
Cc: Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel, linux-kernel, John Stultz
As per the device tree binding the apq8064 scm node requires the core
clock to be specified, so add this.
Cc: John Stultz <john.stultz@linaro.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---
arch/arm/boot/dts/qcom-apq8064.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi
index 268bd470c865..78bf155a52f3 100644
--- a/arch/arm/boot/dts/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-apq8064.dtsi
@@ -303,6 +303,9 @@
firmware {
scm {
compatible = "qcom,scm-apq8064";
+
+ clocks = <&gcc CE3_CORE_CLK>;
+ clock-names = "core";
};
};
--
2.11.0
^ permalink raw reply related
* Re: [PATCH 2/3] NFC: trf7970a: Add device tree option of 1.8 Volt IO voltage
From: Geoff Lansberry @ 2016-12-21 11:47 UTC (permalink / raw)
To: Mark Greer
Cc: linux-wireless, lauro.venancio, aloisio.almeida, sameo, robh+dt,
mark.rutland, netdev, devicetree, linux-kernel, justin
In-Reply-To: <20161221022347.GB5444@animalcreek.com>
Thanks Mark. Should I resubmit patches with the requested edits today, or wait a bit for more comments? What is the desired etiquette?
> On Dec 20, 2016, at 9:23 PM, Mark Greer <mgreer@animalcreek.com> wrote:
>
>> On Tue, Dec 20, 2016 at 11:16:31AM -0500, Geoff Lansberry wrote:
>> From: Geoff Lansberry <geoff@kuvee.com>
>>
>> The TRF7970A has configuration options for supporting hardware designs
>> with 1.8 Volt or 3.3 Volt IO. This commit adds a device tree option,
>> using a fixed regulator binding, for setting the io voltage to match
>> the hardware configuration. If no option is supplied it defaults to
>> 3.3 volt configuration.
>
> Sign-off ?? Same comment for you other patches.
>
> <time passes>
>
> Okay I see you have it at the end of the patch. It should be here.
> 'git commit -s' is your friend.
>
>> ---
>> .../devicetree/bindings/net/nfc/trf7970a.txt | 4 ++--
>> drivers/nfc/trf7970a.c | 28 +++++++++++++++++++++-
>> 2 files changed, 29 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> index e262ac1..b5777d8 100644
>> --- a/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> +++ b/Documentation/devicetree/bindings/net/nfc/trf7970a.txt
>> @@ -21,9 +21,9 @@ Optional SoC Specific Properties:
>> - t5t-rmb-extra-byte-quirk: Specify that the trf7970a has the erratum
>> where an extra byte is returned by Read Multiple Block commands issued
>> to Type 5 tags.
>> +- vdd-io-supply: Regulator specifying voltage for vdd-io
>> - clock-frequency: Set to specify that the input frequency to the trf7970a is 13560000Hz or 27120000Hz
>>
>> -
>> Example (for ARM-based BeagleBone with TRF7970A on SPI1):
>>
>> &spi1 {
>> @@ -41,11 +41,11 @@ Example (for ARM-based BeagleBone with TRF7970A on SPI1):
>> <&gpio2 5 GPIO_ACTIVE_LOW>;
>> vin-supply = <&ldo3_reg>;
>> vin-voltage-override = <5000000>;
>> + vdd-io-supply = <&ldo2_reg>;
>> autosuspend-delay = <30000>;
>> irq-status-read-quirk;
>> en2-rf-quirk;
>> t5t-rmb-extra-byte-quirk;
>> - vdd_io_1v8;
>
> It was already mentioned but this shouldn't have been added in the
> previous patch so it shouldn't be here now.
>
>> clock-frequency = <27120000>;
>> status = "okay";
>> };
>> diff --git a/drivers/nfc/trf7970a.c b/drivers/nfc/trf7970a.c
>> index 4e051e9..8a88195 100644
>> --- a/drivers/nfc/trf7970a.c
>> +++ b/drivers/nfc/trf7970a.c
>
>> @@ -2062,6 +2068,7 @@ static int trf7970a_probe(struct spi_device *spi)
>> return ret;
>> }
>>
>> +
>
> Please don't add an extra blank line.
>
>> of_property_read_u32(np, "clock-frequency", &clk_freq);
>> if ((clk_freq != TRF7970A_27MHZ_CLOCK_FREQUENCY) ||
>> (clk_freq != TRF7970A_27MHZ_CLOCK_FREQUENCY)) {
>> @@ -2105,6 +2112,25 @@ static int trf7970a_probe(struct spi_device *spi)
>> if (uvolts > 4000000)
>> trf->chip_status_ctrl = TRF7970A_CHIP_STATUS_VRS5_3;
>>
>> + trf->regulator = devm_regulator_get(&spi->dev, "vdd-io");
>> + if (IS_ERR(trf->regulator)) {
>> + ret = PTR_ERR(trf->regulator);
>> + dev_err(trf->dev, "Can't get VDD_IO regulator: %d\n", ret);
>> + goto err_destroy_lock;
>> + }
>> +
>> + ret = regulator_enable(trf->regulator);
>> + if (ret) {
>> + dev_err(trf->dev, "Can't enable VDD_IO: %d\n", ret);
>> + goto err_destroy_lock;
>> + }
>> +
>> +
>
> Please don't add an extra blank line.
>
>> + if (regulator_get_voltage(trf->regulator) == 1800000) {
>> + trf->io_ctrl = TRF7970A_REG_IO_CTRL_IO_LOW;
>> + dev_dbg(trf->dev, "trf7970a config vdd_io to 1.8V\n");
>> + }
>> +
>> trf->ddev = nfc_digital_allocate_device(&trf7970a_nfc_ops,
>> TRF7970A_SUPPORTED_PROTOCOLS,
>> NFC_DIGITAL_DRV_CAPS_IN_CRC |
>> --
>> Signed-off-by: Geoff Lansberry <geoff@kuvee.com>
>
> Your 'Signed-off-by:' goes at the end of the commit description not here.
>
> Overall, I think you did the right thing (unless someone disagrees).
> Just some minor issues.
>
> Mark
> --
^ permalink raw reply
* [PATCH] ARM64: dts: meson-gxbb-odroidc2: fix GbE tx link breakage
From: Jerome Brunet @ 2016-12-21 11:31 UTC (permalink / raw)
To: Kevin Hilman, Carlo Caione, linux-amlogic, devicetree
Cc: Jerome Brunet, linux-arm-kernel, linux-kernel
OdroidC2 GbE link breaks under heavy tx transfer. This happens even if the
MAC does not enable Energy Efficient Ethernet (No Low Power state Idle on
the Tx path). The problem seems to come from the phy Rx path, entering the
LPI state.
Disabling EEE advertisement on the phy prevent this feature to be
negociated with the link partner and solve the issue.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
This patch is based on Linus recent master branch [0]
This patch depends on the series [1] which has been merged in this branch.
0: ba6d973f78eb ("Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net")
1: http://lkml.kernel.org/r/1480326409-25419-1-git-send-email-jbrunet@baylibre.com
Fix integration of eee-broken-modes
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 238fbeacd330..d8933e9e9a5a 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -147,6 +147,18 @@
status = "okay";
pinctrl-0 = <ð_rgmii_pins>;
pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
};
&ir {
--
2.7.4
^ permalink raw reply related
* Re: [alsa-devel] [PATCH v3 1/2] ASoC: cs35l35: Add support for Cirrus CS35L35 Amplifier
From: Charles Keepax @ 2016-12-21 10:53 UTC (permalink / raw)
To: Li Xu
Cc: alsa-devel-K7yf7f+aM1XWsZ/bQMPhNw,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
brian.austin-jGc1dHjMKG3QT0dZR+AlfA, tiwai-IBi9RG/b67k,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, lgirdwood-Re5JQEeQqe8AvxtiuMwx3w,
broonie-DgEjT+Ai2ygdnm+yROfE0A,
Paul.Handrigan-jGc1dHjMKG3QT0dZR+AlfA
In-Reply-To: <7566bac5-e4c4-49ff-91b3-bcd578cef21b-XU/xxMRwCJnfk+Ne4bZl5AC/G2K4zDHf@public.gmane.org>
On Tue, Dec 13, 2016 at 10:59:03AM -0600, Li Xu wrote:
> Add driver support for Cirrus Logic CS35L35 boosted
> speaker amplifier
>
> Signed-off-by: Li Xu <li.xu-jGc1dHjMKG3QT0dZR+AlfA@public.gmane.org>
> ---
Mostly just some minor comments.
> +struct classh_cfg {
> + /*
> + * Class H Algorithm Control Variables
> + * You can either have it done
> + * automatically or you can adjust
> + * these variables for tuning
> + *
> + * if you do not enable the internal algorithm
> + * you will get a set of mixer controls for
> + * Class H tuning
> + *
> + * Section 4.3 of the datasheet
> + */
> + /* Internal ClassH Algorithm */
Feels redundant to have this extra comment after the large comment
before it.
> +
> +#include <linux/module.h>
> +#include <linux/moduleparam.h>
> +#include <linux/version.h>
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/delay.h>
> +#include <linux/i2c.h>
> +#include <linux/slab.h>
> +#include <linux/workqueue.h>
Do we need the workqueue header we don't seem to use any
workqueues?
> +static int cs35l35_sdin_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol, int event)
> +{
> + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + int ret = 0;
> +
> + switch (event) {
> + case SND_SOC_DAPM_PRE_PMU:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MCLK_DIS_MASK, 0 << CS35L35_MCLK_DIS_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_DISCHG_FILT_MASK, 0 << CS35L35_DISCHG_FILT_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_PDN_ALL_MASK, 0);
> + break;
Break should be indented for kernel coding style.
> + case SND_SOC_DAPM_POST_PMD:
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_PDN_ALL_MASK, 1);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL1,
> + CS35L35_DISCHG_FILT_MASK, 1 << CS35L35_DISCHG_FILT_SHIFT);
> +
> + ret = wait_for_completion_timeout(&cs35l35->pdn_done,
> + msecs_to_jiffies(100));
> + if (ret == 0) {
> + dev_err(codec->dev, "TIMEOUT PDN_DONE did not complete in 100ms\n");
> + ret = -ETIMEDOUT;
> + }
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MCLK_DIS_MASK, 1 << CS35L35_MCLK_DIS_SHIFT);
> + break;
Ditto.
> + default:
> + dev_err(codec->dev, "Invalid event = 0x%x\n", event);
> + ret = -EINVAL;
> + }
> + return ret;
> +}
> +
> +static int cs35l35_main_amp_event(struct snd_soc_dapm_widget *w,
> + struct snd_kcontrol *kcontrol, int event)
> +{
> + struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + unsigned int reg[4];
> + int i;
> +
> + switch (event) {
> + case SND_SOC_DAPM_PRE_PMU:
> + if (cs35l35->pdata.bst_pdn_fet_on)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 0 << CS35L35_PDN_BST_FETON_SHIFT);
> + else
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 0 << CS35L35_PDN_BST_FETOFF_SHIFT);
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_MUTE_MASK, 0 << CS35L35_AMP_MUTE_SHIFT);
> + break;
> + case SND_SOC_DAPM_POST_PMU:
> + usleep_range(5000, 5100);
> + /* If PDM mode we must use VP
> + * for Voltage control
> + */
Does this comment need to split across multiple lines?
> +static int cs35l35_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
> +{
> + struct snd_soc_codec *codec = codec_dai->codec;
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> +
> + switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
> + case SND_SOC_DAIFMT_CBM_CFM:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MS_MASK, 1 << CS35L35_MS_SHIFT);
> + cs35l35->slave_mode = false;
> + break;
> + case SND_SOC_DAIFMT_CBS_CFS:
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_MS_MASK, 0 << CS35L35_MS_SHIFT);
> + cs35l35->slave_mode = true;
> + break;
> + default:
> + return -EINVAL;
> + }
> +
> + switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> + case SND_SOC_DAIFMT_I2S:
> + cs35l35->i2s_mode = true;
> + cs35l35->pdm_mode = false;
> + break;
> + case SND_SOC_DAIFMT_PDM:
> + cs35l35->pdm_mode = true;
> + cs35l35->i2s_mode = false;
Feels a bit redundant to have both of these if they are only ever
a logical inversion of each other.
> +static int cs35l35_get_clk_config(int sysclk, int srate)
> +{
> + int i;
> +
> + for (i = 0; i < ARRAY_SIZE(cs35l35_clk_ctl); i++) {
> + if (cs35l35_clk_ctl[i].sysclk == sysclk &&
> + cs35l35_clk_ctl[i].srate == srate)
> + return cs35l35_clk_ctl[i].clk_cfg;
> + }
> + return -EINVAL;
> +}
> +
> +static int cs35l35_pcm_hw_params(struct snd_pcm_substream *substream,
> + struct snd_pcm_hw_params *params,
> + struct snd_soc_dai *dai)
> +{
> + struct snd_soc_codec *codec = dai->codec;
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
> + int srate = params_rate(params);
> + int ret = 0;
> + u8 sp_sclks;
> + int audin_format;
> + int errata_chk;
> +
> + int clk_ctl = cs35l35_get_clk_config(cs35l35->sysclk, srate);
> +
> + if (clk_ctl < 0) {
> + dev_err(codec->dev, "Invalid CLK:Rate %d:%d\n",
> + cs35l35->sysclk, srate);
> + return -EINVAL;
> + }
It would normally be slightly better to set constraints in
startup based on the SYSCLK rather than returning an error in
hw_params. This allows user-space to negotiate a rate that is
actually supported and do any sample rate conversion required.
> +
> + ret = regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL2,
> + CS35L35_CLK_CTL2_MASK, clk_ctl);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set port config %d\n", ret);
> + return ret;
> + }
> +
> + /* Rev A0 Errata
> + *
> + * When configured for the weak-drive detection path (CH_WKFET_DIS = 0)
> + * the Class H algorithm does not enable weak-drive operation for
> + * nonzero values of CH_WKFET_DELAY if SP_RATE = 01 or 10
> + *
> + */
> + errata_chk = clk_ctl & CS35L35_SP_RATE_MASK;
> +
> + if (classh->classh_wk_fet_disable == 0x00 &&
> + (errata_chk == 0x01 || errata_chk == 0x03)) {
> + ret = regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DEL_MASK,
> + 0 << CS35L35_CH_WKFET_DEL_SHIFT);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set fet config %d\n",
> + ret);
> + return ret;
> + }
> + }
> +
> +/*
> + * You can pull more Monitor data from the SDOUT pin than going to SDIN
> + * Just make sure your SCLK is fast enough to fill the frame
> + */
> + if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
> + switch (params_width(params)) {
> + case 8:
> + audin_format = CS35L35_SDIN_DEPTH_8;
> + break;
> + case 16:
> + audin_format = CS35L35_SDIN_DEPTH_16;
> + break;
> + case 24:
> + audin_format = CS35L35_SDIN_DEPTH_24;
> + break;
> + default:
> + dev_err(codec->dev, "Unsupported Width %d\n",
> + params_width(params));
> + }
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_DEPTH_CTL, CS35L35_AUDIN_DEPTH_MASK,
> + audin_format << CS35L35_AUDIN_DEPTH_SHIFT);
> + if (cs35l35->pdata.stereo) {
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_DEPTH_CTL, CS35L35_ADVIN_DEPTH_MASK,
> + audin_format << CS35L35_ADVIN_DEPTH_SHIFT);
> + }
> + }
> +/* We have to take the SCLK to derive num sclks
> + * to configure the CLOCK_CTL3 register correctly
> + */
> + if ((cs35l35->sclk / srate) % 4) {
> + dev_err(codec->dev, "Unsupported sclk/fs ratio %d:%d\n",
> + cs35l35->sclk, srate);
> + return -EINVAL;
> + }
Again here it might be slightly better to constraints in startup.
> + sp_sclks = ((cs35l35->sclk / srate) / 4) - 1;
> +
> + if (cs35l35->i2s_mode) {
> + /* Only certain ratios are supported in I2S Slave Mode */
> + if (cs35l35->slave_mode) {
> + switch (sp_sclks) {
> + case CS35L35_SP_SCLKS_32FS:
> + case CS35L35_SP_SCLKS_48FS:
> + case CS35L35_SP_SCLKS_64FS:
> + break;
> + default:
> + dev_err(codec->dev, "ratio not supported\n");
> + return -EINVAL;
> + };
> + } else {
> + /* Only certain ratios supported in I2S MASTER Mode */
> + switch (sp_sclks) {
> + case CS35L35_SP_SCLKS_32FS:
> + case CS35L35_SP_SCLKS_64FS:
> + break;
> + default:
> + dev_err(codec->dev, "ratio not supported\n");
> + return -EINVAL;
> + };
> + }
> + ret = regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLK_CTL3, CS35L35_SP_SCLKS_MASK,
> + sp_sclks << CS35L35_SP_SCLKS_SHIFT);
> + if (ret != 0) {
> + dev_err(codec->dev, "Failed to set fsclk %d\n", ret);
> + return ret;
> + }
> + }
> + if (cs35l35->pdm_mode) {
> + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> + CS35L35_PDM_MODE_MASK, 1 << CS35L35_PDM_MODE_SHIFT);
> + } else {
> + regmap_update_bits(cs35l35->regmap, CS35L35_AMP_INP_DRV_CTL,
> + CS35L35_PDM_MODE_MASK, 0 << CS35L35_PDM_MODE_SHIFT);
> + }
This if could be combined with the one above since pdm_mode ==
!i2s_mode.
> + return ret;
> +}
> +
> +
> +static const struct snd_soc_dai_ops cs35l35_ops = {
> + .startup = cs35l35_pcm_startup,
> + .set_fmt = cs35l35_set_dai_fmt,
> + .hw_params = cs35l35_pcm_hw_params,
> + .set_sysclk = cs35l35_dai_set_sysclk,
> +};
> +
> +static const struct snd_soc_dai_ops cs35l35_pdm_ops = {
> + .startup = cs35l35_pdm_startup,
> + .set_fmt = cs35l35_set_dai_fmt,
> + .hw_params = cs35l35_pcm_hw_params,
I would be tempted to rename the function to just
cs35l35_hw_params if it is shared between both PCM and PDM.
> + .set_sysclk = cs35l35_dai_set_sysclk,
> +};
> +
> +
> +static int cs35l35_codec_probe(struct snd_soc_codec *codec)
> +{
> + struct cs35l35_private *cs35l35 = snd_soc_codec_get_drvdata(codec);
> + struct classh_cfg *classh = &cs35l35->pdata.classh_algo;
> + struct monitor_cfg *monitor_config = &cs35l35->pdata.mon_cfg;
> + int ret;
> +
> + cs35l35->codec = codec;
> +
> + /* Set Platform Data */
> + if (cs35l35->pdata.bst_vctl)
> + regmap_update_bits(cs35l35->regmap, CS35L35_BST_CVTR_V_CTL,
> + CS35L35_BST_CTL_MASK, cs35l35->pdata.bst_vctl);
> +
> + if (cs35l35->pdata.bst_ipk)
> + regmap_update_bits(cs35l35->regmap, CS35L35_BST_PEAK_I,
> + CS35L35_BST_IPK_MASK,
> + cs35l35->pdata.bst_ipk << CS35L35_BST_IPK_SHIFT);
I believe zero is a valid value for this field, but not the
default. Are we happy that the user can never set this value?
> +
> + if (cs35l35->pdata.gain_zc)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_GAIN_ZC_MASK,
> + cs35l35->pdata.gain_zc << CS35L35_AMP_GAIN_ZC_SHIFT);
> +
> + if (cs35l35->pdata.aud_channel)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_AUDIN_RXLOC_CTL,
> + CS35L35_AUD_IN_LR_MASK,
> + cs35l35->pdata.aud_channel << CS35L35_AUD_IN_LR_SHIFT);
> +
> + if (cs35l35->pdata.stereo) {
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_ADVIN_RXLOC_CTL, CS35L35_ADV_IN_LR_MASK,
> + cs35l35->pdata.adv_channel << CS35L35_ADV_IN_LR_SHIFT);
> + if (cs35l35->pdata.shared_bst)
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLASS_H_CTL,
> + CS35L35_CH_STEREO_MASK, 1 << CS35L35_CH_STEREO_SHIFT);
> + ret = snd_soc_add_codec_controls(codec, cs35l35_adv_controls,
> + ARRAY_SIZE(cs35l35_adv_controls));
> + if (ret)
> + return ret;
> + }
> +
> + if (cs35l35->pdata.sp_drv_str)
> + regmap_update_bits(cs35l35->regmap, CS35L35_CLK_CTL1,
> + CS35L35_SP_DRV_MASK,
> + cs35l35->pdata.sp_drv_str << CS35L35_SP_DRV_SHIFT);
> +
> + if (classh->classh_algo_enable) {
> + if (classh->classh_bst_override)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_OVR_MASK,
> + classh->classh_bst_override << CS35L35_CH_BST_OVR_SHIFT);
> + if (classh->classh_bst_max_limit)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_BST_LIM_MASK,
> + classh->classh_bst_max_limit << CS35L35_CH_BST_LIM_SHIFT);
This is a single bit, but the default bit is 1, so this code can
never change the value of the field.
> + if (classh->classh_mem_depth)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_CTL, CS35L35_CH_MEM_DEPTH_MASK,
> + classh->classh_mem_depth << CS35L35_CH_MEM_DEPTH_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_headroom)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_HEADRM_CTL, CS35L35_CH_HDRM_CTL_MASK,
> + classh->classh_headroom << CS35L35_CH_HDRM_CTL_SHIFT);
> + if (classh->classh_release_rate)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_RELEASE_RATE, CS35L35_CH_REL_RATE_MASK,
> + classh->classh_release_rate << CS35L35_CH_REL_RATE_SHIFT);
> + if (classh->classh_wk_fet_disable)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DIS_MASK,
> + classh->classh_wk_fet_disable << CS35L35_CH_WKFET_DIS_SHIFT);
> + if (classh->classh_wk_fet_delay)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_DEL_MASK,
> + classh->classh_wk_fet_delay << CS35L35_CH_WKFET_DEL_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_wk_fet_thld)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_FET_DRIVE_CTL, CS35L35_CH_WKFET_THLD_MASK,
> + classh->classh_wk_fet_thld << CS35L35_CH_WKFET_THLD_SHIFT);
> + if (classh->classh_vpch_auto)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_AUTO_MASK,
> + classh->classh_vpch_auto << CS35L35_CH_VP_AUTO_SHIFT);
Again single bit with a default of 1.
> + if (classh->classh_vpch_rate)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_RATE_MASK,
> + classh->classh_vpch_rate << CS35L35_CH_VP_RATE_SHIFT);
Again zero is a valid value, and not the default.
> + if (classh->classh_vpch_man)
> + regmap_update_bits(cs35l35->regmap,
> + CS35L35_CLASS_H_VP_CTL, CS35L35_CH_VP_MAN_MASK,
> + classh->classh_vpch_man << CS35L35_CH_VP_MAN_SHIFT);
> + }
> +
<snip>
> +static int cs35l35_i2c_probe(struct i2c_client *i2c_client,
> + const struct i2c_device_id *id)
> +{
> + struct cs35l35_private *cs35l35;
> + struct cs35l35_platform_data *pdata =
> + dev_get_platdata(&i2c_client->dev);
> + int i;
> + int ret;
> + unsigned int devid = 0;
> + unsigned int reg;
> +
> + cs35l35 = devm_kzalloc(&i2c_client->dev,
> + sizeof(struct cs35l35_private),
> + GFP_KERNEL);
> + if (!cs35l35) {
> + dev_err(&i2c_client->dev, "could not allocate codec\n");
> + return -ENOMEM;
> + }
> +
> + i2c_set_clientdata(i2c_client, cs35l35);
> + cs35l35->regmap = devm_regmap_init_i2c(i2c_client, &cs35l35_regmap);
> + if (IS_ERR(cs35l35->regmap)) {
> + ret = PTR_ERR(cs35l35->regmap);
> + dev_err(&i2c_client->dev, "regmap_init() failed: %d\n", ret);
> + goto err;
> + }
> +
> + for (i = 0; i < ARRAY_SIZE(cs35l35_supplies); i++)
> + cs35l35->supplies[i].supply = cs35l35_supplies[i];
> + cs35l35->num_supplies = ARRAY_SIZE(cs35l35_supplies);
> +
> + ret = devm_regulator_bulk_get(&i2c_client->dev,
> + cs35l35->num_supplies,
> + cs35l35->supplies);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev,
> + "Failed to request core supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + if (pdata) {
> + cs35l35->pdata = *pdata;
> + } else {
> + pdata = devm_kzalloc(&i2c_client->dev,
> + sizeof(struct cs35l35_platform_data),
> + GFP_KERNEL);
> + if (!pdata) {
> + dev_err(&i2c_client->dev,
> + "could not allocate pdata\n");
> + return -ENOMEM;
> + }
> + if (i2c_client->dev.of_node) {
> + ret = cs35l35_handle_of_data(i2c_client, pdata);
> + if (ret != 0)
> + return ret;
> +
> + }
> + cs35l35->pdata = *pdata;
> + }
> +
> + ret = regulator_bulk_enable(cs35l35->num_supplies,
> + cs35l35->supplies);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev,
> + "Failed to enable core supplies: %d\n",
> + ret);
> + return ret;
> + }
> +
> + /* returning NULL can be an option if in stereo mode */
> + cs35l35->reset_gpio = devm_gpiod_get_optional(&i2c_client->dev,
> + "reset", GPIOD_OUT_LOW);
> + if (IS_ERR(cs35l35->reset_gpio))
> + return PTR_ERR(cs35l35->reset_gpio);
This should be a goto err;
> +
> + if (cs35l35->reset_gpio)
> + gpiod_set_value_cansleep(cs35l35->reset_gpio, 1);
gpiod_set_value_can_sleep does an internal NULL check on the GPIO
desc I would be tempted to just rely on that one.
> +
> + init_completion(&cs35l35->pdn_done);
> +
> + ret = regmap_register_patch(cs35l35->regmap, cs35l35_errata_patch,
> + ARRAY_SIZE(cs35l35_errata_patch));
> + if (ret < 0) {
> + dev_err(&i2c_client->dev, "Failed to apply errata patch\n");
> + return ret;
This should be a goto err;
> + }
> +
> + ret = devm_request_threaded_irq(&i2c_client->dev, i2c_client->irq, NULL,
> + cs35l35_irq, IRQF_ONESHOT | IRQF_TRIGGER_LOW,
> + "cs35l35", cs35l35);
> + if (ret != 0) {
> + dev_err(&i2c_client->dev, "Failed to request IRQ: %d\n", ret);
> + goto err;
> + }
> + /* initialize codec */
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_AB, ®);
> +
> + devid = (reg & 0xFF) << 12;
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_CD, ®);
> + devid |= (reg & 0xFF) << 4;
> + ret = regmap_read(cs35l35->regmap, CS35L35_DEVID_E, ®);
> + devid |= (reg & 0xF0) >> 4;
> +
> + if (devid != CS35L35_CHIP_ID) {
> + dev_err(&i2c_client->dev,
> + "CS35L35 Device ID (%X). Expected ID %X\n",
> + devid, CS35L35_CHIP_ID);
> + ret = -ENODEV;
> + goto err;
> + }
> +
> + ret = regmap_read(cs35l35->regmap, CS35L35_REV_ID, ®);
> + if (ret < 0) {
> + dev_err(&i2c_client->dev, "Get Revision ID failed\n");
> + goto err;
> + }
> +
> + dev_info(&i2c_client->dev,
> + "Cirrus Logic CS35L35 (%x), Revision: %02X\n", devid,
> + ret & 0xFF);
> +
> + /* Set the INT Masks for critical errors */
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_1, CS35L35_INT1_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_2, CS35L35_INT2_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_3, CS35L35_INT3_CRIT_MASK);
> + regmap_write(cs35l35->regmap, CS35L35_INT_MASK_4, CS35L35_INT4_CRIT_MASK);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PWR2_PDN_MASK, CS35L35_PWR2_PDN_MASK);
> +
> + if (cs35l35->pdata.bst_pdn_fet_on)
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 1 << CS35L35_PDN_BST_FETON_SHIFT);
> + else
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL2,
> + CS35L35_PDN_BST_MASK, 1 << CS35L35_PDN_BST_FETOFF_SHIFT);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PWRCTL3,
> + CS35L35_PWR3_PDN_MASK, CS35L35_PWR3_PDN_MASK);
> +
> + regmap_update_bits(cs35l35->regmap, CS35L35_PROTECT_CTL,
> + CS35L35_AMP_MUTE_MASK, 1 << CS35L35_AMP_MUTE_SHIFT);
> +
> + ret = snd_soc_register_codec(&i2c_client->dev,
> + &soc_codec_dev_cs35l35, cs35l35_dai,
> + ARRAY_SIZE(cs35l35_dai));
> + if (ret < 0) {
> + dev_err(&i2c_client->dev,
> + "%s: Register codec failed\n", __func__);
> + goto err;
> + }
> +
> +err:
> + regulator_bulk_disable(cs35l35->num_supplies,
> + cs35l35->supplies);
> + return ret;
> +}
> +
> +static int cs35l35_i2c_remove(struct i2c_client *client)
> +{
> + snd_soc_unregister_codec(&client->dev);
> + kfree(i2c_get_clientdata(client));
clientdata was allocated with devm this kfree will cause a double
free.
> + return 0;
> +}
Thanks,
Charles
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH 3/3] arm64: dts: rockchip: add clk-480m for ehci and ohci of rk3399
From: Xing Zheng @ 2016-12-21 10:44 UTC (permalink / raw)
To: Doug Anderson
Cc: Heiko Stuebner, Frank Wang, Brian Norris, William wu, Rob Herring,
Mark Rutland, Catalin Marinas, Will Deacon, Caesar Wang,
Jianqun Xu, Elaine Zhang,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Dmitry Torokhov, Tao Huang, open list:ARM/Rockchip SoC...
In-Reply-To: <CAD=FV=W1BW6FSZ6MSxR6RhvtZyGsdQbz9vU_QshaQ5A65ENMCg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
Hi Heiko, Doug
在 2016年12月17日 01:28, Doug Anderson 写道:
> Hi,
>
> On Thu, Dec 15, 2016 at 10:57 PM, Xing Zheng <zhengxing-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Hi Heiko, Doug,
>>
>> On 2016年12月16日 02:18, Heiko Stuebner wrote:
>>
>> Am Donnerstag, 15. Dezember 2016, 08:34:09 CET schrieb Doug Anderson:
>>
>>
>> I still need to digest all of the things that were added to this
>> thread overnight, but nothing I've seen so far indicates that you need
>> the post-gated clock. AKA I still think you need to redo your patch
>> to replace:
>>
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&cru SCLK_USBPHY0_480M_SRC>;
>>
>> with:
>>
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&u2phy0>;
>>
>> Can you please comment on that?
>>
>> Also, with the change, the ehci will keep the clock (and thus the phy)
>> always
>> on. Does the phy-autosuspend even save anything now?
>>
>> In any case, could we make the clock-names entry sound nicer than
>> usbphy0_480m
>> please? bindings/usb/atmel-usb.txt calls its UTMI clock simply "usb_clk",
>> but
>> something like "utmi" should also work.
>> While at it you could also fix up the other clock names to something like
>> "host" and "arbiter" or so?.
>>
>>
>> Heiko
>>
>>
>> The usbphy related clock tress like this:
>>
>>
>> Actually, at drivers/phy/phy-rockchip-inno-usb2.c, we can only
>> enable/disable the master gate via GRF is PHY_PLL, not UTMI_CLK.
>>
>> And the naming style of the "hclk_host0" keep the name "hclk_host0" on the
>> clcok tree diagram:
>>
>>
>> Therefore, could we rename the clock name like this:
>> ----
>> for usb_host0_ehci and usb_host0_ohci:
>> clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
>> <&cru SCLK_U2PHY0>;
>> clock-names = "hclk_host0", "hclk_host0_arb",
>> "sclk_u2phy0";
>>
>> for usb_host1_ehci and usb_host1_ohci:
>> clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
>> <&cru SCLK_U2PHY1>;
>> clock-names = "hclk_host1", "hclk_host1_arb",
>> "sclk_u2phy1";
>> ----
>>
>> BTW, the "arb" is an abbreviation for arbiter.
> You don't specify what this new "SCLK_U2PHY0" ID is, so it's a little
> hard for me to know what you're intending.
>
> ...however, I still don't see any reason why you can't just use the
> solution I proposed. Specifying the clock as "<&u2phy0>" is the
> correct thing to do. The input clock to the EHCI driver is exactly
> the clock provided by the USB PHY with no gate in between (just as I
> said). There is no reason to somehow buffer it by the cru. The cru
> doesn't see this clock and has no reason to be involved.
>
> Note that there were many other comments on this thread besides mine.
> Are you planning to address any of them?
>
> -Doug
>
>
Done, and have resent the patch.
Thanks.
--
- Xing Zheng
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox