* Re: [PATCH v4 0/5] mfd: dt: Add bindings for the Aspeed MFDs
From: Corey Minyard @ 2016-12-22 21:47 UTC (permalink / raw)
To: Andrew Jeffery, Lee Jones
Cc: Rob Herring, Mark Rutland, Linus Walleij, Cédric Le Goater,
Joel Stanley, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220071535.27542-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
It looks like this is ready. Should I take this in the IPMI tree, or is
there a better tree for it?
-corey
On 12/20/2016 01:15 AM, Andrew Jeffery wrote:
> Hi Lee,
>
> Here's v4 of the Aspeed LPC MFD devicetree bindings series. v3 can be found at:
>
> https://lkml.org/lkml/2016/12/5/835
>
> Changes since v3:
>
> * Based on Arnd's argument[1], drop the addition of the mfd/syscon bindings
> directory as well as the the last patch in v3, which moved a number of
> existing bindings. Eventually the Aspeed display controller will have a
> device-specific driver so it doesn't belong there either.
>
> * Add a compatible string for the AST2400 in the LPC Host Controller bindings
> as requested by Joel and slightly tweak the reg description for Rob.
>
> [1] https://lkml.org/lkml/2016/12/13/202
>
> Andrew Jeffery (5):
> mfd: dt: Fix "indicates" typo in mfd bindings document
> mfd: dt: ranges, #address-cells and #size-cells as optional properties
> mfd: dt: Add Aspeed Low Pin Count Controller bindings
> mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
> mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
>
> .../devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 137 +++++++++++++++++++++
> Documentation/devicetree/bindings/mfd/mfd.txt | 12 +-
> 3 files changed, 165 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
>
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* Re: Fwd: [PATCH 1/1] of/fdt: failed to mark hotplug range message
From: Frank Rowand @ 2016-12-22 21:31 UTC (permalink / raw)
To: Heinrich Schuchardt, Reza Arbab, Balbir Singh, Andrew Morton
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <5251e7ef-cadf-7833-9a7e-66ebf78e2e94-Mmb7MZpHnFY@public.gmane.org>
And the patch to be fixed was merged via akpm, so adding him.
Fixes: 41a9ada3e6b4 ("of/fdt: mark hotpluggable memory")
-Frank
On 12/21/16 21:52, Heinrich Schuchardt wrote:
> scripts/get_maintainers.pl did not show the people involved in creating
> the code to be changed.
>
> On 12/22/2016 06:34 AM, Heinrich Schuchardt wrote:
>> If marking a hotplug range fails a message
>> "failed to mark hotplug range" is written.
>>
>> The end address is base + size - 1.
>>
>> Signed-off-by: Heinrich Schuchardt <xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
>> ---
>> drivers/of/fdt.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
>> index c9b5cac03b36..fd129b6e5396 100644
>> --- a/drivers/of/fdt.c
>> +++ b/drivers/of/fdt.c
>> @@ -1057,7 +1057,7 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname,
>>
>> if (early_init_dt_mark_hotplug_memory_arch(base, size))
>> pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n",
>> - base, base + size);
>> + base, base + size - 1);
>> }
>>
>> return 0;
>>
>
>
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* Re: [PATCH net-next 01/10] net: netcp: ethss: add support of subsystem register region regmap
From: Rob Herring @ 2016-12-22 21:24 UTC (permalink / raw)
To: Murali Karicheri
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, linux-omap-u79uwXL29TY76Z2rM5mHXA,
grygorii.strashko-l0cyMroinI0, mugunthanvnm-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, devicetree-u79uwXL29TY76Z2rM5mHXA,
mark.rutland-5wv7dgnIgG8
In-Reply-To: <1482271793-7671-2-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
On Tue, Dec 20, 2016 at 05:09:44PM -0500, Murali Karicheri wrote:
> From: WingMan Kwok <w-kwok2-l0cyMroinI0@public.gmane.org>
>
> 10gbe phy driver needs to access the 10gbe subsystem control
> register during phy initialization. To facilitate the shared
> access of the subsystem register region between the 10gbe Ethernet
> driver and the phy driver, this patch adds support of the
> subsystem register region defined by a syscon node in the dts.
>
> Although there is no shared access to the gbe subsystem register
> region, using syscon for that is for the sake of consistency.
>
> This change is backward compatible with previously released gbe
> devicetree bindings.
>
> Signed-off-by: WingMan Kwok <w-kwok2-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
> ---
> .../devicetree/bindings/net/keystone-netcp.txt | 16 ++-
> drivers/net/ethernet/ti/netcp_ethss.c | 140 +++++++++++++++++----
> 2 files changed, 127 insertions(+), 29 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/keystone-netcp.txt b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> index 04ba1dc..0854a73 100644
> --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt
> +++ b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> @@ -72,20 +72,24 @@ Required properties:
> "ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2)
> "ti,netcp-xgbe" for 10 GbE
>
> +- syscon-subsys: phandle to syscon node of the switch
> + subsystem registers.
> +
> - reg: register location and the size for the following register
> regions in the specified order.
> - switch subsystem registers
> + - sgmii module registers
This needs to go on the end of the list. Otherwise, it is not backwards
compatible.
> - sgmii port3/4 module registers (only for NetCP 1.4)
> - switch module registers
> - serdes registers (only for 10G)
>
> NetCP 1.4 ethss, here is the order
> - index #0 - switch subsystem registers
> + index #0 - sgmii module registers
> index #1 - sgmii port3/4 module registers
> index #2 - switch module registers
>
> NetCP 1.5 ethss 9 port, 5 port and 2 port
> - index #0 - switch subsystem registers
> + index #0 - sgmii module registers
> index #1 - switch module registers
> index #2 - serdes registers
>
> @@ -145,6 +149,11 @@ Optional properties:
>
> Example binding:
>
> +gbe_subsys: subsys@2090000 {
> + compatible = "syscon";
> + reg = <0x02090000 0x100>;
> +};
> +
> netcp: netcp@2000000 {
> reg = <0x2620110 0x8>;
> reg-names = "efuse";
> @@ -163,7 +172,8 @@ netcp: netcp@2000000 {
> ranges;
> gbe@90000 {
> label = "netcp-gbe";
> - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
> + syscon-subsys = <&gbe_subsys>;
> + reg = <0x90100 0x200>, <0x90400 0x200>, <0x90800 0x700>;
> /* enable-ale; */
> tx-queue = <648>;
> tx-channel = <8>;
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* Re: [PATCH] devicetree: bindings: clk: mvebu: fix description for sata1 on Armada XP
From: Rob Herring @ 2016-12-22 21:20 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Michael Turquette, Stephen Boyd, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220212005.26139-1-uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
On Tue, Dec 20, 2016 at 10:20:05PM +0100, Uwe Kleine-König wrote:
> SATA Host 0 clock is (as correctly documented) id 15/sata0.
>
> Signed-off-by: Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
> ---
> Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Rob
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> index cb8542d910b3..5142efc8099d 100644
> --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> @@ -117,7 +117,7 @@ ID Clock Peripheral
> 25 tdm Time Division Mplx
> 28 xor1 XOR DMA 1
> 29 sata1lnk
> -30 sata1 SATA Host 0
> +30 sata1 SATA Host 1
>
> The following is a list of provided IDs for Dove:
> ID Clock Peripheral
> --
> 2.10.2
>
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* Re: [PATCH 1/3] doc: DT: Add ti,da830-uart to serial/8250 bindings
From: Rob Herring @ 2016-12-22 21:18 UTC (permalink / raw)
To: David Lechner
Cc: Greg Kroah-Hartman, Mark Rutland, Sekhar Nori, Kevin Hilman,
Axel Haslam, Alexandre Bailon, Bartosz Golaszewski, Jiri Slaby,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1482265384-715-2-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
On Tue, Dec 20, 2016 at 02:23:02PM -0600, David Lechner wrote:
> This adds the ti,da830-uart compatible string to serial 8250 UART bindings.
>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
> Documentation/devicetree/bindings/serial/8250.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v2 pci/next] PCI: rcar: Add compatible string for r8a7796
From: Rob Herring @ 2016-12-22 21:18 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-pci, Bjorn Helgaas, Simon Horman, Magnus Damm,
Geert Uytterhoeven, linux-renesas-soc, devicetree
In-Reply-To: <1482259026-7180-1-git-send-email-ykaneko0929@gmail.com>
On Wed, Dec 21, 2016 at 03:37:06AM +0900, Yoshihiro Kaneko wrote:
> From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
>
> This patch adds support for r8a7796.
>
> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>
> This patch is based on the next branch of the pci tree.
>
> v2 [Yoshihiro Kaneko]
> * As suggested by Geert Uytterhoeven
> Dropped the update of the driver.
>
> Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 6/7] NFC: trf7970a: Enable pins are active high not active low
From: Rob Herring @ 2016-12-22 21:17 UTC (permalink / raw)
To: Mark Greer
Cc: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-nfc-hn68Rpc1hR1g9hUCZPvPmw
In-Reply-To: <20161220183244.5171-7-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
On Tue, Dec 20, 2016 at 11:32:43AM -0700, Mark Greer wrote:
> The example DTS code for the trf7970a sets the GPIOs for the EN
> and EN2 pins to active low when they are really active high so
> correct the error.
>
> Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
> ---
> Documentation/devicetree/bindings/net/nfc/trf7970a.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy
From: Rob Herring @ 2016-12-22 21:16 UTC (permalink / raw)
To: Vivek Gautam
Cc: kishon-l0cyMroinI0, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1482253431-23160-2-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Tue, Dec 20, 2016 at 10:33:48PM +0530, Vivek Gautam wrote:
> Qualcomm chipsets have QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller.
> Adding dt binding information for the same.
>
> Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>
> Changes since v2:
> - Removed binding for "ref_clk_src" since we don't request this
> clock in the driver.
> - Addressed s/vdda-phy-dpdm/vdda-phy-dpdm-supply.
> - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
> - Addressed s/tune2_hstx_trim_efuse/tune2_hstx_trim. Don't need to add
> 'efuse' suffix to nvmem cell.
> - Addressed s/qusb2phy/phy for the node name.
>
> Changes since v1:
> - New patch, forked out of the original driver patch:
> "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips"
> - Updated dt bindings to remove 'hstx-trim-bit-offset' and
> 'hstx-trim-bit-len' bindings.
>
> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 53 ++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> new file mode 100644
> index 000000000000..594f2dcd12dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> @@ -0,0 +1,53 @@
> +Qualcomm QUSB2 phy controller
> +=============================
> +
> +QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> +
> +Required properties:
> + - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 0.
> +
> + - clocks: a list of phandles and clock-specifier pairs,
> + one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "ref" for 19.2 MHz ref clk,
> + "iface" for phy interface clock (Optional).
> +
> + - vdd-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> + - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
> +
> + - resets: a list of phandles and reset controller specifier pairs,
> + one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block.
-names is pointless when only one.
> +
> +Optional properties:
> + - nvmem-cells: a list of phandles to nvmem cells that contain fused
> + tuning parameters for qusb2 phy, one for each entry
> + in nvmem-cell-names.
> + - nvmem-cell-names: must be "tune2_hstx_trim" for cell containing
> + HS Tx trim value.
ditto.
With those dropped,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers
From: Rob Herring @ 2016-12-22 21:03 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220073551.28522-3-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 20, 2016 at 06:05:48PM +1030, Andrew Jeffery wrote:
> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
>
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> Reviewed-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> ---
>
> Joel: I kept your r-b tag here despite reworking the g5 example bindings, as
> you've given your r-b for the lpc bindings which are what I have added.
>
> .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 80 ++++++++--
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 48 ++++--
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 161 +++++++++++++--------
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++--
> 5 files changed, 242 insertions(+), 97 deletions(-)
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* Re: [PATCH v4 1/5] pinctrl: aspeed: dt: Fix compatibles for the System Control Unit
From: Rob Herring @ 2016-12-22 21:01 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220073551.28522-2-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 20, 2016 at 06:05:47PM +1030, Andrew Jeffery wrote:
> Reference the SoC-specific compatible string in the examples as
> required.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> ---
> Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v4 4/5] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
From: Rob Herring @ 2016-12-22 21:00 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Lee Jones, Mark Rutland, Linus Walleij, Corey Minyard,
Cédric Le Goater, Joel Stanley, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20161220071535.27542-5-andrew@aj.id.au>
On Tue, Dec 20, 2016 at 05:45:34PM +1030, Andrew Jeffery wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> on bits in both the System Control Unit and the LPC Host Controller.
>
> The Aspeed LPC Host Controller is described as a child node of the
> LPC host-range syscon device for arbitration of access by the host
> controller and pinmux drivers.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>
> Linus: I've retained your r-b tag I don't think the addition of the ast2400
> compatible string will fuss you. Please let me know if you feel this is
> inappropriate.
>
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 26 ++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 01/21] MIPS memblock: Unpin dts memblock sanity check method
From: Rob Herring @ 2016-12-22 20:57 UTC (permalink / raw)
To: Serge Semin
Cc: Ralf Baechle, Paul Burton, rabinv-VrBV9hrLPhE,
matt.redfearn-1AXoQHu6uovQT0dZR+AlfA, James Hogan,
Alexander Sverdlin, Frank Rowand,
Sergey.Semin-vHJ8rsvMqnUPfZBKTuL5GA, Linux-MIPS,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1482113266-13207-2-git-send-email-fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, Dec 18, 2016 at 8:07 PM, Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> It's necessary to check whether retrieved from dts memory regions
> fits to page alignment and limits restrictions. Sometimes it is
> necessary to perform the same checks, but ito add the memory regions
s/ito/to/
> into a different subsystem. MIPS is going to be that case.
>
> Signed-off-by: Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/of/fdt.c | 47 +++++++++++++++++++++++---------
> include/linux/of_fdt.h | 1 +
> 2 files changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 1f98156..1ee958f 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -983,44 +983,65 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
> #define MAX_MEMBLOCK_ADDR ((phys_addr_t)~0)
> #endif
>
> -void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
> +int __init sanity_check_dt_memory(phys_addr_t *out_base,
> + phys_addr_t *out_size)
As kbuild robot found, you don't want to use phys_addr_t here.
phys_addr_t varies with kernel config such as LPAE on ARM and the DT
does not.
> {
> + phys_addr_t base = *out_base, size = *out_size;
> const u64 phys_offset = MIN_MEMBLOCK_ADDR;
>
> if (!PAGE_ALIGNED(base)) {
> if (size < PAGE_SIZE - (base & ~PAGE_MASK)) {
> - pr_warn("Ignoring memory block 0x%llx - 0x%llx\n",
> + pr_err("Memblock 0x%llx - 0x%llx isn't page aligned\n",
These are not errors. The page alignment is an OS restriction. h/w
(which the DT describes) generally has little concept of page size
outside the MMUs.
Too many unrelated changes in this patch. Add the error return only
and make anything else a separate patch (though I would just drop
everything else).
I've not looked at the rest of the series, but why can't MIPS migrate
to using memblock directly and using the default DT functions using
memblock?
Rob
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^ permalink raw reply
* Re: [PATCH 2/2] clk: hi3660: Clock driver support for Hisilicon hi3660 SoC
From: Stephen Boyd @ 2016-12-22 20:51 UTC (permalink / raw)
To: zhangfei
Cc: Rob Herring, Arnd Bergmann, haojian.zhuang-QSEj5FYQhm4dnm+yROfE0A,
guodong Xu, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <fc7bebd2-ad03-6479-d6e7-42f5d724216c-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
On 12/22, zhangfei wrote:
> On 2016年12月22日 07:25, Stephen Boyd wrote:
> >On 12/15, Zhangfei Gao wrote:
> >>Signed-off-by: Zhangfei Gao <zhangfei.gao-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> >
> >>+
> >>+ switch (type) {
> >>+ case HI3660_CRGCTRL:
> >>+ hi3660_clk_crgctrl_init(np);
> >>+ break;
> >>+ case HI3660_PCTRL:
> >>+ hi3660_clk_pctrl_init(np);
> >>+ break;
> >>+ case HI3660_PMUCTRL:
> >>+ hi3660_clk_pmuctrl_init(np);
> >>+ break;
> >>+ case HI3660_SCTRL:
> >>+ hi3660_clk_sctrl_init(np);
> >>+ break;
> >>+ case HI3660_IOMCU:
> >>+ hi3660_clk_iomcu_init(np);
> >>+ break;
> >This "multi-device" driver design is sort of odd. Why not have
> >different files and struct drivers for the different devices in
> >the system that are clock controllers? I don't really understand
> >why we're controlling the devices with one struct driver
> >instance. Is something shared between the devices?
> Do you mean put in different .c / drivers?
Yes.
> They have to be put in the same file, since the parent / child
> relate to each other.
We handle clk parent/child relationships through strings. So why
does that mean we need to put these in the same file with the
same struct driver?
> They are for the same chip, but some put in different region for
> privilege control.
Ok.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
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^ permalink raw reply
* Re: [PATCH] gpio: of: Add support for multiple GPIOs in a single GPIO hog
From: Rob Herring @ 2016-12-22 20:36 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Linus Walleij, Alexandre Courbot, Mark Rutland, linux-gpio,
devicetree
In-Reply-To: <1482171694-18237-1-git-send-email-geert@linux-m68k.org>
On Mon, Dec 19, 2016 at 07:21:34PM +0100, Geert Uytterhoeven wrote:
> When listing multiple GPIOs in the "gpios" property of a GPIO hog, only
> the first GPIO is affected. The user is left clueless about the
> disfunctioning of the other GPIOs specified.
>
> Fix this by adding and documenting support for specifying multiple
> GPIOs in a single GPIO hog.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> Documentation/devicetree/bindings/gpio/gpio.txt | 8 +++----
> drivers/gpio/gpiolib-of.c | 31 ++++++++++++++++---------
> 2 files changed, 24 insertions(+), 15 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v10 8/8] dt-bindings: mmc: Add Cavium SOCs MMC bindings
From: Rob Herring @ 2016-12-22 20:32 UTC (permalink / raw)
To: Jan Glauber
Cc: Ulf Hansson, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, David Daney, Steven J . Hill,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161219121552.18316-9-jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
On Mon, Dec 19, 2016 at 01:15:52PM +0100, Jan Glauber wrote:
> Add description of Cavium Octeon and ThunderX SOC device tree bindings.
>
> CC: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>
> Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> ---
> .../devicetree/bindings/mmc/octeon-mmc.txt | 59 ++++++++++++++++++++++
Perhaps cavium-mmc.txt would be more appropriate now.
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/octeon-mmc.txt
>
> diff --git a/Documentation/devicetree/bindings/mmc/octeon-mmc.txt b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> new file mode 100644
> index 0000000..aad02eb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> @@ -0,0 +1,59 @@
> +* Cavium Octeon & ThunderX MMC controller
> +
> +The highspeed MMC host controller on Caviums SoCs provides an interface
> +for MMC and SD types of memory cards.
> +
> +Supported maximum speeds are the ones of the eMMC standard 4.41 as well
> +as the speed of SD standard 4.0. Only 3.3 Volt is supported.
> +
> +Required properties:
> + - compatible : should be one of:
> + * "cavium,octeon-6130-mmc"
> + * "cavium,octeon-6130-mmc-slot"
> + * "cavium,octeon-7890-mmc"
> + * "cavium,octeon-7890-mmc-slot"
> + * "cavium,thunder-8190-mmc"
> + * "cavium,thunder-8190-mmc-slot"
> + * "cavium,thunder-8390-mmc"
> + * "cavium,thunder-8390-mmc-slot"
> + - reg : mmc controller base registers
Following PCI addressing?
> + - clocks : phandle
> +
> +Optional properties:
> + - for cd, bus-width and additional generic mmc parameters
> + please refer to mmc.txt within this directory
> + - "cavium,cmd-clk-skew" : number of coprocessor clocks before sampling command
> + - "cavium,dat-clk-skew" : number of coprocessor clocks before sampling data
> +
> +Deprecated properties:
> +- spi-max-frequency : use max-frequency instead
> +- "cavium,bus-max-width" : use bus-width instead
Drop the quotes.
> +
> +Examples:
> + - Within .dtsi:
Don't show the division between files in the example.
> + mmc_1_4: mmc@1,4 {
> + compatible = "cavium,thunder-8390-mmc";
> + reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
> + #address-cells = <1>;
> + #size-cells = <0>;
> + clocks = <&sclk>;
> + };
> +
> + - Within dts:
> + mmc-slot@0 {
Need to show this is a child node.
> + compatible = "cavium,thunder-8390-mmc-slot";
> + reg = <0>;
> + voltage-ranges = <3300 3300>;
> + max-frequency = <42000000>;
> + bus-width = <4>;
> + cap-sd-highspeed;
> + };
> + mmc-slot@1 {
> + compatible = "cavium,thunder-8390-mmc-slot";
> + reg = <1>;
> + voltage-ranges = <3300 3300>;
> + max-frequency = <42000000>;
> + bus-width = <8>;
> + cap-mmc-highspeed;
> + non-removable;
> + };
> --
> 2.9.0.rc0.21.g7777322
>
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^ permalink raw reply
* [RFC PATCH 4/4] dt-bindings: wp8548: Add on-board NAND flash
From: Zoran Markovic @ 2016-12-22 20:05 UTC (permalink / raw)
To: linux-kernel
Cc: Zoran Markovic, Andy Gross, David Brown, Rob Herring,
Mark Rutland, Russell King, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel
In-Reply-To: <1482437139-29329-1-git-send-email-zmarkovic@sierrawireless.com>
Add description of NAND flash on Sierra Wireless WP8548 module
(and MangOH board).
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
---
arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi | 50 ++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
index 7869898..a4d1158 100644
--- a/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615-wp8548.dtsi
@@ -54,6 +54,56 @@
};
};
+&nand0 {
+ nandcs@0 {
+ compatible = "qcom,nandcs";
+ reg = <0>;
+
+ linux,mtd-name = "micron,mt29f4g08";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ nand-ecc-strength = <4>;
+ nand-ecc-step-size = <512>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ bootloader@0x051c0000 {
+ reg = <0x51c0000 0x100000>;
+ read-only;
+ };
+
+ kernel@0x052c0000 {
+ reg = <0x52c0000 0x1400000>;
+ read-only;
+ };
+
+ rootfs@0x066c0000 {
+ reg = <0x66c0000 0x3140000>;
+ read-only;
+ };
+
+ user0@0x09800000 {
+ reg = <0x9800000 0x2780000>;
+ };
+
+ user1@0x0bf80000 {
+ reg = <0xbf80000 0x8B80000>;
+ };
+
+ user2@0x14b00000 {
+ reg = <0x14b00000 0x500000>;
+ };
+
+ user3@0x15000000 {
+ reg = <0x15000000 0x200000>;
+ };
+ };
+ };
+};
+
&msmgpio {
pinctrl-0 = <&reset_out_pins>;
pinctrl-names = "default";
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 3/4] dt-bindings: mdm9615: Add NAND controller
From: Zoran Markovic @ 2016-12-22 20:05 UTC (permalink / raw)
To: linux-kernel
Cc: Zoran Markovic, Andy Gross, David Brown, Rob Herring,
Mark Rutland, Russell King, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel
In-Reply-To: <1482437139-29329-1-git-send-email-zmarkovic@sierrawireless.com>
Add dt description of NAND controller on MDM9615.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
---
arch/arm/boot/dts/qcom-mdm9615.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index fbc7d68..6d42ff3 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -373,6 +373,22 @@
qcom,ee = <0>;
};
+ nand0: nand@1b400000 {
+ compatible = "qcom,ipq806x-nand";
+ reg = <0x1b400000 0x800>;
+ clocks = <&gcc EBI2_CLK>,
+ <&gcc EBI2_AON_CLK>;
+ clock-names = "core", "aon";
+
+ dmas = <&adm_dma 3>;
+ dma-names = "rxtx";
+ qcom,cmd-crci = <15>;
+ qcom,data-crci = <3>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
amba {
compatible = "arm,amba-bus";
#address-cells = <1>;
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 2/4] clk: mdm9615: Add EBI2 clock
From: Zoran Markovic @ 2016-12-22 20:05 UTC (permalink / raw)
To: linux-kernel
Cc: Zoran Markovic, Andy Gross, David Brown, Michael Turquette,
Stephen Boyd, Rob Herring, Mark Rutland, Neil Armstrong,
linux-arm-msm, linux-soc, linux-clk, devicetree
In-Reply-To: <1482437139-29329-1-git-send-email-zmarkovic@sierrawireless.com>
Add definition of EBI2 clock used by MDM9615 NAND controller.
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
---
drivers/clk/qcom/gcc-mdm9615.c | 30 ++++++++++++++++++++++++++
include/dt-bindings/clock/qcom,gcc-mdm9615.h | 3 +++
2 files changed, 33 insertions(+)
diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
index 581a17f..e9e98b1 100644
--- a/drivers/clk/qcom/gcc-mdm9615.c
+++ b/drivers/clk/qcom/gcc-mdm9615.c
@@ -1563,6 +1563,34 @@ enum {
},
};
+static struct clk_branch ebi2_clk = {
+ .hwcg_reg = 0x2664,
+ .hwcg_bit = 6,
+ .halt_reg = 0x2fcc,
+ .halt_bit = 23,
+ .clkr = {
+ .enable_reg = 0x2664,
+ .enable_mask = BIT(6)|BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_clk",
+ .ops = &clk_branch_ops,
+ },
+ },
+};
+
+static struct clk_branch ebi2_aon_clk = {
+ .halt_reg = 0x2fcc,
+ .halt_bit = 23,
+ .clkr = {
+ .enable_reg = 0x2664,
+ .enable_mask = BIT(8),
+ .hw.init = &(struct clk_init_data){
+ .name = "ebi2_always_on_clk",
+ .ops = &clk_branch_ops,
+ },
+ },
+};
+
static struct clk_hw *gcc_mdm9615_hws[] = {
&cxo.hw,
};
@@ -1637,6 +1665,8 @@ enum {
[PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
[PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
[RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
+ [EBI2_CLK] = &ebi2_clk.clkr,
+ [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
};
static const struct qcom_reset_map gcc_mdm9615_resets[] = {
diff --git a/include/dt-bindings/clock/qcom,gcc-mdm9615.h b/include/dt-bindings/clock/qcom,gcc-mdm9615.h
index 9ab2c40..57cdca6 100644
--- a/include/dt-bindings/clock/qcom,gcc-mdm9615.h
+++ b/include/dt-bindings/clock/qcom,gcc-mdm9615.h
@@ -323,5 +323,8 @@
#define CE3_H_CLK 305
#define USB_HS1_SYSTEM_CLK_SRC 306
#define USB_HS1_SYSTEM_CLK 307
+#define EBI2_CLK 309
+#define EBI2_AON_CLK 310
+
#endif
--
1.7.9.5
^ permalink raw reply related
* [RFC PATCH 1/4] dt-bindings: mdm9615: Add ADM DMA engine
From: Zoran Markovic @ 2016-12-22 20:05 UTC (permalink / raw)
To: linux-kernel
Cc: Zoran Markovic, Andy Gross, David Brown, Rob Herring,
Mark Rutland, Russell King, linux-arm-msm, linux-soc, devicetree,
linux-arm-kernel
In-Reply-To: <1482437139-29329-1-git-send-email-zmarkovic@sierrawireless.com>
Add configuration for ADM DMA engine on MDM9615, used by the EBI2
NAND controller. This commit requires the ADM DMA patches from
Andy Gross:
https://lkml.org/lkml/2015/3/17/19
Cc: Andy Gross <andy.gross@linaro.org>
Cc: David Brown <david.brown@linaro.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
---
arch/arm/boot/dts/qcom-mdm9615.dtsi | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi
index 5ae4ec5..fbc7d68 100644
--- a/arch/arm/boot/dts/qcom-mdm9615.dtsi
+++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi
@@ -336,7 +336,24 @@
};
};
- sdcc1bam: dma@12182000{
+ adm_dma: dma@18300000 {
+ compatible = "qcom,adm";
+ reg = <0x18300000 0x100000>;
+ interrupts = <0 170 0>;
+ #dma-cells = <1>;
+
+ clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
+ clock-names = "core", "iface";
+
+ resets = <&gcc ADM0_RESET>,
+ <&gcc ADM0_C0_RESET>,
+ <&gcc ADM0_C1_RESET>,
+ <&gcc ADM0_C2_RESET>;
+ reset-names = "clk", "c0", "c1", "c2";
+ qcom,ee = <0>;
+ };
+
+ sdcc1bam:dma@12182000{
compatible = "qcom,bam-v1.3.0";
reg = <0x12182000 0x8000>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
--
1.7.9.5
^ permalink raw reply related
* Re: [PATCH v7 3/5] ARM: dts: stm32: Add I2C1 support for STM32F429 SoC
From: Uwe Kleine-König @ 2016-12-22 19:11 UTC (permalink / raw)
To: M'boumba Cedric Madianga
Cc: wsa, robh+dt, mcoquelin.stm32, alexandre.torgue, linus.walleij,
patrice.chotard, linux, linux-i2c, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <1482413704-17531-4-git-send-email-cedric.madianga@gmail.com>
Hello,
On Thu, Dec 22, 2016 at 02:35:02PM +0100, M'boumba Cedric Madianga wrote:
> @@ -337,6 +350,16 @@
> slew-rate = <2>;
> };
> };
> +
> + i2c1_pins_b: i2c1@0 {
> + pins1 {
> + pinmux = <STM32F429_PB9_FUNC_I2C1_SDA>;
> + drive-open-drain;
> + };
> + pins2 {
> + pinmux = <STM32F429_PB6_FUNC_I2C1_SCL>;
> + };
the second doesn't need the open-drain property? Why?
> + };
> };
Best regards
Uwe
--
Pengutronix e.K. | Uwe Kleine-König |
Industrial Linux Solutions | http://www.pengutronix.de/ |
^ permalink raw reply
* Re: [PATCH v2 6/7] dt-bindings: media: Add Renesas R-Car DRIF binding
From: Geert Uytterhoeven @ 2016-12-22 19:05 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Ramesh Shanmugasundaram, Rob Herring, Mark Rutland,
Mauro Carvalho Chehab, Hans Verkuil, Sakari Ailus,
Antti Palosaari, Chris Paterson, Geert Uytterhoeven,
Linux Media Mailing List, devicetree@vger.kernel.org,
Linux-Renesas
In-Reply-To: <11494368.ZdobxT7gGY@avalon>
Hi Laurent,
On Thu, Dec 22, 2016 at 6:05 PM, Laurent Pinchart
<laurent.pinchart@ideasonboard.com> wrote:
> On Wednesday 21 Dec 2016 08:10:37 Ramesh Shanmugasundaram wrote:
>> Add binding documentation for Renesas R-Car Digital Radio Interface
>> (DRIF) controller.
>>
>> Signed-off-by: Ramesh Shanmugasundaram
>> <ramesh.shanmugasundaram@bp.renesas.com> ---
>> .../devicetree/bindings/media/renesas,drif.txt | 202 ++++++++++++++++++
>> 1 file changed, 202 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/media/renesas,drif.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt
>> b/Documentation/devicetree/bindings/media/renesas,drif.txt new file mode
>> 100644
>> index 0000000..1f3feaf
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
>> +Optional properties of an internal channel when:
>> + - It is the only enabled channel of the bond (or)
>> + - If it acts as primary among enabled bonds
>> +--------------------------------------------------------
>> +- renesas,syncmd : sync mode
>> + 0 (Frame start sync pulse mode. 1-bit width pulse
>> + indicates start of a frame)
>> + 1 (L/R sync or I2S mode) (default)
>> +- renesas,lsb-first : empty property indicates lsb bit is received
>> first.
>> + When not defined msb bit is received first (default)
>> +- renesas,syncac-active: Indicates sync signal polarity, 0/1 for low/high
>> + respectively. The default is 1 (active high)
>> +- renesas,dtdl : delay between sync signal and start of reception.
>> + The possible values are represented in 0.5 clock
>> + cycle units and the range is 0 to 4. The default
>> + value is 2 (i.e.) 1 clock cycle delay.
>> +- renesas,syncdl : delay between end of reception and sync signal
>> edge.
>> + The possible values are represented in 0.5 clock
>> + cycle units and the range is 0 to 4 & 6. The default
>> + value is 0 (i.e.) no delay.
>
> Most of these properties are pretty similar to the video bus properties
> defined at the endpoint level in
> Documentation/devicetree/bindings/media/video-interfaces.txt. I believe it
> would make sense to use OF graph and try to standardize these properties
> similarly.
Note that the last two properties match the those in
Documentation/devicetree/bindings/spi/sh-msiof.txt.
We may want to use one DRIF channel as a plain SPI slave with the
(modified) MSIOF driver in the future.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply
* Re: [PATCH 0/4 v2] of/overlay: sysfs based ABI for dt overlays
From: Frank Rowand @ 2016-12-22 19:00 UTC (permalink / raw)
To: Heinrich Schuchardt, Pantelis Antoniou, Rob Herring, Mark Rutland
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220190455.25115-1-xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
Hi Heinrich,
On 12/20/16 11:04, Heinrich Schuchardt wrote:
> Currently the kernel only supplies an internal API for creating
> and destroying device tree overlays.
>
> For some boards vendor specific kernel modules exist for
> managing device tree overlays but they have not been
> upstreamed or upstreaming stalled.
> https://lkml.org/lkml/2015/6/12/624
> https://lkml.org/lkml/2013/1/7/366
>
> This patch series provides a sysfs based ABI for creation and
> destruction of dt overlays in /sys/firmware/devicetree/overlays.
>
> The following files are provided:
>
> load: This is a write only file.
> A string written to it is interpreted as the path to a
> flattened device tree overlay file. It is used to create
> and apply the contained overlays.
>
> loaded: This is a read only file.
> It provides the count of loaded overlays as a decimal
> number.
>
> unload: This is a write only file.
> If a positive number n is wrtten to this file the n
> most recent overlays are destroyed.
> If a negative number is written to this file all
> overlays are destroyed.
This patch series follows a _somewhat_ similar approach to what
was first proposed two years ago, and does not address the
issues that were brought up at that time. See:
From: Pantelis Antoniou <pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w@public.gmane.org>
Date: Wed, 3 Dec 2014 13:23:28 +0200
Subject: [PATCH] OF: DT-Overlay configfs interface (v3)
But just responding directly to the two year old issues would not
be a productive approach, since there has been a lot of subsequent
discussion on how to load overlays (you point to two of the many
threads above). The latest discussions are based on the concept
of describing the overlay attachment points as connectors.
Please join in pushing the connectors discussion along to make
sure that it meets your needs.
-Frank
>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
>
> version 2:
> change sysfs path to
> /sys/firmware/devicetree/overlays
>
> Fix errors indicated by kbuild robot:
> Add missing inline attribute to of_overlay_count
> in patch 1.
> Add 'select CONFIG_OF_EARLY_FLATTREE' to Kconfig
> in patch 2.
>
> Change unit test cases to check new functions
> of_overlay_count and of_overlay_destroy_last.
>
> Heinrich Schuchardt (4):
> of/overlay: add API function to count and pop last
> of/overlay: sysfs based ABI for dt overlays
> of/overlay: documentation for sysfs ABI
> of/overlay: test count and destroy_last
>
> .../ABI/testing/sysfs-firmware-devicetree-overlays | 24 +++
> Documentation/devicetree/overlay-notes.txt | 7 +-
> drivers/of/Kconfig | 15 ++
> drivers/of/Makefile | 2 +
> drivers/of/base.c | 1 +
> drivers/of/ov_sysfs.c | 223 +++++++++++++++++++++
> drivers/of/overlay.c | 50 +++++
> drivers/of/unittest.c | 15 +-
> include/linux/of.h | 12 ++
> 9 files changed, 346 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/ABI/testing/sysfs-firmware-devicetree-overlays
> create mode 100644 drivers/of/ov_sysfs.c
>
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^ permalink raw reply
* Re: [PATCH 1/3] NFC: trf7970a: add device tree option for 27MHz clock
From: Rob Herring @ 2016-12-22 18:48 UTC (permalink / raw)
To: Geoff Lansberry
Cc: linux-wireless, Lauro Ramos Venancio, Aloisio Almeida Jr,
Samuel Ortiz, Mark Rutland, netdev,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mark Greer,
Justin Bronder
In-Reply-To: <CAO7Z3WKmEbJCN_=srxTVKXvtz84vHGi41RS+9T7fmkmhRB6nEw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Mon, Dec 19, 2016 at 5:23 PM, Geoff Lansberry <geoff-R+k406RtEhcAvxtiuMwx3w@public.gmane.org> wrote:
> I can make that change, however, I worry that it may be a bit
> misleading, since there are only two supported clock frequencies, but
> a number like that to me implies that it could be set to any number
> you want. I'm new at this, and so I'll go ahead and change it as you
> request, but I'd like to hear your thoughts on my concern.
Then the binding doc just needs to state what are the 2 valid frequencies.
Rob
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* Re: [PATCH v3 2/3] USB3/DWC3: Add property "snps, incr-burst-type-adjustment" for INCR burst type
From: Rob Herring @ 2016-12-22 18:45 UTC (permalink / raw)
To: Changming Huang
Cc: balbi, mark.rutland, catalin.marinas, will.deacon, linux,
devicetree, linux-usb, linux-kernel, linux-arm-kernel
In-Reply-To: <1482139554-13618-2-git-send-email-jerry.huang@nxp.com>
On Mon, Dec 19, 2016 at 05:25:53PM +0800, Changming Huang wrote:
> New property "snps,incr-burst-type-adjustment = <x>, <y>" for USB3.0 DWC3.
> Field "x": 1/0 - undefined length INCR burst type enable or not;
> Field "y": INCR4/INCR8/INCR16/INCR32/INCR64/INCR128/INCR256 burst type.
>
> While enabling undefined length INCR burst type and INCR16 burst type,
> get better write performance on NXP Layerscape platform:
> around 3% improvement (from 364MB/s to 375MB/s).
>
> Signed-off-by: Changming Huang <jerry.huang@nxp.com>
> ---
> Changes in v3:
> - add new property for INCR burst in usb node.
>
> Documentation/devicetree/bindings/usb/dwc3.txt | 5 +++++
> arch/arm/boot/dts/ls1021a.dtsi | 1 +
> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 3 +++
> arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 2 ++
> 4 files changed, 11 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt b/Documentation/devicetree/bindings/usb/dwc3.txt
> index e3e6983..8c405a3 100644
> --- a/Documentation/devicetree/bindings/usb/dwc3.txt
> +++ b/Documentation/devicetree/bindings/usb/dwc3.txt
> @@ -55,6 +55,10 @@ Optional properties:
> fladj_30mhz_sdbnd signal is invalid or incorrect.
>
> - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated.
> + - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0
> + register, undefined length INCR burst type enable and INCRx type.
> + First field is for undefined length INCR burst type enable or not.
> + Second field is for largest INCRx type enabled.
Why do you need the first field? Is the 2nd field used if the 1st is 0?
If not, then just use the presence of the property to enable or not.
Rob
^ permalink raw reply
* Re: [PATCH v3 2/2] crypto: mediatek - add DT bindings documentation
From: Rob Herring @ 2016-12-22 18:41 UTC (permalink / raw)
To: Ryder Lee
Cc: Herbert Xu, David S. Miller, Matthias Brugger,
devicetree-u79uwXL29TY76Z2rM5mHXA, Sean Wang,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Roy Luo,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-crypto-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1482114045-18716-3-git-send-email-ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
On Mon, Dec 19, 2016 at 10:20:45AM +0800, Ryder Lee wrote:
> Add DT bindings documentation for the crypto driver
>
> Signed-off-by: Ryder Lee <ryder.lee-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
> ---
> .../devicetree/bindings/crypto/mediatek-crypto.txt | 27 ++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/mediatek-crypto.txt
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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