* Re: [PATCH v8 1/5] Documentation: synopsys-dw-mshc: add binding for fifo quirks
From: Rob Herring @ 2016-12-22 23:04 UTC (permalink / raw)
To: Jun Nie
Cc: mark.rutland, shawn.guo, xie.baoyou, devicetree, ulf.hansson,
jh80.chung, jason.liu, chen.chaokai, lai.binz, linux-mmc
In-Reply-To: <1482382657-16681-2-git-send-email-jun.nie@linaro.org>
On Thu, Dec 22, 2016 at 12:57:33PM +0800, Jun Nie wrote:
> Add fifo-addr property and fifo-watermark-quirk property to
> synopsys-dw-mshc bindings. It is intended to provide more
> dt interface to support SoCs specific configuration.
>
> Signed-off-by: Jun Nie <jun.nie@linaro.org>
> ---
> Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
Add acks when reposting.
Acked-by: Rob Herring <robh@kernel.org>
Rob
^ permalink raw reply
* Re: [PATCH v3 2/3] NFC: trf7970a: Add device tree option of 1.8 Volt IO voltage
From: Rob Herring @ 2016-12-22 23:02 UTC (permalink / raw)
To: Geoff Lansberry
Cc: linux-wireless, lauro.venancio, aloisio.almeida, sameo,
mark.rutland, netdev, devicetree, linux-kernel, mgreer, justin
In-Reply-To: <1482380314-16440-2-git-send-email-geoff@kuvee.com>
On Wed, Dec 21, 2016 at 11:18:33PM -0500, Geoff Lansberry wrote:
> The TRF7970A has configuration options for supporting hardware designs
> with 1.8 Volt or 3.3 Volt IO. This commit adds a device tree option,
> using a fixed regulator binding, for setting the io voltage to match
> the hardware configuration. If no option is supplied it defaults to
> 3.3 volt configuration.
>
> Signed-off-by: Geoff Lansberry <geoff@kuvee.com>
> ---
> .../devicetree/bindings/net/nfc/trf7970a.txt | 2 ++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/nfc/trf7970a.c | 26 +++++++++++++++++++++-
> 2 files changed, 27 insertions(+), 1 deletion(-)
^ permalink raw reply
* Re: [PATCH v3 1/3] NFC: trf7970a: add device tree option for 27MHz clock
From: Rob Herring @ 2016-12-22 23:01 UTC (permalink / raw)
To: Geoff Lansberry
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA,
lauro.venancio-430g2QfJUUCGglJvpFV4uA,
aloisio.almeida-430g2QfJUUCGglJvpFV4uA,
sameo-VuQAYsv1563Yd54FQh9/CA, mark.rutland-5wv7dgnIgG8,
netdev-u79uwXL29TY76Z2rM5mHXA, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
mgreer-luAo+O/VEmrlveNOaEYElw, justin-R+k406RtEhcAvxtiuMwx3w
In-Reply-To: <1482380314-16440-1-git-send-email-geoff-R+k406RtEhcAvxtiuMwx3w@public.gmane.org>
On Wed, Dec 21, 2016 at 11:18:32PM -0500, Geoff Lansberry wrote:
> The TRF7970A has configuration options to support hardware designs
> which use a 27.12MHz clock. This commit adds a device tree option
> 'clock-frequency' to support configuring the this chip for default
> 13.56MHz clock or the optional 27.12MHz clock.
>
> Signed-off-by: Geoff Lansberry <geoff-R+k406RtEhcAvxtiuMwx3w@public.gmane.org>
> ---
> .../devicetree/bindings/net/nfc/trf7970a.txt | 2 +
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/nfc/trf7970a.c | 50 +++++++++++++++++-----
> 2 files changed, 41 insertions(+), 11 deletions(-)
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* Re: Fwd: [PATCH 1/1] of/fdt: failed to mark hotplug range message
From: Heinrich Schuchardt @ 2016-12-22 22:58 UTC (permalink / raw)
To: Reza Arbab
Cc: Balbir Singh, Rob Herring, Frank Rowand, Andrew Morton,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161222214917.7g6ldgkdvrlqsyq3-qNY8G7rN0TWMBe/gKFfDyNwqlRwYtuWJQQ4Iyu8u01E@public.gmane.org>
On 12/22/2016 10:49 PM, Reza Arbab wrote:
> On Thu, Dec 22, 2016 at 06:52:45AM +0100, Heinrich Schuchardt wrote:
>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
>> index c9b5cac03b36..fd129b6e5396 100644
>> --- a/drivers/of/fdt.c
>> +++ b/drivers/of/fdt.c
>> @@ -1057,7 +1057,7 @@ int __init early_init_dt_scan_memory(unsigned
>> long node, const char *uname,
>>
>> if (early_init_dt_mark_hotplug_memory_arch(base, size))
>> pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n",
>> - base, base + size);
>> + base, base + size - 1);
>> }
>>
>> return 0;
>
> Isn't it implied that ranges printed this way are [start, end)?
>
> If not, the entire file should be fixed, not just this occurrence.
>
The output in the file drivers/of/fdt.c is currently inconsistent.
Alternative output formats are
pr_err("Reserved memory not supported, ignoring range %pa - %pa%s\n",
&base, &size, nomap ? " (nomap)" : "");
and
pr_debug("Reserved memory: reserved region for node '%s': base %pa, size
%ld MiB\n", uname, &base, (unsigned long)size / SZ_1M);
(Here we will see size = 0 for values less then 1 MiB.)
I expect intervals to be closed and not half open if not explicitly
indicated otherwise.
So I suggest we change all occurrences of interval output in
drivers/of/fdt.c to
0xfirstbyte - 0xlastbyte
where firstbyte = base and lastbyte = base + size - 1.
Using the %pa format code ensures that the length of the output matches
the bitness of address pointers in the system.
Best regards
Heinrich Schuchardt
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* Re: [PATCH 4/5] arm: mvebu: Add device tree for 98DX3236 SoCs
From: Rob Herring @ 2016-12-22 22:53 UTC (permalink / raw)
To: Chris Packham
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161222041328.3303-5-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
On Thu, Dec 22, 2016 at 05:13:27PM +1300, Chris Packham wrote:
> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
> with integrated CPUs. They are similar to the Armada XP SoCs but have
> different I/O interfaces.
>
> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
> ---
> .../devicetree/bindings/arm/marvell/98dx3236.txt | 10 +
> arch/arm/boot/dts/armada-xp-98dx3236.dtsi | 231 +++++++++++++++++++++
> arch/arm/boot/dts/armada-xp-98dx3336.dtsi | 78 +++++++
> arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 78 +++++++
> 4 files changed, 397 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3236.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx3336.dtsi
> create mode 100644 arch/arm/boot/dts/armada-xp-98dx4251.dtsi
>
> diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> new file mode 100644
> index 000000000000..e7dc9b2dd90b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt
> @@ -0,0 +1,10 @@
> +Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings
> +----------------------------------------------------------------------
> +
> +Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families
> +shall have the following property:
> +
> +Required root node property:
> +
> +compatible: one of "marvell,armadaxp-98dx3236", "marvell,armadaxp-98dx3336"
> + or "marvell,armadaxp-98dx4251"
The 3336 and 4251 are compatible with 3236 according to the dts files.
That needs to be expressed here.
Rob
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^ permalink raw reply
* Re: [PATCH 3/5] pinctrl: mvebu: pinctrl driver for 98DX3236 SoC
From: Rob Herring @ 2016-12-22 22:48 UTC (permalink / raw)
To: Chris Packham
Cc: linux-arm-kernel, Kalyan Kinthada, Linus Walleij, Mark Rutland,
Laxman Dewangan, Thomas Petazzoni, linux-gpio, devicetree,
linux-kernel
In-Reply-To: <20161222041328.3303-4-chris.packham@alliedtelesis.co.nz>
On Thu, Dec 22, 2016 at 05:13:26PM +1300, Chris Packham wrote:
> From: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
>
> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
> from Marvell.
>
> Signed-off-by: Kalyan Kinthada <kalyan.kinthada@alliedtelesis.co.nz>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> .../pinctrl/marvell,armada-98dx3236-pinctrl.txt | 46 +++++++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/pinctrl/mvebu/pinctrl-armada-xp.c | 145 +++++++++++++++++++++
> 2 files changed, 191 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pinctrl/marvell,armada-98dx3236-pinctrl.txt
^ permalink raw reply
* Re: [PATCH 2/5] arm: mvebu: support for SMP on 98DX3336 SoC
From: Rob Herring @ 2016-12-22 22:47 UTC (permalink / raw)
To: Chris Packham
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Mark Rutland,
Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Russell King, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161222041328.3303-3-chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
On Thu, Dec 22, 2016 at 05:13:25PM +1300, Chris Packham wrote:
> Compared to the armada-xp the 98DX3336 uses different registers to set
> the boot address for the secondary CPU so a new enable-method is needed.
> This will only work if the machine definition doesn't define an overall
> smp_ops because there is not currently a way of overriding this from the
> device tree if it is set in the machine definition.
Doesn't look like you documented the enable-method value.
> Signed-off-by: Chris Packham <chris.packham-6g8wRflRTwXFdCa3tKVlE6U/zSkkHjvu@public.gmane.org>
> ---
> .../bindings/arm/marvell/98dx3236-resume-ctrl.txt | 18 ++++++
> arch/arm/mach-mvebu/Makefile | 1 +
> arch/arm/mach-mvebu/common.h | 1 +
> arch/arm/mach-mvebu/platsmp.c | 43 ++++++++++++++
> arch/arm/mach-mvebu/pmsu-98dx3236.c | 69 ++++++++++++++++++++++
> 5 files changed, 132 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/arm/marvell/98dx3236-resume-ctrl.txt
> create mode 100644 arch/arm/mach-mvebu/pmsu-98dx3236.c
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^ permalink raw reply
* Re: [PATCH 1/2] power: supply: bq24735: allow polling even if there is no ac-detect gpio
From: Rob Herring @ 2016-12-22 22:42 UTC (permalink / raw)
To: Peter Rosin
Cc: linux-kernel, Sebastian Reichel, Mark Rutland, linux-pm,
devicetree
In-Reply-To: <1482355793-16190-2-git-send-email-peda@axentia.se>
On Wed, Dec 21, 2016 at 10:29:52PM +0100, Peter Rosin wrote:
> It is possible to verify AC adapter presence via a register read, without
> any physical connection to the ACOK pin on the charger. Allow this.
>
> Signed-off-by: Peter Rosin <peda@axentia.se>
> ---
> Documentation/devicetree/bindings/power/supply/ti,bq24735.txt | 4 ++--
> drivers/power/supply/bq24735-charger.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v4 2/3] Bluetooth: btusb: Add out-of-band wakeup support
From: Rob Herring @ 2016-12-22 22:39 UTC (permalink / raw)
To: Rajat Jain
Cc: Mark Rutland, Marcel Holtmann, Gustavo Padovan, Johan Hedberg,
Amitkumar Karwar, Wei-Ning Huang, Xinming Hu, netdev, devicetree,
linux-bluetooth, Brian Norris, linux-kernel, rajatxjain
In-Reply-To: <1482352432-38302-2-git-send-email-rajatja@google.com>
On Wed, Dec 21, 2016 at 12:33:51PM -0800, Rajat Jain wrote:
> Some onboard BT chips (e.g. Marvell 8997) contain a wakeup pin that
> can be connected to a gpio on the CPU side, and can be used to wakeup
> the host out-of-band. This can be useful in situations where the
> in-band wakeup is not possible or not preferable (e.g. the in-band
> wakeup may require the USB host controller to remain active, and
> hence consuming more system power during system sleep).
>
> The oob gpio interrupt to be used for wakeup on the CPU side, is
> read from the device tree node, (using standard interrupt descriptors).
> A devcie tree binding document is also added for the driver. The
> compatible string is in compliance with
> Documentation/devicetree/bindings/usb/usb-device.txt
>
> Signed-off-by: Rajat Jain <rajatja@google.com>
> Reviewed-by: Brian Norris <briannorris@chromium.org>
> ---
> v4: Move the set_bit(BTUSB_OOB_WAKE_DISABLED,..) call to the beginning of
> btusb_config_oob_wake() - caught by Brian.
> v3: Add Brian's "Reviewed-by"
> v2: * Use interrupt-names ("wakeup") instead of assuming first interrupt.
> * Leave it on device tree to specify IRQ flags (level /edge triggered)
> * Mark the device as non wakeable on exit.
>
> Documentation/devicetree/bindings/net/btusb.txt | 40 ++++++++++++
Acked-by: Rob Herring <robh@kernel.org>
> drivers/bluetooth/btusb.c | 84 +++++++++++++++++++++++++
> 2 files changed, 124 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/net/btusb.txt
^ permalink raw reply
* Re: [PATCH v4 1/2] iio: adc: hx711: Add DT binding for avia,hx711
From: Rob Herring @ 2016-12-22 22:38 UTC (permalink / raw)
To: Andreas Klinger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, pawel.moll-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg,
galak-sgV2jX0FEOL9JmXXK+q4OQ, jic23-DgEjT+Ai2ygdnm+yROfE0A,
knaack.h-Mmb7MZpHnFY, lars-Qo5EllUWu/uELgA04lAiVw,
pmeerw-jW+XmwGofnusTnJN9+BGXg
In-Reply-To: <20161221152442.GA14543@andreas>
On Wed, Dec 21, 2016 at 04:24:42PM +0100, Andreas Klinger wrote:
> Add DT bindings for avia,hx711
> Add vendor avia to vendor list
>
> [PATCH v3 1/2] of this patch was Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Sorry, but i had to add the regulator (avdd-supply) and therefore it
> needs to be acked once again.
This should go after the '---', but otherwise you can keep my ack.
>
> Signed-off-by: Andreas Klinger <ak-n176/SwNRljddJNmlsFzeA@public.gmane.org>
> ---
> .../devicetree/bindings/iio/adc/avia-hx711.txt | 18 ++++++++++++++++++
> Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
> 2 files changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
> new file mode 100644
> index 000000000000..b3629405f568
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.txt
> @@ -0,0 +1,18 @@
> +* AVIA HX711 ADC chip for weight cells
> + Bit-banging driver
> +
> +Required properties:
> + - compatible: Should be "avia,hx711"
> + - sck-gpios: Definition of the GPIO for the clock
> + - dout-gpios: Definition of the GPIO for data-out
> + See Documentation/devicetree/bindings/gpio/gpio.txt
> + - avdd-supply: Definition of the regulator used as analog supply
> +
> +Example:
> +weight@0 {
> + compatible = "avia,hx711";
> + sck-gpios = <&gpio3 10 GPIO_ACTIVE_HIGH>;
> + dout-gpios = <&gpio0 7 GPIO_ACTIVE_HIGH>;
> + avdd-suppy = <&avdd>;
> +};
> +
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
> index 44ddc980b085..4696bb5c2198 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.txt
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
> @@ -32,6 +32,7 @@ atlas Atlas Scientific LLC
> atmel Atmel Corporation
> auo AU Optronics Corporation
> avago Avago Technologies
> +avia avia semiconductor
> avic Shanghai AVIC Optoelectronics Co., Ltd.
> axis Axis Communications AB
> boe BOE Technology Group Co., Ltd.
> --
> 2.1.4
>
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^ permalink raw reply
* Re: [PATCH net-next 02/10] net: netcp: ethss: add support of 10gbe pcsr link status
From: Rob Herring @ 2016-12-22 22:30 UTC (permalink / raw)
To: Murali Karicheri
Cc: netdev, linux-omap, grygorii.strashko, mugunthanvnm, linux-kernel,
arnd, davem, devicetree, mark.rutland
In-Reply-To: <1482271793-7671-3-git-send-email-m-karicheri2@ti.com>
On Tue, Dec 20, 2016 at 05:09:45PM -0500, Murali Karicheri wrote:
> From: WingMan Kwok <w-kwok2@ti.com>
>
> The 10GBASE-R Physical Coding Sublayer (PCS-R) module provides
> functionality of a physical coding sublayer (PCS) on data being
> transferred between a demuxed XGMII and SerDes supporting a 16
> or 32 bit interface. From the driver point of view, whether
> a ethernet link is up or not depends also on the status of the
> block-lock bit of the PCSR. This patch adds the checking of that
> bit in order to determine the link status.
I would think this would be a common thing and the phy driver should
provide the status, rather than trying to give the ethernet driver
direct access to the phy registers. Is the PCSR the serdes phy or
registers in addition to that?
Rob
^ permalink raw reply
* Re: [PATCH 01/21] MIPS memblock: Unpin dts memblock sanity check method
From: Serge Semin @ 2016-12-22 21:57 UTC (permalink / raw)
To: Rob Herring
Cc: Ralf Baechle, Paul Burton, rabinv-VrBV9hrLPhE,
matt.redfearn-1AXoQHu6uovQT0dZR+AlfA, James Hogan,
Alexander Sverdlin, Frank Rowand,
Sergey.Semin-vHJ8rsvMqnUPfZBKTuL5GA, Linux-MIPS,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAL_JsqKNZRXzYKVFWRJraEZMvZ0Oj8CBoVFSAy+EWTi5Uavesw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Thu, Dec 22, 2016 at 02:57:07PM -0600, Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Sun, Dec 18, 2016 at 8:07 PM, Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > It's necessary to check whether retrieved from dts memory regions
> > fits to page alignment and limits restrictions. Sometimes it is
> > necessary to perform the same checks, but ito add the memory regions
>
> s/ito/to/
>
> > into a different subsystem. MIPS is going to be that case.
> >
> > Signed-off-by: Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > ---
> > drivers/of/fdt.c | 47 +++++++++++++++++++++++---------
> > include/linux/of_fdt.h | 1 +
> > 2 files changed, 35 insertions(+), 13 deletions(-)
> >
> > diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> > index 1f98156..1ee958f 100644
> > --- a/drivers/of/fdt.c
> > +++ b/drivers/of/fdt.c
> > @@ -983,44 +983,65 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
> > #define MAX_MEMBLOCK_ADDR ((phys_addr_t)~0)
> > #endif
> >
> > -void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
> > +int __init sanity_check_dt_memory(phys_addr_t *out_base,
> > + phys_addr_t *out_size)
>
> As kbuild robot found, you don't want to use phys_addr_t here.
> phys_addr_t varies with kernel config such as LPAE on ARM and the DT
> does not.
>
Ok, thanks. I'll fix it. I figured it out when got kbuild notification.
> > {
> > + phys_addr_t base = *out_base, size = *out_size;
> > const u64 phys_offset = MIN_MEMBLOCK_ADDR;
> >
> > if (!PAGE_ALIGNED(base)) {
> > if (size < PAGE_SIZE - (base & ~PAGE_MASK)) {
> > - pr_warn("Ignoring memory block 0x%llx - 0x%llx\n",
> > + pr_err("Memblock 0x%llx - 0x%llx isn't page aligned\n",
>
> These are not errors. The page alignment is an OS restriction. h/w
> (which the DT describes) generally has little concept of page size
> outside the MMUs.
>
Ok. Understood. I'll get back the pr_warn() method call.
> Too many unrelated changes in this patch. Add the error return only
> and make anything else a separate patch (though I would just drop
> everything else).
>
There is no much changes actually. I just unpicked the check function
and switched pr_warn's to pr_error's. Since the last thing is going to
be discarded, then it's not necessary to make any separation.
> I've not looked at the rest of the series, but why can't MIPS migrate
> to using memblock directly and using the default DT functions using
> memblock?
>
> Rob
Of course there is a reason. Otherwise I wouldn't do it.
A lot of platforms dependent code use MIPS-specific boot_mem_map
structure. So in order to prevent a lot of code modifications MIPS
architecture code needs to support that structure as reflection of
available memory regions. For this purpose I've modified
add_memory_region() method (see patch 0003), which adds a passed
memory region to memblock and boot_mem_map simultaneously.
So in order to simplify the MIPS architecture code, I unpicked the
parameters check function from the default
early_init_dt_add_memory_arch() method, and used it in my callback
method together with MIPS-specific add_memory_region().
Another approach would be to leave the early_init_dt_add_memory_arch()
alone with no modification, and add some new MIPS-specific function,
which would be called right after, for instance, plat_mem_setup().
But in this way we can come up with some errors, since we can't be
absolutely sure, that dts memory nodes scan is performed only there.
The method early_init_dt_scan() can be called from some other places
like device_tree_init() or some place else. It can be fixed by moving
early_init_dt_scan() invocations from chip-specific code to MIPS-
architecture code. But in this case We would have to make
modification at __dt_setup_arch(), which is widely used at the
soc-specific code.
Another option would be to leave early_init_dt_add_memory_arch() alone,
but to develop MIPS-specific parameters check function, or just leave
my callback method without it. But in the first case I would duplicate
the code and in the second case it would leave a window for errors,
since it's wrong to have unaligned memory regions. It may lead to
problems with further buddy allocator initialization.
So to speak I've chosen the easiest option of ones I came up to. If
you have any better suggestion, I would gladly get rid of this patch.
The lesser code modifications the better.
-Sergey
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^ permalink raw reply
* Re: Fwd: [PATCH 1/1] of/fdt: failed to mark hotplug range message
From: Reza Arbab @ 2016-12-22 21:49 UTC (permalink / raw)
To: Heinrich Schuchardt
Cc: Balbir Singh, Rob Herring, Frank Rowand, Andrew Morton,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <5251e7ef-cadf-7833-9a7e-66ebf78e2e94-Mmb7MZpHnFY@public.gmane.org>
On Thu, Dec 22, 2016 at 06:52:45AM +0100, Heinrich Schuchardt wrote:
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index c9b5cac03b36..fd129b6e5396 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -1057,7 +1057,7 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname,
>
> if (early_init_dt_mark_hotplug_memory_arch(base, size))
> pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n",
> - base, base + size);
> + base, base + size - 1);
> }
>
> return 0;
Isn't it implied that ranges printed this way are [start, end)?
If not, the entire file should be fixed, not just this occurrence.
--
Reza Arbab
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^ permalink raw reply
* Re: [PATCH v4 0/5] mfd: dt: Add bindings for the Aspeed MFDs
From: Corey Minyard @ 2016-12-22 21:47 UTC (permalink / raw)
To: Andrew Jeffery, Lee Jones
Cc: Rob Herring, Mark Rutland, Linus Walleij, Cédric Le Goater,
Joel Stanley, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220071535.27542-1-andrew-zrmu5oMJ5Fs@public.gmane.org>
It looks like this is ready. Should I take this in the IPMI tree, or is
there a better tree for it?
-corey
On 12/20/2016 01:15 AM, Andrew Jeffery wrote:
> Hi Lee,
>
> Here's v4 of the Aspeed LPC MFD devicetree bindings series. v3 can be found at:
>
> https://lkml.org/lkml/2016/12/5/835
>
> Changes since v3:
>
> * Based on Arnd's argument[1], drop the addition of the mfd/syscon bindings
> directory as well as the the last patch in v3, which moved a number of
> existing bindings. Eventually the Aspeed display controller will have a
> device-specific driver so it doesn't belong there either.
>
> * Add a compatible string for the AST2400 in the LPC Host Controller bindings
> as requested by Joel and slightly tweak the reg description for Rob.
>
> [1] https://lkml.org/lkml/2016/12/13/202
>
> Andrew Jeffery (5):
> mfd: dt: Fix "indicates" typo in mfd bindings document
> mfd: dt: ranges, #address-cells and #size-cells as optional properties
> mfd: dt: Add Aspeed Low Pin Count Controller bindings
> mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
> mfd: dt: Add bindings for the Aspeed SoC Display Controller (GFX)
>
> .../devicetree/bindings/mfd/aspeed-gfx.txt | 17 +++
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 137 +++++++++++++++++++++
> Documentation/devicetree/bindings/mfd/mfd.txt | 12 +-
> 3 files changed, 165 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-gfx.txt
> create mode 100644 Documentation/devicetree/bindings/mfd/aspeed-lpc.txt
>
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^ permalink raw reply
* Re: Fwd: [PATCH 1/1] of/fdt: failed to mark hotplug range message
From: Frank Rowand @ 2016-12-22 21:31 UTC (permalink / raw)
To: Heinrich Schuchardt, Reza Arbab, Balbir Singh, Andrew Morton
Cc: Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <5251e7ef-cadf-7833-9a7e-66ebf78e2e94-Mmb7MZpHnFY@public.gmane.org>
And the patch to be fixed was merged via akpm, so adding him.
Fixes: 41a9ada3e6b4 ("of/fdt: mark hotpluggable memory")
-Frank
On 12/21/16 21:52, Heinrich Schuchardt wrote:
> scripts/get_maintainers.pl did not show the people involved in creating
> the code to be changed.
>
> On 12/22/2016 06:34 AM, Heinrich Schuchardt wrote:
>> If marking a hotplug range fails a message
>> "failed to mark hotplug range" is written.
>>
>> The end address is base + size - 1.
>>
>> Signed-off-by: Heinrich Schuchardt <xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
>> ---
>> drivers/of/fdt.c | 2 +-
>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
>> index c9b5cac03b36..fd129b6e5396 100644
>> --- a/drivers/of/fdt.c
>> +++ b/drivers/of/fdt.c
>> @@ -1057,7 +1057,7 @@ int __init early_init_dt_scan_memory(unsigned long node, const char *uname,
>>
>> if (early_init_dt_mark_hotplug_memory_arch(base, size))
>> pr_warn("failed to mark hotplug range 0x%llx - 0x%llx\n",
>> - base, base + size);
>> + base, base + size - 1);
>> }
>>
>> return 0;
>>
>
>
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^ permalink raw reply
* Re: [PATCH net-next 01/10] net: netcp: ethss: add support of subsystem register region regmap
From: Rob Herring @ 2016-12-22 21:24 UTC (permalink / raw)
To: Murali Karicheri
Cc: netdev-u79uwXL29TY76Z2rM5mHXA, linux-omap-u79uwXL29TY76Z2rM5mHXA,
grygorii.strashko-l0cyMroinI0, mugunthanvnm-l0cyMroinI0,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, arnd-r2nGTMty4D4,
davem-fT/PcQaiUtIeIZ0/mPfg9Q, devicetree-u79uwXL29TY76Z2rM5mHXA,
mark.rutland-5wv7dgnIgG8
In-Reply-To: <1482271793-7671-2-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
On Tue, Dec 20, 2016 at 05:09:44PM -0500, Murali Karicheri wrote:
> From: WingMan Kwok <w-kwok2-l0cyMroinI0@public.gmane.org>
>
> 10gbe phy driver needs to access the 10gbe subsystem control
> register during phy initialization. To facilitate the shared
> access of the subsystem register region between the 10gbe Ethernet
> driver and the phy driver, this patch adds support of the
> subsystem register region defined by a syscon node in the dts.
>
> Although there is no shared access to the gbe subsystem register
> region, using syscon for that is for the sake of consistency.
>
> This change is backward compatible with previously released gbe
> devicetree bindings.
>
> Signed-off-by: WingMan Kwok <w-kwok2-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Murali Karicheri <m-karicheri2-l0cyMroinI0@public.gmane.org>
> Signed-off-by: Sekhar Nori <nsekhar-l0cyMroinI0@public.gmane.org>
> ---
> .../devicetree/bindings/net/keystone-netcp.txt | 16 ++-
> drivers/net/ethernet/ti/netcp_ethss.c | 140 +++++++++++++++++----
> 2 files changed, 127 insertions(+), 29 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/net/keystone-netcp.txt b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> index 04ba1dc..0854a73 100644
> --- a/Documentation/devicetree/bindings/net/keystone-netcp.txt
> +++ b/Documentation/devicetree/bindings/net/keystone-netcp.txt
> @@ -72,20 +72,24 @@ Required properties:
> "ti,netcp-gbe-2" for 1GbE N NetCP 1.5 (N=2)
> "ti,netcp-xgbe" for 10 GbE
>
> +- syscon-subsys: phandle to syscon node of the switch
> + subsystem registers.
> +
> - reg: register location and the size for the following register
> regions in the specified order.
> - switch subsystem registers
> + - sgmii module registers
This needs to go on the end of the list. Otherwise, it is not backwards
compatible.
> - sgmii port3/4 module registers (only for NetCP 1.4)
> - switch module registers
> - serdes registers (only for 10G)
>
> NetCP 1.4 ethss, here is the order
> - index #0 - switch subsystem registers
> + index #0 - sgmii module registers
> index #1 - sgmii port3/4 module registers
> index #2 - switch module registers
>
> NetCP 1.5 ethss 9 port, 5 port and 2 port
> - index #0 - switch subsystem registers
> + index #0 - sgmii module registers
> index #1 - switch module registers
> index #2 - serdes registers
>
> @@ -145,6 +149,11 @@ Optional properties:
>
> Example binding:
>
> +gbe_subsys: subsys@2090000 {
> + compatible = "syscon";
> + reg = <0x02090000 0x100>;
> +};
> +
> netcp: netcp@2000000 {
> reg = <0x2620110 0x8>;
> reg-names = "efuse";
> @@ -163,7 +172,8 @@ netcp: netcp@2000000 {
> ranges;
> gbe@90000 {
> label = "netcp-gbe";
> - reg = <0x90000 0x300>, <0x90400 0x400>, <0x90800 0x700>;
> + syscon-subsys = <&gbe_subsys>;
> + reg = <0x90100 0x200>, <0x90400 0x200>, <0x90800 0x700>;
> /* enable-ale; */
> tx-queue = <648>;
> tx-channel = <8>;
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^ permalink raw reply
* Re: [PATCH] devicetree: bindings: clk: mvebu: fix description for sata1 on Armada XP
From: Rob Herring @ 2016-12-22 21:20 UTC (permalink / raw)
To: Uwe Kleine-König
Cc: Jason Cooper, Andrew Lunn, Gregory Clement, Sebastian Hesselbarth,
Michael Turquette, Stephen Boyd, Mark Rutland,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220212005.26139-1-uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
On Tue, Dec 20, 2016 at 10:20:05PM +0100, Uwe Kleine-König wrote:
> SATA Host 0 clock is (as correctly documented) id 15/sata0.
>
> Signed-off-by: Uwe Kleine-König <uwe-rXY34ruvC2xidJT2blvkqNi2O/JbrIOy@public.gmane.org>
> ---
> Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied, thanks.
Rob
>
> diff --git a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> index cb8542d910b3..5142efc8099d 100644
> --- a/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt
> @@ -117,7 +117,7 @@ ID Clock Peripheral
> 25 tdm Time Division Mplx
> 28 xor1 XOR DMA 1
> 29 sata1lnk
> -30 sata1 SATA Host 0
> +30 sata1 SATA Host 1
>
> The following is a list of provided IDs for Dove:
> ID Clock Peripheral
> --
> 2.10.2
>
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^ permalink raw reply
* Re: [PATCH 1/3] doc: DT: Add ti,da830-uart to serial/8250 bindings
From: Rob Herring @ 2016-12-22 21:18 UTC (permalink / raw)
To: David Lechner
Cc: Greg Kroah-Hartman, Mark Rutland, Sekhar Nori, Kevin Hilman,
Axel Haslam, Alexandre Bailon, Bartosz Golaszewski, Jiri Slaby,
linux-serial-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
In-Reply-To: <1482265384-715-2-git-send-email-david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
On Tue, Dec 20, 2016 at 02:23:02PM -0600, David Lechner wrote:
> This adds the ti,da830-uart compatible string to serial 8250 UART bindings.
>
> Signed-off-by: David Lechner <david-nq/r/kbU++upp/zk7JDF2g@public.gmane.org>
> ---
> Documentation/devicetree/bindings/serial/8250.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v2 pci/next] PCI: rcar: Add compatible string for r8a7796
From: Rob Herring @ 2016-12-22 21:18 UTC (permalink / raw)
To: Yoshihiro Kaneko
Cc: linux-pci, Bjorn Helgaas, Simon Horman, Magnus Damm,
Geert Uytterhoeven, linux-renesas-soc, devicetree
In-Reply-To: <1482259026-7180-1-git-send-email-ykaneko0929@gmail.com>
On Wed, Dec 21, 2016 at 03:37:06AM +0900, Yoshihiro Kaneko wrote:
> From: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
>
> This patch adds support for r8a7796.
>
> Signed-off-by: Harunobu Kurokawa <harunobu.kurokawa.dn@renesas.com>
> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>
> This patch is based on the next branch of the pci tree.
>
> v2 [Yoshihiro Kaneko]
> * As suggested by Geert Uytterhoeven
> Dropped the update of the driver.
>
> Documentation/devicetree/bindings/pci/rcar-pci.txt | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH v2 6/7] NFC: trf7970a: Enable pins are active high not active low
From: Rob Herring @ 2016-12-22 21:17 UTC (permalink / raw)
To: Mark Greer
Cc: Samuel Ortiz, Lauro Ramos Venancio, Aloisio Almeida Jr,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-nfc-hn68Rpc1hR1g9hUCZPvPmw
In-Reply-To: <20161220183244.5171-7-mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
On Tue, Dec 20, 2016 at 11:32:43AM -0700, Mark Greer wrote:
> The example DTS code for the trf7970a sets the GPIOs for the EN
> and EN2 pins to active low when they are really active high so
> correct the error.
>
> Signed-off-by: Mark Greer <mgreer-luAo+O/VEmrlveNOaEYElw@public.gmane.org>
> ---
> Documentation/devicetree/bindings/net/nfc/trf7970a.txt | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v3 1/4] dt-bindings: phy: Add support for QUSB2 phy
From: Rob Herring @ 2016-12-22 21:16 UTC (permalink / raw)
To: Vivek Gautam
Cc: kishon-l0cyMroinI0, sboyd-sgV2jX0FEOL9JmXXK+q4OQ,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A,
linux-arm-msm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <1482253431-23160-2-git-send-email-vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
On Tue, Dec 20, 2016 at 10:33:48PM +0530, Vivek Gautam wrote:
> Qualcomm chipsets have QUSB2 phy controller that provides
> HighSpeed functionality for DWC3 controller.
> Adding dt binding information for the same.
>
> Signed-off-by: Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
> ---
>
> Changes since v2:
> - Removed binding for "ref_clk_src" since we don't request this
> clock in the driver.
> - Addressed s/vdda-phy-dpdm/vdda-phy-dpdm-supply.
> - Addressed s/ref_clk/ref. Don't need to add '_clk' suffix to clock names.
> - Addressed s/tune2_hstx_trim_efuse/tune2_hstx_trim. Don't need to add
> 'efuse' suffix to nvmem cell.
> - Addressed s/qusb2phy/phy for the node name.
>
> Changes since v1:
> - New patch, forked out of the original driver patch:
> "phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips"
> - Updated dt bindings to remove 'hstx-trim-bit-offset' and
> 'hstx-trim-bit-len' bindings.
>
> .../devicetree/bindings/phy/qcom-qusb2-phy.txt | 53 ++++++++++++++++++++++
> 1 file changed, 53 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> new file mode 100644
> index 000000000000..594f2dcd12dd
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt
> @@ -0,0 +1,53 @@
> +Qualcomm QUSB2 phy controller
> +=============================
> +
> +QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
> +
> +Required properties:
> + - compatible: compatible list, contains "qcom,msm8996-qusb2-phy".
> + - reg: offset and length of the PHY register set.
> + - #phy-cells: must be 0.
> +
> + - clocks: a list of phandles and clock-specifier pairs,
> + one for each entry in clock-names.
> + - clock-names: must be "cfg_ahb" for phy config clock,
> + "ref" for 19.2 MHz ref clk,
> + "iface" for phy interface clock (Optional).
> +
> + - vdd-phy-supply: Phandle to a regulator supply to PHY core block.
> + - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
> + - vdda-phy-dpdm-supply: Phandle to 3.1V regulator supply to Dp/Dm port signals.
> +
> + - resets: a list of phandles and reset controller specifier pairs,
> + one for each entry in reset-names.
> + - reset-names: must be "phy" for reset of phy block.
-names is pointless when only one.
> +
> +Optional properties:
> + - nvmem-cells: a list of phandles to nvmem cells that contain fused
> + tuning parameters for qusb2 phy, one for each entry
> + in nvmem-cell-names.
> + - nvmem-cell-names: must be "tune2_hstx_trim" for cell containing
> + HS Tx trim value.
ditto.
With those dropped,
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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* Re: [PATCH v4 2/5] pinctrl: aspeed: Read and write bits in LPC and GFX controllers
From: Rob Herring @ 2016-12-22 21:03 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220073551.28522-3-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 20, 2016 at 06:05:48PM +1030, Andrew Jeffery wrote:
> The System Control Unit IP block in the Aspeed SoCs is typically where
> the pinmux configuration is found, but not always. A number of pins
> depend on state in one of LPC Host Control (LHC) or SoC Display
> Controller (GFX) IP blocks, so the Aspeed pinmux drivers should have the
> means to adjust these as necessary.
>
> We use syscon to cast a regmap over the GFX and LPC blocks, which is
> used as an arbitration layer between the relevant driver and the pinctrl
> subsystem. The regmaps are then exposed to the SoC-specific pinctrl
> drivers by phandles in the devicetree, and are selected during a mux
> request by querying a new 'ip' member in struct aspeed_sig_desc.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> Reviewed-by: Joel Stanley <joel-U3u1mxZcP9KHXe+LvDLADg@public.gmane.org>
> ---
>
> Joel: I kept your r-b tag here despite reworking the g5 example bindings, as
> you've given your r-b for the lpc bindings which are what I have added.
>
> .../devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 80 ++++++++--
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 18 +--
> drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 48 ++++--
> drivers/pinctrl/aspeed/pinctrl-aspeed.c | 161 +++++++++++++--------
> drivers/pinctrl/aspeed/pinctrl-aspeed.h | 32 ++--
> 5 files changed, 242 insertions(+), 97 deletions(-)
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^ permalink raw reply
* Re: [PATCH v4 1/5] pinctrl: aspeed: dt: Fix compatibles for the System Control Unit
From: Rob Herring @ 2016-12-22 21:01 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Linus Walleij, Mark Rutland, Lee Jones, Joel Stanley,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161220073551.28522-2-andrew-zrmu5oMJ5Fs@public.gmane.org>
On Tue, Dec 20, 2016 at 06:05:47PM +1030, Andrew Jeffery wrote:
> Reference the SoC-specific compatible string in the examples as
> required.
>
> Signed-off-by: Andrew Jeffery <andrew-zrmu5oMJ5Fs@public.gmane.org>
> ---
> Documentation/devicetree/bindings/pinctrl/pinctrl-aspeed.txt | 11 ++++++++---
> 1 file changed, 8 insertions(+), 3 deletions(-)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
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^ permalink raw reply
* Re: [PATCH v4 4/5] mfd: dt: Add bindings for the Aspeed LPC Host Controller (LHC)
From: Rob Herring @ 2016-12-22 21:00 UTC (permalink / raw)
To: Andrew Jeffery
Cc: Lee Jones, Mark Rutland, Linus Walleij, Corey Minyard,
Cédric Le Goater, Joel Stanley, devicetree, linux-arm-kernel,
linux-kernel
In-Reply-To: <20161220071535.27542-5-andrew@aj.id.au>
On Tue, Dec 20, 2016 at 05:45:34PM +1030, Andrew Jeffery wrote:
> The LPC bus pinmux configuration on fifth generation Aspeed SoCs depends
> on bits in both the System Control Unit and the LPC Host Controller.
>
> The Aspeed LPC Host Controller is described as a child node of the
> LPC host-range syscon device for arbitration of access by the host
> controller and pinmux drivers.
>
> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
> ---
>
> Linus: I've retained your r-b tag I don't think the addition of the ast2400
> compatible string will fuss you. Please let me know if you feel this is
> inappropriate.
>
> .../devicetree/bindings/mfd/aspeed-lpc.txt | 26 ++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply
* Re: [PATCH 01/21] MIPS memblock: Unpin dts memblock sanity check method
From: Rob Herring @ 2016-12-22 20:57 UTC (permalink / raw)
To: Serge Semin
Cc: Ralf Baechle, Paul Burton, rabinv-VrBV9hrLPhE,
matt.redfearn-1AXoQHu6uovQT0dZR+AlfA, James Hogan,
Alexander Sverdlin, Frank Rowand,
Sergey.Semin-vHJ8rsvMqnUPfZBKTuL5GA, Linux-MIPS,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1482113266-13207-2-git-send-email-fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Sun, Dec 18, 2016 at 8:07 PM, Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> It's necessary to check whether retrieved from dts memory regions
> fits to page alignment and limits restrictions. Sometimes it is
> necessary to perform the same checks, but ito add the memory regions
s/ito/to/
> into a different subsystem. MIPS is going to be that case.
>
> Signed-off-by: Serge Semin <fancer.lancer-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> ---
> drivers/of/fdt.c | 47 +++++++++++++++++++++++---------
> include/linux/of_fdt.h | 1 +
> 2 files changed, 35 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/of/fdt.c b/drivers/of/fdt.c
> index 1f98156..1ee958f 100644
> --- a/drivers/of/fdt.c
> +++ b/drivers/of/fdt.c
> @@ -983,44 +983,65 @@ int __init early_init_dt_scan_chosen(unsigned long node, const char *uname,
> #define MAX_MEMBLOCK_ADDR ((phys_addr_t)~0)
> #endif
>
> -void __init __weak early_init_dt_add_memory_arch(u64 base, u64 size)
> +int __init sanity_check_dt_memory(phys_addr_t *out_base,
> + phys_addr_t *out_size)
As kbuild robot found, you don't want to use phys_addr_t here.
phys_addr_t varies with kernel config such as LPAE on ARM and the DT
does not.
> {
> + phys_addr_t base = *out_base, size = *out_size;
> const u64 phys_offset = MIN_MEMBLOCK_ADDR;
>
> if (!PAGE_ALIGNED(base)) {
> if (size < PAGE_SIZE - (base & ~PAGE_MASK)) {
> - pr_warn("Ignoring memory block 0x%llx - 0x%llx\n",
> + pr_err("Memblock 0x%llx - 0x%llx isn't page aligned\n",
These are not errors. The page alignment is an OS restriction. h/w
(which the DT describes) generally has little concept of page size
outside the MMUs.
Too many unrelated changes in this patch. Add the error return only
and make anything else a separate patch (though I would just drop
everything else).
I've not looked at the rest of the series, but why can't MIPS migrate
to using memblock directly and using the default DT functions using
memblock?
Rob
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