* Re: [PATCH v8 0/5] Add intial support to DW MMC host on ZTE SoC
From: Jun Nie @ 2016-12-26 2:24 UTC (permalink / raw)
To: jh80.chung, shawn.guo, xie.baoyou, devicetree
Cc: ulf.hansson, jason.liu, chen.chaokai, lai.binz, linux-mmc,
robh+dt, mark.rutland
In-Reply-To: <1482382657-16681-1-git-send-email-jun.nie@linaro.org>
On 2016年12月22日 12:57, Jun Nie wrote:
> Add intial support to DW MMC host on ZTE SoC. It include platform
> specific wrapper driver and workarounds for fifo quirk.
>
> Changes vs version 7:
> - Re-order patches sequence so that new dts property is introduced before usage.
> - Remove unecessary property in zx mmc dts.
>
> Changes vs version 6:
> - Resolve confilict when rebase to latest dw-mmc.git for-ulf branch.
> - Add Shawn Lin's review tag.
>
> Changes vs version 5:
> - Add clock delay lock status check to save CPU cycle in timing tuning CMD.
>
> Changes vs version 4:
> - Fix missing empty dts compatible element in the end of compatible array.
>
> Changes vs version 3:
> - Fix brace error in document.
>
> Changes vs version 2:
> - Change dt property fifo-addr to data-addr and fifo-watermark-quirk to
> fifo-watermark-aligned.
> - Polish ZX MMC driver on minor coding style issues.
>
> Changes vs version 1:
> - Change fifo-addr-override to fifo-addr and remove its workaround tag in comments.
> - Remove ZX DW MMC driver reset cap in driver, which can be added in dt nodes.
>
>
> Jun Nie (5):
> Documentation: synopsys-dw-mshc: add binding for fifo quirks
> mmc: dw: Add fifo address property
> mmc: dw: Add fifo watermark alignment property
> mmc: dt-bindings: add ZTE ZX296718 MMC bindings
> mmc: zx: Initial support for ZX mmc controller
>
> .../devicetree/bindings/mmc/synopsys-dw-mshc.txt | 13 ++
> .../devicetree/bindings/mmc/zx-dw-mshc.txt | 33 +++
> drivers/mmc/host/Kconfig | 9 +
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/dw_mmc-zx.c | 242 +++++++++++++++++++++
> drivers/mmc/host/dw_mmc-zx.h | 31 +++
> drivers/mmc/host/dw_mmc.c | 17 +-
> include/linux/mmc/dw_mmc.h | 5 +
> 8 files changed, 348 insertions(+), 3 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/mmc/zx-dw-mshc.txt
> create mode 100644 drivers/mmc/host/dw_mmc-zx.c
> create mode 100644 drivers/mmc/host/dw_mmc-zx.h
>
Jaehoon，
Could you help add this patch set to your branch that for next merge
window? Thank you very much!
Jun
^ permalink raw reply
* Re: [PATCH v6 4/4] of/fdt: mark hotpluggable memory
From: Heinrich Schuchardt @ 2016-12-25 9:02 UTC (permalink / raw)
To: Reza Arbab
Cc: Balbir Singh, Aneesh Kumar K . V, H . Peter Anvin,
Alistair Popple, Benjamin Herrenschmidt, Bharata B Rao,
Frank Rowand, Ingo Molnar, Michael Ellerman, Nathan Fontenot,
Paul Mackerras, Rob Herring, Stewart Smith, Thomas Gleixner,
Andrew Morton, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mm-Bw31MaZKKs3YtjvyW6yDsg, Heinrich Schuchardt
In-Reply-To: <1478562276-25539-5-git-send-email-arbab-23VcF4HTsmIX0ybBhKVfKdBPR1lH4CV8@public.gmane.org>
The patch adds a new property "linux,hotpluggable" to memory nodes of the
device tree.
memory@0 {
reg = <0x0 0x01000000 0x0 0x7f000000>;
linux,hotpluggable;
}
Memory areas marked by this property can later be disabled using the hotplugging
API. Especially for virtual machines this is a very useful capability.
Unfortunately the notation chosen does not fit well with the concept of
devicetree overlays which allow to change the devicetree during runtime.
I suggest to use the following notation
memory@0 {
compatible = "linux,hotpluggable-memory";
reg = <0x0 0x01000000 0x0 0x7f000000>;
status = "disabled";
}
This will allow us to write a device driver that can react to changes of the
devicetree made via devicetree overlays.
This driver could react to the change of the status between "okay" and
"disabled" and update the memory status accordingly.
Further we could use devicetree overlays to provide additional hotpluggable
memory.
The referenced patch has already been pulled for 4.10. But I hope it is not
too late for this design change.
Best regards
Heinrich Schuchardt
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 3/3] nfc: trf7970a: Prevent repeated polling from crashing the kernel
From: Mark Greer @ 2016-12-24 17:24 UTC (permalink / raw)
To: Geoff Lansberry
Cc: linux-wireless, Lauro Ramos Venancio, Aloisio Almeida Jr,
Samuel Ortiz, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, netdev-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Justin Bronder, Jaret Cantu
In-Reply-To: <CAO7Z3W+n85jbr8cmj3HJV1c+eL=oRh-XRy+O=iZ+mD=ov2WABA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Sat, Dec 24, 2016 at 11:17:18AM -0500, Geoff Lansberry wrote:
> Mark - I'm sorry, but I did not write this code, and therefore was not
> able to accurately describe it. It is fixing a different issue, not
> the neard segfault that we are still chasing. Last week Jaret Cantu
> sent a separate email explaining the purpose of the code, which had
> you copied, did you see that?
Hm, no, I didn't. I received an email from Justin Bronder but not from
Jaret Cantu. Justin's email did help but is still pretty high-level.
We need a clear understanding as to what is happening in the digital
layer and the driver to know how execution is getting into a block of
error handling code that should never be executed. Once we understand
that we can start thinking about what the best fix is.
> Does it explain why it was done to
> your satisfaction? I've asked him to join in on the effort to push
> the change upstream, however he will not be available until the new
> year.
I expect that it would help if he joins. After the holidays is fine -
I think many people are taking it easy for the next week or so, anyway.
> I know you did suggest that we split off that change from the others,
> and if now is the time to do that, let me know. If you don't have
> the email from Jaret, also please let me know and I will forward it to
> you.
I think it would help you if you split it off because the first two patches
have a good chance of being accepted but this one doesn't (yet). If you
separate the them, it will make it easier for Samuel to take the first two
(or he may take the first two anyway but its always good to make it as
easy maintainers as you can).
Mark
--
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 3/3] nfc: trf7970a: Prevent repeated polling from crashing the kernel
From: Geoff Lansberry @ 2016-12-24 16:17 UTC (permalink / raw)
To: Mark Greer
Cc: linux-wireless, Lauro Ramos Venancio, Aloisio Almeida Jr,
Samuel Ortiz, robh+dt, mark.rutland, netdev, devicetree,
linux-kernel, Justin Bronder, Jaret Cantu
In-Reply-To: <20161224060141.GA9069@animalcreek.com>
Mark - I'm sorry, but I did not write this code, and therefore was not
able to accurately describe it. It is fixing a different issue, not
the neard segfault that we are still chasing. Last week Jaret Cantu
sent a separate email explaining the purpose of the code, which had
you copied, did you see that? Does it explain why it was done to
your satisfaction? I've asked him to join in on the effort to push
the change upstream, however he will not be available until the new
year.
I know you did suggest that we split off that change from the others,
and if now is the time to do that, let me know. If you don't have
the email from Jaret, also please let me know and I will forward it to
you.
Geoff
Geoff Lansberry
Engineering Guy
Kuvée, Inc
125 Kingston St., 3rd Floor
Boston, MA 02111
1-617-290-1118 (m)
geoff.lansberry (skype)
http://www.kuvee.com
On Sat, Dec 24, 2016 at 1:01 AM, Mark Greer <mgreer@animalcreek.com> wrote:
> On Wed, Dec 21, 2016 at 11:18:34PM -0500, Geoff Lansberry wrote:
>> From: Jaret Cantu <jaret.cantu@timesys.com>
>>
>> Repeated polling attempts cause a NULL dereference error to occur.
>> This is because the state of the trf7970a is currently reading but
>> another request has been made to send a command before it has finished.
>>
>> The solution is to properly kill the waiting reading (workqueue)
>> before failing on the send.
>>
>> Signed-off-by: Geoff Lansberry <geoff@kuvee.com>
>> ---
>
> You've still provided virtually no information on the actual problem(s)
> nor justified why you think this is the best solution. You're adding
> code to a section of code that should _never_ be executed so the only
> reasonable things I can infer is that there are, at least, two problems:
>
> 1) There is a bug causing execution to get into this block of code.
>
> 2) Once in this block of code, there is another bug.
>
> You seem to be attempting to fix 2) and completely ignoring 1).
> 1) is the first bug that needs to be root-caused and fixed.
>
> Also, what exactly is the "NULL dereference error" you mention?
> Is this the neard crash you talked about in another thread or is
> this a kernel crash? If it is the kernel crash, please post the
> relevant information. If this is the neard crash - which seems
> unlikely - then how can changing a section of kernel code that
> shouldn't be executed in the first place fix that?
>
> Mark
> --
^ permalink raw reply
* [PATCH] of: drop duplicate headers
From: Geliang Tang @ 2016-12-24 15:45 UTC (permalink / raw)
To: Pantelis Antoniou, Rob Herring, Frank Rowand
Cc: Geliang Tang, devicetree, linux-kernel
Drop duplicate headers string.h and of_platform.h.
Signed-off-by: Geliang Tang <geliangtang@gmail.com>
---
drivers/of/overlay.c | 1 -
drivers/of/resolver.c | 1 -
drivers/of/unittest.c | 1 -
3 files changed, 3 deletions(-)
diff --git a/drivers/of/overlay.c b/drivers/of/overlay.c
index 0d4cda7..d4e337e 100644
--- a/drivers/of/overlay.c
+++ b/drivers/of/overlay.c
@@ -18,7 +18,6 @@
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/errno.h>
-#include <linux/string.h>
#include <linux/slab.h>
#include <linux/err.h>
#include <linux/idr.h>
diff --git a/drivers/of/resolver.c b/drivers/of/resolver.c
index 8bf12e9..7ae9863 100644
--- a/drivers/of/resolver.c
+++ b/drivers/of/resolver.c
@@ -18,7 +18,6 @@
#include <linux/string.h>
#include <linux/ctype.h>
#include <linux/errno.h>
-#include <linux/string.h>
#include <linux/slab.h>
/* illegal phandle value (set when unresolved) */
diff --git a/drivers/of/unittest.c b/drivers/of/unittest.c
index 53c83d6..b4e8236 100644
--- a/drivers/of/unittest.c
+++ b/drivers/of/unittest.c
@@ -17,7 +17,6 @@
#include <linux/slab.h>
#include <linux/device.h>
#include <linux/platform_device.h>
-#include <linux/of_platform.h>
#include <linux/i2c.h>
#include <linux/i2c-mux.h>
--
2.9.3
^ permalink raw reply related
* Re: [PATCH] ARM: dts: imx: remove obsoleted property fsl,spi-num-chipselects
From: Fabio Estevam @ 2016-12-24 12:47 UTC (permalink / raw)
To: Vladimir Zapolskiy
Cc: Shawn Guo, Fabio Estevam, Sascha Hauer, Alexander Shiyan,
Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <20161224054354.28289-1-vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
On Sat, Dec 24, 2016 at 3:43 AM, Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org> wrote:
> Since commit b36581df7e78 ("spi: imx: Using existing properties for
> chipselects") the device tree property 'fsl,spi-num-chipselects' is
> unused and it is already marked as obsolete in device tree binding
> documentation. Remove the property from the existing DTS files to
> avoid its reoccurence on copying.
>
> Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
Reviewed-by: Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH] adc: add adc driver for Hisilicon BVT SOCs
From: Jonathan Cameron @ 2016-12-24 11:46 UTC (permalink / raw)
To: Allen Liu, jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: akinobu.mita-Re5JQEeQqe8AvxtiuMwx3w,
ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w,
krzk-DgEjT+Ai2ygdnm+yROfE0A, vilhelm.gray-Re5JQEeQqe8AvxtiuMwx3w,
ksenija.stanojevic-Re5JQEeQqe8AvxtiuMwx3w,
zhiyong.tao-NuS5LvNUpcJWk0Htik3J/w,
daniel.baluta-ral2JQCrhuEAvxtiuMwx3w,
leonard.crestez-ral2JQCrhuEAvxtiuMwx3w,
ray.jui-dY08KVG/lbpWk0Htik3J/w,
raveendra.padasalagi-dY08KVG/lbpWk0Htik3J/w,
mranostay-Re5JQEeQqe8AvxtiuMwx3w,
amsfield22-Re5JQEeQqe8AvxtiuMwx3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.lixu-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1482544497-136656-1-git-send-email-liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On 24 December 2016 01:54:57 GMT+00:00, Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org> wrote:
>Add ADC driver for the ADC controller found on HiSilicon BVT SOCs, like
>Hi3516CV300, etc.
>The ADC controller is primarily in charge of detecting voltage.
>
>Reviewed-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>Signed-off-by: Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Reading on phone so may not be that thorough!
Looks pretty good. The device abstraction makes it slightly more complicated than it needs
to be. If you aren't going to follow up quickly with other device support please drop the
abstraction. It can be easily readded when needed.
Various little things inline.
Thanks
Jonathan
>---
> .../devicetree/bindings/iio/adc/hibvt-lsadc.txt | 26 ++
> drivers/iio/adc/Kconfig | 10 +
> drivers/iio/adc/Makefile | 1 +
>drivers/iio/adc/hibvt_lsadc.c | 344
>+++++++++++++++++++++
> 4 files changed, 381 insertions(+)
>create mode 100644
>Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> create mode 100644 drivers/iio/adc/hibvt_lsadc.c
>
>diff --git a/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>new file mode 100644
>index 0000000..63de46e
>--- /dev/null
>+++ b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
>@@ -0,0 +1,26 @@
>+Hisilicon BVT Low Speed (LS) A/D Converter bindings
>+
>+Required properties:
>+- compatible: should be "hisilicon,<name>-lsadc"
>+ - "hisilicon,hibvt-lsadc": for hi3516cv300
>+
>+- reg: physical base address of the controller and length of memory
>mapped
>+ region.
>+- interrupts: The interrupt number to the cpu. The interrupt specifier
>format
>+ depends on the interrupt controller.
A cross reference to the interrupt bindings doc always good to add.
>+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
>+
>+Optional properties:
>+- resets: Must contain an entry for each entry in reset-names if need
>support
>+ this option. See ../reset/reset.txt for details.
>+- reset-names: Must include the name "saradc-apb".
>+
>+Example:
>+ lsadc: hibvt-lsadc@120e0000 {
>+ compatible = "hisilicon,hibvt-lsadc";
>+ reg = <0x120e0000 0x1000>;
>+ interrupts = <19>;
>+ resets = <&crg 0x7c 3>;
>+ reset-names = "lsadc-crg";
Doesn't contain saradc-apb which docs say it must...
>+ status = "disabled";
Not documented...
>+ };
>diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
>index 99c0514..0443f51 100644
>--- a/drivers/iio/adc/Kconfig
>+++ b/drivers/iio/adc/Kconfig
>@@ -225,6 +225,16 @@ config HI8435
> This driver can also be built as a module. If so, the module will be
> called hi8435.
>
>+config HIBVT_LSADC
>+ tristate "HIBVT LSADC driver"
>+ depends on ARCH_HISI || COMPILE_TEST
>+ help
>+ Say yes here to build support for the LSADC found in SoCs from
>+ hisilicon BVT chip.
>+
>+ To compile this driver as a module, choose M here: the
>+ module will be called hibvt_lsadc.
>+
> config INA2XX_ADC
> tristate "Texas Instruments INA2xx Power Monitors IIO driver"
> depends on I2C && !SENSORS_INA2XX
>diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
>index 7a40c04..6554d92 100644
>--- a/drivers/iio/adc/Makefile
>+++ b/drivers/iio/adc/Makefile
>@@ -23,6 +23,7 @@ obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
> obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
> obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
> obj-$(CONFIG_HI8435) += hi8435.o
>+obj-$(CONFIG_HIBVT_LSADC) += hibvt_lsadc.o
> obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
> obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
> obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
>diff --git a/drivers/iio/adc/hibvt_lsadc.c
>b/drivers/iio/adc/hibvt_lsadc.c
>new file mode 100644
>index 0000000..a20afe8
>--- /dev/null
>+++ b/drivers/iio/adc/hibvt_lsadc.c
>@@ -0,0 +1,344 @@
>+/*
>+ * Hisilicon BVT Low Speed (LS) A/D Converter
>+ * Copyright (C) 2016 HiSilicon Technologies Co., Ltd.
>+ *
>+ * This program is free software; you can redistribute it and/or
>modify
>+ * it under the terms of the GNU General Public License as published
>by
>+ * the Free Software Foundation; either version 2 of the License, or
>+ * (at your option) any later version.
>+ *
>+ * This program is distributed in the hope that it will be useful,
>+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
>+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
>+ * GNU General Public License for more details.
>+ */
>+
>+#include <linux/module.h>
>+#include <linux/platform_device.h>
>+#include <linux/interrupt.h>
>+#include <linux/io.h>
>+#include <linux/of.h>
>+#include <linux/of_device.h>
>+#include <linux/clk.h>
>+#include <linux/completion.h>
>+#include <linux/delay.h>
>+#include <linux/reset.h>
>+#include <linux/regulator/consumer.h>
>+#include <linux/iio/iio.h>
>+
>+/* hisilicon bvt adc registers definitions */
>+#define LSADC_CONFIG 0x00
>+#define CONFIG_DEGLITCH BIT(17)
Please add a driver specific prefix to all defines to keep them in their own namespace.
>+#define CONFIG_RESET BIT(15)
>+#define CONFIG_POWERDOWN BIT(14)
>+#define CONFIG_MODE BIT(13)
>+#define CONFIG_CHC_VALID BIT(10)
>+#define CONFIG_CHB_VALID BIT(9)
>+#define CONFIG_CHA_VALID BIT(8)
>+
>+#define LSADC_TIMESCAN 0x08
Lsadc is perhaps to generic a prefix. Clash chances are a bit high
>+#define LSADC_INTEN 0x10
>+#define LSADC_INTSTATUS 0x14
>+#define LSADC_INTCLR 0x18
>+#define LSADC_START 0x1C
>+#define LSADC_STOP 0x20
>+#define LSADC_ACTBIT 0x24
>+#define LSADC_CHNDATA 0x2C
>+
>+#define ADC_CON_EN (1u << 0)
>+#define ADC_CON_DEN (0u << 0)
>+
>+#define ADC_NUM_BITS 10
>+
>+/* fix clk:3000000, default tscan set 10ms */
>+#define DEF_ADC_TSCAN_MS (10*3000)
>+
>+#define LSADC_CHN_MASK 0x7
>+
>+#define LSADC_TIMEOUT msecs_to_jiffies(100)
>+
>+/* default voltage scale for every channel <mv> */
>+static int g_voltage[] = {
>+ 3300, 3300, 3300
>+};
Prefix these as well.
>+
>+struct hibvt_lsadc {
>+ void __iomem *regs;
>+ struct completion completion;
>+ struct reset_control *reset;
>+ const struct hibvt_lsadc_data *data;
>+ unsigned int cur_chn;
>+ unsigned int value;
>+};
>+
>+struct hibvt_lsadc_data {
>+ int num_bits;
>+ const struct iio_chan_spec *channels;
>+ int num_channels;
>+
>+ void (*clear_irq)(struct hibvt_lsadc *info, int mask);
>+ void (*start_conv)(struct hibvt_lsadc *info);
>+ void (*stop_conv)(struct hibvt_lsadc *info);
>+};
>+
>+static int hibvt_lsadc_read_raw(struct iio_dev *indio_dev,
>+ struct iio_chan_spec const *chan,
>+ int *val, int *val2, long mask)
>+{
>+ struct hibvt_lsadc *info = iio_priv(indio_dev);
>+
>+ switch (mask) {
>+ case IIO_CHAN_INFO_RAW:
>+ mutex_lock(&indio_dev->mlock);
>+
>+ reinit_completion(&info->completion);
>+
>+ /* Select the channel to be used */
>+ info->cur_chn = chan->channel;
>+
>+ if (info->data->start_conv)
>+ info->data->start_conv(info);
>+
>+ if (!wait_for_completion_timeout(&info->completion,
>+ LSADC_TIMEOUT)) {
>+ if (info->data->stop_conv)
>+ info->data->stop_conv(info);
>+ mutex_unlock(&indio_dev->mlock);
>+ return -ETIMEDOUT;
>+ }
>+
>+ *val = info->value;
>+ mutex_unlock(&indio_dev->mlock);
>+ return IIO_VAL_INT;
>+ case IIO_CHAN_INFO_SCALE:
>+ *val = g_voltage[chan->channel];
>+ *val2 = info->data->num_bits;
>+ return IIO_VAL_FRACTIONAL_LOG2;
>+ default:
>+ return -EINVAL;
>+ }
>+}
>+
>+static irqreturn_t hibvt_lsadc_isr(int irq, void *dev_id)
>+{
>+ struct hibvt_lsadc *info = (struct hibvt_lsadc *)dev_id;
>+ int mask;
>+
>+ mask = readl(info->regs + LSADC_INTSTATUS);
>+ mask &= LSADC_CHN_MASK;
>+
>+ /* Clear irq */
>+ if (info->data->clear_irq)
>+ info->data->clear_irq(info, mask);
>+
>+ /* Read value */
>+ info->value = readl(info->regs + LSADC_CHNDATA + (info->cur_chn <<
>2));
>+ info->value &= GENMASK(info->data->num_bits - 1, 0);
>+
>+ /* stop adc */
>+ if (info->data->stop_conv)
>+ info->data->stop_conv(info);
>+
>+ complete(&info->completion);
>+
>+ return IRQ_HANDLED;
>+}
>+
>+static const struct iio_info hibvt_lsadc_iio_info = {
>+ .read_raw = hibvt_lsadc_read_raw,
>+ .driver_module = THIS_MODULE,
>+};
>+
>+#define ADC_CHANNEL(_index, _id) { \
Prefix this define.
>+ .type = IIO_VOLTAGE, \
>+ .indexed = 1, \
>+ .channel = _index, \
>+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
>+ BIT(IIO_CHAN_INFO_SCALE), \
>+ .datasheet_name = _id, \
>+}
>+
>+static const struct iio_chan_spec hibvt_lsadc_iio_channels[] = {
>+ ADC_CHANNEL(0, "adc0"),
>+ ADC_CHANNEL(1, "adc1"),
>+ ADC_CHANNEL(2, "adc2"),
>+};
>+
>+static void hibvt_lsadc_clear_irq(struct hibvt_lsadc *info, int mask)
>+{
>+ writel(mask, info->regs + LSADC_INTCLR);
>+}
>+
>+static void hibvt_lsadc_start_conv(struct hibvt_lsadc *info)
>+{
>+ unsigned int con;
>+
>+ /* set number bit */
>+ con = GENMASK(info->data->num_bits - 1, 0);
>+ writel(con, (info->regs + LSADC_ACTBIT));
>+
>+ /* config */
>+ con = readl(info->regs + LSADC_CONFIG);
>+ con &= ~CONFIG_RESET;
>+ con |= (CONFIG_POWERDOWN | CONFIG_DEGLITCH | CONFIG_MODE);
>+ con &= ~(CONFIG_CHA_VALID | CONFIG_CHB_VALID | CONFIG_CHC_VALID);
>+ con |= (CONFIG_CHA_VALID << info->cur_chn);
>+ writel(con, (info->regs + LSADC_CONFIG));
>+
>+ /* set timescan */
>+ writel(DEF_ADC_TSCAN_MS, (info->regs + LSADC_TIMESCAN));
>+
>+ /* clear interrupt */
>+ writel(LSADC_CHN_MASK, info->regs + LSADC_INTCLR);
>+
>+ /* enable interrupt */
>+ writel(ADC_CON_EN, (info->regs + LSADC_INTEN));
>+
>+ /* start scan */
>+ writel(ADC_CON_EN, (info->regs + LSADC_START));
>+}
>+
>+static void hibvt_lsadc_stop_conv(struct hibvt_lsadc *info)
>+{
>+ /* reset the timescan */
>+ writel(ADC_CON_DEN, (info->regs + LSADC_TIMESCAN));
>+
>+ /* disable interrupt */
>+ writel(ADC_CON_DEN, (info->regs + LSADC_INTEN));
>+
>+ /* stop scan */
>+ writel(ADC_CON_EN, (info->regs + LSADC_STOP));
>+}
>+
>+static const struct hibvt_lsadc_data lsadc_data = {
>+ .num_bits = ADC_NUM_BITS,
>+ .channels = hibvt_lsadc_iio_channels,
>+ .num_channels = ARRAY_SIZE(hibvt_lsadc_iio_channels),
>+
>+ .clear_irq = hibvt_lsadc_clear_irq,
>+ .start_conv = hibvt_lsadc_start_conv,
>+ .stop_conv = hibvt_lsadc_stop_conv,
>+};
Usual convention is to only introduce a device type specific structure when more than one device is supported. If you are going to follow up
shortly with more device support then leave it but add a note to the patch description. If not please drop this abstraction.
>+
>+static const struct of_device_id hibvt_lsadc_match[] = {
>+ {
>+ .compatible = "hisilicon,hibvt-lsadc",
>+ .data = &lsadc_data,
>+ },
>+ {},
>+};
>+MODULE_DEVICE_TABLE(of, hibvt_lsadc_match);
>+
>+/**
>+ * Reset LSADC Controller.
Single line comment syntax please.
>+ */
>+static void hibvt_lsadc_reset_controller(struct reset_control *reset)
>+{
>+ reset_control_assert(reset);
>+ usleep_range(10, 20);
>+ reset_control_deassert(reset);
>+}
>+
>+static int hibvt_lsadc_probe(struct platform_device *pdev)
>+{
>+ struct hibvt_lsadc *info = NULL;
>+ struct device_node *np = pdev->dev.of_node;
>+ struct iio_dev *indio_dev = NULL;
>+ struct resource *mem;
>+ const struct of_device_id *match;
>+ int ret;
>+ int irq;
>+
>+ if (!np)
>+ return -ENODEV;
>+
>+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
>+ if (!indio_dev) {
>+ dev_err(&pdev->dev, "failed allocating iio device\n");
>+ return -ENOMEM;
>+ }
>+ info = iio_priv(indio_dev);
>+
>+ match = of_match_device(hibvt_lsadc_match, &pdev->dev);
>+ info->data = match->data;
>+
>+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>+ info->regs = devm_ioremap_resource(&pdev->dev, mem);
>+ if (IS_ERR(info->regs))
>+ return PTR_ERR(info->regs);
>+
>+ /*
>+ * The reset should be an optional property, as it should work
>+ * with old devicetrees as well
>+ */
>+ info->reset = devm_reset_control_get(&pdev->dev, "lsadc-crg");
>+ if (IS_ERR(info->reset)) {
>+ ret = PTR_ERR(info->reset);
>+ if (ret != -ENOENT)
>+ return ret;
>+
>+ dev_dbg(&pdev->dev, "no reset control found\n");
>+ info->reset = NULL;
>+ }
>+
>+ init_completion(&info->completion);
>+
>+ irq = platform_get_irq(pdev, 0);
>+ if (irq < 0) {
>+ dev_err(&pdev->dev, "no irq resource?\n");
>+ return irq;
>+ }
>+
>+ ret = devm_request_irq(&pdev->dev, irq, hibvt_lsadc_isr,
>+ 0, dev_name(&pdev->dev), info);
>+ if (ret < 0) {
>+ dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
>+ return ret;
>+ }
>+
>+ if (info->reset)
>+ hibvt_lsadc_reset_controller(info->reset);
>+
>+ platform_set_drvdata(pdev, indio_dev);
>+
>+ indio_dev->name = dev_name(&pdev->dev);
>+ indio_dev->dev.parent = &pdev->dev;
>+ indio_dev->dev.of_node = pdev->dev.of_node;
>+ indio_dev->info = &hibvt_lsadc_iio_info;
>+ indio_dev->modes = INDIO_DIRECT_MODE;
>+
>+ indio_dev->channels = info->data->channels;
>+ indio_dev->num_channels = info->data->num_channels;
>+
>+ ret = iio_device_register(indio_dev);
>+ if (ret < 0) {
>+ dev_err(&pdev->dev, "failed register iio device\n");
>+ return ret;
>+ }
>+
>+ return 0;
>+}
>+
>+static int hibvt_lsadc_remove(struct platform_device *pdev)
>+{
>+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
>+
>+ iio_device_unregister(indio_dev);
As nothing else here can use devm version of register and drop remove entirely.
>+
>+ return 0;
>+}
>+
>+static struct platform_driver hibvt_lsadc_driver = {
>+ .probe = hibvt_lsadc_probe,
>+ .remove = hibvt_lsadc_remove,
>+ .driver = {
>+ .name = "hibvt-lsadc",
>+ .of_match_table = hibvt_lsadc_match,
>+ },
>+};
>+
>+module_platform_driver(hibvt_lsadc_driver);
>+
>+MODULE_AUTHOR("Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>");
>+MODULE_DESCRIPTION("hisilicon BVT LSADC driver");
>+MODULE_LICENSE("GPL v2");
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
^ permalink raw reply
* Re: [PATCH] iio: misc: add a generic regulator driver
From: Jonathan Cameron @ 2016-12-24 10:43 UTC (permalink / raw)
To: Geert Uytterhoeven, Lars-Peter Clausen
Cc: Bartosz Golaszewski, Jonathan Cameron, Hartmut Knaack,
Peter Meerwald-Stadler, Rob Herring, Mark Rutland,
linux-iio-u79uwXL29TY76Z2rM5mHXA, linux-devicetree, LKML,
Kevin Hilman, Patrick Titiano, Neil Armstrong, Liam Girdwood,
Mark Brown, linus.walleij-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <CAMuHMdXnzDUYcr8qiUTwE2peBdjwuVWPRUkms2J8AHFaQ=SHHQ-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 23 December 2016 12:56:11 GMT+00:00, Geert Uytterhoeven <geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org> wrote:
>Hi Lars,
>
>On Fri, Dec 23, 2016 at 12:35 PM, Lars-Peter Clausen <lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org>
>wrote:
>> On 12/23/2016 11:00 AM, Geert Uytterhoeven wrote:
>>> On Mon, Dec 12, 2016 at 6:15 PM, Lars-Peter Clausen
><lars-Qo5EllUWu/uELgA04lAiVw@public.gmane.org> wrote:
>>>> On 12/06/2016 12:12 PM, Bartosz Golaszewski wrote:
>>>>> We're already using libiio to read the measured data from the
>power
>>>>> monitor, that's why we'd like to use the iio framework for
>>>>> power-cycling the devices as well. My question is: would bridging
>the
>>>>> regulator framework be the right solution? Should we look for
>>>>> something else? Bridge the GPIO framework instead?
>>>>
>>>> I wouldn't necessaries create bridge, but instead just use the GPIO
>>>> framework directly.
>>>>
>>>> We now have the GPIO chardev interface which meant to be used to
>support
>>>> application specific logic that control the GPIOs, but where you
>don't want
>>>> to write a kernel driver.
>>>>
>>>> My idea was to add GPIOs and GPIO chips as high level object inside
>libiio
>>>> that can be accessed through the same context as the IIO devices.
>Similar to
>>>> the current IIO API you have a API for gpios that allows to
>enumerate the
>>>> GPIO devices and their pins as well as modify the pin state.
>>>
>>> That would mean libiio has access to all GPIOs, allowing a remote
>person
>>> to not only control through iiod the GPIOs for industrial control,
>but also the
>>> GPIOs not intended for export, right?
>>
>> Well, it is a policy question. Who gets access to what. Right now it
>is all
>> or nothing, a privileged application gets access to all
>devices/GPIOs, a
>> unprivileged application gets access to nothing. Same for GPIOs as
>well as
>> IIO devices.
>>
>> iiod at the moment does not have any access control at all, which in
>itself
>> is a problem. We need to add support for that at some point. I don't
>see an
>> issue with implementing a finer grained access scheme when we do so.
>E.g.
>> unprivileged applications only get access to certain pins.
>
>OK, so that's WIP.
>
>>> Having a separate GPIO switch driver avoids that, as DT (or some
>other means)
>>> can be used to specify and label the GPIOs for IIO use.
>>
>> Sure, functionally this would be equivalent, but we have to ask
>whether this
>> is the right way to use the DT. Is access policy specification part
>of the
>> hardware description? In my opinion the answer is no. At the hardware
>> description level there is no operating system, there is no userspace
>or
>> kernelspace, there is are no access levels. Putting the distinction
>between
>> a switch/regulator that can be controlled from userspace or can only
>be
>> controlled from kernel space into the DT would be a layering
>violation. It
>> is analogous to why we don't have spidev DT bindings. This is an
>issue that
>> needs to be solved at a higher level. In my opinion this level is a
>> cooperation between kernel- and userspace. Kernelspace offering an
>interface
>> to export a device for userspace access and userspace making use of
>that
>> interface to request access to a device. In a similar way to how vfio
>is
>> structured.
>
>I'm not advocating using DT for policy, only for hardware description.
>
>We have means (bindings) to describe GPIOs connected to LEDs and
>switches
>(incl. their labels), while you can control LEDs through plain GPIO
>sysfs
>export or chardev, too. It's just more error prone to use the latter.
>
>We do not have bindings to describe GPIOs connected to e.g. relays.
We should.
>
>Switching external devices (the internals of those devices not
>described
>itself in DT, like in an industrial context), sounds more like
>something to
>be handled by IIO, doesn't it?
Certainly, if there is known hardware to describe, we should endeavour to describe it.
Userspace interfaces are needed wherever we hit the boundary of what we can describe,
whether because we are measuring things not in our control (e.g. what key is pressed on a
keyboard) or because the next bit of hardware is interchangeable (e.g. your relay example, or
this power switch).
The challenge is to structure the device model for the interchangeable edge case to be the
same, more or less, as it would be if we knew what was hanging off the switch.
Hence, we either cut out early (gpio) or we attempt to put an appropriate consumer in place
for the gpio (or possibly the power switch if we describe that). No problem at all in doing that
last chunk with IIO or GPIO userspace as appropriate...
The challenge is that we are representing the fact the hardware is unknown in device tree.
Perhaps we need a way to make that explicit? Is there one already? Things like extcon do similar
things I guess.
Same is true for regulators, when they are at the edge of the device...
On the binary channel types in IIO we have discussed this a fair bit in the past. There
Is a non trivial amount of work needed to do triggered input (demuxing to multiple consumers
In particular).
Sysfs stuff would be simple but then it would really be gpio interface wrapped up a bit.
What IIO would bring to the mix ultimately is synchronized triggering of input and output.
(Speaking of which, Lars any progress on output buffers? Perhaps if we post that someone else might pick it up and run with it?)
One could argue the relay case is more of a mux than anything else so perhaps the ongoing
generic mux subsystem discussion would be a good place to talk about that?
Interesting discussion, sorry it took me until my Christmas train journey to join in).
Linus, if you get a chance, you have probably thought more about gpio IIO interactions than I have!
Jonathan
>
>Gr{oetje,eeting}s,
>
> Geert
>
>--
>Geert Uytterhoeven -- There's lots of Linux beyond ia32 --
>geert-Td1EMuHUCqxL1ZNQvxDV9g@public.gmane.org
>
>In personal conversations with technical people, I call myself a
>hacker. But
>when I'm talking to journalists I just say "programmer" or something
>like that.
> -- Linus Torvalds
>--
>To unsubscribe from this list: send the line "unsubscribe linux-iio" in
>the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
>More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Sent from my Android device with K-9 Mail. Please excuse my brevity.
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 6/6] arm64: arch_timer: acpi: add hisi timer errata data
From: Kefeng Wang @ 2016-12-24 7:11 UTC (permalink / raw)
To: Ding Tianhong, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, marc.zyngier-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, oss-fOR+EgIDQEHk1uMJSBkQmQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linuxarm-hv44wF8Li93QT0dZR+AlfA
Cc: Hanjun Guo
In-Reply-To: <1482476669-15596-7-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On 2016/12/23 15:04, Ding Tianhong wrote:
> From: Hanjun Guo <hanjun.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>
> Add hisi timer specific erratum fixes.
>
> v3: add hisilicon erratum 161601 for ACPI mode.
>
> v4: update some data structures.
>
> Signed-off-by: Hanjun Guo <hanjun.guo-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> ---
> drivers/clocksource/arm_arch_timer.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index 212bfa5..7b15d2a 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -1089,10 +1089,28 @@ struct gtdt_arch_timer_fixup {
> void *context;
> };
>
> +#ifdef CONFIG_HISILICON_ERRATUM_161601
> +static void __init erratum_workaround_enable(void *context)
> +{
> + u64 erratum = (u64) context;
> +
> + if (erratum & HISILICON_161601) {
> + timer_unstable_counter_workaround = &arch_timer_hisi_161601;
> + static_branch_enable(&arch_timer_read_ool_enabled);
> + pr_info("Enabling workaround for HISILICON ERRATUM 161601\n");
> + }
Use arch_timer_hisi_161601 for context instead of HISILICON_161601 directly,
we can make erratum_workaround_enable more general.
> +}
> +#endif
> +
> /* note: this needs to be updated according to the doc of OEM ID
> * and TABLE ID for different board.
> */
> struct gtdt_arch_timer_fixup arch_timer_quirks[] __initdata = {
> +#ifdef CONFIG_HISILICON_ERRATUM_161601
> + {"HISI", "hip05", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
> + {"HISI", "hip06", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
> + {"HISI", "hip07", 0, &erratum_workaround_enable, (void *) HISILICON_161601},
> +#endif
> };
>
> void __init arch_timer_acpi_quirks_handler(char *oem_id,
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v5 3/6] arm64: arch_timer: Work around Erratum Hisilicon-161601
From: Kefeng Wang @ 2016-12-24 6:07 UTC (permalink / raw)
To: Ding Tianhong, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8, marc.zyngier-5wv7dgnIgG8,
mark.rutland-5wv7dgnIgG8, oss-fOR+EgIDQEHk1uMJSBkQmQ,
devicetree-u79uwXL29TY76Z2rM5mHXA,
shawnguo-DgEjT+Ai2ygdnm+yROfE0A, stuart.yoder-3arQi8VN3Tc,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linuxarm-hv44wF8Li93QT0dZR+AlfA
In-Reply-To: <1482476669-15596-4-git-send-email-dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
On 2016/12/23 15:04, Ding Tianhong wrote:
> Erratum Hisilicon-161601 says that the ARM generic timer counter "has the
> potential to contain an erroneous value when the timer value changes".
> Accesses to TVAL (both read and write) are also affected due to the implicit counter
> read. Accesses to CVAL are not affected.
>
> The workaround is to reread the system count registers until the value of the second
> read is larger than the first one by less than 32, the system counter can be guaranteed
> not to return wrong value twice by back-to-back read and the error value is always larger
> than the correct one by 32. Writes to TVAL are replaced with an equivalent write to CVAL.
>
> The workaround is enabled if the hisilicon,erratum-161601 property is found in
> the timer node in the device tree. This can be overridden with the
> clocksource.arm_arch_timer.hisilicon-161601 boot parameter, which allows KVM
> users to enable the workaround until a mechanism is implemented to
> automatically communicate this information.
>
> Fix some description for fsl erratum a008585.
>
> v2: Significant rework based on feedback, including seperate the fsl erratum a008585
> to another patch, update the erratum name and remove unwanted code.
>
> v3: Significant rework based on feedback, including fix some alignment problem, make the
> #define __hisi_161601_read_reg to be private to the .c file instead of being globally
> visible, add more accurate annotation and modify a bit of logical format to enable
> arch_timer_read_ool_enabled, remove the kernel commandline parameter
> clocksource.arm_arch_timer.hisilicon-161601.
>
> v5: Theoretically the erratum should not occur more than twice in succession when reading
> the system counter, but it is possible that some interrupts may lead to more than twice
> read errors, triggering the warning, so setting the number of retries to 50 which is far
> beyond the number of iterations the loop has been observed to take.
>
> Signed-off-by: Ding Tianhong <dingtianhong-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>
> ---
> Documentation/arm64/silicon-errata.txt | 1 +
> arch/arm64/include/asm/arch_timer.h | 2 +-
> drivers/clocksource/Kconfig | 9 +++++
> drivers/clocksource/arm_arch_timer.c | 70 +++++++++++++++++++++++++++++++---
> 4 files changed, 76 insertions(+), 6 deletions(-)
>
> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt
> index 405da11..1c1a95f 100644
> --- a/Documentation/arm64/silicon-errata.txt
> +++ b/Documentation/arm64/silicon-errata.txt
> @@ -63,3 +63,4 @@ stable kernels.
> | Cavium | ThunderX SMMUv2 | #27704 | N/A |
> | | | | |
> | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 |
> +| Hisilicon | Hip0{5,6,7} | #161601 | HISILICON_ERRATUM_161601|
> diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h
> index f882c7c..ebf4cde 100644
> --- a/arch/arm64/include/asm/arch_timer.h
> +++ b/arch/arm64/include/asm/arch_timer.h
> @@ -29,7 +29,7 @@
>
> #include <clocksource/arm_arch_timer.h>
>
> -#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585)
> +#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
> extern struct static_key_false arch_timer_read_ool_enabled;
> #define needs_unstable_timer_counter_workaround() \
> static_branch_unlikely(&arch_timer_read_ool_enabled)
> diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
> index 4866f7a..162d820 100644
> --- a/drivers/clocksource/Kconfig
> +++ b/drivers/clocksource/Kconfig
> @@ -335,6 +335,15 @@ config FSL_ERRATUM_A008585
> value"). The workaround will only be active if the
> fsl,erratum-a008585 property is found in the timer node.
>
> +config HISILICON_ERRATUM_161601
> + bool "Workaround for Hisilicon Erratum 161601"
> + default y
> + depends on ARM_ARCH_TIMER && ARM64
> + help
> + This option enables a workaround for Hisilicon Erratum
> + 161601. The workaround will be active if the hisilicon,erratum-161601
> + property is found in the timer node.
> +
> config ARM_GLOBAL_TIMER
> bool "Support for the ARM global timer" if COMPILE_TEST
> select CLKSRC_OF if OF
> diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
> index e7406ad..9a82496 100644
> --- a/drivers/clocksource/arm_arch_timer.c
> +++ b/drivers/clocksource/arm_arch_timer.c
> @@ -95,15 +95,18 @@ static int __init early_evtstrm_cfg(char *buf)
> * Architected system timer support.
> */
>
> -#ifdef CONFIG_FSL_ERRATUM_A008585
> +#if CONFIG_FSL_ERRATUM_A008585 || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
> struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
> EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
>
> #define FSL_A008585 0x0001
> +#define HISILICON_161601 0x0002
It looks like the DEFINE is useless，
> +
> +static struct arch_timer_erratum_workaround arch_timer_hisi_161601 = {
> + .erratum = HISILICON_161601,
Just a errata description, eg.
.desc = "HISILICON ERRATUM 161601"
then....
> + .read_cntp_tval_el0 = hisi_161601_read_cntp_tval_el0,
> + .read_cntv_tval_el0 = hisi_161601_read_cntv_tval_el0,
> + .read_cntvct_el0 = hisi_161601_read_cntvct_el0,
> +};
> +#endif /* CONFIG_HISILICON_ERRATUM_161601 */
[..]
> -#ifdef CONFIG_FSL_ERRATUM_A008585
> +#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
> /*
> * Don't use the vdso fastpath if errata require using
> * the out-of-line counter accessor.
> @@ -909,10 +960,19 @@ static int __init arch_timer_of_init(struct device_node *np)
> #ifdef CONFIG_FSL_ERRATUM_A008585
> if (!timer_unstable_counter_workaround && of_property_read_bool(np, "fsl,erratum-a008585"))
> timer_unstable_counter_workaround = &arch_timer_fsl_a008585;
> +#endif
> +
> +#ifdef CONFIG_HISILICON_ERRATUM_161601
> + if (!timer_unstable_counter_workaround && of_property_read_bool(np, "hisilicon,erratum-161601"))
> + timer_unstable_counter_workaround = &arch_timer_hisi_161601;
> +#endif
>
> +#if IS_ENABLED(CONFIG_FSL_ERRATUM_A008585) || IS_ENABLED(CONFIG_HISILICON_ERRATUM_161601)
> if (timer_unstable_counter_workaround) {
> static_branch_enable(&arch_timer_read_ool_enabled);
> - pr_info("Enabling workaround for FSL erratum A-008585\n");
> + pr_info("Enabling workaround for %s\n",
> + timer_unstable_counter_workaround->erratum == FSL_A008585 ?
> + "FSL ERRATUM A-008585" : "HISILICON ERRATUM 161601");
......> pr_info("Enabling workaround for %s\n", timer_unstable_counter_workaround->desc)
> }
> #endif
>
>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v3 3/3] nfc: trf7970a: Prevent repeated polling from crashing the kernel
From: Mark Greer @ 2016-12-24 6:01 UTC (permalink / raw)
To: Geoff Lansberry
Cc: linux-wireless, lauro.venancio, aloisio.almeida, sameo, robh+dt,
mark.rutland, netdev, devicetree, linux-kernel, justin,
Jaret Cantu
In-Reply-To: <1482380314-16440-3-git-send-email-geoff@kuvee.com>
On Wed, Dec 21, 2016 at 11:18:34PM -0500, Geoff Lansberry wrote:
> From: Jaret Cantu <jaret.cantu@timesys.com>
>
> Repeated polling attempts cause a NULL dereference error to occur.
> This is because the state of the trf7970a is currently reading but
> another request has been made to send a command before it has finished.
>
> The solution is to properly kill the waiting reading (workqueue)
> before failing on the send.
>
> Signed-off-by: Geoff Lansberry <geoff@kuvee.com>
> ---
You've still provided virtually no information on the actual problem(s)
nor justified why you think this is the best solution. You're adding
code to a section of code that should _never_ be executed so the only
reasonable things I can infer is that there are, at least, two problems:
1) There is a bug causing execution to get into this block of code.
2) Once in this block of code, there is another bug.
You seem to be attempting to fix 2) and completely ignoring 1).
1) is the first bug that needs to be root-caused and fixed.
Also, what exactly is the "NULL dereference error" you mention?
Is this the neard crash you talked about in another thread or is
this a kernel crash? If it is the kernel crash, please post the
relevant information. If this is the neard crash - which seems
unlikely - then how can changing a section of kernel code that
shouldn't be executed in the first place fix that?
Mark
^ permalink raw reply
* [PATCH] ARM: dts: imx: remove obsoleted property fsl,spi-num-chipselects
From: Vladimir Zapolskiy @ 2016-12-24 5:43 UTC (permalink / raw)
To: Shawn Guo, Fabio Estevam
Cc: Sascha Hauer, Alexander Shiyan, Rob Herring,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA
Since commit b36581df7e78 ("spi: imx: Using existing properties for
chipselects") the device tree property 'fsl,spi-num-chipselects' is
unused and it is already marked as obsolete in device tree binding
documentation. Remove the property from the existing DTS files to
avoid its reoccurence on copying.
Signed-off-by: Vladimir Zapolskiy <vz-ChpfBGZJDbMAvxtiuMwx3w@public.gmane.org>
---
arch/arm/boot/dts/imx1-ads.dts | 1 -
arch/arm/boot/dts/imx27-apf27dev.dts | 2 --
arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts | 1 -
arch/arm/boot/dts/imx27-pdk.dts | 1 -
arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi | 1 -
arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts | 1 -
arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi | 1 -
arch/arm/boot/dts/imx50-evk.dts | 1 -
arch/arm/boot/dts/imx51-apf51dev.dts | 2 --
arch/arm/boot/dts/imx51-babbage.dts | 1 -
arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi | 1 -
arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts | 1 -
arch/arm/boot/dts/imx53-smd.dts | 1 -
arch/arm/boot/dts/imx53-tqma53.dtsi | 2 --
arch/arm/boot/dts/imx53-tx53.dtsi | 1 -
arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi | 1 -
arch/arm/boot/dts/imx6dl-aristainetos_4.dts | 1 -
arch/arm/boot/dts/imx6q-ba16.dtsi | 1 -
arch/arm/boot/dts/imx6q-bx50v3.dtsi | 1 -
arch/arm/boot/dts/imx6q-cm-fx6.dts | 1 -
arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts | 1 -
arch/arm/boot/dts/imx6q-evi.dts | 3 ---
arch/arm/boot/dts/imx6q-gw5400-a.dts | 1 -
arch/arm/boot/dts/imx6q-marsboard.dts | 1 -
arch/arm/boot/dts/imx6q-novena.dts | 1 -
arch/arm/boot/dts/imx6qdl-apalis.dtsi | 2 --
arch/arm/boot/dts/imx6qdl-apf6dev.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-aristainetos.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi | 3 ---
arch/arm/boot/dts/imx6qdl-colibri.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-rex.dtsi | 2 --
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-sabrelite.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-sabresd.dtsi | 1 -
arch/arm/boot/dts/imx6qdl-ts4900.dtsi | 2 --
arch/arm/boot/dts/imx6qdl-tx6.dtsi | 1 -
arch/arm/boot/dts/imx6sl-evk.dts | 1 -
arch/arm/boot/dts/imx6sx-nitrogen6sx.dts | 1 -
arch/arm/boot/dts/imx6ul-tx6ul.dtsi | 1 -
arch/arm/boot/dts/imx7d-sdb.dts | 1 -
47 files changed, 57 deletions(-)
diff --git a/arch/arm/boot/dts/imx1-ads.dts b/arch/arm/boot/dts/imx1-ads.dts
index f504986..5ea28ee 100644
--- a/arch/arm/boot/dts/imx1-ads.dts
+++ b/arch/arm/boot/dts/imx1-ads.dts
@@ -38,7 +38,6 @@
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx27-apf27dev.dts b/arch/arm/boot/dts/imx27-apf27dev.dts
index bba3f41..5f84b59 100644
--- a/arch/arm/boot/dts/imx27-apf27dev.dts
+++ b/arch/arm/boot/dts/imx27-apf27dev.dts
@@ -77,7 +77,6 @@
};
&cspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1 &pinctrl_cspi1_cs>;
@@ -95,7 +94,6 @@
};
&cspi2 {
- fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 21 GPIO_ACTIVE_LOW>,
<&gpio4 27 GPIO_ACTIVE_LOW>,
<&gpio2 17 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
index 27846ff..f565357 100644
--- a/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
+++ b/arch/arm/boot/dts/imx27-eukrea-mbimxsd27-baseboard.dts
@@ -81,7 +81,6 @@
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_LOW>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx27-pdk.dts b/arch/arm/boot/dts/imx27-pdk.dts
index d0ef496..96f442b 100644
--- a/arch/arm/boot/dts/imx27-pdk.dts
+++ b/arch/arm/boot/dts/imx27-pdk.dts
@@ -37,7 +37,6 @@
&cspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi2>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
index 1b62480..4f3e0f4 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycard-s-som.dtsi
@@ -23,7 +23,6 @@
};
&cspi1 {
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_HIGH>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
index cf09e72..2a9198f 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-rdk.dts
@@ -69,7 +69,6 @@
&cspi1 {
pinctrl-0 = <&pinctrl_cspi1>, <&pinctrl_cspi1cs1>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>,
<&gpio4 27 GPIO_ACTIVE_LOW>;
};
diff --git a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
index b4e955e..82fec93 100644
--- a/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
+++ b/arch/arm/boot/dts/imx27-phytec-phycore-som.dtsi
@@ -75,7 +75,6 @@
&cspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi1>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 28 GPIO_ACTIVE_HIGH>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx50-evk.dts b/arch/arm/boot/dts/imx50-evk.dts
index 27d763c..dba2d95 100644
--- a/arch/arm/boot/dts/imx50-evk.dts
+++ b/arch/arm/boot/dts/imx50-evk.dts
@@ -26,7 +26,6 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 11 0>, <&gpio4 13 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx51-apf51dev.dts b/arch/arm/boot/dts/imx51-apf51dev.dts
index 0f3fe29..a5e6091 100644
--- a/arch/arm/boot/dts/imx51-apf51dev.dts
+++ b/arch/arm/boot/dts/imx51-apf51dev.dts
@@ -80,7 +80,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_HIGH>;
status = "okay";
@@ -89,7 +88,6 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 28 GPIO_ACTIVE_LOW>,
<&gpio3 27 GPIO_ACTIVE_LOW>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx51-babbage.dts b/arch/arm/boot/dts/imx51-babbage.dts
index f097b4f..873cf24 100644
--- a/arch/arm/boot/dts/imx51-babbage.dts
+++ b/arch/arm/boot/dts/imx51-babbage.dts
@@ -178,7 +178,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>,
<&gpio4 25 GPIO_ACTIVE_LOW>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
index 16fc69c..b821066 100644
--- a/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
+++ b/arch/arm/boot/dts/imx51-digi-connectcore-som.dtsi
@@ -24,7 +24,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
index 7282128..1305b05 100644
--- a/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
+++ b/arch/arm/boot/dts/imx51-eukrea-mbimxsd51-baseboard.dts
@@ -114,7 +114,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53-smd.dts b/arch/arm/boot/dts/imx53-smd.dts
index 9f51900..472f6f0 100644
--- a/arch/arm/boot/dts/imx53-smd.dts
+++ b/arch/arm/boot/dts/imx53-smd.dts
@@ -63,7 +63,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx53-tqma53.dtsi b/arch/arm/boot/dts/imx53-tqma53.dtsi
index 91a6a9f..85972f2 100644
--- a/arch/arm/boot/dts/imx53-tqma53.dtsi
+++ b/arch/arm/boot/dts/imx53-tqma53.dtsi
@@ -55,7 +55,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>,
<&gpio3 24 0>, <&gpio3 25 0>;
status = "disabled";
@@ -249,7 +248,6 @@
&cspi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cspi>;
- fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio1 18 0>, <&gpio1 19 0>,
<&gpio1 21 0>;
status = "disabled";
diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi
index 57e75f1..3a32201 100644
--- a/arch/arm/boot/dts/imx53-tx53.dtsi
+++ b/arch/arm/boot/dts/imx53-tx53.dtsi
@@ -161,7 +161,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
status = "okay";
cs-gpios = <
diff --git a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
index ba689fb..524192c 100644
--- a/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
+++ b/arch/arm/boot/dts/imx53-voipac-dmm-668.dtsi
@@ -129,7 +129,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio2 30 0>, <&gpio3 19 0>, <&gpio2 16 0>, <&gpio2 17 0>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
index d4c4a22..32a812b 100644
--- a/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
+++ b/arch/arm/boot/dts/imx6dl-aristainetos_4.dts
@@ -66,7 +66,6 @@
};
&ecspi2 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
diff --git a/arch/arm/boot/dts/imx6q-ba16.dtsi b/arch/arm/boot/dts/imx6q-ba16.dtsi
index 308e11c..3577aa7 100644
--- a/arch/arm/boot/dts/imx6q-ba16.dtsi
+++ b/arch/arm/boot/dts/imx6q-ba16.dtsi
@@ -133,7 +133,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6q-bx50v3.dtsi b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
index e4a415f..b1be794 100644
--- a/arch/arm/boot/dts/imx6q-bx50v3.dtsi
+++ b/arch/arm/boot/dts/imx6q-bx50v3.dtsi
@@ -95,7 +95,6 @@
};
&ecspi5 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
diff --git a/arch/arm/boot/dts/imx6q-cm-fx6.dts b/arch/arm/boot/dts/imx6q-cm-fx6.dts
index a150bca..ae90d98 100644
--- a/arch/arm/boot/dts/imx6q-cm-fx6.dts
+++ b/arch/arm/boot/dts/imx6q-cm-fx6.dts
@@ -114,7 +114,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>, <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
index 908dab6..f28883b 100644
--- a/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
+++ b/arch/arm/boot/dts/imx6q-dmo-edmqmx6.dts
@@ -104,7 +104,6 @@
&ecspi5 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi5>;
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio1 12 0>;
status = "okay";
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 7c7c1a8..fd2220a 100644
--- a/arch/arm/boot/dts/imx6q-evi.dts
+++ b/arch/arm/boot/dts/imx6q-evi.dts
@@ -90,7 +90,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 10 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1cs>;
@@ -98,7 +97,6 @@
};
&ecspi3 {
- fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_LOW>,
<&gpio4 25 GPIO_ACTIVE_LOW>,
<&gpio4 26 GPIO_ACTIVE_LOW>;
@@ -108,7 +106,6 @@
};
&ecspi5 {
- fsl,spi-num-chipselects = <4>;
cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
<&gpio1 13 GPIO_ACTIVE_LOW>,
<&gpio1 12 GPIO_ACTIVE_LOW>,
diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts
index 747bc10..8e84713 100644
--- a/arch/arm/boot/dts/imx6q-gw5400-a.dts
+++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts
@@ -138,7 +138,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts
index f7995c5..51220a3 100644
--- a/arch/arm/boot/dts/imx6q-marsboard.dts
+++ b/arch/arm/boot/dts/imx6q-marsboard.dts
@@ -97,7 +97,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>;
- fsl,spi-num-chipselects = <1>;
status = "okay";
m25p80@0 {
diff --git a/arch/arm/boot/dts/imx6q-novena.dts b/arch/arm/boot/dts/imx6q-novena.dts
index 758bca9..0fa32b2 100644
--- a/arch/arm/boot/dts/imx6q-novena.dts
+++ b/arch/arm/boot/dts/imx6q-novena.dts
@@ -210,7 +210,6 @@
&ecspi3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3_novena>;
- fsl,spi-num-chipselects = <3>;
status = "okay";
};
diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
index 8c8a049..82652c1 100644
--- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi
@@ -175,7 +175,6 @@
/* Apalis SPI1 */
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 25 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
@@ -184,7 +183,6 @@
/* Apalis SPI2 */
&ecspi2 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
diff --git a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
index 5e7792d..550e100 100644
--- a/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-apf6dev.dtsi
@@ -176,7 +176,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>,
<&gpio4 10 GPIO_ACTIVE_LOW>,
<&gpio4 11 GPIO_ACTIVE_LOW>;
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
index 54f4f01..b2debc0 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos.dtsi
@@ -100,7 +100,6 @@
};
&ecspi4 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 20 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
diff --git a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
index 7fff02c..0d9e96d 100644
--- a/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-aristainetos2.dtsi
@@ -114,7 +114,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
&gpio4 10 GPIO_ACTIVE_HIGH
&gpio4 11 GPIO_ACTIVE_HIGH>;
@@ -124,7 +123,6 @@
};
&ecspi2 {
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
@@ -132,7 +130,6 @@
};
&ecspi4 {
- fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
index e6faa65..dbad481 100644
--- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi
@@ -138,7 +138,6 @@
/* Colibri SSP */
&ecspi4 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
diff --git a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
index b2c083d..d78312c 100644
--- a/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-dfi-fs700-m60.dtsi
@@ -29,7 +29,6 @@
};
&ecspi3 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
index 54aca3a..ab34f15 100644
--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
@@ -159,7 +159,6 @@
};
&ecspi3 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
index 63acd54..e19f3c3 100644
--- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi
@@ -209,7 +209,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
index 34887a1..e46c914 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi
@@ -353,7 +353,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
index d80f21a..678ab19 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_som2.dtsi
@@ -284,7 +284,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
index e476d01..c4d28e9 100644
--- a/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-nitrogen6x.dtsi
@@ -255,7 +255,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index e9801a2..6e5cb6a 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -76,7 +76,6 @@
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
status = "okay";
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 24 0>;
flash@0 {
diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi
index 17704a5..5cf90c24 100644
--- a/arch/arm/boot/dts/imx6qdl-rex.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi
@@ -89,7 +89,6 @@
};
&ecspi2 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio5 12 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
@@ -97,7 +96,6 @@
};
&ecspi3 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 26 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
index 52390ba..a2a714d 100644
--- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
@@ -124,7 +124,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
index 1f9076e..b0fa0c8 100644
--- a/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabrelite.dtsi
@@ -241,7 +241,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
index 55ef535..63bf95e 100644
--- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi
@@ -160,7 +160,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 9 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
index 5c26b26..bf17ad5 100644
--- a/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-ts4900.dtsi
@@ -95,7 +95,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
@@ -109,7 +108,6 @@
};
&ecspi2 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
index 2bf2e62..1691714 100644
--- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi
@@ -221,7 +221,6 @@
&ecspi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <
&gpio2 30 GPIO_ACTIVE_HIGH
&gpio3 19 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts
index be11882..0a90eea 100644
--- a/arch/arm/boot/dts/imx6sl-evk.dts
+++ b/arch/arm/boot/dts/imx6sl-evk.dts
@@ -117,7 +117,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio4 11 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
index 9b817f3..b54b40a 100644
--- a/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
+++ b/arch/arm/boot/dts/imx6sx-nitrogen6sx.dts
@@ -142,7 +142,6 @@
};
&ecspi1 {
- fsl,spi-num-chipselects = <1>;
cs-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
index 530e9ca..c784a0b 100644
--- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi
@@ -285,7 +285,6 @@
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
- fsl,spi-num-chipselects = <2>;
cs-gpios = <
&gpio1 29 GPIO_ACTIVE_HIGH
&gpio1 10 GPIO_ACTIVE_HIGH
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 2f33c46..9d15273 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -111,7 +111,6 @@
};
&ecspi3 {
- fsl,spi-num-chipselects = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi3>;
cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>;
--
2.10.2
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* Re: [PATCH] adc: add adc driver for Hisilicon BVT SOCs
From: Jiancheng Xue @ 2016-12-24 2:31 UTC (permalink / raw)
To: Allen Liu, jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: yanhaifeng-C8/M+/jPZTeaMJb+Lgu22Q,
hermit.wangheming-C8/M+/jPZTeaMJb+Lgu22Q,
akinobu.mita-Re5JQEeQqe8AvxtiuMwx3w,
ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w,
krzk-DgEjT+Ai2ygdnm+yROfE0A, vilhelm.gray-Re5JQEeQqe8AvxtiuMwx3w,
ksenija.stanojevic-Re5JQEeQqe8AvxtiuMwx3w,
zhiyong.tao-NuS5LvNUpcJWk0Htik3J/w,
daniel.baluta-ral2JQCrhuEAvxtiuMwx3w,
leonard.crestez-ral2JQCrhuEAvxtiuMwx3w,
ray.jui-dY08KVG/lbpWk0Htik3J/w,
raveendra.padasalagi-dY08KVG/lbpWk0Htik3J/w,
mranostay-Re5JQEeQqe8AvxtiuMwx3w,
amsfield22-Re5JQEeQqe8AvxtiuMwx3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
kevin.lixu-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <1482544497-136656-1-git-send-email-liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
On 2016/12/24 9:54, Allen Liu wrote:
> Add ADC driver for the ADC controller found on HiSilicon BVT SOCs, like Hi3516CV300, etc.
> The ADC controller is primarily in charge of detecting voltage.
>
> Reviewed-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Hi
Sorry. I haven't reviewed this patch. Please remove this line. Thank you!
Regards,
Jiancheng
> Signed-off-by: Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
> ---
> .../devicetree/bindings/iio/adc/hibvt-lsadc.txt | 26 ++
> drivers/iio/adc/Kconfig | 10 +
> drivers/iio/adc/Makefile | 1 +
> drivers/iio/adc/hibvt_lsadc.c | 344 +++++++++++++++++++++
> 4 files changed, 381 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> create mode 100644 drivers/iio/adc/hibvt_lsadc.c
>
> diff --git a/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> new file mode 100644
> index 0000000..63de46e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
> @@ -0,0 +1,26 @@
> +Hisilicon BVT Low Speed (LS) A/D Converter bindings
> +
> +Required properties:
> +- compatible: should be "hisilicon,<name>-lsadc"
> + - "hisilicon,hibvt-lsadc": for hi3516cv300
> +
> +- reg: physical base address of the controller and length of memory mapped
> + region.
> +- interrupts: The interrupt number to the cpu. The interrupt specifier format
> + depends on the interrupt controller.
> +- #io-channel-cells: Should be 1, see ../iio-bindings.txt
> +
> +Optional properties:
> +- resets: Must contain an entry for each entry in reset-names if need support
> + this option. See ../reset/reset.txt for details.
> +- reset-names: Must include the name "saradc-apb".
> +
> +Example:
> + lsadc: hibvt-lsadc@120e0000 {
> + compatible = "hisilicon,hibvt-lsadc";
> + reg = <0x120e0000 0x1000>;
> + interrupts = <19>;
> + resets = <&crg 0x7c 3>;
> + reset-names = "lsadc-crg";
> + status = "disabled";
> + };
> diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
> index 99c0514..0443f51 100644
> --- a/drivers/iio/adc/Kconfig
> +++ b/drivers/iio/adc/Kconfig
> @@ -225,6 +225,16 @@ config HI8435
> This driver can also be built as a module. If so, the module will be
> called hi8435.
>
> +config HIBVT_LSADC
> + tristate "HIBVT LSADC driver"
> + depends on ARCH_HISI || COMPILE_TEST
> + help
> + Say yes here to build support for the LSADC found in SoCs from
> + hisilicon BVT chip.
> +
> + To compile this driver as a module, choose M here: the
> + module will be called hibvt_lsadc.
> +
> config INA2XX_ADC
> tristate "Texas Instruments INA2xx Power Monitors IIO driver"
> depends on I2C && !SENSORS_INA2XX
> diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
> index 7a40c04..6554d92 100644
> --- a/drivers/iio/adc/Makefile
> +++ b/drivers/iio/adc/Makefile
> @@ -23,6 +23,7 @@ obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
> obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
> obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
> obj-$(CONFIG_HI8435) += hi8435.o
> +obj-$(CONFIG_HIBVT_LSADC) += hibvt_lsadc.o
> obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
> obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
> obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
> diff --git a/drivers/iio/adc/hibvt_lsadc.c b/drivers/iio/adc/hibvt_lsadc.c
> new file mode 100644
> index 0000000..a20afe8
> --- /dev/null
> +++ b/drivers/iio/adc/hibvt_lsadc.c
> @@ -0,0 +1,344 @@
> +/*
> + * Hisilicon BVT Low Speed (LS) A/D Converter
> + * Copyright (C) 2016 HiSilicon Technologies Co., Ltd.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/interrupt.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/clk.h>
> +#include <linux/completion.h>
> +#include <linux/delay.h>
> +#include <linux/reset.h>
> +#include <linux/regulator/consumer.h>
> +#include <linux/iio/iio.h>
> +
> +/* hisilicon bvt adc registers definitions */
> +#define LSADC_CONFIG 0x00
> +#define CONFIG_DEGLITCH BIT(17)
> +#define CONFIG_RESET BIT(15)
> +#define CONFIG_POWERDOWN BIT(14)
> +#define CONFIG_MODE BIT(13)
> +#define CONFIG_CHC_VALID BIT(10)
> +#define CONFIG_CHB_VALID BIT(9)
> +#define CONFIG_CHA_VALID BIT(8)
> +
> +#define LSADC_TIMESCAN 0x08
> +#define LSADC_INTEN 0x10
> +#define LSADC_INTSTATUS 0x14
> +#define LSADC_INTCLR 0x18
> +#define LSADC_START 0x1C
> +#define LSADC_STOP 0x20
> +#define LSADC_ACTBIT 0x24
> +#define LSADC_CHNDATA 0x2C
> +
> +#define ADC_CON_EN (1u << 0)
> +#define ADC_CON_DEN (0u << 0)
> +
> +#define ADC_NUM_BITS 10
> +
> +/* fix clk:3000000, default tscan set 10ms */
> +#define DEF_ADC_TSCAN_MS (10*3000)
> +
> +#define LSADC_CHN_MASK 0x7
> +
> +#define LSADC_TIMEOUT msecs_to_jiffies(100)
> +
> +/* default voltage scale for every channel <mv> */
> +static int g_voltage[] = {
> + 3300, 3300, 3300
> +};
> +
> +struct hibvt_lsadc {
> + void __iomem *regs;
> + struct completion completion;
> + struct reset_control *reset;
> + const struct hibvt_lsadc_data *data;
> + unsigned int cur_chn;
> + unsigned int value;
> +};
> +
> +struct hibvt_lsadc_data {
> + int num_bits;
> + const struct iio_chan_spec *channels;
> + int num_channels;
> +
> + void (*clear_irq)(struct hibvt_lsadc *info, int mask);
> + void (*start_conv)(struct hibvt_lsadc *info);
> + void (*stop_conv)(struct hibvt_lsadc *info);
> +};
> +
> +static int hibvt_lsadc_read_raw(struct iio_dev *indio_dev,
> + struct iio_chan_spec const *chan,
> + int *val, int *val2, long mask)
> +{
> + struct hibvt_lsadc *info = iio_priv(indio_dev);
> +
> + switch (mask) {
> + case IIO_CHAN_INFO_RAW:
> + mutex_lock(&indio_dev->mlock);
> +
> + reinit_completion(&info->completion);
> +
> + /* Select the channel to be used */
> + info->cur_chn = chan->channel;
> +
> + if (info->data->start_conv)
> + info->data->start_conv(info);
> +
> + if (!wait_for_completion_timeout(&info->completion,
> + LSADC_TIMEOUT)) {
> + if (info->data->stop_conv)
> + info->data->stop_conv(info);
> + mutex_unlock(&indio_dev->mlock);
> + return -ETIMEDOUT;
> + }
> +
> + *val = info->value;
> + mutex_unlock(&indio_dev->mlock);
> + return IIO_VAL_INT;
> + case IIO_CHAN_INFO_SCALE:
> + *val = g_voltage[chan->channel];
> + *val2 = info->data->num_bits;
> + return IIO_VAL_FRACTIONAL_LOG2;
> + default:
> + return -EINVAL;
> + }
> +}
> +
> +static irqreturn_t hibvt_lsadc_isr(int irq, void *dev_id)
> +{
> + struct hibvt_lsadc *info = (struct hibvt_lsadc *)dev_id;
> + int mask;
> +
> + mask = readl(info->regs + LSADC_INTSTATUS);
> + mask &= LSADC_CHN_MASK;
> +
> + /* Clear irq */
> + if (info->data->clear_irq)
> + info->data->clear_irq(info, mask);
> +
> + /* Read value */
> + info->value = readl(info->regs + LSADC_CHNDATA + (info->cur_chn << 2));
> + info->value &= GENMASK(info->data->num_bits - 1, 0);
> +
> + /* stop adc */
> + if (info->data->stop_conv)
> + info->data->stop_conv(info);
> +
> + complete(&info->completion);
> +
> + return IRQ_HANDLED;
> +}
> +
> +static const struct iio_info hibvt_lsadc_iio_info = {
> + .read_raw = hibvt_lsadc_read_raw,
> + .driver_module = THIS_MODULE,
> +};
> +
> +#define ADC_CHANNEL(_index, _id) { \
> + .type = IIO_VOLTAGE, \
> + .indexed = 1, \
> + .channel = _index, \
> + .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
> + BIT(IIO_CHAN_INFO_SCALE), \
> + .datasheet_name = _id, \
> +}
> +
> +static const struct iio_chan_spec hibvt_lsadc_iio_channels[] = {
> + ADC_CHANNEL(0, "adc0"),
> + ADC_CHANNEL(1, "adc1"),
> + ADC_CHANNEL(2, "adc2"),
> +};
> +
> +static void hibvt_lsadc_clear_irq(struct hibvt_lsadc *info, int mask)
> +{
> + writel(mask, info->regs + LSADC_INTCLR);
> +}
> +
> +static void hibvt_lsadc_start_conv(struct hibvt_lsadc *info)
> +{
> + unsigned int con;
> +
> + /* set number bit */
> + con = GENMASK(info->data->num_bits - 1, 0);
> + writel(con, (info->regs + LSADC_ACTBIT));
> +
> + /* config */
> + con = readl(info->regs + LSADC_CONFIG);
> + con &= ~CONFIG_RESET;
> + con |= (CONFIG_POWERDOWN | CONFIG_DEGLITCH | CONFIG_MODE);
> + con &= ~(CONFIG_CHA_VALID | CONFIG_CHB_VALID | CONFIG_CHC_VALID);
> + con |= (CONFIG_CHA_VALID << info->cur_chn);
> + writel(con, (info->regs + LSADC_CONFIG));
> +
> + /* set timescan */
> + writel(DEF_ADC_TSCAN_MS, (info->regs + LSADC_TIMESCAN));
> +
> + /* clear interrupt */
> + writel(LSADC_CHN_MASK, info->regs + LSADC_INTCLR);
> +
> + /* enable interrupt */
> + writel(ADC_CON_EN, (info->regs + LSADC_INTEN));
> +
> + /* start scan */
> + writel(ADC_CON_EN, (info->regs + LSADC_START));
> +}
> +
> +static void hibvt_lsadc_stop_conv(struct hibvt_lsadc *info)
> +{
> + /* reset the timescan */
> + writel(ADC_CON_DEN, (info->regs + LSADC_TIMESCAN));
> +
> + /* disable interrupt */
> + writel(ADC_CON_DEN, (info->regs + LSADC_INTEN));
> +
> + /* stop scan */
> + writel(ADC_CON_EN, (info->regs + LSADC_STOP));
> +}
> +
> +static const struct hibvt_lsadc_data lsadc_data = {
> + .num_bits = ADC_NUM_BITS,
> + .channels = hibvt_lsadc_iio_channels,
> + .num_channels = ARRAY_SIZE(hibvt_lsadc_iio_channels),
> +
> + .clear_irq = hibvt_lsadc_clear_irq,
> + .start_conv = hibvt_lsadc_start_conv,
> + .stop_conv = hibvt_lsadc_stop_conv,
> +};
> +
> +static const struct of_device_id hibvt_lsadc_match[] = {
> + {
> + .compatible = "hisilicon,hibvt-lsadc",
> + .data = &lsadc_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, hibvt_lsadc_match);
> +
> +/**
> + * Reset LSADC Controller.
> + */
> +static void hibvt_lsadc_reset_controller(struct reset_control *reset)
> +{
> + reset_control_assert(reset);
> + usleep_range(10, 20);
> + reset_control_deassert(reset);
> +}
> +
> +static int hibvt_lsadc_probe(struct platform_device *pdev)
> +{
> + struct hibvt_lsadc *info = NULL;
> + struct device_node *np = pdev->dev.of_node;
> + struct iio_dev *indio_dev = NULL;
> + struct resource *mem;
> + const struct of_device_id *match;
> + int ret;
> + int irq;
> +
> + if (!np)
> + return -ENODEV;
> +
> + indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
> + if (!indio_dev) {
> + dev_err(&pdev->dev, "failed allocating iio device\n");
> + return -ENOMEM;
> + }
> + info = iio_priv(indio_dev);
> +
> + match = of_match_device(hibvt_lsadc_match, &pdev->dev);
> + info->data = match->data;
> +
> + mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + info->regs = devm_ioremap_resource(&pdev->dev, mem);
> + if (IS_ERR(info->regs))
> + return PTR_ERR(info->regs);
> +
> + /*
> + * The reset should be an optional property, as it should work
> + * with old devicetrees as well
> + */
> + info->reset = devm_reset_control_get(&pdev->dev, "lsadc-crg");
> + if (IS_ERR(info->reset)) {
> + ret = PTR_ERR(info->reset);
> + if (ret != -ENOENT)
> + return ret;
> +
> + dev_dbg(&pdev->dev, "no reset control found\n");
> + info->reset = NULL;
> + }
> +
> + init_completion(&info->completion);
> +
> + irq = platform_get_irq(pdev, 0);
> + if (irq < 0) {
> + dev_err(&pdev->dev, "no irq resource?\n");
> + return irq;
> + }
> +
> + ret = devm_request_irq(&pdev->dev, irq, hibvt_lsadc_isr,
> + 0, dev_name(&pdev->dev), info);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
> + return ret;
> + }
> +
> + if (info->reset)
> + hibvt_lsadc_reset_controller(info->reset);
> +
> + platform_set_drvdata(pdev, indio_dev);
> +
> + indio_dev->name = dev_name(&pdev->dev);
> + indio_dev->dev.parent = &pdev->dev;
> + indio_dev->dev.of_node = pdev->dev.of_node;
> + indio_dev->info = &hibvt_lsadc_iio_info;
> + indio_dev->modes = INDIO_DIRECT_MODE;
> +
> + indio_dev->channels = info->data->channels;
> + indio_dev->num_channels = info->data->num_channels;
> +
> + ret = iio_device_register(indio_dev);
> + if (ret < 0) {
> + dev_err(&pdev->dev, "failed register iio device\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int hibvt_lsadc_remove(struct platform_device *pdev)
> +{
> + struct iio_dev *indio_dev = platform_get_drvdata(pdev);
> +
> + iio_device_unregister(indio_dev);
> +
> + return 0;
> +}
> +
> +static struct platform_driver hibvt_lsadc_driver = {
> + .probe = hibvt_lsadc_probe,
> + .remove = hibvt_lsadc_remove,
> + .driver = {
> + .name = "hibvt-lsadc",
> + .of_match_table = hibvt_lsadc_match,
> + },
> +};
> +
> +module_platform_driver(hibvt_lsadc_driver);
> +
> +MODULE_AUTHOR("Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>");
> +MODULE_DESCRIPTION("hisilicon BVT LSADC driver");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply
* Re: [PATCH v2 4/4] clk: rockchip: add new pll-type for rk3328
From: Heiko Stuebner @ 2016-12-24 2:18 UTC (permalink / raw)
To: Elaine Zhang
Cc: mturquette, sboyd, xf, robh+dt, mark.rutland, linux-clk,
linux-arm-kernel, devicetree, huangtao, xxx, cl, linux-rockchip,
linux-kernel
In-Reply-To: <1482112573-11613-5-git-send-email-zhangqing@rock-chips.com>
Hi Elaine,
Am Montag, 19. Dezember 2016, 09:56:13 CET schrieb Elaine Zhang:
> The rk3328's pll and clock are similar with rk3036's,
> it different with pll_mode_mask,there are different
> control registers bit,
> so these should be independent and separate from
> the series of rk3328s.
not sure I understand this description. In the patch (and TRM excerpt) I see
that the number of parents is down to only xin24m but the general handling is
similar to the rk3036 and thus reuses its operations.
The description makes it sound like there are operational differences (the
"different control register bit" part), so could you clarify this a bit
please?
Also, please move the pll addition before the addition of the clock-controller
in the series and move the pll-type addition also here from the controller
patch.
Some more below:
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> ---
> drivers/clk/rockchip/clk-pll.c | 13 ++++++++++++-
> 1 file changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
> index 6ed605776abd..9650c75f61d1 100644
> --- a/drivers/clk/rockchip/clk-pll.c
> +++ b/drivers/clk/rockchip/clk-pll.c
> @@ -29,6 +29,7 @@
> #define PLL_MODE_SLOW 0x0
> #define PLL_MODE_NORM 0x1
> #define PLL_MODE_DEEP 0x2
> +#define PLL_RK3328_MODE_MASK 0x1
>
> struct rockchip_clk_pll {
> struct clk_hw hw;
> @@ -865,13 +866,17 @@ struct clk *rockchip_clk_register_pll(struct
> rockchip_clk_provider *ctx, pll_mux = &pll->pll_mux;
> pll_mux->reg = ctx->reg_base + mode_offset;
> pll_mux->shift = mode_shift;
> - pll_mux->mask = PLL_MODE_MASK;
> + if (pll_type == pll_rk3328)
> + pll_mux->mask = PLL_RK3328_MODE_MASK;
> + else
> + pll_mux->mask = PLL_MODE_MASK;
you're missing the other parts handling parents, like num_parents check
and the init.num_parents parameter.
The pll really has only one parent, xin24m, so we should handle this
correctly in the code, instead of having 2 times xin24m in the parent
array coming from the clock controller.
> pll_mux->flags = 0;
> pll_mux->lock = &ctx->lock;
> pll_mux->hw.init = &init;
>
> if (pll_type == pll_rk3036 ||
> pll_type == pll_rk3066 ||
> + pll_type == pll_rk3328 ||
> pll_type == pll_rk3399)
> pll_mux->flags |= CLK_MUX_HIWORD_MASK;
>
> @@ -929,6 +934,12 @@ struct clk *rockchip_clk_register_pll(struct
> rockchip_clk_provider *ctx, else
> init.ops = &rockchip_rk3066_pll_clk_ops;
> break;
> + case pll_rk3328:
> + if (!pll->rate_table || IS_ERR(ctx->grf))
> + init.ops = &rockchip_rk3036_pll_clk_norate_ops;
> + else
> + init.ops = &rockchip_rk3036_pll_clk_ops;
> + break;
please don't duplicate the rk3036-ops assignment, when adding the
pll_rk3328 option to the rk3036 part suffices.
I'd think the pll-patch should look something like the
following (untested, so please test):
--------------- 8< -----------------
Subject: [PATCH] clk: rockchip: add new pll-type for rk3328
The rk3328's pll and clock are similar with rk3036's,
it different with pll_mode_mask,there are different
control registers bit,
so these should be independent and separate from
the series of rk3328s.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
drivers/clk/rockchip/clk-pll.c | 18 ++++++++++++++----
drivers/clk/rockchip/clk.h | 1 +
2 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/rockchip/clk-pll.c b/drivers/clk/rockchip/clk-pll.c
index 6ed6057..99ce483 100644
--- a/drivers/clk/rockchip/clk-pll.c
+++ b/drivers/clk/rockchip/clk-pll.c
@@ -29,6 +29,7 @@
#define PLL_MODE_SLOW 0x0
#define PLL_MODE_NORM 0x1
#define PLL_MODE_DEEP 0x2
+#define PLL_RK3328_MODE_MASK 0x1
struct rockchip_clk_pll {
struct clk_hw hw;
@@ -848,8 +849,9 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
struct clk *pll_clk, *mux_clk;
char pll_name[20];
- if (num_parents != 2) {
- pr_err("%s: needs two parent clocks\n", __func__);
+ if ((pll_type != pll_rk3328 && num_parents != 2) ||
+ (pll_type == pll_rk3328 && num_parents != 1)) {
+ pr_err("%s: missing parent clocks\n", __func__);
return ERR_PTR(-EINVAL);
}
@@ -865,13 +867,17 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
pll_mux = &pll->pll_mux;
pll_mux->reg = ctx->reg_base + mode_offset;
pll_mux->shift = mode_shift;
- pll_mux->mask = PLL_MODE_MASK;
+ if (pll_type == pll_rk3328)
+ pll_mux->mask = PLL_RK3328_MODE_MASK;
+ else
+ pll_mux->mask = PLL_MODE_MASK;
pll_mux->flags = 0;
pll_mux->lock = &ctx->lock;
pll_mux->hw.init = &init;
if (pll_type == pll_rk3036 ||
pll_type == pll_rk3066 ||
+ pll_type == pll_rk3328 ||
pll_type == pll_rk3399)
pll_mux->flags |= CLK_MUX_HIWORD_MASK;
@@ -884,7 +890,10 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
init.flags = CLK_SET_RATE_PARENT;
init.ops = pll->pll_mux_ops;
init.parent_names = pll_parents;
- init.num_parents = ARRAY_SIZE(pll_parents);
+ if (pll_type == pll_rk3328)
+ init.num_parents = 2;
+ else
+ init.num_parents = ARRAY_SIZE(pll_parents);
mux_clk = clk_register(NULL, &pll_mux->hw);
if (IS_ERR(mux_clk))
@@ -918,6 +927,7 @@ struct clk *rockchip_clk_register_pll(struct rockchip_clk_provider *ctx,
switch (pll_type) {
case pll_rk3036:
+ case pll_rk3328:
if (!pll->rate_table || IS_ERR(ctx->grf))
init.ops = &rockchip_rk3036_pll_clk_norate_ops;
else
diff --git a/drivers/clk/rockchip/clk.h b/drivers/clk/rockchip/clk.h
index d67eecc..06acb7e 100644
--- a/drivers/clk/rockchip/clk.h
+++ b/drivers/clk/rockchip/clk.h
@@ -130,6 +130,7 @@ struct clk;
enum rockchip_pll_type {
pll_rk3036,
pll_rk3066,
+ pll_rk3328,
pll_rk3399,
};
--
2.10.2
--------------- 8< -----------------
^ permalink raw reply related
* [PATCH] adc: add adc driver for Hisilicon BVT SOCs
From: Allen Liu @ 2016-12-24 1:54 UTC (permalink / raw)
To: jic23-DgEjT+Ai2ygdnm+yROfE0A, knaack.h-Mmb7MZpHnFY,
lars-Qo5EllUWu/uELgA04lAiVw, pmeerw-jW+XmwGofnusTnJN9+BGXg,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8
Cc: akinobu.mita-Re5JQEeQqe8AvxtiuMwx3w,
ludovic.desroches-AIFe0yeh4nAAvxtiuMwx3w,
krzk-DgEjT+Ai2ygdnm+yROfE0A, vilhelm.gray-Re5JQEeQqe8AvxtiuMwx3w,
ksenija.stanojevic-Re5JQEeQqe8AvxtiuMwx3w,
zhiyong.tao-NuS5LvNUpcJWk0Htik3J/w,
daniel.baluta-ral2JQCrhuEAvxtiuMwx3w,
leonard.crestez-ral2JQCrhuEAvxtiuMwx3w,
ray.jui-dY08KVG/lbpWk0Htik3J/w,
raveendra.padasalagi-dY08KVG/lbpWk0Htik3J/w,
mranostay-Re5JQEeQqe8AvxtiuMwx3w,
amsfield22-Re5JQEeQqe8AvxtiuMwx3w,
linux-iio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q,
kevin.lixu-C8/M+/jPZTeaMJb+Lgu22Q,
liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q
Add ADC driver for the ADC controller found on HiSilicon BVT SOCs, like Hi3516CV300, etc.
The ADC controller is primarily in charge of detecting voltage.
Reviewed-by: Jiancheng Xue <xuejiancheng-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
Signed-off-by: Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
---
.../devicetree/bindings/iio/adc/hibvt-lsadc.txt | 26 ++
drivers/iio/adc/Kconfig | 10 +
drivers/iio/adc/Makefile | 1 +
drivers/iio/adc/hibvt_lsadc.c | 344 +++++++++++++++++++++
4 files changed, 381 insertions(+)
create mode 100644 Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
create mode 100644 drivers/iio/adc/hibvt_lsadc.c
diff --git a/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
new file mode 100644
index 0000000..63de46e
--- /dev/null
+++ b/Documentation/devicetree/bindings/iio/adc/hibvt-lsadc.txt
@@ -0,0 +1,26 @@
+Hisilicon BVT Low Speed (LS) A/D Converter bindings
+
+Required properties:
+- compatible: should be "hisilicon,<name>-lsadc"
+ - "hisilicon,hibvt-lsadc": for hi3516cv300
+
+- reg: physical base address of the controller and length of memory mapped
+ region.
+- interrupts: The interrupt number to the cpu. The interrupt specifier format
+ depends on the interrupt controller.
+- #io-channel-cells: Should be 1, see ../iio-bindings.txt
+
+Optional properties:
+- resets: Must contain an entry for each entry in reset-names if need support
+ this option. See ../reset/reset.txt for details.
+- reset-names: Must include the name "saradc-apb".
+
+Example:
+ lsadc: hibvt-lsadc@120e0000 {
+ compatible = "hisilicon,hibvt-lsadc";
+ reg = <0x120e0000 0x1000>;
+ interrupts = <19>;
+ resets = <&crg 0x7c 3>;
+ reset-names = "lsadc-crg";
+ status = "disabled";
+ };
diff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig
index 99c0514..0443f51 100644
--- a/drivers/iio/adc/Kconfig
+++ b/drivers/iio/adc/Kconfig
@@ -225,6 +225,16 @@ config HI8435
This driver can also be built as a module. If so, the module will be
called hi8435.
+config HIBVT_LSADC
+ tristate "HIBVT LSADC driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ help
+ Say yes here to build support for the LSADC found in SoCs from
+ hisilicon BVT chip.
+
+ To compile this driver as a module, choose M here: the
+ module will be called hibvt_lsadc.
+
config INA2XX_ADC
tristate "Texas Instruments INA2xx Power Monitors IIO driver"
depends on I2C && !SENSORS_INA2XX
diff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile
index 7a40c04..6554d92 100644
--- a/drivers/iio/adc/Makefile
+++ b/drivers/iio/adc/Makefile
@@ -23,6 +23,7 @@ obj-$(CONFIG_DA9150_GPADC) += da9150-gpadc.o
obj-$(CONFIG_EXYNOS_ADC) += exynos_adc.o
obj-$(CONFIG_FSL_MX25_ADC) += fsl-imx25-gcq.o
obj-$(CONFIG_HI8435) += hi8435.o
+obj-$(CONFIG_HIBVT_LSADC) += hibvt_lsadc.o
obj-$(CONFIG_IMX7D_ADC) += imx7d_adc.o
obj-$(CONFIG_INA2XX_ADC) += ina2xx-adc.o
obj-$(CONFIG_LP8788_ADC) += lp8788_adc.o
diff --git a/drivers/iio/adc/hibvt_lsadc.c b/drivers/iio/adc/hibvt_lsadc.c
new file mode 100644
index 0000000..a20afe8
--- /dev/null
+++ b/drivers/iio/adc/hibvt_lsadc.c
@@ -0,0 +1,344 @@
+/*
+ * Hisilicon BVT Low Speed (LS) A/D Converter
+ * Copyright (C) 2016 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+#include <linux/reset.h>
+#include <linux/regulator/consumer.h>
+#include <linux/iio/iio.h>
+
+/* hisilicon bvt adc registers definitions */
+#define LSADC_CONFIG 0x00
+#define CONFIG_DEGLITCH BIT(17)
+#define CONFIG_RESET BIT(15)
+#define CONFIG_POWERDOWN BIT(14)
+#define CONFIG_MODE BIT(13)
+#define CONFIG_CHC_VALID BIT(10)
+#define CONFIG_CHB_VALID BIT(9)
+#define CONFIG_CHA_VALID BIT(8)
+
+#define LSADC_TIMESCAN 0x08
+#define LSADC_INTEN 0x10
+#define LSADC_INTSTATUS 0x14
+#define LSADC_INTCLR 0x18
+#define LSADC_START 0x1C
+#define LSADC_STOP 0x20
+#define LSADC_ACTBIT 0x24
+#define LSADC_CHNDATA 0x2C
+
+#define ADC_CON_EN (1u << 0)
+#define ADC_CON_DEN (0u << 0)
+
+#define ADC_NUM_BITS 10
+
+/* fix clk:3000000, default tscan set 10ms */
+#define DEF_ADC_TSCAN_MS (10*3000)
+
+#define LSADC_CHN_MASK 0x7
+
+#define LSADC_TIMEOUT msecs_to_jiffies(100)
+
+/* default voltage scale for every channel <mv> */
+static int g_voltage[] = {
+ 3300, 3300, 3300
+};
+
+struct hibvt_lsadc {
+ void __iomem *regs;
+ struct completion completion;
+ struct reset_control *reset;
+ const struct hibvt_lsadc_data *data;
+ unsigned int cur_chn;
+ unsigned int value;
+};
+
+struct hibvt_lsadc_data {
+ int num_bits;
+ const struct iio_chan_spec *channels;
+ int num_channels;
+
+ void (*clear_irq)(struct hibvt_lsadc *info, int mask);
+ void (*start_conv)(struct hibvt_lsadc *info);
+ void (*stop_conv)(struct hibvt_lsadc *info);
+};
+
+static int hibvt_lsadc_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2, long mask)
+{
+ struct hibvt_lsadc *info = iio_priv(indio_dev);
+
+ switch (mask) {
+ case IIO_CHAN_INFO_RAW:
+ mutex_lock(&indio_dev->mlock);
+
+ reinit_completion(&info->completion);
+
+ /* Select the channel to be used */
+ info->cur_chn = chan->channel;
+
+ if (info->data->start_conv)
+ info->data->start_conv(info);
+
+ if (!wait_for_completion_timeout(&info->completion,
+ LSADC_TIMEOUT)) {
+ if (info->data->stop_conv)
+ info->data->stop_conv(info);
+ mutex_unlock(&indio_dev->mlock);
+ return -ETIMEDOUT;
+ }
+
+ *val = info->value;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case IIO_CHAN_INFO_SCALE:
+ *val = g_voltage[chan->channel];
+ *val2 = info->data->num_bits;
+ return IIO_VAL_FRACTIONAL_LOG2;
+ default:
+ return -EINVAL;
+ }
+}
+
+static irqreturn_t hibvt_lsadc_isr(int irq, void *dev_id)
+{
+ struct hibvt_lsadc *info = (struct hibvt_lsadc *)dev_id;
+ int mask;
+
+ mask = readl(info->regs + LSADC_INTSTATUS);
+ mask &= LSADC_CHN_MASK;
+
+ /* Clear irq */
+ if (info->data->clear_irq)
+ info->data->clear_irq(info, mask);
+
+ /* Read value */
+ info->value = readl(info->regs + LSADC_CHNDATA + (info->cur_chn << 2));
+ info->value &= GENMASK(info->data->num_bits - 1, 0);
+
+ /* stop adc */
+ if (info->data->stop_conv)
+ info->data->stop_conv(info);
+
+ complete(&info->completion);
+
+ return IRQ_HANDLED;
+}
+
+static const struct iio_info hibvt_lsadc_iio_info = {
+ .read_raw = hibvt_lsadc_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+#define ADC_CHANNEL(_index, _id) { \
+ .type = IIO_VOLTAGE, \
+ .indexed = 1, \
+ .channel = _index, \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_SCALE), \
+ .datasheet_name = _id, \
+}
+
+static const struct iio_chan_spec hibvt_lsadc_iio_channels[] = {
+ ADC_CHANNEL(0, "adc0"),
+ ADC_CHANNEL(1, "adc1"),
+ ADC_CHANNEL(2, "adc2"),
+};
+
+static void hibvt_lsadc_clear_irq(struct hibvt_lsadc *info, int mask)
+{
+ writel(mask, info->regs + LSADC_INTCLR);
+}
+
+static void hibvt_lsadc_start_conv(struct hibvt_lsadc *info)
+{
+ unsigned int con;
+
+ /* set number bit */
+ con = GENMASK(info->data->num_bits - 1, 0);
+ writel(con, (info->regs + LSADC_ACTBIT));
+
+ /* config */
+ con = readl(info->regs + LSADC_CONFIG);
+ con &= ~CONFIG_RESET;
+ con |= (CONFIG_POWERDOWN | CONFIG_DEGLITCH | CONFIG_MODE);
+ con &= ~(CONFIG_CHA_VALID | CONFIG_CHB_VALID | CONFIG_CHC_VALID);
+ con |= (CONFIG_CHA_VALID << info->cur_chn);
+ writel(con, (info->regs + LSADC_CONFIG));
+
+ /* set timescan */
+ writel(DEF_ADC_TSCAN_MS, (info->regs + LSADC_TIMESCAN));
+
+ /* clear interrupt */
+ writel(LSADC_CHN_MASK, info->regs + LSADC_INTCLR);
+
+ /* enable interrupt */
+ writel(ADC_CON_EN, (info->regs + LSADC_INTEN));
+
+ /* start scan */
+ writel(ADC_CON_EN, (info->regs + LSADC_START));
+}
+
+static void hibvt_lsadc_stop_conv(struct hibvt_lsadc *info)
+{
+ /* reset the timescan */
+ writel(ADC_CON_DEN, (info->regs + LSADC_TIMESCAN));
+
+ /* disable interrupt */
+ writel(ADC_CON_DEN, (info->regs + LSADC_INTEN));
+
+ /* stop scan */
+ writel(ADC_CON_EN, (info->regs + LSADC_STOP));
+}
+
+static const struct hibvt_lsadc_data lsadc_data = {
+ .num_bits = ADC_NUM_BITS,
+ .channels = hibvt_lsadc_iio_channels,
+ .num_channels = ARRAY_SIZE(hibvt_lsadc_iio_channels),
+
+ .clear_irq = hibvt_lsadc_clear_irq,
+ .start_conv = hibvt_lsadc_start_conv,
+ .stop_conv = hibvt_lsadc_stop_conv,
+};
+
+static const struct of_device_id hibvt_lsadc_match[] = {
+ {
+ .compatible = "hisilicon,hibvt-lsadc",
+ .data = &lsadc_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, hibvt_lsadc_match);
+
+/**
+ * Reset LSADC Controller.
+ */
+static void hibvt_lsadc_reset_controller(struct reset_control *reset)
+{
+ reset_control_assert(reset);
+ usleep_range(10, 20);
+ reset_control_deassert(reset);
+}
+
+static int hibvt_lsadc_probe(struct platform_device *pdev)
+{
+ struct hibvt_lsadc *info = NULL;
+ struct device_node *np = pdev->dev.of_node;
+ struct iio_dev *indio_dev = NULL;
+ struct resource *mem;
+ const struct of_device_id *match;
+ int ret;
+ int irq;
+
+ if (!np)
+ return -ENODEV;
+
+ indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
+ if (!indio_dev) {
+ dev_err(&pdev->dev, "failed allocating iio device\n");
+ return -ENOMEM;
+ }
+ info = iio_priv(indio_dev);
+
+ match = of_match_device(hibvt_lsadc_match, &pdev->dev);
+ info->data = match->data;
+
+ mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ info->regs = devm_ioremap_resource(&pdev->dev, mem);
+ if (IS_ERR(info->regs))
+ return PTR_ERR(info->regs);
+
+ /*
+ * The reset should be an optional property, as it should work
+ * with old devicetrees as well
+ */
+ info->reset = devm_reset_control_get(&pdev->dev, "lsadc-crg");
+ if (IS_ERR(info->reset)) {
+ ret = PTR_ERR(info->reset);
+ if (ret != -ENOENT)
+ return ret;
+
+ dev_dbg(&pdev->dev, "no reset control found\n");
+ info->reset = NULL;
+ }
+
+ init_completion(&info->completion);
+
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ dev_err(&pdev->dev, "no irq resource?\n");
+ return irq;
+ }
+
+ ret = devm_request_irq(&pdev->dev, irq, hibvt_lsadc_isr,
+ 0, dev_name(&pdev->dev), info);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed requesting irq %d\n", irq);
+ return ret;
+ }
+
+ if (info->reset)
+ hibvt_lsadc_reset_controller(info->reset);
+
+ platform_set_drvdata(pdev, indio_dev);
+
+ indio_dev->name = dev_name(&pdev->dev);
+ indio_dev->dev.parent = &pdev->dev;
+ indio_dev->dev.of_node = pdev->dev.of_node;
+ indio_dev->info = &hibvt_lsadc_iio_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+
+ indio_dev->channels = info->data->channels;
+ indio_dev->num_channels = info->data->num_channels;
+
+ ret = iio_device_register(indio_dev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "failed register iio device\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int hibvt_lsadc_remove(struct platform_device *pdev)
+{
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+static struct platform_driver hibvt_lsadc_driver = {
+ .probe = hibvt_lsadc_probe,
+ .remove = hibvt_lsadc_remove,
+ .driver = {
+ .name = "hibvt-lsadc",
+ .of_match_table = hibvt_lsadc_match,
+ },
+};
+
+module_platform_driver(hibvt_lsadc_driver);
+
+MODULE_AUTHOR("Allen Liu <liurenzhong-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>");
+MODULE_DESCRIPTION("hisilicon BVT LSADC driver");
+MODULE_LICENSE("GPL v2");
--
2.1.4
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC PATCH v2 4/4] hwmon: adc128d818: Support operation modes 1-3
From: Alexander Koch @ 2016-12-23 22:12 UTC (permalink / raw)
To: linux-kernel, linux-hwmon, devicetree
Cc: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Jiri Kosina, Alexander Koch
In-Reply-To: <20161223221205.8825-1-mail@alexanderkoch.net>
Add support for operation modes 1-3 of the ADC128D818 (see datasheet sec.
8.4.1). These differ in the number and type of the available input signals,
requiring the driver to selectively hide sysfs nodes according to the
operation mode configured via devicetree.
Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
---
drivers/hwmon/adc128d818.c | 120 ++++++++++++++++++++++++++++++---------------
1 file changed, 80 insertions(+), 40 deletions(-)
diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c
index cbb3bc5e5229..46c9fc9f1be2 100644
--- a/drivers/hwmon/adc128d818.c
+++ b/drivers/hwmon/adc128d818.c
@@ -59,6 +59,9 @@ static const unsigned short normal_i2c[] = {
#define ADC128_REG_MAN_ID 0x3e
#define ADC128_REG_DEV_ID 0x3f
+/* Voltage inputs visible per operation mode */
+static const u8 num_inputs[] = { 7, 8, 4, 6 };
+
struct adc128_data {
struct i2c_client *client;
struct regulator *regulator;
@@ -68,7 +71,7 @@ struct adc128_data {
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
- u16 in[3][7]; /* Register value, normalized to 12 bit
+ u16 in[3][8]; /* Register value, normalized to 12 bit
* 0: input voltage
* 1: min limit
* 2: max limit
@@ -89,7 +92,7 @@ static struct adc128_data *adc128_update_device(struct device *dev)
mutex_lock(&data->update_lock);
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
- for (i = 0; i < 7; i++) {
+ for (i = 0; i < num_inputs[data->mode]; i++) {
rv = i2c_smbus_read_word_swapped(client,
ADC128_REG_IN(i));
if (rv < 0)
@@ -109,20 +112,25 @@ static struct adc128_data *adc128_update_device(struct device *dev)
data->in[2][i] = rv << 4;
}
- rv = i2c_smbus_read_word_swapped(client, ADC128_REG_TEMP);
- if (rv < 0)
- goto abort;
- data->temp[0] = rv >> 7;
+ if (data->mode != 1) {
+ rv = i2c_smbus_read_word_swapped(client,
+ ADC128_REG_TEMP);
+ if (rv < 0)
+ goto abort;
+ data->temp[0] = rv >> 7;
- rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_MAX);
- if (rv < 0)
- goto abort;
- data->temp[1] = rv << 1;
+ rv = i2c_smbus_read_byte_data(client,
+ ADC128_REG_TEMP_MAX);
+ if (rv < 0)
+ goto abort;
+ data->temp[1] = rv << 1;
- rv = i2c_smbus_read_byte_data(client, ADC128_REG_TEMP_HYST);
- if (rv < 0)
- goto abort;
- data->temp[2] = rv << 1;
+ rv = i2c_smbus_read_byte_data(client,
+ ADC128_REG_TEMP_HYST);
+ if (rv < 0)
+ goto abort;
+ data->temp[2] = rv << 1;
+ }
rv = i2c_smbus_read_byte_data(client, ADC128_REG_ALARM);
if (rv < 0)
@@ -242,6 +250,25 @@ static ssize_t adc128_show_alarm(struct device *dev,
return sprintf(buf, "%u\n", !!(alarms & mask));
}
+static umode_t adc128_is_visible(struct kobject *kobj,
+ struct attribute *attr, int index)
+{
+ struct device *dev = container_of(kobj, struct device, kobj);
+ struct adc128_data *data = dev_get_drvdata(dev);
+
+ if (index < 8 * 4) {
+ /* Voltage, visible according to num_inputs[] */
+ if (index >= num_inputs[data->mode] * 4)
+ return 0;
+ } else {
+ /* Temperature, visible if not in mode 1 */
+ if (data->mode == 1)
+ return 0;
+ }
+
+ return attr->mode;
+}
+
static SENSOR_DEVICE_ATTR_2(in0_input, 0444, adc128_show_in, NULL, 0, 0);
static SENSOR_DEVICE_ATTR_2(in0_min, 0644, adc128_show_in, adc128_set_in, 0, 1);
static SENSOR_DEVICE_ATTR_2(in0_max, 0644, adc128_show_in, adc128_set_in, 0, 2);
@@ -270,6 +297,10 @@ static SENSOR_DEVICE_ATTR_2(in6_input, 0444, adc128_show_in, NULL, 6, 0);
static SENSOR_DEVICE_ATTR_2(in6_min, 0644, adc128_show_in, adc128_set_in, 6, 1);
static SENSOR_DEVICE_ATTR_2(in6_max, 0644, adc128_show_in, adc128_set_in, 6, 2);
+static SENSOR_DEVICE_ATTR_2(in7_input, 0444, adc128_show_in, NULL, 7, 0);
+static SENSOR_DEVICE_ATTR_2(in7_min, 0644, adc128_show_in, adc128_set_in, 7, 1);
+static SENSOR_DEVICE_ATTR_2(in7_max, 0644, adc128_show_in, adc128_set_in, 7, 2);
+
static SENSOR_DEVICE_ATTR(temp1_input, 0444, adc128_show_temp, NULL, 0);
static SENSOR_DEVICE_ATTR(temp1_max, 0644,
adc128_show_temp, adc128_set_temp, 1);
@@ -283,44 +314,54 @@ static SENSOR_DEVICE_ATTR(in3_alarm, 0444, adc128_show_alarm, NULL, 3);
static SENSOR_DEVICE_ATTR(in4_alarm, 0444, adc128_show_alarm, NULL, 4);
static SENSOR_DEVICE_ATTR(in5_alarm, 0444, adc128_show_alarm, NULL, 5);
static SENSOR_DEVICE_ATTR(in6_alarm, 0444, adc128_show_alarm, NULL, 6);
+static SENSOR_DEVICE_ATTR(in7_alarm, 0444, adc128_show_alarm, NULL, 7);
static SENSOR_DEVICE_ATTR(temp1_max_alarm, 0444, adc128_show_alarm, NULL, 7);
static struct attribute *adc128_attrs[] = {
- &sensor_dev_attr_in0_min.dev_attr.attr,
- &sensor_dev_attr_in1_min.dev_attr.attr,
- &sensor_dev_attr_in2_min.dev_attr.attr,
- &sensor_dev_attr_in3_min.dev_attr.attr,
- &sensor_dev_attr_in4_min.dev_attr.attr,
- &sensor_dev_attr_in5_min.dev_attr.attr,
- &sensor_dev_attr_in6_min.dev_attr.attr,
- &sensor_dev_attr_in0_max.dev_attr.attr,
- &sensor_dev_attr_in1_max.dev_attr.attr,
- &sensor_dev_attr_in2_max.dev_attr.attr,
- &sensor_dev_attr_in3_max.dev_attr.attr,
- &sensor_dev_attr_in4_max.dev_attr.attr,
- &sensor_dev_attr_in5_max.dev_attr.attr,
- &sensor_dev_attr_in6_max.dev_attr.attr,
+ &sensor_dev_attr_in0_alarm.dev_attr.attr,
&sensor_dev_attr_in0_input.dev_attr.attr,
+ &sensor_dev_attr_in0_max.dev_attr.attr,
+ &sensor_dev_attr_in0_min.dev_attr.attr,
+ &sensor_dev_attr_in1_alarm.dev_attr.attr,
&sensor_dev_attr_in1_input.dev_attr.attr,
+ &sensor_dev_attr_in1_max.dev_attr.attr,
+ &sensor_dev_attr_in1_min.dev_attr.attr,
+ &sensor_dev_attr_in2_alarm.dev_attr.attr,
&sensor_dev_attr_in2_input.dev_attr.attr,
+ &sensor_dev_attr_in2_max.dev_attr.attr,
+ &sensor_dev_attr_in2_min.dev_attr.attr,
+ &sensor_dev_attr_in3_alarm.dev_attr.attr,
&sensor_dev_attr_in3_input.dev_attr.attr,
+ &sensor_dev_attr_in3_max.dev_attr.attr,
+ &sensor_dev_attr_in3_min.dev_attr.attr,
+ &sensor_dev_attr_in4_alarm.dev_attr.attr,
&sensor_dev_attr_in4_input.dev_attr.attr,
+ &sensor_dev_attr_in4_max.dev_attr.attr,
+ &sensor_dev_attr_in4_min.dev_attr.attr,
+ &sensor_dev_attr_in5_alarm.dev_attr.attr,
&sensor_dev_attr_in5_input.dev_attr.attr,
+ &sensor_dev_attr_in5_max.dev_attr.attr,
+ &sensor_dev_attr_in5_min.dev_attr.attr,
+ &sensor_dev_attr_in6_alarm.dev_attr.attr,
&sensor_dev_attr_in6_input.dev_attr.attr,
+ &sensor_dev_attr_in6_max.dev_attr.attr,
+ &sensor_dev_attr_in6_min.dev_attr.attr,
+ &sensor_dev_attr_in7_alarm.dev_attr.attr,
+ &sensor_dev_attr_in7_input.dev_attr.attr,
+ &sensor_dev_attr_in7_max.dev_attr.attr,
+ &sensor_dev_attr_in7_min.dev_attr.attr,
&sensor_dev_attr_temp1_input.dev_attr.attr,
&sensor_dev_attr_temp1_max.dev_attr.attr,
- &sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
- &sensor_dev_attr_in0_alarm.dev_attr.attr,
- &sensor_dev_attr_in1_alarm.dev_attr.attr,
- &sensor_dev_attr_in2_alarm.dev_attr.attr,
- &sensor_dev_attr_in3_alarm.dev_attr.attr,
- &sensor_dev_attr_in4_alarm.dev_attr.attr,
- &sensor_dev_attr_in5_alarm.dev_attr.attr,
- &sensor_dev_attr_in6_alarm.dev_attr.attr,
&sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
+ &sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
NULL
};
-ATTRIBUTE_GROUPS(adc128);
+
+static struct attribute_group adc128_group = {
+ .attrs = adc128_attrs,
+ .is_visible = adc128_is_visible,
+};
+__ATTRIBUTE_GROUPS(adc128);
static int adc128_detect(struct i2c_client *client, struct i2c_board_info *info)
{
@@ -425,9 +466,8 @@ static int adc128_probe(struct i2c_client *client,
/* Operation mode is optional and defaults to mode 0 */
if (of_property_read_u8(dev->of_node, "mode", &data->mode) == 0) {
- /* Currently only mode 0 supported */
- if (data->mode != 0) {
- dev_err(dev, "unsupported operation mode %d",
+ if (data->mode > 3) {
+ dev_err(dev, "invalid operation mode %d",
data->mode);
err = -EINVAL;
goto error;
--
2.11.0
^ permalink raw reply related
* [RFC PATCH v2 3/4] hwmon: adc128d818: Trivial code style fixup
From: Alexander Koch @ 2016-12-23 22:12 UTC (permalink / raw)
To: linux-kernel, linux-hwmon, devicetree
Cc: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Jiri Kosina, Alexander Koch
In-Reply-To: <20161223221205.8825-1-mail@alexanderkoch.net>
Replace sysfs symbolic file permissions, e.g. 'S_IRUGO', by octal
permissions. This fixes checkpatch.pl warnings.
Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
---
drivers/hwmon/adc128d818.c | 99 ++++++++++++++++++----------------------------
1 file changed, 39 insertions(+), 60 deletions(-)
diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c
index 8667f454ea11..cbb3bc5e5229 100644
--- a/drivers/hwmon/adc128d818.c
+++ b/drivers/hwmon/adc128d818.c
@@ -242,69 +242,48 @@ static ssize_t adc128_show_alarm(struct device *dev,
return sprintf(buf, "%u\n", !!(alarms & mask));
}
-static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO,
- adc128_show_in, NULL, 0, 0);
-static SENSOR_DEVICE_ATTR_2(in0_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 0, 1);
-static SENSOR_DEVICE_ATTR_2(in0_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 0, 2);
-
-static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO,
- adc128_show_in, NULL, 1, 0);
-static SENSOR_DEVICE_ATTR_2(in1_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 1, 1);
-static SENSOR_DEVICE_ATTR_2(in1_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 1, 2);
-
-static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO,
- adc128_show_in, NULL, 2, 0);
-static SENSOR_DEVICE_ATTR_2(in2_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 2, 1);
-static SENSOR_DEVICE_ATTR_2(in2_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 2, 2);
-
-static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO,
- adc128_show_in, NULL, 3, 0);
-static SENSOR_DEVICE_ATTR_2(in3_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 3, 1);
-static SENSOR_DEVICE_ATTR_2(in3_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 3, 2);
-
-static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO,
- adc128_show_in, NULL, 4, 0);
-static SENSOR_DEVICE_ATTR_2(in4_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 4, 1);
-static SENSOR_DEVICE_ATTR_2(in4_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 4, 2);
-
-static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO,
- adc128_show_in, NULL, 5, 0);
-static SENSOR_DEVICE_ATTR_2(in5_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 5, 1);
-static SENSOR_DEVICE_ATTR_2(in5_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 5, 2);
-
-static SENSOR_DEVICE_ATTR_2(in6_input, S_IRUGO,
- adc128_show_in, NULL, 6, 0);
-static SENSOR_DEVICE_ATTR_2(in6_min, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 6, 1);
-static SENSOR_DEVICE_ATTR_2(in6_max, S_IWUSR | S_IRUGO,
- adc128_show_in, adc128_set_in, 6, 2);
-
-static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, adc128_show_temp, NULL, 0);
-static SENSOR_DEVICE_ATTR(temp1_max, S_IWUSR | S_IRUGO,
+static SENSOR_DEVICE_ATTR_2(in0_input, 0444, adc128_show_in, NULL, 0, 0);
+static SENSOR_DEVICE_ATTR_2(in0_min, 0644, adc128_show_in, adc128_set_in, 0, 1);
+static SENSOR_DEVICE_ATTR_2(in0_max, 0644, adc128_show_in, adc128_set_in, 0, 2);
+
+static SENSOR_DEVICE_ATTR_2(in1_input, 0444, adc128_show_in, NULL, 1, 0);
+static SENSOR_DEVICE_ATTR_2(in1_min, 0644, adc128_show_in, adc128_set_in, 1, 1);
+static SENSOR_DEVICE_ATTR_2(in1_max, 0644, adc128_show_in, adc128_set_in, 1, 2);
+
+static SENSOR_DEVICE_ATTR_2(in2_input, 0444, adc128_show_in, NULL, 2, 0);
+static SENSOR_DEVICE_ATTR_2(in2_min, 0644, adc128_show_in, adc128_set_in, 2, 1);
+static SENSOR_DEVICE_ATTR_2(in2_max, 0644, adc128_show_in, adc128_set_in, 2, 2);
+
+static SENSOR_DEVICE_ATTR_2(in3_input, 0444, adc128_show_in, NULL, 3, 0);
+static SENSOR_DEVICE_ATTR_2(in3_min, 0644, adc128_show_in, adc128_set_in, 3, 1);
+static SENSOR_DEVICE_ATTR_2(in3_max, 0644, adc128_show_in, adc128_set_in, 3, 2);
+
+static SENSOR_DEVICE_ATTR_2(in4_input, 0444, adc128_show_in, NULL, 4, 0);
+static SENSOR_DEVICE_ATTR_2(in4_min, 0644, adc128_show_in, adc128_set_in, 4, 1);
+static SENSOR_DEVICE_ATTR_2(in4_max, 0644, adc128_show_in, adc128_set_in, 4, 2);
+
+static SENSOR_DEVICE_ATTR_2(in5_input, 0444, adc128_show_in, NULL, 5, 0);
+static SENSOR_DEVICE_ATTR_2(in5_min, 0644, adc128_show_in, adc128_set_in, 5, 1);
+static SENSOR_DEVICE_ATTR_2(in5_max, 0644, adc128_show_in, adc128_set_in, 5, 2);
+
+static SENSOR_DEVICE_ATTR_2(in6_input, 0444, adc128_show_in, NULL, 6, 0);
+static SENSOR_DEVICE_ATTR_2(in6_min, 0644, adc128_show_in, adc128_set_in, 6, 1);
+static SENSOR_DEVICE_ATTR_2(in6_max, 0644, adc128_show_in, adc128_set_in, 6, 2);
+
+static SENSOR_DEVICE_ATTR(temp1_input, 0444, adc128_show_temp, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_max, 0644,
adc128_show_temp, adc128_set_temp, 1);
-static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IWUSR | S_IRUGO,
+static SENSOR_DEVICE_ATTR(temp1_max_hyst, 0644,
adc128_show_temp, adc128_set_temp, 2);
-static SENSOR_DEVICE_ATTR(in0_alarm, S_IRUGO, adc128_show_alarm, NULL, 0);
-static SENSOR_DEVICE_ATTR(in1_alarm, S_IRUGO, adc128_show_alarm, NULL, 1);
-static SENSOR_DEVICE_ATTR(in2_alarm, S_IRUGO, adc128_show_alarm, NULL, 2);
-static SENSOR_DEVICE_ATTR(in3_alarm, S_IRUGO, adc128_show_alarm, NULL, 3);
-static SENSOR_DEVICE_ATTR(in4_alarm, S_IRUGO, adc128_show_alarm, NULL, 4);
-static SENSOR_DEVICE_ATTR(in5_alarm, S_IRUGO, adc128_show_alarm, NULL, 5);
-static SENSOR_DEVICE_ATTR(in6_alarm, S_IRUGO, adc128_show_alarm, NULL, 6);
-static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, adc128_show_alarm, NULL, 7);
+static SENSOR_DEVICE_ATTR(in0_alarm, 0444, adc128_show_alarm, NULL, 0);
+static SENSOR_DEVICE_ATTR(in1_alarm, 0444, adc128_show_alarm, NULL, 1);
+static SENSOR_DEVICE_ATTR(in2_alarm, 0444, adc128_show_alarm, NULL, 2);
+static SENSOR_DEVICE_ATTR(in3_alarm, 0444, adc128_show_alarm, NULL, 3);
+static SENSOR_DEVICE_ATTR(in4_alarm, 0444, adc128_show_alarm, NULL, 4);
+static SENSOR_DEVICE_ATTR(in5_alarm, 0444, adc128_show_alarm, NULL, 5);
+static SENSOR_DEVICE_ATTR(in6_alarm, 0444, adc128_show_alarm, NULL, 6);
+static SENSOR_DEVICE_ATTR(temp1_max_alarm, 0444, adc128_show_alarm, NULL, 7);
static struct attribute *adc128_attrs[] = {
&sensor_dev_attr_in0_min.dev_attr.attr,
--
2.11.0
^ permalink raw reply related
* [RFC PATCH v2 2/4] hwmon: adc128d818: Implement mode selection via dt
From: Alexander Koch @ 2016-12-23 22:12 UTC (permalink / raw)
To: linux-kernel, linux-hwmon, devicetree
Cc: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Jiri Kosina, Alexander Koch
In-Reply-To: <20161223221205.8825-1-mail@alexanderkoch.net>
Implement operation mode selection using the optional 'mode' devicetree
property (see [1]). The ADC128D818 supports four operation modes differing
in the number and type of input readings (see datasheet, sec. 8.4.1), of
which mode 0 is the default.
We only add handling of the 'mode' property here, the driver still supports
nothing else than the default mode 0.
[1] Documentation/devicetree/bindings/hwmon/adc128d818.txt
Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
---
drivers/hwmon/adc128d818.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/hwmon/adc128d818.c b/drivers/hwmon/adc128d818.c
index ad2b47e40345..8667f454ea11 100644
--- a/drivers/hwmon/adc128d818.c
+++ b/drivers/hwmon/adc128d818.c
@@ -28,6 +28,7 @@
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
#include <linux/bitops.h>
+#include <linux/of.h>
/* Addresses to scan
* The chip also supports addresses 0x35..0x37. Don't scan those addresses
@@ -63,6 +64,7 @@ struct adc128_data {
struct regulator *regulator;
int vref; /* Reference voltage in mV */
struct mutex update_lock;
+ u8 mode; /* Operation mode */
bool valid; /* true if following fields are valid */
unsigned long last_updated; /* In jiffies */
@@ -387,6 +389,15 @@ static int adc128_init_client(struct adc128_data *data)
if (err)
return err;
+ /* Set operation mode, if non-default */
+ if (data->mode != 0) {
+ err = i2c_smbus_write_byte_data(client,
+ ADC128_REG_CONFIG_ADV,
+ data->mode << 1);
+ if (err)
+ return err;
+ }
+
/* Start monitoring */
err = i2c_smbus_write_byte_data(client, ADC128_REG_CONFIG, 0x01);
if (err)
@@ -433,6 +444,19 @@ static int adc128_probe(struct i2c_client *client,
data->vref = 2560; /* 2.56V, in mV */
}
+ /* Operation mode is optional and defaults to mode 0 */
+ if (of_property_read_u8(dev->of_node, "mode", &data->mode) == 0) {
+ /* Currently only mode 0 supported */
+ if (data->mode != 0) {
+ dev_err(dev, "unsupported operation mode %d",
+ data->mode);
+ err = -EINVAL;
+ goto error;
+ }
+ } else {
+ data->mode = 0;
+ }
+
data->client = client;
i2c_set_clientdata(client, data);
mutex_init(&data->update_lock);
--
2.11.0
^ permalink raw reply related
* [RFC PATCH v2 1/4] devicetree: hwmon: Add bindings for ADC128D818
From: Alexander Koch @ 2016-12-23 22:12 UTC (permalink / raw)
To: linux-kernel, linux-hwmon, devicetree
Cc: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Jiri Kosina, Alexander Koch
In-Reply-To: <20161223221205.8825-1-mail@alexanderkoch.net>
Add bindings documentation for the ADC128D818 driver, featuring default I2C
properties along with the optional 'mode' property for chip operation mode
selection (see datasheet, sec. 8.4.1).
Signed-off-by: Alexander Koch <mail@alexanderkoch.net>
---
.../devicetree/bindings/hwmon/adc128d818.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/hwmon/adc128d818.txt
diff --git a/Documentation/devicetree/bindings/hwmon/adc128d818.txt b/Documentation/devicetree/bindings/hwmon/adc128d818.txt
new file mode 100644
index 000000000000..5e14aa36a696
--- /dev/null
+++ b/Documentation/devicetree/bindings/hwmon/adc128d818.txt
@@ -0,0 +1,39 @@
+TI ADC128D818 ADC System Monitor With Temperature Sensor
+--------------------------------------------------------
+
+Operation modes:
+
+ - Mode 0: 7 single-ended voltage readings (IN0-IN6),
+ 1 temperature reading (internal)
+ - Mode 1: 8 single-ended voltage readings (IN0-IN7),
+ no temperature
+ - Mode 2: 4 pseudo-differential voltage readings
+ (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6),
+ 1 temperature reading (internal)
+ - Mode 3: 4 single-ended voltage readings (IN0-IN3),
+ 2 pseudo-differential voltage readings
+ (IN4-IN5, IN7-IN6),
+ 1 temperature reading (internal)
+
+If no operation mode is configured via device tree, the driver defaults
+to Mode 0.
+
+
+Required node properties:
+
+ - compatible: must be set to "ti,adc128d818"
+ - reg: I2C address of the device
+
+Optional node properties:
+
+ - mode: Operation mode (see above).
+
+
+Example (operation mode 2):
+
+ adc128d818@1d {
+ compatible = "ti,adc128d818";
+ reg = <0x1d>;
+ mode = /bits/ 8 <2>;
+ };
+
--
2.11.0
^ permalink raw reply related
* [RFC PATCH v2 0/4] hwmon: adc128d818: Support missing operation modes
From: Alexander Koch @ 2016-12-23 22:12 UTC (permalink / raw)
To: linux-kernel, linux-hwmon, devicetree
Cc: Rob Herring, Mark Rutland, Jean Delvare, Guenter Roeck,
Jiri Kosina, Alexander Koch
The ADC128D818 offers four different chip operation modes which vary in the
number and measurement types of the available input signals (see datasheet
sec. 8.4.1).
The current version of the driver only supports the default chip operation
mode (mode 0), providing seven analog values and a temperature reading.
This patch series adds support for operation modes 1-3, selectable through
the device tree attribute 'mode':
adc1: adc128d818@1d {
compatible = "ti,adc128d818";
reg = <0x1d>;
mode = /bits/ 8 <1>;
};
The changes are transparent as 'mode' defaults to mode 0 which yields the
previous behaviour.
Changes from v1:
- Add bindings document as first patch
- Preserve logical atomicity of code changes
- Improve sysfs device node handling (use is_visible() instead of
duplicate attribute list)
- Add trivial code refactoring stage for checkpatch.pl to succeed
Alexander Koch (4):
devicetree: hwmon: Add bindings for ADC128D818
hwmon: adc128d818: Implement mode selection via dt
hwmon: adc128d818: Trivial code style fixup
hwmon: adc128d818: Support operation modes 1-3
.../devicetree/bindings/hwmon/adc128d818.txt | 39 ++++
drivers/hwmon/adc128d818.c | 237 ++++++++++++---------
2 files changed, 179 insertions(+), 97 deletions(-)
create mode 100644 Documentation/devicetree/bindings/hwmon/adc128d818.txt
--
2.11.0
^ permalink raw reply
* Re: [RFC PATCHv2 2/4] clk: mdm9615: Add EBI2 clock
From: Neil Armstrong @ 2016-12-23 19:50 UTC (permalink / raw)
To: Zoran Markovic, linux-kernel
Cc: Andy Gross, David Brown, Michael Turquette, Stephen Boyd,
Rob Herring, Mark Rutland, linux-arm-msm, linux-soc, linux-clk,
devicetree
In-Reply-To: <1482468884-31027-1-git-send-email-zmarkovic@sierrawireless.com>
Le 23/12/2016 05:54, Zoran Markovic a écrit :
> Add definition of EBI2 clock used by MDM9615 NAND controller.
>
> Cc: Andy Gross <andy.gross@linaro.org>
> Cc: David Brown <david.brown@linaro.org>
> Cc: Michael Turquette <mturquette@baylibre.com>
> Cc: Stephen Boyd <sboyd@codeaurora.org>
> Cc: Rob Herring <robh+dt@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: Neil Armstrong <narmstrong@baylibre.com>
> Cc: linux-arm-msm@vger.kernel.org
> Cc: linux-soc@vger.kernel.org
> Cc: linux-clk@vger.kernel.org
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Zoran Markovic <zmarkovic@sierrawireless.com>
> ---
> drivers/clk/qcom/gcc-mdm9615.c | 30 ++++++++++++++++++++++++++
> include/dt-bindings/clock/qcom,gcc-mdm9615.h | 3 +++
> 2 files changed, 33 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
> index 581a17f..e9e98b1 100644
> --- a/drivers/clk/qcom/gcc-mdm9615.c
> +++ b/drivers/clk/qcom/gcc-mdm9615.c
> @@ -1563,6 +1563,34 @@ enum {
> },
> };
>
> +static struct clk_branch ebi2_clk = {
> + .hwcg_reg = 0x2664,
> + .hwcg_bit = 6,
> + .halt_reg = 0x2fcc,
> + .halt_bit = 23,
> + .clkr = {
> + .enable_reg = 0x2664,
> + .enable_mask = BIT(6) | BIT(4),
> + .hw.init = &(struct clk_init_data){
> + .name = "ebi2_clk",
> + .ops = &clk_branch_ops,
> + },
> + },
> +};
> +
> +static struct clk_branch ebi2_aon_clk = {
> + .halt_reg = 0x2fcc,
> + .halt_bit = 23,
> + .clkr = {
> + .enable_reg = 0x2664,
> + .enable_mask = BIT(8),
> + .hw.init = &(struct clk_init_data){
> + .name = "ebi2_aon_clk",
> + .ops = &clk_branch_ops,
> + },
> + },
> +};
> +
> static struct clk_hw *gcc_mdm9615_hws[] = {
> &cxo.hw,
> };
> @@ -1637,6 +1665,8 @@ enum {
> [PMIC_ARB1_H_CLK] = &pmic_arb1_h_clk.clkr,
> [PMIC_SSBI2_CLK] = &pmic_ssbi2_clk.clkr,
> [RPM_MSG_RAM_H_CLK] = &rpm_msg_ram_h_clk.clkr,
> + [EBI2_CLK] = &ebi2_clk.clkr,
> + [EBI2_AON_CLK] = &ebi2_aon_clk.clkr,
> };
>
> static const struct qcom_reset_map gcc_mdm9615_resets[] = {
> diff --git a/include/dt-bindings/clock/qcom,gcc-mdm9615.h b/include/dt-bindings/clock/qcom,gcc-mdm9615.h
> index 9ab2c40..57cdca6 100644
> --- a/include/dt-bindings/clock/qcom,gcc-mdm9615.h
> +++ b/include/dt-bindings/clock/qcom,gcc-mdm9615.h
> @@ -323,5 +323,8 @@
> #define CE3_H_CLK 305
> #define USB_HS1_SYSTEM_CLK_SRC 306
> #define USB_HS1_SYSTEM_CLK 307
> +#define EBI2_CLK 308
> +#define EBI2_AON_CLK 309
> +
>
> #endif
>
Hi Zoran,
Thanks for this patch, we did not found the definition for these clocks at all !
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Neil
^ permalink raw reply
* Re: [PATCH 1/1] ARM64: dts: meson-gxbb-odroidc2: linux,usable-memory
From: Neil Armstrong @ 2016-12-23 19:48 UTC (permalink / raw)
To: Heinrich Schuchardt, Rob Herring, Mark Rutland, Catalin Marinas,
Will Deacon, Carlo Caione, Kevin Hilman
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-amlogic-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161223125213.5461-1-xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
Le 23/12/2016 13:52, Heinrich Schuchardt a écrit :
> After reading the fdt u-boot overwrites the reg property of the
> memory node with <0x0 0x0 0x0 0x78000000>.
>
> To override this setting we have to use the property
> linux,usable-memory.
>
> If the first 16MB of the 2GB physical memory are used by
> the Linux kernel oops occur on the Odroid C2.
>
> For the Odroid C2 this patch replaces
> [RFT PATCH] ARM64: dts: meson-gxbb: Add reserved memory zone and
> usable memory range
> https://lkml.org/lkml/2016/12/12/127
>
> Fixes: 855960342d1e7 ARM64: dts: amlogic: add Hardkernel ODROID-C2
> CC: Neil Armstrong <narmstrong-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> CC: Kevin Hilman <khilman-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
> Signed-off-by: Heinrich Schuchardt <xypron.glpk-Mmb7MZpHnFY@public.gmane.org>
> ---
> arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> index 238fbeacd330..82ab94417940 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> +++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
> @@ -61,7 +61,7 @@
>
> memory@0 {
> device_type = "memory";
> - reg = <0x0 0x0 0x0 0x80000000>;
> + linux,usable-memory = <0x0 0x01000000 0x0 0x7f000000>;
> };
>
> usb_otg_pwr: regulator-usb-pwrs {
>
Hi Heinrich,
Thanks a lot for testing and pushing this patch, indeed I missed this point abou u-boot overwriting reg.
I will test this next week, and hopefully get these merged.
Neil
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 1/2] mtd: spi-nor: Bindings for Rockchip serial flash controller
From: Marek Vasut @ 2016-12-23 19:00 UTC (permalink / raw)
To: Shawn Lin, David Woodhouse, Brian Norris
Cc: Cyrille Pitchen, Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner
In-Reply-To: <1481794068-241619-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
On 12/15/2016 10:27 AM, Shawn Lin wrote:
> Add binding document for the Rockchip serial flash controller.
>
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>
> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> ---
Acked-by: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
--
Best regards,
Marek Vasut
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* Re: [PATCH v4 2/2] mtd: spi-nor: add rockchip serial flash controller driver
From: Marek Vasut @ 2016-12-23 19:00 UTC (permalink / raw)
To: Shawn Lin, David Woodhouse, Brian Norris
Cc: Cyrille Pitchen, Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Heiko Stuebner
In-Reply-To: <1481794068-241619-3-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
On 12/15/2016 10:27 AM, Shawn Lin wrote:
> Add rockchip serial flash controller driver
>
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Acked-by: Marek Vasut <marek.vasut-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Thanks !
--
Best regards,
Marek Vasut
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply
* [PATCH 2/2] devicetree: add vendor prefix for Zeitec
From: Jelle van der Waa @ 2016-12-23 16:32 UTC (permalink / raw)
To: Rob Herring, Dmitry Torokhov, linux-input, devicetree; +Cc: Jelle van der Waa
In-Reply-To: <20161223163214.7716-1-jelle@vdwaa.nl>
Signed-off-by: Jelle van der Waa <jelle@vdwaa.nl>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/vendor-prefixes.txt b/Documentation/devicetree/bindings/vendor-prefixes.txt
index 16d3b5e7f5d1..a3d7608a5cb3 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.txt
+++ b/Documentation/devicetree/bindings/vendor-prefixes.txt
@@ -329,6 +329,7 @@ xes Extreme Engineering Solutions (X-ES)
xillybus Xillybus Ltd.
xlnx Xilinx
zarlink Zarlink Semiconductor
+zeitec ZEITEC Semiconductor Co., LTD.
zii Zodiac Inflight Innovations
zte ZTE Corp.
zyxel ZyXEL Communications Corp.
--
2.11.0
^ permalink raw reply related
page: next (older) | prev (newer) | latest
- recent:[subjects (threaded)|topics (new)|topics (active)]
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox