* [PATCH 0/3] Add clock and power domain DT nodes for Mediatek MT2701
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
This patch series base on v4.10-rc1, include MT2701 power domain and clock
DT nodes.
An early patch [1] which was not applied in v4.10-rc1 also included in this
patch series.
[1] https://patchwork.kernel.org/patch/9457625/
James Liao (3):
arm: dts: mt2701: Sort DT nodes by register address
arm: dts: mt2701: Add subsystem clock controller device nodes
arm: dts: mt2701: Add power domain controller device node
arch/arm/boot/dts/mt2701.dtsi | 84 +++++++++++++++++++++++++++++++++----------
1 file changed, 66 insertions(+), 18 deletions(-)
--
1.9.1
^ permalink raw reply
* [PATCH 1/3] arm: dts: mt2701: Sort DT nodes by register address
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao@mediatek.com>
This patch rearrange MT2701 DT nodes to keep them in ascending order.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 36 ++++++++++++++++++------------------
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 7eab6f4..73f4b7c 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -96,24 +96,6 @@
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
- pio: pinctrl@10005000 {
- compatible = "mediatek,mt2701-pinctrl";
- reg = <0 0x1000b000 0 0x1000>;
- mediatek,pctl-regmap = <&syscfg_pctl_a>;
- pins-are-numbered;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- syscfg_pctl_a: syscfg@10005000 {
- compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
- reg = <0 0x10005000 0 0x1000>;
- };
-
topckgen: syscon@10000000 {
compatible = "mediatek,mt2701-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
@@ -134,6 +116,24 @@
#reset-cells = <1>;
};
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt2701-pinctrl";
+ reg = <0 0x1000b000 0 0x1000>;
+ mediatek,pctl-regmap = <&syscfg_pctl_a>;
+ pins-are-numbered;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ syscfg_pctl_a: syscfg@10005000 {
+ compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
+ reg = <0 0x10005000 0 0x1000>;
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
--
1.9.1
^ permalink raw reply related
* [PATCH 2/3] arm: dts: mt2701: Add subsystem clock controller device nodes
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree, linux-arm-kernel, linux-kernel, linux-mediatek,
srv_heupstream, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao@mediatek.com>
Add MT2701 subsystem clock controllers, inlcude mmsys, imgsys,
vdecsys, hifsys, ethsys and bdpsys.
Signed-off-by: James Liao <jamesjj.liao@mediatek.com>
---
arch/arm/boot/dts/mt2701.dtsi | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 73f4b7c..150c48d 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -214,4 +214,40 @@
clock-names = "baud", "bus";
status = "disabled";
};
+
+ mmsys: syscon@14000000 {
+ compatible = "mediatek,mt2701-mmsys", "syscon";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: syscon@15000000 {
+ compatible = "mediatek,mt2701-imgsys", "syscon";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: syscon@16000000 {
+ compatible = "mediatek,mt2701-vdecsys", "syscon";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ hifsys: syscon@1a000000 {
+ compatible = "mediatek,mt2701-hifsys", "syscon";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ethsys: syscon@1b000000 {
+ compatible = "mediatek,mt2701-ethsys", "syscon";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ bdpsys: syscon@1c000000 {
+ compatible = "mediatek,mt2701-bdpsys", "syscon";
+ reg = <0 0x1c000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
--
1.9.1
^ permalink raw reply related
* [PATCH 3/3] arm: dts: mt2701: Add power domain controller device node
From: James Liao @ 2016-12-28 5:46 UTC (permalink / raw)
To: Rob Herring, Russell King, Matthias Brugger
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w, James Liao
In-Reply-To: <1482904006-44232-1-git-send-email-jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
Add power domain controller node (scpsys) for MT2701.
Signed-off-by: James Liao <jamesjj.liao-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/mt2701.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi
index 150c48d..bdf8954 100644
--- a/arch/arm/boot/dts/mt2701.dtsi
+++ b/arch/arm/boot/dts/mt2701.dtsi
@@ -13,6 +13,7 @@
*/
#include <dt-bindings/clock/mt2701-clk.h>
+#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/mt2701-resets.h>
@@ -134,6 +135,17 @@
reg = <0 0x10005000 0 0x1000>;
};
+ scpsys: scpsys@10006000 {
+ compatible = "mediatek,mt2701-scpsys", "syscon";
+ #power-domain-cells = <1>;
+ reg = <0 0x10006000 0 0x1000>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_MM_SEL>,
+ <&topckgen CLK_TOP_MFG_SEL>,
+ <&topckgen CLK_TOP_ETHIF_SEL>;
+ clock-names = "mm", "mfg", "ethif";
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt2701-wdt",
"mediatek,mt6589-wdt";
--
1.9.1
--
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^ permalink raw reply related
* [RFC PATCH 0/5] overlay: tool to convert old overlay style dts to new style
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
In response to "Subject: Re: [PATCH v11 5/7] overlay: Documentation for the
overlay sugar syntax" I suggested a tool to convert the old style of dts
overlay files to use the new syntactic sugar [1]:
>>> I can imagine some reasons to support the fully written out version,
>>> but can we document what those reasons are?
>>
>> I believe the main one is the dts files in this format out in the
>> field. Mind you, I guess we're already requiring them to tweak how
>> they declare the /plugin/ option.
>
> It might be easy to write a program that transforms the expanded
> format to the simple format. I'll try to make some time to see
> how difficult it is. The transformation is relatively easy to
> do manually, but I don't know how many dts files would need to
> be converted.
My goal is to minimize legacy issues of dts files that expose the
internal implementation of overlays, such as the fragment and
__overlay__ nodes. Pantelis has submitted the dtc patches to add
the necessary syntactic sugar, and these appear to be moving toward
acceptance.
I have created a perl script to create a new style dts overlay file
from an old style dts overlay file. I have also created a shell
script to provide some error checking and to validate that the
new dts file compiles to the same result as the old dts file.
I treat the issue as a simplistic text processing exercise instead
of using a more complex approach with the hope that this is
sufficient to process the bulk of the existing in the wild overlay
dts files.
I do not think it is worth cluttering the dtc git repo with these
tools, but have no objection to them being hosted there if David
prefers. I can host them on github, elinux.org, or anywhere else
that makes sense for a (hopefully) short lived tool.
Patches 3, 4, and 5 are sample old style dts overlay files and
are not intended to be committed.
Following are several examples of use. One example that converts
properly and two that show how convsersion a malformed old style
dts is reported.
----- example 1
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new a.dts b.dts
$ cat a.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&am3353x_pinmux>;
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
target = <&i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
$ cat b.dts
/dts-v1/;
/plugin/;
&am3353x_pinmux {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
$ diff -u a.dts b.dts
--- a.dts 2016-12-27 15:51:36.433101164 -0800
+++ b.dts 2016-12-27 22:01:28.541530464 -0800
@@ -1,11 +1,7 @@
/dts-v1/;
/plugin/;
-/ {
- fragment@0 {
- target = <&am3353x_pinmux>;
-
- __overlay__ {
+ &am3353x_pinmux {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
@@ -14,12 +10,8 @@
>;
};
};
- };
-
- fragment@1 {
- target = <&i2c1>;
- __overlay__ {
+ &i2c1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
@@ -33,5 +25,3 @@
reg = <0x50>;
};
};
- };
-};
----- example 2
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new bad_a_1.dts bad_b_1.dts
No 'target' property in node fragment@0
ERROR: unable to convert bad_a_1.dts
$ cat bad_a_1.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
target = <&i2c1>;
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
----- example 3
$ export PATH="$PATH:/home/frowand/nobackup/src/github_pantelis/dtc/"
$ ./overlay_convert_old_to_new bad_a_2.dts bad_b_2.dts
No 'target' property in node fragment@1
ERROR: unable to convert bad_a_2.dts
$ cat bad_a_2.dts
/dts-v1/;
/plugin/;
/ {
fragment@0 {
target = <&am3353x_pinmux>;
__overlay__ {
i2c1_pins: pinmux_i2c1_pins {
pinctrl-single,pins = <
0x158 0x72
0x15c 0x72
>;
};
};
};
fragment@1 {
__overlay__ {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
clock-frequency = <400000>;
status = "okay";
at24@50 {
compatible = "at,24c256";
pagesize = <64>;
reg = <0x50>;
};
};
};
};
[1] http://www.spinics.net/lists/devicetree/msg152891.html
Frank Rowand (5):
perl script to convert dts from old overlay style to new overlay style
shell script to make overlay_convert easier to use
a.dts: example of an old style dts file to be converted
bad_a_1.dts: example of an old style dts file unable to be converted
bad_a_2.dts: example of an old style dts file to be converted
^ permalink raw reply
* [RFC PATCH 1/5] overlay: perl script to convert dts from old overlay style to new overlay style
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Convert overlay dts file from hand-coded expanded form to new syntactic
sugar form.
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
overlay_convert | 158 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 158 insertions(+)
create mode 100755 overlay_convert
diff --git a/overlay_convert b/overlay_convert
new file mode 100755
index 000000000000..fede0103fb4e
--- /dev/null
+++ b/overlay_convert
@@ -0,0 +1,158 @@
+#!/usr/bin/perl
+
+# Copyright 2016 Frank Rowand frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org
+# license: GPL V2
+# This file is subject to the terms and conditions of the GNU General Public
+# License v2.
+#
+# Convert overlay dts file from hand-coded expanded form to new syntactic
+# sugar form.
+
+# zzz TODO:
+# - May need to update the "/plugin/" declaration if dtc has changed.
+
+
+use strict 'refs';
+use strict subs;
+
+use Getopt::Long;
+
+$VUFX = "161227a";
+
+$script_name = $0;
+$script_name =~ s|^.*/||;
+
+
+sub usage()
+{
+ print STDERR
+"
+Usage: $script_name [options] DTS
+
+ Convert overlay dts file from hand-coded expanded form to new syntactic
+ sugar form.
+
+ Node names __symbols__, __fixups__, and __local_fixups__ are not allowed.
+ Their presence suggests that DTS has been compiled into a .dtbo and then
+ de-compiled. This is not the preferred form of source since phandle
+ references are not of the form: &label.
+
+Valid options:
+
+ -h Synonym for --help
+ --help Display this message
+ --version Display program version and exit
+
+
+ Return value:
+ 0 no error
+ 1 error processing command line
+ 2 unable to open or read DTS
+ 10 DTS contains a node name other than __overlay__, with leading '_'
+ 11 DTS contains a fragment node with no target property
+
+";
+}
+
+
+# -----------------------------------------------------------------------------
+# program entry point
+
+Getopt::Long::Configure("no_ignore_case", "bundling");
+
+if (!GetOptions(
+ "h" => \$help,
+ "help" => \$help,
+ "version" => \$version,
+ )) {
+
+ exit 1;
+}
+
+if ($version) {
+ print STDERR "\n$script_name $VUFX\n";
+ exit 0;
+}
+
+if ($help) {
+ &usage;
+ exit 0;
+}
+
+
+# ----- scan DTS
+
+$node_depth = 0;
+
+LINE:
+while ($line = <ARGV>) {
+
+ # ----- start of node
+
+ if ($line =~ /{/) {
+ $node_depth++;
+ $node_name = $line;
+ chomp $node_name;
+ $indent = $node_name;
+ $indent =~ s/\S.*//;
+ $node_name =~ s/^\s*//;
+ $node_name =~ s/\s*{.*//;
+
+ $in_fragment = 0;
+ if (($node_depth == 2) && ($node_name =~ /^fragment@\d*$/)) {
+ $in_fragment = 1;
+ $fragment_name = $node_name;
+ push @fragment_depth, $node_depth;
+ } elsif ($node_name =~ /^__overlay__$/) {
+ if (!$save_target) {
+ print STDERR "No 'target' property in node ${fragment_name}\n";
+ exit 11
+ }
+ print "$indent$save_target {\n";
+ undef $save_target;
+ } elsif ($node_name =~ /^_/) {
+ # might be __symbols__, __fixups__, or __local_fixups__
+ print STDERR "\nIllegal node name: $node_name\n\n";
+ exit 10;
+ } elsif ($node_depth > 1) {
+ print "$indent$node_name {\n";
+ }
+
+ next LINE;
+ }
+
+
+ # ----- end of node
+
+ if ($line =~ /}/) {
+
+ $indent = $line;
+ chomp $indent;
+ $indent =~ s/\S.*//;
+
+ $fragment_depth = pop @fragment_depth;
+ if (($node_depth > 2) && ($fragment_depth != $node_depth)) {
+ push @fragment_depth, $fragment_depth;
+ print "$line";
+ }
+
+ $node_depth--;
+
+ next LINE;
+ }
+
+
+ # ----- anything else
+
+ if ($in_fragment && ($line =~ /target = </)) {
+ $save_target = $line;
+ chomp $save_target;
+ $save_target =~ s/.*<\s*//;
+ $save_target =~ s/\s*>.*//;
+ } elsif (!$in_fragment) {
+ print "$line";
+ }
+
+ next LINE;
+
+}
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 2/5] overlay: shell script to make overlay_convert easier to use
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
A slightly paranoid wrapper around overlay_convert. Verifies that
converted dts file is equivalent to original dts file.
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
overlay_convert_old_to_new | 144 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 144 insertions(+)
create mode 100755 overlay_convert_old_to_new
diff --git a/overlay_convert_old_to_new b/overlay_convert_old_to_new
new file mode 100755
index 000000000000..bc26c57d4dc1
--- /dev/null
+++ b/overlay_convert_old_to_new
@@ -0,0 +1,144 @@
+#! /bin/bash
+
+#_______________________________________________________________________________
+
+
+function usage
+{
+echo "" >&2
+echo "usage:" >&2
+echo " `basename $0` -h | -help | --help" >&2
+echo " `basename $0` [options] OLD_DTS NEW_DTS" >&2
+echo "" >&2
+echo " Convert OLD_DTS from old overlay style to new overlay style" >&2
+echo " using syntactic sugar." >&2
+echo "" >&2
+echo " Options:" >&2
+echo " -h synonym for --help" >&2
+echo " --help print this message" >&2
+echo " -o synonym for --overwrite" >&2
+echo " --overwrite overwrite NEW_DTS if it already exists" >&2
+echo "" >&2
+echo " The early patches to dtc to support overlays required 'fragment'" >&2
+echo " and '__overlay__' nodes in the .dts source. Later patches to dtc" >&2
+echo " will not require these nodes (and may possibly disallow them)." >&2
+echo " The new overlay style is expected to be the preferrred form." >&2
+echo "" >&2
+echo " Will not overwrite NEW_DTS if it already exists." >&2
+echo "" >&2
+echo " Exit status is:" >&2
+echo " 0 success" >&2
+echo " 1 general error" >&2
+echo " 2 NEW_DTS already exists" >&2
+echo " 3 conversion problem" >&2
+echo " 4 'dtc -@ -O dts OLD_DTS' is different than 'dtc -@ -O dts NEW_DTS'" >&2
+echo "" >&2
+}
+
+
+unset new_dts
+unset old_dts
+unset overwrite
+
+while [[ ($# -gt 0) ]] ; do
+
+ case $1 in
+
+ -o | --overwrite )
+ shift
+ overwrite=1
+ ;;
+
+ -h | -help | --help )
+ shift
+ help=1
+ ;;
+
+ * )
+ if [[ "${old_dts}" != "" ]] ; then
+
+ if [[ "${new_dts}" != "" ]] ; then
+ echo "" >&2
+ echo "ERROR: too many arguments" >&2
+ echo "" >&2
+ exit 1
+ fi
+
+ new_dts=$1
+ shift
+ else
+ old_dts=$1
+ shift
+ fi
+ ;;
+
+ esac
+done
+
+
+if [[ (${help} == 1) ]] ; then
+ usage
+ exit 1
+fi
+
+
+#_______________________________________________________________________________
+
+if [[ -f ${new_dts} && overwrite -eq 0 ]] ; then
+
+ echo "" >&2
+ echo "ERROR: file '${new_dts}' already exists" >&2
+ echo "" >&2
+
+ exit 2
+fi
+
+
+#_______________________________________________________________________________
+
+
+if which overlay_convert >/dev/null ; then
+ OVERLAY_CONVERT=overlay_convert
+elif which ./overlay_convert >/dev/null ; then
+ OVERLAY_CONVERT=./overlay_convert
+else
+ echo "" >&2
+ echo "ERROR: overlay_convert not found or not executable" >&2
+ echo "" >&2
+
+ exit 1
+fi
+
+if ! ${OVERLAY_CONVERT} ${old_dts} > ${new_dts} ; then
+
+ echo "" >&2
+ echo "ERROR: unable to convert ${old_dts}" >&2
+ echo "" >&2
+
+ rm ${new_dts}
+
+ exit 3
+fi
+
+
+if ! which dtc >/dev/null ; then
+
+ echo "" >&2
+ echo "ERROR: dtc not found or not executable" >&2
+ echo " add the location of dtc to \$PATH" >&2
+ echo "" >&2
+
+ exit 1
+fi
+
+if ! diff -q \
+ <(dtc -@ -O dts ${old_dts} 2>/dev/null) \
+ <(dtc -@ -O dts ${new_dts} 2>/dev/null) ; then
+
+ echo "" >&2
+ echo "ERROR: ${new_dts} is not equivalent to ${old_dts}" >&2
+ echo "" >&2
+
+ exit 4
+fi
+
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 3/5] overlay: a.dts, example of an old style dts file to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new a.dts b.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
a.dts | 37 +++++++++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
create mode 100644 a.dts
diff --git a/a.dts b/a.dts
new file mode 100644
index 000000000000..ec21206a081f
--- /dev/null
+++ b/a.dts
@@ -0,0 +1,37 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&am3353x_pinmux>;
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
--
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More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply related
* [RFC PATCH 4/5] overlay: bad_a_1.dts, example of an old style dts file unable to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new bad_a_1.dts bad_b_1.dts
No 'target' property in node fragment@0
ERROR: unable to convert bad_a_1.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
bad_a_1.dts | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 bad_a_1.dts
diff --git a/bad_a_1.dts b/bad_a_1.dts
new file mode 100644
index 000000000000..b4e26fc8d945
--- /dev/null
+++ b/bad_a_1.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&i2c1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
^ permalink raw reply related
* [RFC PATCH 5/5] overlay: bad_a_2.dts, example of an old style dts file to be converted
From: frowand.list-Re5JQEeQqe8AvxtiuMwx3w @ 2016-12-28 7:20 UTC (permalink / raw)
To: david-xT8FGy+AXnRB3Ne2BGzF6laj5H9X9Tb+, jdl-CYoMK+44s/E,
pantelis.antoniou-OWPKS81ov/FWk0Htik3J/w, Pantelis Antoniou
Cc: devicetree-compiler-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Rob Herring,
glikely-s3s/WqlpOiPyB63q8FvJNQ, jlu-bIcnvbaLZ9MEGnE8C9+IrQ,
s.hauer-bIcnvbaLZ9MEGnE8C9+IrQ, phil-FnsA7b+Nu9XbIbC87yuRow,
sjg-F7+t8E8rja9g9hUCZPvPmw,
thomas.petazzoni-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
boris.brezillon-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
antoine.tenart-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8,
stephen.boyd-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <1482909617-31950-1-git-send-email-frowand.list-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
From: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
Requires a dtc that supports the new syntactic sugar.
One such version is commit: 6f4db2fc2354 DTBO magic and dtbo format options
in url = https://github.com/pantoniou/dtc
$ export PATH="$PATH:/path/dtc/"
$ ./overlay_convert_old_to_new bad_a_2.dts bad_b_2.dts
No 'target' property in node fragment@1
ERROR: unable to convert bad_a_2.dts
Signed-off-by: Frank Rowand <frank.rowand-mEdOJwZ7QcZBDgjK7y7TUQ@public.gmane.org>
---
bad_a_2.dts | 36 ++++++++++++++++++++++++++++++++++++
1 file changed, 36 insertions(+)
create mode 100644 bad_a_2.dts
diff --git a/bad_a_2.dts b/bad_a_2.dts
new file mode 100644
index 000000000000..68ac978f516c
--- /dev/null
+++ b/bad_a_2.dts
@@ -0,0 +1,36 @@
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&am3353x_pinmux>;
+
+ __overlay__ {
+
+ i2c1_pins: pinmux_i2c1_pins {
+ pinctrl-single,pins = <
+ 0x158 0x72
+ 0x15c 0x72
+ >;
+ };
+ };
+ };
+
+ fragment@1 {
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pins>;
+ clock-frequency = <400000>;
+ status = "okay";
+
+ at24@50 {
+ compatible = "at,24c256";
+ pagesize = <64>;
+ reg = <0x50>;
+ };
+ };
+ };
+};
--
1.9.1
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
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^ permalink raw reply related
* Re: [PATCH 2/2] MIPS: BMIPS: Add support SPI device nodes
From: Jaedon Shin @ 2016-12-28 7:39 UTC (permalink / raw)
To: Florian Fainelli
Cc: Ralf Baechle, Kevin Cernekee, Rob Herring,
linux-mips-6z/3iImG2C8G8FEW9MqTrA,
devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <0dffeca2-68bf-bacd-7eff-8b966c721dde-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> On 28 Dec 2016, at 7:12 AM, Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
>
> On 12/26/2016 05:59 PM, Jaedon Shin wrote:
>> Adds SPI device nodes to BCM7xxx MIPS based SoCs.
>>
>> Signed-off-by: Jaedon Shin <jaedon.shin-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
>> ---
>> arch/mips/boot/dts/brcm/bcm7125.dtsi | 55 +++++++++++++++++++++++++++++--
>> arch/mips/boot/dts/brcm/bcm7346.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7358.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7360.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7362.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7420.dtsi | 55 +++++++++++++++++++++++++++++--
>> arch/mips/boot/dts/brcm/bcm7425.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm7435.dtsi | 49 +++++++++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97125cbmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97346dbsmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97358svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97360svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97362svmb.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97420c.dts | 4 +++
>> arch/mips/boot/dts/brcm/bcm97425svmb.dts | 36 ++++++++++++++++++++
>> arch/mips/boot/dts/brcm/bcm97435svmb.dts | 4 +++
>> 16 files changed, 526 insertions(+), 6 deletions(-)
>>
>> diff --git a/arch/mips/boot/dts/brcm/bcm7125.dtsi b/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> index bbd00f65ce39..c1e19e57f64a 100644
>> --- a/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> +++ b/arch/mips/boot/dts/brcm/bcm7125.dtsi
>> @@ -46,6 +46,12 @@
>> #clock-cells = <0>;
>> clock-frequency = <27000000>;
>> };
>> +
>> + spi_clk: spi_clk {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + clock-frequency = <27000000>;
>> + };
>
> Nit, this should actually be upg_clk, since this is the clock that the
> SPI controller uses, and it is a fixed-clock with a 27Mhz frequency.
>
> Other than that, the rest looks good to me, thanks!
> --
> Florian
I will change the qspi uses upg_clk in v2.
Thanks,
Jaedon
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^ permalink raw reply
* Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Vivek Gautam @ 2016-12-28 8:58 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-pci, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
Bjorn Helgaas, robh+dt, Mark Rutland, Kukjin Kim, krzk, javier,
kishon, Will Deacon, catalin.marinas, CPGS
In-Reply-To: <21de9ca7-e586-e5c8-ecda-d30c18bb6e40@samsung.com>
Hi Jaehoon,
On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
> Hi Vivek,
>
> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>>
>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>> When Exynos that supported the pcie want to use the PCIe,
>>> it needs to control the phy resgister.
>>> But it should be more complex to control in their own PCIe device drivers.
>>>
>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>> ---
>>> drivers/phy/Kconfig | 9 ++
>>> drivers/phy/Makefile | 1 +
>>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 237 insertions(+)
>>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>
>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>> index fe00f91..94b0433 100644
>>> --- a/drivers/phy/Kconfig
>>> +++ b/drivers/phy/Kconfig
>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>> This driver provides PHY interface for USB 3.0 DRD controller
>>> present on Exynos5 SoC series.
>>>
>>> +config PHY_EXYNOS_PCIE
>>> + bool "Exynos PCIe PHY driver"
>>
>> Is there a reason for this not being 'tristate' ?
>
> Will change.
I notice that PCI_EXYNOS5433 is bool as well.
If the host has to be 'bool' then it makes sense to have phy
also bool as well. But if PCI_EXYNOS5433 can be made
tristate, then this also changes to tristate.
>
>>
>>> + depends on ARCH_EXYNOS && OF
>>> + depends on PCI_EXYNOS5433
>>> + select GENERIC_PHY
>>> + help
>>> + Enable PCIe PHY support for Exynos SoC series.
>>
>> If this driver is for Exynos5433, then same should come in this help
>> text as well.
>
> will support the other exynos series.
> I'm working on refactoring exynos5440 with PHY generic Framework.
> Then this drive is not for only Exnyos5433. how about?
Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
makes it look like it is for EXYNOS5433. I am fine if that changes as well.
[...]
>>> +
>>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>>> +
>>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>>> +#define PCIE_PHY_MAC_RESET 0x208
>>> +#define PCIE_MAC_RESET_MASK 0xFF
>>> +#define PCIE_MAC_RESET BIT(4)
>>> +#define PCIE_L1SUB_CM_CON 0x1010
>>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>>> +#define PCIE_PHY_COMMON_RESET 0x1020
>>> +#define PCIE_PHY_RESET BIT(0)
>>> +#define PCIE_PHY_GLOBAL_RESET 0x1040
>>> +#define PCIE_GLOBAL_RESET BIT(0)
>>> +#define PCIE_REFCLK BIT(1)
>>> +#define PCIE_REFCLK_MASK 0x16
>>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
>>> +
>>> +enum exynos_pcie_phy_data_type {
>>> + PCIE_PHY_TYPE_EXYNOS5433,
>>> +};
>>> +
>>> +struct exynos_pcie_phy_data {
>>> + enum exynos_pcie_phy_data_type ctrl_type;
>>
>> Why do we need this controller type ?
>> If there are changes in the IP between different version,
>> then you can as well use different compatibles.
>
> Do you mean is the using "of_device_is_compatible()"?
I meant that multiple compatible strings can be added based on the
IP versions. And any IP specific data can be put in the .data field
of 'of_device_id' structure.
If there's more to differentiate between the IP versions at runtime,
you can use of_device_is_compatible().
[...]
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply
* Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Jaehoon Chung @ 2016-12-28 9:35 UTC (permalink / raw)
To: Vivek Gautam
Cc: linux-pci, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org,
Bjorn Helgaas, robh+dt, Mark Rutland, Kukjin Kim, krzk, javier,
kishon, Will Deacon, catalin.marinas, CPGS
In-Reply-To: <CAFp+6iEOvdaRdvmz45ZVpqPrdSmeKk9je0bHg9FtNg8hE8YUxg@mail.gmail.com>
Hi Vivek,
On 12/28/2016 05:58 PM, Vivek Gautam wrote:
> Hi Jaehoon,
>
> On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>> Hi Vivek,
>>
>> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>>> Hi Jaehoon,
>>>
>>>
>>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung@samsung.com> wrote:
>>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>>> When Exynos that supported the pcie want to use the PCIe,
>>>> it needs to control the phy resgister.
>>>> But it should be more complex to control in their own PCIe device drivers.
>>>>
>>>> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
>>>> ---
>>>> drivers/phy/Kconfig | 9 ++
>>>> drivers/phy/Makefile | 1 +
>>>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>>>> 3 files changed, 237 insertions(+)
>>>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>>
>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>>> index fe00f91..94b0433 100644
>>>> --- a/drivers/phy/Kconfig
>>>> +++ b/drivers/phy/Kconfig
>>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>>> This driver provides PHY interface for USB 3.0 DRD controller
>>>> present on Exynos5 SoC series.
>>>>
>>>> +config PHY_EXYNOS_PCIE
>>>> + bool "Exynos PCIe PHY driver"
>>>
>>> Is there a reason for this not being 'tristate' ?
>>
>> Will change.
>
> I notice that PCI_EXYNOS5433 is bool as well.
> If the host has to be 'bool' then it makes sense to have phy
> also bool as well. But if PCI_EXYNOS5433 can be made
> tristate, then this also changes to tristate.
Right. I understood what you said.
>
>>
>>>
>>>> + depends on ARCH_EXYNOS && OF
>>>> + depends on PCI_EXYNOS5433
>>>> + select GENERIC_PHY
>>>> + help
>>>> + Enable PCIe PHY support for Exynos SoC series.
>>>
>>> If this driver is for Exynos5433, then same should come in this help
>>> text as well.
>>
>> will support the other exynos series.
>> I'm working on refactoring exynos5440 with PHY generic Framework.
>> Then this drive is not for only Exnyos5433. how about?
>
> Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
> makes it look like it is for EXYNOS5433. I am fine if that changes as well.
I will not put PCI_EXYNOS5433, just will use the PCI_EXYNOS.
Because it will be supported only one file as pci-exynos.c
>
> [...]
>
>>>> +
>>>> +#define PCIE_EXYNOS5433_PMU_PHY_OFFSET 0x730
>>>> +#define PCIE_PHY_OFFSET(x) ((x) * 0x4)
>>>> +
>>>> +/* Sysreg Fsys register offset and bit for Exynos5433 */
>>>> +#define PCIE_PHY_MAC_RESET 0x208
>>>> +#define PCIE_MAC_RESET_MASK 0xFF
>>>> +#define PCIE_MAC_RESET BIT(4)
>>>> +#define PCIE_L1SUB_CM_CON 0x1010
>>>> +#define PCIE_REFCLK_GATING_EN BIT(0)
>>>> +#define PCIE_PHY_COMMON_RESET 0x1020
>>>> +#define PCIE_PHY_RESET BIT(0)
>>>> +#define PCIE_PHY_GLOBAL_RESET 0x1040
>>>> +#define PCIE_GLOBAL_RESET BIT(0)
>>>> +#define PCIE_REFCLK BIT(1)
>>>> +#define PCIE_REFCLK_MASK 0x16
>>>> +#define PCIE_APP_REQ_EXIT_L1_MODE BIT(5)
>>>> +
>>>> +enum exynos_pcie_phy_data_type {
>>>> + PCIE_PHY_TYPE_EXYNOS5433,
>>>> +};
>>>> +
>>>> +struct exynos_pcie_phy_data {
>>>> + enum exynos_pcie_phy_data_type ctrl_type;
>>>
>>> Why do we need this controller type ?
>>> If there are changes in the IP between different version,
>>> then you can as well use different compatibles.
>>
>> Do you mean is the using "of_device_is_compatible()"?
>
> I meant that multiple compatible strings can be added based on the
> IP versions. And any IP specific data can be put in the .data field
> of 'of_device_id' structure.
> If there's more to differentiate between the IP versions at runtime,
> you can use of_device_is_compatible().
>
> [...]
>
>
>
^ permalink raw reply
* Re: [PATCH v3 1/3] Documentation: dt: net: add mt76 wireless device binding
From: Rafał Miłecki @ 2016-12-28 10:08 UTC (permalink / raw)
To: Kalle Valo
Cc: Arnd Bergmann, Felix Fietkau,
linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Martin Blumenstingl
In-Reply-To: <87vax9r26s.fsf-HodKDYzPHsUD5k0oWYwrnHL1okKdlPRT@public.gmane.org>
On 3 October 2016 at 15:29, Kalle Valo <kvalo-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
> Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> writes:
>
>> On Friday 30 September 2016, Felix Fietkau wrote:
>>> >> >> >> + device_type = "pci";
>>> >> >> >> + mediatek,mtd-eeprom = <&factory 0x8000>;
>>> >> >> >> + mediatek,2ghz = <0>;
>>> >> >
>>> >> > It's not clear what the possible values for the 2ghz property are,
>>> >> > can you be more verbose in the description? How is <0> different
>>> >> > from no property?
>>> >> 0 means disabled, no property means unchanged (compared to EEPROM).
>>> >
>>> > Maybe have a boolean property instead then to say "mediatek,2ghz-disabled" ?
>>> >
>>> > If zero is the only possible value, there is no need to put a number in there.
>>> 1 is also possible, which will force-enable the capability.
>>
>> Ok, then both those values should be documented in the binding.
>
> Related to this, Martin sent patches which add generic bindings for
> enabling 2 Ghz and 5 Ghz bands.
>
> [RFC,1/3] Documentation: dt-bindings: add IEEE 802.11 binding documentation
> https://patchwork.kernel.org/patch/9359833/
>
> [RFC,2/3] of: add IEEE 802.11 device configuration support code
> https://patchwork.kernel.org/patch/9359837/
I would prefer something more generic. Many tri-band routers split 5
GHz band into 2 sets of channels and they have separated radios for
them.
E.g. Netgear R8000 has phy0 which should be used for higher part of 5
GHz band (channels 149+) and phy2 which should be used for lower part
of 5 GHz band (channels from 36 to 48 or 64).
What do you think about some more flexible properties like:
ieee80211-min-center-freq
ieee80211-max-center-freq
--
Rafał
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^ permalink raw reply
* Re: [RFC PATCH 1/6] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Vivek Gautam @ 2016-12-28 10:12 UTC (permalink / raw)
To: Jaehoon Chung
Cc: linux-pci-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Bjorn Helgaas, robh+dt, Mark Rutland, Kukjin Kim,
krzk-DgEjT+Ai2ygdnm+yROfE0A, javier-JPH+aEBZ4P+UEJcrhfAQsw,
kishon, Will Deacon, catalin.marinas-5wv7dgnIgG8, CPGS
In-Reply-To: <ebdb57b1-9a24-f83e-ac26-887f7a2263d3-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
On Wed, Dec 28, 2016 at 3:05 PM, Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> Hi Vivek,
>
> On 12/28/2016 05:58 PM, Vivek Gautam wrote:
>> Hi Jaehoon,
>>
>> On Wed, Dec 28, 2016 at 8:19 AM, Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>>> Hi Vivek,
>>>
>>> On 12/27/2016 02:53 PM, Vivek Gautam wrote:
>>>> Hi Jaehoon,
>>>>
>>>>
>>>> On Mon, Dec 26, 2016 at 10:50 AM, Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
>>>>> This patch supports to use Generic Phy framework for Exynos PCIe phy.
>>>>> When Exynos that supported the pcie want to use the PCIe,
>>>>> it needs to control the phy resgister.
>>>>> But it should be more complex to control in their own PCIe device drivers.
>>>>>
>>>>> Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>>>>> ---
>>>>> drivers/phy/Kconfig | 9 ++
>>>>> drivers/phy/Makefile | 1 +
>>>>> drivers/phy/phy-exynos-pcie.c | 227 ++++++++++++++++++++++++++++++++++++++++++
>>>>> 3 files changed, 237 insertions(+)
>>>>> create mode 100644 drivers/phy/phy-exynos-pcie.c
>>>>>
>>>>> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
>>>>> index fe00f91..94b0433 100644
>>>>> --- a/drivers/phy/Kconfig
>>>>> +++ b/drivers/phy/Kconfig
>>>>> @@ -341,6 +341,15 @@ config PHY_EXYNOS5_USBDRD
>>>>> This driver provides PHY interface for USB 3.0 DRD controller
>>>>> present on Exynos5 SoC series.
>>>>>
>>>>> +config PHY_EXYNOS_PCIE
>>>>> + bool "Exynos PCIe PHY driver"
>>>>
>>>> Is there a reason for this not being 'tristate' ?
>>>
>>> Will change.
>>
>> I notice that PCI_EXYNOS5433 is bool as well.
>> If the host has to be 'bool' then it makes sense to have phy
>> also bool as well. But if PCI_EXYNOS5433 can be made
>> tristate, then this also changes to tristate.
>
> Right. I understood what you said.
>
>>
>>>
>>>>
>>>>> + depends on ARCH_EXYNOS && OF
>>>>> + depends on PCI_EXYNOS5433
>>>>> + select GENERIC_PHY
>>>>> + help
>>>>> + Enable PCIe PHY support for Exynos SoC series.
>>>>
>>>> If this driver is for Exynos5433, then same should come in this help
>>>> text as well.
>>>
>>> will support the other exynos series.
>>> I'm working on refactoring exynos5440 with PHY generic Framework.
>>> Then this drive is not for only Exnyos5433. how about?
>>
>> Ok, it's good then. My only concern is 'depends on PCI_EXYNOS5433'
>> makes it look like it is for EXYNOS5433. I am fine if that changes as well.
>
> I will not put PCI_EXYNOS5433, just will use the PCI_EXYNOS.
> Because it will be supported only one file as pci-exynos.c
cool then.
[...]
--
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^ permalink raw reply
* [PATCH 0/4] PCI: exynos: use the PHY generic framework
From: Jaehoon Chung @ 2016-12-28 10:34 UTC (permalink / raw)
To: linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, alim.akhtar, cpgs, Jaehoon Chung
In-Reply-To: <CGME20161228103455epcas1p1c762bc59add0011beff1d4ff697b5c8d@epcas1p1.samsung.com>
This patch is for using PHY generic framework.
When Exynos5440 had upstreamed, there was no PHY subsytem.
Now the using PHY framework is mandantory.
In future, Exynos variant should be supported in pci-exynos.c
Theses pathces based on the below patches
- Jaehoon's patches
http://patchwork.ozlabs.org/patch/706998/
http://patchwork.ozlabs.org/patch/706997/
http://patchwork.ozlabs.org/patch/706995/
http://patchwork.ozlabs.org/patch/706994/
- Srinivas's patch
http://patchwork.ozlabs.org/patch/703530/
- Pankaj's patch
http://patchwork.ozlabs.org/patch/708414/
Jaehoon Chung (4):
phy: exynos-pcie: Add support for Exynos PCIe phy
Documetation: samsung-phy: add the exynos-pcie-phy binding
Documetation: binding: modify the exynos5440 pcie binding
ARM: dts: exynos5440: support the phy-pcie node for pcie
.../bindings/pci/samsung,exynos5440-pcie.txt | 29 ++-
.../devicetree/bindings/phy/samsung-phy.txt | 23 ++
arch/arm/boot/dts/exynos5440.dtsi | 44 +++-
drivers/pci/host/pci-exynos.c | 198 ++------------
drivers/phy/Kconfig | 9 +
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos-pcie.c | 289 +++++++++++++++++++++
7 files changed, 395 insertions(+), 198 deletions(-)
create mode 100644 drivers/phy/phy-exynos-pcie.c
--
2.10.2
^ permalink raw reply
* [PATCH 1/4] phy: exynos-pcie: Add support for Exynos PCIe phy
From: Jaehoon Chung @ 2016-12-28 10:34 UTC (permalink / raw)
To: linux-pci-u79uwXL29TY76Z2rM5mHXA
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, kgene-DgEjT+Ai2ygdnm+yROfE0A,
krzk-DgEjT+Ai2ygdnm+yROfE0A, kishon-l0cyMroinI0,
jingoohan1-Re5JQEeQqe8AvxtiuMwx3w,
vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ,
pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ,
alim.akhtar-Sze3O3UU22JBDgjK7y7TUQ, cpgs-Sze3O3UU22JBDgjK7y7TUQ,
Jaehoon Chung
In-Reply-To: <20161228103454.26467-1-jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
This patch supports to use Generic Phy framework for Exynos PCIe phy.
When Exynos that supported the pcie want to use the PCIe,
it needs to control the phy resgister.
But it should be more complex to control in their own PCIe device drivers.
To use this, move some codes from driver/pci/host/pci-exynos.c.
Signed-off-by: Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
drivers/pci/host/pci-exynos.c | 198 ++++-------------------------
drivers/phy/Kconfig | 9 ++
drivers/phy/Makefile | 1 +
drivers/phy/phy-exynos-pcie.c | 289 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 321 insertions(+), 176 deletions(-)
create mode 100644 drivers/phy/phy-exynos-pcie.c
diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
index feed0fd..ab03f02 100644
--- a/drivers/pci/host/pci-exynos.c
+++ b/drivers/pci/host/pci-exynos.c
@@ -21,6 +21,7 @@
#include <linux/of_gpio.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
#include <linux/resource.h>
#include <linux/signal.h>
#include <linux/types.h>
@@ -54,49 +55,8 @@
#define PCIE_ELBI_SLV_ARMISC 0x120
#define PCIE_ELBI_SLV_DBI_ENABLE BIT(21)
-/* PCIe Purple registers */
-#define PCIE_PHY_GLOBAL_RESET 0x000
-#define PCIE_PHY_COMMON_RESET 0x004
-#define PCIE_PHY_CMN_REG 0x008
-#define PCIE_PHY_MAC_RESET 0x00c
-#define PCIE_PHY_PLL_LOCKED 0x010
-#define PCIE_PHY_TRSVREG_RESET 0x020
-#define PCIE_PHY_TRSV_RESET 0x024
-
-/* PCIe PHY registers */
-#define PCIE_PHY_IMPEDANCE 0x004
-#define PCIE_PHY_PLL_DIV_0 0x008
-#define PCIE_PHY_PLL_BIAS 0x00c
-#define PCIE_PHY_DCC_FEEDBACK 0x014
-#define PCIE_PHY_PLL_DIV_1 0x05c
-#define PCIE_PHY_COMMON_POWER 0x064
-#define PCIE_PHY_COMMON_PD_CMN BIT(3)
-#define PCIE_PHY_TRSV0_EMP_LVL 0x084
-#define PCIE_PHY_TRSV0_DRV_LVL 0x088
-#define PCIE_PHY_TRSV0_RXCDR 0x0ac
-#define PCIE_PHY_TRSV0_POWER 0x0c4
-#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV0_LVCC 0x0dc
-#define PCIE_PHY_TRSV1_EMP_LVL 0x144
-#define PCIE_PHY_TRSV1_RXCDR 0x16c
-#define PCIE_PHY_TRSV1_POWER 0x184
-#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV1_LVCC 0x19c
-#define PCIE_PHY_TRSV2_EMP_LVL 0x204
-#define PCIE_PHY_TRSV2_RXCDR 0x22c
-#define PCIE_PHY_TRSV2_POWER 0x244
-#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV2_LVCC 0x25c
-#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
-#define PCIE_PHY_TRSV3_RXCDR 0x2ec
-#define PCIE_PHY_TRSV3_POWER 0x304
-#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
-#define PCIE_PHY_TRSV3_LVCC 0x31c
-
struct exynos_pcie_mem_res {
void __iomem *elbi_base; /* DT 0th resource: PCIE CTRL */
- void __iomem *phy_base; /* DT 1st resource: PHY CTRL */
- void __iomem *block_base; /* DT 2nd resource: PHY ADDITIONAL CTRL */
};
struct exynos_pcie_clk_res {
@@ -110,6 +70,7 @@ struct exynos_pcie {
struct exynos_pcie_clk_res *clk_res;
const struct exynos_pcie_ops *ops;
int reset_gpio;
+ struct phy *phy;
};
struct exynos_pcie_ops {
@@ -135,16 +96,6 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
if (IS_ERR(ep->mem_res->elbi_base))
return PTR_ERR(ep->mem_res->elbi_base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
- ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(ep->mem_res->phy_base))
- return PTR_ERR(ep->mem_res->phy_base);
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- ep->mem_res->block_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(ep->mem_res->block_base))
- return PTR_ERR(ep->mem_res->block_base);
-
return 0;
}
@@ -267,111 +218,6 @@ static void exynos_pcie_deassert_core_reset(struct exynos_pcie *ep)
exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_NONSTICKY_RESET);
exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_APP_INIT_RESET);
exynos_pcie_writel(ep->mem_res->elbi_base, 0, PCIE_APP_INIT_RESET);
- exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_MAC_RESET);
-}
-
-static void exynos_pcie_assert_phy_reset(struct exynos_pcie *ep)
-{
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_MAC_RESET);
- exynos_pcie_writel(ep->mem_res->block_base, 1, PCIE_PHY_GLOBAL_RESET);
-}
-
-static void exynos_pcie_deassert_phy_reset(struct exynos_pcie *ep)
-{
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_GLOBAL_RESET);
- exynos_pcie_writel(ep->mem_res->elbi_base, 1, PCIE_PWR_RESET);
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_COMMON_RESET);
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_CMN_REG);
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSVREG_RESET);
- exynos_pcie_writel(ep->mem_res->block_base, 0, PCIE_PHY_TRSV_RESET);
-}
-
-static void exynos_pcie_power_on_phy(struct exynos_pcie *ep)
-{
- u32 val;
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
- val &= ~PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
- val &= ~PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
- val &= ~PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
- val &= ~PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
- val &= ~PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_power_off_phy(struct exynos_pcie *ep)
-{
- u32 val;
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_COMMON_POWER);
- val |= PCIE_PHY_COMMON_PD_CMN;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_COMMON_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV0_POWER);
- val |= PCIE_PHY_TRSV0_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV0_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV1_POWER);
- val |= PCIE_PHY_TRSV1_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV1_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV2_POWER);
- val |= PCIE_PHY_TRSV2_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV2_POWER);
-
- val = exynos_pcie_readl(ep->mem_res->phy_base, PCIE_PHY_TRSV3_POWER);
- val |= PCIE_PHY_TRSV3_PD_TSV;
- exynos_pcie_writel(ep->mem_res->phy_base, val, PCIE_PHY_TRSV3_POWER);
-}
-
-static void exynos_pcie_init_phy(struct exynos_pcie *ep)
-{
- /* DCC feedback control off */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
-
- /* set TX/RX impedance */
- exynos_pcie_writel(ep->mem_res->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
-
- /* set 50Mhz PHY clock */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
-
- /* set TX Differential output for lane 0 */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
-
- /* set TX Pre-emphasis Level Control for lane 0 to minimum */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
-
- /* set RX clock and data recovery bandwidth */
- exynos_pcie_writel(ep->mem_res->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
-
- /* change TX Pre-emphasis Level Control for lanes */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
- exynos_pcie_writel(ep->mem_res->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
-
- /* set LVCC */
- exynos_pcie_writel(ep->mem_res->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
- exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
- exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
- exynos_pcie_writel(ep->mem_res->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
}
static void exynos_pcie_assert_reset(struct exynos_pcie *exynos_pcie)
@@ -388,7 +234,6 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
{
struct pcie_port *pp = &exynos_pcie->pp;
struct device *dev = pp->dev;
- u32 val;
if (dw_pcie_link_up(pp)) {
dev_err(dev, "Link already up\n");
@@ -396,17 +241,13 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
}
exynos_pcie_assert_core_reset(exynos_pcie);
- exynos_pcie_assert_phy_reset(exynos_pcie);
- exynos_pcie_deassert_phy_reset(exynos_pcie);
- exynos_pcie_power_on_phy(exynos_pcie);
- exynos_pcie_init_phy(exynos_pcie);
-
- /* pulse for common reset */
- exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
- PCIE_PHY_COMMON_RESET);
- udelay(500);
- exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
- PCIE_PHY_COMMON_RESET);
+
+ phy_reset(exynos_pcie->phy);
+
+ exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1, PCIE_PWR_RESET);
+
+ phy_power_on(exynos_pcie->phy);
+ phy_init(exynos_pcie->phy);
exynos_pcie_deassert_core_reset(exynos_pcie);
dw_pcie_setup_rc(pp);
@@ -420,13 +261,8 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
if (!dw_pcie_wait_for_link(pp))
return 0;
- while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
- PCIE_PHY_PLL_LOCKED) == 0) {
- val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
- PCIE_PHY_PLL_LOCKED);
- dev_info(dev, "PLL Locked: 0x%x\n", val);
- }
- exynos_pcie_power_off_phy(exynos_pcie);
+ phy_power_off(exynos_pcie->phy);
+
return -ETIMEDOUT;
}
@@ -649,9 +485,19 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
return ret;
}
+ exynos_pcie->phy = devm_phy_get(&pdev->dev, "pcie-phy");
+ if (IS_ERR(exynos_pcie->phy)) {
+ if (PTR_ERR(exynos_pcie->phy) != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "Can't find the pcie-phy\n");
+ ret = PTR_ERR(exynos_pcie->phy);
+ goto fail_probe;
+ }
+
ret = exynos_add_pcie_port(exynos_pcie, pdev);
- if (ret < 0)
+ if (ret < 0) {
+ phy_exit(exynos_pcie->phy);
goto fail_probe;
+ }
platform_set_drvdata(pdev, exynos_pcie);
return 0;
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index e8eb7f2..2dddef4 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
This driver provides PHY interface for USB 3.0 DRD controller
present on Exynos5 SoC series.
+config PHY_EXYNOS_PCIE
+ bool "Exynos PCIe PHY driver"
+ depends on ARCH_EXYNOS && OF
+ depends on PCI_EXYNOS
+ select GENERIC_PHY
+ help
+ Enable PCIe PHY support for Exynos SoC series.
+ This driver provides PHY interface for Exynos PCIe controller.
+
config PHY_PISTACHIO_USB
tristate "IMG Pistachio USB2.0 PHY driver"
depends on MACH_PISTACHIO
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 65eb2f4..081aeb4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
+obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
new file mode 100644
index 0000000..0a99b77
--- /dev/null
+++ b/drivers/phy/phy-exynos-pcie.c
@@ -0,0 +1,289 @@
+/*
+ * Samsung EXYNOS5 SoC series PCIe PHY driver
+ *
+ * Phy provider for PCIe controller on Exynos5 SoC series
+ *
+ * Copyright (C) 2016 Samsung Electronics Co., Ltd.
+ * Jaehoon Chung <jh80.chung-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+#include <linux/phy/phy.h>
+#include <linux/regmap.h>
+
+/* PCIe Purple registers */
+#define PCIE_PHY_GLOBAL_RESET 0x000
+#define PCIE_PHY_COMMON_RESET 0x004
+#define PCIE_PHY_CMN_REG 0x008
+#define PCIE_PHY_MAC_RESET 0x00c
+#define PCIE_PHY_PLL_LOCKED 0x010
+#define PCIE_PHY_TRSVREG_RESET 0x020
+#define PCIE_PHY_TRSV_RESET 0x024
+
+/* PCIe PHY registers */
+#define PCIE_PHY_IMPEDANCE 0x004
+#define PCIE_PHY_PLL_DIV_0 0x008
+#define PCIE_PHY_PLL_BIAS 0x00c
+#define PCIE_PHY_DCC_FEEDBACK 0x014
+#define PCIE_PHY_PLL_DIV_1 0x05c
+#define PCIE_PHY_COMMON_POWER 0x064
+#define PCIE_PHY_COMMON_PD_CMN BIT(3)
+#define PCIE_PHY_TRSV0_EMP_LVL 0x084
+#define PCIE_PHY_TRSV0_DRV_LVL 0x088
+#define PCIE_PHY_TRSV0_RXCDR 0x0ac
+#define PCIE_PHY_TRSV0_POWER 0x0c4
+#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
+#define PCIE_PHY_TRSV0_LVCC 0x0dc
+#define PCIE_PHY_TRSV1_EMP_LVL 0x144
+#define PCIE_PHY_TRSV1_RXCDR 0x16c
+#define PCIE_PHY_TRSV1_POWER 0x184
+#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
+#define PCIE_PHY_TRSV1_LVCC 0x19c
+#define PCIE_PHY_TRSV2_EMP_LVL 0x204
+#define PCIE_PHY_TRSV2_RXCDR 0x22c
+#define PCIE_PHY_TRSV2_POWER 0x244
+#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
+#define PCIE_PHY_TRSV2_LVCC 0x25c
+#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
+#define PCIE_PHY_TRSV3_RXCDR 0x2ec
+#define PCIE_PHY_TRSV3_POWER 0x304
+#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
+#define PCIE_PHY_TRSV3_LVCC 0x31c
+
+struct exynos_pcie_phy_data {
+ struct phy_ops *ops;
+};
+
+/* For Exynos pcie phy */
+struct exynos_pcie_phy {
+ const struct exynos_pcie_phy_data *drv_data;
+ void __iomem *phy_base;
+ void __iomem *blk_base; /* For exynos5440 */
+};
+
+static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
+{
+ writel(val, base + offset);
+}
+
+static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
+{
+ return readl(base + offset);
+}
+
+/* For Exynos5440 specific functions */
+static int exynos5440_pcie_phy_init(struct phy *phy)
+{
+ struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+ /* DCC feedback control off */
+ exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
+
+ /* set TX/RX impedance */
+ exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
+
+ /* set 50Mhz PHY clock */
+ exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
+ exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
+
+ /* set TX Differential output for lane 0 */
+ exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
+
+ /* set TX Pre-emphasis Level Control for lane 0 to minimum */
+ exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
+
+ /* set RX clock and data recovery bandwidth */
+ exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
+ exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
+ exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
+ exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
+ exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
+
+ /* change TX Pre-emphasis Level Control for lanes */
+ exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
+ exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
+ exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
+ exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
+
+ /* set LVCC */
+ exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
+ exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
+ exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
+ exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
+
+ /* pulse for common reset */
+ exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
+ udelay(500);
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+
+ return 0;
+}
+
+static int exynos5440_pcie_phy_power_on(struct phy *phy)
+{
+ struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+ u32 val;
+
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+ val &= ~PCIE_PHY_COMMON_PD_CMN;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+ val &= ~PCIE_PHY_TRSV0_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+ val &= ~PCIE_PHY_TRSV1_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+ val &= ~PCIE_PHY_TRSV2_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+ val &= ~PCIE_PHY_TRSV3_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+ return 0;
+}
+
+static int exynos5440_pcie_phy_power_off(struct phy *phy)
+{
+ struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+ u32 val;
+
+ while (exynos_pcie_phy_readl(ep->phy_base,
+ PCIE_PHY_PLL_LOCKED) == 0) {
+ val = exynos_pcie_phy_readl(ep->blk_base,
+ PCIE_PHY_PLL_LOCKED);
+ dev_info(&phy->dev, "PLL Locked: 0x%x\n", val);
+ }
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
+ val |= PCIE_PHY_COMMON_PD_CMN;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
+ val |= PCIE_PHY_TRSV0_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
+ val |= PCIE_PHY_TRSV1_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
+ val |= PCIE_PHY_TRSV2_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
+
+ val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
+ val |= PCIE_PHY_TRSV3_PD_TSV;
+ exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
+
+ return 0;
+}
+
+static int exynos5440_pcie_phy_reset(struct phy *phy)
+{
+ struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
+
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
+ exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
+ exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
+
+ return 0;
+}
+
+static struct phy_ops exynos5440_phy_ops = {
+ .init = exynos5440_pcie_phy_init,
+ .power_on = exynos5440_pcie_phy_power_on,
+ .power_off = exynos5440_pcie_phy_power_off,
+ .reset = exynos5440_pcie_phy_reset,
+};
+
+static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
+ .ops = &exynos5440_phy_ops,
+};
+
+static const struct of_device_id exynos_pcie_phy_match[] = {
+ {
+ .compatible = "samsung,exynos5440-pcie-phy",
+ .data = &exynos5440_pcie_phy_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
+
+static int exynos_pcie_phy_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct exynos_pcie_phy *exynos_phy;
+ struct phy *generic_phy;
+ struct phy_provider *phy_provider;
+ struct resource *res;
+ const struct exynos_pcie_phy_data *drv_data;
+ struct device_node *child;
+ int ret;
+
+ drv_data = of_device_get_match_data(dev);
+ if (!drv_data)
+ return -ENODEV;
+
+ exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
+ if (!exynos_phy)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ exynos_phy->phy_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(exynos_phy->phy_base))
+ return PTR_ERR(exynos_phy->phy_base);
+
+ exynos_phy->drv_data = drv_data;
+
+ for_each_child_of_node(np, child) {
+ ret = of_address_to_resource(child, 0, res);
+ if (!ret) {
+ exynos_phy->blk_base =
+ devm_ioremap_resource(dev, res);
+ } else {
+ dev_warn(dev, "Failed to get block_base.\n");
+ return ret;
+ }
+ }
+
+ generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
+ if (IS_ERR(generic_phy)) {
+ dev_err(dev, "failed to create PHY\n");
+ return PTR_ERR(generic_phy);
+ }
+
+ phy_set_drvdata(generic_phy, exynos_phy);
+ phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
+
+ return PTR_ERR_OR_ZERO(phy_provider);
+}
+
+static struct platform_driver exynos_pcie_phy_driver = {
+ .probe = exynos_pcie_phy_probe,
+ .driver = {
+ .of_match_table = exynos_pcie_phy_match,
+ .name = "exynos_pcie_phy",
+ }
+};
+module_platform_driver(exynos_pcie_phy_driver);
--
2.10.2
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^ permalink raw reply related
* [PATCH 2/4] Documetation: samsung-phy: add the exynos-pcie-phy binding
From: Jaehoon Chung @ 2016-12-28 10:34 UTC (permalink / raw)
To: linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, alim.akhtar, cpgs, Jaehoon Chung
In-Reply-To: <20161228103454.26467-1-jh80.chung@samsung.com>
Adds the exynos-pcie-phy binding for Exynos PCIe PHY.
This is for using generic PHY framework.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
.../devicetree/bindings/phy/samsung-phy.txt | 23 ++++++++++++++++++++++
1 file changed, 23 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index 9872ba8..1cbc15f 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -191,3 +191,26 @@ Example:
usbdrdphy0 = &usb3_phy0;
usbdrdphy1 = &usb3_phy1;
};
+
+Samsung Exynos SoC series PCIe PHY controller
+--------------------------------------------------
+Required properties:
+- compatible : Should be set to "samsung,exynos5440-pcie-phy"
+- #phy-cells : Must be zero
+- reg : a register used by phy driver.
+
+Required properies for child node:
+- reg : a block register used by phy driver.
+
+Example:
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ block@271000 {
+ reg = <0x271000 0x40>;
+ };
+ };
--
2.10.2
^ permalink raw reply related
* [PATCH 3/4] Documetation: binding: modify the exynos5440 pcie binding
From: Jaehoon Chung @ 2016-12-28 10:34 UTC (permalink / raw)
To: linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, alim.akhtar, cpgs, Jaehoon Chung
In-Reply-To: <20161228103454.26467-1-jh80.chung@samsung.com>
According to using PHY framework, modified the exynos5440-pcie binding.
And use "config" property to follow the designware-pcie binding.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
.../bindings/pci/samsung,exynos5440-pcie.txt | 29 +++++++++++++---------
1 file changed, 17 insertions(+), 12 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
index 4f9d23d..51f6214 100644
--- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
@@ -5,10 +5,15 @@ and thus inherits all the common properties defined in designware-pcie.txt.
Required properties:
- compatible: "samsung,exynos5440-pcie"
-- reg: base addresses and lengths of the pcie controller,
- the phy controller, additional register for the phy controller.
+- reg: base addresses and lengths of the pcie controller
- interrupts: A list of interrupt outputs for level interrupt,
pulse interrupt, special interrupt.
+- phys: From PHY binding. Phandle for the Generic PHY.
+ Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
+- phy-names: Must be "pcie-phy".
+
+Other common properties refer to
+ Documentation/devicetree/binding/pci/designware-pcie.txt
Example:
@@ -16,18 +21,18 @@ SoC specific DT Entry:
pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000
- 0x270000 0x1000
- 0x271000 0x40>;
+ reg = <0x290000 0x1000>, <0x40000000 0x100>;
+ reg-names = "elbi", "config";
interrupts = <0 20 0>, <0 21 0>, <0 22 0>;
clocks = <&clock 28>, <&clock 27>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
+ ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
+ phys = <&pcie_phy0>;
+ phy-names = "pcie-phy";
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
@@ -36,17 +41,17 @@ SoC specific DT Entry:
pcie@2a0000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
+ reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+ reg-names = "elbi", "config";
interrupts = <0 23 0>, <0 24 0>, <0 25 0>;
clocks = <&clock 29>, <&clock 27>;
clock-names = "pcie", "pcie_bus";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
+ phys = <&pcie_phy1>;
+ phy-names = "pcie-phy";
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
--
2.10.2
^ permalink raw reply related
* [PATCH 4/4] ARM: dts: exynos5440: support the phy-pcie node for pcie
From: Jaehoon Chung @ 2016-12-28 10:34 UTC (permalink / raw)
To: linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, alim.akhtar, cpgs, Jaehoon Chung
In-Reply-To: <20161228103454.26467-1-jh80.chung@samsung.com>
Add phy-pcie node for using Exynos5440 pcie.
And some properies are changed to generic usage.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
---
arch/arm/boot/dts/exynos5440.dtsi | 44 ++++++++++++++++++++++++++++++---------
1 file changed, 34 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/exynos5440.dtsi b/arch/arm/boot/dts/exynos5440.dtsi
index 2a2e570..deb2504 100644
--- a/arch/arm/boot/dts/exynos5440.dtsi
+++ b/arch/arm/boot/dts/exynos5440.dtsi
@@ -290,11 +290,34 @@
clock-names = "usbhost";
};
+ pcie_phy0: pcie-phy@270000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x270000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ block@271000 {
+ reg = <0x271000 0x40>;
+ };
+ };
+
+ pcie_phy1: pcie-phy@272000 {
+ #phy-cells = <0>;
+ compatible = "samsung,exynos5440-pcie-phy";
+ reg = <0x272000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ block@271040 {
+ reg = <0x271040 0x40>;
+ };
+ };
+
pcie_0: pcie@290000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x290000 0x1000
- 0x270000 0x1000
- 0x271000 0x40>;
+ reg = <0x290000 0x1000>, <0x40000000 0x1000>;
+ reg-names = "elbi", "config";
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
@@ -303,8 +326,9 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x40000000 0x40000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
+ pyhs = <&pcie_phy0>;
+ phys = "pcie-phy";
+ ranges = <0x81000000 0 0 0x40001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x40011000 0x40011000 0 0x1ffef000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
@@ -315,9 +339,8 @@
pcie_1: pcie@2a0000 {
compatible = "samsung,exynos5440-pcie", "snps,dw-pcie";
- reg = <0x2a0000 0x1000
- 0x272000 0x1000
- 0x271040 0x40>;
+ reg = <0x2a0000 0x1000>, <0x60000000 0x1000>;
+ reg-names = "elbi", "config";
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
@@ -326,8 +349,9 @@
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
- ranges = <0x00000800 0 0x60000000 0x60000000 0 0x00001000 /* configuration space */
- 0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
+ pyhs = <&pcie_phy1>;
+ phys = "pcie-phy";
+ ranges = <0x81000000 0 0 0x60001000 0 0x00010000 /* downstream I/O */
0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>; /* non-prefetchable memory */
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
--
2.10.2
^ permalink raw reply related
* Re: [PATCH v3 1/3] Documentation: dt: net: add mt76 wireless device binding
From: Martin Blumenstingl @ 2016-12-28 10:43 UTC (permalink / raw)
To: Rafał Miłecki
Cc: Kalle Valo, Arnd Bergmann, Felix Fietkau,
linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CACna6ryikdd0Yt2FWB_JT27N5uuh9XU+JUWNRjs4H5YcD5PVpw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On Wed, Dec 28, 2016 at 11:08 AM, Rafał Miłecki <zajec5-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> On 3 October 2016 at 15:29, Kalle Valo <kvalo-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org> wrote:
>> Arnd Bergmann <arnd-r2nGTMty4D4@public.gmane.org> writes:
>>
>>> On Friday 30 September 2016, Felix Fietkau wrote:
>>>> >> >> >> + device_type = "pci";
>>>> >> >> >> + mediatek,mtd-eeprom = <&factory 0x8000>;
>>>> >> >> >> + mediatek,2ghz = <0>;
>>>> >> >
>>>> >> > It's not clear what the possible values for the 2ghz property are,
>>>> >> > can you be more verbose in the description? How is <0> different
>>>> >> > from no property?
>>>> >> 0 means disabled, no property means unchanged (compared to EEPROM).
>>>> >
>>>> > Maybe have a boolean property instead then to say "mediatek,2ghz-disabled" ?
>>>> >
>>>> > If zero is the only possible value, there is no need to put a number in there.
>>>> 1 is also possible, which will force-enable the capability.
>>>
>>> Ok, then both those values should be documented in the binding.
>>
>> Related to this, Martin sent patches which add generic bindings for
>> enabling 2 Ghz and 5 Ghz bands.
>>
>> [RFC,1/3] Documentation: dt-bindings: add IEEE 802.11 binding documentation
>> https://patchwork.kernel.org/patch/9359833/
>>
>> [RFC,2/3] of: add IEEE 802.11 device configuration support code
>> https://patchwork.kernel.org/patch/9359837/
>
> I would prefer something more generic. Many tri-band routers split 5
> GHz band into 2 sets of channels and they have separated radios for
> them.
>
> E.g. Netgear R8000 has phy0 which should be used for higher part of 5
> GHz band (channels 149+) and phy2 which should be used for lower part
> of 5 GHz band (channels from 36 to 48 or 64).
>
> What do you think about some more flexible properties like:
> ieee80211-min-center-freq
> ieee80211-max-center-freq
what would happen if only one of these properties was given or would
we forbid that (because the .dts should always describe the hardware,
and if we describe a lower bound then we should also describe the
upper bound)?
the benefits of your solution are:
- this would allow *enabling* bands as well (my proposal allows this
as well, but the .dts is indeed a bit hard to read - unlike your
solution which looks nice to me)
- we could handle this within generic cfg80211/mac80211 code instead
of "duplicating" it per driver
should we describe the center freq in Hz or MHz (cfg80211's
ieee80211_channel uses the latter)?
@Arnd: what do you think from devicetree perspective?
Regards,
Martin
[0] http://lxr.free-electrons.com/source/include/net/cfg80211.h#L130
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^ permalink raw reply
* Re: [PATCH] of: reserved_mem: set dma_ops for devices using reserved mem
From: Marek Szyprowski @ 2016-12-28 10:55 UTC (permalink / raw)
To: Pankaj Dubey, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA
Cc: robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
frowand.list-Re5JQEeQqe8AvxtiuMwx3w,
hans.verkuil-FYB4Gu1CFyUAvxtiuMwx3w, krzk-DgEjT+Ai2ygdnm+yROfE0A,
kgene-DgEjT+Ai2ygdnm+yROfE0A, Smitha T Murthy
In-Reply-To: <1482299071-22637-1-git-send-email-pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Hi Pankaj,
On 2016-12-21 06:44, Pankaj Dubey wrote:
> From: Smitha T Murthy <smitha.t-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
>
> For some IPs, there may be virtual child devices created and for them its
> necessary to set the dma_ops if it's using reserved memory else it will call
> the dummy dma_ops during buffer operations for the child devices which will
> lead to memory mapping failure.
>
> Signed-off-by: Smitha T Murthy <smitha.t-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> Signed-off-by: Pankaj Dubey <pankaj.dubey-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
Acked-by: Marek Szyprowski <m.szyprowski-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
> drivers/of/of_reserved_mem.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/of/of_reserved_mem.c b/drivers/of/of_reserved_mem.c
> index 366d8c3..d507c35 100644
> --- a/drivers/of/of_reserved_mem.c
> +++ b/drivers/of/of_reserved_mem.c
> @@ -354,6 +354,10 @@ int of_reserved_mem_device_init_by_idx(struct device *dev,
> mutex_lock(&of_rmem_assigned_device_mutex);
> list_add(&rd->list, &of_rmem_assigned_device_list);
> mutex_unlock(&of_rmem_assigned_device_mutex);
> + /* ensure that dma_ops is set for virtual devices
> + * using reserved memory
> + */
> + of_dma_configure(dev, np);
>
> dev_info(dev, "assigned reserved memory node %s\n", rmem->name);
> } else {
Best regards
--
Marek Szyprowski, PhD
Samsung R&D Institute Poland
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^ permalink raw reply
* [PATCH v2 1/8] PM / devfreq: exynos-bus: Add the detailed correlation for Exynos5433
From: Chanwoo Choi @ 2016-12-28 11:56 UTC (permalink / raw)
To: myungjoo.ham, kyungmin.park
Cc: chanwoo, rjw, linux-pm, linux-kernel, Chanwoo Choi, Rob Herring,
Kukjin Kim, Krzysztof Kozlowski, Javier Martinez Canillas,
linux-samsung-soc, devicetree
In-Reply-To: <1482926212-19223-1-git-send-email-cw00.choi@samsung.com>
This patch adds the detailed corrleation between sub-blocks and VDD_INT power
line for Exynos5433. VDD_INT provided the power source to INT (Internal) block.
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Kukjin Kim <kgene@kernel.org>
Cc: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Javier Martinez Canillas <javier@osg.samsung.com>
Cc: linux-samsung-soc@vger.kernel.org
Cc: devicetree@vger.kernel.org
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
---
Documentation/devicetree/bindings/devfreq/exynos-bus.txt | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
index d3ec8e676b6b..d085ef90d27c 100644
--- a/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
+++ b/Documentation/devicetree/bindings/devfreq/exynos-bus.txt
@@ -123,6 +123,20 @@ Detailed correlation between sub-blocks and power line according to Exynos SoC:
|--- FSYS
|--- FSYS2
+- In case of Exynos5433, there is VDD_INT power line as following:
+ VDD_INT |--- G2D (parent device)
+ |--- MSCL
+ |--- GSCL
+ |--- JPEG
+ |--- MFC
+ |--- HEVC
+ |--- BUS0
+ |--- BUS1
+ |--- BUS2
+ |--- PERIS (Fixed clock rate)
+ |--- PERIC (Fixed clock rate)
+ |--- FSYS (Fixed clock rate)
+
Example1:
Show the AXI buses of Exynos3250 SoC. Exynos3250 divides the buses to
power line (regulator). The MIF (Memory Interface) AXI bus is used to
--
1.9.1
^ permalink raw reply related
* Re: [PATCH 2/2] iio: misc: add support for GPIO power switches
From: Linus Walleij @ 2016-12-28 12:50 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Rob Herring, Mark Rutland,
linux-iio@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, Kevin Hilman, Patrick Titiano,
Neil Armstrong, Alexandre Courbot, linux-gpio@vger.kernel.org,
Sebastian Reichel, linux-pm@vger.kernel.org, Mark Brown
In-Reply-To: <1481494905-18037-3-git-send-email-bgolaszewski@baylibre.com>
On Sun, Dec 11, 2016 at 11:21 PM, Bartosz Golaszewski
<bgolaszewski@baylibre.com> wrote:
> Some power-measuring ADCs work together with power load switches which
> allow to power-cycle measured devices.
>
> An example use case would be measuring the power consumption of a
> development board during boot using a power monitor such as TI INA226
> and power-cycling the board remotely using a TPS229* power switch.
>
> Add an iio driver for simple GPIO power switches and expose a sysfs
> attribute allowing to toggle their state.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
I don't get this, isn't this doing the same as
drivers/power/reset/gpio-poweroff.c
?
With the only difference that the latter uses the standard syscall
from pm_power_off to reboot the system instead of some random
sysfs file.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 1/2] devicetree: power: add bindings for GPIO-driven power switches
From: Linus Walleij @ 2016-12-28 12:52 UTC (permalink / raw)
To: Bartosz Golaszewski
Cc: Jonathan Cameron, Hartmut Knaack, Lars-Peter Clausen,
Peter Meerwald-Stadler, Rob Herring, Mark Rutland,
linux-iio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Kevin Hilman, Patrick Titiano, Neil Armstrong, Alexandre Courbot,
linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Sebastian Reichel,
linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, Mark Brown
In-Reply-To: <1481494905-18037-2-git-send-email-bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On Sun, Dec 11, 2016 at 11:21 PM, Bartosz Golaszewski
<bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org> wrote:
> Some boards are equipped with simple, GPIO-driven power load switches.
> An example of such ICs is the TI tps229* series.
>
> Add device tree bindings allowing to describe them.
>
> Signed-off-by: Bartosz Golaszewski <bgolaszewski-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
(...)
> .../bindings/power/gpio-power-switch.txt | 25 ++++++++++++++++++++++
Scrap this and use:
Documentation/devicetree/bindings/power/reset/gpio-poweroff.txt
Yours,
Linus Walleij
^ permalink raw reply
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