* Re: [PATCH 6/6] arm64: dts: sunxi: add support for the Orange Pi PC 2 board
From: Maxime Ripard @ 2017-01-05 22:13 UTC (permalink / raw)
To: Icenowy Zheng
Cc: Linus Walleij, Chen-Yu Tsai, Rob Herring, Andre Przywara,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161226171156.11605-3-icenowy-ymACFijhrKM@public.gmane.org>
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On Tue, Dec 27, 2016 at 01:11:56AM +0800, Icenowy Zheng wrote:
> From: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>
> The Orange Pi PC 2 is a typical single board computer using the
> Allwinner H5 SoC. Apart from the usual suspects it features three
> separately driven USB ports and a Gigabit Ethernet port.
> Also it has a SPI NOR flash soldered, from which the board can boot
> from. This enables the SBC to behave like a "real computer" with
> built-in firmware.
>
> Add the board specific .dts file, which includes the H5 .dtsi and
> enables the peripherals that we support so far.
>
> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
> Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> ---
> arch/arm64/boot/dts/allwinner/Makefile | 1 +
> .../boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts | 183 +++++++++++++++++++++
> 2 files changed, 184 insertions(+)
> create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
>
> diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/allwinner/Makefile
> index 1e29a5ae8282..b26bb46b934c 100644
> --- a/arch/arm64/boot/dts/allwinner/Makefile
> +++ b/arch/arm64/boot/dts/allwinner/Makefile
> @@ -1,4 +1,5 @@
> dtb-$(CONFIG_ARCH_SUNXI) += sun50i-a64-pine64-plus.dtb sun50i-a64-pine64.dtb
> +dtb-$(CONFIG_ARCH_SUNXI) += sun50i-h5-orangepi-pc2.dtb
>
> always := $(dtb-y)
> subdir-y := $(dts-dirs)
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
> new file mode 100644
> index 000000000000..a29ca6b274bb
> --- /dev/null
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h5-orangepi-pc2.dts
> @@ -0,0 +1,183 @@
> +/*
> + * Copyright (C) 2016 ARM Ltd.
> + *
> + * This file is dual-licensed: you can use it either under the terms
> + * of the GPL or the X11 license, at your option. Note that this dual
> + * licensing only applies to this file, and not this project as a
> + * whole.
> + *
> + * a) This file is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License as
> + * published by the Free Software Foundation; either version 2 of the
> + * License, or (at your option) any later version.
> + *
> + * This file is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
> + * GNU General Public License for more details.
> + *
> + * Or, alternatively,
> + *
> + * b) Permission is hereby granted, free of charge, to any person
> + * obtaining a copy of this software and associated documentation
> + * files (the "Software"), to deal in the Software without
> + * restriction, including without limitation the rights to use,
> + * copy, modify, merge, publish, distribute, sublicense, and/or
> + * sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following
> + * conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> + * included in all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
> + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
> + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
> + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
> + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +
> +/dts-v1/;
> +#include "sun50i-h5.dtsi"
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/pinctrl/sun4i-a10.h>
> +
> +/ {
> + model = "Xunlong Orange Pi PC 2";
> + compatible = "xunlong,orangepi-pc2", "allwinner,sun50i-h5";
> +
> + reg_vcc3v3: vcc3v3 {
> + compatible = "regulator-fixed";
> + regulator-name = "vcc3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> +
> + aliases {
> + serial0 = &uart0;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +
> + leds {
> + compatible = "gpio-leds";
> + pinctrl-names = "default";
> + pinctrl-0 = <&leds_opc>, <&leds_r_opc>;
There's no need to declare the LED GPIO in pinctrl.
> +
> + pwr_led {
> + label = "orangepi:green:pwr";
> + gpios = <&r_pio 0 10 GPIO_ACTIVE_HIGH>;
> + default-state = "on";
> + };
> +
> + status_led {
> + label = "orangepi:red:status";
> + gpios = <&pio 0 15 GPIO_ACTIVE_HIGH>;
> + };
> + };
> +
> + r_gpio_keys {
> + compatible = "gpio-keys";
> + pinctrl-names = "default";
> + pinctrl-0 = <&sw_r_opc>;
Ditto
> +
> + sw4 {
> + label = "sw4";
> + linux,code = <BTN_0>;
> + gpios = <&r_pio 0 3 GPIO_ACTIVE_LOW>;
> + };
> + };
> +};
> +
> +&ehci1 {
> + status = "okay";
> +};
> +
> +&ehci2 {
> + status = "okay";
> +};
> +
> +&ehci3 {
> + status = "okay";
> +};
> +
> +&ir {
> + pinctrl-names = "default";
> + pinctrl-0 = <&ir_pins_a>;
> + status = "okay";
> +};
> +
> +&mmc0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins_a>, <&mmc0_cd_pin>;
Ditto
> + vmmc-supply = <®_vcc3v3>;
> + bus-width = <4>;
> + cd-gpios = <&pio 5 6 GPIO_ACTIVE_HIGH>; /* PF6 */
> + cd-inverted;
Do you need both the GPIO flag and the cd-inverted one?
Thanks,
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
^ permalink raw reply
* Re: [PATCH v2 05/19] ARM: dts: imx6-sabresd: add OV5642 and OV5640 camera sensors
From: Steve Longerbeam @ 2017-01-05 22:30 UTC (permalink / raw)
To: Vladimir Zapolskiy, shawnguo, kernel, fabio.estevam, robh+dt,
mark.rutland, linux, mchehab, gregkh, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-media, devel,
Steve Longerbeam
In-Reply-To: <c8c09060-dd6b-f495-da7d-b1f9fad79b89@mentor.com>
On 01/04/2017 04:33 AM, Vladimir Zapolskiy wrote:
>
>> +
>> + camera: ov5642@3c {
> ov5642: camera@3c
done.
>> + pwdn-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>; /* SD1_DAT0 */
>> + reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; /* SD1_DAT1 */
> Comments about SD1_* pad names are redundant.
sure, removed.
>> + status = "disabled";
> Why is it disabled here?
It's explained in the header. I don't yet have the OV5642 module for
the sabresd for testing, so it is disabled for now.
>> +
>> + mipi_camera: ov5640@3c {
> ov5640: camera@3c
done.
>
>> + pwdn-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; /* SD1_DAT2 */
>> + reset-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>; /* SD1_CLK */
> Comments about SD1_* pad names are redundant.
removed.
>> +
>> + pinctrl_ipu1_csi0: ipu1grp-csi0 {
> Please rename the node name to ipu1csi0grp.
>
> Please add new pin control groups preserving the alphanimerical order.
done and done.
Steve
^ permalink raw reply
* Re: [PATCH v2 09/19] ARM: dts: imx6-sabreauto: add the ADV7180 video decoder
From: Steve Longerbeam @ 2017-01-05 22:31 UTC (permalink / raw)
To: Vladimir Zapolskiy, shawnguo, kernel, fabio.estevam, robh+dt,
mark.rutland, linux, mchehab, gregkh, p.zabel
Cc: linux-arm-kernel, devicetree, linux-kernel, linux-media, devel,
Steve Longerbeam
In-Reply-To: <acbdc873-3166-f56d-e6d1-948becb1a57c@mentor.com>
On 01/04/2017 04:41 AM, Vladimir Zapolskiy wrote:
> On 01/03/2017 10:57 PM, Steve Longerbeam wrote:
>> +
>> + camera: adv7180@21 {
> adv7180: camera@21
done.
>>
>> + pinctrl_ipu1_csi0: ipu1grp-csi0 {
> Please rename node name to ipu1csi0grp.
done.
Steve
^ permalink raw reply
* Re: Re: [PATCH 3/6] clk: sunxi-ng: Add H5 clocks
From: Icenowy Zheng @ 2017-01-05 22:48 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andre Przywara,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA, Linus Walleij,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Chen-Yu Tsai
2017年1月6日 06:04于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
>
> On Tue, Dec 27, 2016 at 12:25:15AM +0800, Icenowy Zheng wrote:
> > Add the H5 CCU clocks set based on the H3 one.
> >
> > Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
>
> Is there any difference with H3's?
One more Transport Stream controller, so one more bus gate and bus reset for it.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> --
> You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
> To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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--
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To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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^ permalink raw reply
* Re: Re: [PATCH 1/6] drivers: pinctrl: add driver for Allwinner H5 SoC
From: Icenowy Zheng @ 2017-01-05 22:49 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, Andre Przywara,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA, Linus Walleij,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw, Chen-Yu Tsai
2017年1月6日 06:08于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
>
> On Tue, Dec 27, 2016 at 12:25:13AM +0800, Icenowy Zheng wrote:
> > Based on the Allwinner H5 datasheet and the pinctrl driver of the
> > backward-compatible H3 this introduces the pin multiplex assignments for
> > the H5 SoC.
> >
> > H5 introduced some more pin functions (e.g. three more groups of TS
> > pins, and one more groups of SIM pins) than H3.
> >
> > Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> > ---
> > .../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
> > drivers/pinctrl/sunxi/Kconfig | 4 +
> > drivers/pinctrl/sunxi/Makefile | 1 +
> > drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c | 551 +++++++++++++++++++++
> > 4 files changed, 557 insertions(+)
> > create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> >
> > diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > index c931fb1c01a6..2fd688c8dbdb 100644
> > --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sunxi-pinctrl.txt
> > @@ -23,6 +23,7 @@ Required properties:
> > "allwinner,sun8i-h3-pinctrl"
> > "allwinner,sun8i-h3-r-pinctrl"
> > "allwinner,sun50i-a64-pinctrl"
> > + "allwinner,sun50i-h5-r-pinctrl"
>
> You're using a different compatible in your driver.
oh... just drop "-r".
R_PIO in H5 is the same with H3.
>
> > "nextthing,gr8-pinctrl"
> >
> > - reg: Should contain the register physical address and length for the
> > diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig
> > index bff1ffc6f01e..e9c47e8b2ee0 100644
> > --- a/drivers/pinctrl/sunxi/Kconfig
> > +++ b/drivers/pinctrl/sunxi/Kconfig
> > @@ -76,4 +76,8 @@ config PINCTRL_SUN50I_A64
> > bool
> > select PINCTRL_SUNXI
> >
> > +config PINCTRL_SUN50I_H5
> > + bool
> > + select PINCTRL_SUNXI
> > +
> > endif
> > diff --git a/drivers/pinctrl/sunxi/Makefile b/drivers/pinctrl/sunxi/Makefile
> > index 95f93d0561fc..bab215d25440 100644
> > --- a/drivers/pinctrl/sunxi/Makefile
> > +++ b/drivers/pinctrl/sunxi/Makefile
> > @@ -17,5 +17,6 @@ obj-$(CONFIG_PINCTRL_SUN50I_A64) += pinctrl-sun50i-a64.o
> > obj-$(CONFIG_PINCTRL_SUN8I_A83T) += pinctrl-sun8i-a83t.o
> > obj-$(CONFIG_PINCTRL_SUN8I_H3) += pinctrl-sun8i-h3.o
> > obj-$(CONFIG_PINCTRL_SUN8I_H3_R) += pinctrl-sun8i-h3-r.o
> > +obj-$(CONFIG_PINCTRL_SUN50I_H5) += pinctrl-sun50i-h5.o
> > obj-$(CONFIG_PINCTRL_SUN9I_A80) += pinctrl-sun9i-a80.o
> > obj-$(CONFIG_PINCTRL_SUN9I_A80_R) += pinctrl-sun9i-a80-r.o
> > diff --git a/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> > new file mode 100644
> > index 000000000000..67a55df37782
> > --- /dev/null
> > +++ b/drivers/pinctrl/sunxi/pinctrl-sun50i-h5.c
> > @@ -0,0 +1,551 @@
> > +/*
> > + * Allwinner H5 SoC pinctrl driver.
> > + *
> > + * Copyright (C) 2016 Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> > + *
> > + * Based on pinctrl-sun8i-h3.c, which is:
> > + * Copyright (C) 2015 Jens Kuske <jenskuske-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
> > + *
> > + * Based on pinctrl-sun8i-a23.c, which is:
> > + * Copyright (C) 2014 Chen-Yu Tsai <wens-jdAy2FN1RRM@public.gmane.org>
> > + * Copyright (C) 2014 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
> > + *
> > + * This file is licensed under the terms of the GNU General Public
> > + * License version 2. This program is licensed "as is" without any
> > + * warranty of any kind, whether express or implied.
> > + */
> > +
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/pinctrl/pinctrl.h>
> > +
> > +#include "pinctrl-sunxi.h"
> > +
> > +static const struct sunxi_desc_pin sun50i_h5_pins[] = {
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart2"), /* TX */
> > + SUNXI_FUNCTION(0x3, "jtag"), /* MS */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 0)), /* PA_EINT0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart2"), /* RX */
> > + SUNXI_FUNCTION(0x3, "jtag"), /* CK */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 1)), /* PA_EINT1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart2"), /* RTS */
> > + SUNXI_FUNCTION(0x3, "jtag"), /* DO */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 2)), /* PA_EINT2 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart2"), /* CTS */
> > + SUNXI_FUNCTION(0x3, "jtag"), /* DI */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 3)), /* PA_EINT3 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart0"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 4)), /* PA_EINT4 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart0"), /* RX */
> > + SUNXI_FUNCTION(0x3, "pwm0"),
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 5)), /* PA_EINT5 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "sim"), /* PWREN */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 6)), /* PA_EINT6 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 7),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "sim"), /* CLK */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 7)), /* PA_EINT7 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 8),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "sim"), /* DATA */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 8)), /* PA_EINT8 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 9),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "sim"), /* RST */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 9)), /* PA_EINT9 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 10),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "sim"), /* DET */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 10)), /* PA_EINT10 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 11),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2c0"), /* SCK */
> > + SUNXI_FUNCTION(0x3, "di"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 11)), /* PA_EINT11 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 12),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2c0"), /* SDA */
> > + SUNXI_FUNCTION(0x3, "di"), /* RX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 12)), /* PA_EINT12 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 13),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "spi1"), /* CS */
> > + SUNXI_FUNCTION(0x3, "uart3"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 13)), /* PA_EINT13 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 14),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "spi1"), /* CLK */
> > + SUNXI_FUNCTION(0x3, "uart3"), /* RX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 14)), /* PA_EINT14 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 15),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "spi1"), /* MOSI */
> > + SUNXI_FUNCTION(0x3, "uart3"), /* RTS */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 15)), /* PA_EINT15 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 16),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "spi1"), /* MISO */
> > + SUNXI_FUNCTION(0x3, "uart3"), /* CTS */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 16)), /* PA_EINT16 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 17),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "spdif"), /* OUT */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 17)), /* PA_EINT17 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 18),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s0"), /* SYNC */
> > + SUNXI_FUNCTION(0x3, "i2c1"), /* SCK */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 18)), /* PA_EINT18 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 19),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s0"), /* CLK */
> > + SUNXI_FUNCTION(0x3, "i2c1"), /* SDA */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 19)), /* PA_EINT19 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 20),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s0"), /* DOUT */
> > + SUNXI_FUNCTION(0x3, "sim"), /* VPPEN */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 20)), /* PA_EINT20 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(A, 21),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s0"), /* DIN */
> > + SUNXI_FUNCTION(0x3, "sim"), /* VPPPP */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 0, 21)), /* PA_EINT21 */
> > + /* Hole */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* WE */
> > + SUNXI_FUNCTION(0x3, "spi0")), /* MOSI */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* ALE */
> > + SUNXI_FUNCTION(0x3, "spi0"), /* MISO */
> > + SUNXI_FUNCTION(0x4, "mmc2")), /* DS */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* CLE */
> > + SUNXI_FUNCTION(0x3, "spi0")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* CE1 */
> > + SUNXI_FUNCTION(0x3, "spi0")), /* CS */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* CE0 */
> > + SUNXI_FUNCTION(0x4, "spi0")), /* MISO */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* RE */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* RB0 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* CMD */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 7),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0")), /* RB1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 8),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ0 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 9),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ1 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 10),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ2 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D2 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 11),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ3 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D3 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ4 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ5 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ6 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQ7 */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
> > + SUNXI_FUNCTION(0x3, "mmc2")), /* RST */
> > + /* Hole */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXD3 */
> > + SUNXI_FUNCTION(0x3, "di"), /* TX */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXD2 */
> > + SUNXI_FUNCTION(0x3, "di"), /* RX */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* ERR */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXD1 */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* SYNC */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXD0 */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* DVLD */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXCK */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* D0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXCTL/RXDV */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* D1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* RXERR */
> > + SUNXI_FUNCTION(0x4, "ts2")), /* D2 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 7),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXD3 */
> > + SUNXI_FUNCTION(0x4, "ts2"), /* D3 */
> > + SUNXI_FUNCTION(0x5, "ts3")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 8),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXD2 */
> > + SUNXI_FUNCTION(0x4, "ts2"), /* D4 */
> > + SUNXI_FUNCTION(0x5, "ts3")), /* ERR */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 9),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXD1 */
> > + SUNXI_FUNCTION(0x4, "ts2"), /* D5 */
> > + SUNXI_FUNCTION(0x5, "ts3")), /* SYNC */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 10),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXD0 */
> > + SUNXI_FUNCTION(0x4, "ts2"), /* D6 */
> > + SUNXI_FUNCTION(0x5, "ts3")), /* DVLD */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 11),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* CRS */
> > + SUNXI_FUNCTION(0x4, "ts2"), /* D7 */
> > + SUNXI_FUNCTION(0x5, "ts3")), /* D0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 12),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXCK */
> > + SUNXI_FUNCTION(0x4, "sim")), /* PWREN */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 13),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXCTL/TXEN */
> > + SUNXI_FUNCTION(0x4, "sim")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 14),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* TXERR */
> > + SUNXI_FUNCTION(0x4, "sim")), /* DATA */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 15),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* CLKIN/COL */
> > + SUNXI_FUNCTION(0x4, "sim")), /* RST */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 16),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac"), /* MDC */
> > + SUNXI_FUNCTION(0x4, "sim")), /* DET */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(D, 17),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "emac")), /* MDIO */
> > + /* Hole */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* PCLK */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* MCLK */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* ERR */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* HSYNC */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* SYNC */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* VSYNC */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* DVLD */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D0 */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* D0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D1 */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* D1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D2 */
> > + SUNXI_FUNCTION(0x3, "ts0")), /* D2 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 7),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D3 */
> > + SUNXI_FUNCTION(0x3, "ts0"), /* D3 */
> > + SUNXI_FUNCTION(0x4, "ts1")), /* CLK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 8),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D4 */
> > + SUNXI_FUNCTION(0x3, "ts0"), /* D4 */
> > + SUNXI_FUNCTION(0x4, "ts1")), /* ERR */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 9),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D5 */
> > + SUNXI_FUNCTION(0x3, "ts0"), /* D5 */
> > + SUNXI_FUNCTION(0x4, "ts1")), /* SYNC */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 10),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D6 */
> > + SUNXI_FUNCTION(0x3, "ts0"), /* D6 */
> > + SUNXI_FUNCTION(0x4, "ts1")), /* DVLD */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 11),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* D7 */
> > + SUNXI_FUNCTION(0x3, "ts"), /* D7 */
> > + SUNXI_FUNCTION(0x4, "ts1")), /* D0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 12),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* SCK */
> > + SUNXI_FUNCTION(0x3, "i2c2")), /* SCK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 13),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "csi"), /* SDA */
> > + SUNXI_FUNCTION(0x3, "i2c2")), /* SDA */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 14),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x3, "sim")), /* VPPEN */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(E, 15),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x3, "sim")), /* VPPPP */
> > + /* Hole */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* D1 */
> > + SUNXI_FUNCTION(0x3, "jtag")), /* MS */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* D0 */
> > + SUNXI_FUNCTION(0x3, "jtag")), /* DI */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* CLK */
> > + SUNXI_FUNCTION(0x3, "uart0")), /* TX */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* CMD */
> > + SUNXI_FUNCTION(0x3, "jtag")), /* DO */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* D3 */
> > + SUNXI_FUNCTION(0x3, "uart0")), /* RX */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc0"), /* D2 */
> > + SUNXI_FUNCTION(0x3, "jtag")), /* CK */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(F, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out")),
> > + /* Hole */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 0),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* CLK */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 0)), /* PG_EINT0 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 1),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* CMD */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 1)), /* PG_EINT1 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 2),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* D0 */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 2)), /* PG_EINT2 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 3),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* D1 */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 3)), /* PG_EINT3 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 4),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* D2 */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 4)), /* PG_EINT4 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 5),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "mmc1"), /* D3 */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 5)), /* PG_EINT5 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 6),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart1"), /* TX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 6)), /* PG_EINT6 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 7),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart1"), /* RX */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 7)), /* PG_EINT7 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 8),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart1"), /* RTS */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 8)), /* PG_EINT8 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 9),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "uart1"), /* CTS */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 9)), /* PG_EINT9 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 10),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s1"), /* SYNC */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 10)), /* PG_EINT10 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 11),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s1"), /* CLK */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 11)), /* PG_EINT11 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 12),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s1"), /* DOUT */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 12)), /* PG_EINT12 */
> > + SUNXI_PIN(SUNXI_PINCTRL_PIN(G, 13),
> > + SUNXI_FUNCTION(0x0, "gpio_in"),
> > + SUNXI_FUNCTION(0x1, "gpio_out"),
> > + SUNXI_FUNCTION(0x2, "i2s1"), /* DIN */
> > + SUNXI_FUNCTION_IRQ_BANK(0x6, 1, 13)), /* PG_EINT13 */
> > +};
> > +
> > +static const struct sunxi_pinctrl_desc sun50i_h5_pinctrl_data = {
> > + .pins = sun50i_h5_pins,
> > + .npins = ARRAY_SIZE(sun50i_h5_pins),
> > + .irq_banks = 2,
> > + .irq_read_needs_mux = true
> > +};
> > +
> > +static int sun50i_h5_pinctrl_probe(struct platform_device *pdev)
> > +{
> > + return sunxi_pinctrl_init(pdev,
> > + &sun50i_h5_pinctrl_data);
> > +}
> > +
> > +static const struct of_device_id sun50i_h5_pinctrl_match[] = {
> > + { .compatible = "allwinner,sun50i-h5-pinctrl", },
> > + {}
> > +};
> > +
> > +static struct platform_driver sun50i_h5_pinctrl_driver = {
> > + .probe = sun50i_h5_pinctrl_probe,
> > + .driver = {
> > + .name = "sun50i-h5-pinctrl",
> > + .of_match_table = sun50i_h5_pinctrl_match,
> > + },
> > +};
> > +builtin_platform_driver(sun50i_h5_pinctrl_driver);
>
> This also looks very much like the H3. I'll post a patchset during the
> weekend to avoid duplicating those drivers. This was initially done
> for the sun5i, but it very much applies here.
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
>
> --
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^ permalink raw reply
* Re: [PATCHv2 1/5] clk: mvebu: support for 98DX3236 SoC
From: Chris Packham @ 2017-01-05 23:05 UTC (permalink / raw)
To: Mark Rutland
Cc: Thomas Petazzoni, devicetree@vger.kernel.org, Michael Turquette,
Stephen Boyd, linux-kernel@vger.kernel.org, Rob Herring,
Gregory CLEMENT, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170105135302.GB25333@leverpostej>
On 06/01/17 03:01, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 04:36:37PM +1300, Chris Packham wrote:
>> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
>> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>>
>> The clock gating options are a subset of those on the Armada XP.
>>
>> The core clock divider is different to the Armada XP also.
>>
>> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
>> ---
>> Changes in v2:
>> - Update devicetree binding documentation for new compatible string
>>
>> .../devicetree/bindings/clock/mvebu-cpu-clock.txt | 1 +
>> drivers/clk/mvebu/Makefile | 2 +-
>> drivers/clk/mvebu/armada-xp.c | 42 +++++
>> drivers/clk/mvebu/clk-cpu.c | 33 +++-
>> drivers/clk/mvebu/mv98dx3236-corediv.c | 207 +++++++++++++++++++++
>> 5 files changed, 281 insertions(+), 4 deletions(-)
>> create mode 100644 drivers/clk/mvebu/mv98dx3236-corediv.c
>
>
> It looks like you also need to update
> Documentation/devicetree/bindings/clock/mvebu-corediv-clock.txt for the
> addition of "marvell,mv98dx3236-corediv-clock".
Will do.
>
>>
>> diff --git a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>> index 99c214660bdc..7f28506eaee7 100644
>> --- a/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>> +++ b/Documentation/devicetree/bindings/clock/mvebu-cpu-clock.txt
>> @@ -3,6 +3,7 @@ Device Tree Clock bindings for cpu clock of Marvell EBU platforms
>> Required properties:
>> - compatible : shall be one of the following:
>> "marvell,armada-xp-cpu-clock" - cpu clocks for Armada XP
>> + "marvell,mv98dx3236-cpu-clock" - cpu clocks for 98DX3236 SoC
>> - reg : Address and length of the clock complex register set, followed
>> by address and length of the PMU DFS registers
>> - #clock-cells : should be set to 1.
>
> [...]
>
>> +static void __init mv98dx3236_corediv_clk_init(struct device_node *node)
>> +{
>> + struct clk_init_data init;
>> + struct clk_corediv *corediv;
>> + struct clk **clks;
>> + void __iomem *base;
>> + const __be32 *off;
>> + const char *parent_name;
>> + const char *clk_name;
>> + int len;
>> + struct device_node *dfx_node;
>> +
>> + dfx_node = of_parse_phandle(node, "base", 0);
>> + if (WARN_ON(!dfx_node))
>
> What's going on here? The existing bingings don't mention a "base"
> phandle, and nothing was added to describe it.
>
>> + return;
>> +
>> + off = of_get_property(node, "reg", &len);
>> + if (WARN_ON(!off))
>> + return;
>
> Please don't use of_get_property directly; generally you should use the
> existing higher-level helpers like of_proeprty_read_u32().
>
>> +
>> + base = of_iomap(dfx_node, 0);
>> + if (WARN_ON(!base))
>> + return;
>> +
>> + of_node_put(dfx_node);
>> +
>> + parent_name = of_clk_get_parent_name(node, 0);
>> +
>> + clk_data.clk_num = 1;
>> +
>> + /* clks holds the clock array */
>> + clks = kcalloc(clk_data.clk_num, sizeof(struct clk *),
>> + GFP_KERNEL);
>> + if (WARN_ON(!clks))
>> + goto err_unmap;
>> + /* corediv holds the clock specific array */
>> + corediv = kcalloc(clk_data.clk_num, sizeof(struct clk_corediv),
>> + GFP_KERNEL);
>> + if (WARN_ON(!corediv))
>> + goto err_free_clks;
>> +
>> + spin_lock_init(&corediv->lock);
>> +
>> + of_property_read_string_index(node, "clock-output-names",
>> + 0, &clk_name);
>> +
>> + init.num_parents = 1;
>> + init.parent_names = &parent_name;
>> + init.name = clk_name;
>> + init.ops = &ops;
>> + init.flags = 0;
>> +
>> + corediv[0].reg = (void *)((int)base + be32_to_cpu(*off));
>
> I don't understand this, but I guess this has something to do with that
> base phandle. Is the corediv clock a sub-component of some "base" clock?
> I don't think this binding is the best way of describing that.
Actually once I've got things setup correctly via the dts I only need
some minor modification to mvebu/clk-corediv.c to handle the differences
in the bit fields used.
>
> Thanks,
> Mark.
>
^ permalink raw reply
* Re: [PATCH net-next v4 0/4] Fix OdroidC2 Gigabit Tx link issue
From: Russell King - ARM Linux @ 2017-01-05 23:25 UTC (permalink / raw)
To: Florian Fainelli
Cc: devicetree, Alexandre TORGUE, Neil Armstrong, Martin Blumenstingl,
netdev, Giuseppe Cavallaro, linux-kernel, Yegor Yefremov,
Julia Lawall, Andre Roth, Andrew Lunn, Kevin Hilman, Carlo Caione,
linux-amlogic, Andreas Färber, linux-arm-kernel,
Jerome Brunet
In-Reply-To: <049b1efc-3bad-92e0-45ef-0563dc5d81de@gmail.com>
On Mon, Nov 28, 2016 at 09:54:28AM -0800, Florian Fainelli wrote:
> If we start supporting generic "enable", "disable" type of properties
> with values that map directly to register definitions of the HW, we
> leave too much room for these properties to be utilized to implement a
> specific policy, and this is not acceptable.
Another concern with this patch is that the existing phylib "set_eee"
code is horribly buggy - it just translates the modes from userspace
into the register value and writes them directly to the register with
no validation. So it's possible to set modes in the register that the
hardware doesn't support, and have them advertised to the link partner.
I have a patch which fixes that, restricting (as we do elsewhere) the
advert according to the EEE supported capabilities retrieved from the
PCS - maybe the problem here is that the PCS doesn't support support
EEE in 1000baseT mode?
Out of interest, which PHY is used on this platform?
On the SolidRun boards, they're using AR8035, and have suffered this
occasional link drop problem. What has been found is that it seems to
be to do with the timing parameters, and it seemed to only be 1000bT
that was affected. I don't remember off hand exactly which or what
the change was they made to stabilise it though, but I can probabily
find out tomorrow.
--
RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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according to speedtest.net.
^ permalink raw reply
* Re: [PATCH 2/5] drivers: mmc: sunxi: limit A64 MMC2 to 8K DMA buffer
From: André Przywara @ 2017-01-05 23:33 UTC (permalink / raw)
To: Maxime Ripard, Rob Herring
Cc: Ulf Hansson, Chen-Yu Tsai, Hans De Goede, Icenowy Zheng,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw,
linux-kernel-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170105175746.fq6crpc3krz7tzxi@lukather>
On 05/01/17 17:57, Maxime Ripard wrote:
> Hi Rob,
>
> On Wed, Jan 04, 2017 at 08:07:50AM -0600, Rob Herring wrote:
>> On Mon, Jan 02, 2017 at 11:03:43PM +0000, Andre Przywara wrote:
>>> From: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>>
>>> Unlike the A64 user manual reports, the third MMC controller on the
>>> A64 (and the only one capable of 8-bit HS400 eMMC transfers) has a
>>> DMA buffer size limit of 8KB (much like the very old Allwinner SoCs).
>>> This does not affect the other two controllers, so introduce a new
>>> DT compatible string to let the driver use different settings for that
>>> particular device. This will also help to enable the high-speed transfer
>>> modes of that controller later.
>>>
>>> Signed-off-by: Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>
>>> Signed-off-by: Andre Przywara <andre.przywara-5wv7dgnIgG8@public.gmane.org>
>>> ---
>>> Documentation/devicetree/bindings/mmc/sunxi-mmc.txt | 1 +
>>> drivers/mmc/host/sunxi-mmc.c | 7 +++++++
>>> 2 files changed, 8 insertions(+)
>>
>> Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>
> Some kind of a digression on this: we have three MMC controllers on
> this SoC. Like this patch shows, the third one is clearly different,
> and supports both more modes, a wider bus, and specific quirks. We
> need a new compatible for this one, everything's perfect.
>
> However, the other two are mostly the same, but seems to need
> different tuning parameters to get more performances out of the
> controller (but this is unclear yet). How do we usually deal with
> that?
I guess you wanted to hear Rob's opinion ;-), but "get more performance"
sounds like we add one (or more) properties to tune those values.
If I get this right, it works with default values, but is sub-optimal?
Cheers,
Andre.
^ permalink raw reply
* Re: [PATCHv3] mfd: cpcap: Add minimal support
From: Tony Lindgren @ 2017-01-06 0:08 UTC (permalink / raw)
To: Lee Jones
Cc: Samuel Ortiz, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Marcel Partap, Mark Rutland,
Michael Scott
In-Reply-To: <20170103163515.GM2977@dell>
* Lee Jones <lee.jones-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> [170103 08:32]:
> On Mon, 05 Dec 2016, Tony Lindgren wrote:
> > +static int cpcap_init_irq_chip(struct cpcap_ddata *cpcap, int irq_chip,
> > + int irq_start, int nr_irqs)
> > +{
> > + struct regmap_irq_chip *chip = &cpcap_irq_chip[irq_chip];
> > + int i, ret;
> > +
> > + for (i = irq_start; i < irq_start + nr_irqs; i++) {
> > + struct regmap_irq *cpcap_irq = &cpcap->irqs[i];
> > +
> > + cpcap_irq->reg_offset =
> > + ((i - irq_start) / cpcap->regmap_conf->val_bits) *
> > + cpcap->regmap_conf->reg_stride;
> > + cpcap_irq->mask = BIT(i % cpcap->regmap_conf->val_bits);
>
> If a code segment takes more than a few seconds to work out, it's
> either too cluttered (break it down), too complex (simplify it) or if
> neither of the first two approaches are possible, then a comment is
> required.
Hmm yeah I could not read that myself any longer :) Will split.
> > +static int cpcap_probe(struct spi_device *spi)
> > +{
> > + const struct of_device_id *match;
> > + int ret = -EINVAL;
>
> What is the purpose of initialising ret?
Seems to be not needed.
> > + struct cpcap_ddata *cpcap;
> > +
> > + match = of_match_device(of_match_ptr(cpcap_of_match), &spi->dev);
> > + if (!match)
> > + return -ENODEV;
> > +
> > + cpcap = devm_kzalloc(&spi->dev, sizeof(*cpcap), GFP_KERNEL);
> > + if (!cpcap)
> > + return -ENOMEM;
> > +
> > + cpcap->spi = spi;
> > + spi_set_drvdata(spi, cpcap);
> > +
> > + spi->bits_per_word = 16;
> > + spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
> > +
> > + ret = spi_setup(spi);
> > + if (ret < 0)
> > + return ret;
>
> Is it possible for spi_setup() to return >0?
>
> If not, then "if (!ret)" will do.
You're right, the kerneldoc for spi_setup() says:
"Return: zero on success, else a negative error code."
Need to use "if (ret)" to return on error though, not "if (!ret)".
> > +static struct spi_driver cpcap_driver = {
> > + .driver = {
> > + .name = "cpcap-core",
> > + .of_match_table = cpcap_of_match,
>
> of_match_ptr() ?
Well there needs to be a platform specific init added at least in some
cases. I have not quite yet deciphered what all it does for droid 4
as it's already done for kexec based booting.
> > + * Copyright (C) 2016 Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>.
>
> Actually, it's more traditional to place the CR at the top.
Sure. Will repost v4 shortly.
Thanks,
Tony
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^ permalink raw reply
* Re: [PATCH v2 3/8] ARM: dts: armada-388-clearfog: Utilize new DSA binding
From: Russell King - ARM Linux @ 2017-01-06 0:19 UTC (permalink / raw)
To: Florian Fainelli
Cc: linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Jason Cooper,
Andrew Lunn, Gregory Clement, Sebastian Hesselbarth, Rob Herring,
Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, vivien.didelot-4ysUXcep3aM1wj+D4I0NRVaTQe2KTcn/
In-Reply-To: <20170105192957.14304-4-f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
On Thu, Jan 05, 2017 at 11:29:52AM -0800, Florian Fainelli wrote:
> Utilize the new DSA binding, introduced with commit 8c5ad1d6179d ("net:
> dsa: Document new binding"). The legacy binding node is kept included, but is
> marked disabled.
>
> Signed-off-by: Florian Fainelli <f.fainelli-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
Booted here on clearfog, and tested traffic passes between two lan
ports, and a lan port and the cpu port... and generally still seems
to work as a switch. All seems well on the face of it.
Acked-by: Russell King <rmk+kernel-I+IVW8TIWO2tmTQ+vhA3Yw@public.gmane.org>
Thanks.
> ---
> arch/arm/boot/dts/armada-388-clearfog.dts | 65 +++++++++++++++++++++++++++++++
> 1 file changed, 65 insertions(+)
>
> diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts b/arch/arm/boot/dts/armada-388-clearfog.dts
> index 71ce201c903e..40ec6d768669 100644
> --- a/arch/arm/boot/dts/armada-388-clearfog.dts
> +++ b/arch/arm/boot/dts/armada-388-clearfog.dts
> @@ -351,6 +351,8 @@
> };
>
> dsa@0 {
> + status = "disabled";
> +
> compatible = "marvell,dsa";
> dsa,ethernet = <ð1>;
> dsa,mii-bus = <&mdio>;
> @@ -444,3 +446,66 @@
> status = "disabled";
> };
> };
> +
> +&mdio {
> + status = "okay";
> +
> + switch@4 {
> + compatible = "marvell,mv88e6085";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <4>;
> + pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
> + pinctrl-names = "default";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + label = "lan5";
> + };
> +
> + port@1 {
> + reg = <1>;
> + label = "lan4";
> + };
> +
> + port@2 {
> + reg = <2>;
> + label = "lan3";
> + };
> +
> + port@3 {
> + reg = <3>;
> + label = "lan2";
> + };
> +
> + port@4 {
> + reg = <4>;
> + label = "lan1";
> + };
> +
> + port@5 {
> + reg = <5>;
> + label = "cpu";
> + ethernet = <ð1>;
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> +
> + port@6 {
> + /* 88E1512 external phy */
> + reg = <6>;
> + label = "lan6";
> + fixed-link {
> + speed = <1000>;
> + full-duplex;
> + };
> + };
> + };
> + };
> +};
> --
> 2.9.3
>
--
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FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
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^ permalink raw reply
* Re: [PATCH v2 1/3] devicetree: property-units: add mWh and mAh units
From: Sebastian Reichel @ 2017-01-06 0:24 UTC (permalink / raw)
To: Matt Ranostay
Cc: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170105021007.22088-2-matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1863 bytes --]
Hi,
On Wed, Jan 04, 2017 at 06:10:05PM -0800, Matt Ranostay wrote:
> Add entries for microwatt-hours and microamp-hours to property
> units.
>
> Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
> ---
> Documentation/devicetree/bindings/property-units.txt | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/property-units.txt b/Documentation/devicetree/bindings/property-units.txt
> index 12278d79f6c0..5e8d220cc2b6 100644
> --- a/Documentation/devicetree/bindings/property-units.txt
> +++ b/Documentation/devicetree/bindings/property-units.txt
> @@ -25,8 +25,10 @@ Distance
> Electricity
> ----------------------------------------
> -microamp : micro amps
> +-microamp-hours : micro amp hours
> -ohms : Ohms
> -micro-ohms : micro Ohms
> +-microwatt-hours: micro Watt hours
> -microvolt : micro volts
>
> Temperature
Acked-By: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
As there is no hard-dependency I expect this goes through the DT
subsystem independently of the remaining patchset. Please ping me,
if I should queue it via the power-supply tree instead.
@Matt: You miss a few CC for this patch:
./scripts/get_maintainer.pl -f Documentation/devicetree/bindings/property-units.txt
Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,commit_signer:1/1=100%,authored:1/1=100%,added_lines:39/39=100%)
Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org> (maintainer:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,commit_signer:1/1=100%)
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS)
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org (open list)
-- Sebastian
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [PATCH 1/2] Documentation: phy: introduce new optional property to specify drive impedance
From: Shawn Lin @ 2017-01-06 0:44 UTC (permalink / raw)
To: Heiko Stübner
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
shawn.lin-TNX95d0MmH7DzftRWevZcw, Douglas Anderson,
Kishon Vijay Abraham I,
linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Rob Herring
In-Reply-To: <11505388.Y1Yzh8HsIT@diego>
On 2017/1/5 19:15, Heiko Stübner wrote:
> Hi Shawn,
>
> Am Donnerstag, 5. Januar 2017, 17:31:21 schrieb Shawn Lin:
>> We need to modify the drive impedance according to the
>> different hardware condition. So let's expose this to
>> the DT.
>>
>> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>>
>> Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 5 +++++
>> 1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
>> b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt index
>> e3ea557..731aeb9 100644
>> --- a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
>> +++ b/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
>> @@ -14,6 +14,11 @@ specified by name:
>> access to it), it is strongly suggested.
>> - clocks: Should have a phandle to the card clock exported by the SDHCI
>> driver.
>>
>> +Optional Properties:
>> +- drive_impedance: Must be one of 33, 40, 50, 66, 100. This property allows
>> + different boards to specify their own drive impedance depending on the
>> + hardware condition.
>
> In what unit are your 33, 40 etc values?
>
> It is recommended that properties should specify their unit, see all the
> properties ending in "-ma", "-ns" and so on and also
> Documentation/devicetree/bindings/property-units.txt
>
> Also properties should use dashes ("-") not underscores.
>
> Judging by the second patch, these are Ohm, so combining the above you
> probably want
>
> drive-impedance-ohms
>
> as property name.
>
> Also the patch subject is slightly misleading and should probably specify the
> rockchip-emmc as well :-)
Thanks, will fix them.
>
>
> Heiko
>
>
>
--
Best Regards
Shawn Lin
^ permalink raw reply
* [PATCHv4] mfd: cpcap: Add minimal support
From: Tony Lindgren @ 2017-01-06 0:44 UTC (permalink / raw)
To: Lee Jones, Samuel Ortiz
Cc: linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Marcel Partap, Mark Rutland,
Michael Scott
Many Motorola phones like droid 4 are using a custom PMIC called CPCAP
or 6556002. We can support it's core features quite easily with regmap_spi
and regmap_irq.
The children of cpcap, such as regulators, ADC and USB, can be just regular
device drivers and defined in the dts file. They get probed as we call
of_platform_populate() at the end of our probe, and then the children
can just call dev_get_regmap(dev.parent, NULL) to get the regmap.
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Cc: Marcel Partap <mpartap-hi6Y0CQ0nG0@public.gmane.org>
Cc: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
Cc: Michael Scott <michael.scott-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Signed-off-by: Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
---
Changes from v2:
- Fix typos in binding documentation for #size-cells and spi-cs-high
- Add ack from Rob
Changes from v3:
- Fix comments from Lee, mostly to simplify cpcap_init_irq_chip()
---
.../devicetree/bindings/mfd/motorola-cpcap.txt | 31 +++
drivers/mfd/Kconfig | 11 +
drivers/mfd/Makefile | 1 +
drivers/mfd/motorola-cpcap.c | 259 ++++++++++++++++++
include/linux/mfd/motorola-cpcap.h | 292 +++++++++++++++++++++
5 files changed, 594 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
create mode 100644 drivers/mfd/motorola-cpcap.c
create mode 100644 include/linux/mfd/motorola-cpcap.h
diff --git a/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
new file mode 100644
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/motorola-cpcap.txt
@@ -0,0 +1,31 @@
+Motorola CPCAP PMIC device tree binding
+
+Required properties:
+- compatible : One or both of "motorola,cpcap" or "ste,6556002"
+- reg : SPI chip select
+- interrupt-parent : The parent interrupt controller
+- interrupts : The interrupt line the device is connected to
+- interrupt-controller : Marks the device node as an interrupt controller
+- #interrupt-cells : The number of cells to describe an IRQ, should be 2
+- #address-cells : Child device offset number of cells, should be 1
+- #size-cells : Child device size number of cells, should be 0
+- spi-max-frequency : Typically set to 3000000
+- spi-cs-high : SPI chip select direction
+
+Example:
+
+&mcspi1 {
+ cpcap: pmic@0 {
+ compatible = "motorola,cpcap", "ste,6556002";
+ reg = <0>; /* cs0 */
+ interrupt-parent = <&gpio1>;
+ interrupts = <7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-max-frequency = <3000000>;
+ spi-cs-high;
+ };
+};
+
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -714,6 +714,17 @@ config EZX_PCAP
This enables the PCAP ASIC present on EZX Phones. This is
needed for MMC, TouchScreen, Sound, USB, etc..
+config MFD_CPCAP
+ tristate "Support for Motorola CPCAP"
+ depends on SPI
+ depends on OF || COMPILE_TEST
+ select REGMAP_SPI
+ select REGMAP_IRQ
+ help
+ Say yes here if you want to include driver for CPCAP.
+ It is used on many Motorola phones and tablets as a PMIC.
+ At least Motorola Droid 4 is known to use CPCAP.
+
config MFD_VIPERBOARD
tristate "Nano River Technologies Viperboard"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -97,6 +97,7 @@ obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o
obj-$(CONFIG_MFD_CORE) += mfd-core.o
obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
+obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o
obj-$(CONFIG_MCP) += mcp-core.o
obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
diff --git a/drivers/mfd/motorola-cpcap.c b/drivers/mfd/motorola-cpcap.c
new file mode 100644
--- /dev/null
+++ b/drivers/mfd/motorola-cpcap.c
@@ -0,0 +1,259 @@
+/*
+ * Motorola CPCAP PMIC core driver
+ *
+ * Copyright (C) 2016 Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+#include <linux/sysfs.h>
+
+#include <linux/mfd/motorola-cpcap.h>
+#include <linux/spi/spi.h>
+
+#define CPCAP_NR_IRQ_REG_BANKS 6
+#define CPCAP_NR_IRQ_CHIPS 3
+
+struct cpcap_ddata {
+ struct spi_device *spi;
+ struct regmap_irq *irqs;
+ struct regmap_irq_chip_data *irqdata[CPCAP_NR_IRQ_CHIPS];
+ const struct regmap_config *regmap_conf;
+ struct regmap *regmap;
+};
+
+static int cpcap_check_revision(struct cpcap_ddata *cpcap)
+{
+ u16 vendor, rev;
+ int ret;
+
+ ret = cpcap_get_vendor(&cpcap->spi->dev, cpcap->regmap, &vendor);
+ if (ret)
+ return ret;
+
+ ret = cpcap_get_revision(&cpcap->spi->dev, cpcap->regmap, &rev);
+ if (ret)
+ return ret;
+
+ dev_info(&cpcap->spi->dev, "CPCAP vendor: %s rev: %i.%i (%x)\n",
+ vendor == CPCAP_VENDOR_ST ? "ST" : "TI",
+ CPCAP_REVISION_MAJOR(rev), CPCAP_REVISION_MINOR(rev),
+ rev);
+
+ if (rev < CPCAP_REVISION_2_1) {
+ dev_info(&cpcap->spi->dev,
+ "Please add old CPCAP revision support as needed\n");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+/*
+ * First two irq chips are the two private macro interrupt chips, the third
+ * irq chip is for register banks 1 - 4 and is available for drivers to use.
+ */
+static struct regmap_irq_chip cpcap_irq_chip[CPCAP_NR_IRQ_CHIPS] = {
+ {
+ .name = "cpcap-m2",
+ .num_regs = 1,
+ .status_base = CPCAP_REG_MI1,
+ .ack_base = CPCAP_REG_MI1,
+ .mask_base = CPCAP_REG_MIM1,
+ .use_ack = true,
+ },
+ {
+ .name = "cpcap-m2",
+ .num_regs = 1,
+ .status_base = CPCAP_REG_MI2,
+ .ack_base = CPCAP_REG_MI2,
+ .mask_base = CPCAP_REG_MIM2,
+ .use_ack = true,
+ },
+ {
+ .name = "cpcap1-4",
+ .num_regs = 4,
+ .status_base = CPCAP_REG_INT1,
+ .ack_base = CPCAP_REG_INT1,
+ .mask_base = CPCAP_REG_INTM1,
+ .type_base = CPCAP_REG_INTS1,
+ .use_ack = true,
+ },
+};
+
+static void cpcap_init_one_regmap_irq(struct cpcap_ddata *cpcap,
+ struct regmap_irq *rirq,
+ int irq_base, int irq)
+{
+ unsigned int reg_offset;
+ unsigned int bit, mask;
+
+ reg_offset = irq - irq_base;
+ reg_offset /= cpcap->regmap_conf->val_bits;
+ reg_offset *= cpcap->regmap_conf->reg_stride;
+
+ bit = irq % cpcap->regmap_conf->val_bits;
+ mask = (1 << bit);
+
+ rirq->reg_offset = reg_offset;
+ rirq->mask = mask;
+}
+
+static int cpcap_init_irq_chip(struct cpcap_ddata *cpcap, int irq_chip,
+ int irq_start, int nr_irqs)
+{
+ struct regmap_irq_chip *chip = &cpcap_irq_chip[irq_chip];
+ int i, ret;
+
+ for (i = irq_start; i < irq_start + nr_irqs; i++) {
+ struct regmap_irq *rirq = &cpcap->irqs[i];
+
+ cpcap_init_one_regmap_irq(cpcap, rirq, irq_start, i);
+ }
+ chip->irqs = &cpcap->irqs[irq_start];
+ chip->num_irqs = nr_irqs;
+ chip->irq_drv_data = cpcap;
+
+ ret = devm_regmap_add_irq_chip(&cpcap->spi->dev, cpcap->regmap,
+ cpcap->spi->irq,
+ IRQF_TRIGGER_RISING |
+ IRQF_SHARED, -1,
+ chip, &cpcap->irqdata[irq_chip]);
+ if (ret) {
+ dev_err(&cpcap->spi->dev, "could not add irq chip %i: %i\n",
+ irq_chip, ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int cpcap_init_irq(struct cpcap_ddata *cpcap)
+{
+ int ret;
+
+ cpcap->irqs = devm_kzalloc(&cpcap->spi->dev,
+ sizeof(*cpcap->irqs) *
+ CPCAP_NR_IRQ_REG_BANKS *
+ cpcap->regmap_conf->val_bits,
+ GFP_KERNEL);
+ if (!cpcap->irqs)
+ return -ENOMEM;
+
+ ret = cpcap_init_irq_chip(cpcap, 0, 0, 16);
+ if (ret)
+ return ret;
+
+ ret = cpcap_init_irq_chip(cpcap, 1, 16, 16);
+ if (ret)
+ return ret;
+
+ ret = cpcap_init_irq_chip(cpcap, 2, 32, 64);
+ if (ret)
+ return ret;
+
+ enable_irq_wake(cpcap->spi->irq);
+
+ return 0;
+}
+
+static const struct of_device_id cpcap_of_match[] = {
+ { .compatible = "motorola,cpcap", },
+ { .compatible = "st,6556002", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, cpcap_of_match);
+
+static const struct regmap_config cpcap_regmap_config = {
+ .reg_bits = 16,
+ .reg_stride = 4,
+ .pad_bits = 0,
+ .val_bits = 16,
+ .write_flag_mask = 0x8000,
+ .max_register = CPCAP_REG_ST_TEST2,
+ .cache_type = REGCACHE_NONE,
+ .reg_format_endian = REGMAP_ENDIAN_LITTLE,
+ .val_format_endian = REGMAP_ENDIAN_LITTLE,
+};
+
+static int cpcap_probe(struct spi_device *spi)
+{
+ const struct of_device_id *match;
+ struct cpcap_ddata *cpcap;
+ int ret;
+
+ match = of_match_device(of_match_ptr(cpcap_of_match), &spi->dev);
+ if (!match)
+ return -ENODEV;
+
+ cpcap = devm_kzalloc(&spi->dev, sizeof(*cpcap), GFP_KERNEL);
+ if (!cpcap)
+ return -ENOMEM;
+
+ cpcap->spi = spi;
+ spi_set_drvdata(spi, cpcap);
+
+ spi->bits_per_word = 16;
+ spi->mode = SPI_MODE_0 | SPI_CS_HIGH;
+
+ ret = spi_setup(spi);
+ if (ret)
+ return ret;
+
+ cpcap->regmap_conf = &cpcap_regmap_config;
+ cpcap->regmap = devm_regmap_init_spi(spi, &cpcap_regmap_config);
+ if (IS_ERR(cpcap->regmap)) {
+ ret = PTR_ERR(cpcap->regmap);
+ dev_err(&cpcap->spi->dev, "Failed to initialize regmap: %d\n",
+ ret);
+
+ return ret;
+ }
+
+ ret = cpcap_check_revision(cpcap);
+ if (ret) {
+ dev_err(&cpcap->spi->dev, "Failed to detect CPCAP: %i\n", ret);
+ return ret;
+ }
+
+ ret = cpcap_init_irq(cpcap);
+ if (ret)
+ return ret;
+
+ return of_platform_populate(spi->dev.of_node, NULL, NULL,
+ &cpcap->spi->dev);
+}
+
+static int cpcap_remove(struct spi_device *pdev)
+{
+ struct cpcap_ddata *cpcap = spi_get_drvdata(pdev);
+
+ of_platform_depopulate(&cpcap->spi->dev);
+
+ return 0;
+}
+
+static struct spi_driver cpcap_driver = {
+ .driver = {
+ .name = "cpcap-core",
+ .of_match_table = cpcap_of_match,
+ },
+ .probe = cpcap_probe,
+ .remove = cpcap_remove,
+};
+module_spi_driver(cpcap_driver);
+
+MODULE_ALIAS("platform:cpcap");
+MODULE_DESCRIPTION("CPCAP driver");
+MODULE_AUTHOR("Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>");
+MODULE_LICENSE("GPL v2");
diff --git a/include/linux/mfd/motorola-cpcap.h b/include/linux/mfd/motorola-cpcap.h
new file mode 100644
--- /dev/null
+++ b/include/linux/mfd/motorola-cpcap.h
@@ -0,0 +1,292 @@
+/*
+ * The register defines are based on earlier cpcap.h in Motorola Linux kernel
+ * tree.
+ *
+ * Copyright (C) 2007-2009 Motorola, Inc.
+ *
+ * Rewritten for the real register offsets instead of enumeration
+ * to make the defines usable with Linux kernel regmap support
+ *
+ * Copyright (C) 2016 Tony Lindgren <tony-4v6yS6AI5VpBDgjK7y7TUQ@public.gmane.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#define CPCAP_VENDOR_ST 0
+#define CPCAP_VENDOR_TI 1
+
+#define CPCAP_REVISION_MAJOR(r) (((r) >> 4) + 1)
+#define CPCAP_REVISION_MINOR(r) ((r) & 0xf)
+
+#define CPCAP_REVISION_1_0 0x08
+#define CPCAP_REVISION_1_1 0x09
+#define CPCAP_REVISION_2_0 0x10
+#define CPCAP_REVISION_2_1 0x11
+
+/* CPCAP registers */
+#define CPCAP_REG_INT1 0x0000 /* Interrupt 1 */
+#define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
+#define CPCAP_REG_INT3 0x0008 /* Interrupt 3 */
+#define CPCAP_REG_INT4 0x000c /* Interrupt 4 */
+#define CPCAP_REG_INTM1 0x0010 /* Interrupt Mask 1 */
+#define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
+#define CPCAP_REG_INTM3 0x0018 /* Interrupt Mask 3 */
+#define CPCAP_REG_INTM4 0x001c /* Interrupt Mask 4 */
+#define CPCAP_REG_INTS1 0x0020 /* Interrupt Sense 1 */
+#define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */
+#define CPCAP_REG_INTS3 0x0028 /* Interrupt Sense 3 */
+#define CPCAP_REG_INTS4 0x002c /* Interrupt Sense 4 */
+#define CPCAP_REG_ASSIGN1 0x0030 /* Resource Assignment 1 */
+#define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */
+#define CPCAP_REG_ASSIGN3 0x0038 /* Resource Assignment 3 */
+#define CPCAP_REG_ASSIGN4 0x003c /* Resource Assignment 4 */
+#define CPCAP_REG_ASSIGN5 0x0040 /* Resource Assignment 5 */
+#define CPCAP_REG_ASSIGN6 0x0044 /* Resource Assignment 6 */
+#define CPCAP_REG_VERSC1 0x0048 /* Version Control 1 */
+#define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
+
+#define CPCAP_REG_MI1 0x0200 /* Macro Interrupt 1 */
+#define CPCAP_REG_MIM1 0x0204 /* Macro Interrupt Mask 1 */
+#define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */
+#define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */
+#define CPCAP_REG_UCC1 0x0210 /* UC Control 1 */
+#define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
+
+#define CPCAP_REG_PC1 0x021c /* Power Cut 1 */
+#define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */
+#define CPCAP_REG_BPEOL 0x0224 /* BP and EOL */
+#define CPCAP_REG_PGC 0x0228 /* Power Gate and Control */
+#define CPCAP_REG_MT1 0x022c /* Memory Transfer 1 */
+#define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */
+#define CPCAP_REG_MT3 0x0234 /* Memory Transfer 3 */
+#define CPCAP_REG_PF 0x0238 /* Print Format */
+
+#define CPCAP_REG_SCC 0x0400 /* System Clock Control */
+#define CPCAP_REG_SW1 0x0404 /* Stop Watch 1 */
+#define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */
+#define CPCAP_REG_UCTM 0x040c /* UC Turbo Mode */
+#define CPCAP_REG_TOD1 0x0410 /* Time of Day 1 */
+#define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */
+#define CPCAP_REG_TODA1 0x0418 /* Time of Day Alarm 1 */
+#define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */
+#define CPCAP_REG_DAY 0x0420 /* Day */
+#define CPCAP_REG_DAYA 0x0424 /* Day Alarm */
+#define CPCAP_REG_VAL1 0x0428 /* Validity 1 */
+#define CPCAP_REG_VAL2 0x042c /* Validity 2 */
+
+#define CPCAP_REG_SDVSPLL 0x0600 /* Switcher DVS and PLL */
+#define CPCAP_REG_SI2CC1 0x0604 /* Switcher I2C Control 1 */
+#define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
+#define CPCAP_REG_S1C1 0x060c /* Switcher 1 Control 1 */
+#define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
+#define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */
+#define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */
+#define CPCAP_REG_S3C 0x061c /* Switcher 3 Control */
+#define CPCAP_REG_S4C1 0x0620 /* Switcher 4 Control 1 */
+#define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */
+#define CPCAP_REG_S5C 0x0628 /* Switcher 5 Control */
+#define CPCAP_REG_S6C 0x062c /* Switcher 6 Control */
+#define CPCAP_REG_VCAMC 0x0630 /* VCAM Control */
+#define CPCAP_REG_VCSIC 0x0634 /* VCSI Control */
+#define CPCAP_REG_VDACC 0x0638 /* VDAC Control */
+#define CPCAP_REG_VDIGC 0x063c /* VDIG Control */
+#define CPCAP_REG_VFUSEC 0x0640 /* VFUSE Control */
+#define CPCAP_REG_VHVIOC 0x0644 /* VHVIO Control */
+#define CPCAP_REG_VSDIOC 0x0648 /* VSDIO Control */
+#define CPCAP_REG_VPLLC 0x064c /* VPLL Control */
+#define CPCAP_REG_VRF1C 0x0650 /* VRF1 Control */
+#define CPCAP_REG_VRF2C 0x0654 /* VRF2 Control */
+#define CPCAP_REG_VRFREFC 0x0658 /* VRFREF Control */
+#define CPCAP_REG_VWLAN1C 0x065c /* VWLAN1 Control */
+#define CPCAP_REG_VWLAN2C 0x0660 /* VWLAN2 Control */
+#define CPCAP_REG_VSIMC 0x0664 /* VSIM Control */
+#define CPCAP_REG_VVIBC 0x0668 /* VVIB Control */
+#define CPCAP_REG_VUSBC 0x066c /* VUSB Control */
+#define CPCAP_REG_VUSBINT1C 0x0670 /* VUSBINT1 Control */
+#define CPCAP_REG_VUSBINT2C 0x0674 /* VUSBINT2 Control */
+#define CPCAP_REG_URT 0x0678 /* Useroff Regulator Trigger */
+#define CPCAP_REG_URM1 0x067c /* Useroff Regulator Mask 1 */
+#define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */
+
+#define CPCAP_REG_VAUDIOC 0x0800 /* VAUDIO Control */
+#define CPCAP_REG_CC 0x0804 /* Codec Control */
+#define CPCAP_REG_CDI 0x0808 /* Codec Digital Interface */
+#define CPCAP_REG_SDAC 0x080c /* Stereo DAC */
+#define CPCAP_REG_SDACDI 0x0810 /* Stereo DAC Digital Interface */
+#define CPCAP_REG_TXI 0x0814 /* TX Inputs */
+#define CPCAP_REG_TXMP 0x0818 /* TX MIC PGA's */
+#define CPCAP_REG_RXOA 0x081c /* RX Output Amplifiers */
+#define CPCAP_REG_RXVC 0x0820 /* RX Volume Control */
+#define CPCAP_REG_RXCOA 0x0824 /* RX Codec to Output Amps */
+#define CPCAP_REG_RXSDOA 0x0828 /* RX Stereo DAC to Output Amps */
+#define CPCAP_REG_RXEPOA 0x082c /* RX External PGA to Output Amps */
+#define CPCAP_REG_RXLL 0x0830 /* RX Low Latency */
+#define CPCAP_REG_A2LA 0x0834 /* A2 Loudspeaker Amplifier */
+#define CPCAP_REG_MIPIS1 0x0838 /* MIPI Slimbus 1 */
+#define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */
+#define CPCAP_REG_MIPIS3 0x0840 /* MIPI Slimbus 3. */
+#define CPCAP_REG_LVAB 0x0844 /* LMR Volume and A4 Balanced. */
+
+#define CPCAP_REG_CCC1 0x0a00 /* Coulomb Counter Control 1 */
+#define CPCAP_REG_CRM 0x0a04 /* Charger and Reverse Mode */
+#define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */
+#define CPCAP_REG_CCS1 0x0a0c /* Coulomb Counter Sample 1 */
+#define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */
+#define CPCAP_REG_CCA1 0x0a14 /* Coulomb Counter Accumulator 1 */
+#define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */
+#define CPCAP_REG_CCM 0x0a1c /* Coulomb Counter Mode */
+#define CPCAP_REG_CCO 0x0a20 /* Coulomb Counter Offset */
+#define CPCAP_REG_CCI 0x0a24 /* Coulomb Counter Integrator */
+
+#define CPCAP_REG_ADCC1 0x0c00 /* A/D Converter Configuration 1 */
+#define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */
+#define CPCAP_REG_ADCD0 0x0c08 /* A/D Converter Data 0 */
+#define CPCAP_REG_ADCD1 0x0c0c /* A/D Converter Data 1 */
+#define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */
+#define CPCAP_REG_ADCD3 0x0c14 /* A/D Converter Data 3 */
+#define CPCAP_REG_ADCD4 0x0c18 /* A/D Converter Data 4 */
+#define CPCAP_REG_ADCD5 0x0c1c /* A/D Converter Data 5 */
+#define CPCAP_REG_ADCD6 0x0c20 /* A/D Converter Data 6 */
+#define CPCAP_REG_ADCD7 0x0c24 /* A/D Converter Data 7 */
+#define CPCAP_REG_ADCAL1 0x0c28 /* A/D Converter Calibration 1 */
+#define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */
+
+#define CPCAP_REG_USBC1 0x0e00 /* USB Control 1 */
+#define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */
+#define CPCAP_REG_USBC3 0x0e08 /* USB Control 3 */
+#define CPCAP_REG_UVIDL 0x0e0c /* ULPI Vendor ID Low */
+#define CPCAP_REG_UVIDH 0x0e10 /* ULPI Vendor ID High */
+#define CPCAP_REG_UPIDL 0x0e14 /* ULPI Product ID Low */
+#define CPCAP_REG_UPIDH 0x0e18 /* ULPI Product ID High */
+#define CPCAP_REG_UFC1 0x0e1c /* ULPI Function Control 1 */
+#define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */
+#define CPCAP_REG_UFC3 0x0e24 /* ULPI Function Control 3 */
+#define CPCAP_REG_UIC1 0x0e28 /* ULPI Interface Control 1 */
+#define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */
+#define CPCAP_REG_UIC3 0x0e30 /* ULPI Interface Control 3 */
+#define CPCAP_REG_USBOTG1 0x0e34 /* USB OTG Control 1 */
+#define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */
+#define CPCAP_REG_USBOTG3 0x0e3c /* USB OTG Control 3 */
+#define CPCAP_REG_UIER1 0x0e40 /* USB Interrupt Enable Rising 1 */
+#define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */
+#define CPCAP_REG_UIER3 0x0e48 /* USB Interrupt Enable Rising 3 */
+#define CPCAP_REG_UIEF1 0x0e4c /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIEF2 0x0e50 /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIEF3 0x0e54 /* USB Interrupt Enable Falling 1 */
+#define CPCAP_REG_UIS 0x0e58 /* USB Interrupt Status */
+#define CPCAP_REG_UIL 0x0e5c /* USB Interrupt Latch */
+#define CPCAP_REG_USBD 0x0e60 /* USB Debug */
+#define CPCAP_REG_SCR1 0x0e64 /* Scratch 1 */
+#define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */
+#define CPCAP_REG_SCR3 0x0e6c /* Scratch 3 */
+
+#define CPCAP_REG_VMC 0x0eac /* Video Mux Control */
+#define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */
+#define CPCAP_REG_GPIO0 0x0eb4 /* GPIO 0 Control */
+
+#define CPCAP_REG_GPIO1 0x0ebc /* GPIO 1 Control */
+
+#define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */
+
+#define CPCAP_REG_GPIO3 0x0ecc /* GPIO 3 Control */
+
+#define CPCAP_REG_GPIO4 0x0ed4 /* GPIO 4 Control */
+
+#define CPCAP_REG_GPIO5 0x0edc /* GPIO 5 Control */
+
+#define CPCAP_REG_GPIO6 0x0ee4 /* GPIO 6 Control */
+
+#define CPCAP_REG_MDLC 0x1000 /* Main Display Lighting Control */
+#define CPCAP_REG_KLC 0x1004 /* Keypad Lighting Control */
+#define CPCAP_REG_ADLC 0x1008 /* Aux Display Lighting Control */
+#define CPCAP_REG_REDC 0x100c /* Red Triode Control */
+#define CPCAP_REG_GREENC 0x1010 /* Green Triode Control */
+#define CPCAP_REG_BLUEC 0x1014 /* Blue Triode Control */
+#define CPCAP_REG_CFC 0x1018 /* Camera Flash Control */
+#define CPCAP_REG_ABC 0x101c /* Adaptive Boost Control */
+#define CPCAP_REG_BLEDC 0x1020 /* Bluetooth LED Control */
+#define CPCAP_REG_CLEDC 0x1024 /* Camera Privacy LED Control */
+
+#define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */
+#define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */
+#define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
+#define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */
+
+#define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */
+
+#define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */
+#define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */
+#define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */
+#define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */
+
+#define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */
+
+#define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */
+#define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */
+#define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */
+#define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */
+
+#define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */
+#define CPCAP_REG_GCAIC 0x1258 /* GCAI Clock Control */
+#define CPCAP_REG_GCAIM 0x125c /* GCAI GPIO Mode */
+#define CPCAP_REG_LGDIR 0x1260 /* LMR GCAI GPIO Direction */
+#define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */
+#define CPCAP_REG_LGPIN 0x1268 /* LMR GCAI GPIO Pin */
+#define CPCAP_REG_LGMASK 0x126c /* LMR GCAI GPIO Mask */
+#define CPCAP_REG_LDEB 0x1270 /* LMR Debounce Settings */
+#define CPCAP_REG_LGDET 0x1274 /* LMR GCAI Detach Detect */
+#define CPCAP_REG_LMISC 0x1278 /* LMR Misc Bits */
+#define CPCAP_REG_LMACE 0x127c /* LMR Mace IC Support */
+
+#define CPCAP_REG_TEST 0x7c00 /* Test */
+
+#define CPCAP_REG_ST_TEST1 0x7d08 /* ST Test1 */
+
+#define CPCAP_REG_ST_TEST2 0x7d18 /* ST Test2 */
+
+/*
+ * Helpers for child devices to check the revision and vendor.
+ *
+ * REVISIT: No documentation for the bits below, please update
+ * to use proper names for defines when available.
+ */
+
+static inline int cpcap_get_revision(struct device *dev,
+ struct regmap *regmap,
+ u16 *revision)
+{
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val);
+ if (ret) {
+ dev_err(dev, "Could not read revision\n");
+
+ return ret;
+ }
+
+ *revision = ((val >> 3) & 0x7) | ((val << 3) & 0x38);
+
+ return 0;
+}
+
+static inline int cpcap_get_vendor(struct device *dev,
+ struct regmap *regmap,
+ u16 *vendor)
+{
+ unsigned int val;
+ int ret;
+
+ ret = regmap_read(regmap, CPCAP_REG_VERSC1, &val);
+ if (ret) {
+ dev_err(dev, "Could not read vendor\n");
+
+ return ret;
+ }
+
+ *vendor = (val >> 6) & 0x7;
+
+ return 0;
+}
--
2.11.0
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^ permalink raw reply
* Re: [PATCH 2/2] phy: rockchip-emmc: try to get drive impedance from DT
From: Doug Anderson @ 2017-01-06 0:51 UTC (permalink / raw)
To: Shawn Lin
Cc: Kishon Vijay Abraham I, Rob Herring,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
open list:ARM/Rockchip SoC..., Heiko Stuebner,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <1483608682-226716-2-git-send-email-shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
Hi,
On Thu, Jan 5, 2017 at 1:31 AM, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
> Try to get drive impedance from DT and use it, otherwise
> use 50ohm by default in order not to break the existing boards
> as 50ohm works fine for them already.
>
> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
> ---
>
> drivers/phy/phy-rockchip-emmc.c | 29 ++++++++++++++++++++++++++++-
> 1 file changed, 28 insertions(+), 1 deletion(-)
I could have sworn that you somehow needed to make sure that the eMMC
part itself needed to also be updated to be told the matching drive
impedance so you don't get a mismatch. How do you make that work?
...or am I just confused. I meant to try to dig more, but ran out of
time today. :(
-Doug
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^ permalink raw reply
* Re: [PATCH v2 2/3] devicetree: bq27425: add documentation for bq27425 fuel gauge
From: Sebastian Reichel @ 2017-01-06 0:56 UTC (permalink / raw)
To: Matt Ranostay, Rob Herring, Mark Rutland; +Cc: tony, devicetree, linux-pm
In-Reply-To: <20170105021007.22088-3-matt@ranostay.consulting>
[-- Attachment #1: Type: text/plain, Size: 2175 bytes --]
Hi,
On Wed, Jan 04, 2017 at 06:10:06PM -0800, Matt Ranostay wrote:
> Signed-off-by: Matt Ranostay <matt@ranostay.consulting>
> ---
> .../devicetree/bindings/power/bq27425.txt | 25 ++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/power/bq27425.txt
>
> diff --git a/Documentation/devicetree/bindings/power/bq27425.txt b/Documentation/devicetree/bindings/power/bq27425.txt
> new file mode 100644
> index 000000000000..5d33b61cf9b7
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/power/bq27425.txt
> @@ -0,0 +1,25 @@
> +* TI BQ27425 Fuel Gauge
> +
> +http://www.ti.com/lit/ds/symlink/bq27425-g2a.pdf
> +
> +Please note that if any of the optional properties are defined
> +then all settings must be.
> +
> +Required properties:
> +- compatible: Should be "ti,bq27425"
> +- reg: integer, I2C address of the device
> +
> +Optional properties:
> +- ti,design-microamp-hours: integer of mAh of the battery
> +- ti,design-microvolt-hours: integer of the mWh of the battery
> +- ti,terminate-microvolt: integer of mV of the dead voltage of
> + the battery
> +
> +bq27425 {
> + compatible = "ti,bq27425";
> + reg = <0x55>;
> +
> + ti,design-microamp-hours = <1360>;
> + ti,design-microwatt-hours = <4970>;
> + ti,terminate-microvolt = <3200>;
> +};
The design capacity of the battery is not a property of the fuel
gauge. It should be modelled more like this:
/ {
bat0: battery {
/* Nokia BL-5J */
nominal-microvolt = <3700000>;
design-microwatt-hours = <4900000>;
design-microamp-hours = <1320000>;
chemistry-type = <POWER_SUPPLY_LI_ION>;
/* other battery specific stuff */
};
};
&i2c3 {
bq27425 {
compatible = "ti,bq27425";
reg = <0x55>;
monitored-battery = <&bat0>;
/* other fuel-gauge specific stuff */
};
};
Also there is another pending patch series, that documents bq27xxx.
bq27425 should be documented inside of it. The battery binding would
be generic, so it should be described in its own document.
-- Sebastian
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply
* Re: [RESEND 2/2] arm64: dts: Add dts files for Hisilicon Hi3660 SoC
From: Chen Feng @ 2017-01-06 0:59 UTC (permalink / raw)
To: Andy Gross
Cc: xuwei5-C8/M+/jPZTeaMJb+Lgu22Q, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
mark.rutland-5wv7dgnIgG8, catalin.marinas-5wv7dgnIgG8,
will.deacon-5wv7dgnIgG8,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
suzhuangluan-C8/M+/jPZTeaMJb+Lgu22Q,
xuyiping-C8/M+/jPZTeaMJb+Lgu22Q
In-Reply-To: <20170105141456.GA5710-3KkwrOJo9xYlRp7syxWybdHuzzzSOjJt@public.gmane.org>
On 2017/1/5 22:14, Andy Gross wrote:
> On Mon, Dec 26, 2016 at 05:36:12PM +0800, Chen Feng wrote:
>> Add initial dtsi file to support Hisilicon Hi3660 SoC with
>> support of Octal core CPUs in two clusters(4 * A53 & 4 * A73).
>>
>> Also add dts file to support HiKey960 development board which
>> based on Hi3660 SoC.
>> The output console is earlycon "earlycon=pl011,0xfdf05000".
>> And the con_init uart5 with a fixed clock, which already
>> configured at bootloader.
>>
>> When clock is available, the uart5 will be modified.
>>
>> Tested on HiKey960 Board.
>>
>> Signed-off-by: Chen Feng <puck.chen-C8/M+/jPZTeaMJb+Lgu22Q@public.gmane.org>
>> ---
>> arch/arm64/boot/dts/hisilicon/Makefile | 1 +
>> arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts | 34 +++++
>> arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 156 ++++++++++++++++++++++
>> 3 files changed, 191 insertions(+)
>> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> create mode 100644 arch/arm64/boot/dts/hisilicon/hi3660.dtsi
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/Makefile b/arch/arm64/boot/dts/hisilicon/Makefile
>> index d5f43a0..b633b5d 100644
>> --- a/arch/arm64/boot/dts/hisilicon/Makefile
>> +++ b/arch/arm64/boot/dts/hisilicon/Makefile
>> @@ -1,4 +1,5 @@
>> dtb-$(CONFIG_ARCH_HISI) += hi6220-hikey.dtb
>> +dtb-$(CONFIG_ARCH_HISI) += hi3660-hikey960.dtb
>> dtb-$(CONFIG_ARCH_HISI) += hip05-d02.dtb
>> dtb-$(CONFIG_ARCH_HISI) += hip06-d03.dtb
>>
>> diff --git a/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> new file mode 100644
>> index 0000000..3d7aead
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/hisilicon/hi3660-hikey960.dts
>> @@ -0,0 +1,34 @@
>> +/*
>> + * dts file for Hisilicon HiKey960 Development Board
>> + *
>> + * Copyright (C) 2016, Hisilicon Ltd.
>> + *
>> + */
>> +
>> +/dts-v1/;
>> +
>> +#include "hi3660.dtsi"
>> +
>> +/ {
>> + model = "HiKey960";
>> + compatible = "hisilicon,hi3660";
>> +
>> + aliases {
>> + serial5 = &uart5; /* console UART */
>> + };
>> +
>> + chosen {
>> + stdout-path = "serial5:115200n8";
>> + };
>> +
>> + memory@0 {
>> + device_type = "memory";
>> + reg = <0x0 0x00400000 0x0 0xBFE00000>;
>
> Use lower case letters for hex numbers. 0xbfe00000.
>
ok, thanks!
>> + };
>> +
>> + soc {
>> + uart5: uart@fdf05000 {
>> + status = "ok";
>> + };
>> + };
>> +};
>
> <snip>
>
> Regards,
>
> Andy
>
> .
>
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^ permalink raw reply
* Re: [PATCH 2/2] phy: rockchip-emmc: try to get drive impedance from DT
From: Shawn Lin @ 2017-01-06 1:09 UTC (permalink / raw)
To: Doug Anderson
Cc: shawn.lin-TNX95d0MmH7DzftRWevZcw, Kishon Vijay Abraham I,
Rob Herring, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
open list:ARM/Rockchip SoC..., Heiko Stuebner,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
In-Reply-To: <CAD=FV=V0+=yknRQAZu98FVsbKnRTX_5beeKsLe01P0qT7gb5Zg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
On 2017/1/6 8:51, Doug Anderson wrote:
> Hi,
>
> On Thu, Jan 5, 2017 at 1:31 AM, Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org> wrote:
>> Try to get drive impedance from DT and use it, otherwise
>> use 50ohm by default in order not to break the existing boards
>> as 50ohm works fine for them already.
>>
>> Signed-off-by: Shawn Lin <shawn.lin-TNX95d0MmH7DzftRWevZcw@public.gmane.org>
>> ---
>>
>> drivers/phy/phy-rockchip-emmc.c | 29 ++++++++++++++++++++++++++++-
>> 1 file changed, 28 insertions(+), 1 deletion(-)
>
> I could have sworn that you somehow needed to make sure that the eMMC
> part itself needed to also be updated to be told the matching drive
> impedance so you don't get a mismatch. How do you make that work?
No I didn't. So that means the eMMC part itself still couldn't be
updated. The intention for me to introduce this only for emmc phy is
that I got report that the default drive impedance of one eMMC is not
50ohms, so now we haven't been able to update it for eMMC part but maybe
we could just update it for the phy itself to match them in between.
> ...or am I just confused. I meant to try to dig more, but ran out of
> time today. :(
>
> -Doug
>
>
>
--
Best Regards
Shawn Lin
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^ permalink raw reply
* Re: [PATCH v2 9/9] ARM: sunxi: Convert pinctrl nodes to generic bindings
From: André Przywara @ 2017-01-06 1:17 UTC (permalink / raw)
To: Maxime Ripard
Cc: Chen-Yu Tsai, devicetree, Linus Walleij, linux-kernel,
linux-gpio@vger.kernel.org, linux-arm-kernel
In-Reply-To: <20170105153556.pzec5jjuz7pmvsmn@lukather>
On 05/01/17 15:35, Maxime Ripard wrote:
Hi Maxime,
> On Wed, Jan 04, 2017 at 02:16:23AM +0000, André Przywara wrote:
>> So can I ask that we start taking this seriously and stop doing things
>> which prevent Allwinner boards from being supported properly?
>> Which would first involve dropping this very patch?
>
> The driver still supports the old binding.
Yes, a _current_ version of the driver supports both bindings, but older
versions *require* the older binding and bail out if various
allwinner,xxx properties are missing - as in those proposed new DTs:
4.9 kernel with sunxi/for-next .dtb:
sun8i-h3-pinctrl 1c20800.pinctrl: missing allwinner,function property in
node uart0
sun8i-h3-pinctrl 1c20800.pinctrl: missing allwinner,function property in
node mmc0
sunxi-mmc: probe of 1c0f000.mmc failed with error -22
>> Having done breakage in the past (with "allwinner,sun7i-a20-mmc", for
>> instance) is no excuse for doing it again.
>
> I'm not sure which breakage we introduced with a new compatible: the
> old compatible is working just like it used to, and the new one is
> working like we need it to.
But the new compatible is not recognized with older kernels, preventing
people from using the newest DT with older kernels as well.
I proposed to simply work around this by using the old compatible as a
fallback: compatible="sun7i-a20-mmc", "sun5i-a13-mmc";
Unfortunately this suggestion was not followed.
So now we can't boot a 4.8 (or earlier) kernel with a .dtb from a 4.9 or
later tree. Adding the extra string would fix this.
Actually the recommended approach to avoid this situation in the first
place is to always use compatible strings with the SoC-specific name as
the first string, followed by the compatible string the driver works
with. And this should be done upon introducing a new DT to the tree -
even if at this point the driver doesn't deal with the new string.
Unknown strings will just be skipped.
So for instance the H5 DT should read: "sun50i-h5-mmc",
"sun50i-a64-mmc", "sun5i-a13-mmc"; (with the last string possibly being
optional). The current kernel driver will not match the h5 string, so it
falls back to the a64 string and works. If we learn about a neat eMMC
5.1 feature (or any quirk the H5 can benefit from) somewhere in the
future, we can add the code together with this h5 string to the driver
and don't need to change the DT at all.
>> And especially I want to avoid this habit creeping into the arm64
>> world (thinking about the H5 here, which may be impacted by this
>> very patch, for instance).
>
> And again, if you looked at the entire serie, you would have seen that
> I took this into account.
I saw that and I appreciate that very much, but that post was not about
keeping compatibility with older DTs, but allowing older kernels to run
with the latest DT as well.
Newer DTs from your -next branch do not work with older kernels - that
is what my whole post was about. _Why_ we should care is explained there.
And please don't get me wrong: I am not asking for rewriting and bending
the whole kernel source to make this possible, it's just that we drop
this patch here, for instance, or simply not _change_ compatible names,
but instead add new strings.
Cheers,
Andre.
^ permalink raw reply
* Re: [PATCH v2 10/19] media: Add i.MX media core driver
From: Steve Longerbeam @ 2017-01-06 1:21 UTC (permalink / raw)
To: Vladimir Zapolskiy, shawnguo, kernel, fabio.estevam, robh+dt,
mark.rutland, linux, mchehab, gregkh, p.zabel
Cc: devel, devicetree, Steve Longerbeam, linux-kernel,
linux-arm-kernel, linux-media
In-Reply-To: <c04a85dc-4f62-798f-2e37-d7848657730a@mentor.com>
On 01/04/2017 05:33 AM, Vladimir Zapolskiy wrote:
> Hi Steve,
>
> On 01/03/2017 10:57 PM, Steve Longerbeam wrote:
>> Add the core media driver for i.MX SOC.
>>
>> Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com>
>> ---
>> Documentation/devicetree/bindings/media/imx.txt | 205 +++++
> v2 was sent before getting Rob's review comments, but still they
> should be addressed in v3.
yes, those changes will be part of v3 as well.
>
> Also I would suggest to separate device tree binding documentation
> change and place it as the first patch in the series, this should
> make the following DTS changes valid.
done.
>
>> Documentation/media/v4l-drivers/imx.rst | 430 ++++++++++
>> drivers/staging/media/Kconfig | 2 +
>> drivers/staging/media/Makefile | 1 +
>> drivers/staging/media/imx/Kconfig | 8 +
>> drivers/staging/media/imx/Makefile | 6 +
>> drivers/staging/media/imx/TODO | 18 +
>> drivers/staging/media/imx/imx-media-common.c | 985 ++++++++++++++++++++++
>> drivers/staging/media/imx/imx-media-dev.c | 479 +++++++++++
>> drivers/staging/media/imx/imx-media-fim.c | 509 +++++++++++
>> drivers/staging/media/imx/imx-media-internal-sd.c | 457 ++++++++++
>> drivers/staging/media/imx/imx-media-of.c | 291 +++++++
>> drivers/staging/media/imx/imx-media-of.h | 25 +
>> drivers/staging/media/imx/imx-media.h | 299 +++++++
>> include/media/imx.h | 15 +
>> include/uapi/Kbuild | 1 +
>> include/uapi/linux/v4l2-controls.h | 4 +
>> include/uapi/media/Kbuild | 2 +
>> include/uapi/media/imx.h | 30 +
> Probably Greg should ack the UAPI changes, you may consider
> to split them into a separate patch.
I split out the one-line addition to include/uapi/Kbuild with an empty
include/uapi/media/Kbuild into a new patch "UAPI: Add media UAPI Kbuild
file".
Also added a patch "media: Add userspace header file for i.MX".
>
>
>> +
>> +struct imx_media_subdev *
>> +imx_media_find_subdev_by_sd(struct imx_media_dev *imxmd,
>> + struct v4l2_subdev *sd)
>> +{
>> + struct imx_media_subdev *imxsd;
>> + int i, ret = -ENODEV;
>> +
>> + for (i = 0; i < imxmd->num_subdevs; i++) {
>> + imxsd = &imxmd->subdev[i];
>> + if (sd == imxsd->sd) {
> This can be simplifed:
>
> ...
>
> if (sd == imxsd->sd)
> return imxsd;
> }
>
> return ERR_PTR(-ENODEV);
yep, done.
>
>> +struct imx_media_subdev *
>> +imx_media_find_subdev_by_id(struct imx_media_dev *imxmd, u32 grp_id)
>> +{
>> + struct imx_media_subdev *imxsd;
>> + int i, ret = -ENODEV;
>> +
>> + for (i = 0; i < imxmd->num_subdevs; i++) {
>> + imxsd = &imxmd->subdev[i];
>> + if (imxsd->sd && imxsd->sd->grp_id == grp_id) {
>> + ret = 0;
>> + break;
> This can be simplifed:
>
> ...
>
> if (imxsd->sd && imxsd->sd->grp_id == grp_i)
> return imxsd;
> }
>
> return ERR_PTR(-ENODEV);
done.
>
>
>> diff --git a/drivers/staging/media/imx/imx-media-dev.c b/drivers/staging/media/imx/imx-media-dev.c
>> new file mode 100644
>> index 0000000..8d22730
>> --- /dev/null
>> +++ b/drivers/staging/media/imx/imx-media-dev.c
>> @@ -0,0 +1,479 @@
>> +/*
>> + * V4L2 Media Controller Driver for Freescale i.MX5/6 SOC
>> + *
>> + * Copyright (c) 2016 Mentor Graphics Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#include <linux/module.h>
>> +#include <linux/delay.h>
>> +#include <linux/fs.h>
>> +#include <linux/timer.h>
>> +#include <linux/sched.h>
>> +#include <linux/slab.h>
>> +#include <linux/spinlock.h>
>> +#include <linux/platform_device.h>
>> +#include <linux/pinctrl/consumer.h>
>> +#include <linux/of_platform.h>
>> +#include <media/v4l2-ioctl.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-event.h>
>> +#include <media/v4l2-mc.h>
> Please sort out the list of headers alphabetically.
done.
>> +#include <video/imx-ipu-v3.h>
>> +#include <media/imx.h>
>> +#include "imx-media.h"
>> +#include "imx-media-of.h"
>> +
>> +#define DEVICE_NAME "imx-media"
> I suppose you don't need this macro.
sure why not, removed.
>
> [snip]
>
>> + */
>> +static int imx_media_create_links(struct imx_media_dev *imxmd)
>> +{
>> + struct imx_media_subdev *local_sd;
>> + struct imx_media_subdev *remote_sd;
>> + struct v4l2_subdev *source, *sink;
>> + struct imx_media_link *link;
>> + struct imx_media_pad *pad;
>> + u16 source_pad, sink_pad;
>> + int num_pads, i, j, k;
>> + int ret = 0;
>> +
>> + for (i = 0; i < imxmd->num_subdevs; i++) {
>> + local_sd = &imxmd->subdev[i];
>> + num_pads = local_sd->num_sink_pads + local_sd->num_src_pads;
>> +
>> + for (j = 0; j < num_pads; j++) {
>> + pad = &local_sd->pad[j];
>> +
>> + for (k = 0; k < pad->num_links; k++) {
>> + link = &pad->link[k];
>> +
>> <snip>
> Indentation depth is quite terrific.
yes, it needs to iterate by subdev, pads in the subdev, then links
in the pad. But I moved the code under the innermost loop into a
function imx_media_create_link(), which creates a single media
link. So it's not so much an eye-sore now.
>
>
>> +static struct platform_driver imx_media_pdrv = {
>> + .probe = imx_media_probe,
>> + .remove = imx_media_remove,
>> + .driver = {
>> + .name = DEVICE_NAME,
>> + .owner = THIS_MODULE,
> Setting of .owner is not needed nowadays IIRC.
a quick look at struct device_driver definition didn't mention that
.owner member is deprecated or not needed, so for now I'll leave
it in place. We can revisit that later.
>
>> + .of_match_table = imx_media_dt_ids,
>> + },
>> +};
>> +
>> +module_platform_driver(imx_media_pdrv);
>> +
>> +MODULE_DESCRIPTION("i.MX5/6 v4l2 media controller driver");
>> +MODULE_AUTHOR("Steve Longerbeam <steve_longerbeam@mentor.com>");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/staging/media/imx/imx-media-fim.c b/drivers/staging/media/imx/imx-media-fim.c
>> new file mode 100644
>> index 0000000..52bfa8d
>> --- /dev/null
>> +++ b/drivers/staging/media/imx/imx-media-fim.c
>> @@ -0,0 +1,509 @@
>> +/*
>> + * Frame Interval Monitor.
>> + *
>> + * Copyright (c) 2016 Mentor Graphics Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#include <linux/module.h>
>> +#include <linux/delay.h>
>> +#include <linux/slab.h>
>> +#include <linux/platform_device.h>
>> +#ifdef CONFIG_IMX_GPT_ICAP
>> +#include <linux/mxc_icap.h>
>> +#endif
> This looks clumsy. Include it unconditionally, if needed
> do #ifdef's inside the header file.
The i.MX input capture patch will come later. These are just
placeholders until then, the config name could even change.
For now I just removed the above conditional include.
>
>> +#include <media/v4l2-subdev.h>
>> +#include <media/v4l2-of.h>
>> +#include <media/v4l2-ctrls.h>
> Please sort out the list alphabetically.
done.
>> + if (IS_ENABLED(CONFIG_IMX_GPT_ICAP)) {
>> + ret = of_property_read_u32_array(fim_np,
>> + "input-capture-channel",
>> + icap, 2);
>> + if (!ret) {
>> + fim->icap_channel = icap[0];
>> + fim->icap_flags = icap[1];
>> + }
> Should you return error otherwise?
nope, it's an optional property.
>
>> diff --git a/drivers/staging/media/imx/imx-media-of.c b/drivers/staging/media/imx/imx-media-of.c
>> new file mode 100644
>> index 0000000..018d05a
>> --- /dev/null
>> +++ b/drivers/staging/media/imx/imx-media-of.c
>> @@ -0,0 +1,291 @@
>> +/*
>> + * Media driver for Freescale i.MX5/6 SOC
>> + *
>> + * Open Firmware parsing.
>> + *
>> + * Copyright (c) 2016 Mentor Graphics Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#include <linux/of_platform.h>
>> +#include <media/v4l2-device.h>
>> +#include <media/videobuf2-dma-contig.h>
>> +#include <media/v4l2-subdev.h>
>> +#include <media/v4l2-of.h>
>> +#include <media/v4l2-ctrls.h>
> Please sort out the list alphabetically.
done.
>>
>> +static int of_get_port_count(const struct device_node *np)
>> +{
>> + struct device_node *child;
>> + int num = 0;
>> +
>> + /* if this node is itself a port, return 1 */
>> + if (of_node_cmp(np->name, "port") == 0)
>> + return 1;
>> +
>> + for_each_child_of_node(np, child) {
>> + if (of_node_cmp(child->name, "port") == 0)
>> + num++;
>> + }
> Unneeded bracers.
fixed.
>
>> +static struct imx_media_subdev *
>> +of_parse_subdev(struct imx_media_dev *imxmd, struct device_node *sd_np,
>> + bool is_csi_port)
>> +{
>> + struct imx_media_subdev *imxsd;
>> + int i, num_pads, ret;
>> +
>> + if (!of_device_is_available(sd_np)) {
>> + dev_dbg(imxmd->dev, "%s: %s not enabled\n", __func__,
>> + sd_np->name);
>> + return NULL;
>> + }
>> +
>> + /* register this subdev with async notifier */
>> + imxsd = imx_media_add_async_subdev(imxmd, sd_np, NULL);
>> + if (!imxsd)
>> + return NULL;
>> + if (IS_ERR(imxsd))
>> + return imxsd;
> if (IS_ERR_OR_NULL(imxsd))
> return imxsd;
yep, done.
>> +
>> + if (imxsd->num_sink_pads == 0) {
>> + /* this might be a sensor */
>> + of_parse_sensor(imxmd, imxsd, sd_np);
>> + }
> Unneeded bracers.
ok removed.
>
>> +
>> + for (i = 0; i < num_pads; i++) {
>> + struct device_node *epnode = NULL, *port, *remote_np;
>> + struct imx_media_subdev *remote_imxsd;
>> + struct imx_media_pad *pad;
>> + int remote_pad;
> Too deep indentation, may be move the cycle body into a separate function?
in this case I prefer not to, of_parse_subdev() is called recursively, and I
think it's bad form to hide that fact by moving the recursive call into a
separate function. The indentation is not that deep, only two loops deep.
>
>> +
>> + /* init this pad */
>> + pad = &imxsd->pad[i];
>> + pad->pad.flags = (i < imxsd->num_sink_pads) ?
>> + MEDIA_PAD_FL_SINK : MEDIA_PAD_FL_SOURCE;
>> +
>> + if (is_csi_port)
>> + port = (i < imxsd->num_sink_pads) ? sd_np : NULL;
>> + else
>> + port = of_graph_get_port_by_id(sd_np, i);
>> + if (!port)
>> + continue;
>> +
>> + while ((epnode = of_get_next_child(port, epnode))) {
> Please reuse for_each_child_of_node() here.
done.
>
>> + of_get_remote_pad(epnode, &remote_np, &remote_pad);
>> + if (!remote_np) {
>> + of_node_put(epnode);
> Please remove of_node_put() here, of_get_next_child() does it.
oops, good catch, fixed.
>
>> + continue;
>> + }
>> +
>> + ret = of_add_pad_link(imxmd, pad, sd_np, remote_np,
>> + i, remote_pad);
>> + if (ret) {
>> + imxsd = ERR_PTR(ret);
>> + break;
>> + }
>> +
>> + if (i < imxsd->num_sink_pads) {
>> + /* follow sink endpoints upstream */
>> + remote_imxsd = of_parse_subdev(imxmd,
>> + remote_np,
>> + false);
>> + if (IS_ERR(remote_imxsd)) {
>> + imxsd = remote_imxsd;
>> + break;
>> + }
>> + }
>> +
>> + of_node_put(remote_np);
>> + of_node_put(epnode);
also removed this put of epnode.
>>
>> +
>> +int imx_media_of_parse(struct imx_media_dev *imxmd,
>> + struct imx_media_subdev *(*csi)[4],
>> + struct device_node *np)
>> +{
>> + struct device_node *csi_np;
>> + struct imx_media_subdev *lcsi;
> Please swap two lines above to get the reverse christmas tree ordering.
done.
>
>> + u32 ipu_id, csi_id;
>> + int i, ret;
>> +
>> + for (i = 0; ; i++) {
>> + csi_np = of_parse_phandle(np, "ports", i);
>> + if (!csi_np)
>> + break;
>> +
>> + lcsi = of_parse_subdev(imxmd, csi_np, true);
>> + if (IS_ERR(lcsi)) {
>> + ret = PTR_ERR(lcsi);
>> + goto err_put;
>> + }
>> +
>> + of_property_read_u32(csi_np, "reg", &csi_id);
> Not sure if it is safe enough to ignore return value and potentially
> left csi_id uninitialized.
The CSI nodes are port nodes, and the reg property is required,
so I added a check and error return here.
>
>> + ipu_id = of_alias_get_id(csi_np->parent, "ipu");
>> +
>> + if (ipu_id > 1 || csi_id > 1) {
>> + dev_err(imxmd->dev, "%s: invalid ipu/csi id (%u/%u)\n",
>> + __func__, ipu_id, csi_id);
>> + ret = -EINVAL;
>> + goto err_put;
>> + }
>> +
>> + of_node_put(csi_np);
> You can put the node right after of_alias_get_id() call, then in case
> of error return right from the if block and remove the goto label.
done.
>
>> +
>> + (*csi)[ipu_id * 2 + csi_id] = lcsi;
>> + }
>> +
>> + return 0;
>> +err_put:
>> + of_node_put(csi_np);
>> + return ret;
>> +}
>> diff --git a/drivers/staging/media/imx/imx-media-of.h b/drivers/staging/media/imx/imx-media-of.h
>> new file mode 100644
>> index 0000000..0c61b05
>> --- /dev/null
>> +++ b/drivers/staging/media/imx/imx-media-of.h
>> @@ -0,0 +1,25 @@
>> +/*
>> + * V4L2 Media Controller Driver for Freescale i.MX5/6 SOC
>> + *
>> + * Open Firmware parsing.
>> + *
>> + * Copyright (c) 2016 Mentor Graphics Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#ifndef _IMX_MEDIA_OF_H
>> +#define _IMX_MEDIA_OF_H
>> +
> I do believe you should include some headers or add declarations
> of "struct imx_media_dev", "struct imx_media_subdev", "struct device_node".
actually imx-media-of.h isn't really needed, I just moved those prototypes
into imx-media.h and removed imx-media-of.h.
>> diff --git a/drivers/staging/media/imx/imx-media.h b/drivers/staging/media/imx/imx-media.h
>> new file mode 100644
>> index 0000000..6a018a9
>> --- /dev/null
>> +++ b/drivers/staging/media/imx/imx-media.h
>> @@ -0,0 +1,299 @@
>> +/*
>> + * V4L2 Media Controller Driver for Freescale i.MX5/6 SOC
>> + *
>> + * Copyright (c) 2016 Mentor Graphics Inc.
>> + *
>> + * This program is free software; you can redistribute it and/or modify
>> + * it under the terms of the GNU General Public License as published by
>> + * the Free Software Foundation; either version 2 of the License, or
>> + * (at your option) any later version.
>> + */
>> +#ifndef _IMX_MEDIA_H
>> +#define _IMX_MEDIA_H
> Please insert here an empty line to improve readability.
done.
>
>> +#include <media/v4l2-device.h>
>> +#include <media/v4l2-subdev.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-of.h>
> Please sort out the list alphabetically.
done.
Steve
^ permalink raw reply
* RE: [PATCH v2,7/9] irqchip/ls-scfg-msi: add LS1046a MSI support
From: M.H. Lian @ 2017-01-06 1:45 UTC (permalink / raw)
To: Marc Zyngier, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Cc: Rob Herring, Jason Cooper, Roy Zang, Stuart Yoder, Leo Li,
Scott Wood, Mingkai Hu
In-Reply-To: <7cd3cc33-741a-6ab1-6444-17a626991d33@arm.com>
Hi Marc,
Thanks for your review.
Please see my comments inline.
Thanks,
Minghuan
> -----Original Message-----
> From: Marc Zyngier [mailto:marc.zyngier@arm.com]
> Sent: Thursday, January 05, 2017 11:19 PM
> To: M.H. Lian <minghuan.lian@nxp.com>; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Cc: Rob Herring <robh@kernel.org>; Jason Cooper
> <jason@lakedaemon.net>; Roy Zang <roy.zang@nxp.com>; Mingkai Hu
> <mingkai.hu@nxp.com>; Stuart Yoder <stuart.yoder@nxp.com>; Leo Li
> <leoyang.li@nxp.com>; Scott Wood <scott.wood@nxp.com>
> Subject: Re: [PATCH v2,7/9] irqchip/ls-scfg-msi: add LS1046a MSI support
>
> On 05/01/17 08:10, Minghuan Lian wrote:
> > LS1046a includes 4 MSIRs, each MSIR is assigned a dedicate GIC SPI
> > interrupt and provides 32 MSI interrupts. Compared to previous MSI,
> > LS1046a's IBS(interrupt bit select) shift is changed to 2 and total
> > MSI interrupt number is changed to 128.
> >
> > The patch adds structure 'ls_scfg_msir' to describe MSIR setting and
> > 'ibs_shift' to store the different value between the SoCs.
> >
> > Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
> > ---
> > v2-v1:
> > - MSI dts node change has been merged into the patch 6/9
> >
> > drivers/irqchip/irq-ls-scfg-msi.c | 161
> > +++++++++++++++++++++++++++++---------
> > 1 file changed, 126 insertions(+), 35 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-ls-scfg-msi.c
> > b/drivers/irqchip/irq-ls-scfg-msi.c
> > index cef67cc..67547bd 100644
> > --- a/drivers/irqchip/irq-ls-scfg-msi.c
> > +++ b/drivers/irqchip/irq-ls-scfg-msi.c
> > @@ -17,13 +17,24 @@
> > #include <linux/irq.h>
> > #include <linux/irqchip/chained_irq.h> #include <linux/irqdomain.h>
> > +#include <linux/of_irq.h>
> > #include <linux/of_pci.h>
> > #include <linux/of_platform.h>
> > #include <linux/spinlock.h>
> >
> > -#define MSI_MAX_IRQS 32
> > -#define MSI_IBS_SHIFT 3
> > -#define MSIR 4
> > +#define MSI_IRQS_PER_MSIR 32
> > +#define MSI_MSIR_OFFSET 4
> > +
> > +struct ls_scfg_msi_cfg {
> > + u32 ibs_shift; /* Shift of interrupt bit select */ };
> > +
> > +struct ls_scfg_msir {
> > + struct ls_scfg_msi *msi_data;
> > + unsigned int index;
> > + unsigned int gic_irq;
> > + void __iomem *reg;
> > +};
> >
> > struct ls_scfg_msi {
> > spinlock_t lock;
> > @@ -32,8 +43,11 @@ struct ls_scfg_msi {
> > struct irq_domain *msi_domain;
> > void __iomem *regs;
> > phys_addr_t msiir_addr;
> > - int irq;
> > - DECLARE_BITMAP(used, MSI_MAX_IRQS);
> > + struct ls_scfg_msi_cfg *cfg;
> > + u32 msir_num;
> > + struct ls_scfg_msir *msir;
> > + u32 irqs_num;
> > + unsigned long *used;
> > };
> >
> > static struct irq_chip ls_scfg_msi_irq_chip = { @@ -55,7 +69,7 @@
> > static void ls_scfg_msi_compose_msg(struct irq_data *data, struct
> > msi_msg *msg)
> >
> > msg->address_hi = upper_32_bits(msi_data->msiir_addr);
> > msg->address_lo = lower_32_bits(msi_data->msiir_addr);
> > - msg->data = data->hwirq << MSI_IBS_SHIFT;
> > + msg->data = data->hwirq;
> > }
> >
> > static int ls_scfg_msi_set_affinity(struct irq_data *irq_data, @@
> > -81,8 +95,8 @@ static int ls_scfg_msi_domain_irq_alloc(struct irq_domain
> *domain,
> > WARN_ON(nr_irqs != 1);
> >
> > spin_lock(&msi_data->lock);
> > - pos = find_first_zero_bit(msi_data->used, MSI_MAX_IRQS);
> > - if (pos < MSI_MAX_IRQS)
> > + pos = find_first_zero_bit(msi_data->used, msi_data->irqs_num);
> > + if (pos < msi_data->irqs_num)
> > __set_bit(pos, msi_data->used);
> > else
> > err = -ENOSPC;
> > @@ -106,7 +120,7 @@ static void ls_scfg_msi_domain_irq_free(struct
> irq_domain *domain,
> > int pos;
> >
> > pos = d->hwirq;
> > - if (pos < 0 || pos >= MSI_MAX_IRQS) {
> > + if (pos < 0 || pos >= msi_data->irqs_num) {
> > pr_err("failed to teardown msi. Invalid hwirq %d\n", pos);
> > return;
> > }
> > @@ -123,15 +137,17 @@ static void ls_scfg_msi_domain_irq_free(struct
> > irq_domain *domain,
> >
> > static void ls_scfg_msi_irq_handler(struct irq_desc *desc) {
> > - struct ls_scfg_msi *msi_data = irq_desc_get_handler_data(desc);
> > + struct ls_scfg_msir *msir = irq_desc_get_handler_data(desc);
> > + struct ls_scfg_msi *msi_data = msir->msi_data;
> > unsigned long val;
> > - int pos, virq;
> > + int pos, virq, hwirq;
> >
> > chained_irq_enter(irq_desc_get_chip(desc), desc);
> >
> > - val = ioread32be(msi_data->regs + MSIR);
> > - for_each_set_bit(pos, &val, MSI_MAX_IRQS) {
> > - virq = irq_find_mapping(msi_data->parent, (31 - pos));
> > + val = ioread32be(msir->reg);
> > + for_each_set_bit(pos, &val, MSI_IRQS_PER_MSIR) {
> > + hwirq = ((31 - pos) << msi_data->cfg->ibs_shift) | msir-
> >index;
> > + virq = irq_find_mapping(msi_data->parent, hwirq);
> > if (virq)
> > generic_handle_irq(virq);
> > }
> > @@ -143,7 +159,7 @@ static int ls_scfg_msi_domains_init(struct
> > ls_scfg_msi *msi_data) {
> > /* Initialize MSI domain parent */
> > msi_data->parent = irq_domain_add_linear(NULL,
> > - MSI_MAX_IRQS,
> > + msi_data->irqs_num,
> > &ls_scfg_msi_domain_ops,
> > msi_data);
> > if (!msi_data->parent) {
> > @@ -164,16 +180,83 @@ static int ls_scfg_msi_domains_init(struct
> ls_scfg_msi *msi_data)
> > return 0;
> > }
> >
> > +static int ls_scfg_msi_setup_hwirq(struct ls_scfg_msi *msi_data, int
> > +index) {
> > + struct ls_scfg_msir *msir;
> > + int virq, i, hwirq;
> > +
> > + virq = platform_get_irq(msi_data->pdev, index);
> > + if (virq <= 0)
> > + return -ENODEV;
> > +
> > + msir = &msi_data->msir[index];
> > + msir->index = index;
> > + msir->msi_data = msi_data;
> > + msir->gic_irq = virq;
> > + msir->reg = msi_data->regs + MSI_MSIR_OFFSET + 4 * index;
> > +
> > + irq_set_chained_handler_and_data(msir->gic_irq,
> > + ls_scfg_msi_irq_handler,
> > + msir);
> > +
> > + /* Release the hwirqs corresponding to this MSIR */
> > + for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
> > + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > + bitmap_clear(msi_data->used, hwirq, 1);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int ls_scfg_msi_teardown_hwirq(struct ls_scfg_msir *msir) {
> > + struct ls_scfg_msi *msi_data = msir->msi_data;
> > + int i, hwirq;
> > +
> > + if (msir->gic_irq > 0)
> > + irq_set_chained_handler_and_data(msir->gic_irq, NULL,
> NULL);
> > +
> > + for (i = 0; i < MSI_IRQS_PER_MSIR; i++) {
> > + hwirq = i << msi_data->cfg->ibs_shift | msir->index;
> > + bitmap_set(msi_data->used, hwirq, 1);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct ls_scfg_msi_cfg ls1021_msi_cfg = {
> > + .ibs_shift = 3,
> > +};
> > +
> > +static struct ls_scfg_msi_cfg ls1046_msi_cfg = {
> > + .ibs_shift = 2,
> > +};
> > +
> > +static const struct of_device_id ls_scfg_msi_id[] = {
> > + { .compatible = "fsl,ls1021a-msi", .data = &ls1021_msi_cfg },
> > + { .compatible = "fsl,ls1043a-msi", .data = &ls1021_msi_cfg },
> > + { .compatible = "fsl,ls1046a-msi", .data = &ls1046_msi_cfg },
>
> So after 3 patches adding compatibility between the fsl,1s10 and
> fsl,ls10 names, you discard them? How does it work again with the old DTs?
>
[Minghuan Lian] ok, I will store the old compatible.
This typo makes me very uncomfortable :(
> > + {},
> > +};
> > +MODULE_DEVICE_TABLE(of, ls_scfg_msi_id);
> > +
> > static int ls_scfg_msi_probe(struct platform_device *pdev) {
> > + const struct of_device_id *match;
> > struct ls_scfg_msi *msi_data;
> > struct resource *res;
> > - int ret;
> > + int i, ret;
> > +
> > + match = of_match_device(ls_scfg_msi_id, &pdev->dev);
> > + if (!match)
> > + return -ENODEV;
> >
> > msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data),
> GFP_KERNEL);
> > if (!msi_data)
> > return -ENOMEM;
> >
> > + msi_data->cfg = (struct ls_scfg_msi_cfg *) match->data;
> > +
> > res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> > msi_data->regs = devm_ioremap_resource(&pdev->dev, res);
> > if (IS_ERR(msi_data->regs)) {
> > @@ -182,23 +265,37 @@ static int ls_scfg_msi_probe(struct
> platform_device *pdev)
> > }
> > msi_data->msiir_addr = res->start;
> >
> > - msi_data->irq = platform_get_irq(pdev, 0);
> > - if (msi_data->irq <= 0) {
> > - dev_err(&pdev->dev, "failed to get MSI irq\n");
> > - return -ENODEV;
> > - }
> > -
> > msi_data->pdev = pdev;
> > spin_lock_init(&msi_data->lock);
> >
> > + msi_data->irqs_num = MSI_IRQS_PER_MSIR *
> > + (1 << msi_data->cfg->ibs_shift);
> > + msi_data->used = devm_kcalloc(&pdev->dev,
> > + BITS_TO_LONGS(msi_data->irqs_num),
> > + sizeof(*msi_data->used),
> > + GFP_KERNEL);
> > + if (!msi_data->used)
> > + return -ENOMEM;
> > + /*
> > + * Reserve all the hwirqs
> > + * The available hwirqs will be released in ls1_msi_setup_hwirq()
> > + */
> > + bitmap_set(msi_data->used, 0, msi_data->irqs_num);
> > +
> > + msi_data->msir_num = of_irq_count(pdev->dev.of_node);
> > + msi_data->msir = devm_kcalloc(&pdev->dev, msi_data->msir_num,
> > + sizeof(*msi_data->msir),
> > + GFP_KERNEL);
> > + if (!msi_data->msir)
> > + return -ENOMEM;
> > +
> > + for (i = 0; i < msi_data->msir_num; i++)
> > + ls_scfg_msi_setup_hwirq(msi_data, i);
> > +
> > ret = ls_scfg_msi_domains_init(msi_data);
> > if (ret)
> > return ret;
> >
> > - irq_set_chained_handler_and_data(msi_data->irq,
> > - ls_scfg_msi_irq_handler,
> > - msi_data);
> > -
> > platform_set_drvdata(pdev, msi_data);
> >
> > return 0;
> > @@ -207,8 +304,10 @@ static int ls_scfg_msi_probe(struct
> > platform_device *pdev) static int ls_scfg_msi_remove(struct
> > platform_device *pdev) {
> > struct ls_scfg_msi *msi_data = platform_get_drvdata(pdev);
> > + int i;
> >
> > - irq_set_chained_handler_and_data(msi_data->irq, NULL, NULL);
> > + for (i = 0; i < msi_data->msir_num; i++)
> > + ls_scfg_msi_teardown_hwirq(&msi_data->msir[i]);
> >
> > irq_domain_remove(msi_data->msi_domain);
> > irq_domain_remove(msi_data->parent);
> > @@ -218,14 +317,6 @@ static int ls_scfg_msi_remove(struct
> platform_device *pdev)
> > return 0;
> > }
> >
> > -static const struct of_device_id ls_scfg_msi_id[] = {
> > - { .compatible = "fsl,1s1021a-msi", }, /* a typo */
> > - { .compatible = "fsl,1s1043a-msi", }, /* a typo */
> ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> ^
> these entries definitely need to be restored.
>
> Also, please make sure you have a cover letter at the beginning of the series.
> I flag series to review by flagging the cover letter, and I suspect many of us
> are doing something similar. Not doing so is likely to leave your series
> unreviewed...
[Minghuan Lian] I see. I will add cover letter for this series. And I will
do this for all series of patches.
>
> Thanks,
>
> M.
> --
> Jazz is not dead. It just smells funny...
^ permalink raw reply
* Re: [PATCH v2 3/3] power: bq27xxx: add support for NVRAM R/W access
From: Sebastian Reichel @ 2017-01-06 1:53 UTC (permalink / raw)
To: Matt Ranostay
Cc: tony-4v6yS6AI5VpBDgjK7y7TUQ, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170105021007.22088-4-matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 1876 bytes --]
On Wed, Jan 04, 2017 at 06:10:07PM -0800, Matt Ranostay wrote:
> Initial support for access and modification of the non-volatile regions
> of the bq27425 fuel gauge DesignEnergy, DesignCapacity, and
> TerminateVoltage settings.
>
> This is intended for fine tuning the fuel gauge state machine for the
> respective battery specifications.
>
> Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
> ---
> drivers/power/supply/bq27xxx_battery_i2c.c | 335 +++++++++++++++++++++++++++++
> include/linux/power/bq27xxx_battery.h | 4 +
> 2 files changed, 339 insertions(+)
I only skipped over this one, as the changed DT binding requires
quite some changes in this patch anyways. Here are a couple of
comments how I would like to see this implemented:
Add a patch for the power-supply core, which implements a
structure for the battery info. Something like this:
struct power_supply_battery_info {
uint32 energy; /* µWh */
uint32 power; /* µAh */
uint32 nominal_voltage; /* µV */
/* ... */
};
And a function in the core framework, which gets the information
from DT. The function itself should *not* be DT specific, so that
ACPI/platformdata/whatever support can be added later without
modifying every single driver.
static struct power_supply_battery_info*
power_supply_get_battery_info(struct power_supply *psy) {
if (psy->dt) {
/* get battery phandle or return -ENXIO */
/* fill and return struct */
}
return -ENOTSUP;
}
Then call power_supply_get_battery_info() during bq27xxx probe and
use the struct to initialize the registers. Also I expect that
functionality in bq27xxx_battery.c instead of bq27xxx_battery_i2c.c,
since it's not I²C specific.
-- Sebastian
[-- Attachment #2: signature.asc --]
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^ permalink raw reply
* Re: [PATCH v2 3/4] ARM64: dts: exynos5433: use macros for pinctrl configuration on Exynos5433
From: Andi Shyti @ 2017-01-06 2:23 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Mark Rutland, devicetree@vger.kernel.org, linux-samsung-soc,
Andi Shyti, Javier Martinez Canillas, Catalin Marinas,
Linus Walleij, Will Deacon, Tomasz Figa, stable,
linux-kernel@vger.kernel.org, Chanwoo Choi, Rob Herring,
Kukjin Kim, Sylwester Nawrocki,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <20170105200807.54j2ebve6kqd5bob@kozik-lap>
Hi Krzysztof,
> Andi,
> Please fix missing Signed-off-by and resend with Linus' tags for #1 and
> #2 and with other accumulated tags.
patch #1 has already been merged in mainline:
https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=1259feddd0f83649d5c48d730c140b4f7f3fa288
and patch #2 is in LinusW's -next branch.
does it still make sense to send them again? If you want I can
send again patch 3 and 4 as independent patches with Chanwoo's
review (the only tags).
Thanks,
Andi
^ permalink raw reply
* Re: [PATCH v2 3/3] power: bq27xxx: add support for NVRAM R/W access
From: Matt Ranostay @ 2017-01-06 2:34 UTC (permalink / raw)
To: Sebastian Reichel
Cc: Tony Lindgren, devicetree-u79uwXL29TY76Z2rM5mHXA,
linux-pm-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20170106015314.7qju6eodkwldty6h@earth>
On Thu, Jan 5, 2017 at 5:53 PM, Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org> wrote:
> On Wed, Jan 04, 2017 at 06:10:07PM -0800, Matt Ranostay wrote:
>> Initial support for access and modification of the non-volatile regions
>> of the bq27425 fuel gauge DesignEnergy, DesignCapacity, and
>> TerminateVoltage settings.
>>
>> This is intended for fine tuning the fuel gauge state machine for the
>> respective battery specifications.
>>
>> Cc: Sebastian Reichel <sre-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
>> Signed-off-by: Matt Ranostay <matt-sk+viVC6FLCDq+mSdOJa79kegs52MxvZ@public.gmane.org>
>> ---
>> drivers/power/supply/bq27xxx_battery_i2c.c | 335 +++++++++++++++++++++++++++++
>> include/linux/power/bq27xxx_battery.h | 4 +
>> 2 files changed, 339 insertions(+)
>
> I only skipped over this one, as the changed DT binding requires
> quite some changes in this patch anyways. Here are a couple of
> comments how I would like to see this implemented:
>
> Add a patch for the power-supply core, which implements a
> structure for the battery info. Something like this:
>
> struct power_supply_battery_info {
> uint32 energy; /* µWh */
> uint32 power; /* µAh */
> uint32 nominal_voltage; /* µV */
> /* ... */
> };
>
> And a function in the core framework, which gets the information
> from DT. The function itself should *not* be DT specific, so that
> ACPI/platformdata/whatever support can be added later without
> modifying every single driver.
>
> static struct power_supply_battery_info*
> power_supply_get_battery_info(struct power_supply *psy) {
> if (psy->dt) {
> /* get battery phandle or return -ENXIO */
> /* fill and return struct */
> }
>
> return -ENOTSUP;
> }
>
> Then call power_supply_get_battery_info() during bq27xxx probe and
> use the struct to initialize the registers. Also I expect that
> functionality in bq27xxx_battery.c instead of bq27xxx_battery_i2c.c,
> since it's not I²C specific.
They may not be i2c specific but they are only used by the i2c path of
the code currently. Do you think that platform data would ever have a
struct to pass with the respective data?
Also it would have to be in bq27xxx_battery_setup() and not
bq27xxx_battery_platform_probe() since the former is only thing called
by both code paths.
>
> -- Sebastian
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^ permalink raw reply
* Re: [PATCH v6 3/3] arm: dts: mt2701: Add node for Mediatek JPEG Decoder
From: Rick Chang @ 2017-01-06 2:34 UTC (permalink / raw)
To: Hans Verkuil
Cc: devicetree, Laurent Pinchart, Minghsiu Tsai, srv_heupstream,
linux-kernel, Rob Herring, Hans Verkuil, Matthias Brugger,
linux-mediatek, Mauro Carvalho Chehab, linux-arm-kernel,
linux-media
In-Reply-To: <1479894203.8964.29.camel@mtksdaap41>
Hi Hans,
The dependence on [1] has been merged in 4.10, but [2] has not.Do you have
any idea about this patch series? Should we wait for [2] or we could merge
the source code and dt-binding first?
Best Regards,
Rick
On Wed, 2016-11-23 at 17:43 +0800, Rick Chang wrote:
> On Wed, 2016-11-23 at 09:54 +0800, Rick Chang wrote:
> > Hi Hans,
> >
> > On Tue, 2016-11-22 at 13:43 +0100, Hans Verkuil wrote:
> > > On 22/11/16 04:21, Rick Chang wrote:
> > > > Hi Hans,
> > > >
> > > > On Mon, 2016-11-21 at 15:51 +0100, Hans Verkuil wrote:
> > > >> On 17/11/16 04:38, Rick Chang wrote:
> > > >>> Signed-off-by: Rick Chang <rick.chang@mediatek.com>
> > > >>> Signed-off-by: Minghsiu Tsai <minghsiu.tsai@mediatek.com>
> > > >>> ---
> > > >>> This patch depends on:
> > > >>> CCF "Add clock support for Mediatek MT2701"[1]
> > > >>> iommu and smi "Add the dtsi node of iommu and smi for mt2701"[2]
> > > >>>
> > > >>> [1] http://lists.infradead.org/pipermail/linux-mediatek/2016-October/007271.html
> > > >>> [2] https://patchwork.kernel.org/patch/9164013/
> > > >>
> > > >> I assume that 1 & 2 will appear in 4.10? So this patch needs to go in
> > > >> after the
> > > >> other two are merged in 4.10?
> > > >>
> > > >> Regards,
> > > >>
> > > >> Hans
> > > >
> > > > [1] will appear in 4.10, but [2] will appear latter than 4.10.So this
> > > > patch needs to go in after [1] & [2] will be merged in 4.11.
> > >
> > > So what should I do? Merge the driver for 4.11 and wait with this patch
> > > until [2] is merged in 4.11? Does that sound reasonable?
> > >
> > > Regards,
> > >
> > > Hans
> >
> > What do you think about this? You merge the driver first and I send this
> > patch again after [1] & [2] is merged.
>
> BTW, to prevent merging conflict, the dtsi should be merged by mediatek
> SoC maintainer, Matthias.I think we can only take care on the driver
> part at this moment.
>
^ permalink raw reply
* [PATCH 0/3] Input: add optional enable gpio to pwm-beeper
From: David Lechner @ 2017-01-06 2:43 UTC (permalink / raw)
To: Dmitry Torokhov, Rob Herring, Mark Rutland
Cc: David Lechner, linux-input, devicetree, linux-kernel
This series adds an optional enable gpio to the pwm-beeper driver. This is for
cases when the beeper needs to be "enabled", for example, if there is an
amplifier that drives the speaker that is not always on.
David Lechner (3):
Input: pwm-beeper: suppress error message on probe defer
dt-bindings: Input: Add enable-gpios to pwm-beeper
Input: pwm-beeper: add optional enable gpio
.../devicetree/bindings/input/pwm-beeper.txt | 11 +++++++++
drivers/input/misc/pwm-beeper.c | 27 ++++++++++++++++++----
2 files changed, 34 insertions(+), 4 deletions(-)
--
2.7.4
^ permalink raw reply
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