* [PATCH] pinctrl: qcom: Add msm8998 pinctrl driver
From: Imran Khan @ 2017-01-09 15:00 UTC (permalink / raw)
To: andy.gross
Cc: Imran Khan, Linus Walleij, Rob Herring, Mark Rutland, David Brown,
open list:PIN CONTROL SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:ARM/QUALCOMM SUPPORT,
open list:ARM/QUALCOMM SUPPORT
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8998.
Signed-off-by: Imran Khan <kimran@codeaurora.org>
---
.../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 200 ++
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8998.c | 1933 ++++++++++++++++++++
4 files changed, 2142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8998.c
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
new file mode 100644
index 0000000..23206b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
@@ -0,0 +1,200 @@
+Qualcomm MSM8998 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MSM8998 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,msm8998-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode.
+
+ Valid pins are:
+ gpio0-gpio149
+ Supports mux, bias and drive-strength
+
+ sdc2_clk, sdc2_cmd, sdc2_data
+ Supports bias and drive-strength
+
+ ufs_reset
+ Supports bias and drive-strength
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+
+ blsp_spi1, gpio, blsp_uim1_a, blsp_uart1_a, blsp_i2c1,
+ blsp_spi8, blsp_uart8_a, blsp_uim8_a, qdss_cti0_b,
+ blsp_i2c8, ddr_bist, atest_tsens2, atest_usb1, blsp_spi4,
+ blsp_uart1_b, blsp_uim1_b, wlan1_adc1, atest_usb13,bimc_dte1,
+ tsif1_sync, wlan1_adc0, atest_usb12, bimc_dte0, mdp_vsync_a,
+ blsp_i2c4, atest_gpsadc1, wlan2_adc1, atest_usb11, edp_lcd,
+ dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10, mdp_vsync,
+ m_voc, cam_mclk, pll_bypassnl, qdss_gpio0, pll_reset,
+ qdss_gpio1, qdss_gpio2, qdss_gpio3, cci_i2c, qdss_gpio4,
+ phase_flag14, qdss_gpio5, phase_flag15, qdss_gpio6, qdss_gpio7,
+ cci_timer4, blsp2_spi, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+ qdss_gpio14, qdss_gpio15, cci_timer0, qdss_gpio8, vsense_data0,
+ cci_timer1, qdss_gpio, vsense_data1, cci_timer2, blsp1_spi_b,
+ qdss_gpio9, vsense_mode, cci_timer3, cci_async, blsp1_spi_a,
+ qdss_gpio10, vsense_clkout, hdmi_rcv, hdmi_cec, blsp_spi2,
+ blsp_uart2_a, blsp_uim2_a, pwr_modem, hdmi_ddc, blsp_i2c2,
+ pwr_nav, pwr_crypto, hdmi_hot, edp_hot, pci_e0, jitter_bist,
+ agera_pll, atest_tsens, usb_phy, lpass_slimbus, sd_write,
+ tsif1_error, blsp_spi6, blsp_uart3_b, blsp_uim3_b, blsp_i2c6,
+ bt_reset, blsp_spi3, blsp_uart3_a, blsp_uim3_a, blsp_i2c3,
+ blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a,
+ blsp_i2c9, blsp10_spi_a, blsp_spi7, blsp_uart7_a, blsp_uim7_a,
+ blsp_i2c7, qua_mi2s, blsp10_spi, gcc_gp1_a, ssc_irq, blsp_spi11,
+ blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, qdss_cti1_a, gcc_gp3_a,
+ blsp_i2c11, cri_trng0, cri_trng1, cri_trng, pri_mi2s, sp_cmu,
+ blsp_spi10, blsp_uart7_b, blsp_uim7_b, pri_mi2s_ws, blsp_i2c10,
+ spkr_i2s, audio_ref, blsp9_spi, tsense_pwm1, tsense_pwm2,
+ btfm_slimbus, phase_flag0, ter_mi2s, phase_flag7, phase_flag8,
+ phase_flag9, phase_flag4, gcc_gp1_b, sec_mi2s, blsp_spi12,
+ blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, gcc_gp3_b, blsp_i2c12,
+ blsp_spi5, blsp_uart2_b, blsp_uim2_b, blsp_i2c5, tsif1_clk,
+ phase_flag10, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, tsif1_data, sdc4_cmd,
+ tgu_ch1, phase_flag1, tsif2_error, sdc43, vfr_1, phase_flag2,
+ tsif2_clk, sdc4_clk, tsif2_en, sdc42, sd_card, tsif2_data, sdc41,
+ tsif2_sync, sdc40, phase_flag3, mdp_vsync_b, ldo_en, ldo_update,
+ blsp_uart8, blsp11_i2c, prng_rosc, phase_flag5, uim2_data, uim2_clk,
+ uim2_reset, uim2_present, uim1_data, uim1_clk, uim1_reset,
+ uim1_present, uim_batt, phase_flag16, nav_dr, phase_flag11, phase_flag12,
+ phase_flag13, atest_char, adsp_ext, phase_flag17, atest_char3, phase_flag18,
+ atest_char2, phase_flag19, atest_char1, phase_flag20, atest_char0,
+ phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25,
+ modem_tsync, nav_pps, phase_flag26, phase_flag27, qlink_request, phase_flag28,
+ qlink_enable, phase_flag6, phase_flag29, phase_flag30, phase_flag31,
+ pa_indicator, ssbi1, isense_dbg, mss_lte
+
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@03400000 {
+ compatible = "qcom,msm8998-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <0 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8_a";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 3ebdc01..f572bc8 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_MSM8996
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
+config PINCTRL_MSM8998
+ tristate "Qualcomm MSM8998 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
+
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on GPIOLIB && ACPI
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ab47764..dba7303 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
+obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
new file mode 100644
index 0000000..584a5f0
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -0,0 +1,1933 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define NORTH 0x500000
+#define WEST 0x100000
+#define EAST 0x900000
+#define REG_SIZE 0x1000
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = base + REG_SIZE * id, \
+ .io_reg = base + 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+ .intr_status_reg = base + 0xc + REG_SIZE * id, \
+ .intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+static const struct pinctrl_pin_desc msm8998_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "SDC2_CLK"),
+ PINCTRL_PIN(151, "SDC2_CMD"),
+ PINCTRL_PIN(152, "SDC2_DATA"),
+ PINCTRL_PIN(153, "UFS_RESET"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+
+static const unsigned int sdc2_clk_pins[] = { 150 };
+static const unsigned int sdc2_cmd_pins[] = { 151 };
+static const unsigned int sdc2_data_pins[] = { 152 };
+static const unsigned int ufs_reset_pins[] = { 153 };
+
+enum msm8998_functions {
+ msm_mux_blsp_spi1,
+ msm_mux_blsp_uim1_a,
+ msm_mux_blsp_uart1_a,
+ msm_mux_blsp_i2c1,
+ msm_mux_blsp_spi8,
+ msm_mux_blsp_uart8_a,
+ msm_mux_blsp_uim8_a,
+ msm_mux_qdss_cti0_b,
+ msm_mux_blsp_i2c8,
+ msm_mux_ddr_bist,
+ msm_mux_atest_tsens2,
+ msm_mux_atest_usb1,
+ msm_mux_blsp_spi4,
+ msm_mux_blsp_uart1_b,
+ msm_mux_blsp_uim1_b,
+ msm_mux_wlan1_adc1,
+ msm_mux_atest_usb13,
+ msm_mux_bimc_dte1,
+ msm_mux_tsif1_sync,
+ msm_mux_wlan1_adc0,
+ msm_mux_atest_usb12,
+ msm_mux_bimc_dte0,
+ msm_mux_mdp_vsync_a,
+ msm_mux_blsp_i2c4,
+ msm_mux_atest_gpsadc1,
+ msm_mux_wlan2_adc1,
+ msm_mux_atest_usb11,
+ msm_mux_edp_lcd,
+ msm_mux_dbg_out,
+ msm_mux_atest_gpsadc0,
+ msm_mux_wlan2_adc0,
+ msm_mux_atest_usb10,
+ msm_mux_mdp_vsync,
+ msm_mux_m_voc,
+ msm_mux_cam_mclk,
+ msm_mux_pll_bypassnl,
+ msm_mux_qdss_gpio0,
+ msm_mux_pll_reset,
+ msm_mux_qdss_gpio1,
+ msm_mux_qdss_gpio2,
+ msm_mux_qdss_gpio3,
+ msm_mux_cci_i2c,
+ msm_mux_qdss_gpio4,
+ msm_mux_phase_flag14,
+ msm_mux_qdss_gpio5,
+ msm_mux_phase_flag15,
+ msm_mux_qdss_gpio6,
+ msm_mux_qdss_gpio7,
+ msm_mux_cci_timer4,
+ msm_mux_blsp2_spi,
+ msm_mux_qdss_gpio11,
+ msm_mux_qdss_gpio12,
+ msm_mux_qdss_gpio13,
+ msm_mux_qdss_gpio14,
+ msm_mux_qdss_gpio15,
+ msm_mux_cci_timer0,
+ msm_mux_qdss_gpio8,
+ msm_mux_vsense_data0,
+ msm_mux_cci_timer1,
+ msm_mux_qdss_gpio,
+ msm_mux_vsense_data1,
+ msm_mux_cci_timer2,
+ msm_mux_blsp1_spi_b,
+ msm_mux_qdss_gpio9,
+ msm_mux_vsense_mode,
+ msm_mux_cci_timer3,
+ msm_mux_cci_async,
+ msm_mux_blsp1_spi_a,
+ msm_mux_qdss_gpio10,
+ msm_mux_vsense_clkout,
+ msm_mux_hdmi_rcv,
+ msm_mux_hdmi_cec,
+ msm_mux_blsp_spi2,
+ msm_mux_blsp_uart2_a,
+ msm_mux_blsp_uim2_a,
+ msm_mux_pwr_modem,
+ msm_mux_hdmi_ddc,
+ msm_mux_blsp_i2c2,
+ msm_mux_pwr_nav,
+ msm_mux_pwr_crypto,
+ msm_mux_hdmi_hot,
+ msm_mux_edp_hot,
+ msm_mux_pci_e0,
+ msm_mux_jitter_bist,
+ msm_mux_agera_pll,
+ msm_mux_atest_tsens,
+ msm_mux_usb_phy,
+ msm_mux_lpass_slimbus,
+ msm_mux_sd_write,
+ msm_mux_tsif1_error,
+ msm_mux_blsp_spi6,
+ msm_mux_blsp_uart3_b,
+ msm_mux_blsp_uim3_b,
+ msm_mux_blsp_i2c6,
+ msm_mux_bt_reset,
+ msm_mux_blsp_spi3,
+ msm_mux_blsp_uart3_a,
+ msm_mux_blsp_uim3_a,
+ msm_mux_blsp_i2c3,
+ msm_mux_blsp_spi9,
+ msm_mux_blsp_uart9_a,
+ msm_mux_blsp_uim9_a,
+ msm_mux_blsp10_spi_b,
+ msm_mux_qdss_cti0_a,
+ msm_mux_blsp_i2c9,
+ msm_mux_blsp10_spi_a,
+ msm_mux_blsp_spi7,
+ msm_mux_blsp_uart7_a,
+ msm_mux_blsp_uim7_a,
+ msm_mux_blsp_i2c7,
+ msm_mux_qua_mi2s,
+ msm_mux_blsp10_spi,
+ msm_mux_gcc_gp1_a,
+ msm_mux_ssc_irq,
+ msm_mux_blsp_spi11,
+ msm_mux_blsp_uart8_b,
+ msm_mux_blsp_uim8_b,
+ msm_mux_gcc_gp2_a,
+ msm_mux_qdss_cti1_a,
+ msm_mux_gcc_gp3_a,
+ msm_mux_blsp_i2c11,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cri_trng,
+ msm_mux_pri_mi2s,
+ msm_mux_sp_cmu,
+ msm_mux_blsp_spi10,
+ msm_mux_blsp_uart7_b,
+ msm_mux_blsp_uim7_b,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_blsp_i2c10,
+ msm_mux_spkr_i2s,
+ msm_mux_audio_ref,
+ msm_mux_blsp9_spi,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_btfm_slimbus,
+ msm_mux_phase_flag0,
+ msm_mux_ter_mi2s,
+ msm_mux_phase_flag7,
+ msm_mux_phase_flag8,
+ msm_mux_phase_flag9,
+ msm_mux_phase_flag4,
+ msm_mux_gcc_gp1_b,
+ msm_mux_sec_mi2s,
+ msm_mux_blsp_spi12,
+ msm_mux_blsp_uart9_b,
+ msm_mux_blsp_uim9_b,
+ msm_mux_gcc_gp2_b,
+ msm_mux_gcc_gp3_b,
+ msm_mux_blsp_i2c12,
+ msm_mux_blsp_spi5,
+ msm_mux_blsp_uart2_b,
+ msm_mux_blsp_uim2_b,
+ msm_mux_blsp_i2c5,
+ msm_mux_tsif1_clk,
+ msm_mux_phase_flag10,
+ msm_mux_tsif1_en,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_blsp1_spi,
+ msm_mux_tgu_ch0,
+ msm_mux_qdss_cti1_b,
+ msm_mux_tsif1_data,
+ msm_mux_sdc4_cmd,
+ msm_mux_tgu_ch1,
+ msm_mux_phase_flag1,
+ msm_mux_tsif2_error,
+ msm_mux_sdc43,
+ msm_mux_vfr_1,
+ msm_mux_phase_flag2,
+ msm_mux_tsif2_clk,
+ msm_mux_sdc4_clk,
+ msm_mux_tsif2_en,
+ msm_mux_sdc42,
+ msm_mux_sd_card,
+ msm_mux_tsif2_data,
+ msm_mux_sdc41,
+ msm_mux_tsif2_sync,
+ msm_mux_sdc40,
+ msm_mux_phase_flag3,
+ msm_mux_mdp_vsync_b,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_blsp_uart8,
+ msm_mux_blsp11_i2c,
+ msm_mux_prng_rosc,
+ msm_mux_phase_flag5,
+ msm_mux_uim2_data,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_reset,
+ msm_mux_uim2_present,
+ msm_mux_uim1_data,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_reset,
+ msm_mux_uim1_present,
+ msm_mux_uim_batt,
+ msm_mux_phase_flag16,
+ msm_mux_nav_dr,
+ msm_mux_phase_flag11,
+ msm_mux_phase_flag12,
+ msm_mux_phase_flag13,
+ msm_mux_atest_char,
+ msm_mux_adsp_ext,
+ msm_mux_phase_flag17,
+ msm_mux_atest_char3,
+ msm_mux_phase_flag18,
+ msm_mux_atest_char2,
+ msm_mux_phase_flag19,
+ msm_mux_atest_char1,
+ msm_mux_phase_flag20,
+ msm_mux_atest_char0,
+ msm_mux_phase_flag21,
+ msm_mux_phase_flag22,
+ msm_mux_phase_flag23,
+ msm_mux_phase_flag24,
+ msm_mux_phase_flag25,
+ msm_mux_modem_tsync,
+ msm_mux_nav_pps,
+ msm_mux_phase_flag26,
+ msm_mux_phase_flag27,
+ msm_mux_qlink_request,
+ msm_mux_phase_flag28,
+ msm_mux_qlink_enable,
+ msm_mux_phase_flag6,
+ msm_mux_phase_flag29,
+ msm_mux_phase_flag30,
+ msm_mux_phase_flag31,
+ msm_mux_pa_indicator,
+ msm_mux_ssbi1,
+ msm_mux_isense_dbg,
+ msm_mux_mss_lte,
+ msm_mux_gpio,
+ msm_mux_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149",
+};
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const blsp_uim1_a_groups[] = {
+ "gpio0", "gpio1",
+};
+static const char * const blsp_uart1_a_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const blsp_i2c1_groups[] = {
+ "gpio2", "gpio3",
+};
+static const char * const blsp_spi8_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const blsp_uart8_a_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const blsp_uim8_a_groups[] = {
+ "gpio4", "gpio5",
+};
+static const char * const qdss_cti0_b_groups[] = {
+ "gpio4", "gpio5",
+};
+static const char * const blsp_i2c8_groups[] = {
+ "gpio6", "gpio7",
+};
+static const char * const ddr_bist_groups[] = {
+ "gpio7", "gpio8", "gpio9", "gpio10",
+};
+static const char * const atest_tsens2_groups[] = {
+ "gpio7",
+};
+static const char * const atest_usb1_groups[] = {
+ "gpio7",
+};
+static const char * const blsp_spi4_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_uart1_b_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_uim1_b_groups[] = {
+ "gpio8", "gpio9",
+};
+static const char * const wlan1_adc1_groups[] = {
+ "gpio8",
+};
+static const char * const atest_usb13_groups[] = {
+ "gpio8",
+};
+static const char * const bimc_dte1_groups[] = {
+ "gpio8", "gpio10",
+};
+static const char * const tsif1_sync_groups[] = {
+ "gpio9",
+};
+static const char * const wlan1_adc0_groups[] = {
+ "gpio9",
+};
+static const char * const atest_usb12_groups[] = {
+ "gpio9",
+};
+static const char * const bimc_dte0_groups[] = {
+ "gpio9", "gpio11",
+};
+static const char * const mdp_vsync_a_groups[] = {
+ "gpio10", "gpio11",
+};
+static const char * const blsp_i2c4_groups[] = {
+ "gpio10", "gpio11",
+};
+static const char * const atest_gpsadc1_groups[] = {
+ "gpio10",
+};
+static const char * const wlan2_adc1_groups[] = {
+ "gpio10",
+};
+static const char * const atest_usb11_groups[] = {
+ "gpio10",
+};
+static const char * const edp_lcd_groups[] = {
+ "gpio11",
+};
+static const char * const dbg_out_groups[] = {
+ "gpio11",
+};
+static const char * const atest_gpsadc0_groups[] = {
+ "gpio11",
+};
+static const char * const wlan2_adc0_groups[] = {
+ "gpio11",
+};
+static const char * const atest_usb10_groups[] = {
+ "gpio11",
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio12",
+};
+static const char * const m_voc_groups[] = {
+ "gpio12",
+};
+static const char * const cam_mclk_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16",
+};
+static const char * const pll_bypassnl_groups[] = {
+ "gpio13",
+};
+static const char * const qdss_gpio0_groups[] = {
+ "gpio13", "gpio117",
+};
+static const char * const pll_reset_groups[] = {
+ "gpio14",
+};
+static const char * const qdss_gpio1_groups[] = {
+ "gpio14", "gpio118",
+};
+static const char * const qdss_gpio2_groups[] = {
+ "gpio15", "gpio119",
+};
+static const char * const qdss_gpio3_groups[] = {
+ "gpio16", "gpio120",
+};
+static const char * const cci_i2c_groups[] = {
+ "gpio17", "gpio18", "gpio19", "gpio20",
+};
+static const char * const qdss_gpio4_groups[] = {
+ "gpio17", "gpio121",
+};
+static const char * const phase_flag14_groups[] = {
+ "gpio18",
+};
+static const char * const qdss_gpio5_groups[] = {
+ "gpio18", "gpio122",
+};
+static const char * const phase_flag15_groups[] = {
+ "gpio19",
+};
+static const char * const qdss_gpio6_groups[] = {
+ "gpio19", "gpio41",
+};
+static const char * const qdss_gpio7_groups[] = {
+ "gpio20", "gpio42",
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio25",
+};
+static const char * const blsp2_spi_groups[] = {
+ "gpio25", "gpio29", "gpio30",
+};
+static const char * const qdss_gpio11_groups[] = {
+ "gpio25", "gpio79",
+};
+static const char * const qdss_gpio12_groups[] = {
+ "gpio26", "gpio80",
+};
+static const char * const qdss_gpio13_groups[] = {
+ "gpio27", "gpio93",
+};
+static const char * const qdss_gpio14_groups[] = {
+ "gpio28", "gpio43",
+};
+static const char * const qdss_gpio15_groups[] = {
+ "gpio29", "gpio44",
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio21",
+};
+static const char * const qdss_gpio8_groups[] = {
+ "gpio21", "gpio75",
+};
+static const char * const vsense_data0_groups[] = {
+ "gpio21",
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio22",
+};
+static const char * const qdss_gpio_groups[] = {
+ "gpio22", "gpio30", "gpio123", "gpio124",
+};
+static const char * const vsense_data1_groups[] = {
+ "gpio22",
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio23",
+};
+static const char * const blsp1_spi_b_groups[] = {
+ "gpio23", "gpio28",
+};
+static const char * const qdss_gpio9_groups[] = {
+ "gpio23", "gpio76",
+};
+static const char * const vsense_mode_groups[] = {
+ "gpio23",
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio24",
+};
+static const char * const cci_async_groups[] = {
+ "gpio24", "gpio25", "gpio26",
+};
+static const char * const blsp1_spi_a_groups[] = {
+ "gpio24", "gpio27",
+};
+static const char * const qdss_gpio10_groups[] = {
+ "gpio24", "gpio77",
+};
+static const char * const vsense_clkout_groups[] = {
+ "gpio24",
+};
+static const char * const hdmi_rcv_groups[] = {
+ "gpio30",
+};
+static const char * const hdmi_cec_groups[] = {
+ "gpio31",
+};
+static const char * const blsp_spi2_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const blsp_uart2_a_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const blsp_uim2_a_groups[] = {
+ "gpio31", "gpio34",
+};
+static const char * const pwr_modem_groups[] = {
+ "gpio31",
+};
+static const char * const hdmi_ddc_groups[] = {
+ "gpio32", "gpio33",
+};
+static const char * const blsp_i2c2_groups[] = {
+ "gpio32", "gpio33",
+};
+static const char * const pwr_nav_groups[] = {
+ "gpio32",
+};
+static const char * const pwr_crypto_groups[] = {
+ "gpio33",
+};
+static const char * const hdmi_hot_groups[] = {
+ "gpio34",
+};
+static const char * const edp_hot_groups[] = {
+ "gpio34",
+};
+static const char * const pci_e0_groups[] = {
+ "gpio35", "gpio36", "gpio37",
+};
+static const char * const jitter_bist_groups[] = {
+ "gpio35",
+};
+static const char * const agera_pll_groups[] = {
+ "gpio36", "gpio37",
+};
+static const char * const atest_tsens_groups[] = {
+ "gpio36",
+};
+static const char * const usb_phy_groups[] = {
+ "gpio38",
+};
+static const char * const lpass_slimbus_groups[] = {
+ "gpio39", "gpio70", "gpio71", "gpio72",
+};
+static const char * const sd_write_groups[] = {
+ "gpio40",
+};
+static const char * const tsif1_error_groups[] = {
+ "gpio40",
+};
+static const char * const blsp_spi6_groups[] = {
+ "gpio41", "gpio42", "gpio43", "gpio44",
+};
+static const char * const blsp_uart3_b_groups[] = {
+ "gpio41", "gpio42", "gpio43", "gpio44",
+};
+static const char * const blsp_uim3_b_groups[] = {
+ "gpio41", "gpio42",
+};
+static const char * const blsp_i2c6_groups[] = {
+ "gpio43", "gpio44",
+};
+static const char * const bt_reset_groups[] = {
+ "gpio45",
+};
+static const char * const blsp_spi3_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48",
+};
+static const char * const blsp_uart3_a_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48",
+};
+static const char * const blsp_uim3_a_groups[] = {
+ "gpio45", "gpio46",
+};
+static const char * const blsp_i2c3_groups[] = {
+ "gpio47", "gpio48",
+};
+static const char * const blsp_spi9_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const blsp_uart9_a_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const blsp_uim9_a_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const blsp10_spi_b_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const qdss_cti0_a_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const blsp_i2c9_groups[] = {
+ "gpio51", "gpio52",
+};
+static const char * const blsp10_spi_a_groups[] = {
+ "gpio51", "gpio52",
+};
+static const char * const blsp_spi7_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const blsp_uart7_a_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const blsp_uim7_a_groups[] = {
+ "gpio53", "gpio54",
+};
+static const char * const blsp_i2c7_groups[] = {
+ "gpio55", "gpio56",
+};
+static const char * const qua_mi2s_groups[] = {
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+};
+static const char * const blsp10_spi_groups[] = {
+ "gpio57",
+};
+static const char * const gcc_gp1_a_groups[] = {
+ "gpio57",
+};
+static const char * const ssc_irq_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
+ "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
+ "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
+};
+static const char * const blsp_spi11_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+static const char * const blsp_uart8_b_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+static const char * const blsp_uim8_b_groups[] = {
+ "gpio58", "gpio59",
+};
+static const char * const gcc_gp2_a_groups[] = {
+ "gpio58",
+};
+static const char * const qdss_cti1_a_groups[] = {
+ "gpio58", "gpio59",
+};
+static const char * const gcc_gp3_a_groups[] = {
+ "gpio59",
+};
+static const char * const blsp_i2c11_groups[] = {
+ "gpio60", "gpio61",
+};
+static const char * const cri_trng0_groups[] = {
+ "gpio60",
+};
+static const char * const cri_trng1_groups[] = {
+ "gpio61",
+};
+static const char * const cri_trng_groups[] = {
+ "gpio62",
+};
+static const char * const pri_mi2s_groups[] = {
+ "gpio64", "gpio65", "gpio67", "gpio68",
+};
+static const char * const sp_cmu_groups[] = {
+ "gpio64",
+};
+static const char * const blsp_spi10_groups[] = {
+ "gpio65", "gpio66", "gpio67", "gpio68",
+};
+static const char * const blsp_uart7_b_groups[] = {
+ "gpio65", "gpio66", "gpio67", "gpio68",
+};
+static const char * const blsp_uim7_b_groups[] = {
+ "gpio65", "gpio66",
+};
+static const char * const pri_mi2s_ws_groups[] = {
+ "gpio66",
+};
+static const char * const blsp_i2c10_groups[] = {
+ "gpio67", "gpio68",
+};
+static const char * const spkr_i2s_groups[] = {
+ "gpio69", "gpio70", "gpio71", "gpio72",
+};
+static const char * const audio_ref_groups[] = {
+ "gpio69",
+};
+static const char * const blsp9_spi_groups[] = {
+ "gpio70", "gpio71", "gpio72",
+};
+static const char * const tsense_pwm1_groups[] = {
+ "gpio71",
+};
+static const char * const tsense_pwm2_groups[] = {
+ "gpio71",
+};
+static const char * const btfm_slimbus_groups[] = {
+ "gpio73", "gpio74",
+};
+static const char * const phase_flag0_groups[] = {
+ "gpio73",
+};
+static const char * const ter_mi2s_groups[] = {
+ "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
+};
+static const char * const phase_flag7_groups[] = {
+ "gpio74",
+};
+static const char * const phase_flag8_groups[] = {
+ "gpio75",
+};
+static const char * const phase_flag9_groups[] = {
+ "gpio76",
+};
+static const char * const phase_flag4_groups[] = {
+ "gpio77",
+};
+static const char * const gcc_gp1_b_groups[] = {
+ "gpio78",
+};
+static const char * const sec_mi2s_groups[] = {
+ "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
+};
+static const char * const blsp_spi12_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+static const char * const blsp_uart9_b_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+static const char * const blsp_uim9_b_groups[] = {
+ "gpio81", "gpio82",
+};
+static const char * const gcc_gp2_b_groups[] = {
+ "gpio81",
+};
+static const char * const gcc_gp3_b_groups[] = {
+ "gpio82",
+};
+static const char * const blsp_i2c12_groups[] = {
+ "gpio83", "gpio84",
+};
+static const char * const blsp_spi5_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio88",
+};
+static const char * const blsp_uart2_b_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio88",
+};
+static const char * const blsp_uim2_b_groups[] = {
+ "gpio85", "gpio86",
+};
+static const char * const blsp_i2c5_groups[] = {
+ "gpio87", "gpio88",
+};
+static const char * const tsif1_clk_groups[] = {
+ "gpio89",
+};
+static const char * const phase_flag10_groups[] = {
+ "gpio89",
+};
+static const char * const tsif1_en_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync0_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync1_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync2_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync3_groups[] = {
+ "gpio90",
+};
+static const char * const blsp1_spi_groups[] = {
+ "gpio90",
+};
+static const char * const tgu_ch0_groups[] = {
+ "gpio90",
+};
+static const char * const qdss_cti1_b_groups[] = {
+ "gpio90", "gpio91",
+};
+static const char * const tsif1_data_groups[] = {
+ "gpio91",
+};
+static const char * const sdc4_cmd_groups[] = {
+ "gpio91",
+};
+static const char * const tgu_ch1_groups[] = {
+ "gpio91",
+};
+static const char * const phase_flag1_groups[] = {
+ "gpio91",
+};
+static const char * const tsif2_error_groups[] = {
+ "gpio92",
+};
+static const char * const sdc43_groups[] = {
+ "gpio92",
+};
+static const char * const vfr_1_groups[] = {
+ "gpio92",
+};
+static const char * const phase_flag2_groups[] = {
+ "gpio92",
+};
+static const char * const tsif2_clk_groups[] = {
+ "gpio93",
+};
+static const char * const sdc4_clk_groups[] = {
+ "gpio93",
+};
+static const char * const tsif2_en_groups[] = {
+ "gpio94",
+};
+static const char * const sdc42_groups[] = {
+ "gpio94",
+};
+static const char * const sd_card_groups[] = {
+ "gpio95",
+};
+static const char * const tsif2_data_groups[] = {
+ "gpio95",
+};
+static const char * const sdc41_groups[] = {
+ "gpio95",
+};
+static const char * const tsif2_sync_groups[] = {
+ "gpio96",
+};
+static const char * const sdc40_groups[] = {
+ "gpio96",
+};
+static const char * const phase_flag3_groups[] = {
+ "gpio96",
+};
+static const char * const mdp_vsync_b_groups[] = {
+ "gpio97", "gpio98",
+};
+static const char * const ldo_en_groups[] = {
+ "gpio97",
+};
+static const char * const ldo_update_groups[] = {
+ "gpio98",
+};
+static const char * const blsp_uart8_groups[] = {
+ "gpio100", "gpio101",
+};
+static const char * const blsp11_i2c_groups[] = {
+ "gpio102", "gpio103",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio102",
+};
+static const char * const phase_flag5_groups[] = {
+ "gpio103",
+};
+static const char * const uim2_data_groups[] = {
+ "gpio105",
+};
+static const char * const uim2_clk_groups[] = {
+ "gpio106",
+};
+static const char * const uim2_reset_groups[] = {
+ "gpio107",
+};
+static const char * const uim2_present_groups[] = {
+ "gpio108",
+};
+static const char * const uim1_data_groups[] = {
+ "gpio109",
+};
+static const char * const uim1_clk_groups[] = {
+ "gpio110",
+};
+static const char * const uim1_reset_groups[] = {
+ "gpio111",
+};
+static const char * const uim1_present_groups[] = {
+ "gpio112",
+};
+static const char * const uim_batt_groups[] = {
+ "gpio113",
+};
+static const char * const phase_flag16_groups[] = {
+ "gpio114",
+};
+static const char * const nav_dr_groups[] = {
+ "gpio115",
+};
+static const char * const phase_flag11_groups[] = {
+ "gpio115",
+};
+static const char * const phase_flag12_groups[] = {
+ "gpio116",
+};
+static const char * const phase_flag13_groups[] = {
+ "gpio117",
+};
+static const char * const atest_char_groups[] = {
+ "gpio117",
+};
+static const char * const adsp_ext_groups[] = {
+ "gpio118",
+};
+static const char * const phase_flag17_groups[] = {
+ "gpio118",
+};
+static const char * const atest_char3_groups[] = {
+ "gpio118",
+};
+static const char * const phase_flag18_groups[] = {
+ "gpio119",
+};
+static const char * const atest_char2_groups[] = {
+ "gpio119",
+};
+static const char * const phase_flag19_groups[] = {
+ "gpio120",
+};
+static const char * const atest_char1_groups[] = {
+ "gpio120",
+};
+static const char * const phase_flag20_groups[] = {
+ "gpio121",
+};
+static const char * const atest_char0_groups[] = {
+ "gpio121",
+};
+static const char * const phase_flag21_groups[] = {
+ "gpio122",
+};
+static const char * const phase_flag22_groups[] = {
+ "gpio123",
+};
+static const char * const phase_flag23_groups[] = {
+ "gpio124",
+};
+static const char * const phase_flag24_groups[] = {
+ "gpio125",
+};
+static const char * const phase_flag25_groups[] = {
+ "gpio126",
+};
+static const char * const modem_tsync_groups[] = {
+ "gpio128",
+};
+static const char * const nav_pps_groups[] = {
+ "gpio128",
+};
+static const char * const phase_flag26_groups[] = {
+ "gpio128",
+};
+static const char * const phase_flag27_groups[] = {
+ "gpio129",
+};
+static const char * const qlink_request_groups[] = {
+ "gpio130",
+};
+static const char * const phase_flag28_groups[] = {
+ "gpio130",
+};
+static const char * const qlink_enable_groups[] = {
+ "gpio131",
+};
+static const char * const phase_flag6_groups[] = {
+ "gpio131",
+};
+static const char * const phase_flag29_groups[] = {
+ "gpio132",
+};
+static const char * const phase_flag30_groups[] = {
+ "gpio133",
+};
+static const char * const phase_flag31_groups[] = {
+ "gpio134",
+};
+static const char * const pa_indicator_groups[] = {
+ "gpio135",
+};
+static const char * const ssbi1_groups[] = {
+ "gpio142",
+};
+static const char * const isense_dbg_groups[] = {
+ "gpio143",
+};
+static const char * const mss_lte_groups[] = {
+ "gpio144", "gpio145",
+};
+
+static const struct msm_function msm8998_functions[] = {
+ FUNCTION(blsp_spi1),
+ FUNCTION(gpio),
+ FUNCTION(blsp_uim1_a),
+ FUNCTION(blsp_uart1_a),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_spi8),
+ FUNCTION(blsp_uart8_a),
+ FUNCTION(blsp_uim8_a),
+ FUNCTION(qdss_cti0_b),
+ FUNCTION(blsp_i2c8),
+ FUNCTION(ddr_bist),
+ FUNCTION(atest_tsens2),
+ FUNCTION(atest_usb1),
+ FUNCTION(blsp_spi4),
+ FUNCTION(blsp_uart1_b),
+ FUNCTION(blsp_uim1_b),
+ FUNCTION(wlan1_adc1),
+ FUNCTION(atest_usb13),
+ FUNCTION(bimc_dte1),
+ FUNCTION(tsif1_sync),
+ FUNCTION(wlan1_adc0),
+ FUNCTION(atest_usb12),
+ FUNCTION(bimc_dte0),
+ FUNCTION(mdp_vsync_a),
+ FUNCTION(blsp_i2c4),
+ FUNCTION(atest_gpsadc1),
+ FUNCTION(wlan2_adc1),
+ FUNCTION(atest_usb11),
+ FUNCTION(edp_lcd),
+ FUNCTION(dbg_out),
+ FUNCTION(atest_gpsadc0),
+ FUNCTION(wlan2_adc0),
+ FUNCTION(atest_usb10),
+ FUNCTION(mdp_vsync),
+ FUNCTION(m_voc),
+ FUNCTION(cam_mclk),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(qdss_gpio0),
+ FUNCTION(pll_reset),
+ FUNCTION(qdss_gpio1),
+ FUNCTION(qdss_gpio2),
+ FUNCTION(qdss_gpio3),
+ FUNCTION(cci_i2c),
+ FUNCTION(qdss_gpio4),
+ FUNCTION(phase_flag14),
+ FUNCTION(qdss_gpio5),
+ FUNCTION(phase_flag15),
+ FUNCTION(qdss_gpio6),
+ FUNCTION(qdss_gpio7),
+ FUNCTION(cci_timer4),
+ FUNCTION(blsp2_spi),
+ FUNCTION(qdss_gpio11),
+ FUNCTION(qdss_gpio12),
+ FUNCTION(qdss_gpio13),
+ FUNCTION(qdss_gpio14),
+ FUNCTION(qdss_gpio15),
+ FUNCTION(cci_timer0),
+ FUNCTION(qdss_gpio8),
+ FUNCTION(vsense_data0),
+ FUNCTION(cci_timer1),
+ FUNCTION(qdss_gpio),
+ FUNCTION(vsense_data1),
+ FUNCTION(cci_timer2),
+ FUNCTION(blsp1_spi_b),
+ FUNCTION(qdss_gpio9),
+ FUNCTION(vsense_mode),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_async),
+ FUNCTION(blsp1_spi_a),
+ FUNCTION(qdss_gpio10),
+ FUNCTION(vsense_clkout),
+ FUNCTION(hdmi_rcv),
+ FUNCTION(hdmi_cec),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_uart2_a),
+ FUNCTION(blsp_uim2_a),
+ FUNCTION(pwr_modem),
+ FUNCTION(hdmi_ddc),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(pwr_nav),
+ FUNCTION(pwr_crypto),
+ FUNCTION(hdmi_hot),
+ FUNCTION(edp_hot),
+ FUNCTION(pci_e0),
+ FUNCTION(jitter_bist),
+ FUNCTION(agera_pll),
+ FUNCTION(atest_tsens),
+ FUNCTION(usb_phy),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(sd_write),
+ FUNCTION(tsif1_error),
+ FUNCTION(blsp_spi6),
+ FUNCTION(blsp_uart3_b),
+ FUNCTION(blsp_uim3_b),
+ FUNCTION(blsp_i2c6),
+ FUNCTION(bt_reset),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_uart3_a),
+ FUNCTION(blsp_uim3_a),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_spi9),
+ FUNCTION(blsp_uart9_a),
+ FUNCTION(blsp_uim9_a),
+ FUNCTION(blsp10_spi_b),
+ FUNCTION(qdss_cti0_a),
+ FUNCTION(blsp_i2c9),
+ FUNCTION(blsp10_spi_a),
+ FUNCTION(blsp_spi7),
+ FUNCTION(blsp_uart7_a),
+ FUNCTION(blsp_uim7_a),
+ FUNCTION(blsp_i2c7),
+ FUNCTION(qua_mi2s),
+ FUNCTION(blsp10_spi),
+ FUNCTION(gcc_gp1_a),
+ FUNCTION(ssc_irq),
+ FUNCTION(blsp_spi11),
+ FUNCTION(blsp_uart8_b),
+ FUNCTION(blsp_uim8_b),
+ FUNCTION(gcc_gp2_a),
+ FUNCTION(qdss_cti1_a),
+ FUNCTION(gcc_gp3_a),
+ FUNCTION(blsp_i2c11),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(cri_trng),
+ FUNCTION(pri_mi2s),
+ FUNCTION(sp_cmu),
+ FUNCTION(blsp_spi10),
+ FUNCTION(blsp_uart7_b),
+ FUNCTION(blsp_uim7_b),
+ FUNCTION(pri_mi2s_ws),
+ FUNCTION(blsp_i2c10),
+ FUNCTION(spkr_i2s),
+ FUNCTION(audio_ref),
+ FUNCTION(blsp9_spi),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(btfm_slimbus),
+ FUNCTION(phase_flag0),
+ FUNCTION(ter_mi2s),
+ FUNCTION(phase_flag7),
+ FUNCTION(phase_flag8),
+ FUNCTION(phase_flag9),
+ FUNCTION(phase_flag4),
+ FUNCTION(gcc_gp1_b),
+ FUNCTION(sec_mi2s),
+ FUNCTION(blsp_spi12),
+ FUNCTION(blsp_uart9_b),
+ FUNCTION(blsp_uim9_b),
+ FUNCTION(gcc_gp2_b),
+ FUNCTION(gcc_gp3_b),
+ FUNCTION(blsp_i2c12),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_uart2_b),
+ FUNCTION(blsp_uim2_b),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(tsif1_clk),
+ FUNCTION(phase_flag10),
+ FUNCTION(tsif1_en),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(blsp1_spi),
+ FUNCTION(tgu_ch0),
+ FUNCTION(qdss_cti1_b),
+ FUNCTION(tsif1_data),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(tgu_ch1),
+ FUNCTION(phase_flag1),
+ FUNCTION(tsif2_error),
+ FUNCTION(sdc43),
+ FUNCTION(vfr_1),
+ FUNCTION(phase_flag2),
+ FUNCTION(tsif2_clk),
+ FUNCTION(sdc4_clk),
+ FUNCTION(tsif2_en),
+ FUNCTION(sdc42),
+ FUNCTION(sd_card),
+ FUNCTION(tsif2_data),
+ FUNCTION(sdc41),
+ FUNCTION(tsif2_sync),
+ FUNCTION(sdc40),
+ FUNCTION(phase_flag3),
+ FUNCTION(mdp_vsync_b),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(blsp_uart8),
+ FUNCTION(blsp11_i2c),
+ FUNCTION(prng_rosc),
+ FUNCTION(phase_flag5),
+ FUNCTION(uim2_data),
+ FUNCTION(uim2_clk),
+ FUNCTION(uim2_reset),
+ FUNCTION(uim2_present),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_reset),
+ FUNCTION(uim1_present),
+ FUNCTION(uim_batt),
+ FUNCTION(phase_flag16),
+ FUNCTION(nav_dr),
+ FUNCTION(phase_flag11),
+ FUNCTION(phase_flag12),
+ FUNCTION(phase_flag13),
+ FUNCTION(atest_char),
+ FUNCTION(adsp_ext),
+ FUNCTION(phase_flag17),
+ FUNCTION(atest_char3),
+ FUNCTION(phase_flag18),
+ FUNCTION(atest_char2),
+ FUNCTION(phase_flag19),
+ FUNCTION(atest_char1),
+ FUNCTION(phase_flag20),
+ FUNCTION(atest_char0),
+ FUNCTION(phase_flag21),
+ FUNCTION(phase_flag22),
+ FUNCTION(phase_flag23),
+ FUNCTION(phase_flag24),
+ FUNCTION(phase_flag25),
+ FUNCTION(modem_tsync),
+ FUNCTION(nav_pps),
+ FUNCTION(phase_flag26),
+ FUNCTION(phase_flag27),
+ FUNCTION(qlink_request),
+ FUNCTION(phase_flag28),
+ FUNCTION(qlink_enable),
+ FUNCTION(phase_flag6),
+ FUNCTION(phase_flag29),
+ FUNCTION(phase_flag30),
+ FUNCTION(phase_flag31),
+ FUNCTION(pa_indicator),
+ FUNCTION(ssbi1),
+ FUNCTION(isense_dbg),
+ FUNCTION(mss_lte),
+};
+
+static const struct msm_pingroup msm8998_groups[] = {
+ PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA,
+ qdss_cti0_b, NA, NA, NA, NA),
+ PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA,
+ qdss_cti0_b, NA, NA, NA, NA),
+ PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, NA,
+ atest_tsens2, atest_usb1, NA, NA),
+ PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, NA, ddr_bist,
+ NA, wlan1_adc1, atest_usb13, bimc_dte1),
+ PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync,
+ ddr_bist, NA, wlan1_adc0, atest_usb12, bimc_dte0),
+ PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4,
+ ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
+ PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b,
+ blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
+ PINGROUP(12, EAST, mdp_vsync, m_voc, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss_gpio0, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(14, EAST, cam_mclk, pll_reset, qdss_gpio1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(15, EAST, cam_mclk, qdss_gpio2, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, EAST, cam_mclk, qdss_gpio3, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, EAST, cci_i2c, qdss_gpio4, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, EAST, cci_i2c, phase_flag14, qdss_gpio5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(19, EAST, cci_i2c, phase_flag15, qdss_gpio6, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(20, EAST, cci_i2c, qdss_gpio7, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, EAST, cci_timer0, NA, qdss_gpio8, vsense_data0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(22, EAST, cci_timer1, NA, qdss_gpio, vsense_data1, NA, NA, NA,
+ NA, NA),
+ PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss_gpio9, vsense_mode,
+ NA, NA, NA, NA, NA),
+ PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, NA, qdss_gpio10,
+ vsense_clkout, NA, NA, NA),
+ PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, NA, qdss_gpio11,
+ NA, NA, NA, NA),
+ PINGROUP(26, EAST, cci_async, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, EAST, blsp1_spi_a, qdss_gpio13, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(28, EAST, blsp1_spi_b, qdss_gpio14, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(29, EAST, blsp2_spi, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss_gpio, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a,
+ pwr_modem, NA, NA, NA, NA),
+ PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2,
+ pwr_nav, NA, NA, NA, NA),
+ PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2,
+ pwr_crypto, NA, NA, NA, NA),
+ PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a,
+ blsp_uim2_a, NA, NA, NA, NA),
+ PINGROUP(35, NORTH, pci_e0, jitter_bist, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NORTH, pci_e0, agera_pll, NA, atest_tsens, NA, NA, NA, NA,
+ NA),
+ PINGROUP(37, NORTH, agera_pll, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, WEST, usb_phy, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, WEST, lpass_slimbus, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, EAST, sd_write, tsif1_error, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA,
+ qdss_gpio6, NA, NA, NA, NA),
+ PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA,
+ qdss_gpio7, NA, NA, NA, NA),
+ PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio14,
+ NA, NA, NA, NA),
+ PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio15,
+ NA, NA, NA, NA),
+ PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b,
+ qdss_cti0_a, NA, NA, NA, NA),
+ PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b,
+ qdss_cti0_a, NA, NA, NA, NA),
+ PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a,
+ NA, NA, NA, NA, NA),
+ PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a,
+ NA, NA, NA, NA, NA),
+ PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b,
+ gcc_gp2_a, NA, qdss_cti1_a, NA, NA),
+ PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b,
+ gcc_gp3_a, NA, qdss_cti1_a, NA, NA),
+ PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11,
+ cri_trng0, NA, NA, NA, NA),
+ PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11,
+ cri_trng1, NA, NA, NA, NA),
+ PINGROUP(62, WEST, qua_mi2s, cri_trng, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, WEST, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, WEST, pri_mi2s, sp_cmu, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, NA,
+ NA, NA, NA, NA),
+ PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b,
+ NA, NA, NA, NA, NA),
+ PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA,
+ NA, NA, NA, NA),
+ PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA,
+ NA, NA, NA, NA),
+ PINGROUP(69, WEST, spkr_i2s, audio_ref, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1,
+ tsense_pwm2, NA, NA, NA, NA),
+ PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(73, WEST, btfm_slimbus, phase_flag0, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(75, WEST, ter_mi2s, phase_flag8, qdss_gpio8, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(76, WEST, ter_mi2s, phase_flag9, qdss_gpio9, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(77, WEST, ter_mi2s, phase_flag4, qdss_gpio10, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, WEST, sec_mi2s, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, WEST, sec_mi2s, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b,
+ gcc_gp2_b, NA, NA, NA, NA),
+ PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b,
+ gcc_gp3_b, NA, NA, NA, NA),
+ PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA,
+ NA, NA, NA, NA),
+ PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(89, EAST, tsif1_clk, phase_flag10, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, NA),
+ PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag1,
+ qdss_cti1_b, NA, NA, NA, NA),
+ PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag2, NA, NA, NA,
+ NA, NA),
+ PINGROUP(93, EAST, tsif2_clk, sdc4_clk, NA, qdss_gpio13, NA, NA, NA,
+ NA, NA),
+ PINGROUP(94, EAST, tsif2_en, sdc42, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, EAST, tsif2_data, sdc41, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag3, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(97, WEST, NA, mdp_vsync_b, ldo_en, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, WEST, NA, mdp_vsync_b, ldo_update, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(99, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(100, WEST, NA, NA, blsp_uart8, NA, NA, NA, NA, NA, NA),
+ PINGROUP(101, WEST, NA, blsp_uart8, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(102, WEST, NA, blsp11_i2c, prng_rosc, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(103, WEST, NA, blsp11_i2c, phase_flag5, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(104, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(105, NORTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(106, NORTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(107, NORTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(108, NORTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(109, NORTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(110, NORTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(111, NORTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(112, NORTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(113, NORTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(114, WEST, NA, NA, phase_flag16, NA, NA, NA, NA, NA, NA),
+ PINGROUP(115, WEST, NA, nav_dr, phase_flag11, NA, NA, NA, NA, NA, NA),
+ PINGROUP(116, WEST, phase_flag12, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(117, EAST, phase_flag13, qdss_gpio0, atest_char, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(118, EAST, adsp_ext, phase_flag17, qdss_gpio1, atest_char3,
+ NA, NA, NA, NA, NA),
+ PINGROUP(119, EAST, phase_flag18, qdss_gpio2, atest_char2, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(120, EAST, phase_flag19, qdss_gpio3, atest_char1, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(121, EAST, phase_flag20, qdss_gpio4, atest_char0, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(122, EAST, phase_flag21, qdss_gpio5, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(123, EAST, phase_flag22, qdss_gpio, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(124, EAST, phase_flag23, qdss_gpio, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(125, EAST, phase_flag24, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(126, EAST, phase_flag25, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(127, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag26, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(129, WEST, phase_flag27, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(130, NORTH, qlink_request, phase_flag28, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(131, NORTH, qlink_enable, phase_flag6, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(132, WEST, NA, phase_flag29, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(133, WEST, phase_flag30, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(134, WEST, phase_flag31, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(135, WEST, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(136, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(137, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(138, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(139, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(140, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(141, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(142, WEST, NA, ssbi1, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(143, WEST, isense_dbg, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(144, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(145, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(146, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(147, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(148, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(149, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
+ SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
+ SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
+ UFS_RESET(ufs_reset, 0x19d000),
+};
+
+static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
+ .pins = msm8998_pins,
+ .npins = ARRAY_SIZE(msm8998_pins),
+ .functions = msm8998_functions,
+ .nfunctions = ARRAY_SIZE(msm8998_functions),
+ .groups = msm8998_groups,
+ .ngroups = ARRAY_SIZE(msm8998_groups),
+ .ngpios = 153,
+};
+
+static int msm8998_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
+}
+
+static const struct of_device_id msm8998_pinctrl_of_match[] = {
+ { .compatible = "qcom,msm8998-pinctrl", },
+ { },
+};
+
+static struct platform_driver msm8998_pinctrl_driver = {
+ .driver = {
+ .name = "msm8998-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = msm8998_pinctrl_of_match,
+ },
+ .probe = msm8998_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init msm8998_pinctrl_init(void)
+{
+ return platform_driver_register(&msm8998_pinctrl_driver);
+}
+arch_initcall(msm8998_pinctrl_init);
+
+static void __exit msm8998_pinctrl_exit(void)
+{
+ platform_driver_unregister(&msm8998_pinctrl_driver);
+}
+module_exit(msm8998_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH v10 8/8] dt-bindings: mmc: Add Cavium SOCs MMC bindings
From: Jan Glauber @ 2017-01-09 15:05 UTC (permalink / raw)
To: Rob Herring
Cc: Ulf Hansson, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, David Daney, Steven J . Hill,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161222203242.nxnmqyldtvdxkqhc@rob-hp-laptop>
On Thu, Dec 22, 2016 at 02:32:42PM -0600, Rob Herring wrote:
> On Mon, Dec 19, 2016 at 01:15:52PM +0100, Jan Glauber wrote:
> > Add description of Cavium Octeon and ThunderX SOC device tree bindings.
> >
> > CC: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> > CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >
> > Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> > ---
> > .../devicetree/bindings/mmc/octeon-mmc.txt | 59 ++++++++++++++++++++++
>
> Perhaps cavium-mmc.txt would be more appropriate now.
Yes, forgot to rename it.
> > 1 file changed, 59 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/octeon-mmc.txt b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> > new file mode 100644
> > index 0000000..aad02eb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> > @@ -0,0 +1,59 @@
> > +* Cavium Octeon & ThunderX MMC controller
> > +
> > +The highspeed MMC host controller on Caviums SoCs provides an interface
> > +for MMC and SD types of memory cards.
> > +
> > +Supported maximum speeds are the ones of the eMMC standard 4.41 as well
> > +as the speed of SD standard 4.0. Only 3.3 Volt is supported.
> > +
> > +Required properties:
> > + - compatible : should be one of:
> > + * "cavium,octeon-6130-mmc"
> > + * "cavium,octeon-6130-mmc-slot"
> > + * "cavium,octeon-7890-mmc"
> > + * "cavium,octeon-7890-mmc-slot"
> > + * "cavium,thunder-8190-mmc"
> > + * "cavium,thunder-8190-mmc-slot"
> > + * "cavium,thunder-8390-mmc"
> > + * "cavium,thunder-8390-mmc-slot"
> > + - reg : mmc controller base registers
>
> Following PCI addressing?
Yes for the host controller, for the child nodes we use reg as the
physical slot number. Maybe I should describe the child node properties
separately?
> > + - clocks : phandle
> > +
> > +Optional properties:
> > + - for cd, bus-width and additional generic mmc parameters
> > + please refer to mmc.txt within this directory
> > + - "cavium,cmd-clk-skew" : number of coprocessor clocks before sampling command
> > + - "cavium,dat-clk-skew" : number of coprocessor clocks before sampling data
> > +
> > +Deprecated properties:
> > +- spi-max-frequency : use max-frequency instead
> > +- "cavium,bus-max-width" : use bus-width instead
>
> Drop the quotes.
OK, droped them also above.
> > +
> > +Examples:
> > + - Within .dtsi:
>
> Don't show the division between files in the example.
OK.
> > + mmc_1_4: mmc@1,4 {
> > + compatible = "cavium,thunder-8390-mmc";
> > + reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clocks = <&sclk>;
> > + };
> > +
> > + - Within dts:
> > + mmc-slot@0 {
>
> Need to show this is a child node.
OK.
> > + compatible = "cavium,thunder-8390-mmc-slot";
> > + reg = <0>;
> > + voltage-ranges = <3300 3300>;
> > + max-frequency = <42000000>;
> > + bus-width = <4>;
> > + cap-sd-highspeed;
> > + };
> > + mmc-slot@1 {
> > + compatible = "cavium,thunder-8390-mmc-slot";
> > + reg = <1>;
> > + voltage-ranges = <3300 3300>;
> > + max-frequency = <42000000>;
> > + bus-width = <8>;
> > + cap-mmc-highspeed;
> > + non-removable;
> > + };
> > --
> > 2.9.0.rc0.21.g7777322
> >
--
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^ permalink raw reply
* [PATCH 1/1] ARM: dts: add Armadeus Systems OPOS6UL AND OPOS6ULDEV support
From: Sébastien Szymanski @ 2017-01-09 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, devicetree, Russell King, linux-kernel, Rob Herring,
Sascha Hauer, Fabio Estevam, Julien Boibessot, Shawn Guo
OPOS6UL is an i.MX6UL based SoM.
OPOS6ULDev is a carrier board for the OPOS6UL SoM.
For more details see:
http://www.opossom.com/english/products-processor_boards-opos6ul.html
http://www.opossom.com/english/products-development_boards-opos6ul_dev.html
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 192 +++++++++++++++
arch/arm/boot/dts/imx6ul-opos6uldev.dts | 414 ++++++++++++++++++++++++++++++++
3 files changed, 607 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-opos6ul.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-opos6uldev.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7327250..f839c75 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -435,6 +435,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
imx6ul-liteboard.dtb \
+ imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
new file mode 100644
index 0000000..4673dde
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Armadeus Systems <support@armadeus.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul.dtsi"
+
+/ {
+ memory {
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ phy-supply = <®_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
+/* Bluetooth */
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
+ /* RST# */
+ MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
+ /* BT_REG_ON */
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
+ MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
+ MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
+ MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
+ /* WL_REG_ON */
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
+ /* WL_IRQ */
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
new file mode 100644
index 0000000..a373562
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
@@ -0,0 +1,414 @@
+/*
+ * Copyright 2016 Armadeus Systems <support@armadeus.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6ul-opos6ul.dtsi"
+
+/ {
+ model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
+ compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ lcd_backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_5v>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user-button {
+ label = "User button";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led {
+ label = "User";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_w1>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbotg1_vbus: regulator-usbotg1vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg1vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg2_vbus: regulator-usbotg2vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg2vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&adc1 {
+ vref-supply = <®_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ };
+
+ spidev1: spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock_frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock_frequency = <400000>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ display = <&display0>;
+ lcd-supply = <®_3v3>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <18>;
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <33000033>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <96>;
+ hfront-porch = <96>;
+ vback-porch = <20>;
+ vfront-porch = <21>;
+ hsync-len = <64>;
+ vsync-len = <4>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ vbus-supply = <®_usbotg1_vbus>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbotg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpios>;
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
+ MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
+ MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
+ MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
+ MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
+ MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
+ >;
+ };
+
+ pinctrl_w1: w1grp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1_id: usbotg1_idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: usbotg1_vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg2_vbus: usbotg2_vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
--
2.7.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related
* Re: [PATCH 1/4] ARM: dts: exynos: Fix indentation of EHCI and OHCI ports
From: Javier Martinez Canillas @ 2017-01-09 16:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, Anand Moon, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Peter Chen, ulf.hansson, Markus Reichl, linux-pm, gregkh,
linux-usb, sre, robh+dt, hverkuil, broonie, stern,
Sylwester Nawrocki, Marek Szyprowski
In-Reply-To: <20170107085203.4431-2-krzk@kernel.org>
Hello Krzysztof,
On 01/07/2017 05:52 AM, Krzysztof Kozlowski wrote:
> Replace spaces with tabs in EHCI and OHCI ports indentation.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH 00/11] dmaengine: cppi41: Add dma support to da8xx
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
This series adds support of da8xx to cppi41 dma controller driver.
This update the cppi41 driver to make it more generic (was only supporting
the am335x), and implement the support for the da8xx.
Some other changes are required in platform and musb drivers to make the dma
work on da8xx (though, it should build correctly and should not cause
any issues).
The changes have been tested on the beaglebone black and omapl138-lcd.
I haven't noticed any regression on beaglebone black
(though I have noticed some performence issues since 4.9).
On on da8xx, I have sometime some warnings happening during a teardown.
I only got them while I was running some corner cases and I'm still trying
to fix them.
Anyway, this warnings doesn't seem to cause any issues as usb keep working
after they happen.
I also got some issues related to pm runtime.
I tried to fix them with the series "dmaengine: cppi41: PM runtime fixes",
but I still get few warnings sometime (again, doesn't seem to cause any issue).
Alexandre Bailon (11):
dmaengine: cppi41: rename platform variables
dmaengine: cppi41: Split out the interrupt handler
dmaengine: cppi41: Move some constants to glue layer
dmaengine: cppi41: init_sched(): Get number of channels from DT
dmaengine: cppi41: Add a way to test if the driver is running on
am335x
dmaengine: cppi41: Only configure am335x's registers on amm335x
platform
dt/bindings: da8xx-usb: Add binding for the cppi41 dma controller
dmaengine: cppi41: Implement the glue for da8xx
dmaengine: cppi41: Fix a race between PM runtime and channel abort
dmaengine: cppi41: Fix da8xx interrupt issue
dmaengine: cppi41: Fix teardown warnings
.../devicetree/bindings/usb/da8xx-usb.txt | 39 ++++
drivers/dma/cppi41.c | 252 +++++++++++++++++----
2 files changed, 247 insertions(+), 44 deletions(-)
--
2.10.2
--
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^ permalink raw reply
* [PATCH 01/11] dmaengine: cppi41: rename platform variables
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Currently, only the am335x is supported by the driver.
Though the driver has a glue layer to support different platforms,
some platform variable names are not prefixed with the platform name.
To facilitate the addition of a new platform,
rename some variables owned by the am335x glue.
Currently, only the am335x is supported by the driver.
Though the driver provide a glue layer that should be used to support
another platforms. Rename variable specifics to the am335x glue.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index d5ba43a..25ee71d 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -156,7 +156,7 @@ struct cppi41_dd {
};
#define FIST_COMPLETION_QUEUE 93
-static struct chan_queues usb_queues_tx[] = {
+static struct chan_queues am335x_usb_queues_tx[] = {
/* USB0 ENDP 1 */
[ 0] = { .submit = 32, .complete = 93},
[ 1] = { .submit = 34, .complete = 94},
@@ -192,7 +192,7 @@ static struct chan_queues usb_queues_tx[] = {
[29] = { .submit = 90, .complete = 139},
};
-static const struct chan_queues usb_queues_rx[] = {
+static const struct chan_queues am335x_usb_queues_rx[] = {
/* USB0 ENDP 1 */
[ 0] = { .submit = 1, .complete = 109},
[ 1] = { .submit = 2, .complete = 110},
@@ -918,8 +918,9 @@ static bool cpp41_dma_filter_fn(struct dma_chan *chan, void *param)
else
queues = cdd->queues_rx;
- BUILD_BUG_ON(ARRAY_SIZE(usb_queues_rx) != ARRAY_SIZE(usb_queues_tx));
- if (WARN_ON(cchan->port_num > ARRAY_SIZE(usb_queues_rx)))
+ BUILD_BUG_ON(ARRAY_SIZE(am335x_usb_queues_rx) !=
+ ARRAY_SIZE(am335x_usb_queues_tx));
+ if (WARN_ON(cchan->port_num > ARRAY_SIZE(am335x_usb_queues_rx)))
return false;
cchan->q_num = queues[cchan->port_num].submit;
@@ -947,15 +948,15 @@ static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
&dma_spec->args[0]);
}
-static const struct cppi_glue_infos usb_infos = {
+static const struct cppi_glue_infos am335x_usb_infos = {
.isr = cppi41_irq,
- .queues_rx = usb_queues_rx,
- .queues_tx = usb_queues_tx,
+ .queues_rx = am335x_usb_queues_rx,
+ .queues_tx = am335x_usb_queues_tx,
.td_queue = { .submit = 31, .complete = 0 },
};
static const struct of_device_id cppi41_dma_ids[] = {
- { .compatible = "ti,am3359-cppi41", .data = &usb_infos},
+ { .compatible = "ti,am3359-cppi41", .data = &am335x_usb_infos},
{},
};
MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 02/11] dmaengine: cppi41: Split out the interrupt handler
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
The current interrupt handler do some actions specifics to am335x.
These actions should be made by the platform interrupt handler.
Split out the interrupt handler in two:
one for the am335x platform and a generic one.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 24 +++++++++++++++---------
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 25ee71d..42744ed 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -284,18 +284,11 @@ static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
return desc;
}
-static irqreturn_t cppi41_irq(int irq, void *data)
+static irqreturn_t cppi41_irq(struct cppi41_dd *cdd)
{
- struct cppi41_dd *cdd = data;
struct cppi41_channel *c;
- u32 status;
int i;
- status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
- if (!(status & USBSS_IRQ_PD_COMP))
- return IRQ_NONE;
- cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
-
for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
i++) {
u32 val;
@@ -351,6 +344,19 @@ static irqreturn_t cppi41_irq(int irq, void *data)
return IRQ_HANDLED;
}
+static irqreturn_t am335x_cppi41_irq(int irq, void *data)
+{
+ struct cppi41_dd *cdd = data;
+ u32 status;
+
+ status = cppi_readl(cdd->usbss_mem + USBSS_IRQ_STATUS);
+ if (!(status & USBSS_IRQ_PD_COMP))
+ return IRQ_NONE;
+ cppi_writel(status, cdd->usbss_mem + USBSS_IRQ_STATUS);
+
+ return cppi41_irq(cdd);
+}
+
static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
{
dma_cookie_t cookie;
@@ -949,7 +955,7 @@ static struct dma_chan *cppi41_dma_xlate(struct of_phandle_args *dma_spec,
}
static const struct cppi_glue_infos am335x_usb_infos = {
- .isr = cppi41_irq,
+ .isr = am335x_cppi41_irq,
.queues_rx = am335x_usb_queues_rx,
.queues_tx = am335x_usb_queues_tx,
.td_queue = { .submit = 31, .complete = 0 },
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 03/11] dmaengine: cppi41: Move some constants to glue layer
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Some constants are defined and use by the driver whereas they are
specifics to am335x.
Add new variables to the glue layer, initialize them with the constants,
and use them in the driver.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 20 ++++++++++++++------
1 file changed, 14 insertions(+), 6 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 42744ed..d0d3bdd 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -68,7 +68,6 @@
#define QMGR_MEMCTRL_IDX_SH 16
#define QMGR_MEMCTRL_DESC_SH 8
-#define QMGR_NUM_PEND 5
#define QMGR_PEND(x) (0x90 + (x) * 4)
#define QMGR_PENDING_SLOT_Q(x) (x / 32)
@@ -147,6 +146,8 @@ struct cppi41_dd {
const struct chan_queues *queues_rx;
const struct chan_queues *queues_tx;
struct chan_queues td_queue;
+ u16 first_completion_queue;
+ u16 qmgr_num_pend;
struct list_head pending; /* Pending queued transfers */
spinlock_t lock; /* Lock for pending list */
@@ -155,7 +156,6 @@ struct cppi41_dd {
unsigned int dma_tdfdq;
};
-#define FIST_COMPLETION_QUEUE 93
static struct chan_queues am335x_usb_queues_tx[] = {
/* USB0 ENDP 1 */
[ 0] = { .submit = 32, .complete = 93},
@@ -233,6 +233,8 @@ struct cppi_glue_infos {
const struct chan_queues *queues_rx;
const struct chan_queues *queues_tx;
struct chan_queues td_queue;
+ u16 first_completion_queue;
+ u16 qmgr_num_pend;
};
static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
@@ -286,19 +288,21 @@ static u32 cppi41_pop_desc(struct cppi41_dd *cdd, unsigned queue_num)
static irqreturn_t cppi41_irq(struct cppi41_dd *cdd)
{
+ u16 first_completion_queue = cdd->first_completion_queue;
+ u16 qmgr_num_pend = cdd->qmgr_num_pend;
struct cppi41_channel *c;
int i;
- for (i = QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE); i < QMGR_NUM_PEND;
+ for (i = QMGR_PENDING_SLOT_Q(first_completion_queue); i < qmgr_num_pend;
i++) {
u32 val;
u32 q_num;
val = cppi_readl(cdd->qmgr_mem + QMGR_PEND(i));
- if (i == QMGR_PENDING_SLOT_Q(FIST_COMPLETION_QUEUE) && val) {
+ if (i == QMGR_PENDING_SLOT_Q(first_completion_queue) && val) {
u32 mask;
/* set corresponding bit for completetion Q 93 */
- mask = 1 << QMGR_PENDING_BIT_Q(FIST_COMPLETION_QUEUE);
+ mask = 1 << QMGR_PENDING_BIT_Q(first_completion_queue);
/* not set all bits for queues less than Q 93 */
mask--;
/* now invert and keep only Q 93+ set */
@@ -876,7 +880,7 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
return -ENOMEM;
cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
- cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
+ cppi_writel(TOTAL_DESCS_NUM, cdd->qmgr_mem + QMGR_LRAM_SIZE);
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
ret = init_descs(dev, cdd);
@@ -959,6 +963,8 @@ static const struct cppi_glue_infos am335x_usb_infos = {
.queues_rx = am335x_usb_queues_rx,
.queues_tx = am335x_usb_queues_tx,
.td_queue = { .submit = 31, .complete = 0 },
+ .first_completion_queue = 93,
+ .qmgr_num_pend = 5,
};
static const struct of_device_id cppi41_dma_ids[] = {
@@ -1036,6 +1042,8 @@ static int cppi41_dma_probe(struct platform_device *pdev)
cdd->queues_rx = glue_info->queues_rx;
cdd->queues_tx = glue_info->queues_tx;
cdd->td_queue = glue_info->td_queue;
+ cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
+ cdd->first_completion_queue = glue_info->first_completion_queue;
ret = init_cppi41(dev, cdd);
if (ret)
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 04/11] dmaengine: cppi41: init_sched(): Get number of channels from DT
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Despite the driver is already using DT to get the number of channels,
init_sched() is using an hardcoded value to get it.
Use DT to get the number of channels.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 33 ++++++++++++++++++++-------------
1 file changed, 20 insertions(+), 13 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index d0d3bdd..8d7965d 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -148,6 +148,8 @@ struct cppi41_dd {
struct chan_queues td_queue;
u16 first_completion_queue;
u16 qmgr_num_pend;
+ u32 n_chans;
+ u8 platform;
struct list_head pending; /* Pending queued transfers */
spinlock_t lock; /* Lock for pending list */
@@ -734,13 +736,8 @@ static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
{
struct cppi41_channel *cchan;
int i;
- int ret;
- u32 n_chans;
+ u32 n_chans = cdd->n_chans;
- ret = of_property_read_u32(dev->of_node, "#dma-channels",
- &n_chans);
- if (ret)
- return ret;
/*
* The channels can only be used as TX or as RX. So we add twice
* that much dma channels because USB can only do RX or TX.
@@ -846,7 +843,7 @@ static int init_descs(struct device *dev, struct cppi41_dd *cdd)
return 0;
}
-static void init_sched(struct cppi41_dd *cdd)
+static int init_sched(struct device *dev, struct cppi41_dd *cdd)
{
unsigned ch;
unsigned word;
@@ -854,7 +851,7 @@ static void init_sched(struct cppi41_dd *cdd)
word = 0;
cppi_writel(0, cdd->sched_mem + DMA_SCHED_CTRL);
- for (ch = 0; ch < 15 * 2; ch += 2) {
+ for (ch = 0; ch < cdd->n_chans; ch += 2) {
reg = SCHED_ENTRY0_CHAN(ch);
reg |= SCHED_ENTRY1_CHAN(ch) | SCHED_ENTRY1_IS_RX;
@@ -864,9 +861,11 @@ static void init_sched(struct cppi41_dd *cdd)
cppi_writel(reg, cdd->sched_mem + DMA_SCHED_WORD(word));
word++;
}
- reg = 15 * 2 * 2 - 1;
+ reg = cdd->n_chans * 2 - 1;
reg |= DMA_SCHED_CTRL_EN;
cppi_writel(reg, cdd->sched_mem + DMA_SCHED_CTRL);
+
+ return 0;
}
static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
@@ -885,12 +884,14 @@ static int init_cppi41(struct device *dev, struct cppi41_dd *cdd)
ret = init_descs(dev, cdd);
if (ret)
- goto err_td;
+ goto deinit;
cppi_writel(cdd->td_queue.submit, cdd->ctrl_mem + DMA_TDFDQ);
- init_sched(cdd);
+ ret = init_sched(dev, cdd);
+ if (ret)
+ goto deinit;
return 0;
-err_td:
+deinit:
deinit_cppi41(dev, cdd);
return ret;
}
@@ -1045,6 +1046,11 @@ static int cppi41_dma_probe(struct platform_device *pdev)
cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
cdd->first_completion_queue = glue_info->first_completion_queue;
+ ret = of_property_read_u32(dev->of_node,
+ "#dma-channels", &cdd->n_chans);
+ if (ret)
+ goto err_get_n_chans;
+
ret = init_cppi41(dev, cdd);
if (ret)
goto err_init_cppi;
@@ -1090,6 +1096,7 @@ static int cppi41_dma_probe(struct platform_device *pdev)
deinit_cppi41(dev, cdd);
err_init_cppi:
pm_runtime_dont_use_autosuspend(dev);
+err_get_n_chans:
err_get_sync:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
@@ -1150,7 +1157,7 @@ static int __maybe_unused cppi41_resume(struct device *dev)
if (!c->is_tx)
cppi_writel(c->q_num, c->gcr_reg + RXHPCRA0);
- init_sched(cdd);
+ init_sched(dev, cdd);
cppi_writel(cdd->dma_tdfdq, cdd->ctrl_mem + DMA_TDFDQ);
cppi_writel(cdd->scratch_phys, cdd->qmgr_mem + QMGR_LRAM0_BASE);
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 05/11] dmaengine: cppi41: Add a way to test if the driver is running on am335x
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
As the cppi41 is present in different platform, the driver needs
to determine on which platform it is running to execute instructions
specific to this platform (such as configure IRQ on am335x).
Add a way to test if we are running on am335x.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 8d7965d..58b27ef 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -89,6 +89,8 @@
/* Packet Descriptor */
#define PD2_ZERO_LENGTH (1 << 19)
+#define AM335X_CPPI41 0
+
struct cppi41_channel {
struct dma_chan chan;
struct dma_async_tx_descriptor txd;
@@ -237,6 +239,7 @@ struct cppi_glue_infos {
struct chan_queues td_queue;
u16 first_completion_queue;
u16 qmgr_num_pend;
+ u8 platform;
};
static struct cppi41_channel *to_cpp41_chan(struct dma_chan *c)
@@ -966,6 +969,7 @@ static const struct cppi_glue_infos am335x_usb_infos = {
.td_queue = { .submit = 31, .complete = 0 },
.first_completion_queue = 93,
.qmgr_num_pend = 5,
+ .platform = AM335X_CPPI41,
};
static const struct of_device_id cppi41_dma_ids[] = {
@@ -984,6 +988,13 @@ static const struct cppi_glue_infos *get_glue_info(struct device *dev)
return of_id->data;
}
+static int is_am335x_cppi41(struct device *dev)
+{
+ struct cppi41_dd *cdd = dev_get_drvdata(dev);
+
+ return cdd->platform == AM335X_CPPI41;
+}
+
#define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
@@ -1045,6 +1056,7 @@ static int cppi41_dma_probe(struct platform_device *pdev)
cdd->td_queue = glue_info->td_queue;
cdd->qmgr_num_pend = glue_info->qmgr_num_pend;
cdd->first_completion_queue = glue_info->first_completion_queue;
+ cdd->platform = glue_info->platform;
ret = of_property_read_u32(dev->of_node,
"#dma-channels", &cdd->n_chans);
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 06/11] dmaengine: cppi41: Only configure am335x's registers on amm335x platform
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Currently, the driver configure some am335x's usb registers.
Test if the driver is running on am335x before to configure
these registers.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 58b27ef..939398e 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -1077,7 +1077,9 @@ static int cppi41_dma_probe(struct platform_device *pdev)
goto err_irq;
}
- cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
+ if (is_am335x_cppi41(dev))
+ cppi_writel(USBSS_IRQ_PD_COMP,
+ cdd->usbss_mem + USBSS_IRQ_ENABLER);
ret = devm_request_irq(&pdev->dev, irq, glue_info->isr, IRQF_SHARED,
dev_name(dev), cdd);
@@ -1102,7 +1104,8 @@ static int cppi41_dma_probe(struct platform_device *pdev)
dma_async_device_unregister(&cdd->ddev);
err_dma_reg:
err_irq:
- cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
+ if (is_am335x_cppi41(dev))
+ cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
cleanup_chans(cdd);
err_chans:
deinit_cppi41(dev, cdd);
@@ -1131,7 +1134,8 @@ static int cppi41_dma_remove(struct platform_device *pdev)
of_dma_controller_free(pdev->dev.of_node);
dma_async_device_unregister(&cdd->ddev);
- cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
+ if (is_am335x_cppi41(&pdev->dev))
+ cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
devm_free_irq(&pdev->dev, cdd->irq, cdd);
cleanup_chans(cdd);
deinit_cppi41(&pdev->dev, cdd);
@@ -1150,7 +1154,8 @@ static int __maybe_unused cppi41_suspend(struct device *dev)
struct cppi41_dd *cdd = dev_get_drvdata(dev);
cdd->dma_tdfdq = cppi_readl(cdd->ctrl_mem + DMA_TDFDQ);
- cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
+ if (is_am335x_cppi41(dev))
+ cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
disable_sched(cdd);
return 0;
@@ -1176,7 +1181,9 @@ static int __maybe_unused cppi41_resume(struct device *dev)
cppi_writel(QMGR_SCRATCH_SIZE, cdd->qmgr_mem + QMGR_LRAM_SIZE);
cppi_writel(0, cdd->qmgr_mem + QMGR_LRAM1_BASE);
- cppi_writel(USBSS_IRQ_PD_COMP, cdd->usbss_mem + USBSS_IRQ_ENABLER);
+ if (is_am335x_cppi41(dev))
+ cppi_writel(USBSS_IRQ_PD_COMP,
+ cdd->usbss_mem + USBSS_IRQ_ENABLER);
return 0;
}
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 07/11] dt/bindings: da8xx-usb: Add binding for the cppi41 dma controller
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
DT binding for the TI DA8xx/OMAP-L1x/AM17xx/AM18xx cppi41 dma controller.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
.../devicetree/bindings/usb/da8xx-usb.txt | 39 ++++++++++++++++++++++
1 file changed, 39 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/da8xx-usb.txt b/Documentation/devicetree/bindings/usb/da8xx-usb.txt
index ccb844a..2a4d737 100644
--- a/Documentation/devicetree/bindings/usb/da8xx-usb.txt
+++ b/Documentation/devicetree/bindings/usb/da8xx-usb.txt
@@ -18,10 +18,26 @@ Required properties:
- phy-names: Should be "usb-phy"
+ - dmas: specifies the dma channels
+
+ - dma-names: specifies the names of the channels. Use "rxN" for receive
+ and "txN" for transmit endpoints. N specifies the endpoint number.
+
Optional properties:
~~~~~~~~~~~~~~~~~~~~
- vbus-supply: Phandle to a regulator providing the USB bus power.
+DMA
+~~~
+- compatible: ti,da8xx-cppi41
+- reg: offset and length of the following register spaces: USBSS, USB
+ CPPI DMA Controller, USB CPPI DMA Scheduler, USB Queue Manager
+- reg-names: glue, controller, scheduler, queuemgr
+- #dma-cells: should be set to 2. The first number represents the
+ endpoint number (0 … 3 for endpoints 1 … 4).
+ The second number is 0 for RX and 1 for TX transfers.
+- #dma-channels: should be set to 4 representing the 4 endpoints.
+
Example:
usb_phy: usb-phy {
compatible = "ti,da830-usb-phy";
@@ -39,5 +55,28 @@ Example:
phys = <&usb_phy 0>;
phy-names = "usb-phy";
+ dmas = <&cppi41dma 0 0 &cppi41dma 1 0
+ &cppi41dma 2 0 &cppi41dma 3 0
+ &cppi41dma 0 1 &cppi41dma 1 1
+ &cppi41dma 2 1 &cppi41dma 3 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4",
+ "tx1", "tx2", "tx3", "tx4";
+
status = "okay";
};
+ cppi41dma: dma-controller@201000 {
+ compatible = "ti,da8xx-cppi41";
+ reg = <0x200000 0x1000
+ 0x201000 0x1000
+ 0x202000 0x1000
+ 0x204000 0x4000>;
+ reg-names = "glue", "controller", "scheduler", "queuemgr";
+ interrupts = <58>;
+ interrupt-names = "glue";
+ #dma-cells = <2>;
+ #dma-channels = <4>;
+ #dma-requests = <256>;
+ status = "disabled";
+
+ };
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 08/11] dmaengine: cppi41: Implement the glue for da8xx
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
The da8xx has a cppi41 dma controller.
This is add the glue layer required to make it work on da8xx,
as well some changes in driver (e.g to manage clock).
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 95 ++++++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 939398e..4318e53 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -1,3 +1,4 @@
+#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/dmaengine.h>
#include <linux/dma-mapping.h>
@@ -86,10 +87,19 @@
#define USBSS_IRQ_PD_COMP (1 << 2)
+/* USB DA8XX */
+#define DA8XX_INTR_SRC_MASKED 0x38
+#define DA8XX_END_OF_INTR 0x3c
+
+#define DA8XX_QMGR_PENDING_MASK (0xf << 24)
+
+
+
/* Packet Descriptor */
#define PD2_ZERO_LENGTH (1 << 19)
#define AM335X_CPPI41 0
+#define DA8XX_CPPI41 1
struct cppi41_channel {
struct dma_chan chan;
@@ -158,6 +168,9 @@ struct cppi41_dd {
/* context for suspend/resume */
unsigned int dma_tdfdq;
+
+ /* da8xx clock */
+ struct clk *clk;
};
static struct chan_queues am335x_usb_queues_tx[] = {
@@ -232,6 +245,20 @@ static const struct chan_queues am335x_usb_queues_rx[] = {
[29] = { .submit = 30, .complete = 155},
};
+static const struct chan_queues da8xx_usb_queues_tx[] = {
+ [0] = { .submit = 16, .complete = 24},
+ [1] = { .submit = 18, .complete = 24},
+ [2] = { .submit = 20, .complete = 24},
+ [3] = { .submit = 22, .complete = 24},
+};
+
+static const struct chan_queues da8xx_usb_queues_rx[] = {
+ [0] = { .submit = 1, .complete = 26},
+ [1] = { .submit = 3, .complete = 26},
+ [2] = { .submit = 5, .complete = 26},
+ [3] = { .submit = 7, .complete = 26},
+};
+
struct cppi_glue_infos {
irqreturn_t (*isr)(int irq, void *data);
const struct chan_queues *queues_rx;
@@ -366,6 +393,26 @@ static irqreturn_t am335x_cppi41_irq(int irq, void *data)
return cppi41_irq(cdd);
}
+static irqreturn_t da8xx_cppi41_irq(int irq, void *data)
+{
+ struct cppi41_dd *cdd = data;
+ u32 status;
+ u32 usbss_status;
+
+ status = cppi_readl(cdd->qmgr_mem + QMGR_PEND(0));
+ if (status & DA8XX_QMGR_PENDING_MASK)
+ cppi41_irq(cdd);
+ else
+ return IRQ_NONE;
+
+ /* Re-assert IRQ if there no usb core interrupts pending */
+ usbss_status = cppi_readl(cdd->usbss_mem + DA8XX_INTR_SRC_MASKED);
+ if (!usbss_status)
+ cppi_writel(0, cdd->usbss_mem + DA8XX_END_OF_INTR);
+
+ return IRQ_HANDLED;
+}
+
static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
{
dma_cookie_t cookie;
@@ -972,8 +1019,19 @@ static const struct cppi_glue_infos am335x_usb_infos = {
.platform = AM335X_CPPI41,
};
+static const struct cppi_glue_infos da8xx_usb_infos = {
+ .isr = da8xx_cppi41_irq,
+ .queues_rx = da8xx_usb_queues_rx,
+ .queues_tx = da8xx_usb_queues_tx,
+ .td_queue = { .submit = 31, .complete = 0 },
+ .first_completion_queue = 24,
+ .qmgr_num_pend = 2,
+ .platform = DA8XX_CPPI41,
+};
+
static const struct of_device_id cppi41_dma_ids[] = {
{ .compatible = "ti,am3359-cppi41", .data = &am335x_usb_infos},
+ { .compatible = "ti,da8xx-cppi41", .data = &da8xx_usb_infos},
{},
};
MODULE_DEVICE_TABLE(of, cppi41_dma_ids);
@@ -995,6 +1053,13 @@ static int is_am335x_cppi41(struct device *dev)
return cdd->platform == AM335X_CPPI41;
}
+static int is_da8xx_cppi41(struct device *dev)
+{
+ struct cppi41_dd *cdd = dev_get_drvdata(dev);
+
+ return cdd->platform == DA8XX_CPPI41;
+}
+
#define CPPI41_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
@@ -1058,6 +1123,21 @@ static int cppi41_dma_probe(struct platform_device *pdev)
cdd->first_completion_queue = glue_info->first_completion_queue;
cdd->platform = glue_info->platform;
+ if (is_da8xx_cppi41(dev)) {
+ cdd->clk = devm_clk_get(&pdev->dev, "usb20");
+ ret = PTR_ERR_OR_ZERO(cdd->clk);
+ if (ret) {
+ dev_err(&pdev->dev, "failed to get clock\n");
+ goto err_clk_en;
+ }
+
+ ret = clk_prepare_enable(cdd->clk);
+ if (ret) {
+ dev_err(dev, "failed to enable clock\n");
+ goto err_clk_en;
+ }
+ }
+
ret = of_property_read_u32(dev->of_node,
"#dma-channels", &cdd->n_chans);
if (ret)
@@ -1112,6 +1192,9 @@ static int cppi41_dma_probe(struct platform_device *pdev)
err_init_cppi:
pm_runtime_dont_use_autosuspend(dev);
err_get_n_chans:
+ if (is_da8xx_cppi41(dev))
+ clk_disable_unprepare(cdd->clk);
+err_clk_en:
err_get_sync:
pm_runtime_put_sync(dev);
pm_runtime_disable(dev);
@@ -1146,6 +1229,8 @@ static int cppi41_dma_remove(struct platform_device *pdev)
pm_runtime_dont_use_autosuspend(&pdev->dev);
pm_runtime_put_sync(&pdev->dev);
pm_runtime_disable(&pdev->dev);
+ if (is_da8xx_cppi41(&pdev->dev))
+ clk_disable_unprepare(cdd->clk);
return 0;
}
@@ -1158,6 +1243,9 @@ static int __maybe_unused cppi41_suspend(struct device *dev)
cppi_writel(0, cdd->usbss_mem + USBSS_IRQ_CLEARR);
disable_sched(cdd);
+ if (is_da8xx_cppi41(dev))
+ clk_disable_unprepare(cdd->clk);
+
return 0;
}
@@ -1165,8 +1253,15 @@ static int __maybe_unused cppi41_resume(struct device *dev)
{
struct cppi41_dd *cdd = dev_get_drvdata(dev);
struct cppi41_channel *c;
+ int ret;
int i;
+ if (is_da8xx_cppi41(dev)) {
+ ret = clk_prepare_enable(cdd->clk);
+ if (ret)
+ return ret;
+ }
+
for (i = 0; i < DESCS_AREAS; i++)
cppi_writel(cdd->descs_phys, cdd->qmgr_mem + QMGR_MEMBASE(i));
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 09/11] dmaengine: cppi41: Fix a race between PM runtime and channel abort
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
cppi41_dma_issue_pending() may be called while the device is runtime
suspended. In that case, the descritpor will be push to the pending
list and then be queued to hardware queue.
But if cppi41_stop_chan() is called before the device got time to
resume, then the descriptor will remain in the pending list and be
queued to hardware queue after the teardown.
During the channel stop, check if there is a pendding descriptor
and if so, remove it.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 4318e53..e8470b1 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -751,10 +751,17 @@ static int cppi41_stop_chan(struct dma_chan *chan)
{
struct cppi41_channel *c = to_cpp41_chan(chan);
struct cppi41_dd *cdd = c->cdd;
+ unsigned long flags;
u32 desc_num;
u32 desc_phys;
int ret;
+ /* Remove pending descriptor that haven't been pushed to queue */
+ spin_lock_irqsave(&cdd->lock, flags);
+ if (!list_empty(&c->node))
+ list_del_init(&c->node);
+ spin_unlock_irqrestore(&cdd->lock, flags);
+
desc_phys = lower_32_bits(c->desc_phys);
desc_num = (desc_phys - cdd->descs_phys) / sizeof(struct cppi41_desc);
if (!cdd->chan_busy[desc_num])
@@ -812,6 +819,7 @@ static int cppi41_add_chans(struct device *dev, struct cppi41_dd *cdd)
cchan->desc_phys = cdd->descs_phys;
cchan->desc_phys += i * sizeof(struct cppi41_desc);
cchan->chan.device = &cdd->ddev;
+ INIT_LIST_HEAD(&cchan->node);
list_add_tail(&cchan->chan.device_node, &cdd->ddev.channels);
}
cdd->first_td_desc = n_chans;
@@ -1301,7 +1309,7 @@ static int __maybe_unused cppi41_runtime_resume(struct device *dev)
spin_lock_irqsave(&cdd->lock, flags);
list_for_each_entry_safe(c, _c, &cdd->pending, node) {
push_desc_queue(c);
- list_del(&c->node);
+ list_del_init(&c->node);
}
spin_unlock_irqrestore(&cdd->lock, flags);
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 10/11] dmaengine: cppi41: Fix da8xx interrupt issue
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
Sometime, after a teardown, interrupts are not fired anymore.
This happen because the interrupt handler doesn't re-assert IRQ.
Once the teardown complete, the teardown descriptor is moved
to completion queue, which is causing an interrupt.
But cppi41_tear_down_chan() is called from atomic section,
and it polls the queue until it got the teardown descriptor.
Then, the interrupt handler is called but it is not able
detect the cause of the interrupt and assume the interrupt
has been fired by USB core. In that situation, the IRQ won't
be re-asserted and interrupts won't work anymore.
Add the td_complete variable to detect an interrupt fired by
DMA during a teardown, and then re-assert IRQ.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index e8470b1..0060391 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -171,6 +171,8 @@ struct cppi41_dd {
/* da8xx clock */
struct clk *clk;
+
+ bool td_complete;
};
static struct chan_queues am335x_usb_queues_tx[] = {
@@ -398,19 +400,29 @@ static irqreturn_t da8xx_cppi41_irq(int irq, void *data)
struct cppi41_dd *cdd = data;
u32 status;
u32 usbss_status;
+ irqreturn_t ret = IRQ_NONE;
status = cppi_readl(cdd->qmgr_mem + QMGR_PEND(0));
if (status & DA8XX_QMGR_PENDING_MASK)
- cppi41_irq(cdd);
- else
- return IRQ_NONE;
+ ret = cppi41_irq(cdd);
+
+ if (cdd->td_complete) {
+ /*
+ * Spurious IRQ caused by teardown.
+ * DMA interrupts are not maskable, so there is now way
+ * to prevent it.
+ * Just ensure that the IRQ will be re-asserted.
+ */
+ cdd->td_complete = false;
+ ret = IRQ_HANDLED;
+ }
/* Re-assert IRQ if there no usb core interrupts pending */
usbss_status = cppi_readl(cdd->usbss_mem + DA8XX_INTR_SRC_MASKED);
- if (!usbss_status)
+ if (ret == IRQ_HANDLED && !usbss_status)
cppi_writel(0, cdd->usbss_mem + DA8XX_END_OF_INTR);
- return IRQ_HANDLED;
+ return ret;
}
static dma_cookie_t cppi41_tx_submit(struct dma_async_tx_descriptor *tx)
@@ -740,6 +752,14 @@ static int cppi41_tear_down_chan(struct cppi41_channel *c)
WARN_ON(!desc_phys);
}
+ /* On DA8xx, we are using the PEND0 register to determine if
+ * the interrupt is generated by DMA. But because the teardown has
+ * already been popped from completion queue, PEND0 is clear and
+ * the interrupt handler will assume the interrupt has been fired
+ * by the USB core.
+ */
+ cdd->td_complete = true;
+
c->td_queued = 0;
c->td_seen = 0;
c->td_desc_seen = 0;
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 11/11] dmaengine: cppi41: Fix teardown warnings
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
In-Reply-To: <20170109160656.3470-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
During the teardown of a RX channel, because there is only one
completion queue available for RX channel, descriptor of another
channel may be popped which will cause 2 warnings:
- the first one because we popped a wrong descriptor
(neither the channel's descriptor, neither the teardown descriptor).
- the second one happen during the teardown of another channel,
because we can't find the channel descriptor
(that is, the one that caused the first warning).
Use the teardown queue as completion queue during the teardown.
Note that fix doesn't fix all the teardown warnings:
I still get some when I run some corner case.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
drivers/dma/cppi41.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/dma/cppi41.c b/drivers/dma/cppi41.c
index 0060391..eeab29d 100644
--- a/drivers/dma/cppi41.c
+++ b/drivers/dma/cppi41.c
@@ -698,7 +698,7 @@ static int cppi41_tear_down_chan(struct cppi41_channel *c)
if (!c->is_tx) {
reg |= GCR_STARV_RETRY;
reg |= GCR_DESC_TYPE_HOST;
- reg |= c->q_comp_num;
+ reg |= cdd->td_queue.complete;
}
reg |= GCR_TEARDOWN;
cppi_writel(reg, c->gcr_reg);
@@ -709,7 +709,7 @@ static int cppi41_tear_down_chan(struct cppi41_channel *c)
if (!c->td_seen || !c->td_desc_seen) {
desc_phys = cppi41_pop_desc(cdd, cdd->td_queue.complete);
- if (!desc_phys)
+ if (!desc_phys && c->is_tx)
desc_phys = cppi41_pop_desc(cdd, c->q_comp_num);
if (desc_phys == c->desc_phys) {
--
2.10.2
--
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^ permalink raw reply related
* [PATCH] ARM: davinci: da850: Share the usb20 clock
From: Alexandre Bailon @ 2017-01-09 16:13 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, khilman-rdvid1DuHRBWk0Htik3J/w,
ptitiano-rdvid1DuHRBWk0Htik3J/w, tony-4v6yS6AI5VpBDgjK7y7TUQ,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
On da850, the cppi41 dma controller and usb core are the usb20 clock.
Currently, this clock can only be used by the da8xx musb glue driver.
Update the usb20 clock to be requested by more than one user.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/mach-davinci/da850.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 1d873d1..57e8049 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -567,7 +567,7 @@ static struct clk_lookup da850_clks[] = {
*/
CLK(NULL, "aemif", &aemif_nand_clk),
CLK("ohci-da8xx", "usb11", &usb11_clk),
- CLK("musb-da8xx", "usb20", &usb20_clk),
+ CLK(NULL, "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("vpif", NULL, &vpif_clk),
--
2.10.2
--
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^ permalink raw reply related
* [PATCH] ARM: davinci: da850: Share the usb20 clock
From: Alexandre Bailon @ 2017-01-09 16:13 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, khilman-rdvid1DuHRBWk0Htik3J/w,
ptitiano-rdvid1DuHRBWk0Htik3J/w, tony-4v6yS6AI5VpBDgjK7y7TUQ,
linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
In-Reply-To: <20170109161336.3759-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
On da850, the cppi41 dma controller and usb core are the usb20 clock.
Currently, this clock can only be used by the da8xx musb glue driver.
Update the usb20 clock to be requested by more than one user.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/mach-davinci/da850.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c
index 1d873d1..57e8049 100644
--- a/arch/arm/mach-davinci/da850.c
+++ b/arch/arm/mach-davinci/da850.c
@@ -567,7 +567,7 @@ static struct clk_lookup da850_clks[] = {
*/
CLK(NULL, "aemif", &aemif_nand_clk),
CLK("ohci-da8xx", "usb11", &usb11_clk),
- CLK("musb-da8xx", "usb20", &usb20_clk),
+ CLK(NULL, "usb20", &usb20_clk),
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("vpif", NULL, &vpif_clk),
--
2.10.2
--
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^ permalink raw reply related
* Re: [PATCH 2/4] ARM: dts: exynos: Fix LAN9730 on Odroid U3 after tftpboot
From: Javier Martinez Canillas @ 2017-01-09 16:17 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, Anand Moon, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Marek Szyprowski, Sylwester Nawrocki, Peter Chen, gregkh, stern,
ulf.hansson, broonie, sre, robh+dt, linux-usb, linux-pm, hverkuil,
Markus Reichl
In-Reply-To: <20170107085203.4431-3-krzk@kernel.org>
Hello Krzysztof,
On 01/07/2017 05:52 AM, Krzysztof Kozlowski wrote:
> The ethernet adapter LAN9730, after enabling in bootloader (e.g. for
> tftpboot) requires reset during boot. Otherwise it won't come up.
>
> The schematics of Odroid U3 are detailed enough but after grabbing
> knowledge also from other sources (like U-Boot) the overall design looks
> like:
> 1. LAN9730 is connected to HSIC0 and USB3503 to HSIC1 of EHCI controller.
> 2. USB3503 comes with its own reset pin: gpx3-5.
> 3. Reset pin of LAN9730 is pulled up to 3.3 V so it cannot be used.
> 4. The supply of 3.3 V for LAN9730 is delivered from buck8.
> 5. Buck8 state is a logical OR of registry value (through I2C command)
> and ENB8 pin. The ENB8, not described in schematics, is in fact
> gpa1-1.
> 6. Missing or wrongly timed reset of LAN9730 might result in missing of
> two devices: LAN9730 and USB3503. Without reset, LAN9730 will not
> come up, if it was enabled by bootloader.
>
> To fix the issue use the generic power sequence driver and toggle the
> ENB8 (buck8) pin. Reset duration of 500 us was chosen by experiments
> (shortest working time was 400 us). This is an easiest way to fix the
> long standing LAN9730 reset issue.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Thanks for keep pushing a fix for this long standing issue.
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* Re: [PATCH 3/4] ARM: exynos_defconfig: Enable power sequence for Odroid U3
From: Javier Martinez Canillas @ 2017-01-09 16:19 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, Anand Moon, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Peter Chen, ulf.hansson, Markus Reichl, linux-pm, gregkh,
linux-usb, sre, robh+dt, hverkuil, broonie, stern,
Sylwester Nawrocki, Marek Szyprowski
In-Reply-To: <20170107085203.4431-4-krzk@kernel.org>
Hello Krzysztof,
On 01/07/2017 05:52 AM, Krzysztof Kozlowski wrote:
> Odroid U3 needs a power sequence for lan9730, if it was enabled by
> bootloader. Enable also GPIO_SYSFS which is useful for playing with
> GPIO during debug process.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* Re: [PATCH v1.1] ARM: multi_v7_defconfig: Enable power sequence for Odroid U3
From: Javier Martinez Canillas @ 2017-01-09 16:24 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, Anand Moon, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Peter Chen, ulf.hansson, Markus Reichl, linux-pm, gregkh,
linux-usb, sre, robh+dt, hverkuil, broonie, stern,
Sylwester Nawrocki, Marek Szyprowski
In-Reply-To: <20170107091651.10560-1-krzk@kernel.org>
Hello Krzysztof,
I think it would had been clearer if the subject prefix was "[PATCH v1.1 4/4]" :)
On 01/07/2017 06:16 AM, Krzysztof Kozlowski wrote:
> Odroid U3 needs a power sequence for lan9730, if it was enabled by
> bootloader. Also enable the USB3503 HSCI to USB2.0 driver (device
> is present on Odroid U3).
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
>
> ---
>
Do you think that makes sense to also enable GPIO_SYS for debugging
purposes as you do in patch 3/4?
In any case the patch looks good to me:
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH 0/3] ARM: dts: da850: Enable cppi41 dma
From: Alexandre Bailon @ 2017-01-09 16:24 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
This series enable support of cppi41 for da850.
The bindings and DT support are added in the series
"dmaengine: cppi41: Add dma support to da8xx".
Alexandre Bailon (3):
ARM: dts: da850: Add the cppi41 dma node
ARM: dts: da850: Add the cppi41 dma to the usb otg controller
ARM: dts: da850: Enable cppi41 dma for da850-lcdk
arch/arm/boot/dts/da850-lcdk.dts | 4 ++++
arch/arm/boot/dts/da850.dtsi | 24 ++++++++++++++++++++++++
2 files changed, 28 insertions(+)
--
2.10.2
--
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^ permalink raw reply
* [PATCH 1/3] ARM: dts: da850: Add the cppi41 dma node
From: Alexandre Bailon @ 2017-01-09 16:24 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
In-Reply-To: <20170109162449.5012-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
This adds the device tree node for the cppi41 dma
used by the usb otg controller present in the da850 family of SoC's.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/da850.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 104155d..d6b406a 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -403,6 +403,22 @@
phy-names = "usb-phy";
status = "disabled";
};
+ cppi41dma: dma-controller@201000 {
+ compatible = "ti,da8xx-cppi41";
+ reg = <0x200000 0x1000
+ 0x201000 0x1000
+ 0x202000 0x1000
+ 0x204000 0x4000>;
+ reg-names = "glue", "controller",
+ "scheduler", "queuemgr";
+ interrupts = <58>;
+ interrupt-names = "glue";
+ #dma-cells = <2>;
+ #dma-channels = <4>;
+ #dma-requests = <256>;
+ status = "disabled";
+
+ };
mdio: mdio@224000 {
compatible = "ti,davinci_mdio";
#address-cells = <1>;
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 2/3] ARM: dts: da850: Add the cppi41 dma to the usb otg controller
From: Alexandre Bailon @ 2017-01-09 16:24 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
In-Reply-To: <20170109162449.5012-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
This adds the cppi41 dma controller to the usb otg controller.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/da850.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index d6b406a..0ed0cb9 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -402,6 +402,14 @@
phys = <&usb_phy 0>;
phy-names = "usb-phy";
status = "disabled";
+
+ dmas = <&cppi41dma 0 0 &cppi41dma 1 0
+ &cppi41dma 2 0 &cppi41dma 3 0
+ &cppi41dma 0 1 &cppi41dma 1 1
+ &cppi41dma 2 1 &cppi41dma 3 1>;
+ dma-names =
+ "rx1", "rx2", "rx3", "rx4",
+ "tx1", "tx2", "tx3", "tx4";
};
cppi41dma: dma-controller@201000 {
compatible = "ti,da8xx-cppi41";
--
2.10.2
--
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^ permalink raw reply related
* [PATCH 3/3] ARM: dts: da850: Enable cppi41 dma for da850-lcdk
From: Alexandre Bailon @ 2017-01-09 16:24 UTC (permalink / raw)
To: nsekhar-l0cyMroinI0, khilman-rdvid1DuHRBWk0Htik3J/w
Cc: vinod.koul-ral2JQCrhuEAvxtiuMwx3w,
dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, david-nq/r/kbU++upp/zk7JDF2g, Alexandre Bailon
In-Reply-To: <20170109162449.5012-1-abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
This enable the cppi41 dma controller used by the usb otg for
the da850-lcdk board.
Signed-off-by: Alexandre Bailon <abailon-rdvid1DuHRBWk0Htik3J/w@public.gmane.org>
---
arch/arm/boot/dts/da850-lcdk.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/da850-lcdk.dts b/arch/arm/boot/dts/da850-lcdk.dts
index afcb482..abb9b9d 100644
--- a/arch/arm/boot/dts/da850-lcdk.dts
+++ b/arch/arm/boot/dts/da850-lcdk.dts
@@ -167,6 +167,10 @@
status = "okay";
};
+&cppi41dma {
+ status = "okay";
+};
+
&aemif {
pinctrl-names = "default";
pinctrl-0 = <&nand_pins>;
--
2.10.2
--
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