* [PATCH 00/11] dmaengine: cppi41: Add dma support to da8xx
From: Alexandre Bailon @ 2017-01-09 16:06 UTC (permalink / raw)
To: vinod.koul-ral2JQCrhuEAvxtiuMwx3w
Cc: dmaengine-u79uwXL29TY76Z2rM5mHXA,
linux-usb-u79uwXL29TY76Z2rM5mHXA, nsekhar-l0cyMroinI0,
khilman-rdvid1DuHRBWk0Htik3J/w, ptitiano-rdvid1DuHRBWk0Htik3J/w,
tony-4v6yS6AI5VpBDgjK7y7TUQ, linux-omap-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, robh+dt-DgEjT+Ai2ygdnm+yROfE0A,
b-liu-l0cyMroinI0, Alexandre Bailon
This series adds support of da8xx to cppi41 dma controller driver.
This update the cppi41 driver to make it more generic (was only supporting
the am335x), and implement the support for the da8xx.
Some other changes are required in platform and musb drivers to make the dma
work on da8xx (though, it should build correctly and should not cause
any issues).
The changes have been tested on the beaglebone black and omapl138-lcd.
I haven't noticed any regression on beaglebone black
(though I have noticed some performence issues since 4.9).
On on da8xx, I have sometime some warnings happening during a teardown.
I only got them while I was running some corner cases and I'm still trying
to fix them.
Anyway, this warnings doesn't seem to cause any issues as usb keep working
after they happen.
I also got some issues related to pm runtime.
I tried to fix them with the series "dmaengine: cppi41: PM runtime fixes",
but I still get few warnings sometime (again, doesn't seem to cause any issue).
Alexandre Bailon (11):
dmaengine: cppi41: rename platform variables
dmaengine: cppi41: Split out the interrupt handler
dmaengine: cppi41: Move some constants to glue layer
dmaengine: cppi41: init_sched(): Get number of channels from DT
dmaengine: cppi41: Add a way to test if the driver is running on
am335x
dmaengine: cppi41: Only configure am335x's registers on amm335x
platform
dt/bindings: da8xx-usb: Add binding for the cppi41 dma controller
dmaengine: cppi41: Implement the glue for da8xx
dmaengine: cppi41: Fix a race between PM runtime and channel abort
dmaengine: cppi41: Fix da8xx interrupt issue
dmaengine: cppi41: Fix teardown warnings
.../devicetree/bindings/usb/da8xx-usb.txt | 39 ++++
drivers/dma/cppi41.c | 252 +++++++++++++++++----
2 files changed, 247 insertions(+), 44 deletions(-)
--
2.10.2
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^ permalink raw reply
* Re: [PATCH 1/4] ARM: dts: exynos: Fix indentation of EHCI and OHCI ports
From: Javier Martinez Canillas @ 2017-01-09 16:01 UTC (permalink / raw)
To: Krzysztof Kozlowski, Kukjin Kim, Anand Moon, devicetree,
linux-arm-kernel, linux-samsung-soc, linux-kernel
Cc: Peter Chen, ulf.hansson, Markus Reichl, linux-pm, gregkh,
linux-usb, sre, robh+dt, hverkuil, broonie, stern,
Sylwester Nawrocki, Marek Szyprowski
In-Reply-To: <20170107085203.4431-2-krzk@kernel.org>
Hello Krzysztof,
On 01/07/2017 05:52 AM, Krzysztof Kozlowski wrote:
> Replace spaces with tabs in EHCI and OHCI ports indentation.
>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Best regards,
--
Javier Martinez Canillas
Open Source Group
Samsung Research America
^ permalink raw reply
* [PATCH 1/1] ARM: dts: add Armadeus Systems OPOS6UL AND OPOS6ULDEV support
From: Sébastien Szymanski @ 2017-01-09 16:00 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Mark Rutland, devicetree, Russell King, linux-kernel, Rob Herring,
Sascha Hauer, Fabio Estevam, Julien Boibessot, Shawn Guo
OPOS6UL is an i.MX6UL based SoM.
OPOS6ULDev is a carrier board for the OPOS6UL SoM.
For more details see:
http://www.opossom.com/english/products-processor_boards-opos6ul.html
http://www.opossom.com/english/products-development_boards-opos6ul_dev.html
Signed-off-by: Sébastien Szymanski <sebastien.szymanski@armadeus.com>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/imx6ul-opos6ul.dtsi | 192 +++++++++++++++
arch/arm/boot/dts/imx6ul-opos6uldev.dts | 414 ++++++++++++++++++++++++++++++++
3 files changed, 607 insertions(+)
create mode 100644 arch/arm/boot/dts/imx6ul-opos6ul.dtsi
create mode 100644 arch/arm/boot/dts/imx6ul-opos6uldev.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7327250..f839c75 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -435,6 +435,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-14x14-evk.dtb \
imx6ul-geam-kit.dtb \
imx6ul-liteboard.dtb \
+ imx6ul-opos6uldev.dtb \
imx6ul-pico-hobbit.dtb \
imx6ul-tx6ul-0010.dtb \
imx6ul-tx6ul-0011.dtb \
diff --git a/arch/arm/boot/dts/imx6ul-opos6ul.dtsi b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
new file mode 100644
index 0000000..4673dde
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-opos6ul.dtsi
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2016 Armadeus Systems <support@armadeus.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "imx6ul.dtsi"
+
+/ {
+ memory {
+ reg = <0x80000000 0>; /* will be filled by U-Boot */
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ usdhc3_pwrseq: usdhc3_pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
+ };
+};
+
+&fec1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enet1>;
+ phy-mode = "rmii";
+ phy-reset-duration = <1>;
+ phy-reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>;
+ phy-handle = <ðphy1>;
+ phy-supply = <®_3v3>;
+ status = "okay";
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ interrupt-parent = <&gpio4>;
+ interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+ };
+ };
+};
+
+/* Bluetooth */
+&uart8 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart8>;
+ fsl,uart-has-rtscts;
+ status = "okay";
+};
+
+/* eMMC */
+&usdhc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ bus-width = <8>;
+ no-1-8-v;
+ non-removable;
+ status = "okay";
+};
+
+/* WiFi */
+&usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+ bus-width = <4>;
+ no-1-8-v;
+ non-removable;
+ mmc-pwrseq = <&usdhc3_pwrseq>;
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ brcmf: bcrmf@1 {
+ compatible = "brcm,bcm4329-fmac";
+ reg = <1>;
+ interrupt-parent = <&gpio2>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "host-wake";
+ };
+};
+
+&iomuxc {
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0
+ MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0
+ MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x130b0
+ MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x130b0
+ MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x130b0
+ MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
+ MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
+ MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
+ /* INT# */
+ MX6UL_PAD_NAND_DQS__GPIO4_IO16 0x1b0b0
+ /* RST# */
+ MX6UL_PAD_NAND_DATA00__GPIO4_IO02 0x130b0
+ MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
+ >;
+ };
+
+ pinctrl_uart8: uart8grp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_EN__UART8_DCE_RX 0x1b0b0
+ MX6UL_PAD_ENET2_TX_DATA1__UART8_DCE_TX 0x1b0b0
+ MX6UL_PAD_ENET2_RX_ER__UART8_DCE_RTS 0x1b0b0
+ MX6UL_PAD_ENET2_TX_CLK__UART8_DCE_CTS 0x1b0b0
+ /* BT_REG_ON */
+ MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x130b0
+ >;
+ };
+
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
+ MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
+ MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
+ MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
+ MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
+ MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
+ MX6UL_PAD_NAND_READY_B__USDHC1_DATA4 0x17059
+ MX6UL_PAD_NAND_CE0_B__USDHC1_DATA5 0x17059
+ MX6UL_PAD_NAND_CE1_B__USDHC1_DATA6 0x17059
+ MX6UL_PAD_NAND_CLE__USDHC1_DATA7 0x17059
+ >;
+ };
+
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_DATA18__USDHC2_CMD 0x1b0b0
+ MX6UL_PAD_LCD_DATA19__USDHC2_CLK 0x100b0
+ MX6UL_PAD_LCD_DATA20__USDHC2_DATA0 0x1b0b0
+ MX6UL_PAD_LCD_DATA21__USDHC2_DATA1 0x1b0b0
+ MX6UL_PAD_LCD_DATA22__USDHC2_DATA2 0x1b0b0
+ MX6UL_PAD_LCD_DATA23__USDHC2_DATA3 0x1b0b0
+ /* WL_REG_ON */
+ MX6UL_PAD_ENET2_RX_DATA1__GPIO2_IO09 0x130b0
+ /* WL_IRQ */
+ MX6UL_PAD_ENET2_RX_DATA0__GPIO2_IO08 0x1b0b0
+ >;
+ };
+};
diff --git a/arch/arm/boot/dts/imx6ul-opos6uldev.dts b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
new file mode 100644
index 0000000..a373562
--- /dev/null
+++ b/arch/arm/boot/dts/imx6ul-opos6uldev.dts
@@ -0,0 +1,414 @@
+/*
+ * Copyright 2016 Armadeus Systems <support@armadeus.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public
+ * License along with this file; if not, write to the Free
+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "imx6ul-opos6ul.dtsi"
+
+/ {
+ model = "Armadeus Systems OPOS6UL SoM on OPOS6ULDev board";
+ compatible = "armadeus,opos6uldev", "armadeus,opos6ul", "fsl,imx6ul";
+
+ chosen {
+ stdout-path = &uart1;
+ };
+
+ lcd_backlight {
+ compatible = "pwm-backlight";
+ pwms = <&pwm3 0 191000>;
+ brightness-levels = <0 4 8 16 32 64 128 255>;
+ default-brightness-level = <7>;
+ power-supply = <®_5v>;
+ status = "okay";
+ };
+
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_keys>;
+
+ user-button {
+ label = "User button";
+ gpios = <&gpio2 11 GPIO_ACTIVE_LOW>;
+ linux,code = <BTN_MISC>;
+ wakeup-source;
+ };
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ user_led {
+ label = "User";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_led>;
+ gpios = <&gpio3 4 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
+ onewire {
+ compatible = "w1-gpio";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_w1>;
+ gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>;
+ status = "okay";
+ };
+
+ reg_5v: regulator-5v {
+ compatible = "regulator-fixed";
+ regulator-name = "5V";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ reg_usbotg1_vbus: regulator-usbotg1vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg1vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_vbus>;
+ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ reg_usbotg2_vbus: regulator-usbotg2vbus {
+ compatible = "regulator-fixed";
+ regulator-name = "usbotg2vbus";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg2_vbus>;
+ gpio = <&gpio5 9 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+};
+
+&pwm3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_pwm3>;
+ status = "okay";
+};
+
+&adc1 {
+ vref-supply = <®_3v3>;
+ status = "okay";
+};
+
+&can1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan1>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&can2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_flexcan2>;
+ xceiver-supply = <®_5v>;
+ status = "okay";
+};
+
+&ecspi4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ecspi4>;
+ fsl,spi-num-chipselects = <2>;
+ cs-gpios = <&gpio4 9 GPIO_ACTIVE_LOW>, <&gpio4 3 GPIO_ACTIVE_LOW>;
+ status = "okay";
+
+ spidev0: spi@0 {
+ compatible = "spidev";
+ reg = <0>;
+ spi-max-frequency = <5000000>;
+ };
+
+ spidev1: spi@1 {
+ compatible = "spidev";
+ reg = <1>;
+ spi-max-frequency = <5000000>;
+ };
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+ clock_frequency = <400000>;
+ status = "okay";
+};
+
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2>;
+ clock_frequency = <400000>;
+ status = "okay";
+};
+
+&lcdif {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lcdif>;
+ display = <&display0>;
+ lcd-supply = <®_3v3>;
+ status = "okay";
+
+ display0: display0 {
+ bits-per-pixel = <32>;
+ bus-width = <18>;
+
+ display-timings {
+ timing0: timing0 {
+ clock-frequency = <33000033>;
+ hactive = <800>;
+ vactive = <480>;
+ hback-porch = <96>;
+ hfront-porch = <96>;
+ vback-porch = <20>;
+ vfront-porch = <21>;
+ hsync-len = <64>;
+ vsync-len = <4>;
+ de-active = <1>;
+ pixelclk-active = <0>;
+ };
+ };
+ };
+};
+
+&snvs_pwrkey {
+ status = "disabled";
+};
+
+&tsc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_tsc>;
+ xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
+ measure-delay-time = <0xffff>;
+ pre-charge-time = <0xffff>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart1>;
+ status = "okay";
+};
+
+&uart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_uart2>;
+ status = "okay";
+};
+
+&usbotg1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usbotg1_id>;
+ vbus-supply = <®_usbotg1_vbus>;
+ dr_mode = "otg";
+ disable-over-current;
+ status = "okay";
+};
+
+&usbotg2 {
+ vbus-supply = <®_usbotg2_vbus>;
+ dr_mode = "host";
+ disable-over-current;
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpios>;
+
+ pinctrl_pwm3: pwm3grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_ALE__PWM3_OUT 0x1b0b0
+ >;
+ };
+
+ pinctrl_ecspi4: ecspi4grp {
+ fsl,pins = <
+ MX6UL_PAD_NAND_DATA04__ECSPI4_SCLK 0x1b0b0
+ MX6UL_PAD_NAND_DATA05__ECSPI4_MOSI 0x1b0b0
+ MX6UL_PAD_NAND_DATA06__ECSPI4_MISO 0x1b0b0
+ MX6UL_PAD_NAND_DATA01__GPIO4_IO03 0x1b0b0
+ MX6UL_PAD_NAND_DATA07__GPIO4_IO09 0x1b0b0
+ >;
+ };
+
+ pinctrl_flexcan1: flexcan1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x0b0b0
+ MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_flexcan2: flexcan2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x0b0b0
+ MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpios: gpiosgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x0b0b0
+ MX6UL_PAD_UART3_RX_DATA__GPIO1_IO25 0x0b0b0
+ MX6UL_PAD_UART3_TX_DATA__GPIO1_IO24 0x0b0b0
+ MX6UL_PAD_NAND_RE_B__GPIO4_IO00 0x0b0b0
+ MX6UL_PAD_GPIO1_IO08__GPIO1_IO08 0x0b0b0
+ MX6UL_PAD_UART1_CTS_B__GPIO1_IO18 0x0b0b0
+ MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x0b0b0
+ MX6UL_PAD_NAND_WE_B__GPIO4_IO01 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER2__GPIO5_IO02 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER5__GPIO5_IO05 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER6__GPIO5_IO06 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x0b0b0
+ MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x0b0b0
+ >;
+ };
+
+ pinctrl_w1: w1grp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER1__GPIO5_IO01 0x0b0b0
+ >;
+ };
+
+ pinctrl_gpio_keys: gpio_keysgrp {
+ fsl,pins = <
+ MX6UL_PAD_ENET2_TX_DATA0__GPIO2_IO11 0x0b0b0
+ >;
+ };
+
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
+ MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
+ MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
+ >;
+ };
+
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x100b1
+ MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x100b1
+ MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x100b1
+ MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x100b1
+ MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x100b1
+ MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x100b1
+ MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x100b1
+ MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x100b1
+ MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x100b1
+ MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x100b1
+ MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x100b1
+ MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x100b1
+ MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x100b1
+ MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x100b1
+ MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x100b1
+ MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x100b1
+ MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x100b1
+ MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x100b1
+ MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x100b1
+ MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x100b1
+ MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x100b1
+ MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x100b1
+ >;
+ };
+
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6UL_PAD_LCD_RESET__GPIO3_IO04 0x0b0b0
+ >;
+ };
+
+ pinctrl_tsc: tscgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
+ MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
+ MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
+ MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
+ >;
+ };
+
+ pinctrl_uart1: uart1grp {
+ fsl,pins = <
+ MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_uart2: uart2grp {
+ fsl,pins = <
+ MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
+ MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
+ >;
+ };
+
+ pinctrl_usbotg1_id: usbotg1_idgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg1_vbus: usbotg1_vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x1b0b0
+ >;
+ };
+
+ pinctrl_usbotg2_vbus: usbotg2_vbusgrp {
+ fsl,pins = <
+ MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x1b0b0
+ >;
+ };
+};
--
2.7.3
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^ permalink raw reply related
* Re: [PATCH v10 8/8] dt-bindings: mmc: Add Cavium SOCs MMC bindings
From: Jan Glauber @ 2017-01-09 15:05 UTC (permalink / raw)
To: Rob Herring
Cc: Ulf Hansson, linux-mmc-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, David Daney, Steven J . Hill,
Mark Rutland, devicetree-u79uwXL29TY76Z2rM5mHXA
In-Reply-To: <20161222203242.nxnmqyldtvdxkqhc@rob-hp-laptop>
On Thu, Dec 22, 2016 at 02:32:42PM -0600, Rob Herring wrote:
> On Mon, Dec 19, 2016 at 01:15:52PM +0100, Jan Glauber wrote:
> > Add description of Cavium Octeon and ThunderX SOC device tree bindings.
> >
> > CC: Ulf Hansson <ulf.hansson-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
> > CC: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
> > CC: Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>
> > CC: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
> >
> > Signed-off-by: Jan Glauber <jglauber-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org>
> > ---
> > .../devicetree/bindings/mmc/octeon-mmc.txt | 59 ++++++++++++++++++++++
>
> Perhaps cavium-mmc.txt would be more appropriate now.
Yes, forgot to rename it.
> > 1 file changed, 59 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/octeon-mmc.txt b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> > new file mode 100644
> > index 0000000..aad02eb
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mmc/octeon-mmc.txt
> > @@ -0,0 +1,59 @@
> > +* Cavium Octeon & ThunderX MMC controller
> > +
> > +The highspeed MMC host controller on Caviums SoCs provides an interface
> > +for MMC and SD types of memory cards.
> > +
> > +Supported maximum speeds are the ones of the eMMC standard 4.41 as well
> > +as the speed of SD standard 4.0. Only 3.3 Volt is supported.
> > +
> > +Required properties:
> > + - compatible : should be one of:
> > + * "cavium,octeon-6130-mmc"
> > + * "cavium,octeon-6130-mmc-slot"
> > + * "cavium,octeon-7890-mmc"
> > + * "cavium,octeon-7890-mmc-slot"
> > + * "cavium,thunder-8190-mmc"
> > + * "cavium,thunder-8190-mmc-slot"
> > + * "cavium,thunder-8390-mmc"
> > + * "cavium,thunder-8390-mmc-slot"
> > + - reg : mmc controller base registers
>
> Following PCI addressing?
Yes for the host controller, for the child nodes we use reg as the
physical slot number. Maybe I should describe the child node properties
separately?
> > + - clocks : phandle
> > +
> > +Optional properties:
> > + - for cd, bus-width and additional generic mmc parameters
> > + please refer to mmc.txt within this directory
> > + - "cavium,cmd-clk-skew" : number of coprocessor clocks before sampling command
> > + - "cavium,dat-clk-skew" : number of coprocessor clocks before sampling data
> > +
> > +Deprecated properties:
> > +- spi-max-frequency : use max-frequency instead
> > +- "cavium,bus-max-width" : use bus-width instead
>
> Drop the quotes.
OK, droped them also above.
> > +
> > +Examples:
> > + - Within .dtsi:
>
> Don't show the division between files in the example.
OK.
> > + mmc_1_4: mmc@1,4 {
> > + compatible = "cavium,thunder-8390-mmc";
> > + reg = <0x0c00 0 0 0 0>; /* DEVFN = 0x0c (1:4) */
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + clocks = <&sclk>;
> > + };
> > +
> > + - Within dts:
> > + mmc-slot@0 {
>
> Need to show this is a child node.
OK.
> > + compatible = "cavium,thunder-8390-mmc-slot";
> > + reg = <0>;
> > + voltage-ranges = <3300 3300>;
> > + max-frequency = <42000000>;
> > + bus-width = <4>;
> > + cap-sd-highspeed;
> > + };
> > + mmc-slot@1 {
> > + compatible = "cavium,thunder-8390-mmc-slot";
> > + reg = <1>;
> > + voltage-ranges = <3300 3300>;
> > + max-frequency = <42000000>;
> > + bus-width = <8>;
> > + cap-mmc-highspeed;
> > + non-removable;
> > + };
> > --
> > 2.9.0.rc0.21.g7777322
> >
--
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^ permalink raw reply
* [PATCH] pinctrl: qcom: Add msm8998 pinctrl driver
From: Imran Khan @ 2017-01-09 15:00 UTC (permalink / raw)
To: andy.gross
Cc: Imran Khan, Linus Walleij, Rob Herring, Mark Rutland, David Brown,
open list:PIN CONTROL SUBSYSTEM,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list, open list:ARM/QUALCOMM SUPPORT,
open list:ARM/QUALCOMM SUPPORT
Add initial pinctrl driver to support pin configuration with
pinctrl framework for msm8998.
Signed-off-by: Imran Khan <kimran@codeaurora.org>
---
.../bindings/pinctrl/qcom,msm8998-pinctrl.txt | 200 ++
drivers/pinctrl/qcom/Kconfig | 8 +
drivers/pinctrl/qcom/Makefile | 1 +
drivers/pinctrl/qcom/pinctrl-msm8998.c | 1933 ++++++++++++++++++++
4 files changed, 2142 insertions(+)
create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
create mode 100644 drivers/pinctrl/qcom/pinctrl-msm8998.c
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
new file mode 100644
index 0000000..23206b4
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/qcom,msm8998-pinctrl.txt
@@ -0,0 +1,200 @@
+Qualcomm MSM8998 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+MSM8998 platform.
+
+- compatible:
+ Usage: required
+ Value type: <string>
+ Definition: must be "qcom,msm8998-pinctrl"
+
+- reg:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+ Usage: required
+ Value type: <prop-encoded-array>
+ Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+ Usage: required
+ Value type: <none>
+ Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+ Usage: required
+ Value type: <u32>
+ Definition: must be 2. Specifying the pin number and flags, as defined
+ in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+ Usage: required
+ Value type: <string-array>
+ Definition: List of gpio pins affected by the properties specified in
+ this subnode.
+
+ Valid pins are:
+ gpio0-gpio149
+ Supports mux, bias and drive-strength
+
+ sdc2_clk, sdc2_cmd, sdc2_data
+ Supports bias and drive-strength
+
+ ufs_reset
+ Supports bias and drive-strength
+
+- function:
+ Usage: required
+ Value type: <string>
+ Definition: Specify the alternative function to be configured for the
+ specified pins. Functions are only valid for gpio pins.
+ Valid values are:
+
+ blsp_spi1, gpio, blsp_uim1_a, blsp_uart1_a, blsp_i2c1,
+ blsp_spi8, blsp_uart8_a, blsp_uim8_a, qdss_cti0_b,
+ blsp_i2c8, ddr_bist, atest_tsens2, atest_usb1, blsp_spi4,
+ blsp_uart1_b, blsp_uim1_b, wlan1_adc1, atest_usb13,bimc_dte1,
+ tsif1_sync, wlan1_adc0, atest_usb12, bimc_dte0, mdp_vsync_a,
+ blsp_i2c4, atest_gpsadc1, wlan2_adc1, atest_usb11, edp_lcd,
+ dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10, mdp_vsync,
+ m_voc, cam_mclk, pll_bypassnl, qdss_gpio0, pll_reset,
+ qdss_gpio1, qdss_gpio2, qdss_gpio3, cci_i2c, qdss_gpio4,
+ phase_flag14, qdss_gpio5, phase_flag15, qdss_gpio6, qdss_gpio7,
+ cci_timer4, blsp2_spi, qdss_gpio11, qdss_gpio12, qdss_gpio13,
+ qdss_gpio14, qdss_gpio15, cci_timer0, qdss_gpio8, vsense_data0,
+ cci_timer1, qdss_gpio, vsense_data1, cci_timer2, blsp1_spi_b,
+ qdss_gpio9, vsense_mode, cci_timer3, cci_async, blsp1_spi_a,
+ qdss_gpio10, vsense_clkout, hdmi_rcv, hdmi_cec, blsp_spi2,
+ blsp_uart2_a, blsp_uim2_a, pwr_modem, hdmi_ddc, blsp_i2c2,
+ pwr_nav, pwr_crypto, hdmi_hot, edp_hot, pci_e0, jitter_bist,
+ agera_pll, atest_tsens, usb_phy, lpass_slimbus, sd_write,
+ tsif1_error, blsp_spi6, blsp_uart3_b, blsp_uim3_b, blsp_i2c6,
+ bt_reset, blsp_spi3, blsp_uart3_a, blsp_uim3_a, blsp_i2c3,
+ blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b, qdss_cti0_a,
+ blsp_i2c9, blsp10_spi_a, blsp_spi7, blsp_uart7_a, blsp_uim7_a,
+ blsp_i2c7, qua_mi2s, blsp10_spi, gcc_gp1_a, ssc_irq, blsp_spi11,
+ blsp_uart8_b, blsp_uim8_b, gcc_gp2_a, qdss_cti1_a, gcc_gp3_a,
+ blsp_i2c11, cri_trng0, cri_trng1, cri_trng, pri_mi2s, sp_cmu,
+ blsp_spi10, blsp_uart7_b, blsp_uim7_b, pri_mi2s_ws, blsp_i2c10,
+ spkr_i2s, audio_ref, blsp9_spi, tsense_pwm1, tsense_pwm2,
+ btfm_slimbus, phase_flag0, ter_mi2s, phase_flag7, phase_flag8,
+ phase_flag9, phase_flag4, gcc_gp1_b, sec_mi2s, blsp_spi12,
+ blsp_uart9_b, blsp_uim9_b, gcc_gp2_b, gcc_gp3_b, blsp_i2c12,
+ blsp_spi5, blsp_uart2_b, blsp_uim2_b, blsp_i2c5, tsif1_clk,
+ phase_flag10, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, tsif1_data, sdc4_cmd,
+ tgu_ch1, phase_flag1, tsif2_error, sdc43, vfr_1, phase_flag2,
+ tsif2_clk, sdc4_clk, tsif2_en, sdc42, sd_card, tsif2_data, sdc41,
+ tsif2_sync, sdc40, phase_flag3, mdp_vsync_b, ldo_en, ldo_update,
+ blsp_uart8, blsp11_i2c, prng_rosc, phase_flag5, uim2_data, uim2_clk,
+ uim2_reset, uim2_present, uim1_data, uim1_clk, uim1_reset,
+ uim1_present, uim_batt, phase_flag16, nav_dr, phase_flag11, phase_flag12,
+ phase_flag13, atest_char, adsp_ext, phase_flag17, atest_char3, phase_flag18,
+ atest_char2, phase_flag19, atest_char1, phase_flag20, atest_char0,
+ phase_flag21, phase_flag22, phase_flag23, phase_flag24, phase_flag25,
+ modem_tsync, nav_pps, phase_flag26, phase_flag27, qlink_request, phase_flag28,
+ qlink_enable, phase_flag6, phase_flag29, phase_flag30, phase_flag31,
+ pa_indicator, ssbi1, isense_dbg, mss_lte
+
+
+- bias-disable:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins should be configued as pull up.
+
+- output-high:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ high.
+ Not valid for sdc pins.
+
+- output-low:
+ Usage: optional
+ Value type: <none>
+ Definition: The specified pins are configured in output mode, driven
+ low.
+ Not valid for sdc pins.
+
+- drive-strength:
+ Usage: optional
+ Value type: <u32>
+ Definition: Selects the drive strength for the specified pins, in mA.
+ Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+ tlmm: pinctrl@03400000 {
+ compatible = "qcom,msm8998-pinctrl";
+ reg = <0x03400000 0xc00000>;
+ interrupts = <0 208 0>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+
+ uart_console_active: uart_console_active {
+ mux {
+ pins = "gpio4", "gpio5";
+ function = "blsp_uart8_a";
+ };
+
+ config {
+ pins = "gpio4", "gpio5";
+ drive-strength = <2>;
+ bias-disable;
+ };
+ };
+ };
diff --git a/drivers/pinctrl/qcom/Kconfig b/drivers/pinctrl/qcom/Kconfig
index 3ebdc01..f572bc8 100644
--- a/drivers/pinctrl/qcom/Kconfig
+++ b/drivers/pinctrl/qcom/Kconfig
@@ -96,6 +96,14 @@ config PINCTRL_MSM8996
This is the pinctrl, pinmux, pinconf and gpiolib driver for the
Qualcomm TLMM block found in the Qualcomm MSM8996 platform.
+config PINCTRL_MSM8998
+ tristate "Qualcomm MSM8998 pin controller driver"
+ depends on GPIOLIB && OF
+ select PINCTRL_MSM
+ help
+ This is the pinctrl, pinmux, pinconf and gpiolib driver for the
+ Qualcomm TLMM block found in the Qualcomm MSM8998 platform.
+
config PINCTRL_QDF2XXX
tristate "Qualcomm Technologies QDF2xxx pin controller driver"
depends on GPIOLIB && ACPI
diff --git a/drivers/pinctrl/qcom/Makefile b/drivers/pinctrl/qcom/Makefile
index ab47764..dba7303 100644
--- a/drivers/pinctrl/qcom/Makefile
+++ b/drivers/pinctrl/qcom/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
obj-$(CONFIG_PINCTRL_MSM8916) += pinctrl-msm8916.o
obj-$(CONFIG_PINCTRL_MSM8994) += pinctrl-msm8994.o
obj-$(CONFIG_PINCTRL_MSM8996) += pinctrl-msm8996.o
+obj-$(CONFIG_PINCTRL_MSM8998) += pinctrl-msm8998.o
obj-$(CONFIG_PINCTRL_QDF2XXX) += pinctrl-qdf2xxx.o
obj-$(CONFIG_PINCTRL_MDM9615) += pinctrl-mdm9615.o
obj-$(CONFIG_PINCTRL_QCOM_SPMI_PMIC) += pinctrl-spmi-gpio.o
diff --git a/drivers/pinctrl/qcom/pinctrl-msm8998.c b/drivers/pinctrl/qcom/pinctrl-msm8998.c
new file mode 100644
index 0000000..584a5f0
--- /dev/null
+++ b/drivers/pinctrl/qcom/pinctrl-msm8998.c
@@ -0,0 +1,1933 @@
+/*
+ * Copyright (c) 2015-2016, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname) \
+ [msm_mux_##fname] = { \
+ .name = #fname, \
+ .groups = fname##_groups, \
+ .ngroups = ARRAY_SIZE(fname##_groups), \
+ }
+
+#define NORTH 0x500000
+#define WEST 0x100000
+#define EAST 0x900000
+#define REG_SIZE 0x1000
+#define PINGROUP(id, base, f1, f2, f3, f4, f5, f6, f7, f8, f9) \
+ { \
+ .name = "gpio" #id, \
+ .pins = gpio##id##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins), \
+ .funcs = (int[]){ \
+ msm_mux_gpio, /* gpio mode */ \
+ msm_mux_##f1, \
+ msm_mux_##f2, \
+ msm_mux_##f3, \
+ msm_mux_##f4, \
+ msm_mux_##f5, \
+ msm_mux_##f6, \
+ msm_mux_##f7, \
+ msm_mux_##f8, \
+ msm_mux_##f9 \
+ }, \
+ .nfuncs = 10, \
+ .ctl_reg = base + REG_SIZE * id, \
+ .io_reg = base + 0x4 + REG_SIZE * id, \
+ .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
+ .intr_status_reg = base + 0xc + REG_SIZE * id, \
+ .intr_target_reg = base + 0x8 + REG_SIZE * id, \
+ .mux_bit = 2, \
+ .pull_bit = 0, \
+ .drv_bit = 6, \
+ .oe_bit = 9, \
+ .in_bit = 0, \
+ .out_bit = 1, \
+ .intr_enable_bit = 0, \
+ .intr_status_bit = 0, \
+ .intr_target_bit = 5, \
+ .intr_target_kpss_val = 3, \
+ .intr_raw_status_bit = 4, \
+ .intr_polarity_bit = 1, \
+ .intr_detection_bit = 2, \
+ .intr_detection_width = 2, \
+ }
+
+#define SDC_QDSD_PINGROUP(pg_name, ctl, pull, drv) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = ctl, \
+ .io_reg = 0, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = pull, \
+ .drv_bit = drv, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = -1, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+
+#define UFS_RESET(pg_name, offset) \
+ { \
+ .name = #pg_name, \
+ .pins = pg_name##_pins, \
+ .npins = (unsigned int)ARRAY_SIZE(pg_name##_pins), \
+ .ctl_reg = offset, \
+ .io_reg = offset + 0x4, \
+ .intr_cfg_reg = 0, \
+ .intr_status_reg = 0, \
+ .intr_target_reg = 0, \
+ .mux_bit = -1, \
+ .pull_bit = 3, \
+ .drv_bit = 0, \
+ .oe_bit = -1, \
+ .in_bit = -1, \
+ .out_bit = 0, \
+ .intr_enable_bit = -1, \
+ .intr_status_bit = -1, \
+ .intr_target_bit = -1, \
+ .intr_raw_status_bit = -1, \
+ .intr_polarity_bit = -1, \
+ .intr_detection_bit = -1, \
+ .intr_detection_width = -1, \
+ }
+static const struct pinctrl_pin_desc msm8998_pins[] = {
+ PINCTRL_PIN(0, "GPIO_0"),
+ PINCTRL_PIN(1, "GPIO_1"),
+ PINCTRL_PIN(2, "GPIO_2"),
+ PINCTRL_PIN(3, "GPIO_3"),
+ PINCTRL_PIN(4, "GPIO_4"),
+ PINCTRL_PIN(5, "GPIO_5"),
+ PINCTRL_PIN(6, "GPIO_6"),
+ PINCTRL_PIN(7, "GPIO_7"),
+ PINCTRL_PIN(8, "GPIO_8"),
+ PINCTRL_PIN(9, "GPIO_9"),
+ PINCTRL_PIN(10, "GPIO_10"),
+ PINCTRL_PIN(11, "GPIO_11"),
+ PINCTRL_PIN(12, "GPIO_12"),
+ PINCTRL_PIN(13, "GPIO_13"),
+ PINCTRL_PIN(14, "GPIO_14"),
+ PINCTRL_PIN(15, "GPIO_15"),
+ PINCTRL_PIN(16, "GPIO_16"),
+ PINCTRL_PIN(17, "GPIO_17"),
+ PINCTRL_PIN(18, "GPIO_18"),
+ PINCTRL_PIN(19, "GPIO_19"),
+ PINCTRL_PIN(20, "GPIO_20"),
+ PINCTRL_PIN(21, "GPIO_21"),
+ PINCTRL_PIN(22, "GPIO_22"),
+ PINCTRL_PIN(23, "GPIO_23"),
+ PINCTRL_PIN(24, "GPIO_24"),
+ PINCTRL_PIN(25, "GPIO_25"),
+ PINCTRL_PIN(26, "GPIO_26"),
+ PINCTRL_PIN(27, "GPIO_27"),
+ PINCTRL_PIN(28, "GPIO_28"),
+ PINCTRL_PIN(29, "GPIO_29"),
+ PINCTRL_PIN(30, "GPIO_30"),
+ PINCTRL_PIN(31, "GPIO_31"),
+ PINCTRL_PIN(32, "GPIO_32"),
+ PINCTRL_PIN(33, "GPIO_33"),
+ PINCTRL_PIN(34, "GPIO_34"),
+ PINCTRL_PIN(35, "GPIO_35"),
+ PINCTRL_PIN(36, "GPIO_36"),
+ PINCTRL_PIN(37, "GPIO_37"),
+ PINCTRL_PIN(38, "GPIO_38"),
+ PINCTRL_PIN(39, "GPIO_39"),
+ PINCTRL_PIN(40, "GPIO_40"),
+ PINCTRL_PIN(41, "GPIO_41"),
+ PINCTRL_PIN(42, "GPIO_42"),
+ PINCTRL_PIN(43, "GPIO_43"),
+ PINCTRL_PIN(44, "GPIO_44"),
+ PINCTRL_PIN(45, "GPIO_45"),
+ PINCTRL_PIN(46, "GPIO_46"),
+ PINCTRL_PIN(47, "GPIO_47"),
+ PINCTRL_PIN(48, "GPIO_48"),
+ PINCTRL_PIN(49, "GPIO_49"),
+ PINCTRL_PIN(50, "GPIO_50"),
+ PINCTRL_PIN(51, "GPIO_51"),
+ PINCTRL_PIN(52, "GPIO_52"),
+ PINCTRL_PIN(53, "GPIO_53"),
+ PINCTRL_PIN(54, "GPIO_54"),
+ PINCTRL_PIN(55, "GPIO_55"),
+ PINCTRL_PIN(56, "GPIO_56"),
+ PINCTRL_PIN(57, "GPIO_57"),
+ PINCTRL_PIN(58, "GPIO_58"),
+ PINCTRL_PIN(59, "GPIO_59"),
+ PINCTRL_PIN(60, "GPIO_60"),
+ PINCTRL_PIN(61, "GPIO_61"),
+ PINCTRL_PIN(62, "GPIO_62"),
+ PINCTRL_PIN(63, "GPIO_63"),
+ PINCTRL_PIN(64, "GPIO_64"),
+ PINCTRL_PIN(65, "GPIO_65"),
+ PINCTRL_PIN(66, "GPIO_66"),
+ PINCTRL_PIN(67, "GPIO_67"),
+ PINCTRL_PIN(68, "GPIO_68"),
+ PINCTRL_PIN(69, "GPIO_69"),
+ PINCTRL_PIN(70, "GPIO_70"),
+ PINCTRL_PIN(71, "GPIO_71"),
+ PINCTRL_PIN(72, "GPIO_72"),
+ PINCTRL_PIN(73, "GPIO_73"),
+ PINCTRL_PIN(74, "GPIO_74"),
+ PINCTRL_PIN(75, "GPIO_75"),
+ PINCTRL_PIN(76, "GPIO_76"),
+ PINCTRL_PIN(77, "GPIO_77"),
+ PINCTRL_PIN(78, "GPIO_78"),
+ PINCTRL_PIN(79, "GPIO_79"),
+ PINCTRL_PIN(80, "GPIO_80"),
+ PINCTRL_PIN(81, "GPIO_81"),
+ PINCTRL_PIN(82, "GPIO_82"),
+ PINCTRL_PIN(83, "GPIO_83"),
+ PINCTRL_PIN(84, "GPIO_84"),
+ PINCTRL_PIN(85, "GPIO_85"),
+ PINCTRL_PIN(86, "GPIO_86"),
+ PINCTRL_PIN(87, "GPIO_87"),
+ PINCTRL_PIN(88, "GPIO_88"),
+ PINCTRL_PIN(89, "GPIO_89"),
+ PINCTRL_PIN(90, "GPIO_90"),
+ PINCTRL_PIN(91, "GPIO_91"),
+ PINCTRL_PIN(92, "GPIO_92"),
+ PINCTRL_PIN(93, "GPIO_93"),
+ PINCTRL_PIN(94, "GPIO_94"),
+ PINCTRL_PIN(95, "GPIO_95"),
+ PINCTRL_PIN(96, "GPIO_96"),
+ PINCTRL_PIN(97, "GPIO_97"),
+ PINCTRL_PIN(98, "GPIO_98"),
+ PINCTRL_PIN(99, "GPIO_99"),
+ PINCTRL_PIN(100, "GPIO_100"),
+ PINCTRL_PIN(101, "GPIO_101"),
+ PINCTRL_PIN(102, "GPIO_102"),
+ PINCTRL_PIN(103, "GPIO_103"),
+ PINCTRL_PIN(104, "GPIO_104"),
+ PINCTRL_PIN(105, "GPIO_105"),
+ PINCTRL_PIN(106, "GPIO_106"),
+ PINCTRL_PIN(107, "GPIO_107"),
+ PINCTRL_PIN(108, "GPIO_108"),
+ PINCTRL_PIN(109, "GPIO_109"),
+ PINCTRL_PIN(110, "GPIO_110"),
+ PINCTRL_PIN(111, "GPIO_111"),
+ PINCTRL_PIN(112, "GPIO_112"),
+ PINCTRL_PIN(113, "GPIO_113"),
+ PINCTRL_PIN(114, "GPIO_114"),
+ PINCTRL_PIN(115, "GPIO_115"),
+ PINCTRL_PIN(116, "GPIO_116"),
+ PINCTRL_PIN(117, "GPIO_117"),
+ PINCTRL_PIN(118, "GPIO_118"),
+ PINCTRL_PIN(119, "GPIO_119"),
+ PINCTRL_PIN(120, "GPIO_120"),
+ PINCTRL_PIN(121, "GPIO_121"),
+ PINCTRL_PIN(122, "GPIO_122"),
+ PINCTRL_PIN(123, "GPIO_123"),
+ PINCTRL_PIN(124, "GPIO_124"),
+ PINCTRL_PIN(125, "GPIO_125"),
+ PINCTRL_PIN(126, "GPIO_126"),
+ PINCTRL_PIN(127, "GPIO_127"),
+ PINCTRL_PIN(128, "GPIO_128"),
+ PINCTRL_PIN(129, "GPIO_129"),
+ PINCTRL_PIN(130, "GPIO_130"),
+ PINCTRL_PIN(131, "GPIO_131"),
+ PINCTRL_PIN(132, "GPIO_132"),
+ PINCTRL_PIN(133, "GPIO_133"),
+ PINCTRL_PIN(134, "GPIO_134"),
+ PINCTRL_PIN(135, "GPIO_135"),
+ PINCTRL_PIN(136, "GPIO_136"),
+ PINCTRL_PIN(137, "GPIO_137"),
+ PINCTRL_PIN(138, "GPIO_138"),
+ PINCTRL_PIN(139, "GPIO_139"),
+ PINCTRL_PIN(140, "GPIO_140"),
+ PINCTRL_PIN(141, "GPIO_141"),
+ PINCTRL_PIN(142, "GPIO_142"),
+ PINCTRL_PIN(143, "GPIO_143"),
+ PINCTRL_PIN(144, "GPIO_144"),
+ PINCTRL_PIN(145, "GPIO_145"),
+ PINCTRL_PIN(146, "GPIO_146"),
+ PINCTRL_PIN(147, "GPIO_147"),
+ PINCTRL_PIN(148, "GPIO_148"),
+ PINCTRL_PIN(149, "GPIO_149"),
+ PINCTRL_PIN(150, "SDC2_CLK"),
+ PINCTRL_PIN(151, "SDC2_CMD"),
+ PINCTRL_PIN(152, "SDC2_DATA"),
+ PINCTRL_PIN(153, "UFS_RESET"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+ static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+DECLARE_MSM_GPIO_PINS(70);
+DECLARE_MSM_GPIO_PINS(71);
+DECLARE_MSM_GPIO_PINS(72);
+DECLARE_MSM_GPIO_PINS(73);
+DECLARE_MSM_GPIO_PINS(74);
+DECLARE_MSM_GPIO_PINS(75);
+DECLARE_MSM_GPIO_PINS(76);
+DECLARE_MSM_GPIO_PINS(77);
+DECLARE_MSM_GPIO_PINS(78);
+DECLARE_MSM_GPIO_PINS(79);
+DECLARE_MSM_GPIO_PINS(80);
+DECLARE_MSM_GPIO_PINS(81);
+DECLARE_MSM_GPIO_PINS(82);
+DECLARE_MSM_GPIO_PINS(83);
+DECLARE_MSM_GPIO_PINS(84);
+DECLARE_MSM_GPIO_PINS(85);
+DECLARE_MSM_GPIO_PINS(86);
+DECLARE_MSM_GPIO_PINS(87);
+DECLARE_MSM_GPIO_PINS(88);
+DECLARE_MSM_GPIO_PINS(89);
+DECLARE_MSM_GPIO_PINS(90);
+DECLARE_MSM_GPIO_PINS(91);
+DECLARE_MSM_GPIO_PINS(92);
+DECLARE_MSM_GPIO_PINS(93);
+DECLARE_MSM_GPIO_PINS(94);
+DECLARE_MSM_GPIO_PINS(95);
+DECLARE_MSM_GPIO_PINS(96);
+DECLARE_MSM_GPIO_PINS(97);
+DECLARE_MSM_GPIO_PINS(98);
+DECLARE_MSM_GPIO_PINS(99);
+DECLARE_MSM_GPIO_PINS(100);
+DECLARE_MSM_GPIO_PINS(101);
+DECLARE_MSM_GPIO_PINS(102);
+DECLARE_MSM_GPIO_PINS(103);
+DECLARE_MSM_GPIO_PINS(104);
+DECLARE_MSM_GPIO_PINS(105);
+DECLARE_MSM_GPIO_PINS(106);
+DECLARE_MSM_GPIO_PINS(107);
+DECLARE_MSM_GPIO_PINS(108);
+DECLARE_MSM_GPIO_PINS(109);
+DECLARE_MSM_GPIO_PINS(110);
+DECLARE_MSM_GPIO_PINS(111);
+DECLARE_MSM_GPIO_PINS(112);
+DECLARE_MSM_GPIO_PINS(113);
+DECLARE_MSM_GPIO_PINS(114);
+DECLARE_MSM_GPIO_PINS(115);
+DECLARE_MSM_GPIO_PINS(116);
+DECLARE_MSM_GPIO_PINS(117);
+DECLARE_MSM_GPIO_PINS(118);
+DECLARE_MSM_GPIO_PINS(119);
+DECLARE_MSM_GPIO_PINS(120);
+DECLARE_MSM_GPIO_PINS(121);
+DECLARE_MSM_GPIO_PINS(122);
+DECLARE_MSM_GPIO_PINS(123);
+DECLARE_MSM_GPIO_PINS(124);
+DECLARE_MSM_GPIO_PINS(125);
+DECLARE_MSM_GPIO_PINS(126);
+DECLARE_MSM_GPIO_PINS(127);
+DECLARE_MSM_GPIO_PINS(128);
+DECLARE_MSM_GPIO_PINS(129);
+DECLARE_MSM_GPIO_PINS(130);
+DECLARE_MSM_GPIO_PINS(131);
+DECLARE_MSM_GPIO_PINS(132);
+DECLARE_MSM_GPIO_PINS(133);
+DECLARE_MSM_GPIO_PINS(134);
+DECLARE_MSM_GPIO_PINS(135);
+DECLARE_MSM_GPIO_PINS(136);
+DECLARE_MSM_GPIO_PINS(137);
+DECLARE_MSM_GPIO_PINS(138);
+DECLARE_MSM_GPIO_PINS(139);
+DECLARE_MSM_GPIO_PINS(140);
+DECLARE_MSM_GPIO_PINS(141);
+DECLARE_MSM_GPIO_PINS(142);
+DECLARE_MSM_GPIO_PINS(143);
+DECLARE_MSM_GPIO_PINS(144);
+DECLARE_MSM_GPIO_PINS(145);
+DECLARE_MSM_GPIO_PINS(146);
+DECLARE_MSM_GPIO_PINS(147);
+DECLARE_MSM_GPIO_PINS(148);
+DECLARE_MSM_GPIO_PINS(149);
+
+static const unsigned int sdc2_clk_pins[] = { 150 };
+static const unsigned int sdc2_cmd_pins[] = { 151 };
+static const unsigned int sdc2_data_pins[] = { 152 };
+static const unsigned int ufs_reset_pins[] = { 153 };
+
+enum msm8998_functions {
+ msm_mux_blsp_spi1,
+ msm_mux_blsp_uim1_a,
+ msm_mux_blsp_uart1_a,
+ msm_mux_blsp_i2c1,
+ msm_mux_blsp_spi8,
+ msm_mux_blsp_uart8_a,
+ msm_mux_blsp_uim8_a,
+ msm_mux_qdss_cti0_b,
+ msm_mux_blsp_i2c8,
+ msm_mux_ddr_bist,
+ msm_mux_atest_tsens2,
+ msm_mux_atest_usb1,
+ msm_mux_blsp_spi4,
+ msm_mux_blsp_uart1_b,
+ msm_mux_blsp_uim1_b,
+ msm_mux_wlan1_adc1,
+ msm_mux_atest_usb13,
+ msm_mux_bimc_dte1,
+ msm_mux_tsif1_sync,
+ msm_mux_wlan1_adc0,
+ msm_mux_atest_usb12,
+ msm_mux_bimc_dte0,
+ msm_mux_mdp_vsync_a,
+ msm_mux_blsp_i2c4,
+ msm_mux_atest_gpsadc1,
+ msm_mux_wlan2_adc1,
+ msm_mux_atest_usb11,
+ msm_mux_edp_lcd,
+ msm_mux_dbg_out,
+ msm_mux_atest_gpsadc0,
+ msm_mux_wlan2_adc0,
+ msm_mux_atest_usb10,
+ msm_mux_mdp_vsync,
+ msm_mux_m_voc,
+ msm_mux_cam_mclk,
+ msm_mux_pll_bypassnl,
+ msm_mux_qdss_gpio0,
+ msm_mux_pll_reset,
+ msm_mux_qdss_gpio1,
+ msm_mux_qdss_gpio2,
+ msm_mux_qdss_gpio3,
+ msm_mux_cci_i2c,
+ msm_mux_qdss_gpio4,
+ msm_mux_phase_flag14,
+ msm_mux_qdss_gpio5,
+ msm_mux_phase_flag15,
+ msm_mux_qdss_gpio6,
+ msm_mux_qdss_gpio7,
+ msm_mux_cci_timer4,
+ msm_mux_blsp2_spi,
+ msm_mux_qdss_gpio11,
+ msm_mux_qdss_gpio12,
+ msm_mux_qdss_gpio13,
+ msm_mux_qdss_gpio14,
+ msm_mux_qdss_gpio15,
+ msm_mux_cci_timer0,
+ msm_mux_qdss_gpio8,
+ msm_mux_vsense_data0,
+ msm_mux_cci_timer1,
+ msm_mux_qdss_gpio,
+ msm_mux_vsense_data1,
+ msm_mux_cci_timer2,
+ msm_mux_blsp1_spi_b,
+ msm_mux_qdss_gpio9,
+ msm_mux_vsense_mode,
+ msm_mux_cci_timer3,
+ msm_mux_cci_async,
+ msm_mux_blsp1_spi_a,
+ msm_mux_qdss_gpio10,
+ msm_mux_vsense_clkout,
+ msm_mux_hdmi_rcv,
+ msm_mux_hdmi_cec,
+ msm_mux_blsp_spi2,
+ msm_mux_blsp_uart2_a,
+ msm_mux_blsp_uim2_a,
+ msm_mux_pwr_modem,
+ msm_mux_hdmi_ddc,
+ msm_mux_blsp_i2c2,
+ msm_mux_pwr_nav,
+ msm_mux_pwr_crypto,
+ msm_mux_hdmi_hot,
+ msm_mux_edp_hot,
+ msm_mux_pci_e0,
+ msm_mux_jitter_bist,
+ msm_mux_agera_pll,
+ msm_mux_atest_tsens,
+ msm_mux_usb_phy,
+ msm_mux_lpass_slimbus,
+ msm_mux_sd_write,
+ msm_mux_tsif1_error,
+ msm_mux_blsp_spi6,
+ msm_mux_blsp_uart3_b,
+ msm_mux_blsp_uim3_b,
+ msm_mux_blsp_i2c6,
+ msm_mux_bt_reset,
+ msm_mux_blsp_spi3,
+ msm_mux_blsp_uart3_a,
+ msm_mux_blsp_uim3_a,
+ msm_mux_blsp_i2c3,
+ msm_mux_blsp_spi9,
+ msm_mux_blsp_uart9_a,
+ msm_mux_blsp_uim9_a,
+ msm_mux_blsp10_spi_b,
+ msm_mux_qdss_cti0_a,
+ msm_mux_blsp_i2c9,
+ msm_mux_blsp10_spi_a,
+ msm_mux_blsp_spi7,
+ msm_mux_blsp_uart7_a,
+ msm_mux_blsp_uim7_a,
+ msm_mux_blsp_i2c7,
+ msm_mux_qua_mi2s,
+ msm_mux_blsp10_spi,
+ msm_mux_gcc_gp1_a,
+ msm_mux_ssc_irq,
+ msm_mux_blsp_spi11,
+ msm_mux_blsp_uart8_b,
+ msm_mux_blsp_uim8_b,
+ msm_mux_gcc_gp2_a,
+ msm_mux_qdss_cti1_a,
+ msm_mux_gcc_gp3_a,
+ msm_mux_blsp_i2c11,
+ msm_mux_cri_trng0,
+ msm_mux_cri_trng1,
+ msm_mux_cri_trng,
+ msm_mux_pri_mi2s,
+ msm_mux_sp_cmu,
+ msm_mux_blsp_spi10,
+ msm_mux_blsp_uart7_b,
+ msm_mux_blsp_uim7_b,
+ msm_mux_pri_mi2s_ws,
+ msm_mux_blsp_i2c10,
+ msm_mux_spkr_i2s,
+ msm_mux_audio_ref,
+ msm_mux_blsp9_spi,
+ msm_mux_tsense_pwm1,
+ msm_mux_tsense_pwm2,
+ msm_mux_btfm_slimbus,
+ msm_mux_phase_flag0,
+ msm_mux_ter_mi2s,
+ msm_mux_phase_flag7,
+ msm_mux_phase_flag8,
+ msm_mux_phase_flag9,
+ msm_mux_phase_flag4,
+ msm_mux_gcc_gp1_b,
+ msm_mux_sec_mi2s,
+ msm_mux_blsp_spi12,
+ msm_mux_blsp_uart9_b,
+ msm_mux_blsp_uim9_b,
+ msm_mux_gcc_gp2_b,
+ msm_mux_gcc_gp3_b,
+ msm_mux_blsp_i2c12,
+ msm_mux_blsp_spi5,
+ msm_mux_blsp_uart2_b,
+ msm_mux_blsp_uim2_b,
+ msm_mux_blsp_i2c5,
+ msm_mux_tsif1_clk,
+ msm_mux_phase_flag10,
+ msm_mux_tsif1_en,
+ msm_mux_mdp_vsync0,
+ msm_mux_mdp_vsync1,
+ msm_mux_mdp_vsync2,
+ msm_mux_mdp_vsync3,
+ msm_mux_blsp1_spi,
+ msm_mux_tgu_ch0,
+ msm_mux_qdss_cti1_b,
+ msm_mux_tsif1_data,
+ msm_mux_sdc4_cmd,
+ msm_mux_tgu_ch1,
+ msm_mux_phase_flag1,
+ msm_mux_tsif2_error,
+ msm_mux_sdc43,
+ msm_mux_vfr_1,
+ msm_mux_phase_flag2,
+ msm_mux_tsif2_clk,
+ msm_mux_sdc4_clk,
+ msm_mux_tsif2_en,
+ msm_mux_sdc42,
+ msm_mux_sd_card,
+ msm_mux_tsif2_data,
+ msm_mux_sdc41,
+ msm_mux_tsif2_sync,
+ msm_mux_sdc40,
+ msm_mux_phase_flag3,
+ msm_mux_mdp_vsync_b,
+ msm_mux_ldo_en,
+ msm_mux_ldo_update,
+ msm_mux_blsp_uart8,
+ msm_mux_blsp11_i2c,
+ msm_mux_prng_rosc,
+ msm_mux_phase_flag5,
+ msm_mux_uim2_data,
+ msm_mux_uim2_clk,
+ msm_mux_uim2_reset,
+ msm_mux_uim2_present,
+ msm_mux_uim1_data,
+ msm_mux_uim1_clk,
+ msm_mux_uim1_reset,
+ msm_mux_uim1_present,
+ msm_mux_uim_batt,
+ msm_mux_phase_flag16,
+ msm_mux_nav_dr,
+ msm_mux_phase_flag11,
+ msm_mux_phase_flag12,
+ msm_mux_phase_flag13,
+ msm_mux_atest_char,
+ msm_mux_adsp_ext,
+ msm_mux_phase_flag17,
+ msm_mux_atest_char3,
+ msm_mux_phase_flag18,
+ msm_mux_atest_char2,
+ msm_mux_phase_flag19,
+ msm_mux_atest_char1,
+ msm_mux_phase_flag20,
+ msm_mux_atest_char0,
+ msm_mux_phase_flag21,
+ msm_mux_phase_flag22,
+ msm_mux_phase_flag23,
+ msm_mux_phase_flag24,
+ msm_mux_phase_flag25,
+ msm_mux_modem_tsync,
+ msm_mux_nav_pps,
+ msm_mux_phase_flag26,
+ msm_mux_phase_flag27,
+ msm_mux_qlink_request,
+ msm_mux_phase_flag28,
+ msm_mux_qlink_enable,
+ msm_mux_phase_flag6,
+ msm_mux_phase_flag29,
+ msm_mux_phase_flag30,
+ msm_mux_phase_flag31,
+ msm_mux_pa_indicator,
+ msm_mux_ssbi1,
+ msm_mux_isense_dbg,
+ msm_mux_mss_lte,
+ msm_mux_gpio,
+ msm_mux_NA,
+};
+
+static const char * const gpio_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+ "gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+ "gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+ "gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+ "gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+ "gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+ "gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+ "gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+ "gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69", "gpio70",
+ "gpio71", "gpio72", "gpio73", "gpio74", "gpio75", "gpio76", "gpio77",
+ "gpio78", "gpio79", "gpio80", "gpio81", "gpio82", "gpio83", "gpio84",
+ "gpio85", "gpio86", "gpio87", "gpio88", "gpio89", "gpio90", "gpio91",
+ "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97", "gpio98",
+ "gpio99", "gpio100", "gpio101", "gpio102", "gpio103", "gpio104",
+ "gpio105", "gpio106", "gpio107", "gpio108", "gpio109", "gpio110",
+ "gpio111", "gpio112", "gpio113", "gpio114", "gpio115", "gpio116",
+ "gpio117", "gpio118", "gpio119", "gpio120", "gpio121", "gpio122",
+ "gpio123", "gpio124", "gpio125", "gpio126", "gpio127", "gpio128",
+ "gpio129", "gpio130", "gpio131", "gpio132", "gpio133", "gpio134",
+ "gpio135", "gpio136", "gpio137", "gpio138", "gpio139", "gpio140",
+ "gpio141", "gpio142", "gpio143", "gpio144", "gpio145", "gpio146",
+ "gpio147", "gpio148", "gpio149",
+};
+static const char * const blsp_spi1_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const blsp_uim1_a_groups[] = {
+ "gpio0", "gpio1",
+};
+static const char * const blsp_uart1_a_groups[] = {
+ "gpio0", "gpio1", "gpio2", "gpio3",
+};
+static const char * const blsp_i2c1_groups[] = {
+ "gpio2", "gpio3",
+};
+static const char * const blsp_spi8_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const blsp_uart8_a_groups[] = {
+ "gpio4", "gpio5", "gpio6", "gpio7",
+};
+static const char * const blsp_uim8_a_groups[] = {
+ "gpio4", "gpio5",
+};
+static const char * const qdss_cti0_b_groups[] = {
+ "gpio4", "gpio5",
+};
+static const char * const blsp_i2c8_groups[] = {
+ "gpio6", "gpio7",
+};
+static const char * const ddr_bist_groups[] = {
+ "gpio7", "gpio8", "gpio9", "gpio10",
+};
+static const char * const atest_tsens2_groups[] = {
+ "gpio7",
+};
+static const char * const atest_usb1_groups[] = {
+ "gpio7",
+};
+static const char * const blsp_spi4_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_uart1_b_groups[] = {
+ "gpio8", "gpio9", "gpio10", "gpio11",
+};
+static const char * const blsp_uim1_b_groups[] = {
+ "gpio8", "gpio9",
+};
+static const char * const wlan1_adc1_groups[] = {
+ "gpio8",
+};
+static const char * const atest_usb13_groups[] = {
+ "gpio8",
+};
+static const char * const bimc_dte1_groups[] = {
+ "gpio8", "gpio10",
+};
+static const char * const tsif1_sync_groups[] = {
+ "gpio9",
+};
+static const char * const wlan1_adc0_groups[] = {
+ "gpio9",
+};
+static const char * const atest_usb12_groups[] = {
+ "gpio9",
+};
+static const char * const bimc_dte0_groups[] = {
+ "gpio9", "gpio11",
+};
+static const char * const mdp_vsync_a_groups[] = {
+ "gpio10", "gpio11",
+};
+static const char * const blsp_i2c4_groups[] = {
+ "gpio10", "gpio11",
+};
+static const char * const atest_gpsadc1_groups[] = {
+ "gpio10",
+};
+static const char * const wlan2_adc1_groups[] = {
+ "gpio10",
+};
+static const char * const atest_usb11_groups[] = {
+ "gpio10",
+};
+static const char * const edp_lcd_groups[] = {
+ "gpio11",
+};
+static const char * const dbg_out_groups[] = {
+ "gpio11",
+};
+static const char * const atest_gpsadc0_groups[] = {
+ "gpio11",
+};
+static const char * const wlan2_adc0_groups[] = {
+ "gpio11",
+};
+static const char * const atest_usb10_groups[] = {
+ "gpio11",
+};
+static const char * const mdp_vsync_groups[] = {
+ "gpio12",
+};
+static const char * const m_voc_groups[] = {
+ "gpio12",
+};
+static const char * const cam_mclk_groups[] = {
+ "gpio13", "gpio14", "gpio15", "gpio16",
+};
+static const char * const pll_bypassnl_groups[] = {
+ "gpio13",
+};
+static const char * const qdss_gpio0_groups[] = {
+ "gpio13", "gpio117",
+};
+static const char * const pll_reset_groups[] = {
+ "gpio14",
+};
+static const char * const qdss_gpio1_groups[] = {
+ "gpio14", "gpio118",
+};
+static const char * const qdss_gpio2_groups[] = {
+ "gpio15", "gpio119",
+};
+static const char * const qdss_gpio3_groups[] = {
+ "gpio16", "gpio120",
+};
+static const char * const cci_i2c_groups[] = {
+ "gpio17", "gpio18", "gpio19", "gpio20",
+};
+static const char * const qdss_gpio4_groups[] = {
+ "gpio17", "gpio121",
+};
+static const char * const phase_flag14_groups[] = {
+ "gpio18",
+};
+static const char * const qdss_gpio5_groups[] = {
+ "gpio18", "gpio122",
+};
+static const char * const phase_flag15_groups[] = {
+ "gpio19",
+};
+static const char * const qdss_gpio6_groups[] = {
+ "gpio19", "gpio41",
+};
+static const char * const qdss_gpio7_groups[] = {
+ "gpio20", "gpio42",
+};
+static const char * const cci_timer4_groups[] = {
+ "gpio25",
+};
+static const char * const blsp2_spi_groups[] = {
+ "gpio25", "gpio29", "gpio30",
+};
+static const char * const qdss_gpio11_groups[] = {
+ "gpio25", "gpio79",
+};
+static const char * const qdss_gpio12_groups[] = {
+ "gpio26", "gpio80",
+};
+static const char * const qdss_gpio13_groups[] = {
+ "gpio27", "gpio93",
+};
+static const char * const qdss_gpio14_groups[] = {
+ "gpio28", "gpio43",
+};
+static const char * const qdss_gpio15_groups[] = {
+ "gpio29", "gpio44",
+};
+static const char * const cci_timer0_groups[] = {
+ "gpio21",
+};
+static const char * const qdss_gpio8_groups[] = {
+ "gpio21", "gpio75",
+};
+static const char * const vsense_data0_groups[] = {
+ "gpio21",
+};
+static const char * const cci_timer1_groups[] = {
+ "gpio22",
+};
+static const char * const qdss_gpio_groups[] = {
+ "gpio22", "gpio30", "gpio123", "gpio124",
+};
+static const char * const vsense_data1_groups[] = {
+ "gpio22",
+};
+static const char * const cci_timer2_groups[] = {
+ "gpio23",
+};
+static const char * const blsp1_spi_b_groups[] = {
+ "gpio23", "gpio28",
+};
+static const char * const qdss_gpio9_groups[] = {
+ "gpio23", "gpio76",
+};
+static const char * const vsense_mode_groups[] = {
+ "gpio23",
+};
+static const char * const cci_timer3_groups[] = {
+ "gpio24",
+};
+static const char * const cci_async_groups[] = {
+ "gpio24", "gpio25", "gpio26",
+};
+static const char * const blsp1_spi_a_groups[] = {
+ "gpio24", "gpio27",
+};
+static const char * const qdss_gpio10_groups[] = {
+ "gpio24", "gpio77",
+};
+static const char * const vsense_clkout_groups[] = {
+ "gpio24",
+};
+static const char * const hdmi_rcv_groups[] = {
+ "gpio30",
+};
+static const char * const hdmi_cec_groups[] = {
+ "gpio31",
+};
+static const char * const blsp_spi2_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const blsp_uart2_a_groups[] = {
+ "gpio31", "gpio32", "gpio33", "gpio34",
+};
+static const char * const blsp_uim2_a_groups[] = {
+ "gpio31", "gpio34",
+};
+static const char * const pwr_modem_groups[] = {
+ "gpio31",
+};
+static const char * const hdmi_ddc_groups[] = {
+ "gpio32", "gpio33",
+};
+static const char * const blsp_i2c2_groups[] = {
+ "gpio32", "gpio33",
+};
+static const char * const pwr_nav_groups[] = {
+ "gpio32",
+};
+static const char * const pwr_crypto_groups[] = {
+ "gpio33",
+};
+static const char * const hdmi_hot_groups[] = {
+ "gpio34",
+};
+static const char * const edp_hot_groups[] = {
+ "gpio34",
+};
+static const char * const pci_e0_groups[] = {
+ "gpio35", "gpio36", "gpio37",
+};
+static const char * const jitter_bist_groups[] = {
+ "gpio35",
+};
+static const char * const agera_pll_groups[] = {
+ "gpio36", "gpio37",
+};
+static const char * const atest_tsens_groups[] = {
+ "gpio36",
+};
+static const char * const usb_phy_groups[] = {
+ "gpio38",
+};
+static const char * const lpass_slimbus_groups[] = {
+ "gpio39", "gpio70", "gpio71", "gpio72",
+};
+static const char * const sd_write_groups[] = {
+ "gpio40",
+};
+static const char * const tsif1_error_groups[] = {
+ "gpio40",
+};
+static const char * const blsp_spi6_groups[] = {
+ "gpio41", "gpio42", "gpio43", "gpio44",
+};
+static const char * const blsp_uart3_b_groups[] = {
+ "gpio41", "gpio42", "gpio43", "gpio44",
+};
+static const char * const blsp_uim3_b_groups[] = {
+ "gpio41", "gpio42",
+};
+static const char * const blsp_i2c6_groups[] = {
+ "gpio43", "gpio44",
+};
+static const char * const bt_reset_groups[] = {
+ "gpio45",
+};
+static const char * const blsp_spi3_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48",
+};
+static const char * const blsp_uart3_a_groups[] = {
+ "gpio45", "gpio46", "gpio47", "gpio48",
+};
+static const char * const blsp_uim3_a_groups[] = {
+ "gpio45", "gpio46",
+};
+static const char * const blsp_i2c3_groups[] = {
+ "gpio47", "gpio48",
+};
+static const char * const blsp_spi9_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const blsp_uart9_a_groups[] = {
+ "gpio49", "gpio50", "gpio51", "gpio52",
+};
+static const char * const blsp_uim9_a_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const blsp10_spi_b_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const qdss_cti0_a_groups[] = {
+ "gpio49", "gpio50",
+};
+static const char * const blsp_i2c9_groups[] = {
+ "gpio51", "gpio52",
+};
+static const char * const blsp10_spi_a_groups[] = {
+ "gpio51", "gpio52",
+};
+static const char * const blsp_spi7_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const blsp_uart7_a_groups[] = {
+ "gpio53", "gpio54", "gpio55", "gpio56",
+};
+static const char * const blsp_uim7_a_groups[] = {
+ "gpio53", "gpio54",
+};
+static const char * const blsp_i2c7_groups[] = {
+ "gpio55", "gpio56",
+};
+static const char * const qua_mi2s_groups[] = {
+ "gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+};
+static const char * const blsp10_spi_groups[] = {
+ "gpio57",
+};
+static const char * const gcc_gp1_a_groups[] = {
+ "gpio57",
+};
+static const char * const ssc_irq_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63", "gpio78",
+ "gpio79", "gpio80", "gpio117", "gpio118", "gpio119", "gpio120",
+ "gpio121", "gpio122", "gpio123", "gpio124", "gpio125",
+};
+static const char * const blsp_spi11_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+static const char * const blsp_uart8_b_groups[] = {
+ "gpio58", "gpio59", "gpio60", "gpio61",
+};
+static const char * const blsp_uim8_b_groups[] = {
+ "gpio58", "gpio59",
+};
+static const char * const gcc_gp2_a_groups[] = {
+ "gpio58",
+};
+static const char * const qdss_cti1_a_groups[] = {
+ "gpio58", "gpio59",
+};
+static const char * const gcc_gp3_a_groups[] = {
+ "gpio59",
+};
+static const char * const blsp_i2c11_groups[] = {
+ "gpio60", "gpio61",
+};
+static const char * const cri_trng0_groups[] = {
+ "gpio60",
+};
+static const char * const cri_trng1_groups[] = {
+ "gpio61",
+};
+static const char * const cri_trng_groups[] = {
+ "gpio62",
+};
+static const char * const pri_mi2s_groups[] = {
+ "gpio64", "gpio65", "gpio67", "gpio68",
+};
+static const char * const sp_cmu_groups[] = {
+ "gpio64",
+};
+static const char * const blsp_spi10_groups[] = {
+ "gpio65", "gpio66", "gpio67", "gpio68",
+};
+static const char * const blsp_uart7_b_groups[] = {
+ "gpio65", "gpio66", "gpio67", "gpio68",
+};
+static const char * const blsp_uim7_b_groups[] = {
+ "gpio65", "gpio66",
+};
+static const char * const pri_mi2s_ws_groups[] = {
+ "gpio66",
+};
+static const char * const blsp_i2c10_groups[] = {
+ "gpio67", "gpio68",
+};
+static const char * const spkr_i2s_groups[] = {
+ "gpio69", "gpio70", "gpio71", "gpio72",
+};
+static const char * const audio_ref_groups[] = {
+ "gpio69",
+};
+static const char * const blsp9_spi_groups[] = {
+ "gpio70", "gpio71", "gpio72",
+};
+static const char * const tsense_pwm1_groups[] = {
+ "gpio71",
+};
+static const char * const tsense_pwm2_groups[] = {
+ "gpio71",
+};
+static const char * const btfm_slimbus_groups[] = {
+ "gpio73", "gpio74",
+};
+static const char * const phase_flag0_groups[] = {
+ "gpio73",
+};
+static const char * const ter_mi2s_groups[] = {
+ "gpio74", "gpio75", "gpio76", "gpio77", "gpio78",
+};
+static const char * const phase_flag7_groups[] = {
+ "gpio74",
+};
+static const char * const phase_flag8_groups[] = {
+ "gpio75",
+};
+static const char * const phase_flag9_groups[] = {
+ "gpio76",
+};
+static const char * const phase_flag4_groups[] = {
+ "gpio77",
+};
+static const char * const gcc_gp1_b_groups[] = {
+ "gpio78",
+};
+static const char * const sec_mi2s_groups[] = {
+ "gpio79", "gpio80", "gpio81", "gpio82", "gpio83",
+};
+static const char * const blsp_spi12_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+static const char * const blsp_uart9_b_groups[] = {
+ "gpio81", "gpio82", "gpio83", "gpio84",
+};
+static const char * const blsp_uim9_b_groups[] = {
+ "gpio81", "gpio82",
+};
+static const char * const gcc_gp2_b_groups[] = {
+ "gpio81",
+};
+static const char * const gcc_gp3_b_groups[] = {
+ "gpio82",
+};
+static const char * const blsp_i2c12_groups[] = {
+ "gpio83", "gpio84",
+};
+static const char * const blsp_spi5_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio88",
+};
+static const char * const blsp_uart2_b_groups[] = {
+ "gpio85", "gpio86", "gpio87", "gpio88",
+};
+static const char * const blsp_uim2_b_groups[] = {
+ "gpio85", "gpio86",
+};
+static const char * const blsp_i2c5_groups[] = {
+ "gpio87", "gpio88",
+};
+static const char * const tsif1_clk_groups[] = {
+ "gpio89",
+};
+static const char * const phase_flag10_groups[] = {
+ "gpio89",
+};
+static const char * const tsif1_en_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync0_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync1_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync2_groups[] = {
+ "gpio90",
+};
+static const char * const mdp_vsync3_groups[] = {
+ "gpio90",
+};
+static const char * const blsp1_spi_groups[] = {
+ "gpio90",
+};
+static const char * const tgu_ch0_groups[] = {
+ "gpio90",
+};
+static const char * const qdss_cti1_b_groups[] = {
+ "gpio90", "gpio91",
+};
+static const char * const tsif1_data_groups[] = {
+ "gpio91",
+};
+static const char * const sdc4_cmd_groups[] = {
+ "gpio91",
+};
+static const char * const tgu_ch1_groups[] = {
+ "gpio91",
+};
+static const char * const phase_flag1_groups[] = {
+ "gpio91",
+};
+static const char * const tsif2_error_groups[] = {
+ "gpio92",
+};
+static const char * const sdc43_groups[] = {
+ "gpio92",
+};
+static const char * const vfr_1_groups[] = {
+ "gpio92",
+};
+static const char * const phase_flag2_groups[] = {
+ "gpio92",
+};
+static const char * const tsif2_clk_groups[] = {
+ "gpio93",
+};
+static const char * const sdc4_clk_groups[] = {
+ "gpio93",
+};
+static const char * const tsif2_en_groups[] = {
+ "gpio94",
+};
+static const char * const sdc42_groups[] = {
+ "gpio94",
+};
+static const char * const sd_card_groups[] = {
+ "gpio95",
+};
+static const char * const tsif2_data_groups[] = {
+ "gpio95",
+};
+static const char * const sdc41_groups[] = {
+ "gpio95",
+};
+static const char * const tsif2_sync_groups[] = {
+ "gpio96",
+};
+static const char * const sdc40_groups[] = {
+ "gpio96",
+};
+static const char * const phase_flag3_groups[] = {
+ "gpio96",
+};
+static const char * const mdp_vsync_b_groups[] = {
+ "gpio97", "gpio98",
+};
+static const char * const ldo_en_groups[] = {
+ "gpio97",
+};
+static const char * const ldo_update_groups[] = {
+ "gpio98",
+};
+static const char * const blsp_uart8_groups[] = {
+ "gpio100", "gpio101",
+};
+static const char * const blsp11_i2c_groups[] = {
+ "gpio102", "gpio103",
+};
+static const char * const prng_rosc_groups[] = {
+ "gpio102",
+};
+static const char * const phase_flag5_groups[] = {
+ "gpio103",
+};
+static const char * const uim2_data_groups[] = {
+ "gpio105",
+};
+static const char * const uim2_clk_groups[] = {
+ "gpio106",
+};
+static const char * const uim2_reset_groups[] = {
+ "gpio107",
+};
+static const char * const uim2_present_groups[] = {
+ "gpio108",
+};
+static const char * const uim1_data_groups[] = {
+ "gpio109",
+};
+static const char * const uim1_clk_groups[] = {
+ "gpio110",
+};
+static const char * const uim1_reset_groups[] = {
+ "gpio111",
+};
+static const char * const uim1_present_groups[] = {
+ "gpio112",
+};
+static const char * const uim_batt_groups[] = {
+ "gpio113",
+};
+static const char * const phase_flag16_groups[] = {
+ "gpio114",
+};
+static const char * const nav_dr_groups[] = {
+ "gpio115",
+};
+static const char * const phase_flag11_groups[] = {
+ "gpio115",
+};
+static const char * const phase_flag12_groups[] = {
+ "gpio116",
+};
+static const char * const phase_flag13_groups[] = {
+ "gpio117",
+};
+static const char * const atest_char_groups[] = {
+ "gpio117",
+};
+static const char * const adsp_ext_groups[] = {
+ "gpio118",
+};
+static const char * const phase_flag17_groups[] = {
+ "gpio118",
+};
+static const char * const atest_char3_groups[] = {
+ "gpio118",
+};
+static const char * const phase_flag18_groups[] = {
+ "gpio119",
+};
+static const char * const atest_char2_groups[] = {
+ "gpio119",
+};
+static const char * const phase_flag19_groups[] = {
+ "gpio120",
+};
+static const char * const atest_char1_groups[] = {
+ "gpio120",
+};
+static const char * const phase_flag20_groups[] = {
+ "gpio121",
+};
+static const char * const atest_char0_groups[] = {
+ "gpio121",
+};
+static const char * const phase_flag21_groups[] = {
+ "gpio122",
+};
+static const char * const phase_flag22_groups[] = {
+ "gpio123",
+};
+static const char * const phase_flag23_groups[] = {
+ "gpio124",
+};
+static const char * const phase_flag24_groups[] = {
+ "gpio125",
+};
+static const char * const phase_flag25_groups[] = {
+ "gpio126",
+};
+static const char * const modem_tsync_groups[] = {
+ "gpio128",
+};
+static const char * const nav_pps_groups[] = {
+ "gpio128",
+};
+static const char * const phase_flag26_groups[] = {
+ "gpio128",
+};
+static const char * const phase_flag27_groups[] = {
+ "gpio129",
+};
+static const char * const qlink_request_groups[] = {
+ "gpio130",
+};
+static const char * const phase_flag28_groups[] = {
+ "gpio130",
+};
+static const char * const qlink_enable_groups[] = {
+ "gpio131",
+};
+static const char * const phase_flag6_groups[] = {
+ "gpio131",
+};
+static const char * const phase_flag29_groups[] = {
+ "gpio132",
+};
+static const char * const phase_flag30_groups[] = {
+ "gpio133",
+};
+static const char * const phase_flag31_groups[] = {
+ "gpio134",
+};
+static const char * const pa_indicator_groups[] = {
+ "gpio135",
+};
+static const char * const ssbi1_groups[] = {
+ "gpio142",
+};
+static const char * const isense_dbg_groups[] = {
+ "gpio143",
+};
+static const char * const mss_lte_groups[] = {
+ "gpio144", "gpio145",
+};
+
+static const struct msm_function msm8998_functions[] = {
+ FUNCTION(blsp_spi1),
+ FUNCTION(gpio),
+ FUNCTION(blsp_uim1_a),
+ FUNCTION(blsp_uart1_a),
+ FUNCTION(blsp_i2c1),
+ FUNCTION(blsp_spi8),
+ FUNCTION(blsp_uart8_a),
+ FUNCTION(blsp_uim8_a),
+ FUNCTION(qdss_cti0_b),
+ FUNCTION(blsp_i2c8),
+ FUNCTION(ddr_bist),
+ FUNCTION(atest_tsens2),
+ FUNCTION(atest_usb1),
+ FUNCTION(blsp_spi4),
+ FUNCTION(blsp_uart1_b),
+ FUNCTION(blsp_uim1_b),
+ FUNCTION(wlan1_adc1),
+ FUNCTION(atest_usb13),
+ FUNCTION(bimc_dte1),
+ FUNCTION(tsif1_sync),
+ FUNCTION(wlan1_adc0),
+ FUNCTION(atest_usb12),
+ FUNCTION(bimc_dte0),
+ FUNCTION(mdp_vsync_a),
+ FUNCTION(blsp_i2c4),
+ FUNCTION(atest_gpsadc1),
+ FUNCTION(wlan2_adc1),
+ FUNCTION(atest_usb11),
+ FUNCTION(edp_lcd),
+ FUNCTION(dbg_out),
+ FUNCTION(atest_gpsadc0),
+ FUNCTION(wlan2_adc0),
+ FUNCTION(atest_usb10),
+ FUNCTION(mdp_vsync),
+ FUNCTION(m_voc),
+ FUNCTION(cam_mclk),
+ FUNCTION(pll_bypassnl),
+ FUNCTION(qdss_gpio0),
+ FUNCTION(pll_reset),
+ FUNCTION(qdss_gpio1),
+ FUNCTION(qdss_gpio2),
+ FUNCTION(qdss_gpio3),
+ FUNCTION(cci_i2c),
+ FUNCTION(qdss_gpio4),
+ FUNCTION(phase_flag14),
+ FUNCTION(qdss_gpio5),
+ FUNCTION(phase_flag15),
+ FUNCTION(qdss_gpio6),
+ FUNCTION(qdss_gpio7),
+ FUNCTION(cci_timer4),
+ FUNCTION(blsp2_spi),
+ FUNCTION(qdss_gpio11),
+ FUNCTION(qdss_gpio12),
+ FUNCTION(qdss_gpio13),
+ FUNCTION(qdss_gpio14),
+ FUNCTION(qdss_gpio15),
+ FUNCTION(cci_timer0),
+ FUNCTION(qdss_gpio8),
+ FUNCTION(vsense_data0),
+ FUNCTION(cci_timer1),
+ FUNCTION(qdss_gpio),
+ FUNCTION(vsense_data1),
+ FUNCTION(cci_timer2),
+ FUNCTION(blsp1_spi_b),
+ FUNCTION(qdss_gpio9),
+ FUNCTION(vsense_mode),
+ FUNCTION(cci_timer3),
+ FUNCTION(cci_async),
+ FUNCTION(blsp1_spi_a),
+ FUNCTION(qdss_gpio10),
+ FUNCTION(vsense_clkout),
+ FUNCTION(hdmi_rcv),
+ FUNCTION(hdmi_cec),
+ FUNCTION(blsp_spi2),
+ FUNCTION(blsp_uart2_a),
+ FUNCTION(blsp_uim2_a),
+ FUNCTION(pwr_modem),
+ FUNCTION(hdmi_ddc),
+ FUNCTION(blsp_i2c2),
+ FUNCTION(pwr_nav),
+ FUNCTION(pwr_crypto),
+ FUNCTION(hdmi_hot),
+ FUNCTION(edp_hot),
+ FUNCTION(pci_e0),
+ FUNCTION(jitter_bist),
+ FUNCTION(agera_pll),
+ FUNCTION(atest_tsens),
+ FUNCTION(usb_phy),
+ FUNCTION(lpass_slimbus),
+ FUNCTION(sd_write),
+ FUNCTION(tsif1_error),
+ FUNCTION(blsp_spi6),
+ FUNCTION(blsp_uart3_b),
+ FUNCTION(blsp_uim3_b),
+ FUNCTION(blsp_i2c6),
+ FUNCTION(bt_reset),
+ FUNCTION(blsp_spi3),
+ FUNCTION(blsp_uart3_a),
+ FUNCTION(blsp_uim3_a),
+ FUNCTION(blsp_i2c3),
+ FUNCTION(blsp_spi9),
+ FUNCTION(blsp_uart9_a),
+ FUNCTION(blsp_uim9_a),
+ FUNCTION(blsp10_spi_b),
+ FUNCTION(qdss_cti0_a),
+ FUNCTION(blsp_i2c9),
+ FUNCTION(blsp10_spi_a),
+ FUNCTION(blsp_spi7),
+ FUNCTION(blsp_uart7_a),
+ FUNCTION(blsp_uim7_a),
+ FUNCTION(blsp_i2c7),
+ FUNCTION(qua_mi2s),
+ FUNCTION(blsp10_spi),
+ FUNCTION(gcc_gp1_a),
+ FUNCTION(ssc_irq),
+ FUNCTION(blsp_spi11),
+ FUNCTION(blsp_uart8_b),
+ FUNCTION(blsp_uim8_b),
+ FUNCTION(gcc_gp2_a),
+ FUNCTION(qdss_cti1_a),
+ FUNCTION(gcc_gp3_a),
+ FUNCTION(blsp_i2c11),
+ FUNCTION(cri_trng0),
+ FUNCTION(cri_trng1),
+ FUNCTION(cri_trng),
+ FUNCTION(pri_mi2s),
+ FUNCTION(sp_cmu),
+ FUNCTION(blsp_spi10),
+ FUNCTION(blsp_uart7_b),
+ FUNCTION(blsp_uim7_b),
+ FUNCTION(pri_mi2s_ws),
+ FUNCTION(blsp_i2c10),
+ FUNCTION(spkr_i2s),
+ FUNCTION(audio_ref),
+ FUNCTION(blsp9_spi),
+ FUNCTION(tsense_pwm1),
+ FUNCTION(tsense_pwm2),
+ FUNCTION(btfm_slimbus),
+ FUNCTION(phase_flag0),
+ FUNCTION(ter_mi2s),
+ FUNCTION(phase_flag7),
+ FUNCTION(phase_flag8),
+ FUNCTION(phase_flag9),
+ FUNCTION(phase_flag4),
+ FUNCTION(gcc_gp1_b),
+ FUNCTION(sec_mi2s),
+ FUNCTION(blsp_spi12),
+ FUNCTION(blsp_uart9_b),
+ FUNCTION(blsp_uim9_b),
+ FUNCTION(gcc_gp2_b),
+ FUNCTION(gcc_gp3_b),
+ FUNCTION(blsp_i2c12),
+ FUNCTION(blsp_spi5),
+ FUNCTION(blsp_uart2_b),
+ FUNCTION(blsp_uim2_b),
+ FUNCTION(blsp_i2c5),
+ FUNCTION(tsif1_clk),
+ FUNCTION(phase_flag10),
+ FUNCTION(tsif1_en),
+ FUNCTION(mdp_vsync0),
+ FUNCTION(mdp_vsync1),
+ FUNCTION(mdp_vsync2),
+ FUNCTION(mdp_vsync3),
+ FUNCTION(blsp1_spi),
+ FUNCTION(tgu_ch0),
+ FUNCTION(qdss_cti1_b),
+ FUNCTION(tsif1_data),
+ FUNCTION(sdc4_cmd),
+ FUNCTION(tgu_ch1),
+ FUNCTION(phase_flag1),
+ FUNCTION(tsif2_error),
+ FUNCTION(sdc43),
+ FUNCTION(vfr_1),
+ FUNCTION(phase_flag2),
+ FUNCTION(tsif2_clk),
+ FUNCTION(sdc4_clk),
+ FUNCTION(tsif2_en),
+ FUNCTION(sdc42),
+ FUNCTION(sd_card),
+ FUNCTION(tsif2_data),
+ FUNCTION(sdc41),
+ FUNCTION(tsif2_sync),
+ FUNCTION(sdc40),
+ FUNCTION(phase_flag3),
+ FUNCTION(mdp_vsync_b),
+ FUNCTION(ldo_en),
+ FUNCTION(ldo_update),
+ FUNCTION(blsp_uart8),
+ FUNCTION(blsp11_i2c),
+ FUNCTION(prng_rosc),
+ FUNCTION(phase_flag5),
+ FUNCTION(uim2_data),
+ FUNCTION(uim2_clk),
+ FUNCTION(uim2_reset),
+ FUNCTION(uim2_present),
+ FUNCTION(uim1_data),
+ FUNCTION(uim1_clk),
+ FUNCTION(uim1_reset),
+ FUNCTION(uim1_present),
+ FUNCTION(uim_batt),
+ FUNCTION(phase_flag16),
+ FUNCTION(nav_dr),
+ FUNCTION(phase_flag11),
+ FUNCTION(phase_flag12),
+ FUNCTION(phase_flag13),
+ FUNCTION(atest_char),
+ FUNCTION(adsp_ext),
+ FUNCTION(phase_flag17),
+ FUNCTION(atest_char3),
+ FUNCTION(phase_flag18),
+ FUNCTION(atest_char2),
+ FUNCTION(phase_flag19),
+ FUNCTION(atest_char1),
+ FUNCTION(phase_flag20),
+ FUNCTION(atest_char0),
+ FUNCTION(phase_flag21),
+ FUNCTION(phase_flag22),
+ FUNCTION(phase_flag23),
+ FUNCTION(phase_flag24),
+ FUNCTION(phase_flag25),
+ FUNCTION(modem_tsync),
+ FUNCTION(nav_pps),
+ FUNCTION(phase_flag26),
+ FUNCTION(phase_flag27),
+ FUNCTION(qlink_request),
+ FUNCTION(phase_flag28),
+ FUNCTION(qlink_enable),
+ FUNCTION(phase_flag6),
+ FUNCTION(phase_flag29),
+ FUNCTION(phase_flag30),
+ FUNCTION(phase_flag31),
+ FUNCTION(pa_indicator),
+ FUNCTION(ssbi1),
+ FUNCTION(isense_dbg),
+ FUNCTION(mss_lte),
+};
+
+static const struct msm_pingroup msm8998_groups[] = {
+ PINGROUP(0, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(1, EAST, blsp_spi1, blsp_uart1_a, blsp_uim1_a, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(2, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(3, EAST, blsp_spi1, blsp_uart1_a, blsp_i2c1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(4, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA,
+ qdss_cti0_b, NA, NA, NA, NA),
+ PINGROUP(5, WEST, blsp_spi8, blsp_uart8_a, blsp_uim8_a, NA,
+ qdss_cti0_b, NA, NA, NA, NA),
+ PINGROUP(6, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(7, WEST, blsp_spi8, blsp_uart8_a, blsp_i2c8, ddr_bist, NA,
+ atest_tsens2, atest_usb1, NA, NA),
+ PINGROUP(8, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, NA, ddr_bist,
+ NA, wlan1_adc1, atest_usb13, bimc_dte1),
+ PINGROUP(9, EAST, blsp_spi4, blsp_uart1_b, blsp_uim1_b, tsif1_sync,
+ ddr_bist, NA, wlan1_adc0, atest_usb12, bimc_dte0),
+ PINGROUP(10, EAST, mdp_vsync_a, blsp_spi4, blsp_uart1_b, blsp_i2c4,
+ ddr_bist, atest_gpsadc1, wlan2_adc1, atest_usb11, bimc_dte1),
+ PINGROUP(11, EAST, mdp_vsync_a, edp_lcd, blsp_spi4, blsp_uart1_b,
+ blsp_i2c4, dbg_out, atest_gpsadc0, wlan2_adc0, atest_usb10),
+ PINGROUP(12, EAST, mdp_vsync, m_voc, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(13, EAST, cam_mclk, pll_bypassnl, qdss_gpio0, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(14, EAST, cam_mclk, pll_reset, qdss_gpio1, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(15, EAST, cam_mclk, qdss_gpio2, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(16, EAST, cam_mclk, qdss_gpio3, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(17, EAST, cci_i2c, qdss_gpio4, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(18, EAST, cci_i2c, phase_flag14, qdss_gpio5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(19, EAST, cci_i2c, phase_flag15, qdss_gpio6, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(20, EAST, cci_i2c, qdss_gpio7, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(21, EAST, cci_timer0, NA, qdss_gpio8, vsense_data0, NA, NA,
+ NA, NA, NA),
+ PINGROUP(22, EAST, cci_timer1, NA, qdss_gpio, vsense_data1, NA, NA, NA,
+ NA, NA),
+ PINGROUP(23, EAST, cci_timer2, blsp1_spi_b, qdss_gpio9, vsense_mode,
+ NA, NA, NA, NA, NA),
+ PINGROUP(24, EAST, cci_timer3, cci_async, blsp1_spi_a, NA, qdss_gpio10,
+ vsense_clkout, NA, NA, NA),
+ PINGROUP(25, EAST, cci_timer4, cci_async, blsp2_spi, NA, qdss_gpio11,
+ NA, NA, NA, NA),
+ PINGROUP(26, EAST, cci_async, qdss_gpio12, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(27, EAST, blsp1_spi_a, qdss_gpio13, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(28, EAST, blsp1_spi_b, qdss_gpio14, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(29, EAST, blsp2_spi, NA, qdss_gpio15, NA, NA, NA, NA, NA, NA),
+ PINGROUP(30, EAST, hdmi_rcv, blsp2_spi, qdss_gpio, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(31, EAST, hdmi_cec, blsp_spi2, blsp_uart2_a, blsp_uim2_a,
+ pwr_modem, NA, NA, NA, NA),
+ PINGROUP(32, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2,
+ pwr_nav, NA, NA, NA, NA),
+ PINGROUP(33, EAST, hdmi_ddc, blsp_spi2, blsp_uart2_a, blsp_i2c2,
+ pwr_crypto, NA, NA, NA, NA),
+ PINGROUP(34, EAST, hdmi_hot, edp_hot, blsp_spi2, blsp_uart2_a,
+ blsp_uim2_a, NA, NA, NA, NA),
+ PINGROUP(35, NORTH, pci_e0, jitter_bist, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(36, NORTH, pci_e0, agera_pll, NA, atest_tsens, NA, NA, NA, NA,
+ NA),
+ PINGROUP(37, NORTH, agera_pll, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(38, WEST, usb_phy, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(39, WEST, lpass_slimbus, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(40, EAST, sd_write, tsif1_error, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(41, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA,
+ qdss_gpio6, NA, NA, NA, NA),
+ PINGROUP(42, EAST, blsp_spi6, blsp_uart3_b, blsp_uim3_b, NA,
+ qdss_gpio7, NA, NA, NA, NA),
+ PINGROUP(43, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio14,
+ NA, NA, NA, NA),
+ PINGROUP(44, EAST, blsp_spi6, blsp_uart3_b, blsp_i2c6, NA, qdss_gpio15,
+ NA, NA, NA, NA),
+ PINGROUP(45, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(46, EAST, blsp_spi3, blsp_uart3_a, blsp_uim3_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(47, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(48, EAST, blsp_spi3, blsp_uart3_a, blsp_i2c3, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(49, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b,
+ qdss_cti0_a, NA, NA, NA, NA),
+ PINGROUP(50, NORTH, blsp_spi9, blsp_uart9_a, blsp_uim9_a, blsp10_spi_b,
+ qdss_cti0_a, NA, NA, NA, NA),
+ PINGROUP(51, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a,
+ NA, NA, NA, NA, NA),
+ PINGROUP(52, NORTH, blsp_spi9, blsp_uart9_a, blsp_i2c9, blsp10_spi_a,
+ NA, NA, NA, NA, NA),
+ PINGROUP(53, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(54, WEST, blsp_spi7, blsp_uart7_a, blsp_uim7_a, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(55, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(56, WEST, blsp_spi7, blsp_uart7_a, blsp_i2c7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(57, WEST, qua_mi2s, blsp10_spi, gcc_gp1_a, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(58, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b,
+ gcc_gp2_a, NA, qdss_cti1_a, NA, NA),
+ PINGROUP(59, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_uim8_b,
+ gcc_gp3_a, NA, qdss_cti1_a, NA, NA),
+ PINGROUP(60, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11,
+ cri_trng0, NA, NA, NA, NA),
+ PINGROUP(61, WEST, qua_mi2s, blsp_spi11, blsp_uart8_b, blsp_i2c11,
+ cri_trng1, NA, NA, NA, NA),
+ PINGROUP(62, WEST, qua_mi2s, cri_trng, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(63, WEST, qua_mi2s, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(64, WEST, pri_mi2s, sp_cmu, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(65, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_uim7_b, NA,
+ NA, NA, NA, NA),
+ PINGROUP(66, WEST, pri_mi2s_ws, blsp_spi10, blsp_uart7_b, blsp_uim7_b,
+ NA, NA, NA, NA, NA),
+ PINGROUP(67, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA,
+ NA, NA, NA, NA),
+ PINGROUP(68, WEST, pri_mi2s, blsp_spi10, blsp_uart7_b, blsp_i2c10, NA,
+ NA, NA, NA, NA),
+ PINGROUP(69, WEST, spkr_i2s, audio_ref, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(70, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(71, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, tsense_pwm1,
+ tsense_pwm2, NA, NA, NA, NA),
+ PINGROUP(72, WEST, lpass_slimbus, spkr_i2s, blsp9_spi, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(73, WEST, btfm_slimbus, phase_flag0, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(74, WEST, btfm_slimbus, ter_mi2s, phase_flag7, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(75, WEST, ter_mi2s, phase_flag8, qdss_gpio8, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(76, WEST, ter_mi2s, phase_flag9, qdss_gpio9, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(77, WEST, ter_mi2s, phase_flag4, qdss_gpio10, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(78, WEST, ter_mi2s, gcc_gp1_b, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(79, WEST, sec_mi2s, NA, qdss_gpio11, NA, NA, NA, NA, NA, NA),
+ PINGROUP(80, WEST, sec_mi2s, NA, qdss_gpio12, NA, NA, NA, NA, NA, NA),
+ PINGROUP(81, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b,
+ gcc_gp2_b, NA, NA, NA, NA),
+ PINGROUP(82, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_uim9_b,
+ gcc_gp3_b, NA, NA, NA, NA),
+ PINGROUP(83, WEST, sec_mi2s, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA,
+ NA, NA, NA, NA),
+ PINGROUP(84, WEST, blsp_spi12, blsp_uart9_b, blsp_i2c12, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(85, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(86, EAST, blsp_spi5, blsp_uart2_b, blsp_uim2_b, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(87, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(88, EAST, blsp_spi5, blsp_uart2_b, blsp_i2c5, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(89, EAST, tsif1_clk, phase_flag10, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(90, EAST, tsif1_en, mdp_vsync0, mdp_vsync1, mdp_vsync2,
+ mdp_vsync3, blsp1_spi, tgu_ch0, qdss_cti1_b, NA),
+ PINGROUP(91, EAST, tsif1_data, sdc4_cmd, tgu_ch1, phase_flag1,
+ qdss_cti1_b, NA, NA, NA, NA),
+ PINGROUP(92, EAST, tsif2_error, sdc43, vfr_1, phase_flag2, NA, NA, NA,
+ NA, NA),
+ PINGROUP(93, EAST, tsif2_clk, sdc4_clk, NA, qdss_gpio13, NA, NA, NA,
+ NA, NA),
+ PINGROUP(94, EAST, tsif2_en, sdc42, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(95, EAST, tsif2_data, sdc41, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(96, EAST, tsif2_sync, sdc40, phase_flag3, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(97, WEST, NA, mdp_vsync_b, ldo_en, NA, NA, NA, NA, NA, NA),
+ PINGROUP(98, WEST, NA, mdp_vsync_b, ldo_update, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(99, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(100, WEST, NA, NA, blsp_uart8, NA, NA, NA, NA, NA, NA),
+ PINGROUP(101, WEST, NA, blsp_uart8, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(102, WEST, NA, blsp11_i2c, prng_rosc, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(103, WEST, NA, blsp11_i2c, phase_flag5, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(104, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(105, NORTH, uim2_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(106, NORTH, uim2_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(107, NORTH, uim2_reset, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(108, NORTH, uim2_present, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(109, NORTH, uim1_data, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(110, NORTH, uim1_clk, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(111, NORTH, uim1_reset, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(112, NORTH, uim1_present, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(113, NORTH, uim_batt, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(114, WEST, NA, NA, phase_flag16, NA, NA, NA, NA, NA, NA),
+ PINGROUP(115, WEST, NA, nav_dr, phase_flag11, NA, NA, NA, NA, NA, NA),
+ PINGROUP(116, WEST, phase_flag12, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(117, EAST, phase_flag13, qdss_gpio0, atest_char, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(118, EAST, adsp_ext, phase_flag17, qdss_gpio1, atest_char3,
+ NA, NA, NA, NA, NA),
+ PINGROUP(119, EAST, phase_flag18, qdss_gpio2, atest_char2, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(120, EAST, phase_flag19, qdss_gpio3, atest_char1, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(121, EAST, phase_flag20, qdss_gpio4, atest_char0, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(122, EAST, phase_flag21, qdss_gpio5, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(123, EAST, phase_flag22, qdss_gpio, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(124, EAST, phase_flag23, qdss_gpio, NA, NA, NA, NA, NA, NA,
+ NA),
+ PINGROUP(125, EAST, phase_flag24, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(126, EAST, phase_flag25, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(127, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(128, WEST, modem_tsync, nav_pps, phase_flag26, NA, NA, NA,
+ NA, NA, NA),
+ PINGROUP(129, WEST, phase_flag27, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(130, NORTH, qlink_request, phase_flag28, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(131, NORTH, qlink_enable, phase_flag6, NA, NA, NA, NA, NA,
+ NA, NA),
+ PINGROUP(132, WEST, NA, phase_flag29, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(133, WEST, phase_flag30, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(134, WEST, phase_flag31, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(135, WEST, NA, pa_indicator, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(136, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(137, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(138, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(139, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(140, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(141, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(142, WEST, NA, ssbi1, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(143, WEST, isense_dbg, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(144, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(145, WEST, mss_lte, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(146, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(147, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(148, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ PINGROUP(149, WEST, NA, NA, NA, NA, NA, NA, NA, NA, NA),
+ SDC_QDSD_PINGROUP(sdc2_clk, 0x999000, 14, 6),
+ SDC_QDSD_PINGROUP(sdc2_cmd, 0x999000, 11, 3),
+ SDC_QDSD_PINGROUP(sdc2_data, 0x999000, 9, 0),
+ UFS_RESET(ufs_reset, 0x19d000),
+};
+
+static const struct msm_pinctrl_soc_data msm8998_pinctrl = {
+ .pins = msm8998_pins,
+ .npins = ARRAY_SIZE(msm8998_pins),
+ .functions = msm8998_functions,
+ .nfunctions = ARRAY_SIZE(msm8998_functions),
+ .groups = msm8998_groups,
+ .ngroups = ARRAY_SIZE(msm8998_groups),
+ .ngpios = 153,
+};
+
+static int msm8998_pinctrl_probe(struct platform_device *pdev)
+{
+ return msm_pinctrl_probe(pdev, &msm8998_pinctrl);
+}
+
+static const struct of_device_id msm8998_pinctrl_of_match[] = {
+ { .compatible = "qcom,msm8998-pinctrl", },
+ { },
+};
+
+static struct platform_driver msm8998_pinctrl_driver = {
+ .driver = {
+ .name = "msm8998-pinctrl",
+ .owner = THIS_MODULE,
+ .of_match_table = msm8998_pinctrl_of_match,
+ },
+ .probe = msm8998_pinctrl_probe,
+ .remove = msm_pinctrl_remove,
+};
+
+static int __init msm8998_pinctrl_init(void)
+{
+ return platform_driver_register(&msm8998_pinctrl_driver);
+}
+arch_initcall(msm8998_pinctrl_init);
+
+static void __exit msm8998_pinctrl_exit(void)
+{
+ platform_driver_unregister(&msm8998_pinctrl_driver);
+}
+module_exit(msm8998_pinctrl_exit);
+
+MODULE_DESCRIPTION("QTI msm8998 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, msm8998_pinctrl_of_match);
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
^ permalink raw reply related
* Re: [PATCH 3/3] ARM: dts: stm32: enable ADC on stm32f429i-eval board
From: Alexandre Torgue @ 2017-01-09 14:48 UTC (permalink / raw)
To: Fabrice GASNIER, mcoquelin.stm32@gmail.com, linux@armlinux.org.uk,
mark.rutland@arm.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1480687022-12851-4-git-send-email-fabrice.gasnier@st.com>
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
> Enable analog to digital converter on stm32f429i-eval board.
> It has on-board potentimeter wired to ADC3 in8 analog pin and
> uses fixed regulator to provide reference voltage.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> arch/arm/boot/dts/stm32429i-eval.dts | 25 +++++++++++++++++++++++++
> 1 file changed, 25 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts
> index 13c7cd2..6be0a24 100644
> --- a/arch/arm/boot/dts/stm32429i-eval.dts
> +++ b/arch/arm/boot/dts/stm32429i-eval.dts
> @@ -65,6 +65,20 @@
> serial0 = &usart1;
> };
>
> + regulators {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg_vref: regulator@0 {
> + compatible = "regulator-fixed";
> + reg = <0>;
> + regulator-name = "vref";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + };
> + };
> +
> leds {
> compatible = "gpio-leds";
> green {
> @@ -123,3 +137,14 @@
> pinctrl-names = "default";
> status = "okay";
> };
> +
> +&adc {
> + pinctrl-names = "default";
> + pinctrl-0 = <&adc3_in8_pin>;
> + vref-supply = <®_vref>;
> + status = "okay";
> + adc3: adc@200 {
> + st,adc-channels = <8>;
> + status = "okay";
> + };
> +};
>
After node reordering:
Applied on stm32-dt-for-v4.11
Thanks
Alex
^ permalink raw reply
* Re: [PATCH 1/6] drivers: pinctrl: add driver for Allwinner H5 SoC
From: Linus Walleij @ 2017-01-09 14:47 UTC (permalink / raw)
To: Maxime Ripard
Cc: Icenowy Zheng, Chen-Yu Tsai, Rob Herring, Andre Przywara,
linux-sunxi, linux-gpio-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-clk
In-Reply-To: <20170105220823.5ai4yvcblmzmaey2@lukather>
On Thu, Jan 5, 2017 at 11:08 PM, Maxime Ripard
<maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org> wrote:
> On Tue, Dec 27, 2016 at 12:25:13AM +0800, Icenowy Zheng wrote:
>> +builtin_platform_driver(sun50i_h5_pinctrl_driver);
>
> This also looks very much like the H3. I'll post a patchset during the
> weekend to avoid duplicating those drivers. This was initially done
> for the sun5i, but it very much applies here.
I have applied Maxime's patch set from today.
Icenowy, please investigate the direction taken by Maxime
here for future revisions if needed.
Yours,
Linus Walleij
^ permalink raw reply
* Re: [PATCH 2/3] ARM: dts: stm32: Add ADC support to stm32f429
From: Alexandre Torgue @ 2017-01-09 14:46 UTC (permalink / raw)
To: Fabrice GASNIER, mcoquelin.stm32@gmail.com, linux@armlinux.org.uk,
mark.rutland@arm.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1480687022-12851-3-git-send-email-fabrice.gasnier@st.com>
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
> Add ADC support & pinctrl analog phandle (adc3_in8) to stm32f429.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> arch/arm/boot/dts/stm32f429.dtsi | 49 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi
> index 3dd47eb..be1d970 100644
> --- a/arch/arm/boot/dts/stm32f429.dtsi
> +++ b/arch/arm/boot/dts/stm32f429.dtsi
> @@ -172,6 +172,49 @@
> status = "disabled";
> };
>
> + adc: adc@40012000 {
> + compatible = "st,stm32f4-adc-core";
> + reg = <0x40012000 0x400>;
> + interrupts = <18>;
> + clocks = <&rcc 0 168>;
> + clock-names = "adc";
> + interrupt-controller;
> + #interrupt-cells = <1>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + adc1: adc@0 {
> + compatible = "st,stm32f4-adc";
> + #io-channel-cells = <1>;
> + reg = <0x0>;
> + clocks = <&rcc 0 168>;
> + interrupt-parent = <&adc>;
> + interrupts = <0>;
> + status = "disabled";
> + };
> +
> + adc2: adc@100 {
> + compatible = "st,stm32f4-adc";
> + #io-channel-cells = <1>;
> + reg = <0x100>;
> + clocks = <&rcc 0 169>;
> + interrupt-parent = <&adc>;
> + interrupts = <1>;
> + status = "disabled";
> + };
> +
> + adc3: adc@200 {
> + compatible = "st,stm32f4-adc";
> + #io-channel-cells = <1>;
> + reg = <0x200>;
> + clocks = <&rcc 0 170>;
> + interrupt-parent = <&adc>;
> + interrupts = <2>;
> + status = "disabled";
> + };
> + };
> +
> syscfg: system-config@40013800 {
> compatible = "syscon";
> reg = <0x40013800 0x400>;
> @@ -334,6 +377,12 @@
> slew-rate = <2>;
> };
> };
> +
> + adc3_in8_pin: adc@200 {
> + pins {
> + pinmux = <STM32F429_PF10_FUNC_ANALOG>;
> + };
> + };
> };
>
> rcc: rcc@40023810 {
>
Applied on stm32-dt-for-v4.11
Thanks
Alex
^ permalink raw reply
* Re: [PATCH 1/3] ARM: configs: stm32: enable ADC driver
From: Alexandre Torgue @ 2017-01-09 14:46 UTC (permalink / raw)
To: Fabrice GASNIER, mcoquelin.stm32@gmail.com, linux@armlinux.org.uk,
mark.rutland@arm.com, robh+dt@kernel.org
Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
In-Reply-To: <1480687022-12851-2-git-send-email-fabrice.gasnier@st.com>
Hi Fabrice
On 12/02/2016 02:57 PM, Fabrice GASNIER wrote:
> ADC driver depends on REGULATOR and IIO that are not yet selected.
> Current hardware boards (like stm32f429i-eval) is using fixed
> regulators.
>
> Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
> ---
> arch/arm/configs/stm32_defconfig | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/arm/configs/stm32_defconfig b/arch/arm/configs/stm32_defconfig
> index a60b5cb..92ccc3c 100644
> --- a/arch/arm/configs/stm32_defconfig
> +++ b/arch/arm/configs/stm32_defconfig
> @@ -49,6 +49,8 @@ CONFIG_SERIAL_STM32=y
> CONFIG_SERIAL_STM32_CONSOLE=y
> # CONFIG_HW_RANDOM is not set
> # CONFIG_HWMON is not set
> +CONFIG_REGULATOR=y
> +CONFIG_REGULATOR_FIXED_VOLTAGE=y
> # CONFIG_USB_SUPPORT is not set
> CONFIG_NEW_LEDS=y
> CONFIG_LEDS_CLASS=y
> @@ -57,6 +59,9 @@ CONFIG_LEDS_TRIGGERS=y
> CONFIG_LEDS_TRIGGER_HEARTBEAT=y
> CONFIG_DMADEVICES=y
> CONFIG_STM32_DMA=y
> +CONFIG_IIO=y
> +CONFIG_STM32_ADC_CORE=y
> +CONFIG_STM32_ADC=y
> # CONFIG_FILE_LOCKING is not set
> # CONFIG_DNOTIFY is not set
> # CONFIG_INOTIFY_USER is not set
>
Applied on stm32-defconfig-for-v4.11
Thanks.
Alex
^ permalink raw reply
* RE: [PATCH v2 6/7] dt-bindings: media: Add Renesas R-Car DRIF binding
From: Ramesh Shanmugasundaram @ 2017-01-09 14:42 UTC (permalink / raw)
To: Hans Verkuil, Geert Uytterhoeven, Laurent Pinchart
Cc: Rob Herring, Mark Rutland, Mauro Carvalho Chehab, Sakari Ailus,
Antti Palosaari, Chris Paterson, Geert Uytterhoeven,
Linux Media Mailing List, devicetree@vger.kernel.org,
Linux-Renesas
In-Reply-To: <cca1ade8-01ef-8eab-f4b1-7dd7f204fdea@xs4all.nl>
Hi Hans,
Thanks for the review.
> >>> On Wednesday 21 Dec 2016 08:10:37 Ramesh Shanmugasundaram wrote:
> >>>> Add binding documentation for Renesas R-Car Digital Radio Interface
> >>>> (DRIF) controller.
> >>>>
> >>>> Signed-off-by: Ramesh Shanmugasundaram
> >>>> <ramesh.shanmugasundaram@bp.renesas.com> ---
> >>>> .../devicetree/bindings/media/renesas,drif.txt | 202
> >> ++++++++++++++++++
> >>>> 1 file changed, 202 insertions(+)
> >>>> create mode 100644
> >>>> Documentation/devicetree/bindings/media/renesas,drif.txt
> >>>>
> >>>> diff --git
> >>>> a/Documentation/devicetree/bindings/media/renesas,drif.txt
> >>>> b/Documentation/devicetree/bindings/media/renesas,drif.txt new file
> >>>> mode
> >>>> 100644
> >>>> index 0000000..1f3feaf
> >>>> --- /dev/null
> >>>> +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
> >>
> >>>> +Optional properties of an internal channel when:
> >>>> + - It is the only enabled channel of the bond (or)
> >>>> + - If it acts as primary among enabled bonds
> >>>> +--------------------------------------------------------
> >>>> +- renesas,syncmd : sync mode
> >>>> + 0 (Frame start sync pulse mode. 1-bit width
> >> pulse
> >>>> + indicates start of a frame)
> >>>> + 1 (L/R sync or I2S mode) (default)
> >>>> +- renesas,lsb-first : empty property indicates lsb bit is
> received
> >>>> first.
> >>>> + When not defined msb bit is received first
> >>>> +(default)
> >>>> +- renesas,syncac-active: Indicates sync signal polarity, 0/1 for
> >> low/high
>
> Shouldn't this be 'renesas,sync-active' instead of syncac-active?
>
> I'm not sure if syncac is intended or if it is a typo.
Yes, "syncac" is intended. I kept the same name as in h/w manual for easy reference. Same for other properties - syncmd, dtdl & syncdl.
>
> >>>> + respectively. The default is 1 (active high)
> >>>> +- renesas,dtdl : delay between sync signal and start of
> >> reception.
> >>>> + The possible values are represented in 0.5
> clock
> >>>> + cycle units and the range is 0 to 4. The
> default
> >>>> + value is 2 (i.e.) 1 clock cycle delay.
> >>>> +- renesas,syncdl : delay between end of reception and sync
> >> signal
> >>>> edge.
> >>>> + The possible values are represented in 0.5
> clock
> >>>> + cycle units and the range is 0 to 4 & 6. The
> >> default
> >>>> + value is 0 (i.e.) no delay.
> >>>
> >>> Most of these properties are pretty similar to the video bus
> >>> properties defined at the endpoint level in
> >>> Documentation/devicetree/bindings/media/video-interfaces.txt. I
> >>> believe it would make sense to use OF graph and try to standardize
> >>> these properties similarly.
>
> Other than sync-active, is there really anything else that is similar? And
> even the sync-active isn't a good fit since here there is only one sync
> signal instead of two for video (h and vsync).
>
> Regards,
>
> Hans
>
Thanks,
Ramesh
^ permalink raw reply
* Re: [PATCH 01/10] doc: DT: camss: Binding document for Qualcomm Camera subsystem driver
From: Todor Tomov @ 2017-01-09 14:33 UTC (permalink / raw)
To: Rob Herring
Cc: mchehab-DgEjT+Ai2ygdnm+yROfE0A,
laurent.pinchart+renesas-ryLnwIuWjnjg/C1BVhZhaw,
hans.verkuil-FYB4Gu1CFyUAvxtiuMwx3w,
javier-JPH+aEBZ4P+UEJcrhfAQsw, s.nawrocki-Sze3O3UU22JBDgjK7y7TUQ,
linux-media-u79uwXL29TY76Z2rM5mHXA,
linux-kernel-u79uwXL29TY76Z2rM5mHXA, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA,
bjorn.andersson-QSEj5FYQhm4dnm+yROfE0A,
srinivas.kandagatla-QSEj5FYQhm4dnm+yROfE0A
In-Reply-To: <20161130220350.q37rbo2biaeg2sad@rob-hp-laptop>
Hi Rob,
Happy new year,
And thank you for the review.
On 12/01/2016 12:03 AM, Rob Herring wrote:
> On Fri, Nov 25, 2016 at 04:56:53PM +0200, Todor Tomov wrote:
>> Add DT binding document for Qualcomm Camera subsystem driver.
>>
>> Signed-off-by: Todor Tomov <todor.tomov-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>
>> ---
>> .../devicetree/bindings/media/qcom,camss.txt | 196 +++++++++++++++++++++
>> 1 file changed, 196 insertions(+)
>> create mode 100644 Documentation/devicetree/bindings/media/qcom,camss.txt
>>
>> diff --git a/Documentation/devicetree/bindings/media/qcom,camss.txt b/Documentation/devicetree/bindings/media/qcom,camss.txt
>> new file mode 100644
>> index 0000000..76ad89a
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/media/qcom,camss.txt
>> @@ -0,0 +1,196 @@
>> +Qualcomm Camera Subsystem
>> +
>> +* Properties
>> +
>> +- compatible:
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Should contain:
>> + - "qcom,8x16-camss"
>
> Don't use wildcards in compatible strings. One string per SoC.
Ok, I'll fix this.
>
>> +- reg:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: Register ranges as listed in the reg-names property.
>> +- reg-names:
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Should contain the following entries:
>> + - "csiphy0"
>> + - "csiphy0_clk_mux"
>> + - "csiphy1"
>> + - "csiphy1_clk_mux"
>> + - "csid0"
>> + - "csid1"
>> + - "ispif"
>> + - "csi_clk_mux"
>> + - "vfe0"
>
> Kind of looks like the phy's should be separate nodes since each phy has
> its own register range, irq, clocks, etc.
Yes, there are a lot of hardware resources here.
I have decided to keep everything into a single platform device as this
represents it better from system point of view.
>
>> +- interrupts:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: Interrupts as listed in the interrupt-names property.
>> +- interrupt-names:
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Should contain the following entries:
>> + - "csiphy0"
>> + - "csiphy1"
>> + - "csid0"
>> + - "csid1"
>> + - "ispif"
>> + - "vfe0"
>> +- power-domains:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: A phandle and power domain specifier pairs to the
>> + power domain which is responsible for collapsing
>> + and restoring power to the peripheral.
>> +- clocks:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: A list of phandle and clock specifier pairs as listed
>> + in clock-names property.
>> +- clock-names:
>> + Usage: required
>> + Value type: <stringlist>
>> + Definition: Should contain the following entries:
>> + - "camss_top_ahb_clk"
>> + - "ispif_ahb_clk"
>> + - "csiphy0_timer_clk"
>> + - "csiphy1_timer_clk"
>> + - "csi0_ahb_clk"
>> + - "csi0_clk"
>> + - "csi0_phy_clk"
>> + - "csi0_pix_clk"
>> + - "csi0_rdi_clk"
>> + - "csi1_ahb_clk"
>> + - "csi1_clk"
>> + - "csi1_phy_clk"
>> + - "csi1_pix_clk"
>> + - "csi1_rdi_clk"
>> + - "camss_ahb_clk"
>> + - "camss_vfe_vfe_clk"
>> + - "camss_csi_vfe_clk"
>> + - "iface_clk"
>> + - "bus_clk"
>> +- vdda-supply:
>> + Usage: required
>> + Value type: <phandle>
>> + Definition: A phandle to voltage supply for CSI2.
>> +- iommus:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: A list of phandle and IOMMU specifier pairs.
>> +
>> +* Nodes
>> +
>> +- ports:
>> + Usage: required
>> + Definition: As described in video-interfaces.txt in same directory.
>> + Properties:
>> + - reg:
>> + Usage: required
>> + Value type: <u32>
>> + Definition: Selects CSI2 PHY interface - PHY0 or PHY1.
>> + Endpoint node properties:
>> + - clock-lanes:
>> + Usage: required
>> + Value type: <u32>
>> + Definition: The clock lane.
>> + - data-lanes:
>> + Usage: required
>> + Value type: <prop-encoded-array>
>> + Definition: An array of data lanes.
>> + - qcom,settle-cnt:
>
> This should go in phy node ideally.
>
>> + Usage: required
>> + Value type: <u32>
>> + Definition: The settle count parameter for CSI PHY.
>> +
>> +* An Example
>> +
>> + camss: camss@1b00000 {
>> + compatible = "qcom,8x16-camss";
>> + reg = <0x1b0ac00 0x200>,
>> + <0x1b00030 0x4>,
>> + <0x1b0b000 0x200>,
>> + <0x1b00038 0x4>,
>> + <0x1b08000 0x100>,
>> + <0x1b08400 0x100>,
>> + <0x1b0a000 0x500>,
>> + <0x1b00020 0x10>,
>> + <0x1b10000 0x1000>;
>> + reg-names = "csiphy0",
>> + "csiphy0_clk_mux",
>> + "csiphy1",
>> + "csiphy1_clk_mux",
>> + "csid0",
>> + "csid1",
>> + "ispif",
>> + "csi_clk_mux",
>> + "vfe0";
>> + interrupts = <GIC_SPI 78 0>,
>> + <GIC_SPI 79 0>,
>> + <GIC_SPI 51 0>,
>> + <GIC_SPI 52 0>,
>> + <GIC_SPI 55 0>,
>> + <GIC_SPI 57 0>;
>> + interrupt-names = "csiphy0",
>> + "csiphy1",
>> + "csid0",
>> + "csid1",
>> + "ispif",
>> + "vfe0";
>> + power-domains = <&gcc VFE_GDSC>;
>> + clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
>> + <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
>> + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
>> + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
>> + <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
>> + <&gcc GCC_CAMSS_CSI0_CLK>,
>> + <&gcc GCC_CAMSS_CSI0PHY_CLK>,
>> + <&gcc GCC_CAMSS_CSI0PIX_CLK>,
>> + <&gcc GCC_CAMSS_CSI0RDI_CLK>,
>> + <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
>> + <&gcc GCC_CAMSS_CSI1_CLK>,
>> + <&gcc GCC_CAMSS_CSI1PHY_CLK>,
>> + <&gcc GCC_CAMSS_CSI1PIX_CLK>,
>> + <&gcc GCC_CAMSS_CSI1RDI_CLK>,
>> + <&gcc GCC_CAMSS_AHB_CLK>,
>> + <&gcc GCC_CAMSS_VFE0_CLK>,
>> + <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
>> + <&gcc GCC_CAMSS_VFE_AHB_CLK>,
>> + <&gcc GCC_CAMSS_VFE_AXI_CLK>;
>> + clock-names = "camss_top_ahb_clk",
>> + "ispif_ahb_clk",
>> + "csiphy0_timer_clk",
>> + "csiphy1_timer_clk",
>> + "csi0_ahb_clk",
>> + "csi0_clk",
>> + "csi0_phy_clk",
>> + "csi0_pix_clk",
>> + "csi0_rdi_clk",
>> + "csi1_ahb_clk",
>> + "csi1_clk",
>> + "csi1_phy_clk",
>> + "csi1_pix_clk",
>> + "csi1_rdi_clk",
>> + "camss_ahb_clk",
>> + "camss_vfe_vfe_clk",
>> + "camss_csi_vfe_clk",
>> + "iface_clk",
>> + "bus_clk";
>> + vdda-supply = <&pm8916_l2>;
>> + iommus = <&apps_iommu 3>;
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> + port@0 {
>> + reg = <0>;
>> + csiphy0_ep: endpoint {
>> + clock-lanes = <1>;
>> + data-lanes = <0 2>;
>> + qcom,settle-cnt = <0xe>;
>> + remote-endpoint = <&ov5645_ep>;
>> + };
>> + };
>> + };
>> + };
>> --
>> 1.9.1
>>
--
Best regards,
Todor Tomov
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^ permalink raw reply
* Re: [PATCH V2 4/5] PCI: exynos: support the using PHY generic framework
From: Alim Akhtar @ 2017-01-09 13:39 UTC (permalink / raw)
To: Jaehoon Chung, linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, cpgs
In-Reply-To: <20170104123435.30740-5-jh80.chung@samsung.com>
Hi Jaehoon,
On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
> This patch is for using PHY generic framework.
> To maintain backward compatibility, check whether phy is supported or
> not with 'using_phy'.
>
> And if someone use the old dt-file, display the "deprecated" message.
> But it's still working fine with it.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> Changelog on V2:
> - This patch is split from previous PATCH[1/4]
> - Maintain the backward compatibility
> - Adds 'using_phy' for cheching whether phy framework is used or not
> - Adds 'DEPRECATED' message for old dt-binding way
>
> drivers/pci/host/pci-exynos.c | 61 +++++++++++++++++++++++++++++++++++--------
> 1 file changed, 50 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/pci/host/pci-exynos.c b/drivers/pci/host/pci-exynos.c
> index feed0fd..34f2eed 100644
> --- a/drivers/pci/host/pci-exynos.c
> +++ b/drivers/pci/host/pci-exynos.c
> @@ -21,6 +21,7 @@
> #include <linux/of_gpio.h>
> #include <linux/pci.h>
> #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> #include <linux/resource.h>
> #include <linux/signal.h>
> #include <linux/types.h>
> @@ -110,6 +111,10 @@ struct exynos_pcie {
> struct exynos_pcie_clk_res *clk_res;
> const struct exynos_pcie_ops *ops;
> int reset_gpio;
> +
> + /* For Generic PHY Framework */
> + bool using_phy;
> + struct phy *phy;
> };
>
> struct exynos_pcie_ops {
> @@ -135,6 +140,10 @@ static int exynos5440_pcie_get_mem_resources(struct platform_device *pdev,
> if (IS_ERR(ep->mem_res->elbi_base))
> return PTR_ERR(ep->mem_res->elbi_base);
>
> + /* If using the PHY framework, doesn't need to get other resource */
> + if (ep->using_phy)
> + return 0;
> +
> res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> ep->mem_res->phy_base = devm_ioremap_resource(dev, res);
> if (IS_ERR(ep->mem_res->phy_base))
> @@ -396,17 +405,28 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
> }
>
> exynos_pcie_assert_core_reset(exynos_pcie);
> - exynos_pcie_assert_phy_reset(exynos_pcie);
> - exynos_pcie_deassert_phy_reset(exynos_pcie);
> - exynos_pcie_power_on_phy(exynos_pcie);
> - exynos_pcie_init_phy(exynos_pcie);
> -
> - /* pulse for common reset */
> - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> - PCIE_PHY_COMMON_RESET);
> - udelay(500);
> - exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> - PCIE_PHY_COMMON_RESET);
> +
> + if (exynos_pcie->using_phy) {
> + phy_reset(exynos_pcie->phy);
> +
> + exynos_pcie_writel(exynos_pcie->mem_res->elbi_base, 1,
> + PCIE_PWR_RESET);
> +
> + phy_power_on(exynos_pcie->phy);
> + phy_init(exynos_pcie->phy);
> + } else {
> + exynos_pcie_assert_phy_reset(exynos_pcie);
> + exynos_pcie_deassert_phy_reset(exynos_pcie);
> + exynos_pcie_power_on_phy(exynos_pcie);
> + exynos_pcie_init_phy(exynos_pcie);
> +
> + /* pulse for common reset */
> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 1,
> + PCIE_PHY_COMMON_RESET);
> + udelay(500);
> + exynos_pcie_writel(exynos_pcie->mem_res->block_base, 0,
> + PCIE_PHY_COMMON_RESET);
> + }
>
> exynos_pcie_deassert_core_reset(exynos_pcie);
> dw_pcie_setup_rc(pp);
> @@ -420,6 +440,11 @@ static int exynos_pcie_establish_link(struct exynos_pcie *exynos_pcie)
> if (!dw_pcie_wait_for_link(pp))
> return 0;
>
> + if (exynos_pcie->using_phy) {
> + phy_power_off(exynos_pcie->phy);
> + return -ETIMEDOUT;
> + }
> +
> while (exynos_pcie_readl(exynos_pcie->mem_res->phy_base,
> PCIE_PHY_PLL_LOCKED) == 0) {
> val = exynos_pcie_readl(exynos_pcie->mem_res->block_base,
> @@ -633,6 +658,17 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
>
> exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0);
>
> + /* Assume that controller doesn't use the PHY framework */
> + exynos_pcie->using_phy = false;
> +
> + exynos_pcie->phy = devm_of_phy_get(dev, np, NULL);
> + if (IS_ERR(exynos_pcie->phy)) {
> + if (PTR_ERR(exynos_pcie->phy) == -EPROBE_DEFER)
> + return PTR_ERR(exynos_pcie->phy);
> + dev_warn(dev, "Use the 'phy' property. Current DT of pci-exynos was deprecated!!\n");
> + } else
> + exynos_pcie->using_phy = true;
> +
> if (exynos_pcie->ops && exynos_pcie->ops->get_mem_resources) {
> ret = exynos_pcie->ops->get_mem_resources(pdev, exynos_pcie);
> if (ret)
> @@ -657,6 +693,9 @@ static int __init exynos_pcie_probe(struct platform_device *pdev)
> return 0;
>
> fail_probe:
> + if (exynos_pcie->using_phy)
> + phy_exit(exynos_pcie->phy);
> +
> if (exynos_pcie->ops && exynos_pcie->ops->deinit_clk_resources)
> exynos_pcie->ops->deinit_clk_resources(exynos_pcie);
> return ret;
>
^ permalink raw reply
* Re: [PATCH v2 6/7] dt-bindings: media: Add Renesas R-Car DRIF binding
From: Hans Verkuil @ 2017-01-09 13:36 UTC (permalink / raw)
To: Ramesh Shanmugasundaram, Geert Uytterhoeven, Laurent Pinchart
Cc: Rob Herring, Mark Rutland, Mauro Carvalho Chehab, Sakari Ailus,
Antti Palosaari, Chris Paterson, Geert Uytterhoeven,
Linux Media Mailing List, devicetree@vger.kernel.org,
Linux-Renesas
In-Reply-To: <HK2PR06MB05453E11C8931F881E106939C36E0@HK2PR06MB0545.apcprd06.prod.outlook.com>
On 01/03/2017 04:20 PM, Ramesh Shanmugasundaram wrote:
> Hi Laurent, Geert,
>
> Thanks for the review comments.
>
>>> On Wednesday 21 Dec 2016 08:10:37 Ramesh Shanmugasundaram wrote:
>>>> Add binding documentation for Renesas R-Car Digital Radio Interface
>>>> (DRIF) controller.
>>>>
>>>> Signed-off-by: Ramesh Shanmugasundaram
>>>> <ramesh.shanmugasundaram@bp.renesas.com> ---
>>>> .../devicetree/bindings/media/renesas,drif.txt | 202
>> ++++++++++++++++++
>>>> 1 file changed, 202 insertions(+)
>>>> create mode 100644
>>>> Documentation/devicetree/bindings/media/renesas,drif.txt
>>>>
>>>> diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt
>>>> b/Documentation/devicetree/bindings/media/renesas,drif.txt new file
>>>> mode
>>>> 100644
>>>> index 0000000..1f3feaf
>>>> --- /dev/null
>>>> +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt
>>
>>>> +Optional properties of an internal channel when:
>>>> + - It is the only enabled channel of the bond (or)
>>>> + - If it acts as primary among enabled bonds
>>>> +--------------------------------------------------------
>>>> +- renesas,syncmd : sync mode
>>>> + 0 (Frame start sync pulse mode. 1-bit width
>> pulse
>>>> + indicates start of a frame)
>>>> + 1 (L/R sync or I2S mode) (default)
>>>> +- renesas,lsb-first : empty property indicates lsb bit is received
>>>> first.
>>>> + When not defined msb bit is received first
>>>> +(default)
>>>> +- renesas,syncac-active: Indicates sync signal polarity, 0/1 for
>> low/high
Shouldn't this be 'renesas,sync-active' instead of syncac-active?
I'm not sure if syncac is intended or if it is a typo.
>>>> + respectively. The default is 1 (active high)
>>>> +- renesas,dtdl : delay between sync signal and start of
>> reception.
>>>> + The possible values are represented in 0.5 clock
>>>> + cycle units and the range is 0 to 4. The default
>>>> + value is 2 (i.e.) 1 clock cycle delay.
>>>> +- renesas,syncdl : delay between end of reception and sync
>> signal
>>>> edge.
>>>> + The possible values are represented in 0.5 clock
>>>> + cycle units and the range is 0 to 4 & 6. The
>> default
>>>> + value is 0 (i.e.) no delay.
>>>
>>> Most of these properties are pretty similar to the video bus
>>> properties defined at the endpoint level in
>>> Documentation/devicetree/bindings/media/video-interfaces.txt. I
>>> believe it would make sense to use OF graph and try to standardize
>>> these properties similarly.
Other than sync-active, is there really anything else that is similar? And
even the sync-active isn't a good fit since here there is only one sync
signal instead of two for video (h and vsync).
Regards,
Hans
>> Note that the last two properties match the those in
>> Documentation/devicetree/bindings/spi/sh-msiof.txt.
>> We may want to use one DRIF channel as a plain SPI slave with the
>> (modified) MSIOF driver in the future.
>
> Should I leave it as it is or modify these as in video-interfaces.txt? Shall we conclude on this please?
>
> Thanks,
> Ramesh
> N�����r��y���b�X��ǧv�^�){.n�+����{���bj)���w*\x1fjg���\x1e�����ݢj/���z�ޖ��2�ޙ���&�)ߡ�a��\x7f��\x1e�G���h�\x0f�j:+v���w�٥
>
^ permalink raw reply
* Re: [PATCH V2 3/5] Documetation: binding: modify the exynos5440 pcie binding
From: Alim Akhtar @ 2017-01-09 13:36 UTC (permalink / raw)
To: Jaehoon Chung, linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, cpgs
In-Reply-To: <20170104123435.30740-4-jh80.chung@samsung.com>
Hi Jaehoon,
On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
> According to using PHY framework, updates the exynos5440-pcie binding.
> For maintaining backward compatibility, leaves the current dt-binding.
> (It should be deprecated.)
>
> Recommends to use the Phy Framework and "config" property to follow
> the designware-pcie binding.
> If you use the old way, can see "mssing *config* reg space" message.
> Because the getting configuration space address from range is old way.
>
> NOTE: When use the "config" property, first name of 'reg-names' must be
> set to "elbi". Otherwise driver can't maintain the backward capability.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
> Changelog on V2:
> - Describes more commit message
> - Fixes the typos
> - Adds the new example for using PHY framework
> - Deprecated the old dt-binding description
> - Removes 'phy-names'
>
> .../bindings/pci/samsung,exynos5440-pcie.txt | 29 ++++++++++++++++++++++
> 1 file changed, 29 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> index 4f9d23d..1d0af0e 100644
> --- a/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> +++ b/Documentation/devicetree/bindings/pci/samsung,exynos5440-pcie.txt
> @@ -7,8 +7,19 @@ Required properties:
> - compatible: "samsung,exynos5440-pcie"
> - reg: base addresses and lengths of the pcie controller,
> the phy controller, additional register for the phy controller.
> + (Registers for the phy controller are DEPRECATED.
> + Use the PHY framework.)
> +- reg-names : First name should be set to "elbi".
> + And use the "config" instead of getting the confgiruation address space
> + from "ranges".
> + NOTE: When use the "config" property, reg-names must be set.
> - interrupts: A list of interrupt outputs for level interrupt,
> pulse interrupt, special interrupt.
> +- phys: From PHY binding. Phandle for the Generic PHY.
> + Refer to Documentation/devicetree/bindings/phy/samsung-phy.txt
> +
> +Other common properties refer to
> + Documentation/devicetree/binding/pci/designware-pcie.txt
>
> Example:
>
> @@ -54,6 +65,24 @@ SoC specific DT Entry:
> num-lanes = <4>;
> };
>
> +With using PHY framework:
> + pcie_phy0: pcie-phy@270000 {
> + ...
> + reg = <0x270000 0x1000>, <0x271000 0x40>;
> + regn-names = "phy", "block";
> + ...
> + };
> +
> + pcie@290000 {
> + ...
> + reg = <0x290000 0x1000>, <0x40000000 0x1000>;
> + reg-names = "elbi", "config";
> + phys = <&pcie_phy0>;
> + ranges = <0x81000000 0 0 0x60001000 0 0x00010000
> + 0x82000000 0 0x60011000 0x60011000 0 0x1ffef000>;
> + ...
> + };
> +
> Board specific DT Entry:
>
> pcie@290000 {
>
^ permalink raw reply
* Re: [PATCH V2 2/5] phy: phy-exynos-pcie: Add support for Exynos PCIe phy
From: Alim Akhtar @ 2017-01-09 13:34 UTC (permalink / raw)
To: Jaehoon Chung, linux-pci
Cc: devicetree, linux-kernel, linux-samsung-soc, bhelgaas, robh+dt,
mark.rutland, kgene, krzk, kishon, jingoohan1, vivek.gautam,
pankaj.dubey, cpgs
In-Reply-To: <20170104123435.30740-3-jh80.chung@samsung.com>
Hi,
On 01/04/2017 06:04 PM, Jaehoon Chung wrote:
> This patch supports to use Generic Phy framework for Exynos PCIe phy.
> When Exynos that supported the pcie want to use the PCIe,
> it needs to control the phy resgister.
> But it should be more complex to control in their own PCIe device drivers.
>
> Currently, there is an exynos5440 case to support the pcie.
> So this driver is based on Exynos5440 PCIe.
> In future, will support the Other exynos SoCs likes exynos5433, exynos7.
>
> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
> ---
> Changelog on V2:
> - Not include the codes relevant to pci-exynos.
> - Remove the getting child node.
>
> drivers/phy/Kconfig | 9 ++
> drivers/phy/Makefile | 1 +
> drivers/phy/phy-exynos-pcie.c | 280 ++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 290 insertions(+)
> create mode 100644 drivers/phy/phy-exynos-pcie.c
>
> diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
> index e8eb7f2..2dddef4 100644
> --- a/drivers/phy/Kconfig
> +++ b/drivers/phy/Kconfig
> @@ -331,6 +331,15 @@ config PHY_EXYNOS5_USBDRD
> This driver provides PHY interface for USB 3.0 DRD controller
> present on Exynos5 SoC series.
>
> +config PHY_EXYNOS_PCIE
> + bool "Exynos PCIe PHY driver"
> + depends on ARCH_EXYNOS && OF
Please add a depends on COMPILE_TEST as well.
Apart from this looks ok.
> + depends on PCI_EXYNOS
> + select GENERIC_PHY
> + help
> + Enable PCIe PHY support for Exynos SoC series.
> + This driver provides PHY interface for Exynos PCIe controller.
> +
> config PHY_PISTACHIO_USB
> tristate "IMG Pistachio USB2.0 PHY driver"
> depends on MACH_PISTACHIO
> diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
> index 65eb2f4..081aeb4 100644
> --- a/drivers/phy/Makefile
> +++ b/drivers/phy/Makefile
> @@ -37,6 +37,7 @@ phy-exynos-usb2-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o
> phy-exynos-usb2-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o
> obj-$(CONFIG_PHY_EXYNOS5_USBDRD) += phy-exynos5-usbdrd.o
> +obj-$(CONFIG_PHY_EXYNOS_PCIE) += phy-exynos-pcie.o
> obj-$(CONFIG_PHY_QCOM_APQ8064_SATA) += phy-qcom-apq8064-sata.o
> obj-$(CONFIG_PHY_ROCKCHIP_USB) += phy-rockchip-usb.o
> obj-$(CONFIG_PHY_ROCKCHIP_INNO_USB2) += phy-rockchip-inno-usb2.o
> diff --git a/drivers/phy/phy-exynos-pcie.c b/drivers/phy/phy-exynos-pcie.c
> new file mode 100644
> index 0000000..b57f49b
> --- /dev/null
> +++ b/drivers/phy/phy-exynos-pcie.c
> @@ -0,0 +1,280 @@
> +/*
> + * Samsung EXYNOS SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on Exynos SoC series
> + *
> + * Copyright (C) 2016 Samsung Electronics Co., Ltd.
> + * Jaehoon Chung <jh80.chung@samsung.com>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +
> +#include <linux/delay.h>
> +#include <linux/io.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> +#include <linux/regmap.h>
> +
> +/* PCIe Purple registers */
> +#define PCIE_PHY_GLOBAL_RESET 0x000
> +#define PCIE_PHY_COMMON_RESET 0x004
> +#define PCIE_PHY_CMN_REG 0x008
> +#define PCIE_PHY_MAC_RESET 0x00c
> +#define PCIE_PHY_PLL_LOCKED 0x010
> +#define PCIE_PHY_TRSVREG_RESET 0x020
> +#define PCIE_PHY_TRSV_RESET 0x024
> +
> +/* PCIe PHY registers */
> +#define PCIE_PHY_IMPEDANCE 0x004
> +#define PCIE_PHY_PLL_DIV_0 0x008
> +#define PCIE_PHY_PLL_BIAS 0x00c
> +#define PCIE_PHY_DCC_FEEDBACK 0x014
> +#define PCIE_PHY_PLL_DIV_1 0x05c
> +#define PCIE_PHY_COMMON_POWER 0x064
> +#define PCIE_PHY_COMMON_PD_CMN BIT(3)
> +#define PCIE_PHY_TRSV0_EMP_LVL 0x084
> +#define PCIE_PHY_TRSV0_DRV_LVL 0x088
> +#define PCIE_PHY_TRSV0_RXCDR 0x0ac
> +#define PCIE_PHY_TRSV0_POWER 0x0c4
> +#define PCIE_PHY_TRSV0_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV0_LVCC 0x0dc
> +#define PCIE_PHY_TRSV1_EMP_LVL 0x144
> +#define PCIE_PHY_TRSV1_RXCDR 0x16c
> +#define PCIE_PHY_TRSV1_POWER 0x184
> +#define PCIE_PHY_TRSV1_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV1_LVCC 0x19c
> +#define PCIE_PHY_TRSV2_EMP_LVL 0x204
> +#define PCIE_PHY_TRSV2_RXCDR 0x22c
> +#define PCIE_PHY_TRSV2_POWER 0x244
> +#define PCIE_PHY_TRSV2_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV2_LVCC 0x25c
> +#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4
> +#define PCIE_PHY_TRSV3_RXCDR 0x2ec
> +#define PCIE_PHY_TRSV3_POWER 0x304
> +#define PCIE_PHY_TRSV3_PD_TSV BIT(7)
> +#define PCIE_PHY_TRSV3_LVCC 0x31c
> +
> +struct exynos_pcie_phy_data {
> + struct phy_ops *ops;
> +};
> +
> +/* For Exynos pcie phy */
> +struct exynos_pcie_phy {
> + const struct exynos_pcie_phy_data *drv_data;
> + void __iomem *phy_base;
> + void __iomem *blk_base; /* For exynos5440 */
> +};
> +
> +static void exynos_pcie_phy_writel(void __iomem *base, u32 val, u32 offset)
> +{
> + writel(val, base + offset);
> +}
> +
> +static u32 exynos_pcie_phy_readl(void __iomem *base, u32 offset)
> +{
> + return readl(base + offset);
> +}
> +
> +/* For Exynos5440 specific functions */
> +static int exynos5440_pcie_phy_init(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + /* DCC feedback control off */
> + exynos_pcie_phy_writel(ep->phy_base, 0x29, PCIE_PHY_DCC_FEEDBACK);
> +
> + /* set TX/RX impedance */
> + exynos_pcie_phy_writel(ep->phy_base, 0xd5, PCIE_PHY_IMPEDANCE);
> +
> + /* set 50Mhz PHY clock */
> + exynos_pcie_phy_writel(ep->phy_base, 0x14, PCIE_PHY_PLL_DIV_0);
> + exynos_pcie_phy_writel(ep->phy_base, 0x12, PCIE_PHY_PLL_DIV_1);
> +
> + /* set TX Differential output for lane 0 */
> + exynos_pcie_phy_writel(ep->phy_base, 0x7f, PCIE_PHY_TRSV0_DRV_LVL);
> +
> + /* set TX Pre-emphasis Level Control for lane 0 to minimum */
> + exynos_pcie_phy_writel(ep->phy_base, 0x0, PCIE_PHY_TRSV0_EMP_LVL);
> +
> + /* set RX clock and data recovery bandwidth */
> + exynos_pcie_phy_writel(ep->phy_base, 0xe7, PCIE_PHY_PLL_BIAS);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV0_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV1_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV2_RXCDR);
> + exynos_pcie_phy_writel(ep->phy_base, 0x82, PCIE_PHY_TRSV3_RXCDR);
> +
> + /* change TX Pre-emphasis Level Control for lanes */
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV0_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV1_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV2_EMP_LVL);
> + exynos_pcie_phy_writel(ep->phy_base, 0x39, PCIE_PHY_TRSV3_EMP_LVL);
> +
> + /* set LVCC */
> + exynos_pcie_phy_writel(ep->phy_base, 0x20, PCIE_PHY_TRSV0_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV1_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV2_LVCC);
> + exynos_pcie_phy_writel(ep->phy_base, 0xa0, PCIE_PHY_TRSV3_LVCC);
> +
> + /* pulse for common reset */
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_COMMON_RESET);
> + udelay(500);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_on(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_COMMON_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_CMN_REG);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSVREG_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_TRSV_RESET);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val &= ~PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val &= ~PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val &= ~PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val &= ~PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val &= ~PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_power_off(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> + u32 val;
> +
> + while (exynos_pcie_phy_readl(ep->phy_base,
> + PCIE_PHY_PLL_LOCKED) == 0) {
> + val = exynos_pcie_phy_readl(ep->blk_base,
> + PCIE_PHY_PLL_LOCKED);
> + dev_info(&phy->dev, "PLL Locked: 0x%x\n", val);
> + }
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_COMMON_POWER);
> + val |= PCIE_PHY_COMMON_PD_CMN;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_COMMON_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV0_POWER);
> + val |= PCIE_PHY_TRSV0_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV0_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV1_POWER);
> + val |= PCIE_PHY_TRSV1_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV1_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV2_POWER);
> + val |= PCIE_PHY_TRSV2_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV2_POWER);
> +
> + val = exynos_pcie_phy_readl(ep->phy_base, PCIE_PHY_TRSV3_POWER);
> + val |= PCIE_PHY_TRSV3_PD_TSV;
> + exynos_pcie_phy_writel(ep->phy_base, val, PCIE_PHY_TRSV3_POWER);
> +
> + return 0;
> +}
> +
> +static int exynos5440_pcie_phy_reset(struct phy *phy)
> +{
> + struct exynos_pcie_phy *ep = phy_get_drvdata(phy);
> +
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_MAC_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 1, PCIE_PHY_GLOBAL_RESET);
> + exynos_pcie_phy_writel(ep->blk_base, 0, PCIE_PHY_GLOBAL_RESET);
> +
> + return 0;
> +}
> +
> +static struct phy_ops exynos5440_phy_ops = {
> + .init = exynos5440_pcie_phy_init,
> + .power_on = exynos5440_pcie_phy_power_on,
> + .power_off = exynos5440_pcie_phy_power_off,
> + .reset = exynos5440_pcie_phy_reset,
> +};
> +
> +static const struct exynos_pcie_phy_data exynos5440_pcie_phy_data = {
> + .ops = &exynos5440_phy_ops,
> +};
> +
> +static const struct of_device_id exynos_pcie_phy_match[] = {
> + {
> + .compatible = "samsung,exynos5440-pcie-phy",
> + .data = &exynos5440_pcie_phy_data,
> + },
> + {},
> +};
> +MODULE_DEVICE_TABLE(of, exynos_pcie_phy_match);
> +
> +static int exynos_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct exynos_pcie_phy *exynos_phy;
> + struct phy *generic_phy;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct exynos_pcie_phy_data *drv_data;
> +
> + drv_data = of_device_get_match_data(dev);
> + if (!drv_data)
> + return -ENODEV;
> +
> + exynos_phy = devm_kzalloc(dev, sizeof(*exynos_phy), GFP_KERNEL);
> + if (!exynos_phy)
> + return -ENOMEM;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + exynos_phy->phy_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
> + exynos_phy->blk_base = devm_ioremap_resource(dev, res);
> + if (IS_ERR(exynos_phy->phy_base))
> + return PTR_ERR(exynos_phy->phy_base);
> +
> + exynos_phy->drv_data = drv_data;
> +
> + generic_phy = devm_phy_create(dev, dev->of_node, drv_data->ops);
> + if (IS_ERR(generic_phy)) {
> + dev_err(dev, "failed to create PHY\n");
> + return PTR_ERR(generic_phy);
> + }
> +
> + phy_set_drvdata(generic_phy, exynos_phy);
> + phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
> +
> + return PTR_ERR_OR_ZERO(phy_provider);
> +}
> +
> +static struct platform_driver exynos_pcie_phy_driver = {
> + .probe = exynos_pcie_phy_probe,
> + .driver = {
> + .of_match_table = exynos_pcie_phy_match,
> + .name = "exynos_pcie_phy",
> + }
> +};
> +module_platform_driver(exynos_pcie_phy_driver);
>
^ permalink raw reply
* Re: Re: [PATCH 3/6] clk: sunxi-ng: Add H5 clocks
From: Icenowy Zheng @ 2017-01-09 13:13 UTC (permalink / raw)
To: Maxime Ripard
Cc: Rob Herring, Andre Przywara, linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-clk-u79uwXL29TY76Z2rM5mHXA,
linux-gpio-u79uwXL29TY76Z2rM5mHXA,
devicetree-u79uwXL29TY76Z2rM5mHXA, Linus Walleij,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r, Chen-Yu Tsai,
linux-sunxi-/JYPxA39Uh5TLH3MbocFFw
2017年1月9日 下午7:01于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
>
> On Fri, Jan 06, 2017 at 06:48:31AM +0800, Icenowy Zheng wrote:
> >
> > 2017年1月6日 06:04于 Maxime Ripard <maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org>写道：
> > >
> > > On Tue, Dec 27, 2016 at 12:25:15AM +0800, Icenowy Zheng wrote:
> > > > Add the H5 CCU clocks set based on the H3 one.
> > > >
> > > > Signed-off-by: Icenowy Zheng <icenowy-ymACFijhrKM@public.gmane.org>
> > >
> > > Is there any difference with H3's?
> >
> > One more Transport Stream controller, so one more bus gate and bus
> > reset for it.
>
> There's no need to duplicate more than 1000 lines of code just for
> that then. Just add a new compatible and reuse the clocks already
> defined.
How can I do this? Add them in ccu-sun8i-h3.c ?
>
> Maxime
>
> --
> Maxime Ripard, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
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To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
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^ permalink raw reply
* Re: [PATCH 2/2] media: rc: add driver for IR remote receiver on MT7623 SoC
From: Sean Young @ 2017-01-09 12:39 UTC (permalink / raw)
To: Sean Wang
Cc: mark.rutland, devicetree, ivo.g.dimitrov.75, keyhaede, mchehab,
linux-kernel, andi.shyti, hverkuil, hdegoede, robh+dt,
linux-mediatek, matthias.bgg, linux-media, linux-arm-kernel,
hkallweit1
In-Reply-To: <1483931601.16976.48.camel@mtkswgap22>
On Mon, Jan 09, 2017 at 11:13:21AM +0800, Sean Wang wrote:
> I had another question. I found multiple and same IR messages being
> received when using SONY remote controller. Should driver needs to
> report each message or only one of these to the upper layer ?
In general the driver shouldn't try to change any IR message, this should
be done in rc-core if necessary.
rc-core should handle this correctly. If the same key is received twice
within IR_KEYPRESS_TIMEOUT (250ms) then it not reported to the input
layer.
Thanks
Sean
^ permalink raw reply
* Re: [PATCH v2 3/5] ARM: davinci_all_defconfig: enable iio and ADS7950
From: Sekhar Nori @ 2017-01-09 12:29 UTC (permalink / raw)
To: David Lechner
Cc: Mark Rutland, devicetree, Kevin Hilman, linux-kernel, Rob Herring,
linux-arm-kernel
In-Reply-To: <1483677228-2325-4-git-send-email-david@lechnology.com>
On Friday 06 January 2017 10:03 AM, David Lechner wrote:
> This enables the iio subsystem and the TI ADS7950 driver. This is used by
> LEGO MINDSTORMS EV3, which has an ADS7957 chip.
Can you add your sign-off?
> ---
>
> The CONFIG_TI_ADS7950 driver is currently in iio/testing, so some coordination
> may be needed before picking up this patch.
>
> arch/arm/configs/davinci_all_defconfig | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm/configs/davinci_all_defconfig b/arch/arm/configs/davinci_all_defconfig
> index 2b1967a..a899876 100644
> --- a/arch/arm/configs/davinci_all_defconfig
> +++ b/arch/arm/configs/davinci_all_defconfig
> @@ -200,6 +200,13 @@ CONFIG_TI_EDMA=y
> CONFIG_MEMORY=y
> CONFIG_TI_AEMIF=m
> CONFIG_DA8XX_DDRCTL=y
> +CONFIG_IIO=m
> +CONFIG_IIO_BUFFER_CB=m
> +CONFIG_IIO_SW_DEVICE=m
> +CONFIG_IIO_SW_TRIGGER=m
> +CONFIG_TI_ADS7950=m
Can you separate this from rest of the patch. I would like to enable
this option only after I can find the symbol in linux-next.
> +CONFIG_IIO_HRTIMER_TRIGGER=m
> +CONFIG_IIO_SYSFS_TRIGGER=m
Need CONFIG_IIO_TRIGGER=y also for these two options to take effect.
Thanks,
Sekhar
^ permalink raw reply
* [PATCH] ARM: dts: OMAP5 / DRA7: indicate that SATA port 0 is available.
From: Jean-Jacques Hiblot @ 2017-01-09 12:22 UTC (permalink / raw)
To: bcousson, tony, linux-omap, devicetree
Cc: rogerq, Jean-Jacques Hiblot, stable
AHCI provides the register PORTS_IMPL to let the software know which port
is supported. The register must be initialized by the bootloader. However
in some cases u-boot doesn't properly initialize this value (if it is not
compiled with SATA support for example or if the SATA initialization fails).
The DTS entry "ports-implemented" can be used to override the value in
PORTS_IMPL.
Adding this entry in the dts allows us no to worry about what is done by
the bootloader.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Cc: <stable@vger.kernel.org> # v4.6+
---
arch/arm/boot/dts/dra7.dtsi | 1 +
arch/arm/boot/dts/omap5.dtsi | 1 +
2 files changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 1faf24a..5ba1616 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -1378,6 +1378,7 @@
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
+ ports-implemented = <0x1>;
};
rtc: rtc@48838000 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7cd92ba..0844737 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -988,6 +988,7 @@
phy-names = "sata-phy";
clocks = <&sata_ref_clk>;
ti,hwmods = "sata";
+ ports-implemented = <0x1>;
};
dss: dss@58000000 {
--
1.9.1
^ permalink raw reply related
* Re: [PATCH v2 2/5] ARM: davinci_all_defconfig: Enable PWM modules
From: Sekhar Nori @ 2017-01-09 12:18 UTC (permalink / raw)
To: David Lechner
Cc: Mark Rutland, devicetree, Kevin Hilman, linux-kernel, Rob Herring,
linux-arm-kernel
In-Reply-To: <1483677228-2325-3-git-send-email-david@lechnology.com>
On Friday 06 January 2017 10:03 AM, David Lechner wrote:
> This enables PWM and the TI ECAP and EHRWPM modules. These are used on LEGO
> MINDSTORMS EV3.
Here too. Please resend with sign-off.
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH v2 1/5] ARM: davinci_all_defconfig: enable DA8xx pinconf
From: Sekhar Nori @ 2017-01-09 12:18 UTC (permalink / raw)
To: David Lechner
Cc: Mark Rutland, devicetree, Kevin Hilman, linux-kernel, Rob Herring,
linux-arm-kernel
In-Reply-To: <1483677228-2325-2-git-send-email-david@lechnology.com>
On Friday 06 January 2017 10:03 AM, David Lechner wrote:
> This enables the DA8xx pinconf driver by default. It is needed by LEGO
> MINDSTORMS EV3.
Missing your sign-off. I cannot apply that myself. Please resend.
Thanks,
Sekhar
^ permalink raw reply
* Re: [PATCH v6 3/3] arm: dts: mt2701: Add node for Mediatek JPEG Decoder
From: Hans Verkuil @ 2017-01-09 11:29 UTC (permalink / raw)
To: Rick Chang
Cc: Hans Verkuil, Laurent Pinchart, Mauro Carvalho Chehab,
Matthias Brugger, Rob Herring,
linux-kernel-u79uwXL29TY76Z2rM5mHXA,
linux-media-u79uwXL29TY76Z2rM5mHXA,
srv_heupstream-NuS5LvNUpcJWk0Htik3J/w,
linux-mediatek-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r,
devicetree-u79uwXL29TY76Z2rM5mHXA, Minghsiu Tsai
In-Reply-To: <1483670099.18931.5.camel@mtksdaap41>
Hi Rick,
On 01/06/2017 03:34 AM, Rick Chang wrote:
> Hi Hans,
>
> The dependence on [1] has been merged in 4.10, but [2] has not.Do you have
> any idea about this patch series? Should we wait for [2] or we could merge
> the source code and dt-binding first?
Looking at [2] I noticed that the last comment was July 4th. What is the reason
it hasn't been merged yet?
If I know [2] will be merged for 4.11, then I am fine with merging this media
patch series. The dependency of this patch on [2] is something Mauro can handle.
If [2] is not merged for 4.11, then I think it is better to wait until it is
merged.
Regards,
Hans
>
> Best Regards,
> Rick
>
> On Wed, 2016-11-23 at 17:43 +0800, Rick Chang wrote:
>> On Wed, 2016-11-23 at 09:54 +0800, Rick Chang wrote:
>>> Hi Hans,
>>>
>>> On Tue, 2016-11-22 at 13:43 +0100, Hans Verkuil wrote:
>>>> On 22/11/16 04:21, Rick Chang wrote:
>>>>> Hi Hans,
>>>>>
>>>>> On Mon, 2016-11-21 at 15:51 +0100, Hans Verkuil wrote:
>>>>>> On 17/11/16 04:38, Rick Chang wrote:
>>>>>>> Signed-off-by: Rick Chang <rick.chang-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>>>>>> Signed-off-by: Minghsiu Tsai <minghsiu.tsai-NuS5LvNUpcJWk0Htik3J/w@public.gmane.org>
>>>>>>> ---
>>>>>>> This patch depends on:
>>>>>>> CCF "Add clock support for Mediatek MT2701"[1]
>>>>>>> iommu and smi "Add the dtsi node of iommu and smi for mt2701"[2]
>>>>>>>
>>>>>>> [1] http://lists.infradead.org/pipermail/linux-mediatek/2016-October/007271.html
>>>>>>> [2] https://patchwork.kernel.org/patch/9164013/
>>>>>>
>>>>>> I assume that 1 & 2 will appear in 4.10? So this patch needs to go in
>>>>>> after the
>>>>>> other two are merged in 4.10?
>>>>>>
>>>>>> Regards,
>>>>>>
>>>>>> Hans
>>>>>
>>>>> [1] will appear in 4.10, but [2] will appear latter than 4.10.So this
>>>>> patch needs to go in after [1] & [2] will be merged in 4.11.
>>>>
>>>> So what should I do? Merge the driver for 4.11 and wait with this patch
>>>> until [2] is merged in 4.11? Does that sound reasonable?
>>>>
>>>> Regards,
>>>>
>>>> Hans
>>>
>>> What do you think about this? You merge the driver first and I send this
>>> patch again after [1] & [2] is merged.
>>
>> BTW, to prevent merging conflict, the dtsi should be merged by mediatek
>> SoC maintainer, Matthias.I think we can only take care on the driver
>> part at this moment.
>>
>
>
>
> --
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>
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^ permalink raw reply
* Re: [PATCH v2 9/9] ARM: sunxi: Convert pinctrl nodes to generic bindings
From: Maxime Ripard @ 2017-01-09 11:16 UTC (permalink / raw)
To: André Przywara
Cc: devicetree, Linus Walleij, linux-kernel,
linux-gpio@vger.kernel.org, Chen-Yu Tsai, linux-arm-kernel
In-Reply-To: <dfd7242d-6b16-6091-979f-0bff85a20806@arm.com>
[-- Attachment #1.1: Type: text/plain, Size: 3913 bytes --]
On Fri, Jan 06, 2017 at 01:17:21AM +0000, André Przywara wrote:
> > On Wed, Jan 04, 2017 at 02:16:23AM +0000, André Przywara wrote:
> >> So can I ask that we start taking this seriously and stop doing things
> >> which prevent Allwinner boards from being supported properly?
> >> Which would first involve dropping this very patch?
> >
> > The driver still supports the old binding.
>
> Yes, a _current_ version of the driver supports both bindings, but older
> versions *require* the older binding and bail out if various
> allwinner,xxx properties are missing - as in those proposed new DTs:
>
> 4.9 kernel with sunxi/for-next .dtb:
> sun8i-h3-pinctrl 1c20800.pinctrl: missing allwinner,function property in
> node uart0
> sun8i-h3-pinctrl 1c20800.pinctrl: missing allwinner,function property in
> node mmc0
> sunxi-mmc: probe of 1c0f000.mmc failed with error -22
This is seriously getting out of control. We already come to great
length (and sometimes a painful amount of hacks) to satisfy a few
individuals with a theorical interest in backward compatibility (and
apparently, we're even the only one doing so, even more platforms
choosing to not support that as we speak), there's seriously no reason
to support forward compatibility as well. This has *never* been a
thing, never has been documented nor advertised, I don't know why it
should be one more thing to carry on our shoulders.
Only maybe to slow us even more in the process, and effectively
prevent us from doing any actual work.
> >> Having done breakage in the past (with "allwinner,sun7i-a20-mmc", for
> >> instance) is no excuse for doing it again.
> >
> > I'm not sure which breakage we introduced with a new compatible: the
> > old compatible is working just like it used to, and the new one is
> > working like we need it to.
>
> But the new compatible is not recognized with older kernels, preventing
> people from using the newest DT with older kernels as well.
When do you draw the line exactly? You could have the same argument
for any feature that will be supported in the future... Do you also
want to backport any given driver for any kernel version?
This is ridiculous. 4.9 didn't have MMC support. Who cares about
whether MMC (or any other driver) works? This was never supposed to!
> I proposed to simply work around this by using the old compatible as a
> fallback: compatible="sun7i-a20-mmc", "sun5i-a13-mmc";
> Unfortunately this suggestion was not followed.
> So now we can't boot a 4.8 (or earlier) kernel with a .dtb from a 4.9 or
> later tree. Adding the extra string would fix this.
>
> Actually the recommended approach to avoid this situation in the first
> place is to always use compatible strings with the SoC-specific name as
> the first string, followed by the compatible string the driver works
> with. And this should be done upon introducing a new DT to the tree -
> even if at this point the driver doesn't deal with the new string.
> Unknown strings will just be skipped.
> So for instance the H5 DT should read: "sun50i-h5-mmc",
> "sun50i-a64-mmc", "sun5i-a13-mmc"; (with the last string possibly being
> optional). The current kernel driver will not match the h5 string, so it
> falls back to the a64 string and works. If we learn about a neat eMMC
> 5.1 feature (or any quirk the H5 can benefit from) somewhere in the
> future, we can add the code together with this h5 string to the driver
> and don't need to change the DT at all.
And what about the situation that you encountered last week too? IE
the compatibility was introduced because it was convenient, and it
turns out it's not working as expected?
We remove the bogus compatible from the list? But then, we can't boot
anymore on older kernels...
Maxime
--
Maxime Ripard, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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^ permalink raw reply
* RE: [RFC PATCH] iommu/arm-smmu: Add global SMR masking property
From: Bharat Bhushan @ 2017-01-09 11:14 UTC (permalink / raw)
To: Nipun Gupta, Robin Murphy,
iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org,
devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org,
will.deacon-5wv7dgnIgG8@public.gmane.org, Stuart Yoder
In-Reply-To: <DB6PR0402MB2694957C2D7C648CC342627FE69F0-2mNvjAGDOPn2WJ5A9zev/o3W/0Ik+aLCnBOFsp37pqbUKgpGm//BTAC/G2K4zDHf@public.gmane.org>
Hi Robin,
> -----Original Message-----
> From: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org [mailto:iommu-
> bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org] On Behalf Of Nipun Gupta
> Sent: Sunday, December 18, 2016 2:37 AM
> To: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>; iommu-cunTk1MwBs/ROKNJybVBZg@public.gmane.org
> foundation.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-arm-
> kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org; Stuart Yoder
> <stuart.yoder-3arQi8VN3Tc@public.gmane.org>
> Subject: RE: [RFC PATCH] iommu/arm-smmu: Add global SMR masking
> property
>
>
>
> > -----Original Message-----
> > From: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org [mailto:iommu-
> > bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org] On Behalf Of Robin Murphy
> > Sent: Friday, December 16, 2016 18:49
> > To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org;
> > linux-arm- kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org
> > Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org; Stuart Yoder
> > <stuart.yoder-3arQi8VN3Tc@public.gmane.org>
> > Subject: [RFC PATCH] iommu/arm-smmu: Add global SMR masking
> property
> >
> > The current SMR masking support using a 2-cell iommu-specifier is
> > primarily intended to handle individual masters with large and/or
> > complex Stream ID assignments; it quickly gets a bit clunky in other
> > SMR use-cases where we just want to consistently mask out the same
> > part of every Stream ID (e.g. for MMU-500 configurations where the
> > appended TBU number gets in the way unnecessarily). Let's add a new
> > property to allow a single global mask value to better fit the latter situation.
> >
> > CC: Stuart Yoder <stuart.yoder-3arQi8VN3Tc@public.gmane.org>
>
> Tested-by: Nipun Gupta <nipun.gupta-3arQi8VN3Tc@public.gmane.org>
We have verified this patches with PCI and FSL-MC bus devices.
I do not see any comment on this patch, I know there were holidays around, can we assume this as accepted and we can develop u-boot patches.
Thanks
-Bharat
>
> > Signed-off-by: Robin Murphy <robin.murphy-5wv7dgnIgG8@public.gmane.org>
> > ---
> >
> > Compile-tested only...
> >
> > Documentation/devicetree/bindings/iommu/arm,smmu.txt | 8 ++++++++
> > drivers/iommu/arm-smmu.c | 4 +++-
> > 2 files changed, 11 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> > b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> > index e862d1485205..98f5cbe5fdb4 100644
> > --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt
> > @@ -60,6 +60,14 @@ conditions.
> > aliases of secure registers have to be used during
> > SMMU configuration.
> >
> > +- stream-match-mask : Specifies a fixed SMR mask value to combine with
> > + the Stream ID value from every iommu-specifier. This
> > + may be used instead of an "#iommu-cells" value of 2
> > + when there is no need for per-master SMR masks, but
> > + it is still desired to mask some portion of every
> > + Stream ID (e.g. for certain MMU-500 configurations
> > + given globally unique external IDs).
> > +
> > ** Deprecated properties:
> >
> > - mmu-masters (deprecated in favour of the generic "iommus" binding) :
> > diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
> index
> > 8f7281444551..f1abcb7dde36 100644
> > --- a/drivers/iommu/arm-smmu.c
> > +++ b/drivers/iommu/arm-smmu.c
> > @@ -1534,13 +1534,15 @@ static int arm_smmu_domain_set_attr(struct
> > iommu_domain *domain,
> >
> > static int arm_smmu_of_xlate(struct device *dev, struct
> > of_phandle_args *args) {
> > - u32 fwid = 0;
> > + u32 mask, fwid = 0;
> >
> > if (args->args_count > 0)
> > fwid |= (u16)args->args[0];
> >
> > if (args->args_count > 1)
> > fwid |= (u16)args->args[1] << SMR_MASK_SHIFT;
> > + else if (!of_property_read_u32(args->np, "stream-match-mask",
> > &mask))
> > + fwid |= (u16)mask << SMR_MASK_SHIFT;
> >
> > return iommu_fwspec_add_ids(dev, &fwid, 1); }
> > --
> > 2.10.2.dirty
> >
> > _______________________________________________
> > iommu mailing list
> > iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
> > https://lists.linuxfoundation.org/mailman/listinfo/iommu
> _______________________________________________
> iommu mailing list
> iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org
> https://lists.linuxfoundation.org/mailman/listinfo/iommu
^ permalink raw reply
* Re: [PATCH V6 4/3] brcmfmac: use wiphy_read_of_freq_limits to respect extra limits
From: Johannes Berg @ 2017-01-09 11:07 UTC (permalink / raw)
To: Arend Van Spriel, Rafał Miłecki
Cc: linux-wireless-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Martin Blumenstingl, Felix Fietkau, Arend van Spriel,
Arnd Bergmann, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
Rob Herring, Rafał Miłecki
In-Reply-To: <684d1aff-a9ce-ae42-0c11-5840d3a92daf-dY08KVG/lbpWk0Htik3J/w@public.gmane.org>
On Mon, 2017-01-09 at 12:02 +0100, Arend Van Spriel wrote:
> > However, with the OF, I argued (succesfully it seems :P) that the
> > sensible thing to do was to register with the DISABLED flag and
> > thereby
> > "permanently" disable the channels that OF didn't think were
> > usable,
> > but in this case now the driver has to adhere to the cfg80211 logic
> > of
> > preserving orig_flags forever.
>
> By adhere you mean we should not enable channes for which orig_flags
> indicate DISABLED?
Well, the regulatory code will "OR" in all the orig_flags after
modifications. If you don't use any of the others before registering,
and you don't use any other helpers other than the OF one that we know
sets only DISABLED, then keeping only the DISABLED flag would be OK -
however, it should *also* be OK to always keep *all* of the orig_flags,
just like the normal regulatory code would?
johannes
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^ permalink raw reply
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